From c5ce071e5244e9331a40c81679537e36fae1025f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 11 Mar 2021 15:05:20 +0100 Subject: [PATCH 001/227] PACKAGING: remove gdb exta information to slim library --- tools/profiles/develop.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 21ba5c88d53..5995d276e4e 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", - "-fomit-frame-pointer", "-Os", "-g", "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-fomit-frame-pointer", "-Os", "-DMBED_TRAP_ERRORS_ENABLED=1"], "asm": ["-c", "-x", "assembler-with-cpp"], "c": ["-c", "-std=gnu11"], "cxx": ["-c", "-std=gnu++14", "-fno-rtti", "-Wvla"], From 2c06761fffc1f493dd5dcc327f986572f38ae44f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 28 Oct 2020 15:26:21 +0100 Subject: [PATCH 002/227] Portenta: enable certificates in filesystem --- targets/targets.json | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index ec59258f6e5..ccfcd47116b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3540,6 +3540,8 @@ } }, "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", "CM4_BOOT_BY_APPLICATION", "QSPI_NO_SAMPLE_SHIFT", "CYW43XXX_UNBUFFERED_UART" From f253ffd9e7717ff049cb678364b4ccf36d9d5245 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 1 Apr 2020 12:21:59 +0200 Subject: [PATCH 003/227] I2CSlave.read(buf, count) returns the number of bytes actually read --- drivers/include/drivers/I2CSlave.h | 2 +- drivers/source/I2CSlave.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/include/drivers/I2CSlave.h b/drivers/include/drivers/I2CSlave.h index 663b326870b..96cbddfd931 100644 --- a/drivers/include/drivers/I2CSlave.h +++ b/drivers/include/drivers/I2CSlave.h @@ -172,7 +172,7 @@ class I2CSlave { * * @return Result of the operation. * @retval 0 If the number of bytes read is equal to length requested. - * @retval nonzero On error or if the number of bytes read is less than requested. + * @retval the number of bytes read. */ int read(char *data, int length); diff --git a/drivers/source/I2CSlave.cpp b/drivers/source/I2CSlave.cpp index 4317df9656e..e4515820add 100644 --- a/drivers/source/I2CSlave.cpp +++ b/drivers/source/I2CSlave.cpp @@ -52,7 +52,7 @@ int I2CSlave::receive(void) int I2CSlave::read(char *data, int length) { - return i2c_slave_read(&_i2c, data, length) != length; + return i2c_slave_read(&_i2c, data, length); } int I2CSlave::read(void) From 76c93b67d821c29dc00c5c2e1017cb99fcc14c99 Mon Sep 17 00:00:00 2001 From: Paolo Calao Date: Wed, 13 May 2020 11:59:46 +0200 Subject: [PATCH 004/227] Add AnalogIn configure function This adds a weak method to configure AnalogIn objects. Also, a strong implementation of such method for NRF5284 is provided. --- drivers/include/drivers/AnalogIn.h | 11 ++++-- drivers/source/AnalogIn.cpp | 7 ++++ hal/include/hal/analogin_api.h | 13 +++++++ .../TARGET_NRF5x/TARGET_NRF52/analogin_api.c | 34 +++++++++++++++++++ .../TARGET_NRF5x/TARGET_NRF52/objects.h | 14 ++++++++ 5 files changed, 76 insertions(+), 3 deletions(-) diff --git a/drivers/include/drivers/AnalogIn.h b/drivers/include/drivers/AnalogIn.h index dd5d067a2fd..9cfd6600cad 100644 --- a/drivers/include/drivers/AnalogIn.h +++ b/drivers/include/drivers/AnalogIn.h @@ -88,6 +88,13 @@ class AnalogIn { */ AnalogIn(PinName pin, float vref = MBED_CONF_TARGET_DEFAULT_ADC_VREF); + + /** Reconfigure the adc object using the given configuration + * + * @param config reference to structure which holds AnalogIn configuration + */ + void configure(const analogin_config_t &config); + /** Read the input voltage, represented as a float in the range [0.0, 1.0] * * @returns A floating-point value representing the current input voltage, measured as a percentage @@ -151,9 +158,7 @@ class AnalogIn { virtual ~AnalogIn() { - lock(); - analogin_free(&_adc); - unlock(); + // Do nothing } protected: diff --git a/drivers/source/AnalogIn.cpp b/drivers/source/AnalogIn.cpp index 596d034f194..f9e271d5d9e 100644 --- a/drivers/source/AnalogIn.cpp +++ b/drivers/source/AnalogIn.cpp @@ -38,6 +38,13 @@ AnalogIn::AnalogIn(const PinMap &pinmap, float vref) : _vref(vref) unlock(); } +void AnalogIn::configure(const analogin_config_t &config) +{ + lock(); + analogin_configure(&_adc, &config); + unlock(); +} + float AnalogIn::read() { lock(); diff --git a/hal/include/hal/analogin_api.h b/hal/include/hal/analogin_api.h index d172607c69f..07208443f55 100644 --- a/hal/include/hal/analogin_api.h +++ b/hal/include/hal/analogin_api.h @@ -33,6 +33,10 @@ extern "C" { */ typedef struct analogin_s analogin_t; +/** Analogin configuration hal structure. analogin_config_s is declared in the target's hal + */ +typedef struct analogin_config_s analogin_config_t; + /** * \defgroup hal_analogin Analogin hal functions * @@ -77,6 +81,15 @@ void analogin_init_direct(analogin_t *obj, const PinMap *pinmap); */ void analogin_init(analogin_t *obj, PinName pin); +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + * @param pinmap pointer to structure which holds analogin configuration + */ +void __attribute__((weak)) analogin_configure(analogin_t *obj, const analogin_config_t *config); + /** Release the analogin peripheral * * Releases the pin used by analogin. diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/analogin_api.c index e66be66f505..863c7b090df 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/analogin_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/analogin_api.c @@ -122,6 +122,40 @@ void analogin_init(analogin_t *obj, PinName pin) ANALOGIN_INIT_DIRECT(obj, &static_pinmap); } +/** Reconfigure the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param config pointer to structure which holds analogin configuration + */ +void analogin_configure(analogin_t *obj, const analogin_config_t *config) +{ + MBED_ASSERT(obj); + + /* Get associated channel from the adc object. */ + uint32_t channel = obj->channel; + MBED_ASSERT(channel != (uint32_t) NC); + + /* Account for an off-by-one in Channel definition and Input definition. */ + nrf_saadc_input_t input = channel + 1; + + /* Configure channel and pin */ + nrf_saadc_channel_config_t channel_config = { + .resistor_p = config->resistor_p, + .resistor_n = config->resistor_n, + .gain = config->gain, + .reference = config->reference, + .acq_time = config->acq_time, + .mode = config->mode, + .burst = config->burst, + .pin_p = input, + .pin_n = config->pin_n + }; + + ret_code_t result = nrfx_saadc_channel_init(channel, &channel_config); + MBED_ASSERT(result == NRFX_SUCCESS); +} + /** Read the input voltage, represented as a float in the range [0.0, 1.0] * * @param obj The analogin object diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h index 41b87722acc..4466f680c7c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h @@ -50,6 +50,8 @@ #endif #include "nrf_twi.h" +#include "nrf_saadc.h" + #include "nrf_pwm.h" #ifdef __cplusplus @@ -148,6 +150,18 @@ struct analogin_s { uint8_t channel; }; +struct analogin_config_s { + nrf_saadc_resistor_t resistor_p; + nrf_saadc_resistor_t resistor_n; + nrf_saadc_gain_t gain; + nrf_saadc_reference_t reference; + nrf_saadc_acqtime_t acq_time; + nrf_saadc_mode_t mode; + nrf_saadc_burst_t burst; + nrf_saadc_input_t pin_p; + nrf_saadc_input_t pin_n; +}; + struct gpio_irq_s { uint32_t ch; }; From a6f3b88ed5bd11c0585ce3b6c20efe2a3c659482 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 31 Jul 2019 12:48:04 +0200 Subject: [PATCH 005/227] HACK: avoid #10862 by not firing the assert --- drivers/usb/source/USBDevice.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/usb/source/USBDevice.cpp b/drivers/usb/source/USBDevice.cpp index 6d3cfc87d47..ddeabcfa150 100644 --- a/drivers/usb/source/USBDevice.cpp +++ b/drivers/usb/source/USBDevice.cpp @@ -980,10 +980,11 @@ void USBDevice::out(usb_ep_t endpoint) endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; - MBED_ASSERT(info->pending >= 1); - info->pending -= 1; - if (info->callback) { - info->callback(); + if (info->pending >= 1) { + info->pending -= 1; + if (info->callback) { + info->callback(); + } } } @@ -1007,10 +1008,11 @@ void USBDevice::in(usb_ep_t endpoint) endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; - MBED_ASSERT(info->pending >= 1); - info->pending -= 1; - if (info->callback) { - info->callback(); + if (info->pending >= 1) { + info->pending -= 1; + if (info->callback) { + info->callback(); + } } } From 870bd11b57b6497fec6469c7ed59a627fcc96996 Mon Sep 17 00:00:00 2001 From: Paolo Calao Date: Thu, 29 Oct 2020 15:40:32 +0100 Subject: [PATCH 006/227] portentaH7: Change BLE public address --- .../ble/FEATURE_BLE/COMPONENT_CYW43XXX/HCIDriver.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/HCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/HCIDriver.cpp index 957e37594b3..ff389c9f815 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/HCIDriver.cpp +++ b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/HCIDriver.cpp @@ -378,6 +378,16 @@ class HCIDriver : public CordioHCIDriver { #endif /* BT_UART_NO_3M_SUPPORT */ } + void inject_bdaddr(uint8_t* pBuf) + { + if (service_pack_ptr + service_pack_index == brcm_patchram_buf) { + uint8_t bdAddr[6] = { 0xFF, 0xFF, 0xFF, 0x0A, 0x61, 0xA8 }; + uint32_t uniqueId = HAL_GetUIDw0() ^ HAL_GetUIDw1() ^ HAL_GetUIDw2(); + memcpy(bdAddr, &uniqueId, 3); + memcpy(&pBuf[33], bdAddr, sizeof(bdAddr)); + } + } + void send_service_pack_command(void) { uint16_t cmd_len = service_pack_ptr[service_pack_index + 2]; @@ -385,6 +395,7 @@ class HCIDriver : public CordioHCIDriver { uint8_t *pBuf = hciCmdAlloc(cmd_opcode, cmd_len); if (pBuf) { memcpy(pBuf + HCI_CMD_HDR_LEN, service_pack_ptr + service_pack_index + HCI_CMD_HDR_LEN, cmd_len); + inject_bdaddr(pBuf); hciCmdSend(pBuf); } else { } From c1b9413d1eba88fcb1ae858481d7b0e692c7491d Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 9 Nov 2020 10:00:01 +0100 Subject: [PATCH 007/227] TLSSocketWrapper: add method to retrieve certificates from filesystem --- connectivity/mbedtls/source/x509_crt.c | 4 +++ .../include/netsocket/TLSSocketWrapper.h | 12 ++++++++ .../netsocket/source/TLSSocketWrapper.cpp | 29 +++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/connectivity/mbedtls/source/x509_crt.c b/connectivity/mbedtls/source/x509_crt.c index a623c57a6c1..57d5c788f31 100644 --- a/connectivity/mbedtls/source/x509_crt.c +++ b/connectivity/mbedtls/source/x509_crt.c @@ -74,7 +74,11 @@ #if !defined(_WIN32) || defined(EFIX64) || defined(EFI32) #include #include +#if defined(__MBED__) +#include +#else #include +#endif /* __MBED__ */ #endif /* !_WIN32 || EFIX64 || EFI32 */ #endif diff --git a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h index 1ea28d8f612..143dda3aff8 100644 --- a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h @@ -116,6 +116,18 @@ class TLSSocketWrapper : public Socket { */ nsapi_error_t set_root_ca_cert(const char *root_ca_pem); + /** Sets the certification of Root CA. + * + * @note Must be called before calling connect() + * + * @param root_ca Path containing Root CA Certificate files in any Mbed TLS-supported format. + * @retval NSAPI_ERROR_OK on success. + * @retval NSAPI_ERROR_NO_MEMORY in case there is not enough memory to allocate certificate. + * @retval NSAPI_ERROR_PARAMETER in case the provided root_ca parameter failed parsing. + * + */ + nsapi_error_t set_root_ca_cert_path(const char *root_ca); + /** Sets client certificate, and client private key. * * @param client_cert Client certification in PEM or DER format. diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index cebaf047034..8202151eb7b 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -136,6 +136,35 @@ nsapi_error_t TLSSocketWrapper::set_root_ca_cert(const char *root_ca_pem) return set_root_ca_cert(root_ca_pem, strlen(root_ca_pem) + 1); } +nsapi_error_t TLSSocketWrapper::set_root_ca_cert_path(const char *root_ca) +{ +#if !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_FS_IO) + return NSAPI_ERROR_UNSUPPORTED; +#else + mbedtls_x509_crt *crt; + + crt = new (std::nothrow) mbedtls_x509_crt; + if (!crt) { + return NSAPI_ERROR_NO_MEMORY; + } + + mbedtls_x509_crt_init(crt); + + /* Parse CA certification */ + int ret = mbedtls_x509_crt_parse_path(crt, root_ca); + if (ret < 0) { + print_mbedtls_error("mbedtls_x509_crt_parse", ret); + mbedtls_x509_crt_free(crt); + delete crt; + return NSAPI_ERROR_PARAMETER; + } + set_ca_chain(crt); + _cacert_allocated = true; + return NSAPI_ERROR_OK; +#endif +} + + nsapi_error_t TLSSocketWrapper::set_client_cert_key(const char *client_cert_pem, const char *client_private_key_pem) { return set_client_cert_key(client_cert_pem, strlen(client_cert_pem) + 1, client_private_key_pem, strlen(client_private_key_pem) + 1); From 2ea47a9ca4cc1b6f92eacafe54cdb02df1cad6b5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 9 Nov 2020 13:34:18 +0100 Subject: [PATCH 008/227] TLSSocketWrapper: Add unit test for set_root_ca_cert_path --- .../test/coap-service/unittest/stub/mbedtls_stub.c | 6 ++++++ .../netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp | 6 ++++++ .../UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c b/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c index b63eb0269d2..32026c4fe6e 100644 --- a/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +++ b/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c @@ -303,6 +303,12 @@ int mbedtls_x509_crt_parse(mbedtls_x509_crt *a, const unsigned char *b, size_t c return mbedtls_stub.expected_int; } +int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *a, const char *b) +{ + // means 5 valid certificates found + return 5; +} + int mbedtls_x509_crt_info(char *buf, size_t size, const char *prefix, const mbedtls_x509_crt *crt) { diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp index b0e473a401e..6ba24218175 100644 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp @@ -399,6 +399,12 @@ TEST_F(TestTLSSocketWrapper, set_root_ca_cert_invalid) EXPECT_EQ(wrapper->set_root_ca_cert(cert, strlen(cert)), NSAPI_ERROR_PARAMETER); } +TEST_F(TestTLSSocketWrapper, set_root_ca_cert_path) +{ + EXPECT_EQ(transport->open(&stack), NSAPI_ERROR_OK); + EXPECT_EQ(wrapper->set_root_ca_cert_path("/"), NSAPI_ERROR_OK); +} + TEST_F(TestTLSSocketWrapper, set_client_cert_key) { EXPECT_EQ(wrapper->get_own_cert(), static_cast(NULL)); diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h index 4f9ce6b96c5..ad2d3d8d44c 100644 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h @@ -19,6 +19,6 @@ #define UNITTESTS_FEATURES_NETSOCKET_TLSSOCKET_TLS_TEST_CONFIG_H_ #define MBEDTLS_SSL_CLI_C - +#define MBEDTLS_FS_IO #endif /* UNITTESTS_FEATURES_NETSOCKET_TLSSOCKET_TLS_TEST_CONFIG_H_ */ From 33ec14f8249f1bd509dde015e80ecf291b56077a Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 9 Nov 2020 13:52:28 +0100 Subject: [PATCH 009/227] TLSSocketWrapper: add test for certificates stored in filesystem --- .../tests/TESTS/netsocket/tls/main.cpp | 3 ++ .../tests/TESTS/netsocket/tls/tls_tests.h | 1 + .../tls/tlssocket_cert_in_filesystem.cpp | 50 +++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 connectivity/netsocket/tests/TESTS/netsocket/tls/tlssocket_cert_in_filesystem.cpp diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp index a3dfcb1667a..7e1659d865e 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp @@ -235,6 +235,9 @@ Case cases[] = { // Case("TLSSOCKET_SEND_REPEAT", TLSSOCKET_SEND_REPEAT), // Case("TLSSOCKET_SEND_TIMEOUT", TLSSOCKET_SEND_TIMEOUT), // Case("TLSSOCKET_NO_CERT", TLSSOCKET_NO_CERT), +#if defined(MBEDTLS_SSL_CLI_C) && defined(MBEDTLS_FS_IO) + Case("TLSSOCKET_CERT_IN_FILESYSTEM", TLSSOCKET_CERT_IN_FILESYSTEM), +#endif // Temporarily removing this test, as TLS library consumes too much memory // and we see frequent memory allocation failures on architectures with less // RAM such as DISCO_L475VG_IOT1A and NUCLEO_F207ZG (both have 128 kB RAM) diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tls/tls_tests.h b/connectivity/netsocket/tests/TESTS/netsocket/tls/tls_tests.h index f0905fa8ec3..57461683c8b 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/tls/tls_tests.h +++ b/connectivity/netsocket/tests/TESTS/netsocket/tls/tls_tests.h @@ -89,6 +89,7 @@ void TLSSOCKET_SEND_UNCONNECTED(); void TLSSOCKET_SEND_CLOSED(); void TLSSOCKET_SEND_REPEAT(); void TLSSOCKET_NO_CERT(); +void TLSSOCKET_CERT_IN_FILESYSTEM(); void TLSSOCKET_SIMULTANEOUS(); void TLSSOCKET_SEND_TIMEOUT(); diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tls/tlssocket_cert_in_filesystem.cpp b/connectivity/netsocket/tests/TESTS/netsocket/tls/tlssocket_cert_in_filesystem.cpp new file mode 100644 index 00000000000..cf3dff2e932 --- /dev/null +++ b/connectivity/netsocket/tests/TESTS/netsocket/tls/tlssocket_cert_in_filesystem.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020, Arduino SA, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "TLSSocket.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" +#include "tls_tests.h" +#include "HeapBlockDevice.h" +#include "LittleFileSystem.h" + +using namespace utest::v1; + +void TLSSOCKET_CERT_IN_FILESYSTEM() +{ + SKIP_IF_TCP_UNSUPPORTED(); + + HeapBlockDevice bd(1024 * 10); + LittleFileSystem fs("fs"); + TEST_ASSERT_EQUAL(0, fs.format(&bd)); + TEST_ASSERT_EQUAL(0, fs.mount(&bd)); + + FILE *fp = fopen("/fs/certs.pem", "wb"); + int ret = fwrite(tls_global::cert, strlen(tls_global::cert), 1, fp); + fclose(fp); + + TLSSocket sock; + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(NetworkInterface::get_default_instance())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.set_root_ca_cert_path("/fs")); + + SocketAddress a; + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, NetworkInterface::get_default_instance()->gethostbyname(ECHO_SERVER_ADDR, &a)); + a.set_port(ECHO_SERVER_PORT_TLS); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(a)); +} \ No newline at end of file From e7078e7b5cb20902943b4ef3ae797de4e6e4c571 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 10 Dec 2020 19:39:01 +0100 Subject: [PATCH 010/227] Initial: support Portenta Beta TODO: add 27mhz clock configuration --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index ccfcd47116b..8d418bd6b9f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3567,7 +3567,7 @@ "overrides": { "system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO", "clock_source": "USE_PLL_HSE_EXTC", - "lse_available": 1, + "lse_available": 0, "lpticker_delay_ticks": 0, "network-default-interface-type": "ETHERNET", "i2c_timing_value_algo": true From a6594adeff91a1a1942b69db209abf2b77794357 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 11 Mar 2021 11:50:18 +0100 Subject: [PATCH 011/227] STM32: USB: allow dynamic USB speed configuration based on bootloader parameters --- targets/TARGET_STM/USBPhy_STM32.cpp | 68 +++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index a243961a975..3c86f208832 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -217,10 +217,29 @@ void USB_reenumerate() } #endif +#ifdef USB_DYNAMIC_CONFIGURATION +#undef USBHAL_IRQn + +uint8_t getUSBSpeedFromBootloader() { + // 1 -> USE_USB_OTG_HS + // 2 -> USE_USB_OTG_FS + // 3 -> USE_USB_OTG_HS_IN_FS + uint8_t* bootloader_data = (uint8_t*)(0x801F000); + return bootloader_data[3]; +} +#endif + void USBPhyHw::init(USBPhyEvents *events) { const PinMap *map = NULL; +#if defined(USB_DYNAMIC_CONFIGURATION) + auto USBHAL_IRQn = OTG_FS_IRQn; + if (getUSBSpeedFromBootloader() == 1) { + USBHAL_IRQn = OTG_HS_IRQn; + } +#endif + NVIC_DisableIRQ(USBHAL_IRQn); if (this->events == NULL) { @@ -240,7 +259,12 @@ void USBPhyHw::init(USBPhyEvents *events) hpcd.Init.battery_charging_enable = DISABLE; #endif -#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_HS) +#ifdef USB_DYNAMIC_CONFIGURATION + if (getUSBSpeedFromBootloader() == 1) { +#endif + +#if defined(USB_DYNAMIC_CONFIGURATION) || (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_HS) + hpcd.Instance = USB_OTG_HS; hpcd.Init.phy_itface = PCD_PHY_ULPI; hpcd.Init.Sof_enable = 1; @@ -255,7 +279,12 @@ void USBPhyHw::init(USBPhyEvents *events) __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE(); map = PinMap_USB_HS; -#elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) + #ifdef USB_DYNAMIC_CONFIGURATION + } if (getUSBSpeedFromBootloader() == 3) { + #endif +#endif + +#if defined(USB_DYNAMIC_CONFIGURATION) || (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) hpcd.Instance = USB_OTG_HS; hpcd.Init.phy_itface = USB_OTG_EMBEDDED_PHY; hpcd.Init.Sof_enable = ENABLE; @@ -284,7 +313,12 @@ void USBPhyHw::init(USBPhyEvents *events) map = PinMap_USB_HS; -#elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_FS) + #ifdef USB_DYNAMIC_CONFIGURATION + } if (getUSBSpeedFromBootloader() == 2) { + #endif +#endif + +#if defined(USB_DYNAMIC_CONFIGURATION) || (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_FS) hpcd.Instance = USB_OTG_FS; hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; hpcd.Init.Sof_enable = 1; @@ -301,7 +335,12 @@ void USBPhyHw::init(USBPhyEvents *events) map = PinMap_USB_FS; -#elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG) + #ifdef USB_DYNAMIC_CONFIGURATION + } + #endif +#endif + +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG) hpcd.Instance = USB; hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; hpcd.Init.speed = PCD_SPEED_FULL; @@ -414,6 +453,13 @@ void USBPhyHw::deinit() HAL_StatusTypeDef ret = HAL_PCD_DeInit(&hpcd); MBED_ASSERT(ret == HAL_OK); +#if defined(USB_DYNAMIC_CONFIGURATION) + auto USBHAL_IRQn = OTG_FS_IRQn; + if (getUSBSpeedFromBootloader() == 1) { + USBHAL_IRQn = OTG_HS_IRQn; + } +#endif + NVIC_DisableIRQ(USBHAL_IRQn); if (events != NULL) { @@ -648,6 +694,13 @@ void USBPhyHw::endpoint_abort(usb_ep_t endpoint) void USBPhyHw::process() { +#if defined(USB_DYNAMIC_CONFIGURATION) + auto USBHAL_IRQn = OTG_FS_IRQn; + if (getUSBSpeedFromBootloader() == 1) { + USBHAL_IRQn = OTG_HS_IRQn; + } +#endif + HAL_PCD_IRQHandler(&instance->hpcd); // Re-enable interrupt NVIC_ClearPendingIRQ(USBHAL_IRQn); @@ -656,6 +709,13 @@ void USBPhyHw::process() void USBPhyHw::_usbisr(void) { +#if defined(USB_DYNAMIC_CONFIGURATION) + auto USBHAL_IRQn = OTG_FS_IRQn; + if (getUSBSpeedFromBootloader() == 1) { + USBHAL_IRQn = OTG_HS_IRQn; + } +#endif + NVIC_DisableIRQ(USBHAL_IRQn); instance->events->start_process(); } From c6ba27d3661f7b4684a118fa6cb929b884962128 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 10 Dec 2020 09:43:14 +0100 Subject: [PATCH 012/227] Increase Cordio memory pool for nRF52832 completes 9354bc2a958966739adb0b9584c966bc13e675d5 --- .../TARGET_NORDIC_CORDIO/TARGET_NRF5x/mbed_lib.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/mbed_lib.json b/connectivity/drivers/ble/FEATURE_BLE/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/mbed_lib.json index 05e5a45eee8..3a3d85128d8 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/mbed_lib.json +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/mbed_lib.json @@ -8,7 +8,7 @@ }, "hci-driver-buffer-size": { "help": "Defines the memory to be allocated by the NRFCordiHciDriver.", - "value": 12500 + "value": 13000 }, "wsf-pool-buffer-size": { "help": "Defines the memory allocated for the wsf memory pool.", From ad6f40e1aaa9ed00efaff3679ea76297b86a9f82 Mon Sep 17 00:00:00 2001 From: Paolo Calao Date: Wed, 26 Aug 2020 17:57:42 +0200 Subject: [PATCH 013/227] Cordio Add sendCmplt Callback for updating NumCmplPckts on disconnection --- .../stack/controller/sources/ble/lctr/lctr_main_conn.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/connectivity/FEATURE_BLE/libraries/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_main_conn.c b/connectivity/FEATURE_BLE/libraries/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_main_conn.c index 766c5170ec7..5bc21901441 100644 --- a/connectivity/FEATURE_BLE/libraries/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_main_conn.c +++ b/connectivity/FEATURE_BLE/libraries/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_main_conn.c @@ -514,14 +514,16 @@ void lctrFreeConnCtx(lctrConnCtx_t *pCtx) WsfMsgFree(pBuf); } + uint16_t handle = LCTR_GET_CONN_HANDLE(pCtx); + + lmgrPersistCb.sendCompCback(handle, numTxBufs); + /* Cleanup timers. */ WsfTimerStop(&pCtx->tmrSupTimeout); WsfTimerStop(&pCtx->tmrProcRsp); WsfTimerStop(&pCtx->tmrPingTimeout); WsfTimerStop(&pCtx->tmrAuthTimeout); - uint16_t handle = LCTR_GET_CONN_HANDLE(pCtx); - /* VS cleanup. */ if (pLctrVsHdlrs && pLctrVsHdlrs->connCleanup) { From fe02240e6f395771a11e37705386e3d6dd82cd58 Mon Sep 17 00:00:00 2001 From: Giampaolo Mancini Date: Wed, 8 Jan 2020 16:42:46 +0100 Subject: [PATCH 014/227] Add support for Arduino Edge Control --- .../TARGET_EDGE_CONTROL/PinNames.h | 207 ++++++++++++++++++ .../TARGET_EDGE_CONTROL/device.h | 38 ++++ targets/targets.json | 13 ++ 3 files changed, 258 insertions(+) create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/PinNames.h create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/device.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/PinNames.h new file mode 100644 index 00000000000..afce4108944 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/PinNames.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2019 Arduino SA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "nrf_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y) +#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num) + + +typedef enum { + PinDef(0 , 0), // P0_0 = 0... + PinDef(0 , 1), + PinDef(0 , 2), + PinDef(0 , 3), + PinDef(0 , 4), + PinDef(0 , 5), + PinDef(0 , 6), + PinDef(0 , 7), + PinDef(0 , 8), + PinDef(0 , 9), + PinDef(0 , 10), + PinDef(0 , 11), + PinDef(0 , 12), + PinDef(0 , 13), + PinDef(0 , 14), + PinDef(0 , 15), + PinDef(0 , 16), + PinDef(0 , 17), + PinDef(0 , 18), + PinDef(0 , 19), + PinDef(0 , 20), + PinDef(0 , 21), + PinDef(0 , 22), + PinDef(0 , 23), + PinDef(0 , 24), + PinDef(0 , 25), + PinDef(0 , 26), + PinDef(0 , 27), + PinDef(0 , 28), + PinDef(0 , 29), + PinDef(0 , 30), + PinDef(0 , 31), + + PinDef(1 , 0), //P1_1 = 32... + PinDef(1 , 1), + PinDef(1 , 2), + PinDef(1 , 3), + PinDef(1 , 4), + PinDef(1 , 5), + PinDef(1 , 6), + PinDef(1 , 7), + PinDef(1 , 8), + PinDef(1 , 9), + PinDef(1 , 10), + PinDef(1 , 11), + PinDef(1 , 12), + PinDef(1 , 13), + PinDef(1 , 14), + PinDef(1 , 15), + + // Port0 + p0 = P0_0, + p1 = P0_1, + p2 = P0_2, + p3 = P0_3, + p4 = P0_4, + p5 = P0_5, + p6 = P0_6, + p7 = P0_7, + p8 = P0_8, + p9 = P0_9, + p10 = P0_10, + p11 = P0_11, + p12 = P0_12, + p13 = P0_13, + p14 = P0_14, + p15 = P0_15, + p16 = P0_16, + p17 = P0_17, + p18 = P0_18, + p19 = P0_19, + p20 = P0_20, + p21 = P0_21, + p22 = P0_22, + p23 = P0_23, + p24 = P0_24, + p25 = P0_25, + p26 = P0_26, + p27 = P0_27, + p28 = P0_28, + p29 = P0_29, + p30 = P0_30, + p31 = P0_31, + + // Port1 + p32 = P1_0, + p33 = P1_1, + p34 = P1_2, + p35 = P1_3, + p36 = P1_4, + p37 = P1_5, + p38 = P1_6, + p39 = P1_7, + p40 = P1_8, + p41 = P1_9, + p42 = P1_10, + p43 = P1_11, + p44 = P1_12, + p45 = P1_13, + p46 = P1_14, + p47 = P1_15, + + TX_PIN_NUMBER = P1_11, + RX_PIN_NUMBER = P1_10, + + + // mBed interface Pins + CONSOLE_TX = TX_PIN_NUMBER, + CONSOLE_RX = RX_PIN_NUMBER, + STDIO_UART_TX = TX_PIN_NUMBER, + STDIO_UART_RX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = P0_20, + SPI_PSELMISO0 = P0_21, + SPI_PSELSCK0 = P0_19, + SPI_PSELSS0 = P1_12, + + SPIS_PSELMOSI = P0_20, + SPIS_PSELMISO = P0_21, + SPIS_PSELSCK = P0_19, + SPIS_PSELSS = P1_12, + + I2C_SDA0 = P1_9, + I2C_SCL0 = P0_11, + I2C_SDA1 = P0_31, + I2C_SCL1 = P0_2, + + /**** QSPI pins ****/ + QSPI1_IO0 = P0_20, + QSPI1_IO1 = P0_21, + QSPI1_IO2 = P0_22, + QSPI1_IO3 = P0_23, + QSPI1_SCK = P0_19, + QSPI1_CSN = P0_17, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = QSPI1_IO0, + QSPI_FLASH1_IO1 = QSPI1_IO1, + QSPI_FLASH1_IO2 = QSPI1_IO2, + QSPI_FLASH1_IO3 = QSPI1_IO3, + QSPI_FLASH1_SCK = QSPI1_SCK, + QSPI_FLASH1_CSN = QSPI1_CSN, + + // Not connected + NC = (int)0xFFFFFFFF, + + STDIO_UART_RTS = NC, + STDIO_UART_CTS = NC, + + LED1 = NC, + LED2 = NC, + LED3 = NC, + LED4 = NC, + BUTTON1 = NC, + BUTTON2 = NC, + BUTTON3 = NC, + BUTTON4 = NC, +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/device.h new file mode 100644 index 00000000000..2427e752ea9 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EDGE_CONTROL/device.h @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/targets/targets.json b/targets/targets.json index 8d418bd6b9f..c035a6ed521 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7067,6 +7067,19 @@ "CONFIG_GPIO_AS_PINRESET" ] }, + "EDGE_CONTROL": { + "inherits": ["MCU_NRF52840"], + "features_add": ["STORAGE"], + "device_has_remove": ["ITM"], + "device_has_add": ["WATCHDOG"], + "components_add": [ + "SD", + "SPIF" + ], + "macros_add": [ + "CONFIG_GPIO_AS_PINRESET" + ] + }, "NUMAKER_PFM_NUC472": { "core": "Cortex-M4F", "components_add": [ From 0895da5d527a12b7623fa265f1972c3a56ea77a3 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 10:45:27 +0200 Subject: [PATCH 015/227] RASPBERRYPI: import pico-sdk --- .../TARGET_RP2040/pico-sdk/CMakeLists.txt | 89 + .../TARGET_RP2040/pico-sdk/board_setup.cmake | 31 + .../pico-sdk/boards/generic_board.cmake | 23 + .../pico-sdk/boards/include/boards/none.h | 15 + .../pico-sdk/boards/include/boards/pico.h | 52 + .../pico-sdk/boards/include/boards/vgaboard.h | 104 + .../pico-sdk/common/CMakeLists.txt | 16 + .../TARGET_RP2040/pico-sdk/common/README.md | 3 + .../common/boot_picoboot/CMakeLists.txt | 2 + .../boot_picoboot/include/boot/picoboot.h | 124 + .../pico-sdk/common/boot_uf2/CMakeLists.txt | 2 + .../common/boot_uf2/include/boot/uf2.h | 46 + .../pico-sdk/common/pico_base/CMakeLists.txt | 40 + .../pico-sdk/common/pico_base/include/pico.h | 23 + .../common/pico_base/include/pico/assert.h | 51 + .../common/pico_base/include/pico/config.h | 19 + .../common/pico_base/include/pico/error.h | 21 + .../common/pico_base/include/pico/types.h | 79 + .../pico_base/include/pico/version.h.in | 19 + .../common/pico_binary_info/CMakeLists.txt | 30 + .../include/pico/binary_info.h | 28 + .../include/pico/binary_info/code.h | 139 + .../include/pico/binary_info/defs.h | 43 + .../include/pico/binary_info/structure.h | 150 + .../common/pico_bit_ops/CMakeLists.txt | 5 + .../pico_bit_ops/include/pico/bit_ops.h | 44 + .../common/pico_divider/CMakeLists.txt | 5 + .../pico_divider/include/pico/divider.h | 322 + .../common/pico_stdlib/CMakeLists.txt | 11 + .../common/pico_stdlib/include/pico/stdlib.h | 130 + .../pico-sdk/common/pico_sync/CMakeLists.txt | 44 + .../common/pico_sync/critical_section.c | 24 + .../pico_sync/include/pico/critical_section.h | 75 + .../common/pico_sync/include/pico/lock_core.h | 28 + .../common/pico_sync/include/pico/mutex.h | 135 + .../common/pico_sync/include/pico/sem.h | 101 + .../common/pico_sync/include/pico/sync.h | 19 + .../pico-sdk/common/pico_sync/lock_core.c | 13 + .../pico-sdk/common/pico_sync/mutex.c | 79 + .../pico-sdk/common/pico_sync/sem.c | 82 + .../pico-sdk/common/pico_time/CMakeLists.txt | 16 + .../common/pico_time/include/pico/time.h | 696 + .../pico_time/include/pico/timeout_helper.h | 30 + .../pico-sdk/common/pico_time/time.c | 353 + .../common/pico_time/timeout_helper.c | 30 + .../pico-sdk/common/pico_util/CMakeLists.txt | 15 + .../pico-sdk/common/pico_util/datetime.c | 41 + .../pico-sdk/common/pico_util/doc.h | 4 + .../pico_util/include/pico/util/datetime.h | 27 + .../pico_util/include/pico/util/pheap.h | 155 + .../pico_util/include/pico/util/queue.h | 184 + .../pico-sdk/common/pico_util/pheap.c | 130 + .../pico-sdk/common/pico_util/queue.c | 98 + .../pico-sdk/generated/pico/version.h | 19 + .../TARGET_RP2040/pico-sdk/host.cmake | 10 + .../pico-sdk/host/CMakeLists.txt | 28 + .../TARGET_RP2040/pico-sdk/host/README.md | 14 + .../TARGET_RP2040/pico-sdk/host/boot_stage2.c | 1 + .../host/hardware_divider/CMakeLists.txt | 1 + .../pico-sdk/host/hardware_divider/divider.c | 9 + .../include/hardware/divider.h | 122 + .../host/hardware_gpio/CMakeLists.txt | 1 + .../pico-sdk/host/hardware_gpio/gpio.c | 118 + .../hardware_gpio/include/hardware/gpio.h | 147 + .../host/hardware_sync/CMakeLists.txt | 12 + .../hardware_sync/include/hardware/sync.h | 106 + .../host/hardware_sync/sync_core0_only.c | 140 + .../host/hardware_timer/CMakeLists.txt | 16 + .../hardware_timer/include/hardware/timer.h | 42 + .../pico-sdk/host/hardware_timer/timer.c | 104 + .../host/hardware_uart/CMakeLists.txt | 1 + .../hardware_uart/include/hardware/uart.h | 91 + .../pico-sdk/host/hardware_uart/uart.c | 118 + .../pico-sdk/host/pico_bit_ops/CMakeLists.txt | 9 + .../pico-sdk/host/pico_bit_ops/bit_ops.c | 22 + .../pico-sdk/host/pico_divider/CMakeLists.txt | 9 + .../pico-sdk/host/pico_divider/divider.c | 114 + .../host/pico_multicore/CMakeLists.txt | 8 + .../pico_multicore/include/pico/multicore.h | 44 + .../host/pico_platform/CMakeLists.txt | 25 + .../include/hardware/platform_defs.h | 24 + .../pico_platform/include/pico/platform.h | 137 + .../host/pico_platform/platform_base.c | 46 + .../pico-sdk/host/pico_printf/CMakeLists.txt | 6 + .../pico-sdk/host/pico_stdio/CMakeLists.txt | 20 + .../host/pico_stdio/include/pico/stdio.h | 21 + .../pico-sdk/host/pico_stdio/stdio.c | 23 + .../pico-sdk/host/pico_stdlib/CMakeLists.txt | 19 + .../pico-sdk/host/pico_stdlib/stdlib.c | 27 + .../TARGET_RP2040/pico-sdk/rp2040.cmake | 6 + .../pico-sdk/rp2040/CMakeLists.txt | 6 + .../TARGET_RP2040/pico-sdk/rp2040/README.md | 7 + .../rp2040/hardware_regs/CMakeLists.txt | 3 + .../include/hardware/platform_defs.h | 48 + .../hardware_regs/include/hardware/regs/adc.h | 314 + .../include/hardware/regs/addressmap.h | 72 + .../include/hardware/regs/busctrl.h | 160 + .../include/hardware/regs/clocks.h | 2359 + .../hardware_regs/include/hardware/regs/dma.h | 5313 ++ .../include/hardware/regs/dreq.h | 50 + .../hardware_regs/include/hardware/regs/i2c.h | 2685 + .../include/hardware/regs/intctrl.h | 63 + .../include/hardware/regs/io_bank0.h | 14937 ++++++ .../include/hardware/regs/io_qspi.h | 2931 ++ .../include/hardware/regs/m0plus.h | 1149 + .../include/hardware/regs/pads_bank0.h | 2300 + .../include/hardware/regs/pads_qspi.h | 454 + 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.../hardware_timer/include/hardware/timer.h | 180 + .../rp2_common/hardware_timer/timer.c | 207 + .../rp2_common/hardware_uart/CMakeLists.txt | 1 + .../hardware_uart/include/hardware/uart.h | 433 + .../pico-sdk/rp2_common/hardware_uart/uart.c | 114 + .../rp2_common/hardware_vreg/CMakeLists.txt | 1 + .../hardware_vreg/include/hardware/vreg.h | 55 + .../pico-sdk/rp2_common/hardware_vreg/vreg.c | 12 + .../hardware_watchdog/CMakeLists.txt | 1 + .../include/hardware/watchdog.h | 87 + .../rp2_common/hardware_watchdog/watchdog.c | 99 + .../rp2_common/hardware_xosc/CMakeLists.txt | 1 + .../hardware_xosc/include/hardware/xosc.h | 50 + .../pico-sdk/rp2_common/hardware_xosc/xosc.c | 46 + .../rp2_common/pico_bit_ops/CMakeLists.txt | 57 + .../rp2_common/pico_bit_ops/bit_ops_aeabi.S | 132 + .../rp2_common/pico_bootrom/CMakeLists.txt | 8 + .../rp2_common/pico_bootrom/bootrom.c | 38 + .../pico_bootrom/include/pico/bootrom.h | 85 + .../include/pico/bootrom/sf_table.h | 50 + .../pico_cxx_options/CMakeLists.txt | 23 + .../rp2_common/pico_cxx_options/doc.h | 4 + .../rp2_common/pico_divider/CMakeLists.txt | 52 + .../rp2_common/pico_divider/divider.S | 863 + .../rp2_common/pico_double/CMakeLists.txt | 127 + .../rp2_common/pico_double/double_aeabi.S | 801 + .../rp2_common/pico_double/double_init_rom.c | 66 + .../rp2_common/pico_double/double_math.c | 607 + .../rp2_common/pico_double/double_none.S | 82 + .../pico_double/double_v1_rom_shim.S | 2184 + .../pico_double/include/pico/double.h | 60 + .../rp2_common/pico_fix/CMakeLists.txt | 1 + .../CMakeLists.txt | 9 + .../pico/fix/rp2040_usb_device_enumeration.h | 17 + .../rp2040_usb_device_enumeration.c | 121 + .../rp2_common/pico_float/CMakeLists.txt | 126 + .../rp2_common/pico_float/float_aeabi.S | 724 + .../rp2_common/pico_float/float_init_rom.c | 70 + .../rp2_common/pico_float/float_math.c | 565 + .../rp2_common/pico_float/float_none.S | 80 + .../rp2_common/pico_float/float_v1_rom_shim.S | 347 + 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.../pico-sdk/rp2_common/pico_printf/printf.c | 937 + .../rp2_common/pico_printf/printf_none.S | 23 + .../rp2_common/pico_runtime/CMakeLists.txt | 44 + .../pico_runtime/include/pico/runtime.h | 26 + .../rp2_common/pico_runtime/runtime.c | 248 + .../pico_standard_link/CMakeLists.txt | 93 + .../pico_standard_link/binary_info.c | 85 + .../rp2_common/pico_standard_link/crt0.S | 329 + .../rp2_common/pico_standard_link/doc.h | 10 + .../pico_standard_link/memmap_blocked_ram.ld | 252 + .../pico_standard_link/memmap_copy_to_ram.ld | 253 + .../pico_standard_link/memmap_default.ld | 252 + .../pico_standard_link/memmap_no_flash.ld | 217 + .../pico_standard_link/new_delete.cpp | 26 + .../rp2_common/pico_stdio/CMakeLists.txt | 18 + .../pico-sdk/rp2_common/pico_stdio/LICENSE | 22 + .../pico_stdio/include/pico/stdio.h | 107 + .../pico_stdio/include/pico/stdio/driver.h | 24 + .../pico-sdk/rp2_common/pico_stdio/stdio.c | 287 + .../pico_stdio_semihosting/CMakeLists.txt | 13 + .../include/pico/stdio_semihosting.h | 34 + .../stdio_semihosting.c | 51 + .../rp2_common/pico_stdio_uart/CMakeLists.txt | 13 + .../pico_stdio_uart/include/pico/stdio_uart.h | 62 + .../rp2_common/pico_stdio_uart/stdio_uart.c | 97 + .../rp2_common/pico_stdio_usb/CMakeLists.txt | 20 + .../pico_stdio_usb/include/pico/stdio_usb.h | 52 + .../pico_stdio_usb/include/tusb_config.h | 36 + .../rp2_common/pico_stdio_usb/stdio_usb.c | 115 + .../pico_stdio_usb/stdio_usb_descriptors.c | 121 + .../rp2_common/pico_stdlib/CMakeLists.txt | 45 + .../pico-sdk/rp2_common/pico_stdlib/stdlib.c | 104 + .../rp2_common/pico_unique_id/CMakeLists.txt | 9 + .../pico_unique_id/include/pico/unique_id.h | 64 + .../rp2_common/pico_unique_id/unique_id.c | 28 + .../rp2_common/tinyusb/CMakeLists.txt | 111 + .../pico-sdk/rp2_common/tinyusb/doc.h | 7 + 328 files changed, 119349 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt create mode 100644 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targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c create mode 100644 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100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/doc.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_none.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_v1_rom_shim.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/include/pico/double.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_none.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_v1_rom_shim.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/pico/float.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf_none.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/doc.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_blocked_ram.ld create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_copy_to_ram.ld create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_default.ld create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_no_flash.ld create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/LICENSE create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_uart/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_uart/stdio_uart.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/include/tusb_config.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/doc.h diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt new file mode 100644 index 00000000000..5d7a4c77833 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt @@ -0,0 +1,89 @@ +cmake_policy(SET CMP0079 NEW) # allow inserting of dependencies into our INTERFACE libraries +set(PICO_PLATFORM_CMAKE_FILE "" CACHE INTERNAL "") +set(PICO_DOXYGEN_PATHS "" CACHE INTERNAL "") # generated each time + +if (NOT PICO_PLATFORM_CMAKE_FILE) + set(PICO_PLATFORM_CMAKE_FILE ${CMAKE_CURRENT_LIST_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "") +endif () + +if (NOT EXISTS "${PICO_PLATFORM_CMAKE_FILE}") + message(FATAL_ERROR "${PICO_PLATFORM_CMAKE_FILE} does not exist. \ + Either specify a valid PICO_PLATFORM (or PICO_PLATFORM_CMAKE_FILE).") +endif () + +include(${CMAKE_CURRENT_LIST_DIR}/board_setup.cmake) + +# todo add option to disable skip flag +function(pico_add_subdirectory subdir) + string(TOUPPER ${subdir} subdir_upper) + set(replace_flag SKIP_${subdir_upper}) + if (NOT ${replace_flag}) + add_subdirectory(${subdir}) + else () + message("Not including ${subdir} because ${replace_flag} defined.") + endif () +endfunction() + +function(pico_wrap_function TARGET FUNCNAME) + target_link_options(${TARGET} INTERFACE "LINKER:--wrap=${FUNCNAME}") +endfunction() + +function(pico_add_map_output TARGET) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + target_link_options(${TARGET} PRIVATE "LINKER:-Map=$${CMAKE_EXECUTABLE_SUFFIX}.map") + else () + target_link_options(${TARGET} INTERFACE "LINKER:-Map=$${CMAKE_EXECUTABLE_SUFFIX}.map") + endif () +endfunction() + +macro(pico_simple_hardware_target NAME) + pico_simple_hardware_headers_target(${NAME}) + pico_simple_hardware_impl_target(${NAME}) +endmacro() + +macro(pico_simple_hardware_headers_target NAME) + if (NOT TARGET hardware_${NAME}_headers) + add_library(hardware_${NAME}_headers INTERFACE) + + target_include_directories(hardware_${NAME}_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(hardware_${NAME}_headers INTERFACE pico_base_headers) + if (NOT PICO_NO_HARDWARE) + target_link_libraries(hardware_${NAME}_headers INTERFACE hardware_structs hardware_claim) + endif() + endif() +endmacro() + +macro(pico_simple_hardware_headers_only_target NAME) + if (NOT TARGET hardware_${NAME}) + add_library(hardware_${NAME} INTERFACE) + + target_include_directories(hardware_${NAME} INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(hardware_${NAME} INTERFACE pico_base_headers) + if (NOT PICO_NO_HARDWARE) + target_link_libraries(hardware_${NAME} INTERFACE hardware_structs) + endif() + endif() +endmacro() + +macro(pico_simple_hardware_impl_target NAME) + if (NOT TARGET hardware_${NAME}) + add_library(hardware_${NAME} INTERFACE) + + target_sources(hardware_${NAME} INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/${NAME}.c + ) + + target_link_libraries(hardware_${NAME} INTERFACE hardware_${NAME}_headers pico_platform) + endif() +endmacro() + +function(pico_add_doxygen SOURCE_DIR) + set(PICO_DOXYGEN_PATHS "${PICO_DOXYGEN_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "") +endfunction() + +function(pico_add_doxygen_exclude SOURCE_DIR) + set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "") +endfunction() + +include(${PICO_PLATFORM_CMAKE_FILE}) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake new file mode 100644 index 00000000000..86b80f9e0a6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake @@ -0,0 +1,31 @@ +# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=rp2040, group=build +if (DEFINED ENV{PICO_BOARD}) + set(PICO_BOARD $ENV{PICO_BOARD}) + message("Using PICO_BOARD from environment ('${PICO_BOARD}')") +else() + if (NOT PICO_BOARD) + set(PICO_BOARD "pico") + pico_message("Defaulting PICO target board to ${PICO_BOARD} since not specified.") + else() + message("PICO target board is ${PICO_BOARD}.") + endif() +endif() +set(PICO_BOARD ${PICO_BOARD} CACHE STRING "PICO target board (e.g. pico)") + +# PICO_CMAKE_CONFIG: PICO_BOARD_CMAKE_DIRS, Directories to look for .cmake in. This is overridable from the user environment, type=list, default="", group=build +if (DEFINED ENV{PICO_BOARD_CMAKE_DIRS}) + set(PICO_BOARD_CMAKE_DIRS $ENV{PICO_BOARD_CMAKE_DIRS}) + message("Using PICO_BOARD_CMAKE_DIRS from environment ('${PICO_BOARD_CMAKE_DIRS}')") +endif() + +list(APPEND PICO_BOARD_CMAKE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards) + +pico_find_in_paths(PICO_BOARD_CMAKE_FILE PICO_BOARD_CMAKE_DIRS ${PICO_BOARD}.cmake) +if (EXISTS "${PICO_BOARD_CMAKE_FILE}") + message("Using CMake board configuration from ${PICO_BOARD_CMAKE_FILE}") + include(${PICO_BOARD_CMAKE_FILE} board_config) +else() + include(boards/generic_board.cmake) +endif() + +list(APPEND PICO_INCLUDE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards/include) # so boards/foo.h can be explicitly included diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/generic_board.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/generic_board.cmake new file mode 100644 index 00000000000..54b43d144f9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/generic_board.cmake @@ -0,0 +1,23 @@ +# For boards without their own cmake file, simply include a header + +# PICO_CMAKE_CONFIG: PICO_BOARD_HEADER_DIRS, Directories to look for .h in. This is overridable from the user environment, type=list, default="", group=build +if (DEFINED ENV{PICO_BOARD_HEADER_DIRS}) + set(PICO_BOARD_HEADER_DIRS $ENV{PICO_BOARD_HEADER_DIRS}) + message("Using PICO_BOARD_HEADER_DIRS from environment ('${PICO_BOARD_HEADER_DIRS}')") +endif() +set(PICO_BOARD_HEADER_DIRS ${PICO_BOARD_HEADER_DIRS} CACHE STRING "PICO board header directories") + +list(APPEND PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}/include/boards) +pico_find_in_paths(PICO_BOARD_HEADER_FILE PICO_BOARD_HEADER_DIRS ${PICO_BOARD}.h) + +if (EXISTS ${PICO_BOARD_HEADER_FILE}) + message("Using board configuration from ${PICO_BOARD_HEADER_FILE}") + list(APPEND PICO_CONFIG_HEADER_FILES ${PICO_BOARD_HEADER_FILE}) +else() + set(msg "Unable to find definition of board '${PICO_BOARD}' (specified by PICO_BOARD):\n") + list(JOIN PICO_BOARD_HEADER_DIRS ", " DIRS) + string(CONCAT msg ${msg} " Looked for ${PICO_BOARD}.h in ${DIRS} (additional paths specified by PICO_BOARD_HEADER_DIRS)\n") + list(JOIN PICO_BOARD_CMAKE_DIRS ", " DIRS) + string(CONCAT msg ${msg} " Looked for ${PICO_BOARD}.cmake in ${DIRS} (additional paths specified by PICO_BOARD_CMAKE_DIRS)") + message(FATAL_ERROR ${msg}) +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/none.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/none.h new file mode 100644 index 00000000000..236c395eb3a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/none.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_NONE_H +#define _BOARDS_NONE_H + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h new file mode 100644 index 00000000000..c1ab7819a24 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pico.h" + +#ifndef _BOARDS_PICO_H +#define _BOARDS_PICO_H + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +#ifndef PICO_FLOAT_SUPPORT_ROM_V1 +#define PICO_FLOAT_SUPPORT_ROM_V1 1 +#endif + +#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 +#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h new file mode 100644 index 00000000000..e2c3674c26d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_VGABOARD_H +#define _BOARDS_VGABOARD_H + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 21 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 // same as Pico +#endif + +// Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R. +// - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as +// they are constant duty cycle, and above the filter cutoff +// - When outputting PWM, I2S DIN should be low, so I2S should remain silent. +#define VGABOARD_I2S_DIN_PIN 26 +#define VGABOARD_I2S_BCK_PIN 27 +#define VGABOARD_I2S_LRCK_PIN 28 + +#define VGABOARD_PWM_L_PIN 28 +#define VGABOARD_PWM_R_PIN 27 + +#define VGABOARD_VGA_COLOR_PIN_BASE 0 +#define VGABOARD_VGA_SYNC_PIN_BASE 16 + +// Note DAT2/3 are shared with UART TX/RX (pull jumpers off header to access +// UART pins and disconnect SD DAT2/3) +#define VGABOARD_SD_CLK_PIN 5 +#define VGABOARD_SD_CMD_PIN 18 +#define VGABOARD_SD_DAT0_PIN 19 + +// Note buttons are shared with VGA colour LSBs -- if using VGA, you can float +// the pin on VSYNC assertion and sample on VSYNC deassertion +#define VGABOARD_BUTTON_A_PIN 0 +#define VGABOARD_BUTTON_B_PIN 6 +#define VGABOARD_BUTTON_C_PIN 11 + +#ifndef PICO_SCANVIDEO_COLOR_PIN_BASE +#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE +#endif + +#ifndef PICO_SCANVIDEO_SYMC_PIN_BASE +#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE +#endif + +#ifndef PICO_SD_CLK_PIN +#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN +#endif + +#ifndef PICO_SD_CMD_PIN +#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN +#endif + +#ifndef PICO_SD_DAT0_PIN +#define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN +#endif + +#define PICO_AUDIO_I2S_DATA_PIN VGABOARD_I2S_DIN_PIN +#define PICO_AUDIO_I2S_CLOCK_PIN_BASE VGABOARD_I2S_BCK_PIN + +#define PICO_AUDIO_PWM_L_PIN VGABOARD_PWM_L_PIN +#define PICO_AUDIO_PWM_R_PIN VGABOARD_PWM_R_PIN + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +#ifndef PICO_FLOAT_SUPPORT_ROM_V1 +#define PICO_FLOAT_SUPPORT_ROM_V1 1 +#endif + +#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 +#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#endif + +#define PICO_VGA_BOARD + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt new file mode 100644 index 00000000000..9b256a080cd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt @@ -0,0 +1,16 @@ +pico_add_subdirectory(boot_picoboot) +pico_add_subdirectory(boot_uf2) +pico_add_subdirectory(pico_base) + +# PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build +if (NOT PICO_BARE_METAL) + pico_add_subdirectory(pico_bit_ops) + pico_add_subdirectory(pico_binary_info) + pico_add_subdirectory(pico_divider) + pico_add_subdirectory(pico_sync) + pico_add_subdirectory(pico_time) + pico_add_subdirectory(pico_util) + pico_add_subdirectory(pico_stdlib) +endif() + +pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/README.md b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/README.md new file mode 100644 index 00000000000..0f30a4211e2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/README.md @@ -0,0 +1,3 @@ +This directory code that is common to all builds regardless of `PICO_PLATFORM`. It is a mix +of common header files, or high level functionality built entirely using `hardware_` or `pico_` libraries provided +by the actual target `PICO_PLATFORM`` \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/CMakeLists.txt new file mode 100644 index 00000000000..463fde42d08 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(boot_picoboot_headers INTERFACE) +target_include_directories(boot_picoboot_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/include/boot/picoboot.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/include/boot/picoboot.h new file mode 100644 index 00000000000..ddfa0aaad45 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_picoboot/include/boot/picoboot.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_PICOBOOT_H +#define _BOOT_PICOBOOT_H + +#include +#include +#include + +#ifndef NO_PICO_PLATFORM +#include "pico/platform.h" +#endif + +/** \file picoboot.h +* \defgroup boot_picoboot boot_picoboot +* +* Header file for the PICOBOOT USB interface exposed by an RP2040 in BOOTSEL mode. +*/ + +#define PICOBOOT_MAGIC 0x431fd10bu + +// -------------------------------------------- +// CONTROL REQUESTS FOR THE PICOBOOT INTERFACE +// -------------------------------------------- + +// size 0 OUT - unstall EPs and reset +#define PICOBOOT_IF_RESET 0x41 + +// size 16 IN - return the status of the last command +#define PICOBOOT_IF_CMD_STATUS 0x42 + +// -------------------------------------------------- +// COMMAND REQUESTS SENT TO THE PICOBOOT OUT ENDPOINT +// -------------------------------------------------- +// +// picoboot_cmd structure of size 32 is sent to OUT endpoint +// transfer_length bytes are transferred via IN/OUT +// device responds on success with 0 length ACK packet set via OUT/IN +// device may stall the transferring endpoint in case of error + +enum picoboot_cmd_id { + PC_EXCLUSIVE_ACCESS = 0x1, + PC_REBOOT = 0x2, + PC_FLASH_ERASE = 0x3, + PC_READ = 0x84, // either RAM or FLASH + PC_WRITE = 5, // either RAM or FLASH (does no erase) + PC_EXIT_XIP = 0x6, + PC_ENTER_CMD_XIP = 0x7, + PC_EXEC = 0x8, + PC_VECTORIZE_FLASH = 0x9 +}; + +enum picoboot_status { + PICOBOOT_OK = 0, + PICOBOOT_UNKNOWN_CMD = 1, + PICOBOOT_INVALID_CMD_LENGTH = 2, + PICOBOOT_INVALID_TRANSFER_LENGTH = 3, + PICOBOOT_INVALID_ADDRESS = 4, + PICOBOOT_BAD_ALIGNMENT = 5, + PICOBOOT_INTERLEAVED_WRITE = 6, + PICOBOOT_REBOOTING = 7, + PICOBOOT_UNKNOWN_ERROR = 8, +}; + +struct __packed picoboot_reboot_cmd { + uint32_t dPC; // 0 means reset into bootrom + uint32_t dSP; + uint32_t dDelayMS; +}; + +// used for EXEC, VECTORIZE_FLASH +struct __packed picoboot_address_only_cmd { + uint32_t dAddr; +}; + +// used for READ, WRITE, FLASH_ERASE +struct __packed picoboot_range_cmd { + uint32_t dAddr; + uint32_t dSize; +}; + +enum picoboot_exclusive_type { + NOT_EXCLUSIVE = 0, + EXCLUSIVE, + EXCLUSIVE_AND_EJECT +}; + +struct __packed picoboot_exclusive_cmd { + uint8_t bExclusive; +}; + +// little endian +struct __packed __aligned(4) picoboot_cmd { + uint32_t dMagic; + uint32_t dToken; // an identifier for this token to correlate with a status response + uint8_t bCmdId; // top bit set for IN + uint8_t bCmdSize; // bytes of actual data in the arg part of this structure + uint16_t _unused; + uint32_t dTransferLength; // length of IN/OUT transfer (or 0) if none + union { + uint8_t args[16]; + struct picoboot_reboot_cmd reboot_cmd; + struct picoboot_range_cmd range_cmd; + struct picoboot_address_only_cmd address_only_cmd; + struct picoboot_exclusive_cmd exclusive_cmd; + }; +}; + +static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big"); + +struct __packed __aligned(4) picoboot_cmd_status { + uint32_t dToken; + uint32_t dStatusCode; + uint8_t bCmdId; + uint8_t bInProgress; + uint8_t _pad[6]; +}; + +static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big"); +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/CMakeLists.txt new file mode 100644 index 00000000000..6ca5c2063cf --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(boot_uf2_headers INTERFACE) +target_include_directories(boot_uf2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/include/boot/uf2.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/include/boot/uf2.h new file mode 100644 index 00000000000..a040242bd9a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/boot_uf2/include/boot/uf2.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_UF2_H +#define _BOOT_UF2_H + +#include +#include + +/** \file uf2.h +* \defgroup boot_uf2 boot_uf2 +* +* Header file for the UF2 format supported by an RP2040 in BOOTSEL mode. +*/ + +#define UF2_MAGIC_START0 0x0A324655u +#define UF2_MAGIC_START1 0x9E5D5157u +#define UF2_MAGIC_END 0x0AB16F30u + +#define UF2_FLAG_NOT_MAIN_FLASH 0x00000001u +#define UF2_FLAG_FILE_CONTAINER 0x00001000u +#define UF2_FLAG_FAMILY_ID_PRESENT 0x00002000u +#define UF2_FLAG_MD5_PRESENT 0x00004000u + +#define RP2040_FAMILY_ID 0xe48bff56 + +struct uf2_block { + // 32 byte header + uint32_t magic_start0; + uint32_t magic_start1; + uint32_t flags; + uint32_t target_addr; + uint32_t payload_size; + uint32_t block_no; + uint32_t num_blocks; + uint32_t file_size; // or familyID; + uint8_t data[476]; + uint32_t magic_end; +}; + +static_assert(sizeof(struct uf2_block) == 512, "uf2_block not sector sized"); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt new file mode 100644 index 00000000000..af04c121c7c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt @@ -0,0 +1,40 @@ +if (NOT TARGET pico_base_headers) + # build the auto gen config headers + + set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES\n// DO NOT EDIT!\n") + string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER) + + macro(add_header_content_from_var VAR) + set(header_content "${header_content}\n\n// based on ${VAR}:\n") + foreach(var IN LISTS ${VAR}) + set(header_content "${header_content}\n#include \"${var}\"") + endforeach() + endmacro() + + # PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base + add_header_content_from_var(PICO_CONFIG_HEADER_FILES) + + # PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base + # PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base + add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) + + file(GENERATE + OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h + CONTENT "${header_content}" + ) + + configure_file( include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h) + + add_library(pico_base_headers INTERFACE) + target_include_directories(pico_base_headers INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base) + + foreach(DIR IN LISTS PICO_INCLUDE_DIRS) + target_include_directories(pico_base_headers INTERFACE ${DIR}) + endforeach() + + # PICO_BUILD_DEFINE: PICO_BOARD, Name of board, type=string, default=CMake PICO_BOARD variable, group=pico_base + target_compile_definitions(pico_base_headers INTERFACE + PICO_BOARD="${PICO_BOARD}") + + target_link_libraries(pico_base_headers INTERFACE pico_platform_headers) +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h new file mode 100644 index 00000000000..cdd5c237381 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PICO_H_ +#define PICO_H_ + +/** \file pico.h +* \defgroup pico_base pico_base +* +* Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code +*/ + +#include "pico/types.h" +#include "pico/version.h" +#include "pico/config.h" +#include "pico/platform.h" +#include "pico/assert.h" +#include "pico/error.h" + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h new file mode 100644 index 00000000000..7d2beff9538 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_ASSERT_H +#define _PICO_ASSERT_H + +#include "pico/types.h" + +#ifdef __cplusplus + +#include + +extern "C" { +#else +#include +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLE_ALL, Global assert enable, type=bool, default=0, group=pico_base +// PICO_CONFIG: PARAM_ASSERTIONS_DISABLE_ALL, Global assert disable, type=bool, default=0, group=pico_base + +#ifndef PARAM_ASSERTIONS_ENABLE_ALL +#define PARAM_ASSERTIONS_ENABLE_ALL 0 +#endif + +#ifndef PARAM_ASSERTIONS_DISABLE_ALL +#define PARAM_ASSERTIONS_DISABLE_ALL 0 +#endif + +#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL) + +#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));}) +#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);}) +#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) + +#ifdef NDEBUG +extern void hard_assertion_failure(); +static inline void hard_assert(bool condition, ...) { + if (!condition) + hard_assertion_failure(); +} +#else +#define hard_assert assert +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h new file mode 100644 index 00000000000..a0d5c0b4058 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PICO_CONFIG_H_ +#define PICO_CONFIG_H_ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// OR USE #ifndef __ASSEMBLER__ guards +// ------------- + +// PICO_CONFIG_HEADER_FILES and then PICO_SDK__CONFIG_INCLUDE_FILES +// entries are dumped in order at build time into this generated header + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h new file mode 100644 index 00000000000..722a696f511 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_ERROR_H +#define _PICO_ERROR_H + +/*! + * Common return codes from pico_sdk methods that return a status + */ +enum { + PICO_OK = 0, + PICO_ERROR_NONE = 0, + PICO_ERROR_TIMEOUT = -1, + PICO_ERROR_GENERIC = -2, + PICO_ERROR_NO_DATA = -3, +}; + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h new file mode 100644 index 00000000000..37a4c303c04 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TYPES_H +#define _PICO_TYPES_H + +#include +#include +#include + +typedef unsigned int uint; + +#ifdef NDEBUG +/*! \typedef absolute_time_t + \brief An opaque 64 bit timestamp in microseconds + + The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong + time units where an absolute time is required. It is equivalent to uint64_t in release builds. + + \see to_us_since_boot + \see update_us_since_boot +*/ +typedef uint64_t absolute_time_t; + +/*! fn to_us_since_boot + * \brief convert an absolute_time_t into a number of microseconds since boot. + * \param t the number of microseconds since boot + * \return an absolute_time_t value equivalent to t + */ +static inline uint64_t to_us_since_boot(absolute_time_t t) { + return t; +} + +/*! fn update_us_since_boot + * \brief update an absolute_time_t value to represent a given number of microseconds since boot + * \param t the absolute time value to update + * \param us_since_boot the number of microseconds since boot to represent + */ +static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { + *t = us_since_boot; +} + +#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value +#else +typedef struct { + uint64_t _private_us_since_boot; +} absolute_time_t; + +static inline uint64_t to_us_since_boot(absolute_time_t t) { + return t._private_us_since_boot; +} + +static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { + t->_private_us_since_boot = us_since_boot; +} +#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} +#endif + +/** \struct datetime_t + * \ingroup util_datetime + * \brief Structure containing date and time information + * + * When setting an RTC alarm, set a field to -1 tells + * the RTC to not match on this field + */ +typedef struct { + int16_t year; ///< 0..4095 + int8_t month; ///< 1..12, 1 is January + int8_t day; ///< 1..28,29,30,31 depending on month + int8_t dotw; ///< 0..6, 0 is Sunday + int8_t hour; ///< 0..23 + int8_t min; ///< 0..59 + int8_t sec; ///< 0..59 +} datetime_t; + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/version.h.in b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/version.h.in new file mode 100644 index 00000000000..08fbfb52e53 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/version.h.in @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// --------------------------------------- +// THIS FILE IS AUTOGENERATED; DO NOT EDIT +// --------------------------------------- + +#ifndef _PICO_VERSION_H +#define _PICO_VERSION_H + +#define PICO_SDK_VERSION_MAJOR ${PICO_SDK_VERSION_MAJOR} +#define PICO_SDK_VERSION_MINOR ${PICO_SDK_VERSION_MINOR} +#define PICO_SDK_VERSION_REVISION ${PICO_SDK_VERSION_REVISION} +#define PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_STRING}" + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt new file mode 100644 index 00000000000..2660e9114ac --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt @@ -0,0 +1,30 @@ +add_library(pico_binary_info_headers INTERFACE) + +target_include_directories(pico_binary_info_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +add_library(pico_binary_info INTERFACE) + +target_link_libraries(pico_binary_info INTERFACE pico_binary_info_headers) + +function(pico_set_program_name TARGET name) + # PICO_BUILD_DEFINE: PICO_PROGRAM_NAME, value passed to pico_set_program_name, type=string, default=none, group=pico_binary_info + target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_NAME="${name}") +endfunction() + +function(pico_set_program_description TARGET description) + # since this is the command line, we will remove newlines + string(REPLACE "\n" " " description ${description}) + string(REPLACE "\"" "\\\"" description ${description}) + # PICO_BUILD_DEFINE: PICO_PROGRAM_DESCRIPTION, value passed to pico_set_program_description, type=string, default=none, group=pico_binary_info + target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_DESCRIPTION="${description}") +endfunction() + +function(pico_set_program_url TARGET url) + # PICO_BUILD_DEFINE: PICO_PROGRAM_URL, value passed to pico_set_program_url, type=string, default=none, group=pico_binary_info + target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_URL="${url}") +endfunction() + +function(pico_set_program_version TARGET version) + # PICO_BUILD_DEFINE: PICO_PROGRAM_VERSION_STRING, value passed to pico_set_program_version, type=string, default=none, group=pico_binary_info + target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_VERSION_STRING="${version}") +endfunction() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h new file mode 100644 index 00000000000..2a641abda06 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BINARY_INFO_H +#define _PICO_BINARY_INFO_H + +/** + * Binary info is intended for embedding machine readable information with the binary in FLASH. + * + * Example uses include: + * + * - Program identification / information + * - Pin layouts + * - Included features + * - Identifying flash regions used as block devices/storage + */ + +#include "pico/binary_info/defs.h" +#include "pico/binary_info/structure.h" +#if PICO_ON_DEVICE +#include "pico/binary_info/code.h" +#endif + + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h new file mode 100644 index 00000000000..af3ce554e6b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BINARY_INFO_CODE_H +#define _PICO_BINARY_INFO_CODE_H + +#include "pico.h" +#include "pico/binary_info/structure.h" + +#if !PICO_NO_BINARY_INFO +#define __bi_decl(name, bi, section_prefix, attr) static const attr __attribute__((section(section_prefix __STRING(name)))) struct _binary_info_core *name = bi +#define __bi_lineno_var_name __CONCAT(__bi_, __LINE__) +#define __bi_ptr_lineno_var_name __CONCAT(__bi_ptr, __LINE__) +#define __bi_enclosure_check_lineno_var_name __CONCAT(_error_bi_is_missing_enclosing_decl_,__LINE__) +#define __bi_mark_enclosure static const __unused int __bi_enclosure_check_lineno_var_name=0; +#if !defined(__GNUC__) || __cplusplus || __GNUC__ >= 8 +#define __bi_enclosure_check(x) (x + __bi_enclosure_check_lineno_var_name) +#else +// skip the version check on older GCC non C++, as it doesn't compile.. this is only here to catch the +// user accidentally forgetting to enclose the binary item with bi_decl +#define __bi_enclosure_check(x) (x) +#endif +/** + * Declare some binary information that will be included if the contain source file/line is compiled into the binary + */ +#define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); +/** + * Declare some binary information that will be included if the function containing the decl is linked into the binary. + * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated + * binary information declared this way will also be stripped + */ +#define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;}); + +#define bi_decl_with_attr(_decl, _attr) __bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); +#define bi_decl_if_func_used_with_attr(_decl, _attr) ({__bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;}); +#else +#define __bi_decl(bi, name, attr) +#define bi_decl_with_attr(_decl, _attr) +#define bi_decl(_decl) +#define bi_decl_if_func_used_with_attr(_decl, _attr) ((void)0); +#define bi_decl_if_func_used(_decl) ((void)0); +#endif + +#define bi_int(_tag, _id, _value) \ + static const struct _binary_info_id_and_int __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_INT), \ + .tag = _tag, \ + },\ + .id = _id, \ + .value = _value \ + }; + +#define bi_string(_tag, _id, _value) \ + static const struct _binary_info_id_and_string __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_STRING), \ + .tag = _tag, \ + },\ + .id = _id, \ + .value = _value, \ + } + +#define bi_block_device(_tag, _name, _address, _size, _extra, _flags) \ + static const struct _binary_info_block_device __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_BLOCK_DEVICE), \ + .tag = _tag, \ + },\ + .name = _name, \ + .address = _address, \ + .size = _size, \ + .extra = _extra, \ + .flags = _flags, \ + } + +#define __bi_encoded_pins_with_func(_encoding) \ + static const struct _binary_info_pins_with_func __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_FUNC), \ + .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ + },\ + .pin_encoding = _encoding \ + } + +#define __bi_pins_with_name(_mask, _label) \ + static const struct _binary_info_pins_with_name __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_NAME), \ + .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ + },\ + .pin_mask = _mask, \ + .label = _label \ + } + +#define __bi_named_group(_parent_tag, _parent_id, _group_tag, _group_id, _label, _flags) \ +static const struct _binary_info_named_group __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_NAMED_GROUP), \ + .tag = _parent_tag, \ + },\ + .parent_id = _parent_id, \ + .group_tag = _group_tag, \ + .flags = _flags, \ + .group_id = _group_id, \ + .label = _label \ + } + +#define bi_binary_end(end) bi_int(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BINARY_END, end) +#define bi_program_name(name) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_NAME, name) +#define bi_program_description(description) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION, description) +#define bi_program_version_string(version_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING, version_string) +#define bi_program_build_date_string(date_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING, date_string) +#define bi_program_url(url) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_URL, url) +// multiple of these may be added +#define bi_program_feature(feature) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, feature) +#define bi_program_build_attribute(attr) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE, attr) +#define bi_program_feature_group(tag, id, name) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, 0) +#define bi_program_feature_group_with_flags(tag, id, name, flags) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, flags) + +#define bi_1pin_with_func(p0, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p0) << 12)) +#define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p1) << 17)) +#define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p2) << 22)) +#define bi_4pins_with_func(p0, p1, p2, p3, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p3) << 27)) +#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p4) << 27)) +#define bi_pin_range_with_func(plo, phi, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 7) | ((phi) << 12)) + +#define bi_pin_mask_with_name(pmask, label) __bi_pins_with_name((pmask), (label)) +// names are sperated by | ... i.e. "name1|name2|name3" +#define bi_pin_mask_with_names(pmask, label) __bi_pins_with_name((pmask), (label)) +#define bi_1pin_with_name(p0, name) bi_pin_mask_with_name(1u << (p0), name) +#define bi_2pins_with_names(p0, name0, p1, name1) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)), name0 "|" name1) +#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2) +#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3) + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h new file mode 100644 index 00000000000..407c0ac4885 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/defs.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BINARY_INFO_DEFS_H +#define _PICO_BINARY_INFO_DEFS_H + +// this file is for pre-processor definitions only + +// should be found within the first 256 bytes of the real binary (i.e. after the flash second stage if a flash binary) +// +// Note the layout is: +// +// addr : BINARY_INFO_MARKER_START +// addr+0x04 : __binary_info_start +// addr+0x08 : __binary_info_end +// addr+0x0c : __address_mapping_table +// addr+0x10 | BINARY_INFO_MARKER_END +// +// __binary_info_start to __binary_info_end are the start, end (non inclusive) of an array +// of pointers to binary_info_t structures +// +// __address_mapping_table is an array of the following items: +// +// uint32_t source_addr_start +// uint32_t dest_addr_start +// uint32_t dest_addr_end +// +// representing a mapping from the stored address in the binary/flash to addresses at runtime. +// The linker will store pointers within the binary using their runtime values, however because of +// "AT" mapping in the link script these addresses actually correspond to a different address in the binary +// image. This mapping (which in the case of crt0.S is simply the data copy table used at initialization +// to copy data into it's runtime location) can be used by picotool or others to reverse the mapping to find data +// within the binary. +// +// Note the above array is terminated with a NULL source_addr_start + +#define BINARY_INFO_MARKER_START 0x7188ebf2 +#define BINARY_INFO_MARKER_END 0xe71aa390 + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h new file mode 100644 index 00000000000..2e261b252b6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BINARY_INFO_STRUCTURE_H +#define _PICO_BINARY_INFO_STRUCTURE_H + +// NOTE: This file may be included by non SDK code, so does not use SDK includes + +// NOTE: ALL CHANGES MUST BE BACKWARDS COMPATIBLE + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef __packed +#define __packed __attribute__((packed)) +#endif + +typedef struct _binary_info_core binary_info_t; + +#define BINARY_INFO_TYPE_RAW_DATA 1 +#define BINARY_INFO_TYPE_SIZED_DATA 2 +#define BINARY_INFO_TYPE_BINARY_INFO_LIST_ZERO_TERMINATED 3 +#define BINARY_INFO_TYPE_BSON 4 +#define BINARY_INFO_TYPE_ID_AND_INT 5 +#define BINARY_INFO_TYPE_ID_AND_STRING 6 +// traditional block device +#define BINARY_INFO_TYPE_BLOCK_DEVICE 7 +#define BINARY_INFO_TYPE_PINS_WITH_FUNC 8 +#define BINARY_INFO_TYPE_PINS_WITH_NAME 9 +#define BINARY_INFO_TYPE_PINS_WITH_NAMES 9 +#define BINARY_INFO_TYPE_NAMED_GROUP 10 + +// note plan is to reserve c1 = 0->31 for "collision tags"; i.e. +// for which you should always use random IDs with the binary_info, +// giving you 4 + 8 + 32 = 44 bits to avoid collisions +#define BINARY_INFO_MAKE_TAG(c1, c2) ((((uint)c2&0xffu)<<8u)|((uint)c1&0xffu)) + +// Raspberry Pi defined. do not use +#define BINARY_INFO_TAG_RASPBERRY_PI BINARY_INFO_MAKE_TAG('R','P') + +#define BINARY_INFO_ID_RP_PROGRAM_NAME 0x02031c86 +#define BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING 0x11a9bc3a +#define BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING 0x9da22254 +#define BINARY_INFO_ID_RP_BINARY_END 0x68f465de +#define BINARY_INFO_ID_RP_PROGRAM_URL 0x1856239a +#define BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION 0xb6a07c19 +#define BINARY_INFO_ID_RP_PROGRAM_FEATURE 0xa1f4b453 +#define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3 +#define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab +#define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb + +#if PICO_ON_DEVICE +#define bi_ptr_of(x) x * +#else +#define bi_ptr_of(x) uint32_t +#endif +typedef struct __packed _binary_info_core { + uint16_t type; + uint16_t tag; +} binary_info_core_t; + +typedef struct __packed _binary_info_raw_data { + struct _binary_info_core core; + uint8_t bytes[1]; +} binary_info_raw_data_t; + +typedef struct __packed _binary_info_sized_data { + struct _binary_info_core core; + uint32_t length; + uint8_t bytes[1]; +} binary_info_sized_data_t; + +typedef struct __packed _binary_info_list_zero_terminated { + struct _binary_info_core core; + bi_ptr_of(binary_info_t) list; +} binary_info_list_zero_terminated_t; + +typedef struct __packed _binary_info_id_and_int { + struct _binary_info_core core; + uint32_t id; + int32_t value; +} binary_info_id_and_int_t; + +typedef struct __packed _binary_info_id_and_string { + struct _binary_info_core core; + uint32_t id; + bi_ptr_of(const char) value; +} binary_info_id_and_string_t; + +typedef struct __packed _binary_info_block_device { + struct _binary_info_core core; + bi_ptr_of(const char) name; // optional static name (independent of what is formatted) + uint32_t address; + uint32_t size; + bi_ptr_of(binary_info_t) extra; // additional info + uint16_t flags; +} binary_info_block_device_t; + +#define BI_PINS_ENCODING_RANGE 1 +#define BI_PINS_ENCODING_MULTI 2 + +typedef struct __packed _binary_info_pins_with_func { + struct _binary_info_core core; + // p4_5 : p3_5 : p2_5 : p1_5 : p0_5 : func_4 : 001_3 //individual pins p0,p1,p2,p3,p4 ... if fewer than 5 then duplicate p + // phi_5 : plo_5 : func_4 : 010_3 // pin range plo-phi inclusive + uint32_t pin_encoding; +} binary_info_pins_with_func_t; + +typedef struct __packed _binary_info_pins_with_name { + struct _binary_info_core core; + uint32_t pin_mask; + bi_ptr_of(const char) label; +} binary_info_pins_with_name_t; + +#define BI_NAMED_GROUP_SHOW_IF_EMPTY 0x0001 // default is to hide +#define BI_NAMED_GROUP_SEPARATE_COMMAS 0x0002 // default is newlines +#define BI_NAMED_GROUP_SORT_ALPHA 0x0004 // default is no sort +#define BI_NAMED_GROUP_ADVANCED 0x0008 // if set, then only shown in say info -a + +typedef struct __packed _binary_info_named_group { + struct _binary_info_core core; + uint32_t parent_id; + uint16_t flags; + uint16_t group_tag; + uint32_t group_id; + bi_ptr_of(const char) label; +} binary_info_named_group_t; + +enum { + BINARY_INFO_BLOCK_DEV_FLAG_READ = + 1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it + BINARY_INFO_BLOCK_DEV_FLAG_WRITE = 1 << 1, + BINARY_INFO_BLOCK_DEV_FLAG_REFORMAT = 1 << 2, // may be reformatted.. + + BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN = 0 << 4, // unknown free to look + BINARY_INFO_BLOCK_DEV_FLAG_PT_MBR = 1 << 4, // expect MBR + BINARY_INFO_BLOCK_DEV_FLAG_PT_GPT = 2 << 4, // expect GPT + BINARY_INFO_BLOCK_DEV_FLAG_PT_NONE = 3 << 4, // no partition table +}; + +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/CMakeLists.txt new file mode 100644 index 00000000000..603a520609c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/CMakeLists.txt @@ -0,0 +1,5 @@ +if (NOT TARGET pico_bit_ops_headers) + add_library(pico_bit_ops_headers INTERFACE) + target_include_directories(pico_bit_ops_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(pico_bit_ops_headers INTERFACE pico_base_headers) +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/include/pico/bit_ops.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/include/pico/bit_ops.h new file mode 100644 index 00000000000..7b63c1dcd7b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_bit_ops/include/pico/bit_ops.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BIT_OPS_H +#define _PICO_BIT_OPS_H + +#include "pico.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file bit_ops.h +* \defgroup pico_bit_ops pico_bit_ops +* +* Optimized bit manipulation functions. +* Additionally provides replacement implementations of the compiler built-ins __builtin_popcount, __builtin_clz +* and __bulitin_ctz +*/ + +/*! \brief Reverse the bits in a 32 bit word + * \ingroup pico_bit_ops + * + * \param bits 32 bit input + * \return the 32 input bits reversed + */ +uint32_t __rev(uint32_t bits); + +/*! \brief Reverse the bits in a 64 bit double word + * \ingroup pico_bit_ops + * + * \param bits 64 bit input + * \return the 64 input bits reversed + */ +uint64_t __revll(uint64_t bits); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/CMakeLists.txt new file mode 100644 index 00000000000..aed07d29275 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/CMakeLists.txt @@ -0,0 +1,5 @@ +if (NOT TARGET pico_divider_headers) + add_library(pico_divider_headers INTERFACE) + target_include_directories(pico_divider_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(pico_divider_headers INTERFACE pico_base_headers) +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/include/pico/divider.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/include/pico/divider.h new file mode 100644 index 00000000000..749f734be91 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_divider/include/pico/divider.h @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_DIVIDER_H_ +#define _PICO_DIVIDER_H_ + +#include "pico.h" +#include "hardware/divider.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup pico_divider pico_divider + * Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider. + * Additionally provides integration with the C `/` and `%` operators + */ + +/** \file pico/divider.h +* \brief High level APIs including combined quotient and remainder functions for 32 and 64 bit accelerated by the hardware divider +* \ingroup pico_divider +* +* These functions all call __aeabi_idiv0 or __aebi_ldiv0 on division by zero +* passing the largest applicably signed value +* +* Functions with unsafe in their name do not save/restore divider state, so are unsafe to call from interrupts. Unsafe functions are slightly faster. +*/ + +/** + * \brief Integer divide of two signed 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient + */ +int32_t div_s32s32(int32_t a, int32_t b); + +/** + * \brief Integer divide of two signed 32-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + */ +static inline int32_t divmod_s32s32_rem(int32_t a, int32_t b, int32_t *rem) { + divmod_result_t r = hw_divider_divmod_s32(a, b); + *rem = to_remainder_s32(r); + return to_quotient_s32(r); +} + +/** + * \brief Integer divide of two signed 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in low word/r0, remainder in high word/r1 + */ +divmod_result_t divmod_s32s32(int32_t a, int32_t b); + +/** + * \brief Integer divide of two unsigned 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + */ +uint32_t div_u32u32(uint32_t a, uint32_t b); + +/** + * \brief Integer divide of two unsigned 32-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + */ +static inline uint32_t divmod_u32u32_rem(uint32_t a, uint32_t b, uint32_t *rem) { + divmod_result_t r = hw_divider_divmod_u32(a, b); + *rem = to_remainder_u32(r); + return to_quotient_u32(r); +} + +/** + * \brief Integer divide of two unsigned 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in low word/r0, remainder in high word/r1 + */ +divmod_result_t divmod_u32u32(uint32_t a, uint32_t b); + +/** + * \brief Integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + */ +int64_t div_s64s64(int64_t a, int64_t b); + +/** + * \brief Integer divide of two signed 64-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + */ +int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem); + +/** + * \brief Integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in result (r0,r1), remainder in regs (r2, r3) + */ +int64_t divmod_s64s64(int64_t a, int64_t b); + +/** + * \brief Integer divide of two unsigned 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + */ +uint64_t div_u64u64(uint64_t a, uint64_t b); + +/** + * \brief Integer divide of two unsigned 64-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + */ +uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem); + + +/** + * \brief Integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in result (r0,r1), remainder in regs (r2, r3) + */ +uint64_t divmod_u64u64(uint64_t a, uint64_t b); + +// ----------------------------------------------------------------------- +// these "unsafe" functions are slightly faster, but do not save the divider state, +// so are not generally safe to be called from interrupts +// ----------------------------------------------------------------------- + +/** + * \brief Unsafe integer divide of two signed 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient + * + * Do not use in interrupts + */ +int32_t div_s32s32_unsafe(int32_t a, int32_t b); + +/** + * \brief Unsafe integer divide of two signed 32-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + * + * Do not use in interrupts + */ +int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem); + +/** + * \brief Unsafe integer divide of two unsigned 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in low word/r0, remainder in high word/r1 + * + * Do not use in interrupts + */ +int64_t divmod_s32s32_unsafe(int32_t a, int32_t b); + +/** + * \brief Unsafe integer divide of two unsigned 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + * + * Do not use in interrupts + */ +uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b); + +/** + * \brief Unsafe integer divide of two unsigned 32-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + * + * Do not use in interrupts + */ +uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem); + +/** + * \brief Unsafe integer divide of two unsigned 32-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in low word/r0, remainder in high word/r1 + * + * Do not use in interrupts + */ +uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b); + +/** + * \brief Unsafe integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + * + * Do not use in interrupts + */ +int64_t div_s64s64_unsafe(int64_t a, int64_t b); + +/** + * \brief Unsafe integer divide of two signed 64-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + * + * Do not use in interrupts + */ +int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem); + +/** + * \brief Unsafe integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in result (r0,r1), remainder in regs (r2, r3) + * + * Do not use in interrupts + */ +int64_t divmod_s64s64_unsafe(int64_t a, int64_t b); + +/** + * \brief Unsafe integer divide of two unsigned 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return Quotient + * + * Do not use in interrupts + */ +uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b); + +/** + * \brief Unsafe integer divide of two unsigned 64-bit values, with remainder + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \param [out] rem The remainder of dividend/divisor + * \return Quotient result of dividend/divisor + * + * Do not use in interrupts + */ +uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem); + +/** + * \brief Unsafe integer divide of two signed 64-bit values + * \ingroup pico_divider + * + * \param a Dividend + * \param b Divisor + * \return quotient in result (r0,r1), remainder in regs (r2, r3) + * + * Do not use in interrupts + */ +uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/CMakeLists.txt new file mode 100644 index 00000000000..454ea578a82 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/CMakeLists.txt @@ -0,0 +1,11 @@ +if (NOT TARGET pico_stdlib_headers) + add_library(pico_stdlib_headers INTERFACE) + target_include_directories(pico_stdlib_headers INTERFACE include) + target_link_libraries(pico_stdlib_headers INTERFACE + hardware_gpio + hardware_uart + hardware_divider + pico_time + pico_util + ) +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h new file mode 100644 index 00000000000..04e62750d3d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_STDLIB_H +#define _PICO_STDLIB_H + +#include "pico.h" +#include "pico/stdio.h" +#include "pico/time.h" +#include "hardware/gpio.h" +#include "hardware/uart.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file stdlib.h + * \defgroup pico_stdlib pico_stdlib + * + * Aggregation of a core subset of Raspberry Pi Pico SDK libraries used by most executables along with some additional + * utility methods. Including pico_stdlib gives you everything you need to get a basic program running + * which prints to stdout or flashes a LED + * + * This library aggregates: + * - @ref hardware_uart + * - @ref hardware_gpio + * - @ref pico_binary_info + * - @ref pico_runtime + * - @ref pico_platform + * - @ref pico_printf + * - @ref pico_stdio + * - @ref pico_standard_link + * - @ref pico_util + * + * There are some basic default values used by these functions that will default to + * usable values, however, they can be customised in a board definition header via + * config.h or similar + */ + +// Note PICO_STDIO_UART, PICO_STDIO_USB, PICO_STDIO_SEMIHOSTING are set by the +// respective INTERFACE libraries, so these defines are set if the library +// is included for the target executable + +#if PICO_STDIO_UART +#include "pico/stdio_uart.h" +#endif + +#if PICO_STDIO_USB +#include "pico/stdio_usb.h" +#endif + +#if PICO_STDIO_SEMIHOSTING +#include "pico/stdio_semihosting.h" +#endif + +/*! \brief Set up the default UART and assign it to the default GPIO's + * \ingroup pico_stdlib + * + * By default this will use UART 0, with TX to pin GPIO 0, + * RX to pin GPIO 1, and the baudrate to 115200 + * + * Calling this method also initializes stdin/stdout over UART if the + * @ref pico_stdio_uart library is linked. + * + * Defaults can be changed using configuration defines, + * PICO_DEFAULT_UART_INSTANCE, + * PICO_DEFAULT_UART_BAUD_RATE + * PICO_DEFAULT_UART_TX_PIN + * PICO_DEFAULT_UART_RX_PIN + */ +void setup_default_uart(); + +/*! \brief Initialise the system clock to 48MHz + * \ingroup pico_stdlib + * + * Set the system clock to 48MHz, and set the peripheral clock to match. + */ +void set_sys_clock_48mhz(); + +/*! \brief Initialise the system clock + * \ingroup pico_stdlib + * + * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL + * \param post_div1 The first post divider for the SYS PLL + * \param post_div2 The second post divider for the SYS PLL. + * + * See the PLL documentation in the datasheet for details of driving the PLLs. + */ +void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2); + +/*! \brief Check if a given system clock frequency is valid/attainable + * \ingroup pico_stdlib + * + * \param freq_khz Requested frequency + * \param vco_freq_out On success, the voltage controller oscillator frequeucny to be used by the SYS PLL + * \param post_div1_out On success, The first post divider for the SYS PLL + * \param post_div2_out On success, The second post divider for the SYS PLL. + * @return true if the frequency is possible and the output parameters have been written. + */ +bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); + +/*! \brief Attempt to set a system clock frequency in khz + * \ingroup pico_stdlib + * + * Note that not all clock frequencies are possible; it is preferred that you + * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters + * for use with set_sys_clock_pll + * + * \param freq_khz Requested frequency + * \param required if true then this function will assert if the frequency is not attainable. + * \return true if the clock was configured + */ +static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) { + uint vco, postdiv1, postdiv2; + if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) { + set_sys_clock_pll(vco, postdiv1, postdiv2); + return true; + } else if (required) { + panic("System clock of %u kHz cannot be exactly achieved", freq_khz); + } + return false; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt new file mode 100644 index 00000000000..8d1d0f832f1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt @@ -0,0 +1,44 @@ +if (NOT TARGET pico_sync_headers) + add_library(pico_sync_headers INTERFACE) + target_include_directories(pico_sync_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(pico_sync_headers INTERFACE hardware_sync pico_time) +endif() + +if (NOT TARGET pico_sync_core) + add_library(pico_sync_core INTERFACE) + target_sources(pico_sync_core INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/lock_core.c + ) + target_link_libraries(pico_sync_core INTERFACE pico_sync_headers) +endif() + +if (NOT TARGET pico_sync_sem) + add_library(pico_sync_sem INTERFACE) + target_sources(pico_sync_sem INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/sem.c + ) + target_link_libraries(pico_sync_sem INTERFACE pico_sync_core pico_time) +endif() + +if (NOT TARGET pico_sync_mutex) + add_library(pico_sync_mutex INTERFACE) + target_sources(pico_sync_mutex INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/mutex.c + ) + target_link_libraries(pico_sync_mutex INTERFACE pico_sync_core pico_time) +endif() + +if (NOT TARGET pico_sync_critical_section) + add_library(pico_sync_critical_section INTERFACE) + target_sources(pico_sync_critical_section INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/critical_section.c + ) + target_link_libraries(pico_sync_critical_section INTERFACE pico_sync_core pico_time) +endif() + +if (NOT TARGET pico_sync) + add_library(pico_sync INTERFACE) + target_link_libraries(pico_sync INTERFACE pico_sync_sem pico_sync_mutex pico_sync_critical_section pico_sync_core) +endif() + + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c new file mode 100644 index 00000000000..5f47090d7c6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/critical_section.h" + +#if !PICO_NO_HARDWARE +static_assert(sizeof(critical_section_t) == 8, ""); +#endif + +void critical_section_init(critical_section_t *critsec) { + critical_section_init_with_lock_num(critsec, spin_lock_claim_unused(true)); +} + +void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num) { + lock_init(&critsec->core, lock_num); + __mem_fence_release(); +} + +void critical_section_deinit(critical_section_t *critsec) { + spin_lock_unclaim(spin_lock_get_num(critsec->core.spin_lock)); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h new file mode 100644 index 00000000000..17a8b3f4754 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PLATFORM_CRITICAL_SECTION_H +#define _PLATFORM_CRITICAL_SECTION_H + +#include "pico/lock_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file critical_section.h + * \defgroup critical_section critical_section + * \ingroup pico_sync + * \brief Critical Section API for short-lived mutual exclusion safe for IRQ and multi-core + * + * A critical section is non-reentrant, and provides mutual exclusion using a spin-lock to prevent access + * from the other core, and from (higher priority) interrupts on the same core. It does the former + * using a spin lock and the latter by disabling interrupts on the calling core. + * + * Because interrupts are disabled by this function, uses of the critical_section should be as short as possible. + */ + +typedef struct __packed_aligned critical_section { + lock_core_t core; + uint32_t save; +} critical_section_t; + +/*! \brief Initialise a critical_section structure allowing the system to assign a spin lock number + * \ingroup critical_section + * + * The critical section is initialized ready for use, and will use a (possibly shared) spin lock + * number assigned by the system. Note that in general it is unlikely that you would be nesting + * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num + * to ensure that the spin lock's used are different. + * + * \param critsec Pointer to critical_section structure + */ +void critical_section_init(critical_section_t *critsec); + +/*! \brief Initialise a critical_section structure assigning a specific spin lock number + * \ingroup critical_section + * \param critsec Pointer to critical_section structure + * \param lock_num the specific spin lock number to use + */ +void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num); + +/*! \brief Enter a critical_section + * \ingroup critical_section + * + * If the spin lock associated with this critical section is in use, then this + * method will block until it is released. + * + * \param critsec Pointer to critical_section structure + */ +static inline void critical_section_enter_blocking(critical_section_t *critsec) { + critsec->save = spin_lock_blocking(critsec->core.spin_lock); +} + +/*! \brief Release a critical_section + * \ingroup critical_section + * + * \param critsec Pointer to critical_section structure + */ +static inline void critical_section_exit(critical_section_t *critsec) { + spin_unlock(critsec->core.spin_lock, critsec->save); +} +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h new file mode 100644 index 00000000000..758eb94fb51 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LOCK_CORE_H +#define _PICO_LOCK_CORE_H + +#include "pico.h" +#include "hardware/sync.h" + +/** \file lock_core.h + * \ingroup pico_sync + * + * Base implementation for locking primitives protected by a spin lock + */ +typedef struct lock_core { + // spin lock protecting this lock's state + spin_lock_t *spin_lock; + + // note any lock members in containing structures need not be volatile; + // they are protected by memory/compiler barriers when gaining and release spin locks +} lock_core_t; + +void lock_init(lock_core_t *core, uint lock_num); + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h new file mode 100644 index 00000000000..4b5d1759c1e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PLATFORM_MUTEX_H +#define _PLATFORM_MUTEX_H + +#include "pico/lock_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file mutex.h + * \defgroup mutex mutex + * \ingroup pico_sync + * \brief Mutex API for non IRQ mutual exclusion between cores + * + * Mutexes are application level locks usually used protecting data structures that might be used by + * multiple cores. Unlike critical sections, the mutex protected code is not necessarily + * required/expected to complete quickly, as no other sytemwide locks are held on account of a locked mutex. + * + * Because they are not re-entrant on the same core, blocking on a mutex should never be done in an IRQ + * handler. It is valid to call \ref mutex_try_enter from within an IRQ handler, if the operation + * that would be conducted under lock can be skipped if the mutex is locked (at least by the same core). + * + * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers + */ + +typedef struct __packed_aligned mutex { + lock_core_t core; + int8_t owner; //! core number or -1 for unowned +} mutex_t; + +/*! \brief Initialise a mutex structure + * \ingroup mutex + * + * \param mtx Pointer to mutex structure + */ +void mutex_init(mutex_t *mtx); + +/*! \brief Take ownership of a mutex + * \ingroup mutex + * + * This function will block until the calling core can claim ownership of the mutex. + * On return the caller core owns the mutex + * + * \param mtx Pointer to mutex structure + */ +void mutex_enter_blocking(mutex_t *mtx); + +/*! \brief Check to see if a mutex is available + * \ingroup mutex + * + * Will return true if the mutex is unowned, false otherwise + * + * \param mtx Pointer to mutex structure + * \param owner_out If mutex is owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex + */ +bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out); + +/*! \brief Wait for mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the mutex. If the calling + * core can take ownership of the mutex before the timeout expires, then true will be returned + * and the calling core will own the mutex, otherwise false will be returned and the calling + * core will *NOT* own the mutex. + * + * \param mtx Pointer to mutex structure + * \param timeout_ms The timeout in milliseconds. + * \return true if mutex now owned, false if timeout occurred before mutex became available + */ +bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms); + +/*! \brief Wait for mutex until a specific time + * \ingroup mutex + * + * Wait until the specific time to take ownership of the mutex. If the calling + * core can take ownership of the mutex before the timeout expires, then true will be returned + * and the calling core will own the mutex, otherwise false will be returned and the calling + * core will *NOT* own the mutex. + * + * \param mtx Pointer to mutex structure + * \param until The time after which to return if the core cannot take owner ship of the mutex + * \return true if mutex now owned, false if timeout occurred before mutex became available + */ +bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); + +/*! \brief Release ownership of a mutex + * \ingroup mutex + * + * \param mtx Pointer to mutex structure + */ +void mutex_exit(mutex_t *mtx); + +/*! \brief Test for mutex initialised state + * \ingroup mutex + * + * \param mtx Pointer to mutex structure + * \return true if the mutex is initialised, false otherwise + */ +static inline bool mutex_is_initialzed(mutex_t *mtx) { + return mtx->core.spin_lock != 0; +} + +/*! \brief Helper macro for static definition of mutexes + * \ingroup mutex + * + * A mutex defined as follows: + * + * ```c + * auto_init_mutex(my_mutex); + * ``` + * + * Is equivalent to doing + * + * ```c + * static mutex_t my_mutex; + * + * void my_init_function() { + * mutex_init(&my_mutex); + * } + * ``` + * + * But the initialization of the mutex is performed automatically during runtime initialization + */ +#define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h new file mode 100644 index 00000000000..19ac2925a36 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PLATFORM_SEM_H +#define _PLATFORM_SEM_H + +#include "pico/lock_core.h" + +/** \file sem.h + * \defgroup sem sem + * \ingroup pico_sync + * \brief Semaphore API for restricting access to a resource + * + * A semaphore holds a number of available permits. `sem_acquire` methods will acquire a permit if available + * (reducing the available count by 1) or block if the number of available permits is 0. + * \ref sem_release() increases the number of available permits by one potentially unblocking a `sem_acquire` method. + * + * Note that \ref sem_release() may be called an arbitrary number of times, however the number of available + * permits is capped to the max_permit value specified during semaphore initialization. + * + * Although these semaphore related functions can be used from IRQ handlers, it is obviously preferable to only + * release semaphores from within an IRQ handler (i.e. avoid blocking) + */ + +#ifdef __cplusplus +extern "C" { +#endif +typedef struct __packed_aligned semaphore { + struct lock_core core; + int16_t permits; + int16_t max_permits; +} semaphore_t; + + +/*! \brief Initialise a semaphore structure + * \ingroup sem + * + * \param sem Pointer to semaphore structure + * \param initial_permits How many permits are initially acquired + * \param max_permits Total number of permits allowed for this semaphore + */ +void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits); + +/*! \brief Return number of available permits on the semaphore + * \ingroup sem + * + * \param sem Pointer to semaphore structure + * \return The number of permits available on the semaphore. + */ +int sem_available(semaphore_t *sem); + +/*! \brief Release a permit on a semaphore + * \ingroup sem + * + * Increases the number of permits by one (unless the number of permits is already at the maximum). + * A blocked `sem_acquire` will be released if the number of permits is increased. + * + * \param sem Pointer to semaphore structure + * \return true if the number of permits available was increased. + */ +bool sem_release(semaphore_t *sem); + +/*! \brief Reset semaphore to a specific number of available permits + * \ingroup sem + * + * Reset value should be from 0 to the max_permits specified in the init function + * + * \param sem Pointer to semaphore structure + * \param permits the new number of available permits + */ +void sem_reset(semaphore_t *sem, int16_t permits); + +/*! \brief Acquire a permit from the semaphore + * \ingroup sem + * + * This function will block and wait if no permits are available. + * + * \param sem Pointer to semaphore structure + */ +void sem_acquire_blocking(semaphore_t *sem); + +/*! \brief Acquire a permit from a semaphore, with timeout + * \ingroup sem + * + * This function will block and wait if no permits are available, until the + * defined timeout has been reached. If the timeout is reached the function will + * return false, otherwise it will return true. + * + * \param sem Pointer to semaphore structure + * \param timeout_ms Time to wait to acquire the semaphore, in ms. + * \return false if timeout reached, true if permit was acquired. + */ +bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sync.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sync.h new file mode 100644 index 00000000000..041bfd7ffc7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sync.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_SYNC_H +#define _PICO_SYNC_H + +/** \file pico/sync.h + * \defgroup pico_sync pico_sync + * Synchronization primitives and mutual exclusion + */ + +#include "pico/sem.h" +#include "pico/mutex.h" +#include "pico/critical_section.h" + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c new file mode 100644 index 00000000000..cf53a05c635 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/lock_core.h" + +void lock_init(lock_core_t *core, uint lock_num) { + assert(lock_num >= 0 && lock_num < NUM_SPIN_LOCKS); + core->spin_lock = spin_lock_instance(lock_num); +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c new file mode 100644 index 00000000000..531666fbea8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/mutex.h" +#include "pico/time.h" + +#if !PICO_NO_HARDWARE +static_assert(sizeof(mutex_t) == 8, ""); +#endif + +void mutex_init(mutex_t *mtx) { + lock_init(&mtx->core, next_striped_spin_lock_num()); + mtx->owner = -1; + __mem_fence_release(); +} + +void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) { + assert(mtx->core.spin_lock); + bool block = true; + do { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (mtx->owner < 0) { + mtx->owner = get_core_num(); + block = false; + } + spin_unlock(mtx->core.spin_lock, save); + if (block) { + __wfe(); + } + } while (block); +} + +bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) { + bool entered; + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (mtx->owner < 0) { + mtx->owner = get_core_num(); + entered = true; + } else { + if (owner_out) *owner_out = mtx->owner; + entered = false; + } + spin_unlock(mtx->core.spin_lock, save); + return entered; +} + +bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout_ms) { + return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms)); +} + +bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) { + assert(mtx->core.spin_lock); + bool block = true; + do { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (mtx->owner < 0) { + mtx->owner = get_core_num(); + block = false; + } + spin_unlock(mtx->core.spin_lock, save); + if (block) { + if (best_effort_wfe_or_timeout(until)) { + return false; + } + } + } while (block); + return true; +} + +void __time_critical_func(mutex_exit)(mutex_t *mtx) { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + assert(mtx->owner >= 0); + mtx->owner = -1; + __sev(); + spin_unlock(mtx->core.spin_lock, save); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c new file mode 100644 index 00000000000..4ed7285450b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/sem.h" +#include "pico/time.h" + +void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits) { + lock_init(&sem->core, next_striped_spin_lock_num()); + sem->permits = initial_permits; + sem->max_permits = max_permits; + __mem_fence_release(); +} + +int __time_critical_func(sem_available)(semaphore_t *sem) { + return *(volatile typeof(sem->permits) *) &sem->permits; +} + +void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) { + bool block = true; + do { + uint32_t save = spin_lock_blocking(sem->core.spin_lock); + if (sem->permits > 0) { + sem->permits--; + __sev(); + block = false; + } + spin_unlock(sem->core.spin_lock, save); + if (block) { + __wfe(); + } + } while (block); +} + +bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) { + bool block = true; + absolute_time_t target = nil_time; + do { + uint32_t save = spin_lock_blocking(sem->core.spin_lock); + if (sem->permits > 0) { + sem->permits--; + __sev(); + block = false; + } + spin_unlock(sem->core.spin_lock, save); + if (block) { + if (is_nil_time(target)) { + target = make_timeout_time_ms(timeout_ms); + } + if (best_effort_wfe_or_timeout(target)) { + return false; + } + } + } while (block); + return true; +} + +// todo this should really have a blocking variant for when permits are maxed out +bool __time_critical_func(sem_release)(semaphore_t *sem) { + bool rc; + uint32_t save = spin_lock_blocking(sem->core.spin_lock); + int32_t count = sem->permits; + if (count < sem->max_permits) { + sem->permits = count + 1; + __sev(); + rc = true; + } else { + rc = false; + } + spin_unlock(sem->core.spin_lock, save); + return rc; +} + +void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) { + assert(permits >= 0 && permits <= sem->max_permits); + uint32_t save = spin_lock_blocking(sem->core.spin_lock); + if (permits > sem->permits) __sev(); + sem->permits = permits; + spin_unlock(sem->core.spin_lock, save); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt new file mode 100644 index 00000000000..fe388558513 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt @@ -0,0 +1,16 @@ +if (NOT TARGET pico_time_headers) + add_library(pico_time_headers INTERFACE) + + target_include_directories(pico_time_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_link_libraries(pico_time_headers INTERFACE hardware_timer) +endif() + +if (NOT TARGET pico_time) + add_library(pico_time INTERFACE) + + target_sources(pico_time INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/time.c + ${CMAKE_CURRENT_LIST_DIR}/timeout_helper.c) + target_link_libraries(pico_time INTERFACE pico_time_headers pico_sync pico_util) +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h new file mode 100644 index 00000000000..ae0a84f7c5d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h @@ -0,0 +1,696 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TIME_H +#define _PICO_TIME_H + +#include "pico.h" +#include "hardware/timer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file time.h + * \defgroup pico_time pico_time + * + * API for accurate timestamps, sleeping, and time based callbacks + * + * \note The functions defined here provide a much more powerful and user friendly wrapping around the + * low level hardware timer functionality. For these functions (and any other SDK functionality + * e.g. timeouts, that relies on them) to work correctly, the hardware timer should not be modified. i.e. it is expected + * to be monotonically increasing once per microsecond. Fortunately there is no need to modify the hardware + * timer as any functionality you can think of that isn't already covered here can easily be modelled + * by adding or subtracting a constant value from the unmodified hardware timer. + * + * \sa \ref hardware_timer + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIME, Enable/disable assertions in the time module, type=bool, default=0, group=pico_time +#ifndef PARAM_ASSERTIONS_ENABLED_TIME +#define PARAM_ASSERTIONS_ENABLED_TIME 0 +#endif + +// PICO_CONFIG: PICO_TIME_SLEEP_OVERHEAD_ADJUST_US, How many microseconds to wake up early (and then busy_wait) to account for timer overhead when sleeping in low power mode, type=int, default=6, group=pico_time +#ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US +#define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 6 +#endif +/*! + * \defgroup timestamp timestamp + * \ingroup pico_time + * \brief Timestamp functions relating to points in time (including the current time) + * + * These are functions for dealing with timestamps (i.e. instants in time) represented by the type absolute_time_t. This opaque + * type is provided to help prevent accidental mixing of timestamps and relative time values. + */ + +/*! \brief Return a representation of the current time. + * \ingroup timestamp + * + * Returns an opaque high fidelity representation of the current time sampled during the call. + * + * \return the absolute time (now) of the hardware timer + * + * \sa absolute_time_t + * \sa sleep_until() + * \sa time_us_64() + */ +static inline absolute_time_t get_absolute_time() { + absolute_time_t t; + update_us_since_boot(&t, time_us_64()); + return t; +} + +static inline uint32_t us_to_ms(uint64_t us) { + if (us >> 32u) { + return (uint32_t)(us / 1000u); + } else { + return ((uint32_t)us) / 1000u; + } +} + +/*! fn to_ms_since_boot + * \ingroup timestamp + * \brief Convert a timestamp into a number of milliseconds since boot. + * \param t an absolute_time_t value to convert + * \return the number of microseconds since boot represented by t + * \sa to_us_since_boot + */ +static inline uint32_t to_ms_since_boot(absolute_time_t t) { + uint64_t us = to_us_since_boot(t); + return us_to_ms(us); +} + +/*! \brief Return a timestamp value obtained by adding a number of microseconds to another timestamp + * \ingroup timestamp + * + * \param t the base timestamp + * \param us the number of microseconds to add + * \return the timestamp representing the resulting time + */ +static inline absolute_time_t delayed_by_us(const absolute_time_t t, uint64_t us) { + absolute_time_t t2; + uint64_t base = to_us_since_boot(t); + uint64_t delayed = base + us; + if (delayed < base) { + delayed = (uint64_t)-1; + } + update_us_since_boot(&t2, delayed); + return t2; +} + +/*! \brief Return a timestamp value obtained by adding a number of milliseconds to another timestamp + * \ingroup timestamp + * + * \param t the base timestamp + * \param ms the number of milliseconds to add + * \return the timestamp representing the resulting time + */ +static inline absolute_time_t delayed_by_ms(const absolute_time_t t, uint32_t ms) { + absolute_time_t t2; + uint64_t base = to_us_since_boot(t); + uint64_t delayed = base + ms * 1000ull; + if (delayed < base) { + delayed = (uint64_t)-1; + } + update_us_since_boot(&t2, delayed); + return t2; +} + +/*! \brief Convenience method to get the timestamp a number of microseconds from the current time + * \ingroup timestamp + * + * \param us the number of microseconds to add to the current timestamp + * \return the future timestamp + */ +static inline absolute_time_t make_timeout_time_us(uint64_t us) { + return delayed_by_us(get_absolute_time(), us); +} + +/*! \brief Convenience method to get the timestamp a number of milliseconds from the current time + * \ingroup timestamp + * + * \param ms the number of milliseconds to add to the current timestamp + * \return the future timestamp + */ +static inline absolute_time_t make_timeout_time_ms(uint32_t ms) { + return delayed_by_ms(get_absolute_time(), ms); +} + +/*! \brief Return the difference in microseconds between two timestamps + * \ingroup timestamp + * + * \note be careful when diffing against large timestamps (e.g. \ref at_the_end_of_time) + * as the signed integer may overflow. + * + * \param from the first timestamp + * \param to the second timestamp + * \return the number of microseconds between the two timestamps (positive if `to` is after `from` except + * in case of overflow) + */ +static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) { + return to_us_since_boot(to) - to_us_since_boot(from); +} + +/*! \brief The timestamp representing the end of time; no timestamp is after this + * \ingroup timestamp + */ +extern const absolute_time_t at_the_end_of_time; + +/*! \brief The timestamp representing a null timestamp + * \ingroup timestamp + */ +extern const absolute_time_t nil_time; + +/*! \brief Determine if the given timestamp is nil + * \ingroup timestamp + * \param t the timestamp + * \return true if the timestamp is nil + * \sa nil_time() + */ +static inline bool is_nil_time(absolute_time_t t) { + return !to_us_since_boot(t); +} + +/*! + * \defgroup sleep sleep + * \ingroup pico_time + * \brief Sleep functions for delaying execution in a lower power state. + * + * These functions allow the calling core to sleep. This is a lower powered sleep; waking and re-checking time on every processor + * event (WFE) + * + * \note These functions should not be called from an IRQ handler. + * + * \note Lower powered sleep requires use of the \link alarm_pool_get_default default alarm pool\endlink which may + * be disabled by the #PICO_TIME_DEFAULT_ALARM_POOL_DISABLED define or currently full in which case these functions + * become busy waits instead. + * + * \note Whilst \a sleep_ functions are preferable to \a busy_wait functions from a power perspective, the \a busy_wait equivalent function + * may return slightly sooner after the target is reached. + * + * \sa busy_wait_until() \sa busy_wait_us() \sa busy_wait_us_32() + */ + +/*! \brief Wait until after the given timestamp to return + * \ingroup sleep + * + * \note This method attempts to perform a lower power (WFE) sleep + * + * \param target the time after which to return + * \sa sleep_us() + * \sa busy_wait_until() + * */ +void sleep_until(absolute_time_t target); + +/*! \brief Wait for the given number of microseconds before returning + * \ingroup sleep + * + * \note This method attempts to perform a lower power (WFE) sleep + * + * \param us the number of microseconds to sleep + * \sa busy_wait_us() + */ +void sleep_us(uint64_t us); + +/*! \brief Wait for the given number of milliseconds before returning + * \ingroup sleep + * + * \note This method attempts to perform a lower power sleep (using WFE) as much as possible. + * + * \param ms the number of milliseconds to sleep + */ +void sleep_ms(uint32_t ms); + +/*! \brief Helper method for blocking on a timeout + * \ingroup sleep + * + * This method will return in response to a an event (as per __wfe) or + * when the target time is reached, or at any point before. + * + * This method can be used to implement a lower power polling loop waiting on + * some condition signalled by an event (__sev()). + * + * This is called \a best_effort because under certain circumstances (notably the default timer pool + * being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling + * code into a busy wait. + * + * Example usage: + * ```c + * bool my_function_with_timeout_us(uint64_t timeout_us) { + * absolute_time_t timeout_time = make_timeout_time_us(timeout_us); + * do { + * // each time round the loop, we check to see if the condition + * // we are waiting on has happened + * if (my_check_done()) { + * // do something + * return true; + * } + * // will try to sleep until timeout or the next processor event + * } while (!best_effort_wfe_or_timeout(timeout_time)); + * return false; // timed out + * } + * ``` + * + * @param timeout_timestamp the timeout time + * @return true if the target time is reached, false otherwise + */ +bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); + +/*! + * \defgroup alarm alarm + * \ingroup pico_time + * \brief Alarm functions for scheduling future execution + * + * Alarms are added to alarm pools, which may hold a certain fixed number of active alarms. Each alarm pool + * utilizes one of four underlying hardware alarms, thus you may have up to four alarm pools. An alarm pool + * calls (except when the callback would happen before or during being set) the callback on the core from which + * the alarm pool was created. Callbacks are called from the hardware alarm IRQ handler, so care must + * be taken in their implementation. + * + * A default pool is created the core specified by PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM + * on core 0, and may be used by the method variants that take no alarm pool parameter. + * + * \sa struct alarm_pool + * \sa hardware_timer + */ + +// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_DISABLED, Disable the default alarm pool, type=bool, default=0, advanced=true, group=pico_time +#ifndef PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +/*! + * \brief If 1 then the default alarm pool is disabled (so no hardware alarm is claimed for the pool) + * + * \note Setting to 1 may cause some code not to compile as default timer pool related methods are removed + * + * \note When the default alarm pool is disabled, \a sleep_ methods and timeouts are no longer lower powered + * (they become \a busy_wait_) + * + * \ingroup alarm + * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM + * \sa alarm_pool_get_default() + */ +#define PICO_TIME_DEFAULT_ALARM_POOL_DISABLED 0 +#endif + +// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, Select which HW alarm is used for the default alarm pool, min=0, max=3, default=3, advanced=true, group=pico_time +#ifndef PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM +/*! + * \brief Selects which hardware alarm is used for the default alarm pool + * \ingroup alarm + * \sa alarm_pool_get_default() + */ +#define PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM 3 +#endif + +// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, Selects the maximum number of concurrent timers in the default alarm pool, min=0, max=255, default=16, advanced=true, group=pico_time +#ifndef PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS +/*! + * \brief Selects the maximum number of concurrent timers in the default alarm pool + * \ingroup alarm + * + * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 + * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM + * \sa alarm_pool_get_default() + */ +#define PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS 16 +#endif + +/** + * \brief The identifier for an alarm + * + * \note this identifier is signed because -1 is used as an error condition when creating alarms + * + * \note alarm ids may be reused, however for convenience the implementation makes an attempt to defer + * reusing as long as possible. You should certainly expect it to be hundreds of ids before one is + * reused, although in most cases it is more. Nonetheless care must still be taken when cancelling + * alarms or other functionality based on alarms when the alarm may have expired, as eventually + * the alarm id may be reused for another alarm. + * + * \ingroup alarm + */ +typedef int32_t alarm_id_t; // note this is signed because we use -1 as a meaningful error value + +/** + * \brief User alarm callback + * \ingroup alarm + * \param id the alarm_id as returned when the alarm was added + * \param user_data the user data passed when the alarm was added + * \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire + * \return >0 to reschedule the same alarm this many us from the time this method returns + * \return 0 to not reschedule the alarm + */ +typedef int64_t (*alarm_callback_t)(alarm_id_t id, void *user_data); + +typedef struct alarm_pool alarm_pool_t; + +/** + * \brief Create the default alarm pool (if not already created or disabled) + * \ingroup alarm + */ +void alarm_pool_init_default(); + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +/*! + * \brief The default alarm pool used when alarms are added without specifying an alarm pool, + * and also used by the SDK to support lower power sleeps and timeouts. + * + * \ingroup alarm + * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM + */ +alarm_pool_t *alarm_pool_get_default(); +#endif + +/** + * \brief Create an alarm pool + * + * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from. + * + * In many situations there is never any need for anything other than the default alarm pool, however you + * might want to create another if you want alarm callbacks on core 1 or require alarm pools of + * different priority (IRQ priority based preemption of callbacks) + * + * \note This method will hard assert if the hardware alarm is already claimed. + * + * \ingroup alarm + * \param hardware_alarm_num the hardware alarm to use to back this pool + * \param max_timers the maximum number of timers + * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 + * \sa alarm_pool_get_default() + * \sa hardware_claiming + */ +alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers); + +/** + * \brief Return the hardware alarm used by an alarm pool + * \ingroup alarm + * \param pool the pool + * \return the hardware alarm used by the pool + */ +uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool); + +/** + * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm + * \ingroup alarm + * \param pool the pool + * \return the hardware alarm used by the pool + */ +void alarm_pool_destroy(alarm_pool_t *pool); + +/*! + * \brief Add an alarm callback to be called at a specific time + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core the alarm pool was created on. If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param time the timestamp when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past); + +/*! + * \brief Add an alarm callback to be called after a delay specified in microseconds + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core the alarm pool was created on. If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param us the delay (from now) in microseconds when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { + return alarm_pool_add_alarm_at(pool, delayed_by_us(get_absolute_time(), us), callback, user_data, fire_if_past); +} + +/*! + * \brief Add an alarm callback to be called after a delay specified in milliseconds + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core the alarm pool was created on. If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param ms the delay (from now) in milliseconds when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { + return alarm_pool_add_alarm_at(pool, delayed_by_ms(get_absolute_time(), ms), callback, user_data, fire_if_past); +} + +/*! + * \brief Cancel an alarm + * \ingroup alarm + * \param pool the alarm_pool containing the alarm + * \param alarm_id the alarm + * \return true if the alarm was cancelled, false if it didn't exist + * \sa alarm_id_t for a note on reuse of IDs + */ +bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id); + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +/*! + * \brief Add an alarm callback to be called at a specific time + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param time the timestamp when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { + return alarm_pool_add_alarm_at(alarm_pool_get_default(), time, callback, user_data, fire_if_past); +} + +/*! + * \brief Add an alarm callback to be called after a delay specified in microseconds + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param us the delay (from now) in microseconds when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { + return alarm_pool_add_alarm_in_us(alarm_pool_get_default(), us, callback, user_data, fire_if_past); +} + +/*! + * \brief Add an alarm callback to be called after a delay specified in milliseconds + * \ingroup alarm + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param ms the delay (from now) in milliseconds when (after which) the callback should fire + * @param callback the callback function + * @param user_data user data to pass to the callback function + * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @return >0 the alarm id + * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return -1 if there were no alarm slots available + */ +static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { + return alarm_pool_add_alarm_in_ms(alarm_pool_get_default(), ms, callback, user_data, fire_if_past); +} +/*! + * \brief Cancel an alarm from the default alarm pool + * \ingroup alarm + * \param alarm_id the alarm + * \return true if the alarm was cancelled, false if it didn't exist + * \sa alarm_id_t for a note on reuse of IDs + */ +static inline bool cancel_alarm(alarm_id_t alarm_id) { + return alarm_pool_cancel_alarm(alarm_pool_get_default(), alarm_id); +} + +#endif + +/*! + * \defgroup repeating_timer repeating_timer + * \ingroup pico_time + * \brief Repeating Timer functions for simple scheduling of repeated execution + * + * \note The regular \a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback), + * however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which + * the alarm framework does not have space for). + */ + +typedef struct repeating_timer repeating_timer_t; + +/** + * \brief Callback for a repeating timer + * \ingroup repeating_timer + * \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user + * \return true to continue repeating, false to stop. + */ +typedef bool (*repeating_timer_callback_t)(repeating_timer_t *rt); + +/** + * \brief Information about a repeating timer + * \ingroup repeating_timer + * \return + */ +struct repeating_timer { + int64_t delay_us; + alarm_pool_t *pool; + alarm_id_t alarm_id; + repeating_timer_callback_t callback; + void *user_data; +}; + +/*! + * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds + * \ingroup repeating_timer + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core the alarm pool was created on. If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback) + * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 + * @param callback the repeating timer callback function + * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. + * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space + * @return false if there were no alarm slots available to create the timer, true otherwise. + */ +bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out); + +/*! + * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds + * \ingroup repeating_timer + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core the alarm pool was created on. If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback) + * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond + * @param callback the repeating timer callback function + * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. + * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space + * @return false if there were no alarm slots available to create the timer, true otherwise. + */ +static inline bool alarm_pool_add_repeating_timer_ms(alarm_pool_t *pool, int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { + return alarm_pool_add_repeating_timer_us(pool, delay_ms * (int64_t)1000, callback, user_data, out); +} + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +/*! + * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds + * \ingroup repeating_timer + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 + * @param callback the repeating timer callback function + * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. + * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space + * @return false if there were no alarm slots available to create the timer, true otherwise. + */ +static inline bool add_repeating_timer_us(int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { + return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_us, callback, user_data, out); +} + +/*! + * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds + * \ingroup repeating_timer + * + * Generally the callback is called as soon as possible after the time specified from an IRQ handler + * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before + * the alarm setup could be completed, then this method will optionally call the callback itself + * and then return a return code to indicate that the target time has passed. + * + * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. + * + * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond + * @param callback the repeating timer callback function + * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. + * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space + * @return false if there were no alarm slots available to create the timer, true otherwise. + */ +static inline bool add_repeating_timer_ms(int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { + return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_ms * (int64_t)1000, callback, user_data, out); +} +#endif + +/** + * \brief Cancel a repeating timer + * \ingroup repeating_timer + * \param timer the repeating timer to cancel + * \return true if the repeating timer was cancelled, false if it didn't exist + * \sa alarm_id_t for a note on reuse of IDs + */ +bool cancel_repeating_timer(repeating_timer_t *timer); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/timeout_helper.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/timeout_helper.h new file mode 100644 index 00000000000..e757f730589 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/timeout_helper.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TIMEOUT_HELPER_H +#define _PICO_TIMEOUT_HELPER_H + +#include "pico/time.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct timeout_state { + absolute_time_t next_timeout; + uint64_t param; +} timeout_state_t; + +typedef bool (*check_timeout_fn)(timeout_state_t *ts); + +check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target); +check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c new file mode 100644 index 00000000000..e004c00d81e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "pico.h" +#include "pico/time.h" +#include "pico/util/pheap.h" +#include "hardware/sync.h" +#include "hardware/gpio.h" + +const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0); +const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, ULONG_MAX); + +typedef struct alarm_pool_entry { + absolute_time_t target; + alarm_callback_t callback; + void *user_data; +} alarm_pool_entry_t; + +typedef struct alarm_pool { + pheap_t *heap; + spin_lock_t *lock; + alarm_pool_entry_t *entries; + // one byte per entry, used to provide more longevity to public IDs than heap node ids do + // (this is increment every time the heap node id is re-used) + uint8_t *entry_ids_high; + alarm_id_t alarm_in_progress; // this is set during a callback from the IRQ handler... it can be cleared by alarm_cancel to prevent repeats + uint8_t hardware_alarm_num; +} alarm_pool_t; + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +static alarm_pool_t *default_alarm_pool; +#endif +static alarm_pool_t *pools[NUM_TIMERS]; + +void alarm_pool_init_default() { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + // allow multiple calls for ease of use from host tests + if (!default_alarm_pool) { + default_alarm_pool = alarm_pool_create(PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, + PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); + } +#endif +} + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +alarm_pool_t *alarm_pool_get_default() { + assert(default_alarm_pool); + return default_alarm_pool; +} +#endif + +static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) { + assert(id && id <= pool->heap->max_nodes); + return pool->entries + id - 1; +} + +static inline uint8_t *get_entry_id_high(alarm_pool_t *pool, pheap_node_id_t id) { + assert(id && id <= pool->heap->max_nodes); + return pool->entry_ids_high + id - 1; +} + +bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_id_t b) { + alarm_pool_t *pool = (alarm_pool_t *)user_data; + return to_us_since_boot(get_entry(pool, a)->target) < to_us_since_boot(get_entry(pool, b)->target); +} + +static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) { + return ((uint)id_high << 8u * sizeof(id)) | id; +} + +static alarm_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, + void *user_data, alarm_id_t reuse_id, bool create_if_past, bool *missed) { + alarm_id_t id; + if (reuse_id) { + assert(!ph_contains(pool->heap, reuse_id)); + id = reuse_id; + } else { + id = ph_new_node(pool->heap); + } + if (id) { + alarm_pool_entry_t *entry = get_entry(pool, id); + entry->target = time; + entry->callback = callback; + entry->user_data = user_data; + if (id == ph_insert(pool->heap, id)) { + bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time); + if (is_missed && !create_if_past) { + ph_delete(pool->heap, id); + } + if (missed) *missed = is_missed; + } + } + return id; +} + +static void alarm_pool_alarm_callback(uint alarm_num) { + // note this is called from timer IRQ handler + alarm_pool_t *pool = pools[alarm_num]; + bool again; + do { + absolute_time_t now = get_absolute_time(); + alarm_callback_t callback = NULL; + absolute_time_t target = nil_time; + void *user_data = NULL; + uint8_t id_high; + again = false; + uint32_t save = spin_lock_blocking(pool->lock); + pheap_node_id_t next_id = ph_peek_head(pool->heap); + if (next_id) { + alarm_pool_entry_t *entry = get_entry(pool, next_id); + if (absolute_time_diff_us(now, entry->target) <= 0) { + // we reserve the id in case we need to re-add the timer + pheap_node_id_t __unused removed_id = ph_remove_head_reserve(pool->heap, true); + assert(removed_id == next_id); // will be true under lock + target = entry->target; + callback = entry->callback; + user_data = entry->user_data; + assert(callback); + id_high = *get_entry_id_high(pool, next_id); + pool->alarm_in_progress = make_public_id(id_high, removed_id); + } else { + if (hardware_alarm_set_target(alarm_num, entry->target)) { + again = true; + } + } + } + spin_unlock(pool->lock, save); + if (callback) { + int64_t repeat = callback(make_public_id(id_high, next_id), user_data); + save = spin_lock_blocking(pool->lock); + // todo think more about whether we want to keep calling + if (repeat < 0 && pool->alarm_in_progress) { + assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); + add_alarm_under_lock(pool, delayed_by_us(target, -repeat), callback, user_data, next_id, true, NULL); + } else if (repeat > 0 && pool->alarm_in_progress) { + assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); + add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), repeat), callback, user_data, next_id, + true, NULL); + } else { + // need to return the id to the heap + ph_add_to_free_list(pool->heap, next_id); + (*get_entry_id_high(pool, next_id))++; // we bump it for next use of id + } + pool->alarm_in_progress = 0; + spin_unlock(pool->lock, save); + again = true; + } + } while (again); +} + +// note the timer is create with IRQs on this core +alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) { + hardware_alarm_claim(hardware_alarm_num); + hardware_alarm_cancel(hardware_alarm_num); + hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback); + alarm_pool_t *pool = (alarm_pool_t *)malloc(sizeof(alarm_pool_t)); + pool->lock = spin_lock_instance(next_striped_spin_lock_num()); + pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool); + pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t)); + pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t)); + pool->hardware_alarm_num = hardware_alarm_num; + pools[hardware_alarm_num] = pool; + return pool; +} + +void alarm_pool_destroy(alarm_pool_t *pool) { + assert(pools[pool->hardware_alarm_num] == pool); + pools[pool->hardware_alarm_num] = NULL; + // todo clear out timers + ph_destroy(pool->heap); + hardware_alarm_set_callback(pool->hardware_alarm_num, NULL); + hardware_alarm_unclaim(pool->hardware_alarm_num); + free(pool->entry_ids_high); + free(pool->entries); + free(pool); +} + +alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, + void *user_data, bool fire_if_past) { + bool missed = false; + + uint public_id; + do { + uint8_t id_high = 0; + uint32_t save = spin_lock_blocking(pool->lock); + pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed); + if (id) id_high = *get_entry_id_high(pool, id); + + spin_unlock(pool->lock, save); + + if (!id) { + return -1; + } + + public_id = missed ? 0 : make_public_id(id_high, id); + if (missed && fire_if_past) { + int64_t repeat = callback(public_id, user_data); + if (!repeat) { + public_id = 0; + break; + } else if (repeat < 0) { + time = delayed_by_us(time, -repeat); + } else { + time = delayed_by_us(get_absolute_time(), repeat); + } + } else { + break; + } + } while (true); + return public_id; +} + +bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) { + bool rc = false; + uint32_t save = spin_lock_blocking(pool->lock); + pheap_node_id_t id = (pheap_node_id_t) alarm_id; + if (ph_contains(pool->heap, id)) { + assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress + // check we have the right high value + uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t)); + if (id_high == *get_entry_id_high(pool, id)) { + rc = ph_delete(pool->heap, id); + // note we don't bother to remove the actual hardware alarm timeout... + // it will either do callbacks or not depending on other alarms, and reset the next timeout itself + assert(rc); + } + } else { + if (alarm_id == pool->alarm_in_progress) { + // make sure the alarm doesn't repeat + pool->alarm_in_progress = 0; + } + } + spin_unlock(pool->lock, save); + return rc; +} + +uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) { + return pool->hardware_alarm_num; +} + +static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) { + alarm_pool_t *pool = (alarm_pool_t *)user_data; +#if PICO_ON_DEVICE + printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id)); +#else + printf("%ld", to_us_since_boot(get_entry(pool, id)->target)); +#endif +} + +static int64_t repeating_timer_callback(alarm_id_t id, void *user_data) { + repeating_timer_t *rt = (repeating_timer_t *)user_data; + if (rt->callback(rt)) { + return rt->delay_us; + } else { + rt->alarm_id = 0; + return 0; + } +} + +bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { + if (!delay_us) delay_us = 1; + out->pool = pool; + out->callback = callback; + out->delay_us = delay_us; + out->user_data = user_data; + out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us(delay_us >= 0 ? delay_us : -delay_us), repeating_timer_callback, out, true); + return out->alarm_id > 0; +} + +bool cancel_repeating_timer(repeating_timer_t *timer) { + bool rc = false; + if (timer->alarm_id) { + rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id); + timer->alarm_id = 0; + } + return rc; +} + +void alarm_pool_dump(alarm_pool_t *pool) { + uint32_t save = spin_lock_blocking(pool->lock); + ph_dump(pool->heap, alarm_pool_dump_key, pool); + spin_unlock(pool->lock, save); +} + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +static int64_t sev_callback(alarm_id_t id, void *user_data) { + __sev(); + return 0; +} +#endif + +void sleep_until(absolute_time_t t) { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + uint64_t t_us = to_us_since_boot(t); + uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US; + // needs to work in the first PICO_TIME_SLEEP_OVERHEAD_ADJUST_US of boot + if (t_before_us > t_us) t_before_us = 0; + absolute_time_t t_before; + update_us_since_boot(&t_before, t_before_us); + if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) { + if (add_alarm_at(t_before, sev_callback, NULL, false) >= 0) { + // able to add alarm for just before the time + while (!time_reached(t_before)) { + __wfe(); + } + } + } +#endif + // now wait until the exact time + busy_wait_until(t); +} + +void sleep_us(uint64_t us) { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + sleep_until(make_timeout_time_us(us)); +#else + if (us >> 32u) { + busy_wait_until(make_timeout_time_us(us)); + } else { + busy_wait_us_32(us); + } +#endif + +} + +void sleep_ms(uint32_t ms) { + sleep_us(ms * 1000ull); +} + +bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + alarm_id_t id; + id = add_alarm_at(timeout_timestamp, sev_callback, NULL, false); + if (id <= 0) { + tight_loop_contents(); + return time_reached(timeout_timestamp); + } else { + __wfe(); + // we need to clean up if it wasn't us that caused the wfe; if it was this will be a noop. + cancel_alarm(id); + return time_reached(timeout_timestamp); + } +#else + tight_loop_contents(); + return time_reached(timeout_timestamp); +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/timeout_helper.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/timeout_helper.c new file mode 100644 index 00000000000..d9abe5a33b0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/timeout_helper.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/timeout_helper.h" + +static bool check_single_timeout_us(timeout_state_t *ts) { + return time_reached(ts->next_timeout); +} + +check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target) { + ts->next_timeout = target; + return check_single_timeout_us; +} + +static bool check_per_iteration_timeout_us(timeout_state_t *ts) { + if (time_reached(ts->next_timeout)) { + return true; + } + ts->next_timeout = make_timeout_time_us(ts->param); + return false; +} + +check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us) { + ts->next_timeout = make_timeout_time_us(per_iteration_timeout_us); + ts->param = per_iteration_timeout_us; + return check_per_iteration_timeout_us; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt new file mode 100644 index 00000000000..a829c14e94c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt @@ -0,0 +1,15 @@ +if (NOT TARGET pico_util_headers) + add_library(pico_util_headers INTERFACE) + target_include_directories(pico_util_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(pico_util_headers INTERFACE pico_base_headers hardware_sync) +endif() + +if (NOT TARGET pico_util) + add_library(pico_util INTERFACE) + target_sources(pico_util INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/datetime.c + ${CMAKE_CURRENT_LIST_DIR}/pheap.c + ${CMAKE_CURRENT_LIST_DIR}/queue.c + ) + target_link_libraries(pico_util INTERFACE pico_util_headers) +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/datetime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/datetime.c new file mode 100644 index 00000000000..e035515d37b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/datetime.c @@ -0,0 +1,41 @@ +#include "pico/util/datetime.h" + +#include + +static const char *DATETIME_MONTHS[12] = { + "January", + "February", + "March", + "April", + "May", + "June", + "July", + "August", + "September", + "October", + "November", + "December" +}; + +static const char *DATETIME_DOWS[7] = { + "Sunday", + "Monday", + "Tuesday", + "Wednesday", + "Thursday", + "Friday", + "Saturday", +}; + +void datetime_to_str(char *buf, uint buf_size, const datetime_t *t) { + snprintf(buf, + buf_size, + "%s %d %s %d:%02d:%02d %d", + DATETIME_DOWS[t->dotw], + t->day, + DATETIME_MONTHS[t->month - 1], + t->hour, + t->min, + t->sec, + t->year); +}; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/doc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/doc.h new file mode 100644 index 00000000000..4485b5d5ffe --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup pico_util pico_util + * \brief Useful data structures and utility functions + */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h new file mode 100644 index 00000000000..61b5c7e9230 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_DATETIME_H +#define _PICO_DATETIME_H + +#include "pico.h" + +/** \file datetime.h + * \defgroup util_datetime datetime + * \brief Date/Time formatting + * \ingroup pico_util + */ + +/*! \brief Convert a datetime_t structure to a string + * \ingroup util_datetime + * + * \param buf character buffer to accept generated string + * \param buf_size The size of the passed in buffer + * \param t The datetime to be converted. + */ +void datetime_to_str(char *buf, uint buf_size, const datetime_t *t); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h new file mode 100644 index 00000000000..59617e7def8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_UTIL_PHEAP_H +#define _PICO_UTIL_PHEAP_H + +#include "pico.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PHEAP, Enable/disable assertions in the pheap module, type=bool, default=0, group=pico_util +#ifndef PARAM_ASSERTIONS_ENABLED_PHEAP +#define PARAM_ASSERTIONS_ENABLED_PHEAP 0 +#endif + +/** + * \file pheap.h + * \defgroup util_pheap pheap + * Pairing Heap Implementation + * \ingroup pico_util + * + * pheap defines a simple pairing heap. the implementation simply tracks array indexes, it is up to + * the user to provide storage for heap entries and a comparison function. + * + * NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore + * if used concurrently, the caller needs to protect around their use of the returned id. + * for example, ph_remove_head returns the id of an element that is no longer in the heap. + * + * The user can still use this to look at the data in their companion array, however obviously further operations + * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations + * + */ +// PICO_CONFIG: PICO_PHEAP_MAX_ENTRIES, Maximum number of entries in the pheap, min=1, max=65534, default=255, group=pico_util +#ifndef PICO_PHEAP_MAX_ENTRIES +#define PICO_PHEAP_MAX_ENTRIES 255 +#endif + +// public heap_node ids are numbered from 1 (0 means none) +#if PICO_PHEAP_MAX_ENTRIES < 256 +typedef uint8_t pheap_node_id_t; +#elif PICO_PHEAP_MAX_ENTRIES < 65535 +typedef uint16_t pheap_node_id_t; +#else +#error invalid PICO_PHEAP_MAX_ENTRIES +#endif + +typedef struct pheap_node { + pheap_node_id_t child, sibling, parent; +} pheap_node_t; + +// return true if a < b in natural order +typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b); + +typedef struct pheap { + pheap_node_t *nodes; + pheap_comparator comparator; + void *user_data; + pheap_node_id_t max_nodes; + pheap_node_id_t root_id; + // we remove from head and add to tail to stop reusing the same ids + pheap_node_id_t free_head_id; + pheap_node_id_t free_tail_id; +} pheap_t; + +pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data); + +void ph_clear(pheap_t *heap); + +void ph_destroy(pheap_t *heap); + +static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) { + assert(id && id <= heap->max_nodes); + return heap->nodes + id - 1; +} + +static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) { + pheap_node_t *n = ph_get_node(heap, parent_id); + assert(parent_id); + assert(child_id); + assert(parent_id != child_id); + pheap_node_t *c = ph_get_node(heap, child_id); + c->parent = parent_id; + if (!n->child) { + n->child = child_id; + } else { + c->sibling = n->child; + n->child = child_id; + } +} + +static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) { + if (!a) return b; + if (!b) return a; + if (heap->comparator(heap->user_data, a, b)) { + ph_add_child_node(heap, a, b); + return a; + } else { + ph_add_child_node(heap, b, a); + return b; + } +} + +static inline pheap_node_id_t ph_new_node(pheap_t *heap) { + if (!heap->free_head_id) return 0; + pheap_node_id_t id = heap->free_head_id; + heap->free_head_id = ph_get_node(heap, id)->sibling; + if (!heap->free_head_id) heap->free_tail_id = 0; + return id; +} + +// note this will callback the comparator for the node +// returns the (new) root of the heap +static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) { + assert(id); + pheap_node_t *hn = ph_get_node(heap, id); + hn->child = hn->sibling = hn->parent = 0; + heap->root_id = ph_merge_nodes(heap, heap->root_id, id); + return heap->root_id; +} + +static inline pheap_node_id_t ph_peek_head(pheap_t *heap) { + return heap->root_id; +} + +pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve); + +static inline pheap_node_id_t ph_remove_head(pheap_t *heap) { + return ph_remove_head_reserve(heap, false); +} + +static inline bool ph_contains(pheap_t *heap, pheap_node_id_t id) { + return id == heap->root_id || ph_get_node(heap, id)->parent; +} + +bool ph_delete(pheap_t *heap, pheap_node_id_t id); + +static inline void ph_add_to_free_list(pheap_t *heap, pheap_node_id_t id) { + assert(id && !ph_contains(heap, id)); + if (heap->free_tail_id) { + ph_get_node(heap, heap->free_tail_id)->sibling = id; + } + heap->free_tail_id = id; +} + +void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h new file mode 100644 index 00000000000..d65548eaa72 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _UTIL_QUEUE_H +#define _UTIL_QUEUE_H + +#include "pico.h" +#include "hardware/sync.h" + +/** \file queue.h + * \defgroup queue queue + * Multi-core and IRQ safe queue implementation. + * + * Note that this queue stores values of a specified size, and pushed values are copied into the queue + * \ingroup pico_util + */ + +typedef struct { + spin_lock_t *lock; + uint8_t *data; + uint16_t wptr; + uint16_t rptr; + uint16_t element_size; + uint16_t element_count; +} queue_t; + +/*! \brief Initialise a queue with a specific spinlock for concurrency protection + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param element_size Size of each value in the queue + * \param element_count Maximum number of entries in the queue + * \param spinlock_num The spin ID used to protect the queue + */ +void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num); + +/*! \brief Initialise a queue, allocating a (possibly shared) spinlock + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param element_size Size of each value in the queue + * \param element_count Maximum number of entries in the queue + */ +static inline void queue_init(queue_t *q, uint element_size, uint element_count) { + return queue_init_with_spinlock(q, element_size, element_count, next_striped_spin_lock_num()); +} + +/*! \brief Destroy the specified queue. + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * + * Does not deallocate the queue_t structure itself. + */ +void queue_free(queue_t *q); + +/*! \brief Unsafe check of level of the specified queue. + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return Number of entries in the queue + * + * This does not use the spinlock, so may return incorrect results if the + * spin lock is not externally locked + */ +static inline uint queue_get_level_unsafe(queue_t *q) { + int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr; + if (rc < 0) { + rc += + q->element_count + 1; + } + return rc; +} + +/*! \brief Check of level of the specified queue. + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return Number of entries in the queue + */ +static inline uint queue_get_level(queue_t *q) { + uint32_t save = spin_lock_blocking(q->lock); + uint level = queue_get_level_unsafe(q); + spin_unlock(q->lock, save); + return level; +} + +/*! \brief Check if queue is empty + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return true if queue is empty, false otherwise + * + * This function is interrupt and multicore safe. + */ +static inline bool queue_is_empty(queue_t *q) { + return queue_get_level(q) == 0; +} + +/*! \brief Check if queue is full + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return true if queue is full, false otherwise + * + * This function is interrupt and multicore safe. + */ +static inline bool queue_is_full(queue_t *q) { + return queue_get_level(q) == q->element_count; +} + +// nonblocking queue access functions: + +/*! \brief Non-blocking add value queue if not full + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to value to be copied into the queue + * \return true if the value was added + * + * If the queue is full this function will return immediately with false, otherwise + * the data is copied into a new value added to the queue, and this function will return true. + */ +bool queue_try_add(queue_t *q, void *data); + +/*! \brief Non-blocking removal of entry from the queue if non empty + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to the location to receive the removed value + * \return true if a value was removed + * + * If the queue is not empty function will copy the removed value into the location provided and return + * immediately with true, otherwise the function will return immediately with false. + */ +bool queue_try_remove(queue_t *q, void *data); + +/*! \brief Non-blocking peek at the next item to be removed from the queue + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to the location to receive the peeked value + * \return true if there was a value to peek + * + * If the queue is not empty this function will return immediately with true with the peeked entry + * copied into the location specified by the data parameter, otherwise the function will return false. + */ +bool queue_try_peek(queue_t *q, void *data); + +// blocking queue access functions: + +/*! \brief Blocking add of value to queue + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to value to be copied into the queue + * + * If the queue is full this function will block, until a removal happens on the queue + */ +void queue_add_blocking(queue_t *q, void *data); + +/*! \brief Blocking remove entry from queue + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to the location to receive the removed value + * + * If the queue is empty this function will block until a value is added. + */ +void queue_remove_blocking(queue_t *q, void *data); + +/*! \brief Blocking peek at next value to be removed from queue + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \param data Pointer to the location to receive the peeked value + * + * If the queue is empty function will block until a value is added + */ +void queue_peek_blocking(queue_t *q, void *data); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c new file mode 100644 index 00000000000..8e9c68614c3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "pico/util/pheap.h" + +pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) { + invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << sizeof(pheap_node_id_t))); + pheap_t *heap = calloc(1, sizeof(pheap_t)); + heap->max_nodes = max_nodes; + heap->comparator = comparator; + heap->nodes = calloc(max_nodes, sizeof(pheap_node_t)); + heap->user_data = user_data; + ph_clear(heap); + return heap; +} + +void ph_clear(pheap_t *heap) { + heap->root_id = 0; + heap->free_head_id = 1; + heap->free_tail_id = heap->max_nodes; + for(uint i = 1; i < heap->max_nodes; i++) { + ph_get_node(heap, i)->sibling = i + 1; + } + ph_get_node(heap, heap->max_nodes)->sibling = 0; +} + +void ph_destroy(pheap_t *heap) { + free(heap->nodes); + free(heap); +} + +pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) { + if (!id || !ph_get_node(heap, id)->sibling) { + return id; + } else { + pheap_node_id_t a, b, new_node; + a = id; + b = ph_get_node(heap, id)->sibling; + new_node = ph_get_node(heap, b)->sibling; + ph_get_node(heap, a)->sibling = ph_get_node(heap, b)->sibling = 0; + return ph_merge_nodes(heap, ph_merge_nodes(heap, a, b), ph_merge_two_pass(heap, new_node)); + } +} + +static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool reserve) { + assert(root_id); +// printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling); + assert(!ph_get_node(heap, root_id)->sibling); + assert(!ph_get_node(heap, root_id)->parent); + pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child); + if (!reserve) { + if (heap->free_tail_id) { + ph_get_node(heap, heap->free_tail_id)->sibling = root_id; + } + heap->free_tail_id = root_id; + } + if (new_root_id) ph_get_node(heap, new_root_id)->parent = 0; + ph_get_node(heap, root_id)->sibling = 0; + return new_root_id; +} + +pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve) { + pheap_node_id_t old_root_id = ph_peek_head(heap); + heap->root_id = ph_remove_any_head(heap, old_root_id, reserve); + return old_root_id; +} + +#include +bool ph_delete(pheap_t *heap, pheap_node_id_t id) { + // 1) trivial cases + if (!id) return false; + if (id == heap->root_id) { + ph_remove_head(heap); + return true; + } + // 2) unlink the node from the tree + pheap_node_t *node = ph_get_node(heap, id); + if (!node->parent) return false; // not in tree + pheap_node_t *parent = ph_get_node(heap, node->parent); + if (parent->child == id) { + parent->child = node->sibling; + } else { + pheap_node_id_t prev_sibling_id = parent->child; + bool __unused found = false; + do { + pheap_node_t *prev_sibling = ph_get_node(heap, prev_sibling_id); + if (prev_sibling->sibling == id) { + prev_sibling->sibling = node->sibling; + found = true; + break; + } + prev_sibling_id = prev_sibling->sibling; + } while (prev_sibling_id); + assert(found); + } + node->sibling = node->parent = 0; +// ph_dump(heap, NULL, NULL); + // 3) remove it from the head of its own subtree + pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, false); + assert(new_sub_tree != heap->root_id); + heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree); + return true; +} + +static uint ph_dump_node(pheap_t *heap, pheap_node_id_t id, void (*dump_key)(pheap_node_id_t, void *), void *user_data, uint indent) { + uint count = 0; + if (id) { + count++; + for (uint i = 0; i < indent * 2; i++) { + putchar(' '); + } + pheap_node_t *node = ph_get_node(heap, id); + printf("%d (c=%d s=%d p=%d) ", id, node->child, node->sibling, node->parent); + if (dump_key) dump_key(id, user_data); + printf("\n"); + count += ph_dump_node(heap, node->child, dump_key, user_data, indent + 1); + count += ph_dump_node(heap, node->sibling, dump_key, user_data, indent); + } + return count; +} + +void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data) { + uint count = ph_dump_node(heap, heap->root_id, dump_key, user_data, 0); + printf("node_count %d\n", count); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c new file mode 100644 index 00000000000..785e7f01ade --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "pico/util/queue.h" + +void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) { + q->lock = spin_lock_instance(spinlock_num); + q->data = (uint8_t *)calloc(element_count + 1, element_size); + q->element_count = element_count; + q->element_size = element_size; + q->wptr = 0; + q->rptr = 0; +} + +void queue_free(queue_t *q) { + free(q->data); +} + +static inline void *element_ptr(queue_t *q, uint index) { + assert(index <= q->element_count); + return q->data + index * q->element_size; +} + +static inline uint16_t inc_index(queue_t *q, uint16_t index) { + if (++index > q->element_count) { // > because we have element_count + 1 elements + index = 0; + } + return index; +} + +bool queue_try_add(queue_t *q, void *data) { + bool success = false; + uint32_t flags = spin_lock_blocking(q->lock); + if (queue_get_level_unsafe(q) != q->element_count) { + memcpy(element_ptr(q, q->wptr), data, q->element_size); + q->wptr = inc_index(q, q->wptr); + success = true; + } + spin_unlock(q->lock, flags); + if (success) __sev(); + return success; +} + +bool queue_try_remove(queue_t *q, void *data) { + bool success = false; + uint32_t flags = spin_lock_blocking(q->lock); + if (queue_get_level_unsafe(q) != 0) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + q->rptr = inc_index(q, q->rptr); + success = true; + } + spin_unlock(q->lock, flags); + if (success) __sev(); + return success; +} + +bool queue_try_peek(queue_t *q, void *data) { + bool success = false; + uint32_t flags = spin_lock_blocking(q->lock); + if (queue_get_level_unsafe(q) != 0) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + success = true; + } + spin_unlock(q->lock, flags); + return success; +} + +void queue_add_blocking(queue_t *q, void *data) { + bool done; + do { + done = queue_try_add(q, data); + if (done) break; + __wfe(); + } while (true); +} + +void queue_remove_blocking(queue_t *q, void *data) { + bool done; + do { + done = queue_try_remove(q, data); + if (done) break; + __wfe(); + } while (true); +} + +void queue_peek_blocking(queue_t *q, void *data) { + bool done; + do { + done = queue_try_peek(q, data); + if (done) break; + __wfe(); + } while (true); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h new file mode 100644 index 00000000000..7b537522f9a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// --------------------------------------- +// THIS FILE IS AUTOGENERATED; DO NOT EDIT +// --------------------------------------- + +#ifndef _PICO_VERSION_H +#define _PICO_VERSION_H + +#define PICO_SDK_VERSION_MAJOR 1 +#define PICO_SDK_VERSION_MINOR 0 +#define PICO_SDK_VERSION_REVISION 1 +#define PICO_SDK_VERSION_STRING "1.0.1" + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host.cmake new file mode 100644 index 00000000000..5a3f3584acb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host.cmake @@ -0,0 +1,10 @@ +# For targeting the host for testing purposes + +function(pico_add_extra_outputs TARGET) +endfunction() + +set(PICO_NO_HARDWARE "1" CACHE INTERNAL "") +set(PICO_ON_DEVICE "0" CACHE INTERNAL "") + +add_subdirectory(common) +add_subdirectory(host) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt new file mode 100644 index 00000000000..56790055b06 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt @@ -0,0 +1,28 @@ +pico_add_subdirectory(hardware_divider) +pico_add_subdirectory(hardware_gpio) +pico_add_subdirectory(hardware_sync) +pico_add_subdirectory(hardware_timer) +pico_add_subdirectory(hardware_uart) +pico_add_subdirectory(pico_bit_ops) +pico_add_subdirectory(pico_divider) +pico_add_subdirectory(pico_multicore) +pico_add_subdirectory(pico_platform) +pico_add_subdirectory(pico_printf) +pico_add_subdirectory(pico_stdio) +pico_add_subdirectory(pico_stdlib) + +pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) + +macro(pico_set_float_implementation TARGET IMPL) +endmacro() + +macro(pico_set_double_implementation TARGET IMPL) +endmacro() + +macro(pico_set_boot_stage2 TARGET IMPL) +endmacro() + +set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") +function(pico_define_boot_stage2 NAME) + add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c) +endfunction() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/README.md b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/README.md new file mode 100644 index 00000000000..c6d89622af1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/README.md @@ -0,0 +1,14 @@ +This is a basic set of replacement library implementations sufficient to get simple applications +running on your computer (Raspberry Pi OS, Linux, macOS or Windows using Cygwin or Windows Subsystem for Linux). +It is selected by `PICO_PLATFORM=host` in your CMake build + +This can be extremely useful for testing and debugging higher level application code, or porting code which is not yet small enough +to run on the RP2040 device itself. + +This base level host library provides a minimal environment to compile programs, but is likely sufficient for programs +that don't access hardware directly. + +It is possible however to inject additional SDK library implementations/simulations to provide +more complete functionality. For an example of this see the [pico-host-sdl](https://github.com/raspberrypi/pico-host-sdl) +which uses the SDL2 library to add additional library support for pico_multicore, timers/alarms in pico-time and +pico-audio/pico-scanvideo from [pico-extras](https://github.com/raspberrypi/pico-extras) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c new file mode 100644 index 00000000000..cfa374bdb67 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c @@ -0,0 +1 @@ +// empty \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/CMakeLists.txt new file mode 100644 index 00000000000..a6156c0794a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(divider) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/divider.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/divider.c new file mode 100644 index 00000000000..a1331799840 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/divider.c @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/divider.h" + +__thread uint64_t hw_divider_result_threadlocal; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h new file mode 100644 index 00000000000..4d818747add --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_DIVIDER_H +#define _HARDWARE_DIVIDER_H + +#include "pico/types.h" + +typedef uint64_t divmod_result_t; + +static inline int __sign_of(int32_t v) { + return v > 0 ? 1 : (v < 0 ? -1 : 0); +} + +// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline uint64_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { + if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this + return (((uint64_t)(a%b))<<32u) | (a/b); +} + +// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline uint64_t hw_divider_divmod_s32(int32_t a, int32_t b) { + if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); + return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); +} + +extern __thread divmod_result_t hw_divider_result_threadlocal; + +static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { + hw_divider_result_threadlocal = hw_divider_divmod_s32(a, b); +} + +static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { + hw_divider_result_threadlocal = hw_divider_divmod_u32(a, b); +} + +static inline divmod_result_t hw_divider_result_wait() { + return hw_divider_result_threadlocal; +} + +static inline uint64_t hw_divider_result_nowait() { + return hw_divider_result_threadlocal; +} + +inline static uint32_t to_quotient_u32(unsigned long long int r) { + return (uint32_t) r; +} + +inline static int32_t to_quotient_s32(unsigned long long int r) { + return (int32_t)(uint32_t)r; +} + +inline static uint32_t to_remainder_u32(unsigned long long int r) { + return (uint32_t)(r >> 32u); +} + +inline static int32_t to_remainder_s32(unsigned long long int r) { + return (int32_t)(r >> 32u); +} + +static inline uint32_t hw_divider_u32_quotient_wait() { + return to_quotient_u32(hw_divider_result_wait()); +} + +static inline uint32_t hw_divider_u32_remainder_wait() { + return to_remainder_u32(hw_divider_result_wait()); +} + +static inline int32_t hw_divider_s32_quotient_wait() { + return to_quotient_s32(hw_divider_result_wait()); +} + +static inline int32_t hw_divider_s32_remainder_wait() { + return to_remainder_s32(hw_divider_result_wait()); +} + +static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { + return b ? (a / b) : -1; +} + +static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { + return b ? (a % b) : a; +} + +static inline int32_t hw_divider_s32_quotient(int32_t a, int32_t b) { + return b ? (a / b) : -__sign_of(a); +} + +static inline int32_t hw_divider_s32_remainder(int32_t a, int32_t b) { + return b ? (a % b) : a; +} + +static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { + return hw_divider_u32_quotient(a,b); +} + +static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { + return hw_divider_u32_remainder(a,b); +} + +static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { + return hw_divider_s32_quotient(a,b); +} + +static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { + return hw_divider_s32_remainder(a,b); +} + +typedef uint64_t hw_divider_state_t; + +static inline void hw_divider_save_state(hw_divider_state_t *dest) { + *dest = hw_divider_result_threadlocal; +} + +static inline void hw_divider_restore_state(hw_divider_state_t *src) { + hw_divider_result_threadlocal = *src; +} + +#endif // _HARDWARE_DIVIDER_H diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/CMakeLists.txt new file mode 100644 index 00000000000..1bfb078f37f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(gpio) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c new file mode 100644 index 00000000000..d5f4996f25a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/gpio.h" + +// todo weak or replace? probably weak +void gpio_set_function(uint gpio, enum gpio_function fn) { + +} + +void gpio_pull_up(uint gpio) { + +} + +void gpio_pull_down(uint gpio) { + +} + +void gpio_disable_pulls(uint gpio) { + +} + +void gpio_set_pulls(uint gpio, bool up, bool down) { + +} + +void gpio_set_outover(uint gpio, uint value) { + +} + +void gpio_set_inover(uint gpio, uint value) { + +} + +void gpio_set_oeover(uint gpio, uint value) { + +} + +void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) { + +} + +void gpio_acknowledge_irq(uint gpio, uint32_t events) { + +} + +void gpio_init(uint gpio) { + +} + +PICO_WEAK_FUNCTION_DEF(gpio_get) + +bool PICO_WEAK_FUNCTION_IMPL_NAME(gpio_get)(uint gpio) { + return 0; +} + +uint32_t gpio_get_all() { + return 0; +} + +void gpio_set_mask(uint32_t mask) { + +} + +void gpio_clr_mask(uint32_t mask) { + +} + +void gpio_xor_mask(uint32_t mask) { + +} + +void gpio_put_masked(uint32_t mask, uint32_t value) { + +} + +void gpio_put_all(uint32_t value) { + +} + +void gpio_put(uint gpio, int value) { + +} + +void gpio_set_dir_out_masked(uint32_t mask) { + +} + +void gpio_set_dir_in_masked(uint32_t mask) { + +} + +void gpio_set_dir_masked(uint32_t mask, uint32_t value) { + +} + +void gpio_set_dir_all_bits(uint32_t value) { + +} + +void gpio_set_dir(uint gpio, bool out) { + +} + +void gpio_debug_pins_init() { + +} + +void gpio_set_input_enabled(uint gpio, bool enable) { + +} + +void gpio_init_mask(uint gpio_mask) { + +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h new file mode 100644 index 00000000000..d1b14ba9d90 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_GPIO_H_ +#define _HARDWARE_GPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pico.h" + +enum gpio_function { + GPIO_FUNC_XIP = 0, + GPIO_FUNC_SPI = 1, + GPIO_FUNC_UART = 2, + GPIO_FUNC_I2C = 3, + GPIO_FUNC_PWM = 4, + GPIO_FUNC_SIO = 5, + GPIO_FUNC_PIO0 = 6, + GPIO_FUNC_PIO1 = 7, + GPIO_FUNC_GPCK = 8, + GPIO_FUNC_USB = 9, + GPIO_FUNC_NULL = 0xf, +}; + + +#define GPIO_OUT 1 +#define GPIO_IN 0 + +#define NUM_BANK0_GPIOS 30 + +// ---------------------------------------------------------------------------- +// Pad Controls + IO Muxing +// ---------------------------------------------------------------------------- +// Declarations for gpio.c + +void gpio_set_function(uint gpio, enum gpio_function fn); + +enum gpio_function gpio_get_function(uint gpio); + +void gpio_pull_up(uint gpio); + +void gpio_pull_down(uint gpio); + +void gpio_disable_pulls(uint gpio); + +void gpio_set_pulls(uint gpio, bool up, bool down); + +void gpio_set_outover(uint gpio, uint value); + +void gpio_set_inover(uint gpio, uint value); + +void gpio_set_oeover(uint gpio, uint value); + +void gpio_set_input_enabled(uint gpio, bool enable); + +// Configure a GPIO for direct input/output from software +void gpio_init(uint gpio); + +void gpio_init_mask(uint gpio_mask); + +// ---------------------------------------------------------------------------- +// Input +// ---------------------------------------------------------------------------- + +// Get the value of a single GPIO +bool gpio_get(uint gpio); + +// Get raw value of all +uint32_t gpio_get_all(); + +// ---------------------------------------------------------------------------- +// Output +// ---------------------------------------------------------------------------- + +// Drive high every GPIO appearing in mask +void gpio_set_mask(uint32_t mask); + +void gpio_clr_mask(uint32_t mask); + +// Toggle every GPIO appearing in mask +void gpio_xor_mask(uint32_t mask); + + +// For each 1 bit in "mask", drive that pin to the value given by +// corresponding bit in "value", leaving other pins unchanged. +// Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ +// bashing different pins from the same core. +void gpio_put_masked(uint32_t mask, uint32_t value); + +// Drive all pins simultaneously +void gpio_put_all(uint32_t value); + + +// Drive a single GPIO high/low +void gpio_put(uint gpio, int value); + +// ---------------------------------------------------------------------------- +// Direction +// ---------------------------------------------------------------------------- + +// Switch all GPIOs in "mask" to output +void gpio_set_dir_out_masked(uint32_t mask); + +// Switch all GPIOs in "mask" to input +void gpio_set_dir_in_masked(uint32_t mask); + +// For each 1 bit in "mask", switch that pin to the direction given by +// corresponding bit in "value", leaving other pins unchanged. +// E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, +// simultaneously. +void gpio_set_dir_masked(uint32_t mask, uint32_t value); + +// Set direction of all pins simultaneously. +// For each bit in value, +// 1 = out +// 0 = in +void gpio_set_dir_all_bits(uint32_t value); + +// Set a single GPIO to input/output. +// true = out +// 0 = in +void gpio_set_dir(uint gpio, bool out); + +// debugging +#define PICO_DEBUG_PIN_BASE 19u + +// note these two macros may only be used once per compilation unit +#define CU_REGISTER_DEBUG_PINS(p, ...) +#define CU_SELECT_DEBUG_PINS(x) +#define DEBUG_PINS_ENABLED(p) false + +#define DEBUG_PINS_SET(p, v) ((void)0) +#define DEBUG_PINS_CLR(p, v) ((void)0) +#define DEBUG_PINS_XOR(p, v) ((void)0) + +void gpio_debug_pins_init(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/CMakeLists.txt new file mode 100644 index 00000000000..4f6917740e0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/CMakeLists.txt @@ -0,0 +1,12 @@ +pico_simple_hardware_headers_target(sync) + +if (NOT TARGET hardware_sync) + add_library(hardware_sync INTERFACE) + + target_sources(hardware_sync INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/sync_core0_only.c + ) + + target_link_libraries(hardware_sync INTERFACE hardware_sync_headers pico_platform) +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/include/hardware/sync.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/include/hardware/sync.h new file mode 100644 index 00000000000..a27ea01005e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/include/hardware/sync.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_SYNC_H +#define _HARDWARE_SYNC_H + +#include "pico.h" + +#ifndef __cplusplus + +#if (__STDC_VERSION__ >= 201112L) +#include +#else +enum { + memory_order_acquire, memory_order_release +}; +static inline void atomic_thread_fence(uint x) {} +#endif + +#else + +#include + +#endif + +#ifndef PICO_SPINLOCK_ID_TIMER +#define PICO_SPINLOCK_ID_TIMER 10 +#endif + +#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST +#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 +#endif + +#ifndef PICO_SPINLOCK_ID_STRIPED_LAST +#define PICO_SPINLOCK_ID_STRIPED_LAST 23 +#endif + +typedef struct _spin_lock_t spin_lock_t; + +inline static void __mem_fence_acquire() { +#ifndef __cplusplus + atomic_thread_fence(memory_order_acquire); +#else + std::atomic_thread_fence(std::memory_order_acquire); +#endif +} + +inline static void __mem_fence_release() { +#ifndef __cplusplus + atomic_thread_fence(memory_order_release); +#else + std::atomic_thread_fence(std::memory_order_release); +#endif +} + +#ifdef __cplusplus +extern "C" { +#endif + +void __sev(); + +void __wev(); + +void __wfi(); + +void __wfe(); + +uint32_t save_and_disable_interrupts(); + +void restore_interrupts(uint32_t status); + +uint spin_lock_get_num(spin_lock_t *lock); + +spin_lock_t *spin_lock_instance(uint lock_num); + +void spin_lock_unsafe_blocking(spin_lock_t *lock); + +void spin_unlock_unsafe(spin_lock_t *lock); + +uint32_t spin_lock_blocking(spin_lock_t *lock); + +bool is_spin_locked(const spin_lock_t *lock); + +void spin_unlock(spin_lock_t *lock, uint32_t saved_irq); + +uint get_core_num(); + +spin_lock_t *spin_lock_init(uint lock_num); + +void clear_spin_locks(void); + +uint next_striped_spin_lock_num(); + +void spin_lock_claim(uint lock_num); +void spin_lock_claim_mask(uint32_t lock_num_mask); +void spin_lock_unclaim(uint lock_num); +int spin_lock_claim_unused(bool required); +uint spin_lock_num(spin_lock_t *lock); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/sync_core0_only.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/sync_core0_only.c new file mode 100644 index 00000000000..878eba68f84 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_sync/sync_core0_only.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/sync.h" +#include "hardware/platform_defs.h" + +// This is a dummy implementation that is single threaded + +static struct _spin_lock_t { + bool locked; +} _spinlocks[NUM_SPIN_LOCKS]; + +PICO_WEAK_FUNCTION_DEF(save_and_disable_interrupts) + +//static uint8_t striped_spin_lock_num; + +uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(save_and_disable_interrupts)() { + return 0; +} + +PICO_WEAK_FUNCTION_DEF(restore_interrupts) + +void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts)(uint32_t status) { +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_instance) + +spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_instance)(uint lock_num) { + assert(lock_num < NUM_SPIN_LOCKS); + return &_spinlocks[lock_num]; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_get_num) + +uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_get_num)(spin_lock_t *lock) { + return lock - _spinlocks; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_init) + +spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_init)(uint lock_num) { + spin_lock_t *lock = spin_lock_instance(lock_num); + spin_unlock_unsafe(lock); + return lock; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_unsafe_blocking) + +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unsafe_blocking)(spin_lock_t *lock) { + lock->locked = true; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_blocking) + +uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_blocking)(spin_lock_t *lock) { + spin_lock_unsafe_blocking(lock); + return 1; // todo wrong value +} + +PICO_WEAK_FUNCTION_DEF(is_spin_locked) + +bool PICO_WEAK_FUNCTION_IMPL_NAME(is_spin_locked)(const spin_lock_t *lock) { + return lock->locked; +} + +PICO_WEAK_FUNCTION_DEF(spin_unlock_unsafe) + +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock_unsafe)(spin_lock_t *lock) { + lock->locked = false; +} + +PICO_WEAK_FUNCTION_DEF(spin_unlock) + +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock)(spin_lock_t *lock, uint32_t saved_irq) { + spin_unlock_unsafe(lock); +} + +PICO_WEAK_FUNCTION_DEF(__sev) + +volatile bool event_fired; + +void PICO_WEAK_FUNCTION_IMPL_NAME(__sev)() { + event_fired = true; +} + +PICO_WEAK_FUNCTION_DEF(__wfi) + +void PICO_WEAK_FUNCTION_IMPL_NAME(__wfi)() { + panic("Can't wait on irq for host core0 only implementation"); +} + +PICO_WEAK_FUNCTION_DEF(__wfe) + +void PICO_WEAK_FUNCTION_IMPL_NAME(__wfe)() { + while (!event_fired) tight_loop_contents(); +} + +PICO_WEAK_FUNCTION_DEF(get_core_num) + +uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() { + return 0; +} + +PICO_WEAK_FUNCTION_DEF(clear_spin_locks) + +void PICO_WEAK_FUNCTION_IMPL_NAME(clear_spin_locks)(void) { + for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { + spin_unlock_unsafe(spin_lock_instance(i)); + } +} + +PICO_WEAK_FUNCTION_DEF(next_striped_spin_lock_num) +uint PICO_WEAK_FUNCTION_IMPL_NAME(next_striped_spin_lock_num)() { + return 0; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_claim) +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim)(uint lock_num) { +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_claim_mask) +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_mask)(uint32_t mask) { +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_unclaim) +void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unclaim)(uint lock_num) { +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_claim_unused) +int PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_unused)(bool required) { + return 0; +} + +PICO_WEAK_FUNCTION_DEF(spin_lock_num) +uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_num)(spin_lock_t *lock) { + return 0; +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/CMakeLists.txt new file mode 100644 index 00000000000..ba00444ae3f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/CMakeLists.txt @@ -0,0 +1,16 @@ +pico_simple_hardware_target(timer) + +target_compile_definitions(hardware_timer INTERFACE + PICO_HARDWARE_TIMER_RESOLUTION_US=1000 # to loosen tests a little +) + +if (NOT DEFINED PICO_TIME_NO_ALARM_SUPPORT) + # we don't have alarm pools in the basic host support, though pico_host_sdl adds it + set(PICO_TIME_NO_ALARM_SUPPORT "1" CACHE INTERNAL "") +endif() + +if (PICO_TIME_NO_ALARM_SUPPORT) + target_compile_definitions(hardware_timer INTERFACE + PICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1 + ) +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/include/hardware/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/include/hardware/timer.h new file mode 100644 index 00000000000..3ddf427a668 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/include/hardware/timer.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_TIMER_H +#define _HARDWARE_TIMER_H + +#include "pico.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef PARAM_ASSERTIONS_ENABLED_TIMER +#define PARAM_ASSERTIONS_ENABLED_TIMER 0 +#endif + +static inline void check_hardware_alarm_num_param(uint alarm_num) { + invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); +} + +uint32_t time_us_32(); +uint64_t time_us_64(); +void busy_wait_us_32(uint32_t delay_us); +void busy_wait_us(uint64_t delay_us); +void busy_wait_until(absolute_time_t t); +bool time_reached(absolute_time_t t); +typedef void (*hardware_alarm_callback_t)(uint alarm_num); +void hardware_alarm_claim(uint alarm_num); +void hardware_alarm_unclaim(uint alarm_num); +void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); +bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); +void hardware_alarm_cancel(uint alarm_num); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c new file mode 100644 index 00000000000..d6dfa1cee2c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/timer.h" +#if defined(__unix__) || defined(__APPLE__) +#include +#include +#include + +#endif + +// in our case not a busy wait +PICO_WEAK_FUNCTION_DEF(busy_wait_us) +void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us_32)(uint32_t delay_us) { +#if defined(__unix__) || defined(__APPLE__) + usleep(delay_us); +#else + assert(false); +#endif +} +PICO_WEAK_FUNCTION_DEF(busy_wait_us) +void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us)(uint64_t delay_us) { + absolute_time_t t; + update_us_since_boot(&t, time_us_64() + delay_us); + busy_wait_until(t); +} + +// this may or may not wrap +PICO_WEAK_FUNCTION_DEF(time_us_64) +uint64_t PICO_WEAK_FUNCTION_IMPL_NAME(time_us_64)() { +#if defined(__unix__) || defined(__APPLE__) +// struct timeval tv; +// gettimeofday(&tv, NULL); +// return tv.tv_sec * (uint64_t) 1000000 + tv.tv_usec; + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return ts.tv_sec * (uint64_t) 1000000 + ts.tv_nsec / 1000; +#else + panic_unsupported(); +#endif +} + +PICO_WEAK_FUNCTION_DEF(timer_us_32) +uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() { + return (uint32_t) time_us_64(); +} + +PICO_WEAK_FUNCTION_DEF(time_reached) +bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) { + uint64_t target = to_us_since_boot(t); + if (target > 0xffffffffu) return false; + return time_us_64() >= target; +} + +PICO_WEAK_FUNCTION_DEF(busy_wait_until) +void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) { +#if defined(__unix__) + struct timespec tspec; + tspec.tv_sec = to_us_since_boot(target) / 1000000; + tspec.tv_nsec = (to_us_since_boot(target) % 1000000) * 1000; + clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &tspec, NULL); +#else + const int chunk = 1u<<30u; + uint64_t target_us = to_us_since_boot(target); + uint64_t time_us = time_us_64(); + while (target_us - time_us >= chunk) { + busy_wait_us_32(chunk); + time_us = time_us_64(); + } + if (target_us != time_us) { + busy_wait_us_32(target_us - chunk); + } +#endif +} + +static uint8_t claimed_alarms; + +void hardware_alarm_claim(uint alarm_num) { + assert(!(claimed_alarms & (1u << alarm_num))); + claimed_alarms |= 1u < +#include "hardware/uart.h" + +#if defined(__unix) || defined(__APPLE__) +#define _XOPEN_SOURCE 600 /* for ONLCR */ +#define __BSD_VISIBLE 1 /* for ONLCR in *BSD */ + +#include +#include +#include +#include + +#ifndef FNONBLOCK +#define FNONBLOCK O_NONBLOCK +#endif + +struct termios _tty; +static tcflag_t _res_oflg = 0; +static tcflag_t _res_lflg = 0; + +void _resetty(void) { + if (!isatty(STDIN_FILENO)) + return; + + /* reset tty: */ + _tty.c_oflag = _res_oflg; + _tty.c_lflag = _res_lflg; + tcsetattr(STDIN_FILENO, TCSADRAIN, &_tty); +} + +void _inittty(void) { + if (!isatty(STDIN_FILENO)) + return; + + /* save tty: */ + tcgetattr(STDIN_FILENO, &_tty); + _res_oflg = _tty.c_oflag; + _res_lflg = _tty.c_lflag; + + /* set raw: */ + _tty.c_lflag &= ~(ICANON | ICRNL);// | ISIG); + //_tty.c_oflag &= ~ONLCR; + tcsetattr(STDIN_FILENO, TCSANOW, &_tty); + + fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK); + atexit(_resetty); +} + +#else +void _inittty() {} +#endif + +typedef struct { + bool dummy; +} uart_hw_t; + +uart_inst_t *const uart0; +uart_inst_t *const uart1; + +static int _nextchar = EOF; + +static bool _peekchar() { + if (_nextchar == EOF) { + _nextchar = getchar(); + } + return _nextchar != EOF; +} + +uint uart_init(uart_inst_t *uart, uint baud_rate) { + _inittty(); + return baud_rate; +} + +size_t uart_is_writable(uart_inst_t *uart) { + return 1; +} + +// If returns 0, no data is available to be read from UART. +// If returns nonzero, at least that many bytes can be written without blocking. +size_t uart_is_readable(uart_inst_t *uart) { + return _peekchar() ? 1 : 0; +} + +// Write len bytes directly from src to the UART +//void uart_write_blocking(uart_inst_t uart, const uint8_t *src, size_t len); + +// Read len bytes directly from the UART to dst +//void uart_read_blocking(uart_inst_t uart, uint8_t *dst, size_t len); + +// ---------------------------------------------------------------------------- +// UART-specific operations and aliases + +void uart_putc(uart_inst_t *uart, char c) { + putchar(c); +} + +void uart_puts(uart_inst_t *uart, const char *s) { + puts(s); +} + +char uart_getc(uart_inst_t *uart) { + while (!_peekchar()) { + tight_loop_contents(); + } + char rc = (char) _nextchar; + _nextchar = EOF; + return rc; +} + +void uart_default_tx_wait_blocking() { + +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt new file mode 100644 index 00000000000..e4f88292287 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt @@ -0,0 +1,9 @@ +add_library(pico_bit_ops INTERFACE) + +target_sources(pico_bit_ops INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/bit_ops.c) + +target_link_libraries(pico_bit_ops INTERFACE pico_bit_ops_headers) + +macro(pico_set_bit_ops_implementation TARGET IMPL) +endmacro() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/bit_ops.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/bit_ops.c new file mode 100644 index 00000000000..11f69fe6366 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/bit_ops.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/bit_ops.h" + +uint32_t __rev(uint32_t v) { + v = ((v & 0x55555555u) << 1u) | ((v >> 1u) & 0x55555555u); + v = ((v & 0x33333333u) << 2u) | ((v >> 2u) & 0x33333333u); + v = ((v & 0x0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0fu); + return (v << 24u) | ((v & 0xff00u) << 8u) | ((v >> 8u) & 0xff00u) | (v >> 24u); +} + +uint64_t __revll(uint64_t v) { + v = ((v & 0x5555555555555555u) << 1u) | ((v >> 1u) & 0x5555555555555555u); + v = ((v & 0x3333333333333333u) << 2u) | ((v >> 2u) & 0x3333333333333333u); + v = ((v & 0x0f0f0f0f0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0f0f0f0f0fu); + v = ((v & 0x00ff00ff00ff00ffu) << 8u) | ((v >> 8u) & 0x00ff00ff00ff00ffu); + return (v << 48u) | ((v & 0xffff0000u) << 16u) | ((v >> 16u) & 0xffff0000u) | (v >> 48u); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt new file mode 100644 index 00000000000..7a26204c2d4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt @@ -0,0 +1,9 @@ +add_library(pico_divider INTERFACE) + +target_sources(pico_divider INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/divider.c) + +target_link_libraries(pico_divider INTERFACE pico_divider_headers) + +macro(pico_set_divider_implementation TARGET IMPL) +endmacro() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/divider.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/divider.c new file mode 100644 index 00000000000..df0e275171e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/divider.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/divider.h" + +// These functions save/restore divider state, so are safe to call from interrupts +int32_t div_s32s32(int32_t a, int32_t b) { + return hw_divider_s32_quotient(a, b); +} + +divmod_result_t divmod_s32s32(int32_t a, int32_t b) { + return hw_divider_divmod_s32(a, b); +} + +uint32_t div_u32u32(uint32_t a, uint32_t b) { + return hw_divider_u32_quotient(a, b); +} + +divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) { + return hw_divider_divmod_u32(a, b); +} + +static inline int __sign_of_64(int32_t v) { + return v > 0 ? 1 : (v < 0 ? -1 : 0); +} + +typedef struct { + uint64_t quotient; + uint64_t remainder; +} qr_u64; + +typedef struct { + int64_t quotient; + int64_t remainder; +} qr_s64; + +// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline qr_u64 udiv64(uint64_t a, uint64_t b) { + qr_u64 rc; + if (!b) { + rc.quotient = (uint64_t)-1; // todo check this + rc.remainder = a; + } else { + rc.quotient = a/b; + rc.remainder = a%b; + } + return rc; +} + +// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline qr_s64 div64(int64_t a, int64_t b) { + qr_s64 rc; + if (!b) { + rc.quotient = (uint64_t)(-__sign_of_64(a)); + rc.remainder = a; + } else { + rc.quotient = a/b; + rc.remainder = a%b; + } + return rc; +} + +int64_t div_s64s64(int64_t a, int64_t b) { + qr_s64 qr = div64(a, b); + return qr.quotient; +} + +int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) { + qr_s64 qr = div64(a, b); + *rem = qr.remainder; + return qr.quotient; +} + +int64_t divmod_s64s64(int64_t a, int64_t b) { + qr_s64 qr = div64(a, b); + return qr.quotient; +} + +uint64_t div_u64u64(uint64_t a, uint64_t b) { + qr_u64 qr = udiv64(a, b); + return qr.quotient; +} + +uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) { + qr_u64 qr = udiv64(a, b); + *rem = qr.remainder; + return qr.quotient; +} + +uint64_t divmod_u64u64(uint64_t a, uint64_t b) { + qr_u64 qr = udiv64(a, b); + return qr.quotient; +} + +// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts + +int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); } +int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); } +int64_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } + +uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); } +uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); } +uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); } + +int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); } +int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); } +int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); } + +uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); } +uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); } +uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt new file mode 100644 index 00000000000..c5eabdab2be --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt @@ -0,0 +1,8 @@ +if (NOT TARGET pico_multicore) + add_library(pico_multicore INTERFACE) + + target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +endif() + + + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h new file mode 100644 index 00000000000..de6672ae278 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_MULTICORE_H +#define _PICO_MULTICORE_H + +#include "pico/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void multicore_reset_core1(); +void multicore_launch_core1(void (*entry)(void)); +void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); +void multicore_sleep_core1(); +void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); + +bool multicore_fifo_rvalid(); +bool multicore_fifo_wready(); +void multicore_fifo_push(uint32_t data); +uint32_t multicore_fifo_pop_blocking(); +void multicore_fifo_drain(); +void multicore_fifo_clear_irq(); +int32_t multicore_fifo_get_status(); + +// call this from the lockout victim thread +void multicore_lockout_victim_init(); + +// start locking out the other core (it will be +bool multicore_lockout_start_timeout_us(uint64_t timeout_us); +void multicore_lockout_start_blocking(); + +bool multicore_lockout_end_timeout_us(uint64_t timeout_us); +void multicore_lockout_end_blocking(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt new file mode 100644 index 00000000000..92ae6a2b703 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt @@ -0,0 +1,25 @@ +if (NOT TARGET pico_platform_headers) + add_library(pico_platform_headers INTERFACE) + + target_compile_definitions(pico_platform_headers INTERFACE + PICO_NO_HARDWARE=1 + PICO_ON_DEVICE=0 + PICO_BUILD=1 + ) + + target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +endif() + +if (NOT TARGET pico_platform) + add_library(pico_platform INTERFACE) + + target_sources(pico_platform INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/platform_base.c + ) + + target_link_libraries(pico_platform INTERFACE pico_platform_headers pico_bit_ops ${PICO_PLATFORM_EXTRA_LIBRARIES}) +endif() + +function(pico_add_platform_library TARGET) + target_link_libraries(pico_platform INTERFACE ${TARGET}) +endfunction() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h new file mode 100644 index 00000000000..1ca575e29b8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +#define NUM_CORES 2u + +#define NUM_DMA_CHANNELS 12u + +#define NUM_TIMERS 4u + +#define NUM_IRQS 32u + +#define NUM_SPIN_LOCKS 32u + +#define XOSC_MHZ 12 + +#define NUM_SPIN_LOCKS 32u + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h new file mode 100644 index 00000000000..0e994d9b480 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_H_ +#define _PICO_PLATFORM_H_ + +#include "hardware/platform_defs.h" +#include + +#ifdef __unix__ + +#include + +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define __not_in_flash(grup) +#define __not_in_flash_func(func) func +#define __no_inline_not_in_flash_func(func) +#define __in_flash(group) +#define __scratch_x(group) +#define __scratch_y(group) + +#define __packed_aligned +#define __packed + +#define __time_critical_func(x) x +#define __after_data(group) + +//int running_on_fpga() { return false; } +extern void tight_loop_contents(); + +#ifndef _MSC_VER +#ifndef __noreturn +#define __noreturn __attribute((noreturn)) +#endif + +#ifndef __unused +#define __unused __attribute__((unused)) +#endif + +#ifndef __noinline +#define __noinline __attribute__((noinline)) +#endif + +#ifndef __aligned +#define __aligned(x) __attribute__((aligned(x))) +#endif + +#define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x)) +#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x + +#else +#ifndef __noreturn +#define __noreturn __declspec(noreturn) +#endif + +#ifndef __unused +#define __unused +#endif + +#ifndef __noinline +#define __noinline __declspec(noinline) +#endif + +#ifndef __aligned +#define __aligned(x) __declspec(align(x)) +#endif + +#ifndef __CONCAT +#define __CONCAT(x,y) x ## y +#endif + +#ifndef __STRING +#define __STRING(x) #x +#endif() + +#define __thread __declspec( thread ) + +#define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak))); +#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x ## __weak + +static __noreturn void __builtin_unreachable() { +} + +#include +#define __builtin_clz __lzcnt +#endif + +#ifndef count_of +#define count_of(a) (sizeof(a)/sizeof((a)[0])) +#endif + +#ifndef MAX +#define MAX(a, b) ((a)>(b)?(a):(b)) +#endif + +#ifndef MIN +#define MIN(a, b) ((b)>(a)?(a):(b)) +#endif + +// abort in our case +void __noreturn __breakpoint(); + +void __noreturn panic_unsupported(); + +void __noreturn panic(const char *fmt, ...); + +// arggggghhhh there is a weak function called sem_init used by SDL +#define sem_init sem_init_alternative + +extern uint32_t host_safe_hw_ptr_impl(uintptr_t x); +// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values +// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore +// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode +#define host_safe_hw_ptr(x) host_safe_hw_ptr_impl((uintptr_t)(x)) +void *decode_host_safe_hw_ptr(uint32_t ptr); + +#define __fast_mul(a,b) ((a)*(b)) + +typedef unsigned int uint; + +inline static int32_t __mul_instruction(int32_t a,int32_t b) +{ + return a*b; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/platform_base.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/platform_base.c new file mode 100644 index 00000000000..be1dbd444ac --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/platform_base.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include + +#include "pico.h" + +PICO_WEAK_FUNCTION_DEF(tight_loop_contents) + +void PICO_WEAK_FUNCTION_IMPL_NAME(tight_loop_contents)() { + +} + +void __noreturn panic_unsupported() { + panic("not supported"); +} + +void hard_assertion_failure(void) { + panic("Hard assert"); +} + +void panic(const char *fmt, ...) { + va_list args; + + puts("*** PANIC ***\n"); + if (fmt) { + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); + } + + puts("\n"); + + __breakpoint(); +} + +void __breakpoint() { + #ifdef _MSC_VER + __debugbreak(); + #else + __builtin_trap(); + #endif +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt new file mode 100644 index 00000000000..2151746d73c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt @@ -0,0 +1,6 @@ +if (NOT TARGET pico_printf) + add_library(pico_printf INTERFACE) + function(pico_set_printf_implementation) + endfunction() +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt new file mode 100644 index 00000000000..8ab5ed466d4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt @@ -0,0 +1,20 @@ +if (NOT TARGET pico_stdio) + add_library(pico_stdio INTERFACE) + + target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_sources(pico_stdio INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/stdio.c + ) + add_library(pico_stdio_usb INTERFACE) + add_library(pico_stdio_uart INTERFACE) + add_library(pico_stdio_semihosting INTERFACE) + + function(pico_enable_stdio_uart) + endfunction() + function(pico_enable_stdio_usb) + endfunction() + function(pico_enable_stdio_semihosting) + endfunction() +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h new file mode 100644 index 00000000000..798edb3a171 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _PICO_STDIO_H +#define _PICO_STDIO_H + +typedef struct stdio_driver stdio_driver_t; + +#define STDIO_ERROR -1 +#define STDIO_NO_INPUT -2 + +static inline void stdio_usb_init() {} +void stdio_uart_init(); +static inline void stdio_init_all() { stdio_uart_init(); } +static inline void stdio_filter_driver(stdio_driver_t *); +static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {} +int getchar_timeout_us(uint32_t timeout_us); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/stdio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/stdio.c new file mode 100644 index 00000000000..87be91da3e6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/stdio.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/stdlib.h" +#include "hardware/uart.h" + +int getchar_timeout_us(uint32_t timeout_us) { + absolute_time_t t = make_timeout_time_us(timeout_us); + while (!uart_is_readable(uart_default)) { + if (absolute_time_diff_us(t, get_absolute_time()) > 0) { + return STDIO_NO_INPUT; + } + sleep_ms(1); + } + return uart_getc(uart_default); +} + +void stdio_uart_init() { + uart_init(uart_default, 0); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt new file mode 100644 index 00000000000..f4dac4d8dee --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt @@ -0,0 +1,19 @@ +if (NOT TARGET pico_stdlib) + add_library(pico_stdlib INTERFACE) + + target_sources(pico_stdlib INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/stdlib.c + ) + + target_link_libraries(pico_stdlib INTERFACE + pico_stdlib_headers + pico_platform + pico_time + pico_divider + pico_binary_info + pico_printf + pico_stdio + hardware_gpio + ) +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/stdlib.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/stdlib.c new file mode 100644 index 00000000000..166bd5fed23 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/stdlib.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/stdlib.h" + +void setup_default_uart() { + +} + +void set_sys_clock_48mhz() { + +} + +bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { + *vco_out = 1000000; + *postdiv1_out = 0; + *postdiv2_out = 0; + return true; +} + +void set_sys_clock_pll(__unused uint32_t vco_freq, __unused uint post_div1, __unused uint post_div2) { + +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040.cmake new file mode 100644 index 00000000000..c68df450a49 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040.cmake @@ -0,0 +1,6 @@ +# include everything needed to build against rp2040 + +include(rp2_common.cmake) + +add_subdirectory(rp2040) + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt new file mode 100644 index 00000000000..a6089de0646 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt @@ -0,0 +1,6 @@ +# Targets specific to B0 silicon +pico_add_subdirectory(hardware_regs) +pico_add_subdirectory(hardware_structs) + +pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) +pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/README.md b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/README.md new file mode 100644 index 00000000000..b705b35a9ac --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/README.md @@ -0,0 +1,7 @@ +This directory contains header files defining the RP2040 hardware. It is selected when +`PICO_PLATFORM=rp2040` (the default) is specified for the build + +`hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself. + +`hardware_structs` contains C structures for accessing memory mapped registers + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/CMakeLists.txt new file mode 100644 index 00000000000..46358cabec6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/CMakeLists.txt @@ -0,0 +1,3 @@ +add_library(hardware_regs INTERFACE) +target_include_directories(hardware_regs INTERFACE include) +target_link_libraries(hardware_regs INTERFACE hardware_base) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h new file mode 100644 index 00000000000..51c027222df --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +// This header is included from C and assembler - only define macros + +#include "hardware/regs/addressmap.h" + +#define NUM_CORES 2u +#define NUM_DMA_CHANNELS 12u +#define NUM_IRQS 32u +#define NUM_PIOS 2u +#define NUM_PIO_STATE_MACHINES 4u +#define NUM_PWM_SLICES 8u +#define NUM_SPIN_LOCKS 32u +#define NUM_UARTS 2u +#define NUM_BANK0_GPIOS 30u + +#define PIO_INSTRUCTION_COUNT 32u + +#define XOSC_MHZ 12u + +// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE 0x800u +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE 0x800 +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +#endif + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h new file mode 100644 index 00000000000..82bb0f8fb69 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h @@ -0,0 +1,314 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ADC +// Version : 2 +// Bus type : apb +// Description : Control and data interface to SAR ADC +// ============================================================================= +#ifndef HARDWARE_REGS_ADC_DEFINED +#define HARDWARE_REGS_ADC_DEFINED +// ============================================================================= +// Register : ADC_CS +// Description : ADC Control and Status +#define ADC_CS_OFFSET 0x00000000 +#define ADC_CS_BITS 0x001f770f +#define ADC_CS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_CS_RROBIN +// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to +// disable. +// Otherwise, the ADC will cycle through each enabled channel in a +// round-robin fashion. +// The first channel to be sampled will be the one currently +// indicated by AINSEL. +// AINSEL will be updated after each conversion with the +// newly-selected channel. +#define ADC_CS_RROBIN_RESET 0x00 +#define ADC_CS_RROBIN_BITS 0x001f0000 +#define ADC_CS_RROBIN_MSB 20 +#define ADC_CS_RROBIN_LSB 16 +#define ADC_CS_RROBIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_AINSEL +// Description : Select analog mux input. Updated automatically in round-robin +// mode. +#define ADC_CS_AINSEL_RESET 0x0 +#define ADC_CS_AINSEL_BITS 0x00007000 +#define ADC_CS_AINSEL_MSB 14 +#define ADC_CS_AINSEL_LSB 12 +#define ADC_CS_AINSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR_STICKY +// Description : Some past ADC conversion encountered an error. Write 1 to +// clear. +#define ADC_CS_ERR_STICKY_RESET 0x0 +#define ADC_CS_ERR_STICKY_BITS 0x00000400 +#define ADC_CS_ERR_STICKY_MSB 10 +#define ADC_CS_ERR_STICKY_LSB 10 +#define ADC_CS_ERR_STICKY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR +// Description : The most recent ADC conversion encountered an error; result is +// undefined or noisy. +#define ADC_CS_ERR_RESET 0x0 +#define ADC_CS_ERR_BITS 0x00000200 +#define ADC_CS_ERR_MSB 9 +#define ADC_CS_ERR_LSB 9 +#define ADC_CS_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_READY +// Description : 1 if the ADC is ready to start a new conversion. Implies any +// previous conversion has completed. +// 0 whilst conversion in progress. +#define ADC_CS_READY_RESET 0x0 +#define ADC_CS_READY_BITS 0x00000100 +#define ADC_CS_READY_MSB 8 +#define ADC_CS_READY_LSB 8 +#define ADC_CS_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_MANY +// Description : Continuously perform conversions whilst this bit is 1. A new +// conversion will start immediately after the previous finishes. +#define ADC_CS_START_MANY_RESET 0x0 +#define ADC_CS_START_MANY_BITS 0x00000008 +#define ADC_CS_START_MANY_MSB 3 +#define ADC_CS_START_MANY_LSB 3 +#define ADC_CS_START_MANY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_ONCE +// Description : Start a single conversion. Self-clearing. Ignored if start_many +// is asserted. +#define ADC_CS_START_ONCE_RESET 0x0 +#define ADC_CS_START_ONCE_BITS 0x00000004 +#define ADC_CS_START_ONCE_MSB 2 +#define ADC_CS_START_ONCE_LSB 2 +#define ADC_CS_START_ONCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_TS_EN +// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. +#define ADC_CS_TS_EN_RESET 0x0 +#define ADC_CS_TS_EN_BITS 0x00000002 +#define ADC_CS_TS_EN_MSB 1 +#define ADC_CS_TS_EN_LSB 1 +#define ADC_CS_TS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_EN +// Description : Power on ADC and enable its clock. +// 1 - enabled. 0 - disabled. +#define ADC_CS_EN_RESET 0x0 +#define ADC_CS_EN_BITS 0x00000001 +#define ADC_CS_EN_MSB 0 +#define ADC_CS_EN_LSB 0 +#define ADC_CS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_RESULT +// Description : Result of most recent ADC conversion +#define ADC_RESULT_OFFSET 0x00000004 +#define ADC_RESULT_BITS 0x00000fff +#define ADC_RESULT_RESET 0x00000000 +#define ADC_RESULT_MSB 11 +#define ADC_RESULT_LSB 0 +#define ADC_RESULT_ACCESS "RO" +// ============================================================================= +// Register : ADC_FCS +// Description : FIFO control and status +#define ADC_FCS_OFFSET 0x00000008 +#define ADC_FCS_BITS 0x0f0f0f0f +#define ADC_FCS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_THRESH +// Description : DREQ/IRQ asserted when level >= threshold +#define ADC_FCS_THRESH_RESET 0x0 +#define ADC_FCS_THRESH_BITS 0x0f000000 +#define ADC_FCS_THRESH_MSB 27 +#define ADC_FCS_THRESH_LSB 24 +#define ADC_FCS_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_LEVEL +// Description : The number of conversion results currently waiting in the FIFO +#define ADC_FCS_LEVEL_RESET 0x0 +#define ADC_FCS_LEVEL_BITS 0x000f0000 +#define ADC_FCS_LEVEL_MSB 19 +#define ADC_FCS_LEVEL_LSB 16 +#define ADC_FCS_LEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_OVER +// Description : 1 if the FIFO has been overflowed. Write 1 to clear. +#define ADC_FCS_OVER_RESET 0x0 +#define ADC_FCS_OVER_BITS 0x00000800 +#define ADC_FCS_OVER_MSB 11 +#define ADC_FCS_OVER_LSB 11 +#define ADC_FCS_OVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_UNDER +// Description : 1 if the FIFO has been underflowed. Write 1 to clear. +#define ADC_FCS_UNDER_RESET 0x0 +#define ADC_FCS_UNDER_BITS 0x00000400 +#define ADC_FCS_UNDER_MSB 10 +#define ADC_FCS_UNDER_LSB 10 +#define ADC_FCS_UNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_FULL +// Description : None +#define ADC_FCS_FULL_RESET 0x0 +#define ADC_FCS_FULL_BITS 0x00000200 +#define ADC_FCS_FULL_MSB 9 +#define ADC_FCS_FULL_LSB 9 +#define ADC_FCS_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EMPTY +// Description : None +#define ADC_FCS_EMPTY_RESET 0x0 +#define ADC_FCS_EMPTY_BITS 0x00000100 +#define ADC_FCS_EMPTY_MSB 8 +#define ADC_FCS_EMPTY_LSB 8 +#define ADC_FCS_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_DREQ_EN +// Description : If 1: assert DMA requests when FIFO contains data +#define ADC_FCS_DREQ_EN_RESET 0x0 +#define ADC_FCS_DREQ_EN_BITS 0x00000008 +#define ADC_FCS_DREQ_EN_MSB 3 +#define ADC_FCS_DREQ_EN_LSB 3 +#define ADC_FCS_DREQ_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_ERR +// Description : If 1: conversion error bit appears in the FIFO alongside the +// result +#define ADC_FCS_ERR_RESET 0x0 +#define ADC_FCS_ERR_BITS 0x00000004 +#define ADC_FCS_ERR_MSB 2 +#define ADC_FCS_ERR_LSB 2 +#define ADC_FCS_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_SHIFT +// Description : If 1: FIFO results are right-shifted to be one byte in size. +// Enables DMA to byte buffers. +#define ADC_FCS_SHIFT_RESET 0x0 +#define ADC_FCS_SHIFT_BITS 0x00000002 +#define ADC_FCS_SHIFT_MSB 1 +#define ADC_FCS_SHIFT_LSB 1 +#define ADC_FCS_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EN +// Description : If 1: write result to the FIFO after each conversion. +#define ADC_FCS_EN_RESET 0x0 +#define ADC_FCS_EN_BITS 0x00000001 +#define ADC_FCS_EN_MSB 0 +#define ADC_FCS_EN_LSB 0 +#define ADC_FCS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_FIFO +// Description : Conversion result FIFO +#define ADC_FIFO_OFFSET 0x0000000c +#define ADC_FIFO_BITS 0x00008fff +#define ADC_FIFO_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_ERR +// Description : 1 if this particular sample experienced a conversion error. +// Remains in the same location if the sample is shifted. +#define ADC_FIFO_ERR_RESET "-" +#define ADC_FIFO_ERR_BITS 0x00008000 +#define ADC_FIFO_ERR_MSB 15 +#define ADC_FIFO_ERR_LSB 15 +#define ADC_FIFO_ERR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_VAL +// Description : None +#define ADC_FIFO_VAL_RESET "-" +#define ADC_FIFO_VAL_BITS 0x00000fff +#define ADC_FIFO_VAL_MSB 11 +#define ADC_FIFO_VAL_LSB 0 +#define ADC_FIFO_VAL_ACCESS "RF" +// ============================================================================= +// Register : ADC_DIV +// Description : Clock divider. If non-zero, CS_START_MANY will start +// conversions +// at regular intervals rather than back-to-back. +// The divider is reset when either of these fields are written. +// Total period is 1 + INT + FRAC / 256 +#define ADC_DIV_OFFSET 0x00000010 +#define ADC_DIV_BITS 0x00ffffff +#define ADC_DIV_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_INT +// Description : Integer part of clock divisor. +#define ADC_DIV_INT_RESET 0x0000 +#define ADC_DIV_INT_BITS 0x00ffff00 +#define ADC_DIV_INT_MSB 23 +#define ADC_DIV_INT_LSB 8 +#define ADC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_FRAC +// Description : Fractional part of clock divisor. First-order delta-sigma. +#define ADC_DIV_FRAC_RESET 0x00 +#define ADC_DIV_FRAC_BITS 0x000000ff +#define ADC_DIV_FRAC_MSB 7 +#define ADC_DIV_FRAC_LSB 0 +#define ADC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTR +// Description : Raw Interrupts +#define ADC_INTR_OFFSET 0x00000014 +#define ADC_INTR_BITS 0x00000001 +#define ADC_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTR_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTR_FIFO_RESET 0x0 +#define ADC_INTR_FIFO_BITS 0x00000001 +#define ADC_INTR_FIFO_MSB 0 +#define ADC_INTR_FIFO_LSB 0 +#define ADC_INTR_FIFO_ACCESS "RO" +// ============================================================================= +// Register : ADC_INTE +// Description : Interrupt Enable +#define ADC_INTE_OFFSET 0x00000018 +#define ADC_INTE_BITS 0x00000001 +#define ADC_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTE_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTE_FIFO_RESET 0x0 +#define ADC_INTE_FIFO_BITS 0x00000001 +#define ADC_INTE_FIFO_MSB 0 +#define ADC_INTE_FIFO_LSB 0 +#define ADC_INTE_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTF +// Description : Interrupt Force +#define ADC_INTF_OFFSET 0x0000001c +#define ADC_INTF_BITS 0x00000001 +#define ADC_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTF_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTF_FIFO_RESET 0x0 +#define ADC_INTF_FIFO_BITS 0x00000001 +#define ADC_INTF_FIFO_MSB 0 +#define ADC_INTF_FIFO_LSB 0 +#define ADC_INTF_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTS +// Description : Interrupt status after masking & forcing +#define ADC_INTS_OFFSET 0x00000020 +#define ADC_INTS_BITS 0x00000001 +#define ADC_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTS_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTS_FIFO_RESET 0x0 +#define ADC_INTS_FIFO_BITS 0x00000001 +#define ADC_INTS_FIFO_MSB 0 +#define ADC_INTS_FIFO_LSB 0 +#define ADC_INTS_FIFO_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_ADC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h new file mode 100644 index 00000000000..39451ac22ce --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h @@ -0,0 +1,72 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _ADDRESSMAP_H_ +#define _ADDRESSMAP_H_ + +// Register address offsets for atomic RMW aliases +#define REG_ALIAS_RW_BITS (0x0u << 12u) +#define REG_ALIAS_XOR_BITS (0x1u << 12u) +#define REG_ALIAS_SET_BITS (0x2u << 12u) +#define REG_ALIAS_CLR_BITS (0x3u << 12u) + +#define ROM_BASE 0x00000000 +#define XIP_BASE 0x10000000 +#define XIP_MAIN_BASE 0x10000000 +#define XIP_NOALLOC_BASE 0x11000000 +#define XIP_NOCACHE_BASE 0x12000000 +#define XIP_NOCACHE_NOALLOC_BASE 0x13000000 +#define XIP_CTRL_BASE 0x14000000 +#define XIP_SRAM_BASE 0x15000000 +#define XIP_SRAM_END 0x15004000 +#define XIP_SSI_BASE 0x18000000 +#define SRAM_BASE 0x20000000 +#define SRAM_STRIPED_BASE 0x20000000 +#define SRAM_STRIPED_END 0x20040000 +#define SRAM4_BASE 0x20040000 +#define SRAM5_BASE 0x20041000 +#define SRAM_END 0x20042000 +#define SRAM0_BASE 0x21000000 +#define SRAM1_BASE 0x21010000 +#define SRAM2_BASE 0x21020000 +#define SRAM3_BASE 0x21030000 +#define SYSINFO_BASE 0x40000000 +#define SYSCFG_BASE 0x40004000 +#define CLOCKS_BASE 0x40008000 +#define RESETS_BASE 0x4000c000 +#define PSM_BASE 0x40010000 +#define IO_BANK0_BASE 0x40014000 +#define IO_QSPI_BASE 0x40018000 +#define PADS_BANK0_BASE 0x4001c000 +#define PADS_QSPI_BASE 0x40020000 +#define XOSC_BASE 0x40024000 +#define PLL_SYS_BASE 0x40028000 +#define PLL_USB_BASE 0x4002c000 +#define BUSCTRL_BASE 0x40030000 +#define UART0_BASE 0x40034000 +#define UART1_BASE 0x40038000 +#define SPI0_BASE 0x4003c000 +#define SPI1_BASE 0x40040000 +#define I2C0_BASE 0x40044000 +#define I2C1_BASE 0x40048000 +#define ADC_BASE 0x4004c000 +#define PWM_BASE 0x40050000 +#define TIMER_BASE 0x40054000 +#define WATCHDOG_BASE 0x40058000 +#define RTC_BASE 0x4005c000 +#define ROSC_BASE 0x40060000 +#define VREG_AND_CHIP_RESET_BASE 0x40064000 +#define TBMAN_BASE 0x4006c000 +#define DMA_BASE 0x50000000 +#define USBCTRL_DPRAM_BASE 0x50100000 +#define USBCTRL_BASE 0x50100000 +#define USBCTRL_REGS_BASE 0x50110000 +#define PIO0_BASE 0x50200000 +#define PIO1_BASE 0x50300000 +#define XIP_AUX_BASE 0x50400000 +#define SIO_BASE 0xd0000000 +#define PPB_BASE 0xe0000000 + +#endif // _ADDRESSMAP_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h new file mode 100644 index 00000000000..6c02aee54a1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h @@ -0,0 +1,160 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BUSCTRL +// Version : 1 +// Bus type : apb +// Description : Register block for busfabric control signals and performance +// counters +// ============================================================================= +#ifndef HARDWARE_REGS_BUSCTRL_DEFINED +#define HARDWARE_REGS_BUSCTRL_DEFINED +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY +// Description : Set the priority of each master for bus arbitration. +#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111 +#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_W +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000 +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_R +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100 +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC1 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010 +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC0 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001 +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY_ACK +// Description : Bus priority acknowledge +// Goes to 1 once all arbiters have registered the new global +// priority levels. +// Arbiters update their local priority when servicing a new +// nonsequential access. +// In normal circumstances this will happen almost immediately. +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004 +#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001 +#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" +// ============================================================================= +// Register : BUSCTRL_PERFCTR0 +// Description : Bus fabric performance counter 0 +// Busfabric saturating performance counter 0 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL0 +#define BUSCTRL_PERFCTR0_OFFSET 0x00000008 +#define BUSCTRL_PERFCTR0_BITS 0x00ffffff +#define BUSCTRL_PERFCTR0_RESET 0x00000000 +#define BUSCTRL_PERFCTR0_MSB 23 +#define BUSCTRL_PERFCTR0_LSB 0 +#define BUSCTRL_PERFCTR0_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL0 +// Description : Bus fabric performance event select for PERFCTR0 +// Select a performance event for PERFCTR0 +#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c +#define BUSCTRL_PERFSEL0_BITS 0x0000001f +#define BUSCTRL_PERFSEL0_RESET 0x0000001f +#define BUSCTRL_PERFSEL0_MSB 4 +#define BUSCTRL_PERFSEL0_LSB 0 +#define BUSCTRL_PERFSEL0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR1 +// Description : Bus fabric performance counter 1 +// Busfabric saturating performance counter 1 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL1 +#define BUSCTRL_PERFCTR1_OFFSET 0x00000010 +#define BUSCTRL_PERFCTR1_BITS 0x00ffffff +#define BUSCTRL_PERFCTR1_RESET 0x00000000 +#define BUSCTRL_PERFCTR1_MSB 23 +#define BUSCTRL_PERFCTR1_LSB 0 +#define BUSCTRL_PERFCTR1_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL1 +// Description : Bus fabric performance event select for PERFCTR1 +// Select a performance event for PERFCTR1 +#define BUSCTRL_PERFSEL1_OFFSET 0x00000014 +#define BUSCTRL_PERFSEL1_BITS 0x0000001f +#define BUSCTRL_PERFSEL1_RESET 0x0000001f +#define BUSCTRL_PERFSEL1_MSB 4 +#define BUSCTRL_PERFSEL1_LSB 0 +#define BUSCTRL_PERFSEL1_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR2 +// Description : Bus fabric performance counter 2 +// Busfabric saturating performance counter 2 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL2 +#define BUSCTRL_PERFCTR2_OFFSET 0x00000018 +#define BUSCTRL_PERFCTR2_BITS 0x00ffffff +#define BUSCTRL_PERFCTR2_RESET 0x00000000 +#define BUSCTRL_PERFCTR2_MSB 23 +#define BUSCTRL_PERFCTR2_LSB 0 +#define BUSCTRL_PERFCTR2_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL2 +// Description : Bus fabric performance event select for PERFCTR2 +// Select a performance event for PERFCTR2 +#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c +#define BUSCTRL_PERFSEL2_BITS 0x0000001f +#define BUSCTRL_PERFSEL2_RESET 0x0000001f +#define BUSCTRL_PERFSEL2_MSB 4 +#define BUSCTRL_PERFSEL2_LSB 0 +#define BUSCTRL_PERFSEL2_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR3 +// Description : Bus fabric performance counter 3 +// Busfabric saturating performance counter 3 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL3 +#define BUSCTRL_PERFCTR3_OFFSET 0x00000020 +#define BUSCTRL_PERFCTR3_BITS 0x00ffffff +#define BUSCTRL_PERFCTR3_RESET 0x00000000 +#define BUSCTRL_PERFCTR3_MSB 23 +#define BUSCTRL_PERFCTR3_LSB 0 +#define BUSCTRL_PERFCTR3_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL3 +// Description : Bus fabric performance event select for PERFCTR3 +// Select a performance event for PERFCTR3 +#define BUSCTRL_PERFSEL3_OFFSET 0x00000024 +#define BUSCTRL_PERFSEL3_BITS 0x0000001f +#define BUSCTRL_PERFSEL3_RESET 0x0000001f +#define BUSCTRL_PERFSEL3_MSB 4 +#define BUSCTRL_PERFSEL3_LSB 0 +#define BUSCTRL_PERFSEL3_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_BUSCTRL_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h new file mode 100644 index 00000000000..1b44490f7c6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h @@ -0,0 +1,2359 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CLOCKS +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_CLOCKS_DEFINED +#define HARDWARE_REGS_CLOCKS_DEFINED +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET 0x00000000 +#define CLOCKS_CLK_GPOUT0_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT0_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET 0x00000004 +#define CLOCKS_CLK_GPOUT0_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT0_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET 0x00000008 +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET 0x0000000c +#define CLOCKS_CLK_GPOUT1_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT1_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET 0x00000010 +#define CLOCKS_CLK_GPOUT1_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT1_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET 0x00000014 +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET 0x00000018 +#define CLOCKS_CLK_GPOUT2_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT2_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc_ph +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET 0x0000001c +#define CLOCKS_CLK_GPOUT2_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT2_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET 0x00000020 +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET 0x00000024 +#define CLOCKS_CLK_GPOUT3_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT3_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc_ph +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET 0x00000028 +#define CLOCKS_CLK_GPOUT3_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT3_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET 0x0000002c +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_REF_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_REF_CTRL_OFFSET 0x00000030 +#define CLOCKS_CLK_REF_CTRL_BITS 0x00000063 +#define CLOCKS_CLK_REF_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS 0x00000060 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB 6 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed +// on-the-fly +// 0x0 -> rosc_clksrc_ph +// 0x1 -> clksrc_clk_ref_aux +// 0x2 -> xosc_clksrc +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS 0x00000003 +#define CLOCKS_CLK_REF_CTRL_SRC_MSB 1 +#define CLOCKS_CLK_REF_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH 0x0 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX 0x1 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC 0x2 +// ============================================================================= +// Register : CLOCKS_CLK_REF_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_REF_DIV_OFFSET 0x00000034 +#define CLOCKS_CLK_REF_DIV_BITS 0x00000300 +#define CLOCKS_CLK_REF_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_REF_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_REF_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_REF_DIV_INT_MSB 9 +#define CLOCKS_CLK_REF_DIV_INT_LSB 8 +#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_REF_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_REF_SELECTED_OFFSET 0x00000038 +#define CLOCKS_CLK_REF_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_REF_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_REF_SELECTED_MSB 31 +#define CLOCKS_CLK_REF_SELECTED_LSB 0 +#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_SYS_CTRL_OFFSET 0x0000003c +#define CLOCKS_CLK_SYS_CTRL_BITS 0x000000e1 +#define CLOCKS_CLK_SYS_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_pll_usb +// 0x2 -> rosc_clksrc +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x2 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed +// on-the-fly +// 0x0 -> clk_ref +// 0x1 -> clksrc_clk_sys_aux +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET 0x0 +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS 0x00000001 +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF 0x0 +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX 0x1 +// ============================================================================= +// Register : CLOCKS_CLK_SYS_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_SYS_DIV_OFFSET 0x00000040 +#define CLOCKS_CLK_SYS_DIV_BITS 0xffffffff +#define CLOCKS_CLK_SYS_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_SYS_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_SYS_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_SYS_DIV_INT_MSB 31 +#define CLOCKS_CLK_SYS_DIV_INT_LSB 8 +#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_SYS_SELECTED_OFFSET 0x00000044 +#define CLOCKS_CLK_SYS_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_SYS_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_SYS_SELECTED_MSB 31 +#define CLOCKS_CLK_SYS_SELECTED_LSB 0 +#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_PERI_CTRL_OFFSET 0x00000048 +#define CLOCKS_CLK_PERI_CTRL_BITS 0x00000ce0 +#define CLOCKS_CLK_PERI_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> rosc_clksrc_ph +// 0x4 -> xosc_clksrc +// 0x5 -> clksrc_gpin0 +// 0x6 -> clksrc_gpin1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS 0x0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x2 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x3 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x4 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x6 +// ============================================================================= +// Register : CLOCKS_CLK_PERI_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_PERI_SELECTED_OFFSET 0x00000050 +#define CLOCKS_CLK_PERI_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_PERI_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_PERI_SELECTED_MSB 31 +#define CLOCKS_CLK_PERI_SELECTED_LSB 0 +#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_USB_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_USB_CTRL_OFFSET 0x00000054 +#define CLOCKS_CLK_USB_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_USB_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_USB_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_USB_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_USB_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_USB_DIV_OFFSET 0x00000058 +#define CLOCKS_CLK_USB_DIV_BITS 0x00000300 +#define CLOCKS_CLK_USB_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_USB_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_USB_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_USB_DIV_INT_MSB 9 +#define CLOCKS_CLK_USB_DIV_INT_LSB 8 +#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_USB_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_USB_SELECTED_OFFSET 0x0000005c +#define CLOCKS_CLK_USB_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_USB_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_USB_SELECTED_MSB 31 +#define CLOCKS_CLK_USB_SELECTED_LSB 0 +#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_ADC_CTRL_OFFSET 0x00000060 +#define CLOCKS_CLK_ADC_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_ADC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_ADC_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_ADC_DIV_OFFSET 0x00000064 +#define CLOCKS_CLK_ADC_DIV_BITS 0x00000300 +#define CLOCKS_CLK_ADC_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_ADC_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_ADC_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_ADC_DIV_INT_MSB 9 +#define CLOCKS_CLK_ADC_DIV_INT_LSB 8 +#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_ADC_SELECTED_OFFSET 0x00000068 +#define CLOCKS_CLK_ADC_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_ADC_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_ADC_SELECTED_MSB 31 +#define CLOCKS_CLK_ADC_SELECTED_LSB 0 +#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_RTC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_RTC_CTRL_OFFSET 0x0000006c +#define CLOCKS_CLK_RTC_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_RTC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_RTC_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_RTC_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_RTC_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_RTC_DIV_OFFSET 0x00000070 +#define CLOCKS_CLK_RTC_DIV_BITS 0xffffffff +#define CLOCKS_CLK_RTC_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_RTC_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_RTC_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_RTC_DIV_INT_MSB 31 +#define CLOCKS_CLK_RTC_DIV_INT_LSB 8 +#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_RTC_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_RTC_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_RTC_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_RTC_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_RTC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_RTC_SELECTED_OFFSET 0x00000074 +#define CLOCKS_CLK_RTC_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_RTC_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_RTC_SELECTED_MSB 31 +#define CLOCKS_CLK_RTC_SELECTED_LSB 0 +#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_CTRL +// Description : None +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x00000078 +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS 0x000111ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET 0x000000ff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR +// Description : For clearing the resus after the fault that triggered it has +// been corrected +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS 0x00010000 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE +// Description : Force a resus, for test purposes only +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS 0x00001000 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE +// Description : Enable resus +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS 0x00000100 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT +// Description : This is expressed as a number of clk_ref cycles +// and must be >= 2x clk_ref_freq/min_clk_tst_freq +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET 0xff +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS 0x000000ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB 7 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_STATUS +// Description : None +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x0000007c +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS 0x00000001 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED +// Description : Clock has been resuscitated, correct the error then send +// ctrl_clear=1 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS 0x00000001 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_REF_KHZ +// Description : Reference clock frequency in kHz +#define CLOCKS_FC0_REF_KHZ_OFFSET 0x00000080 +#define CLOCKS_FC0_REF_KHZ_BITS 0x000fffff +#define CLOCKS_FC0_REF_KHZ_RESET 0x00000000 +#define CLOCKS_FC0_REF_KHZ_MSB 19 +#define CLOCKS_FC0_REF_KHZ_LSB 0 +#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MIN_KHZ +// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if +// you are not using the pass/fail flags +#define CLOCKS_FC0_MIN_KHZ_OFFSET 0x00000084 +#define CLOCKS_FC0_MIN_KHZ_BITS 0x01ffffff +#define CLOCKS_FC0_MIN_KHZ_RESET 0x00000000 +#define CLOCKS_FC0_MIN_KHZ_MSB 24 +#define CLOCKS_FC0_MIN_KHZ_LSB 0 +#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MAX_KHZ +// Description : Maximum pass frequency in kHz. This is optional. Set to +// 0x1ffffff if you are not using the pass/fail flags +#define CLOCKS_FC0_MAX_KHZ_OFFSET 0x00000088 +#define CLOCKS_FC0_MAX_KHZ_BITS 0x01ffffff +#define CLOCKS_FC0_MAX_KHZ_RESET 0x01ffffff +#define CLOCKS_FC0_MAX_KHZ_MSB 24 +#define CLOCKS_FC0_MAX_KHZ_LSB 0 +#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_DELAY +// Description : Delays the start of frequency counting to allow the mux to +// settle +// Delay is measured in multiples of the reference clock period +#define CLOCKS_FC0_DELAY_OFFSET 0x0000008c +#define CLOCKS_FC0_DELAY_BITS 0x00000007 +#define CLOCKS_FC0_DELAY_RESET 0x00000001 +#define CLOCKS_FC0_DELAY_MSB 2 +#define CLOCKS_FC0_DELAY_LSB 0 +#define CLOCKS_FC0_DELAY_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_INTERVAL +// Description : The test interval is 0.98us * 2**interval, but let's call it +// 1us * 2**interval +// The default gives a test interval of 250us +#define CLOCKS_FC0_INTERVAL_OFFSET 0x00000090 +#define CLOCKS_FC0_INTERVAL_BITS 0x0000000f +#define CLOCKS_FC0_INTERVAL_RESET 0x00000008 +#define CLOCKS_FC0_INTERVAL_MSB 3 +#define CLOCKS_FC0_INTERVAL_LSB 0 +#define CLOCKS_FC0_INTERVAL_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_SRC +// Description : Clock sent to frequency counter, set to 0 when not required +// Writing to this register initiates the frequency count +// 0x00 -> NULL +// 0x01 -> pll_sys_clksrc_primary +// 0x02 -> pll_usb_clksrc_primary +// 0x03 -> rosc_clksrc +// 0x04 -> rosc_clksrc_ph +// 0x05 -> xosc_clksrc +// 0x06 -> clksrc_gpin0 +// 0x07 -> clksrc_gpin1 +// 0x08 -> clk_ref +// 0x09 -> clk_sys +// 0x0a -> clk_peri +// 0x0b -> clk_usb +// 0x0c -> clk_adc +// 0x0d -> clk_rtc +#define CLOCKS_FC0_SRC_OFFSET 0x00000094 +#define CLOCKS_FC0_SRC_BITS 0x000000ff +#define CLOCKS_FC0_SRC_RESET 0x00000000 +#define CLOCKS_FC0_SRC_MSB 7 +#define CLOCKS_FC0_SRC_LSB 0 +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL 0x00 +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY 0x01 +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY 0x02 +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC 0x03 +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH 0x04 +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC 0x05 +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 0x06 +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 0x07 +#define CLOCKS_FC0_SRC_VALUE_CLK_REF 0x08 +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS 0x09 +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI 0x0a +#define CLOCKS_FC0_SRC_VALUE_CLK_USB 0x0b +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC 0x0c +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC 0x0d +// ============================================================================= +// Register : CLOCKS_FC0_STATUS +// Description : Frequency counter status +#define CLOCKS_FC0_STATUS_OFFSET 0x00000098 +#define CLOCKS_FC0_STATUS_BITS 0x11111111 +#define CLOCKS_FC0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DIED +// Description : Test clock stopped during test +#define CLOCKS_FC0_STATUS_DIED_RESET 0x0 +#define CLOCKS_FC0_STATUS_DIED_BITS 0x10000000 +#define CLOCKS_FC0_STATUS_DIED_MSB 28 +#define CLOCKS_FC0_STATUS_DIED_LSB 28 +#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAST +// Description : Test clock faster than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_FAST_RESET 0x0 +#define CLOCKS_FC0_STATUS_FAST_BITS 0x01000000 +#define CLOCKS_FC0_STATUS_FAST_MSB 24 +#define CLOCKS_FC0_STATUS_FAST_LSB 24 +#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_SLOW +// Description : Test clock slower than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_SLOW_RESET 0x0 +#define CLOCKS_FC0_STATUS_SLOW_BITS 0x00100000 +#define CLOCKS_FC0_STATUS_SLOW_MSB 20 +#define CLOCKS_FC0_STATUS_SLOW_LSB 20 +#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAIL +// Description : Test failed +#define CLOCKS_FC0_STATUS_FAIL_RESET 0x0 +#define CLOCKS_FC0_STATUS_FAIL_BITS 0x00010000 +#define CLOCKS_FC0_STATUS_FAIL_MSB 16 +#define CLOCKS_FC0_STATUS_FAIL_LSB 16 +#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_WAITING +// Description : Waiting for test clock to start +#define CLOCKS_FC0_STATUS_WAITING_RESET 0x0 +#define CLOCKS_FC0_STATUS_WAITING_BITS 0x00001000 +#define CLOCKS_FC0_STATUS_WAITING_MSB 12 +#define CLOCKS_FC0_STATUS_WAITING_LSB 12 +#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_RUNNING +// Description : Test running +#define CLOCKS_FC0_STATUS_RUNNING_RESET 0x0 +#define CLOCKS_FC0_STATUS_RUNNING_BITS 0x00000100 +#define CLOCKS_FC0_STATUS_RUNNING_MSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_LSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DONE +// Description : Test complete +#define CLOCKS_FC0_STATUS_DONE_RESET 0x0 +#define CLOCKS_FC0_STATUS_DONE_BITS 0x00000010 +#define CLOCKS_FC0_STATUS_DONE_MSB 4 +#define CLOCKS_FC0_STATUS_DONE_LSB 4 +#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_PASS +// Description : Test passed +#define CLOCKS_FC0_STATUS_PASS_RESET 0x0 +#define CLOCKS_FC0_STATUS_PASS_BITS 0x00000001 +#define CLOCKS_FC0_STATUS_PASS_MSB 0 +#define CLOCKS_FC0_STATUS_PASS_LSB 0 +#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_RESULT +// Description : Result of frequency measurement, only valid when status_done=1 +#define CLOCKS_FC0_RESULT_OFFSET 0x0000009c +#define CLOCKS_FC0_RESULT_BITS 0x3fffffff +#define CLOCKS_FC0_RESULT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_KHZ +// Description : None +#define CLOCKS_FC0_RESULT_KHZ_RESET 0x0000000 +#define CLOCKS_FC0_RESULT_KHZ_BITS 0x3fffffe0 +#define CLOCKS_FC0_RESULT_KHZ_MSB 29 +#define CLOCKS_FC0_RESULT_KHZ_LSB 5 +#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_FRAC +// Description : None +#define CLOCKS_FC0_RESULT_FRAC_RESET 0x00 +#define CLOCKS_FC0_RESULT_FRAC_BITS 0x0000001f +#define CLOCKS_FC0_RESULT_FRAC_MSB 4 +#define CLOCKS_FC0_RESULT_FRAC_LSB 0 +#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_WAKE_EN0 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN0_OFFSET 0x000000a0 +#define CLOCKS_WAKE_EN0_BITS 0xffffffff +#define CLOCKS_WAKE_EN0_RESET 0xffffffff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_WAKE_EN1 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN1_OFFSET 0x000000a4 +#define CLOCKS_WAKE_EN1_BITS 0x00007fff +#define CLOCKS_WAKE_EN1_RESET 0x00007fff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN0 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN0_OFFSET 0x000000a8 +#define CLOCKS_SLEEP_EN0_BITS 0xffffffff +#define CLOCKS_SLEEP_EN0_RESET 0xffffffff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN1 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN1_OFFSET 0x000000ac +#define CLOCKS_SLEEP_EN1_BITS 0x00007fff +#define CLOCKS_SLEEP_EN1_RESET 0x00007fff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_ENABLED0 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED0_OFFSET 0x000000b0 +#define CLOCKS_ENABLED0_BITS 0xffffffff +#define CLOCKS_ENABLED0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SIO +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RTC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_RTC_RTC +// Description : None +#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PWM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PSM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PADS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_IO +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_DMA +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ADC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_ADC_ADC +// Description : None +#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_ENABLED1 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED1_OFFSET 0x000000b4 +#define CLOCKS_ENABLED1_BITS 0x00007fff +#define CLOCKS_ENABLED1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XIP +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTR +// Description : Raw Interrupts +#define CLOCKS_INTR_OFFSET 0x000000b8 +#define CLOCKS_INTR_BITS 0x00000001 +#define CLOCKS_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTR_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTE +// Description : Interrupt Enable +#define CLOCKS_INTE_OFFSET 0x000000bc +#define CLOCKS_INTE_BITS 0x00000001 +#define CLOCKS_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTE_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTF +// Description : Interrupt Force +#define CLOCKS_INTF_OFFSET 0x000000c0 +#define CLOCKS_INTF_BITS 0x00000001 +#define CLOCKS_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTF_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTS +// Description : Interrupt status after masking & forcing +#define CLOCKS_INTS_OFFSET 0x000000c4 +#define CLOCKS_INTS_BITS 0x00000001 +#define CLOCKS_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTS_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_CLOCKS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h new file mode 100644 index 00000000000..3a1fdbca12e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -0,0 +1,5313 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : DMA +// Version : 1 +// Bus type : apb +// Description : DMA with separate read and write masters +// ============================================================================= +#ifndef HARDWARE_REGS_DMA_DEFINED +#define HARDWARE_REGS_DMA_DEFINED +// ============================================================================= +// Register : DMA_CH0_READ_ADDR +// Description : DMA Channel 0 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH0_READ_ADDR_OFFSET 0x00000000 +#define DMA_CH0_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_READ_ADDR_RESET 0x00000000 +#define DMA_CH0_READ_ADDR_MSB 31 +#define DMA_CH0_READ_ADDR_LSB 0 +#define DMA_CH0_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_WRITE_ADDR +// Description : DMA Channel 0 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH0_WRITE_ADDR_OFFSET 0x00000004 +#define DMA_CH0_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH0_WRITE_ADDR_MSB 31 +#define DMA_CH0_WRITE_ADDR_LSB 0 +#define DMA_CH0_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_TRANS_COUNT +// Description : DMA Channel 0 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH0_TRANS_COUNT_OFFSET 0x00000008 +#define DMA_CH0_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH0_TRANS_COUNT_MSB 31 +#define DMA_CH0_TRANS_COUNT_LSB 0 +#define DMA_CH0_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_CTRL_TRIG +// Description : DMA Channel 0 Control and Status +#define DMA_CH0_CTRL_TRIG_OFFSET 0x0000000c +#define DMA_CH0_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH0_CTRL_TRIG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH0_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH0_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (0). +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH0_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH0_CTRL_TRIG_EN_MSB 0 +#define DMA_CH0_CTRL_TRIG_EN_LSB 0 +#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL1_CTRL_OFFSET 0x00000010 +#define DMA_CH0_AL1_CTRL_BITS 0xffffffff +#define DMA_CH0_AL1_CTRL_RESET "-" +#define DMA_CH0_AL1_CTRL_MSB 31 +#define DMA_CH0_AL1_CTRL_LSB 0 +#define DMA_CH0_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL1_READ_ADDR_OFFSET 0x00000014 +#define DMA_CH0_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_READ_ADDR_RESET "-" +#define DMA_CH0_AL1_READ_ADDR_MSB 31 +#define DMA_CH0_AL1_READ_ADDR_LSB 0 +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET 0x00000018 +#define DMA_CH0_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH0_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 0 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000001c +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL2_CTRL_OFFSET 0x00000020 +#define DMA_CH0_AL2_CTRL_BITS 0xffffffff +#define DMA_CH0_AL2_CTRL_RESET "-" +#define DMA_CH0_AL2_CTRL_MSB 31 +#define DMA_CH0_AL2_CTRL_LSB 0 +#define DMA_CH0_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET 0x00000024 +#define DMA_CH0_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH0_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL2_READ_ADDR_OFFSET 0x00000028 +#define DMA_CH0_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL2_READ_ADDR_RESET "-" +#define DMA_CH0_AL2_READ_ADDR_MSB 31 +#define DMA_CH0_AL2_READ_ADDR_LSB 0 +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 0 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000002c +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL3_CTRL_OFFSET 0x00000030 +#define DMA_CH0_AL3_CTRL_BITS 0xffffffff +#define DMA_CH0_AL3_CTRL_RESET "-" +#define DMA_CH0_AL3_CTRL_MSB 31 +#define DMA_CH0_AL3_CTRL_LSB 0 +#define DMA_CH0_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET 0x00000034 +#define DMA_CH0_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH0_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET 0x00000038 +#define DMA_CH0_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH0_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_READ_ADDR_TRIG +// Description : Alias for channel 0 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET 0x0000003c +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_READ_ADDR +// Description : DMA Channel 1 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH1_READ_ADDR_OFFSET 0x00000040 +#define DMA_CH1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_READ_ADDR_RESET 0x00000000 +#define DMA_CH1_READ_ADDR_MSB 31 +#define DMA_CH1_READ_ADDR_LSB 0 +#define DMA_CH1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_WRITE_ADDR +// Description : DMA Channel 1 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH1_WRITE_ADDR_OFFSET 0x00000044 +#define DMA_CH1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH1_WRITE_ADDR_MSB 31 +#define DMA_CH1_WRITE_ADDR_LSB 0 +#define DMA_CH1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_TRANS_COUNT +// Description : DMA Channel 1 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH1_TRANS_COUNT_OFFSET 0x00000048 +#define DMA_CH1_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH1_TRANS_COUNT_MSB 31 +#define DMA_CH1_TRANS_COUNT_LSB 0 +#define DMA_CH1_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_CTRL_TRIG +// Description : DMA Channel 1 Control and Status +#define DMA_CH1_CTRL_TRIG_OFFSET 0x0000004c +#define DMA_CH1_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH1_CTRL_TRIG_RESET 0x00000800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH1_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH1_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (1). +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET 0x1 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH1_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH1_CTRL_TRIG_EN_MSB 0 +#define DMA_CH1_CTRL_TRIG_EN_LSB 0 +#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL1_CTRL_OFFSET 0x00000050 +#define DMA_CH1_AL1_CTRL_BITS 0xffffffff +#define DMA_CH1_AL1_CTRL_RESET "-" +#define DMA_CH1_AL1_CTRL_MSB 31 +#define DMA_CH1_AL1_CTRL_LSB 0 +#define DMA_CH1_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL1_READ_ADDR_OFFSET 0x00000054 +#define DMA_CH1_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_READ_ADDR_RESET "-" +#define DMA_CH1_AL1_READ_ADDR_MSB 31 +#define DMA_CH1_AL1_READ_ADDR_LSB 0 +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET 0x00000058 +#define DMA_CH1_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH1_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 1 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000005c +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL2_CTRL_OFFSET 0x00000060 +#define DMA_CH1_AL2_CTRL_BITS 0xffffffff +#define DMA_CH1_AL2_CTRL_RESET "-" +#define DMA_CH1_AL2_CTRL_MSB 31 +#define DMA_CH1_AL2_CTRL_LSB 0 +#define DMA_CH1_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET 0x00000064 +#define DMA_CH1_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH1_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL2_READ_ADDR_OFFSET 0x00000068 +#define DMA_CH1_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL2_READ_ADDR_RESET "-" +#define DMA_CH1_AL2_READ_ADDR_MSB 31 +#define DMA_CH1_AL2_READ_ADDR_LSB 0 +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 1 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000006c +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL3_CTRL_OFFSET 0x00000070 +#define DMA_CH1_AL3_CTRL_BITS 0xffffffff +#define DMA_CH1_AL3_CTRL_RESET "-" +#define DMA_CH1_AL3_CTRL_MSB 31 +#define DMA_CH1_AL3_CTRL_LSB 0 +#define DMA_CH1_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET 0x00000074 +#define DMA_CH1_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH1_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET 0x00000078 +#define DMA_CH1_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH1_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_READ_ADDR_TRIG +// Description : Alias for channel 1 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET 0x0000007c +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_READ_ADDR +// Description : DMA Channel 2 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH2_READ_ADDR_OFFSET 0x00000080 +#define DMA_CH2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_READ_ADDR_RESET 0x00000000 +#define DMA_CH2_READ_ADDR_MSB 31 +#define DMA_CH2_READ_ADDR_LSB 0 +#define DMA_CH2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_WRITE_ADDR +// Description : DMA Channel 2 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH2_WRITE_ADDR_OFFSET 0x00000084 +#define DMA_CH2_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH2_WRITE_ADDR_MSB 31 +#define DMA_CH2_WRITE_ADDR_LSB 0 +#define DMA_CH2_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_TRANS_COUNT +// Description : DMA Channel 2 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH2_TRANS_COUNT_OFFSET 0x00000088 +#define DMA_CH2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH2_TRANS_COUNT_MSB 31 +#define DMA_CH2_TRANS_COUNT_LSB 0 +#define DMA_CH2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_CTRL_TRIG +// Description : DMA Channel 2 Control and Status +#define DMA_CH2_CTRL_TRIG_OFFSET 0x0000008c +#define DMA_CH2_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH2_CTRL_TRIG_RESET 0x00001000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH2_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH2_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (2). +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET 0x2 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH2_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH2_CTRL_TRIG_EN_MSB 0 +#define DMA_CH2_CTRL_TRIG_EN_LSB 0 +#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL1_CTRL_OFFSET 0x00000090 +#define DMA_CH2_AL1_CTRL_BITS 0xffffffff +#define DMA_CH2_AL1_CTRL_RESET "-" +#define DMA_CH2_AL1_CTRL_MSB 31 +#define DMA_CH2_AL1_CTRL_LSB 0 +#define DMA_CH2_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL1_READ_ADDR_OFFSET 0x00000094 +#define DMA_CH2_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_READ_ADDR_RESET "-" +#define DMA_CH2_AL1_READ_ADDR_MSB 31 +#define DMA_CH2_AL1_READ_ADDR_LSB 0 +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET 0x00000098 +#define DMA_CH2_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH2_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 2 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000009c +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL2_CTRL_OFFSET 0x000000a0 +#define DMA_CH2_AL2_CTRL_BITS 0xffffffff +#define DMA_CH2_AL2_CTRL_RESET "-" +#define DMA_CH2_AL2_CTRL_MSB 31 +#define DMA_CH2_AL2_CTRL_LSB 0 +#define DMA_CH2_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET 0x000000a4 +#define DMA_CH2_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH2_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL2_READ_ADDR_OFFSET 0x000000a8 +#define DMA_CH2_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL2_READ_ADDR_RESET "-" +#define DMA_CH2_AL2_READ_ADDR_MSB 31 +#define DMA_CH2_AL2_READ_ADDR_LSB 0 +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 2 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ac +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL3_CTRL_OFFSET 0x000000b0 +#define DMA_CH2_AL3_CTRL_BITS 0xffffffff +#define DMA_CH2_AL3_CTRL_RESET "-" +#define DMA_CH2_AL3_CTRL_MSB 31 +#define DMA_CH2_AL3_CTRL_LSB 0 +#define DMA_CH2_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET 0x000000b4 +#define DMA_CH2_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH2_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET 0x000000b8 +#define DMA_CH2_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH2_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_READ_ADDR_TRIG +// Description : Alias for channel 2 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET 0x000000bc +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_READ_ADDR +// Description : DMA Channel 3 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH3_READ_ADDR_OFFSET 0x000000c0 +#define DMA_CH3_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_READ_ADDR_RESET 0x00000000 +#define DMA_CH3_READ_ADDR_MSB 31 +#define DMA_CH3_READ_ADDR_LSB 0 +#define DMA_CH3_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_WRITE_ADDR +// Description : DMA Channel 3 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH3_WRITE_ADDR_OFFSET 0x000000c4 +#define DMA_CH3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH3_WRITE_ADDR_MSB 31 +#define DMA_CH3_WRITE_ADDR_LSB 0 +#define DMA_CH3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_TRANS_COUNT +// Description : DMA Channel 3 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH3_TRANS_COUNT_OFFSET 0x000000c8 +#define DMA_CH3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH3_TRANS_COUNT_MSB 31 +#define DMA_CH3_TRANS_COUNT_LSB 0 +#define DMA_CH3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_CTRL_TRIG +// Description : DMA Channel 3 Control and Status +#define DMA_CH3_CTRL_TRIG_OFFSET 0x000000cc +#define DMA_CH3_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH3_CTRL_TRIG_RESET 0x00001800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH3_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH3_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (3). +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET 0x3 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH3_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH3_CTRL_TRIG_EN_MSB 0 +#define DMA_CH3_CTRL_TRIG_EN_LSB 0 +#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL1_CTRL_OFFSET 0x000000d0 +#define DMA_CH3_AL1_CTRL_BITS 0xffffffff +#define DMA_CH3_AL1_CTRL_RESET "-" +#define DMA_CH3_AL1_CTRL_MSB 31 +#define DMA_CH3_AL1_CTRL_LSB 0 +#define DMA_CH3_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL1_READ_ADDR_OFFSET 0x000000d4 +#define DMA_CH3_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_READ_ADDR_RESET "-" +#define DMA_CH3_AL1_READ_ADDR_MSB 31 +#define DMA_CH3_AL1_READ_ADDR_LSB 0 +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET 0x000000d8 +#define DMA_CH3_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH3_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 3 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET 0x000000dc +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL2_CTRL_OFFSET 0x000000e0 +#define DMA_CH3_AL2_CTRL_BITS 0xffffffff +#define DMA_CH3_AL2_CTRL_RESET "-" +#define DMA_CH3_AL2_CTRL_MSB 31 +#define DMA_CH3_AL2_CTRL_LSB 0 +#define DMA_CH3_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET 0x000000e4 +#define DMA_CH3_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH3_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL2_READ_ADDR_OFFSET 0x000000e8 +#define DMA_CH3_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL2_READ_ADDR_RESET "-" +#define DMA_CH3_AL2_READ_ADDR_MSB 31 +#define DMA_CH3_AL2_READ_ADDR_LSB 0 +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 3 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ec +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL3_CTRL_OFFSET 0x000000f0 +#define DMA_CH3_AL3_CTRL_BITS 0xffffffff +#define DMA_CH3_AL3_CTRL_RESET "-" +#define DMA_CH3_AL3_CTRL_MSB 31 +#define DMA_CH3_AL3_CTRL_LSB 0 +#define DMA_CH3_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET 0x000000f4 +#define DMA_CH3_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH3_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET 0x000000f8 +#define DMA_CH3_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH3_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_READ_ADDR_TRIG +// Description : Alias for channel 3 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET 0x000000fc +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_READ_ADDR +// Description : DMA Channel 4 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH4_READ_ADDR_OFFSET 0x00000100 +#define DMA_CH4_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_READ_ADDR_RESET 0x00000000 +#define DMA_CH4_READ_ADDR_MSB 31 +#define DMA_CH4_READ_ADDR_LSB 0 +#define DMA_CH4_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_WRITE_ADDR +// Description : DMA Channel 4 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH4_WRITE_ADDR_OFFSET 0x00000104 +#define DMA_CH4_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH4_WRITE_ADDR_MSB 31 +#define DMA_CH4_WRITE_ADDR_LSB 0 +#define DMA_CH4_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_TRANS_COUNT +// Description : DMA Channel 4 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH4_TRANS_COUNT_OFFSET 0x00000108 +#define DMA_CH4_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH4_TRANS_COUNT_MSB 31 +#define DMA_CH4_TRANS_COUNT_LSB 0 +#define DMA_CH4_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_CTRL_TRIG +// Description : DMA Channel 4 Control and Status +#define DMA_CH4_CTRL_TRIG_OFFSET 0x0000010c +#define DMA_CH4_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH4_CTRL_TRIG_RESET 0x00002000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH4_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH4_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (4). +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET 0x4 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH4_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH4_CTRL_TRIG_EN_MSB 0 +#define DMA_CH4_CTRL_TRIG_EN_LSB 0 +#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL1_CTRL_OFFSET 0x00000110 +#define DMA_CH4_AL1_CTRL_BITS 0xffffffff +#define DMA_CH4_AL1_CTRL_RESET "-" +#define DMA_CH4_AL1_CTRL_MSB 31 +#define DMA_CH4_AL1_CTRL_LSB 0 +#define DMA_CH4_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL1_READ_ADDR_OFFSET 0x00000114 +#define DMA_CH4_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_READ_ADDR_RESET "-" +#define DMA_CH4_AL1_READ_ADDR_MSB 31 +#define DMA_CH4_AL1_READ_ADDR_LSB 0 +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET 0x00000118 +#define DMA_CH4_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH4_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 4 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000011c +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL2_CTRL_OFFSET 0x00000120 +#define DMA_CH4_AL2_CTRL_BITS 0xffffffff +#define DMA_CH4_AL2_CTRL_RESET "-" +#define DMA_CH4_AL2_CTRL_MSB 31 +#define DMA_CH4_AL2_CTRL_LSB 0 +#define DMA_CH4_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET 0x00000124 +#define DMA_CH4_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH4_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL2_READ_ADDR_OFFSET 0x00000128 +#define DMA_CH4_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL2_READ_ADDR_RESET "-" +#define DMA_CH4_AL2_READ_ADDR_MSB 31 +#define DMA_CH4_AL2_READ_ADDR_LSB 0 +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 4 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000012c +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL3_CTRL_OFFSET 0x00000130 +#define DMA_CH4_AL3_CTRL_BITS 0xffffffff +#define DMA_CH4_AL3_CTRL_RESET "-" +#define DMA_CH4_AL3_CTRL_MSB 31 +#define DMA_CH4_AL3_CTRL_LSB 0 +#define DMA_CH4_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET 0x00000134 +#define DMA_CH4_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH4_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET 0x00000138 +#define DMA_CH4_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH4_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_READ_ADDR_TRIG +// Description : Alias for channel 4 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET 0x0000013c +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_READ_ADDR +// Description : DMA Channel 5 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH5_READ_ADDR_OFFSET 0x00000140 +#define DMA_CH5_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_READ_ADDR_RESET 0x00000000 +#define DMA_CH5_READ_ADDR_MSB 31 +#define DMA_CH5_READ_ADDR_LSB 0 +#define DMA_CH5_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_WRITE_ADDR +// Description : DMA Channel 5 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH5_WRITE_ADDR_OFFSET 0x00000144 +#define DMA_CH5_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH5_WRITE_ADDR_MSB 31 +#define DMA_CH5_WRITE_ADDR_LSB 0 +#define DMA_CH5_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_TRANS_COUNT +// Description : DMA Channel 5 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH5_TRANS_COUNT_OFFSET 0x00000148 +#define DMA_CH5_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH5_TRANS_COUNT_MSB 31 +#define DMA_CH5_TRANS_COUNT_LSB 0 +#define DMA_CH5_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_CTRL_TRIG +// Description : DMA Channel 5 Control and Status +#define DMA_CH5_CTRL_TRIG_OFFSET 0x0000014c +#define DMA_CH5_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH5_CTRL_TRIG_RESET 0x00002800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH5_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH5_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (5). +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET 0x5 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH5_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH5_CTRL_TRIG_EN_MSB 0 +#define DMA_CH5_CTRL_TRIG_EN_LSB 0 +#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL1_CTRL_OFFSET 0x00000150 +#define DMA_CH5_AL1_CTRL_BITS 0xffffffff +#define DMA_CH5_AL1_CTRL_RESET "-" +#define DMA_CH5_AL1_CTRL_MSB 31 +#define DMA_CH5_AL1_CTRL_LSB 0 +#define DMA_CH5_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL1_READ_ADDR_OFFSET 0x00000154 +#define DMA_CH5_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_READ_ADDR_RESET "-" +#define DMA_CH5_AL1_READ_ADDR_MSB 31 +#define DMA_CH5_AL1_READ_ADDR_LSB 0 +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET 0x00000158 +#define DMA_CH5_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH5_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 5 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000015c +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL2_CTRL_OFFSET 0x00000160 +#define DMA_CH5_AL2_CTRL_BITS 0xffffffff +#define DMA_CH5_AL2_CTRL_RESET "-" +#define DMA_CH5_AL2_CTRL_MSB 31 +#define DMA_CH5_AL2_CTRL_LSB 0 +#define DMA_CH5_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET 0x00000164 +#define DMA_CH5_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH5_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL2_READ_ADDR_OFFSET 0x00000168 +#define DMA_CH5_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL2_READ_ADDR_RESET "-" +#define DMA_CH5_AL2_READ_ADDR_MSB 31 +#define DMA_CH5_AL2_READ_ADDR_LSB 0 +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 5 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000016c +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL3_CTRL_OFFSET 0x00000170 +#define DMA_CH5_AL3_CTRL_BITS 0xffffffff +#define DMA_CH5_AL3_CTRL_RESET "-" +#define DMA_CH5_AL3_CTRL_MSB 31 +#define DMA_CH5_AL3_CTRL_LSB 0 +#define DMA_CH5_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET 0x00000174 +#define DMA_CH5_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH5_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET 0x00000178 +#define DMA_CH5_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH5_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_READ_ADDR_TRIG +// Description : Alias for channel 5 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET 0x0000017c +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_READ_ADDR +// Description : DMA Channel 6 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH6_READ_ADDR_OFFSET 0x00000180 +#define DMA_CH6_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_READ_ADDR_RESET 0x00000000 +#define DMA_CH6_READ_ADDR_MSB 31 +#define DMA_CH6_READ_ADDR_LSB 0 +#define DMA_CH6_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_WRITE_ADDR +// Description : DMA Channel 6 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH6_WRITE_ADDR_OFFSET 0x00000184 +#define DMA_CH6_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH6_WRITE_ADDR_MSB 31 +#define DMA_CH6_WRITE_ADDR_LSB 0 +#define DMA_CH6_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_TRANS_COUNT +// Description : DMA Channel 6 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH6_TRANS_COUNT_OFFSET 0x00000188 +#define DMA_CH6_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH6_TRANS_COUNT_MSB 31 +#define DMA_CH6_TRANS_COUNT_LSB 0 +#define DMA_CH6_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_CTRL_TRIG +// Description : DMA Channel 6 Control and Status +#define DMA_CH6_CTRL_TRIG_OFFSET 0x0000018c +#define DMA_CH6_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH6_CTRL_TRIG_RESET 0x00003000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH6_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH6_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (6). +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET 0x6 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH6_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH6_CTRL_TRIG_EN_MSB 0 +#define DMA_CH6_CTRL_TRIG_EN_LSB 0 +#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL1_CTRL_OFFSET 0x00000190 +#define DMA_CH6_AL1_CTRL_BITS 0xffffffff +#define DMA_CH6_AL1_CTRL_RESET "-" +#define DMA_CH6_AL1_CTRL_MSB 31 +#define DMA_CH6_AL1_CTRL_LSB 0 +#define DMA_CH6_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL1_READ_ADDR_OFFSET 0x00000194 +#define DMA_CH6_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_READ_ADDR_RESET "-" +#define DMA_CH6_AL1_READ_ADDR_MSB 31 +#define DMA_CH6_AL1_READ_ADDR_LSB 0 +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET 0x00000198 +#define DMA_CH6_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH6_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 6 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000019c +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL2_CTRL_OFFSET 0x000001a0 +#define DMA_CH6_AL2_CTRL_BITS 0xffffffff +#define DMA_CH6_AL2_CTRL_RESET "-" +#define DMA_CH6_AL2_CTRL_MSB 31 +#define DMA_CH6_AL2_CTRL_LSB 0 +#define DMA_CH6_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET 0x000001a4 +#define DMA_CH6_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH6_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL2_READ_ADDR_OFFSET 0x000001a8 +#define DMA_CH6_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL2_READ_ADDR_RESET "-" +#define DMA_CH6_AL2_READ_ADDR_MSB 31 +#define DMA_CH6_AL2_READ_ADDR_LSB 0 +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 6 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ac +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL3_CTRL_OFFSET 0x000001b0 +#define DMA_CH6_AL3_CTRL_BITS 0xffffffff +#define DMA_CH6_AL3_CTRL_RESET "-" +#define DMA_CH6_AL3_CTRL_MSB 31 +#define DMA_CH6_AL3_CTRL_LSB 0 +#define DMA_CH6_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET 0x000001b4 +#define DMA_CH6_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH6_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET 0x000001b8 +#define DMA_CH6_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH6_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_READ_ADDR_TRIG +// Description : Alias for channel 6 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET 0x000001bc +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_READ_ADDR +// Description : DMA Channel 7 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH7_READ_ADDR_OFFSET 0x000001c0 +#define DMA_CH7_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_READ_ADDR_RESET 0x00000000 +#define DMA_CH7_READ_ADDR_MSB 31 +#define DMA_CH7_READ_ADDR_LSB 0 +#define DMA_CH7_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_WRITE_ADDR +// Description : DMA Channel 7 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH7_WRITE_ADDR_OFFSET 0x000001c4 +#define DMA_CH7_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH7_WRITE_ADDR_MSB 31 +#define DMA_CH7_WRITE_ADDR_LSB 0 +#define DMA_CH7_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_TRANS_COUNT +// Description : DMA Channel 7 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH7_TRANS_COUNT_OFFSET 0x000001c8 +#define DMA_CH7_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH7_TRANS_COUNT_MSB 31 +#define DMA_CH7_TRANS_COUNT_LSB 0 +#define DMA_CH7_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_CTRL_TRIG +// Description : DMA Channel 7 Control and Status +#define DMA_CH7_CTRL_TRIG_OFFSET 0x000001cc +#define DMA_CH7_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH7_CTRL_TRIG_RESET 0x00003800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH7_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH7_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (7). +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET 0x7 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH7_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH7_CTRL_TRIG_EN_MSB 0 +#define DMA_CH7_CTRL_TRIG_EN_LSB 0 +#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL1_CTRL_OFFSET 0x000001d0 +#define DMA_CH7_AL1_CTRL_BITS 0xffffffff +#define DMA_CH7_AL1_CTRL_RESET "-" +#define DMA_CH7_AL1_CTRL_MSB 31 +#define DMA_CH7_AL1_CTRL_LSB 0 +#define DMA_CH7_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL1_READ_ADDR_OFFSET 0x000001d4 +#define DMA_CH7_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_READ_ADDR_RESET "-" +#define DMA_CH7_AL1_READ_ADDR_MSB 31 +#define DMA_CH7_AL1_READ_ADDR_LSB 0 +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET 0x000001d8 +#define DMA_CH7_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH7_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 7 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET 0x000001dc +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL2_CTRL_OFFSET 0x000001e0 +#define DMA_CH7_AL2_CTRL_BITS 0xffffffff +#define DMA_CH7_AL2_CTRL_RESET "-" +#define DMA_CH7_AL2_CTRL_MSB 31 +#define DMA_CH7_AL2_CTRL_LSB 0 +#define DMA_CH7_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET 0x000001e4 +#define DMA_CH7_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH7_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL2_READ_ADDR_OFFSET 0x000001e8 +#define DMA_CH7_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL2_READ_ADDR_RESET "-" +#define DMA_CH7_AL2_READ_ADDR_MSB 31 +#define DMA_CH7_AL2_READ_ADDR_LSB 0 +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 7 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ec +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL3_CTRL_OFFSET 0x000001f0 +#define DMA_CH7_AL3_CTRL_BITS 0xffffffff +#define DMA_CH7_AL3_CTRL_RESET "-" +#define DMA_CH7_AL3_CTRL_MSB 31 +#define DMA_CH7_AL3_CTRL_LSB 0 +#define DMA_CH7_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET 0x000001f4 +#define DMA_CH7_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH7_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET 0x000001f8 +#define DMA_CH7_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH7_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_READ_ADDR_TRIG +// Description : Alias for channel 7 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET 0x000001fc +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_READ_ADDR +// Description : DMA Channel 8 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH8_READ_ADDR_OFFSET 0x00000200 +#define DMA_CH8_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_READ_ADDR_RESET 0x00000000 +#define DMA_CH8_READ_ADDR_MSB 31 +#define DMA_CH8_READ_ADDR_LSB 0 +#define DMA_CH8_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_WRITE_ADDR +// Description : DMA Channel 8 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH8_WRITE_ADDR_OFFSET 0x00000204 +#define DMA_CH8_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH8_WRITE_ADDR_MSB 31 +#define DMA_CH8_WRITE_ADDR_LSB 0 +#define DMA_CH8_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_TRANS_COUNT +// Description : DMA Channel 8 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH8_TRANS_COUNT_OFFSET 0x00000208 +#define DMA_CH8_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH8_TRANS_COUNT_MSB 31 +#define DMA_CH8_TRANS_COUNT_LSB 0 +#define DMA_CH8_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_CTRL_TRIG +// Description : DMA Channel 8 Control and Status +#define DMA_CH8_CTRL_TRIG_OFFSET 0x0000020c +#define DMA_CH8_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH8_CTRL_TRIG_RESET 0x00004000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH8_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH8_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (8). +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET 0x8 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH8_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH8_CTRL_TRIG_EN_MSB 0 +#define DMA_CH8_CTRL_TRIG_EN_LSB 0 +#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL1_CTRL_OFFSET 0x00000210 +#define DMA_CH8_AL1_CTRL_BITS 0xffffffff +#define DMA_CH8_AL1_CTRL_RESET "-" +#define DMA_CH8_AL1_CTRL_MSB 31 +#define DMA_CH8_AL1_CTRL_LSB 0 +#define DMA_CH8_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL1_READ_ADDR_OFFSET 0x00000214 +#define DMA_CH8_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_READ_ADDR_RESET "-" +#define DMA_CH8_AL1_READ_ADDR_MSB 31 +#define DMA_CH8_AL1_READ_ADDR_LSB 0 +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET 0x00000218 +#define DMA_CH8_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH8_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 8 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000021c +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL2_CTRL_OFFSET 0x00000220 +#define DMA_CH8_AL2_CTRL_BITS 0xffffffff +#define DMA_CH8_AL2_CTRL_RESET "-" +#define DMA_CH8_AL2_CTRL_MSB 31 +#define DMA_CH8_AL2_CTRL_LSB 0 +#define DMA_CH8_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET 0x00000224 +#define DMA_CH8_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH8_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL2_READ_ADDR_OFFSET 0x00000228 +#define DMA_CH8_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL2_READ_ADDR_RESET "-" +#define DMA_CH8_AL2_READ_ADDR_MSB 31 +#define DMA_CH8_AL2_READ_ADDR_LSB 0 +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 8 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000022c +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL3_CTRL_OFFSET 0x00000230 +#define DMA_CH8_AL3_CTRL_BITS 0xffffffff +#define DMA_CH8_AL3_CTRL_RESET "-" +#define DMA_CH8_AL3_CTRL_MSB 31 +#define DMA_CH8_AL3_CTRL_LSB 0 +#define DMA_CH8_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET 0x00000234 +#define DMA_CH8_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH8_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET 0x00000238 +#define DMA_CH8_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH8_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_READ_ADDR_TRIG +// Description : Alias for channel 8 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET 0x0000023c +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_READ_ADDR +// Description : DMA Channel 9 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH9_READ_ADDR_OFFSET 0x00000240 +#define DMA_CH9_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_READ_ADDR_RESET 0x00000000 +#define DMA_CH9_READ_ADDR_MSB 31 +#define DMA_CH9_READ_ADDR_LSB 0 +#define DMA_CH9_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_WRITE_ADDR +// Description : DMA Channel 9 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH9_WRITE_ADDR_OFFSET 0x00000244 +#define DMA_CH9_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH9_WRITE_ADDR_MSB 31 +#define DMA_CH9_WRITE_ADDR_LSB 0 +#define DMA_CH9_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_TRANS_COUNT +// Description : DMA Channel 9 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH9_TRANS_COUNT_OFFSET 0x00000248 +#define DMA_CH9_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH9_TRANS_COUNT_MSB 31 +#define DMA_CH9_TRANS_COUNT_LSB 0 +#define DMA_CH9_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_CTRL_TRIG +// Description : DMA Channel 9 Control and Status +#define DMA_CH9_CTRL_TRIG_OFFSET 0x0000024c +#define DMA_CH9_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH9_CTRL_TRIG_RESET 0x00004800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH9_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH9_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (9). +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET 0x9 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH9_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH9_CTRL_TRIG_EN_MSB 0 +#define DMA_CH9_CTRL_TRIG_EN_LSB 0 +#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL1_CTRL_OFFSET 0x00000250 +#define DMA_CH9_AL1_CTRL_BITS 0xffffffff +#define DMA_CH9_AL1_CTRL_RESET "-" +#define DMA_CH9_AL1_CTRL_MSB 31 +#define DMA_CH9_AL1_CTRL_LSB 0 +#define DMA_CH9_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL1_READ_ADDR_OFFSET 0x00000254 +#define DMA_CH9_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_READ_ADDR_RESET "-" +#define DMA_CH9_AL1_READ_ADDR_MSB 31 +#define DMA_CH9_AL1_READ_ADDR_LSB 0 +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET 0x00000258 +#define DMA_CH9_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH9_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 9 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000025c +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL2_CTRL_OFFSET 0x00000260 +#define DMA_CH9_AL2_CTRL_BITS 0xffffffff +#define DMA_CH9_AL2_CTRL_RESET "-" +#define DMA_CH9_AL2_CTRL_MSB 31 +#define DMA_CH9_AL2_CTRL_LSB 0 +#define DMA_CH9_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET 0x00000264 +#define DMA_CH9_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH9_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL2_READ_ADDR_OFFSET 0x00000268 +#define DMA_CH9_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL2_READ_ADDR_RESET "-" +#define DMA_CH9_AL2_READ_ADDR_MSB 31 +#define DMA_CH9_AL2_READ_ADDR_LSB 0 +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 9 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000026c +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL3_CTRL_OFFSET 0x00000270 +#define DMA_CH9_AL3_CTRL_BITS 0xffffffff +#define DMA_CH9_AL3_CTRL_RESET "-" +#define DMA_CH9_AL3_CTRL_MSB 31 +#define DMA_CH9_AL3_CTRL_LSB 0 +#define DMA_CH9_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET 0x00000274 +#define DMA_CH9_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH9_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET 0x00000278 +#define DMA_CH9_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH9_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_READ_ADDR_TRIG +// Description : Alias for channel 9 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET 0x0000027c +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_READ_ADDR +// Description : DMA Channel 10 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH10_READ_ADDR_OFFSET 0x00000280 +#define DMA_CH10_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_READ_ADDR_RESET 0x00000000 +#define DMA_CH10_READ_ADDR_MSB 31 +#define DMA_CH10_READ_ADDR_LSB 0 +#define DMA_CH10_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_WRITE_ADDR +// Description : DMA Channel 10 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH10_WRITE_ADDR_OFFSET 0x00000284 +#define DMA_CH10_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH10_WRITE_ADDR_MSB 31 +#define DMA_CH10_WRITE_ADDR_LSB 0 +#define DMA_CH10_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_TRANS_COUNT +// Description : DMA Channel 10 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH10_TRANS_COUNT_OFFSET 0x00000288 +#define DMA_CH10_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH10_TRANS_COUNT_MSB 31 +#define DMA_CH10_TRANS_COUNT_LSB 0 +#define DMA_CH10_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_CTRL_TRIG +// Description : DMA Channel 10 Control and Status +#define DMA_CH10_CTRL_TRIG_OFFSET 0x0000028c +#define DMA_CH10_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH10_CTRL_TRIG_RESET 0x00005000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH10_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH10_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (10). +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET 0xa +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH10_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH10_CTRL_TRIG_EN_MSB 0 +#define DMA_CH10_CTRL_TRIG_EN_LSB 0 +#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL1_CTRL_OFFSET 0x00000290 +#define DMA_CH10_AL1_CTRL_BITS 0xffffffff +#define DMA_CH10_AL1_CTRL_RESET "-" +#define DMA_CH10_AL1_CTRL_MSB 31 +#define DMA_CH10_AL1_CTRL_LSB 0 +#define DMA_CH10_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL1_READ_ADDR_OFFSET 0x00000294 +#define DMA_CH10_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_READ_ADDR_RESET "-" +#define DMA_CH10_AL1_READ_ADDR_MSB 31 +#define DMA_CH10_AL1_READ_ADDR_LSB 0 +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET 0x00000298 +#define DMA_CH10_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH10_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 10 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000029c +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL2_CTRL_OFFSET 0x000002a0 +#define DMA_CH10_AL2_CTRL_BITS 0xffffffff +#define DMA_CH10_AL2_CTRL_RESET "-" +#define DMA_CH10_AL2_CTRL_MSB 31 +#define DMA_CH10_AL2_CTRL_LSB 0 +#define DMA_CH10_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET 0x000002a4 +#define DMA_CH10_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH10_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL2_READ_ADDR_OFFSET 0x000002a8 +#define DMA_CH10_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL2_READ_ADDR_RESET "-" +#define DMA_CH10_AL2_READ_ADDR_MSB 31 +#define DMA_CH10_AL2_READ_ADDR_LSB 0 +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 10 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ac +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL3_CTRL_OFFSET 0x000002b0 +#define DMA_CH10_AL3_CTRL_BITS 0xffffffff +#define DMA_CH10_AL3_CTRL_RESET "-" +#define DMA_CH10_AL3_CTRL_MSB 31 +#define DMA_CH10_AL3_CTRL_LSB 0 +#define DMA_CH10_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET 0x000002b4 +#define DMA_CH10_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH10_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET 0x000002b8 +#define DMA_CH10_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH10_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_READ_ADDR_TRIG +// Description : Alias for channel 10 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET 0x000002bc +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_READ_ADDR +// Description : DMA Channel 11 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH11_READ_ADDR_OFFSET 0x000002c0 +#define DMA_CH11_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_READ_ADDR_RESET 0x00000000 +#define DMA_CH11_READ_ADDR_MSB 31 +#define DMA_CH11_READ_ADDR_LSB 0 +#define DMA_CH11_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_WRITE_ADDR +// Description : DMA Channel 11 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH11_WRITE_ADDR_OFFSET 0x000002c4 +#define DMA_CH11_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH11_WRITE_ADDR_MSB 31 +#define DMA_CH11_WRITE_ADDR_LSB 0 +#define DMA_CH11_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_TRANS_COUNT +// Description : DMA Channel 11 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH11_TRANS_COUNT_OFFSET 0x000002c8 +#define DMA_CH11_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH11_TRANS_COUNT_MSB 31 +#define DMA_CH11_TRANS_COUNT_LSB 0 +#define DMA_CH11_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_CTRL_TRIG +// Description : DMA Channel 11 Control and Status +#define DMA_CH11_CTRL_TRIG_OFFSET 0x000002cc +#define DMA_CH11_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH11_CTRL_TRIG_RESET 0x00005800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH11_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH11_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (11). +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET 0xb +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH11_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH11_CTRL_TRIG_EN_MSB 0 +#define DMA_CH11_CTRL_TRIG_EN_LSB 0 +#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL1_CTRL_OFFSET 0x000002d0 +#define DMA_CH11_AL1_CTRL_BITS 0xffffffff +#define DMA_CH11_AL1_CTRL_RESET "-" +#define DMA_CH11_AL1_CTRL_MSB 31 +#define DMA_CH11_AL1_CTRL_LSB 0 +#define DMA_CH11_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL1_READ_ADDR_OFFSET 0x000002d4 +#define DMA_CH11_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_READ_ADDR_RESET "-" +#define DMA_CH11_AL1_READ_ADDR_MSB 31 +#define DMA_CH11_AL1_READ_ADDR_LSB 0 +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET 0x000002d8 +#define DMA_CH11_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH11_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 11 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET 0x000002dc +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL2_CTRL_OFFSET 0x000002e0 +#define DMA_CH11_AL2_CTRL_BITS 0xffffffff +#define DMA_CH11_AL2_CTRL_RESET "-" +#define DMA_CH11_AL2_CTRL_MSB 31 +#define DMA_CH11_AL2_CTRL_LSB 0 +#define DMA_CH11_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET 0x000002e4 +#define DMA_CH11_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH11_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL2_READ_ADDR_OFFSET 0x000002e8 +#define DMA_CH11_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL2_READ_ADDR_RESET "-" +#define DMA_CH11_AL2_READ_ADDR_MSB 31 +#define DMA_CH11_AL2_READ_ADDR_LSB 0 +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 11 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ec +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL3_CTRL_OFFSET 0x000002f0 +#define DMA_CH11_AL3_CTRL_BITS 0xffffffff +#define DMA_CH11_AL3_CTRL_RESET "-" +#define DMA_CH11_AL3_CTRL_MSB 31 +#define DMA_CH11_AL3_CTRL_LSB 0 +#define DMA_CH11_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET 0x000002f4 +#define DMA_CH11_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH11_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET 0x000002f8 +#define DMA_CH11_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH11_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_READ_ADDR_TRIG +// Description : Alias for channel 11 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET 0x000002fc +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_INTR +// Description : Interrupt Status (raw) +// Raw interrupt status for DMA Channels 0..15. Bit n corresponds +// to channel n. Ignores any masking or forcing. Channel +// interrupts can be cleared by writing a bit mask to INTR, INTS0 +// or INTS1. +// +// Channel interrupts can be routed to either of two system-level +// IRQs based on INTE0 and INTE1. +// +// This can be used vector different channel interrupts to +// different ISRs: this might be done to allow NVIC IRQ preemption +// for more time-critical channels, or to spread IRQ load across +// different cores. +// +// It is also valid to ignore this behaviour and just use +// INTE0/INTS0/IRQ 0. +#define DMA_INTR_OFFSET 0x00000400 +#define DMA_INTR_BITS 0x0000ffff +#define DMA_INTR_RESET 0x00000000 +#define DMA_INTR_MSB 15 +#define DMA_INTR_LSB 0 +#define DMA_INTR_ACCESS "RO" +// ============================================================================= +// Register : DMA_INTE0 +// Description : Interrupt Enables for IRQ 0 +// Set bit n to pass interrupts from channel n to DMA IRQ 0. +#define DMA_INTE0_OFFSET 0x00000404 +#define DMA_INTE0_BITS 0x0000ffff +#define DMA_INTE0_RESET 0x00000000 +#define DMA_INTE0_MSB 15 +#define DMA_INTE0_LSB 0 +#define DMA_INTE0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF0 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTE0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF0_OFFSET 0x00000408 +#define DMA_INTF0_BITS 0x0000ffff +#define DMA_INTF0_RESET 0x00000000 +#define DMA_INTF0_MSB 15 +#define DMA_INTF0_LSB 0 +#define DMA_INTF0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS0 +// Description : Interrupt Status for IRQ 0 +// Indicates active channel interrupt requests which are currently +// causing IRQ 0 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +#define DMA_INTS0_OFFSET 0x0000040c +#define DMA_INTS0_BITS 0x0000ffff +#define DMA_INTS0_RESET 0x00000000 +#define DMA_INTS0_MSB 15 +#define DMA_INTS0_LSB 0 +#define DMA_INTS0_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE1 +// Description : Interrupt Enables for IRQ 1 +// Set bit n to pass interrupts from channel n to DMA IRQ 1. +#define DMA_INTE1_OFFSET 0x00000414 +#define DMA_INTE1_BITS 0x0000ffff +#define DMA_INTE1_RESET 0x00000000 +#define DMA_INTE1_MSB 15 +#define DMA_INTE1_LSB 0 +#define DMA_INTE1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF1 +// Description : Force Interrupts for IRQ 1 +// Write 1s to force the corresponding bits in INTE0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF1_OFFSET 0x00000418 +#define DMA_INTF1_BITS 0x0000ffff +#define DMA_INTF1_RESET 0x00000000 +#define DMA_INTF1_MSB 15 +#define DMA_INTF1_LSB 0 +#define DMA_INTF1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS1 +// Description : Interrupt Status (masked) for IRQ 1 +// Indicates active channel interrupt requests which are currently +// causing IRQ 1 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +#define DMA_INTS1_OFFSET 0x0000041c +#define DMA_INTS1_BITS 0x0000ffff +#define DMA_INTS1_RESET 0x00000000 +#define DMA_INTS1_MSB 15 +#define DMA_INTS1_LSB 0 +#define DMA_INTS1_ACCESS "WC" +// ============================================================================= +// Register : DMA_TIMER0 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER0_OFFSET 0x00000420 +#define DMA_TIMER0_BITS 0xffffffff +#define DMA_TIMER0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_X_RESET 0x0000 +#define DMA_TIMER0_X_BITS 0xffff0000 +#define DMA_TIMER0_X_MSB 31 +#define DMA_TIMER0_X_LSB 16 +#define DMA_TIMER0_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_Y_RESET 0x0000 +#define DMA_TIMER0_Y_BITS 0x0000ffff +#define DMA_TIMER0_Y_MSB 15 +#define DMA_TIMER0_Y_LSB 0 +#define DMA_TIMER0_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER1 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER1_OFFSET 0x00000424 +#define DMA_TIMER1_BITS 0xffffffff +#define DMA_TIMER1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_X_RESET 0x0000 +#define DMA_TIMER1_X_BITS 0xffff0000 +#define DMA_TIMER1_X_MSB 31 +#define DMA_TIMER1_X_LSB 16 +#define DMA_TIMER1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_Y_RESET 0x0000 +#define DMA_TIMER1_Y_BITS 0x0000ffff +#define DMA_TIMER1_Y_MSB 15 +#define DMA_TIMER1_Y_LSB 0 +#define DMA_TIMER1_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER2 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER2_OFFSET 0x00000428 +#define DMA_TIMER2_BITS 0xffffffff +#define DMA_TIMER2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_X_RESET 0x0000 +#define DMA_TIMER2_X_BITS 0xffff0000 +#define DMA_TIMER2_X_MSB 31 +#define DMA_TIMER2_X_LSB 16 +#define DMA_TIMER2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_Y_RESET 0x0000 +#define DMA_TIMER2_Y_BITS 0x0000ffff +#define DMA_TIMER2_Y_MSB 15 +#define DMA_TIMER2_Y_LSB 0 +#define DMA_TIMER2_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER3 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER3_OFFSET 0x0000042c +#define DMA_TIMER3_BITS 0xffffffff +#define DMA_TIMER3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_X_RESET 0x0000 +#define DMA_TIMER3_X_BITS 0xffff0000 +#define DMA_TIMER3_X_MSB 31 +#define DMA_TIMER3_X_LSB 16 +#define DMA_TIMER3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_Y_RESET 0x0000 +#define DMA_TIMER3_Y_BITS 0x0000ffff +#define DMA_TIMER3_Y_MSB 15 +#define DMA_TIMER3_Y_LSB 0 +#define DMA_TIMER3_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_MULTI_CHAN_TRIGGER +// Description : Trigger one or more channels simultaneously +// Each bit in this register corresponds to a DMA channel. Writing +// a 1 to the relevant bit is the same as writing to that +// channel's trigger register; the channel will start if it is +// currently enabled and not already busy. +#define DMA_MULTI_CHAN_TRIGGER_OFFSET 0x00000430 +#define DMA_MULTI_CHAN_TRIGGER_BITS 0x0000ffff +#define DMA_MULTI_CHAN_TRIGGER_RESET 0x00000000 +#define DMA_MULTI_CHAN_TRIGGER_MSB 15 +#define DMA_MULTI_CHAN_TRIGGER_LSB 0 +#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" +// ============================================================================= +// Register : DMA_SNIFF_CTRL +// Description : Sniffer Control +#define DMA_SNIFF_CTRL_OFFSET 0x00000434 +#define DMA_SNIFF_CTRL_BITS 0x00000fff +#define DMA_SNIFF_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_INV +// Description : If set, the result appears inverted (bitwise complement) when +// read. This does not affect the way the checksum is calculated; +// the result is transformed on-the-fly between the result +// register and the bus. +#define DMA_SNIFF_CTRL_OUT_INV_RESET 0x0 +#define DMA_SNIFF_CTRL_OUT_INV_BITS 0x00000800 +#define DMA_SNIFF_CTRL_OUT_INV_MSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_LSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_REV +// Description : If set, the result appears bit-reversed when read. This does +// not affect the way the checksum is calculated; the result is +// transformed on-the-fly between the result register and the bus. +#define DMA_SNIFF_CTRL_OUT_REV_RESET 0x0 +#define DMA_SNIFF_CTRL_OUT_REV_BITS 0x00000400 +#define DMA_SNIFF_CTRL_OUT_REV_MSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_LSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_BSWAP +// Description : Locally perform a byte reverse on the sniffed data, before +// feeding into checksum. +// +// Note that the sniff hardware is downstream of the DMA channel +// byteswap performed in the read master: if channel CTRL_BSWAP +// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel +// from the sniffer's point of view. +#define DMA_SNIFF_CTRL_BSWAP_RESET 0x0 +#define DMA_SNIFF_CTRL_BSWAP_BITS 0x00000200 +#define DMA_SNIFF_CTRL_BSWAP_MSB 9 +#define DMA_SNIFF_CTRL_BSWAP_LSB 9 +#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_CALC +// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit +// reversed data +// 0x2 -> Calculate a CRC-16-CCITT +// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data +// 0xe -> XOR reduction over all data. == 1 if the total 1 +// population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 +// bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET 0x0 +#define DMA_SNIFF_CTRL_CALC_BITS 0x000001e0 +#define DMA_SNIFF_CTRL_CALC_MSB 8 +#define DMA_SNIFF_CTRL_CALC_LSB 5 +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 0x0 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R 0x1 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 0x2 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R 0x3 +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN 0xe +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM 0xf +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_DMACH +// Description : DMA channel for Sniffer to observe +#define DMA_SNIFF_CTRL_DMACH_RESET 0x0 +#define DMA_SNIFF_CTRL_DMACH_BITS 0x0000001e +#define DMA_SNIFF_CTRL_DMACH_MSB 4 +#define DMA_SNIFF_CTRL_DMACH_LSB 1 +#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_EN +// Description : Enable sniffer +#define DMA_SNIFF_CTRL_EN_RESET 0x0 +#define DMA_SNIFF_CTRL_EN_BITS 0x00000001 +#define DMA_SNIFF_CTRL_EN_MSB 0 +#define DMA_SNIFF_CTRL_EN_LSB 0 +#define DMA_SNIFF_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_SNIFF_DATA +// Description : Data accumulator for sniff hardware +// Write an initial seed value here before starting a DMA transfer +// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will +// update this register each time it observes a read from the +// indicated channel. Once the channel completes, the final result +// can be read from this register. +#define DMA_SNIFF_DATA_OFFSET 0x00000438 +#define DMA_SNIFF_DATA_BITS 0xffffffff +#define DMA_SNIFF_DATA_RESET 0x00000000 +#define DMA_SNIFF_DATA_MSB 31 +#define DMA_SNIFF_DATA_LSB 0 +#define DMA_SNIFF_DATA_ACCESS "RW" +// ============================================================================= +// Register : DMA_FIFO_LEVELS +// Description : Debug RAF, WAF, TDF levels +#define DMA_FIFO_LEVELS_OFFSET 0x00000440 +#define DMA_FIFO_LEVELS_BITS 0x00ffffff +#define DMA_FIFO_LEVELS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_RAF_LVL +// Description : Current Read-Address-FIFO fill level +#define DMA_FIFO_LEVELS_RAF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_RAF_LVL_BITS 0x00ff0000 +#define DMA_FIFO_LEVELS_RAF_LVL_MSB 23 +#define DMA_FIFO_LEVELS_RAF_LVL_LSB 16 +#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_WAF_LVL +// Description : Current Write-Address-FIFO fill level +#define DMA_FIFO_LEVELS_WAF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_WAF_LVL_BITS 0x0000ff00 +#define DMA_FIFO_LEVELS_WAF_LVL_MSB 15 +#define DMA_FIFO_LEVELS_WAF_LVL_LSB 8 +#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_TDF_LVL +// Description : Current Transfer-Data-FIFO fill level +#define DMA_FIFO_LEVELS_TDF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_TDF_LVL_BITS 0x000000ff +#define DMA_FIFO_LEVELS_TDF_LVL_MSB 7 +#define DMA_FIFO_LEVELS_TDF_LVL_LSB 0 +#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CHAN_ABORT +// Description : Abort an in-progress transfer sequence on one or more channels +// Each bit corresponds to a channel. Writing a 1 aborts whatever +// transfer sequence is in progress on that channel. The bit will +// remain high until any in-flight transfers have been flushed +// through the address and data FIFOs. +// +// After writing, this register must be polled until it returns +// all-zero. Until this point, it is unsafe to restart the +// channel. +#define DMA_CHAN_ABORT_OFFSET 0x00000444 +#define DMA_CHAN_ABORT_BITS 0x0000ffff +#define DMA_CHAN_ABORT_RESET 0x00000000 +#define DMA_CHAN_ABORT_MSB 15 +#define DMA_CHAN_ABORT_LSB 0 +#define DMA_CHAN_ABORT_ACCESS "SC" +// ============================================================================= +// Register : DMA_N_CHANNELS +// Description : The number of channels this DMA instance is equipped with. This +// DMA supports up to 16 hardware channels, but can be configured +// with as few as one, to minimise silicon area. +#define DMA_N_CHANNELS_OFFSET 0x00000448 +#define DMA_N_CHANNELS_BITS 0x0000001f +#define DMA_N_CHANNELS_RESET "-" +#define DMA_N_CHANNELS_MSB 4 +#define DMA_N_CHANNELS_LSB 0 +#define DMA_N_CHANNELS_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH0_DBG_CTDREQ_OFFSET 0x00000800 +#define DMA_CH0_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH0_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH0_DBG_CTDREQ_MSB 5 +#define DMA_CH0_DBG_CTDREQ_LSB 0 +#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH0_DBG_TCR_OFFSET 0x00000804 +#define DMA_CH0_DBG_TCR_BITS 0xffffffff +#define DMA_CH0_DBG_TCR_RESET 0x00000000 +#define DMA_CH0_DBG_TCR_MSB 31 +#define DMA_CH0_DBG_TCR_LSB 0 +#define DMA_CH0_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH1_DBG_CTDREQ_OFFSET 0x00000840 +#define DMA_CH1_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH1_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH1_DBG_CTDREQ_MSB 5 +#define DMA_CH1_DBG_CTDREQ_LSB 0 +#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH1_DBG_TCR_OFFSET 0x00000844 +#define DMA_CH1_DBG_TCR_BITS 0xffffffff +#define DMA_CH1_DBG_TCR_RESET 0x00000000 +#define DMA_CH1_DBG_TCR_MSB 31 +#define DMA_CH1_DBG_TCR_LSB 0 +#define DMA_CH1_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH2_DBG_CTDREQ_OFFSET 0x00000880 +#define DMA_CH2_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH2_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH2_DBG_CTDREQ_MSB 5 +#define DMA_CH2_DBG_CTDREQ_LSB 0 +#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH2_DBG_TCR_OFFSET 0x00000884 +#define DMA_CH2_DBG_TCR_BITS 0xffffffff +#define DMA_CH2_DBG_TCR_RESET 0x00000000 +#define DMA_CH2_DBG_TCR_MSB 31 +#define DMA_CH2_DBG_TCR_LSB 0 +#define DMA_CH2_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH3_DBG_CTDREQ_OFFSET 0x000008c0 +#define DMA_CH3_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH3_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH3_DBG_CTDREQ_MSB 5 +#define DMA_CH3_DBG_CTDREQ_LSB 0 +#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH3_DBG_TCR_OFFSET 0x000008c4 +#define DMA_CH3_DBG_TCR_BITS 0xffffffff +#define DMA_CH3_DBG_TCR_RESET 0x00000000 +#define DMA_CH3_DBG_TCR_MSB 31 +#define DMA_CH3_DBG_TCR_LSB 0 +#define DMA_CH3_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH4_DBG_CTDREQ_OFFSET 0x00000900 +#define DMA_CH4_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH4_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH4_DBG_CTDREQ_MSB 5 +#define DMA_CH4_DBG_CTDREQ_LSB 0 +#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH4_DBG_TCR_OFFSET 0x00000904 +#define DMA_CH4_DBG_TCR_BITS 0xffffffff +#define DMA_CH4_DBG_TCR_RESET 0x00000000 +#define DMA_CH4_DBG_TCR_MSB 31 +#define DMA_CH4_DBG_TCR_LSB 0 +#define DMA_CH4_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH5_DBG_CTDREQ_OFFSET 0x00000940 +#define DMA_CH5_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH5_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH5_DBG_CTDREQ_MSB 5 +#define DMA_CH5_DBG_CTDREQ_LSB 0 +#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH5_DBG_TCR_OFFSET 0x00000944 +#define DMA_CH5_DBG_TCR_BITS 0xffffffff +#define DMA_CH5_DBG_TCR_RESET 0x00000000 +#define DMA_CH5_DBG_TCR_MSB 31 +#define DMA_CH5_DBG_TCR_LSB 0 +#define DMA_CH5_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH6_DBG_CTDREQ_OFFSET 0x00000980 +#define DMA_CH6_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH6_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH6_DBG_CTDREQ_MSB 5 +#define DMA_CH6_DBG_CTDREQ_LSB 0 +#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH6_DBG_TCR_OFFSET 0x00000984 +#define DMA_CH6_DBG_TCR_BITS 0xffffffff +#define DMA_CH6_DBG_TCR_RESET 0x00000000 +#define DMA_CH6_DBG_TCR_MSB 31 +#define DMA_CH6_DBG_TCR_LSB 0 +#define DMA_CH6_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH7_DBG_CTDREQ_OFFSET 0x000009c0 +#define DMA_CH7_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH7_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH7_DBG_CTDREQ_MSB 5 +#define DMA_CH7_DBG_CTDREQ_LSB 0 +#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH7_DBG_TCR_OFFSET 0x000009c4 +#define DMA_CH7_DBG_TCR_BITS 0xffffffff +#define DMA_CH7_DBG_TCR_RESET 0x00000000 +#define DMA_CH7_DBG_TCR_MSB 31 +#define DMA_CH7_DBG_TCR_LSB 0 +#define DMA_CH7_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH8_DBG_CTDREQ_OFFSET 0x00000a00 +#define DMA_CH8_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH8_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH8_DBG_CTDREQ_MSB 5 +#define DMA_CH8_DBG_CTDREQ_LSB 0 +#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH8_DBG_TCR_OFFSET 0x00000a04 +#define DMA_CH8_DBG_TCR_BITS 0xffffffff +#define DMA_CH8_DBG_TCR_RESET 0x00000000 +#define DMA_CH8_DBG_TCR_MSB 31 +#define DMA_CH8_DBG_TCR_LSB 0 +#define DMA_CH8_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH9_DBG_CTDREQ_OFFSET 0x00000a40 +#define DMA_CH9_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH9_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH9_DBG_CTDREQ_MSB 5 +#define DMA_CH9_DBG_CTDREQ_LSB 0 +#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH9_DBG_TCR_OFFSET 0x00000a44 +#define DMA_CH9_DBG_TCR_BITS 0xffffffff +#define DMA_CH9_DBG_TCR_RESET 0x00000000 +#define DMA_CH9_DBG_TCR_MSB 31 +#define DMA_CH9_DBG_TCR_LSB 0 +#define DMA_CH9_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH10_DBG_CTDREQ_OFFSET 0x00000a80 +#define DMA_CH10_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH10_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH10_DBG_CTDREQ_MSB 5 +#define DMA_CH10_DBG_CTDREQ_LSB 0 +#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH10_DBG_TCR_OFFSET 0x00000a84 +#define DMA_CH10_DBG_TCR_BITS 0xffffffff +#define DMA_CH10_DBG_TCR_RESET 0x00000000 +#define DMA_CH10_DBG_TCR_MSB 31 +#define DMA_CH10_DBG_TCR_LSB 0 +#define DMA_CH10_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH11_DBG_CTDREQ_OFFSET 0x00000ac0 +#define DMA_CH11_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH11_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH11_DBG_CTDREQ_MSB 5 +#define DMA_CH11_DBG_CTDREQ_LSB 0 +#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH11_DBG_TCR_OFFSET 0x00000ac4 +#define DMA_CH11_DBG_TCR_BITS 0xffffffff +#define DMA_CH11_DBG_TCR_RESET 0x00000000 +#define DMA_CH11_DBG_TCR_MSB 31 +#define DMA_CH11_DBG_TCR_LSB 0 +#define DMA_CH11_DBG_TCR_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_DMA_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h new file mode 100644 index 00000000000..9de9dd5fde5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dreq.h @@ -0,0 +1,50 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _DREQ_H_ +#define _DREQ_H_ + +#define DREQ_PIO0_TX0 0x0 +#define DREQ_PIO0_TX1 0x1 +#define DREQ_PIO0_TX2 0x2 +#define DREQ_PIO0_TX3 0x3 +#define DREQ_PIO0_RX0 0x4 +#define DREQ_PIO0_RX1 0x5 +#define DREQ_PIO0_RX2 0x6 +#define DREQ_PIO0_RX3 0x7 +#define DREQ_PIO1_TX0 0x8 +#define DREQ_PIO1_TX1 0x9 +#define DREQ_PIO1_TX2 0xa +#define DREQ_PIO1_TX3 0xb +#define DREQ_PIO1_RX0 0xc +#define DREQ_PIO1_RX1 0xd +#define DREQ_PIO1_RX2 0xe +#define DREQ_PIO1_RX3 0xf +#define DREQ_SPI0_TX 0x10 +#define DREQ_SPI0_RX 0x11 +#define DREQ_SPI1_TX 0x12 +#define DREQ_SPI1_RX 0x13 +#define DREQ_UART0_TX 0x14 +#define DREQ_UART0_RX 0x15 +#define DREQ_UART1_TX 0x16 +#define DREQ_UART1_RX 0x17 +#define DREQ_PWM_WRAP0 0x18 +#define DREQ_PWM_WRAP1 0x19 +#define DREQ_PWM_WRAP2 0x1a +#define DREQ_PWM_WRAP3 0x1b +#define DREQ_PWM_WRAP4 0x1c +#define DREQ_PWM_WRAP5 0x1d +#define DREQ_PWM_WRAP6 0x1e +#define DREQ_PWM_WRAP7 0x1f +#define DREQ_I2C0_TX 0x20 +#define DREQ_I2C0_RX 0x21 +#define DREQ_I2C1_TX 0x22 +#define DREQ_I2C1_RX 0x23 +#define DREQ_ADC 0x24 +#define DREQ_XIP_STREAM 0x25 +#define DREQ_XIP_SSITX 0x26 +#define DREQ_XIP_SSIRX 0x27 + +#endif // _DREQ_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h new file mode 100644 index 00000000000..c027119a8ef --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h @@ -0,0 +1,2685 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : I2C +// Version : 1 +// Bus type : apb +// Description : DW_apb_i2c address block +// ============================================================================= +#ifndef HARDWARE_REGS_I2C_DEFINED +#define HARDWARE_REGS_I2C_DEFINED +// ============================================================================= +// Register : I2C_IC_CON +// Description : I2C Control Register. This register can be written only when +// the DW_apb_i2c is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// Read/Write Access: - bit 10 is read only. - bit 11 is read only +// - bit 16 is read only - bit 17 is read only - bits 18 and 19 +// are read only. +#define I2C_IC_CON_OFFSET 0x00000000 +#define I2C_IC_CON_BITS 0x000007ff +#define I2C_IC_CON_RESET 0x00000065 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE +// Description : Master issues the STOP_DET interrupt irrespective of whether +// master is active or not +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS 0x00000400 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL +// Description : This bit controls whether DW_apb_i2c should hold the bus when +// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as +// described in the IC_RX_FULL_HLD_BUS_EN parameter. +// +// Reset value: 0x0. +// 0x0 -> Overflow when RX_FIFO is full +// 0x1 -> Hold bus when RX_FIFO is full +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS 0x00000200 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED 0x0 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_TX_EMPTY_CTRL +// Description : This bit controls the generation of the TX_EMPTY interrupt, as +// described in the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0. +// 0x0 -> Default behaviour of TX_EMPTY interrupt +// 0x1 -> Controlled generation of TX_EMPTY interrupt +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0 +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS 0x00000100 +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED 0x0 +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IFADDRESSED +// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when +// it is addressed. - 1'b0: issues the STOP_DET irrespective of +// whether it's addressed or not. Reset value: 0x0 +// +// NOTE: During a general call address, this slave does not issue +// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if +// the slave responds to the general call address by generating +// ACK. The STOP_DET interrupt is generated only when the +// transmitted address matches the slave address (SAR). +// 0x0 -> slave issues STOP_DET intr always +// 0x1 -> slave issues STOP_DET intr only if addressed +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS 0x00000080 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED 0x0 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_SLAVE_DISABLE +// Description : This bit controls whether I2C has its slave disabled, which +// means once the presetn signal is applied, then this bit is set +// and the slave is disabled. +// +// If this bit is set (slave is disabled), DW_apb_i2c functions +// only as a master and does not perform any action that requires +// a slave. +// +// NOTE: Software should ensure that if this bit is written with +// 0, then bit 0 should also be written with a 0. +// 0x0 -> Slave mode is enabled +// 0x1 -> Slave mode is disabled +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1 +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS 0x00000040 +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED 0x0 +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_RESTART_EN +// Description : Determines whether RESTART conditions may be sent when acting +// as a master. Some older slaves do not support handling RESTART +// conditions; however, RESTART conditions are used in several +// DW_apb_i2c operations. When RESTART is disabled, the master is +// prohibited from performing the following functions: - Sending a +// START BYTE - Performing any high-speed mode operation - +// High-speed mode operation - Performing direction changes in +// combined format mode - Performing a read operation with a +// 10-bit address By replacing RESTART condition followed by a +// STOP and a subsequent START condition, split operations are +// broken down into multiple DW_apb_i2c transfers. If the above +// operations are performed, it will result in setting bit 6 +// (TX_ABRT) of the IC_RAW_INTR_STAT register. +// +// Reset value: ENABLED +// 0x0 -> Master restart disabled +// 0x1 -> Master restart enabled +#define I2C_IC_CON_IC_RESTART_EN_RESET 0x1 +#define I2C_IC_CON_IC_RESTART_EN_BITS 0x00000020 +#define I2C_IC_CON_IC_RESTART_EN_MSB 5 +#define I2C_IC_CON_IC_RESTART_EN_LSB 5 +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED 0x0 +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_MASTER +// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or +// 10-bit addressing mode when acting as a master. - 0: 7-bit +// addressing - 1: 10-bit addressing +// 0x0 -> Master 7Bit addressing mode +// 0x1 -> Master 10Bit addressing mode +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET 0x0 +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS 0x00000010 +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS 0x0 +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_SLAVE +// Description : When acting as a slave, this bit controls whether the +// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit +// addressing. The DW_apb_i2c ignores transactions that involve +// 10-bit addressing; for 7-bit addressing, only the lower 7 bits +// of the IC_SAR register are compared. - 1: 10-bit addressing. +// The DW_apb_i2c responds to only 10-bit addressing transfers +// that match the full 10 bits of the IC_SAR register. +// 0x0 -> Slave 7Bit addressing +// 0x1 -> Slave 10Bit addressing +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x0 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS 0x00000008 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS 0x0 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_SPEED +// Description : These bits control at which speed the DW_apb_i2c operates; its +// setting is relevant only if one is operating the DW_apb_i2c in +// master mode. Hardware protects against illegal values being +// programmed by software. These bits must be programmed +// appropriately for slave mode also, as it is used to capture +// correct value of spike filter as per the speed mode. +// +// This register should be programmed only with a value in the +// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates +// this register with the value of IC_MAX_SPEED_MODE. +// +// 1: standard mode (100 kbit/s) +// +// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) +// +// 3: high speed mode (3.4 Mbit/s) +// +// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 +// 0x1 -> Standard Speed mode of operation +// 0x2 -> Fast or Fast Plus mode of operation +// 0x3 -> High Speed mode of operation +#define I2C_IC_CON_SPEED_RESET 0x2 +#define I2C_IC_CON_SPEED_BITS 0x00000006 +#define I2C_IC_CON_SPEED_MSB 2 +#define I2C_IC_CON_SPEED_LSB 1 +#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_VALUE_STANDARD 0x1 +#define I2C_IC_CON_SPEED_VALUE_FAST 0x2 +#define I2C_IC_CON_SPEED_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_MASTER_MODE +// Description : This bit controls whether the DW_apb_i2c master is enabled. +// +// NOTE: Software should ensure that if this bit is written with +// '1' then bit 6 should also be written with a '1'. +// 0x0 -> Master mode is disabled +// 0x1 -> Master mode is enabled +#define I2C_IC_CON_MASTER_MODE_RESET 0x1 +#define I2C_IC_CON_MASTER_MODE_BITS 0x00000001 +#define I2C_IC_CON_MASTER_MODE_MSB 0 +#define I2C_IC_CON_MASTER_MODE_LSB 0 +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED 0x0 +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_TAR +// Description : I2C Target Address Register +// +// This register is 12 bits wide, and bits 31:12 are reserved. +// This register can be written to only when IC_ENABLE[0] is set +// to 0. +// +// Note: If the software or application is aware that the +// DW_apb_i2c is not using the TAR address for the pending +// commands in the Tx FIFO, then it is possible to update the TAR +// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - +// It is not necessary to perform any write to this register if +// DW_apb_i2c is enabled as an I2C slave only. +#define I2C_IC_TAR_OFFSET 0x00000004 +#define I2C_IC_TAR_BITS 0x00000fff +#define I2C_IC_TAR_RESET 0x00000055 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_SPECIAL +// Description : This bit indicates whether software performs a Device-ID or +// General Call or START BYTE command. - 0: ignore bit 10 +// GC_OR_START and use IC_TAR normally - 1: perform special I2C +// command as specified in Device_ID or GC_OR_START bit Reset +// value: 0x0 +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE +// transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE +// transmission +#define I2C_IC_TAR_SPECIAL_RESET 0x0 +#define I2C_IC_TAR_SPECIAL_BITS 0x00000800 +#define I2C_IC_TAR_SPECIAL_MSB 11 +#define I2C_IC_TAR_SPECIAL_LSB 11 +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED 0x0 +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_GC_OR_START +// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to +// 0, then this bit indicates whether a General Call or START byte +// command is to be performed by the DW_apb_i2c. - 0: General Call +// Address - after issuing a General Call, only writes may be +// performed. Attempting to issue a read command results in +// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The +// DW_apb_i2c remains in General Call mode until the SPECIAL bit +// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 +// 0x0 -> GENERAL_CALL byte transmission +// 0x1 -> START byte transmission +#define I2C_IC_TAR_GC_OR_START_RESET 0x0 +#define I2C_IC_TAR_GC_OR_START_BITS 0x00000400 +#define I2C_IC_TAR_GC_OR_START_MSB 10 +#define I2C_IC_TAR_GC_OR_START_LSB 10 +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL 0x0 +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_IC_TAR +// Description : This is the target address for any master transaction. When +// transmitting a General Call, these bits are ignored. To +// generate a START BYTE, the CPU needs to write only once into +// these bits. +// +// If the IC_TAR and IC_SAR are the same, loopback exists but the +// FIFOs are shared between master and slave, so full loopback is +// not feasible. Only one direction loopback mode is supported +// (simplex), not duplex. A master cannot transmit to itself; it +// can transmit to only a slave. +#define I2C_IC_TAR_IC_TAR_RESET 0x055 +#define I2C_IC_TAR_IC_TAR_BITS 0x000003ff +#define I2C_IC_TAR_IC_TAR_MSB 9 +#define I2C_IC_TAR_IC_TAR_LSB 0 +#define I2C_IC_TAR_IC_TAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SAR +// Description : I2C Slave Address Register +#define I2C_IC_SAR_OFFSET 0x00000008 +#define I2C_IC_SAR_BITS 0x000003ff +#define I2C_IC_SAR_RESET 0x00000055 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SAR_IC_SAR +// Description : The IC_SAR holds the slave address when the I2C is operating as +// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// Note: The default values cannot be any of the reserved address +// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct +// operation of the device is not guaranteed if you program the +// IC_SAR or IC_TAR to a reserved value. Refer to +// <> for a complete list of these +// reserved values. +#define I2C_IC_SAR_IC_SAR_RESET 0x055 +#define I2C_IC_SAR_IC_SAR_BITS 0x000003ff +#define I2C_IC_SAR_IC_SAR_MSB 9 +#define I2C_IC_SAR_IC_SAR_LSB 0 +#define I2C_IC_SAR_IC_SAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DATA_CMD +// Description : I2C Rx/Tx Data Buffer and Command Register; this is the +// register the CPU writes to when filling the TX FIFO and the CPU +// reads from when retrieving bytes from RX FIFO. +// +// The size of the register changes as follows: +// +// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits +// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when +// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when +// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c +// to continue acknowledging reads, a read command should be +// written for every byte that is to be received; otherwise the +// DW_apb_i2c will stop acknowledging. +#define I2C_IC_DATA_CMD_OFFSET 0x00000010 +#define I2C_IC_DATA_CMD_BITS 0x00000fff +#define I2C_IC_DATA_CMD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE +// Description : Indicates the first data byte received after the address phase +// for receive transfer in Master receiver or Slave receiver mode. +// +// Reset value : 0x0 +// +// NOTE: In case of APB_DATA_WIDTH=8, +// +// 1. The user has to perform two APB Reads to IC_DATA_CMD in +// order to get status on 11 bit. +// +// 2. In order to read the 11 bit, the user has to perform the +// first data byte read [7:0] (offset 0x10) and then perform the +// second read [15:8] (offset 0x11) in order to know the status of +// 11 bit (whether the data received in previous read is a first +// data byte or not). +// +// 3. The 11th bit is an optional read field, user can ignore 2nd +// byte read [15:8] (offset 0x11) if not interested in +// FIRST_DATA_BYTE status. +// 0x0 -> Sequential data byte received +// 0x1 -> Non sequential data byte received +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS 0x00000800 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE 0x0 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_RESTART +// Description : This bit controls whether a RESTART is issued before the byte +// is sent or received. +// +// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data +// is sent/received (according to the value of CMD), regardless of +// whether or not the transfer direction is changing from the +// previous command; if IC_RESTART_EN is 0, a STOP followed by a +// START is issued instead. +// +// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the +// transfer direction is changing from the previous command; if +// IC_RESTART_EN is 0, a STOP followed by a START is issued +// instead. +// +// Reset value: 0x0 +// 0x0 -> Don't Issue RESTART before this command +// 0x1 -> Issue RESTART before this command +#define I2C_IC_DATA_CMD_RESTART_RESET 0x0 +#define I2C_IC_DATA_CMD_RESTART_BITS 0x00000400 +#define I2C_IC_DATA_CMD_RESTART_MSB 10 +#define I2C_IC_DATA_CMD_RESTART_LSB 10 +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE 0x0 +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_STOP +// Description : This bit controls whether a STOP is issued after the byte is +// sent or received. +// +// - 1 - STOP is issued after this byte, regardless of whether or +// not the Tx FIFO is empty. If the Tx FIFO is not empty, the +// master immediately tries to start a new transfer by issuing a +// START and arbitrating for the bus. - 0 - STOP is not issued +// after this byte, regardless of whether or not the Tx FIFO is +// empty. If the Tx FIFO is not empty, the master continues the +// current transfer by sending/receiving data bytes according to +// the value of the CMD bit. If the Tx FIFO is empty, the master +// holds the SCL line low and stalls the bus until a new command +// is available in the Tx FIFO. Reset value: 0x0 +// 0x0 -> Don't Issue STOP after this command +// 0x1 -> Issue STOP after this command +#define I2C_IC_DATA_CMD_STOP_RESET 0x0 +#define I2C_IC_DATA_CMD_STOP_BITS 0x00000200 +#define I2C_IC_DATA_CMD_STOP_MSB 9 +#define I2C_IC_DATA_CMD_STOP_LSB 9 +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE 0x0 +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_CMD +// Description : This bit controls whether a read or a write is performed. This +// bit does not control the direction when the DW_apb_i2con acts +// as a slave. It controls only the direction when it acts as a +// master. +// +// When a command is entered in the TX FIFO, this bit +// distinguishes the write and read commands. In slave-receiver +// mode, this bit is a 'don't care' because writes to this +// register are not required. In slave-transmitter mode, a '0' +// indicates that the data in IC_DATA_CMD is to be transmitted. +// +// When programming this bit, you should remember the following: +// attempting to perform a read operation after a General Call +// command has been sent results in a TX_ABRT interrupt (bit 6 of +// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the +// IC_TAR register has been cleared. If a '1' is written to this +// bit after receiving a RD_REQ interrupt, then a TX_ABRT +// interrupt occurs. +// +// Reset value: 0x0 +// 0x0 -> Master Write Command +// 0x1 -> Master Read Command +#define I2C_IC_DATA_CMD_CMD_RESET 0x0 +#define I2C_IC_DATA_CMD_CMD_BITS 0x00000100 +#define I2C_IC_DATA_CMD_CMD_MSB 8 +#define I2C_IC_DATA_CMD_CMD_LSB 8 +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE 0x0 +#define I2C_IC_DATA_CMD_CMD_VALUE_READ 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_DAT +// Description : This register contains the data to be transmitted or received +// on the I2C bus. If you are writing to this register and want to +// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. +// However, when you read this register, these bits return the +// value of data received on the DW_apb_i2c interface. +// +// Reset value: 0x0 +#define I2C_IC_DATA_CMD_DAT_RESET 0x00 +#define I2C_IC_DATA_CMD_DAT_BITS 0x000000ff +#define I2C_IC_DATA_CMD_DAT_MSB 7 +#define I2C_IC_DATA_CMD_DAT_LSB 0 +#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_HCNT +// Description : Standard Speed I2C Clock SCL High Count Register +#define I2C_IC_SS_SCL_HCNT_OFFSET 0x00000014 +#define I2C_IC_SS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_HCNT_RESET 0x00000028 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration'. +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +// +// NOTE: This register must not be programmed to a value higher +// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an +// I2C bus idle condition when this counter reaches a value of +// IC_SS_SCL_HCNT + 10. +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x0028 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_LCNT +// Description : Standard Speed I2C Clock SCL Low Count Register +#define I2C_IC_SS_SCL_LCNT_OFFSET 0x00000018 +#define I2C_IC_SS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_LCNT_RESET 0x0000002f +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration' +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted, results in 8 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of +// DW_apb_i2c. The lower byte must be programmed first, and then +// the upper byte is programmed. +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x002f +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_HCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register +#define I2C_IC_FS_SCL_HCNT_OFFSET 0x0000001c +#define I2C_IC_FS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_HCNT_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for fast mode or fast mode plus. It +// is used in high-speed mode to send the Master Code and START +// BYTE or General CALL. For more information, refer to 'IC_CLK +// Frequency Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. This register can be written only +// when the I2C interface is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH == 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x0006 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_LCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register +#define I2C_IC_FS_SCL_LCNT_OFFSET 0x00000020 +#define I2C_IC_FS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_LCNT_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for fast speed. It is used in +// high-speed mode to send the Master Code and START BYTE or +// General CALL. For more information, refer to 'IC_CLK Frequency +// Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted results in 8 being +// set. For designs with APB_DATA_WIDTH = 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. If the value is less than 8 then the +// count value gets changed to 8. +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x000d +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_INTR_STAT +// Description : I2C Interrupt Status Register +// +// Each bit in this register has a corresponding mask bit in the +// IC_INTR_MASK register. These bits are cleared by reading the +// matching interrupt clear register. The unmasked raw versions of +// these bits are available in the IC_RAW_INTR_STAT register. +#define I2C_IC_INTR_STAT_OFFSET 0x0000002c +#define I2C_IC_INTR_STAT_BITS 0x00003fff +#define I2C_IC_INTR_STAT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_MASTER_ON_HOLD bit. +// +// Reset value: 0x0 +// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive +// 0x1 -> R_MASTER_ON_HOLD interrupt is active +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS 0x00002000 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RESTART_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_RESTART_DET bit. +// +// Reset value: 0x0 +// 0x0 -> R_RESTART_DET interrupt is inactive +// 0x1 -> R_RESTART_DET interrupt is active +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS 0x00001000 +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_GEN_CALL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_GEN_CALL interrupt is inactive +// 0x1 -> R_GEN_CALL interrupt is active +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0 +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS 0x00000800 +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_START_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_START_DET interrupt is inactive +// 0x1 -> R_START_DET interrupt is active +#define I2C_IC_INTR_STAT_R_START_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_START_DET_BITS 0x00000400 +#define I2C_IC_INTR_STAT_R_START_DET_MSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_LSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_STOP_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_STOP_DET interrupt is inactive +// 0x1 -> R_STOP_DET interrupt is active +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS 0x00000200 +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_ACTIVITY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_ACTIVITY interrupt is inactive +// 0x1 -> R_ACTIVITY interrupt is active +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0 +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS 0x00000100 +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_DONE +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_DONE interrupt is inactive +// 0x1 -> R_RX_DONE interrupt is active +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS 0x00000080 +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_ABRT +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_ABRT interrupt is inactive +// 0x1 -> R_TX_ABRT interrupt is active +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS 0x00000040 +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RD_REQ +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RD_REQ interrupt is inactive +// 0x1 -> R_RD_REQ interrupt is active +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS 0x00000020 +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_EMPTY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_EMPTY interrupt is inactive +// 0x1 -> R_TX_EMPTY interrupt is active +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_OVER interrupt is inactive +// 0x1 -> R_TX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS 0x00000008 +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_FULL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_FULL interrupt is inactive +// 0x1 -> R_RX_FULL interrupt is active +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS 0x00000004 +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_OVER interrupt is inactive +// 0x1 -> R_RX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS 0x00000002 +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_UNDER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER +// bit. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS 0x00000001 +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_INTR_MASK +// Description : I2C Interrupt Mask Register. +// +// These bits mask their corresponding interrupt status bits. This +// register is active low; a value of 0 masks the interrupt, +// whereas a value of 1 unmasks the interrupt. +#define I2C_IC_INTR_MASK_OFFSET 0x00000030 +#define I2C_IC_INTR_MASK_BITS 0x00003fff +#define I2C_IC_INTR_MASK_RESET 0x000008ff +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY +// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD +// interrupt in IC_INTR_STAT register. +// +// Reset value: 0x0 +// 0x0 -> MASTER_ON_HOLD interrupt is masked +// 0x1 -> MASTER_ON_HOLD interrupt is unmasked +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET 0x0 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS 0x00002000 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB 13 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB 13 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO" +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RESTART_DET +// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is masked +// 0x1 -> RESTART_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS 0x00001000 +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_GEN_CALL +// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> GEN_CALL interrupt is masked +// 0x1 -> GEN_CALL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1 +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS 0x00000800 +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_START_DET +// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is masked +// 0x1 -> START_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_START_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_START_DET_BITS 0x00000400 +#define I2C_IC_INTR_MASK_M_START_DET_MSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_LSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_STOP_DET +// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is masked +// 0x1 -> STOP_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS 0x00000200 +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_ACTIVITY +// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> ACTIVITY interrupt is masked +// 0x1 -> ACTIVITY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0 +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS 0x00000100 +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_DONE +// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_DONE interrupt is masked +// 0x1 -> RX_DONE interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS 0x00000080 +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_ABRT +// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_ABORT interrupt is masked +// 0x1 -> TX_ABORT interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS 0x00000040 +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RD_REQ +// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. +// +// Reset value: 0x1 +// 0x0 -> RD_REQ interrupt is masked +// 0x1 -> RD_REQ interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS 0x00000020 +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_EMPTY +// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_EMPTY interrupt is masked +// 0x1 -> TX_EMPTY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_OVER +// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_OVER interrupt is masked +// 0x1 -> TX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS 0x00000008 +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_FULL +// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_FULL interrupt is masked +// 0x1 -> RX_FULL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS 0x00000004 +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_OVER +// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_OVER interrupt is masked +// 0x1 -> RX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS 0x00000002 +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_UNDER +// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_UNDER interrupt is masked +// 0x1 -> RX_UNDER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS 0x00000001 +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED 0x1 +// ============================================================================= +// Register : I2C_IC_RAW_INTR_STAT +// Description : I2C Raw Interrupt Status Register +// +// Unlike the IC_INTR_STAT register, these bits are not masked so +// they always show the true status of the DW_apb_i2c. +#define I2C_IC_RAW_INTR_STAT_OFFSET 0x00000034 +#define I2C_IC_RAW_INTR_STAT_BITS 0x00003fff +#define I2C_IC_RAW_INTR_STAT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD +// Description : Indicates whether master is holding the bus and TX FIFO is +// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and +// IC_EMPTYFIFO_HOLD_MASTER_EN=1. +// +// Reset value: 0x0 +// 0x0 -> MASTER_ON_HOLD interrupt is inactive +// 0x1 -> MASTER_ON_HOLD interrupt is active +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS 0x00002000 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET +// Description : Indicates whether a RESTART condition has occurred on the I2C +// interface when DW_apb_i2c is operating in Slave mode and the +// slave is being addressed. Enabled only when +// IC_SLV_RESTART_DET_EN=1. +// +// Note: However, in high-speed mode or during a START BYTE +// transfer, the RESTART comes before the address field as per the +// I2C protocol. In this case, the slave is not the addressed +// slave when the RESTART is issued, therefore DW_apb_i2c does not +// generate the RESTART_DET interrupt. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is inactive +// 0x1 -> RESTART_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS 0x00001000 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL +// Description : Set only when a General Call address is received and it is +// acknowledged. It stays set until it is cleared either by +// disabling DW_apb_i2c or when the CPU reads bit 0 of the +// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data +// in the Rx buffer. +// +// Reset value: 0x0 +// 0x0 -> GEN_CALL interrupt is inactive +// 0x1 -> GEN_CALL interrupt is active +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS 0x00000800 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_START_DET +// Description : Indicates whether a START or RESTART condition has occurred on +// the I2C interface regardless of whether DW_apb_i2c is operating +// in slave or master mode. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is inactive +// 0x1 -> START_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS 0x00000400 +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_STOP_DET +// Description : Indicates whether a STOP condition has occurred on the I2C +// interface regardless of whether DW_apb_i2c is operating in +// slave or master mode. +// +// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the +// STOP_DET interrupt will be issued only if slave is addressed. +// Note: During a general call address, this slave does not issue +// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the +// slave responds to the general call address by generating ACK. +// The STOP_DET interrupt is generated only when the transmitted +// address matches the slave address (SAR). - If IC_CON[7]=1'b0 +// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued +// irrespective of whether it is being addressed. In Master Mode: +// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET +// interrupt will be issued only if Master is active. - If +// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt +// will be issued irrespective of whether master is active or not. +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is inactive +// 0x1 -> STOP_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS 0x00000200 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY +// Description : This bit captures DW_apb_i2c activity and stays set until it is +// cleared. There are four ways to clear it: - Disabling the +// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the +// IC_CLR_INTR register - System reset Once this bit is set, it +// stays set unless one of the four methods is used to clear it. +// Even if the DW_apb_i2c module is idle, this bit remains set +// until cleared, indicating that there was activity on the bus. +// +// Reset value: 0x0 +// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive +// 0x1 -> RAW_INTR_ACTIVITY interrupt is active +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS 0x00000100 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_DONE +// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit +// is set to 1 if the master does not acknowledge a transmitted +// byte. This occurs on the last byte of the transmission, +// indicating that the transmission is done. +// +// Reset value: 0x0 +// 0x0 -> RX_DONE interrupt is inactive +// 0x1 -> RX_DONE interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS 0x00000080 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT +// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is +// unable to complete the intended actions on the contents of the +// transmit FIFO. This situation can occur both as an I2C master +// or an I2C slave, and is referred to as a 'transmit abort'. When +// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates +// the reason why the transmit abort takes places. +// +// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and +// RX_FIFO whenever there is a transmit abort caused by any of the +// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs +// remains in this flushed state until the register IC_CLR_TX_ABRT +// is read. Once this read is performed, the Tx FIFO is then ready +// to accept more data bytes from the APB interface. +// +// Reset value: 0x0 +// 0x0 -> TX_ABRT interrupt is inactive +// 0x1 -> TX_ABRT interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS 0x00000040 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RD_REQ +// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and +// another I2C master is attempting to read data from DW_apb_i2c. +// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until +// this interrupt is serviced, which means that the slave has been +// addressed by a remote master that is asking for data to be +// transferred. The processor must respond to this interrupt and +// then write the requested data to the IC_DATA_CMD register. This +// bit is set to 0 just after the processor reads the +// IC_CLR_RD_REQ register. +// +// Reset value: 0x0 +// 0x0 -> RD_REQ interrupt is inactive +// 0x1 -> RD_REQ interrupt is active +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS 0x00000020 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY +// Description : The behavior of the TX_EMPTY interrupt status differs based on +// the TX_EMPTY_CTRL selection in the IC_CON register. - When +// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit +// buffer is at or below the threshold value set in the IC_TX_TL +// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when +// the transmit buffer is at or below the threshold value set in +// the IC_TX_TL register and the transmission of the address/data +// from the internal shift register for the most recently popped +// command is completed. It is automatically cleared by hardware +// when the buffer level goes above the threshold. When +// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in +// reset. There the TX FIFO looks like it has no data within it, +// so this bit is set to 1, provided there is activity in the +// master or slave state machines. When there is no longer any +// activity, then with ic_en=0, this bit is set to 0. +// +// Reset value: 0x0. +// 0x0 -> TX_EMPTY interrupt is inactive +// 0x1 -> TX_EMPTY interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_OVER +// Description : Set during transmit if the transmit buffer is filled to +// IC_TX_BUFFER_DEPTH and the processor attempts to issue another +// I2C command by writing to the IC_DATA_CMD register. When the +// module is disabled, this bit keeps its level until the master +// or slave state machines go into idle, and when ic_en goes to 0, +// this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> TX_OVER interrupt is inactive +// 0x1 -> TX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS 0x00000008 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_FULL +// Description : Set when the receive buffer reaches or goes above the RX_TL +// threshold in the IC_RX_TL register. It is automatically cleared +// by hardware when buffer level goes below the threshold. If the +// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and +// held in reset; therefore the RX FIFO is not full. So this bit +// is cleared once the IC_ENABLE bit 0 is programmed with a 0, +// regardless of the activity that continues. +// +// Reset value: 0x0 +// 0x0 -> RX_FULL interrupt is inactive +// 0x1 -> RX_FULL interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS 0x00000004 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_OVER +// Description : Set if the receive buffer is completely filled to +// IC_RX_BUFFER_DEPTH and an additional byte is received from an +// external I2C device. The DW_apb_i2c acknowledges this, but any +// data bytes received after the FIFO is full are lost. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) +// is programmed to HIGH, then the RX_OVER interrupt never occurs, +// because the Rx FIFO never overflows. +// +// Reset value: 0x0 +// 0x0 -> RX_OVER interrupt is inactive +// 0x1 -> RX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS 0x00000002 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER +// Description : Set if the processor attempts to read the receive buffer when +// it is empty by reading from the IC_DATA_CMD register. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS 0x00000001 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_RX_TL +// Description : I2C Receive FIFO Threshold Register +#define I2C_IC_RX_TL_OFFSET 0x00000038 +#define I2C_IC_RX_TL_BITS 0x000000ff +#define I2C_IC_RX_TL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RX_TL_RX_TL +// Description : Receive FIFO Threshold Level. +// +// Controls the level of entries (or above) that triggers the +// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that +// hardware does not allow this value to be set to a value larger +// than the depth of the buffer. If an attempt is made to do that, +// the actual value set will be the maximum depth of the buffer. A +// value of 0 sets the threshold for 1 entry, and a value of 255 +// sets the threshold for 256 entries. +#define I2C_IC_RX_TL_RX_TL_RESET 0x00 +#define I2C_IC_RX_TL_RX_TL_BITS 0x000000ff +#define I2C_IC_RX_TL_RX_TL_MSB 7 +#define I2C_IC_RX_TL_RX_TL_LSB 0 +#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_TL +// Description : I2C Transmit FIFO Threshold Register +#define I2C_IC_TX_TL_OFFSET 0x0000003c +#define I2C_IC_TX_TL_BITS 0x000000ff +#define I2C_IC_TX_TL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_TL_TX_TL +// Description : Transmit FIFO Threshold Level. +// +// Controls the level of entries (or below) that trigger the +// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that it +// may not be set to value larger than the depth of the buffer. If +// an attempt is made to do that, the actual value set will be the +// maximum depth of the buffer. A value of 0 sets the threshold +// for 0 entries, and a value of 255 sets the threshold for 255 +// entries. +#define I2C_IC_TX_TL_TX_TL_RESET 0x00 +#define I2C_IC_TX_TL_TX_TL_BITS 0x000000ff +#define I2C_IC_TX_TL_TX_TL_MSB 7 +#define I2C_IC_TX_TL_TX_TL_LSB 0 +#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_INTR +// Description : Clear Combined and Individual Interrupt Register +#define I2C_IC_CLR_INTR_OFFSET 0x00000040 +#define I2C_IC_CLR_INTR_BITS 0x00000001 +#define I2C_IC_CLR_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_INTR_CLR_INTR +// Description : Read this register to clear the combined interrupt, all +// individual interrupts, and the IC_TX_ABRT_SOURCE register. This +// bit does not clear hardware clearable interrupts but software +// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE +// register for an exception to clearing IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_BITS 0x00000001 +#define I2C_IC_CLR_INTR_CLR_INTR_MSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_LSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_UNDER +// Description : Clear RX_UNDER Interrupt Register +#define I2C_IC_CLR_RX_UNDER_OFFSET 0x00000044 +#define I2C_IC_CLR_RX_UNDER_BITS 0x00000001 +#define I2C_IC_CLR_RX_UNDER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER +// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS 0x00000001 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_OVER +// Description : Clear RX_OVER Interrupt Register +#define I2C_IC_CLR_RX_OVER_OFFSET 0x00000048 +#define I2C_IC_CLR_RX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_RX_OVER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER +// Description : Read this register to clear the RX_OVER interrupt (bit 1) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_OVER +// Description : Clear TX_OVER Interrupt Register +#define I2C_IC_CLR_TX_OVER_OFFSET 0x0000004c +#define I2C_IC_CLR_TX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_TX_OVER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER +// Description : Read this register to clear the TX_OVER interrupt (bit 3) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RD_REQ +// Description : Clear RD_REQ Interrupt Register +#define I2C_IC_CLR_RD_REQ_OFFSET 0x00000050 +#define I2C_IC_CLR_RD_REQ_BITS 0x00000001 +#define I2C_IC_CLR_RD_REQ_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ +// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS 0x00000001 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_ABRT +// Description : Clear TX_ABRT Interrupt Register +#define I2C_IC_CLR_TX_ABRT_OFFSET 0x00000054 +#define I2C_IC_CLR_TX_ABRT_BITS 0x00000001 +#define I2C_IC_CLR_TX_ABRT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT +// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of +// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE +// register. This also releases the TX FIFO from the flushed/reset +// state, allowing more writes to the TX FIFO. Refer to Bit 9 of +// the IC_TX_ABRT_SOURCE register for an exception to clearing +// IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS 0x00000001 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_DONE +// Description : Clear RX_DONE Interrupt Register +#define I2C_IC_CLR_RX_DONE_OFFSET 0x00000058 +#define I2C_IC_CLR_RX_DONE_BITS 0x00000001 +#define I2C_IC_CLR_RX_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE +// Description : Read this register to clear the RX_DONE interrupt (bit 7) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS 0x00000001 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_ACTIVITY +// Description : Clear ACTIVITY Interrupt Register +#define I2C_IC_CLR_ACTIVITY_OFFSET 0x0000005c +#define I2C_IC_CLR_ACTIVITY_BITS 0x00000001 +#define I2C_IC_CLR_ACTIVITY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY +// Description : Reading this register clears the ACTIVITY interrupt if the I2C +// is not active anymore. If the I2C module is still active on the +// bus, the ACTIVITY interrupt bit continues to be set. It is +// automatically cleared by hardware if the module is disabled and +// if there is no further activity on the bus. The value read from +// this register to get status of the ACTIVITY interrupt (bit 8) +// of the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS 0x00000001 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_STOP_DET +// Description : Clear STOP_DET Interrupt Register +#define I2C_IC_CLR_STOP_DET_OFFSET 0x00000060 +#define I2C_IC_CLR_STOP_DET_BITS 0x00000001 +#define I2C_IC_CLR_STOP_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET +// Description : Read this register to clear the STOP_DET interrupt (bit 9) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS 0x00000001 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_START_DET +// Description : Clear START_DET Interrupt Register +#define I2C_IC_CLR_START_DET_OFFSET 0x00000064 +#define I2C_IC_CLR_START_DET_BITS 0x00000001 +#define I2C_IC_CLR_START_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_START_DET_CLR_START_DET +// Description : Read this register to clear the START_DET interrupt (bit 10) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS 0x00000001 +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_GEN_CALL +// Description : Clear GEN_CALL Interrupt Register +#define I2C_IC_CLR_GEN_CALL_OFFSET 0x00000068 +#define I2C_IC_CLR_GEN_CALL_BITS 0x00000001 +#define I2C_IC_CLR_GEN_CALL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL +// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS 0x00000001 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_ENABLE +// Description : I2C Enable Register +#define I2C_IC_ENABLE_OFFSET 0x0000006c +#define I2C_IC_ENABLE_BITS 0x00000007 +#define I2C_IC_ENABLE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_TX_CMD_BLOCK +// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C +// bus even if Tx FIFO has data to transmit. - 1'b0: The +// transmission of data starts on I2C bus automatically, as soon +// as the first data is available in the Tx FIFO. Note: To block +// the execution of Master commands, set the TX_CMD_BLOCK bit only +// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle +// state (IC_STATUS[5] == 0). Any further commands put in the Tx +// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset +// value: IC_TX_CMD_BLOCK_DEFAULT +// 0x0 -> Tx Command execution not blocked +// 0x1 -> Tx Command execution blocked +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS 0x00000004 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED 0x0 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ABORT +// Description : When set, the controller initiates the transfer abort. - 0: +// ABORT not initiated or ABORT done - 1: ABORT operation in +// progress The software can abort the I2C transfer in master mode +// by setting this bit. The software can set this bit only when +// ENABLE is already set; otherwise, the controller ignores any +// write to ABORT bit. The software cannot clear the ABORT bit +// once set. In response to an ABORT, the controller issues a STOP +// and flushes the Tx FIFO after completing the current transfer, +// then sets the TX_ABORT interrupt after the abort operation. The +// ABORT bit is cleared automatically after the abort operation. +// +// For a detailed description on how to abort I2C transfers, refer +// to 'Aborting I2C Transfers'. +// +// Reset value: 0x0 +// 0x0 -> ABORT operation not in progress +// 0x1 -> ABORT operation in progress +#define I2C_IC_ENABLE_ABORT_RESET 0x0 +#define I2C_IC_ENABLE_ABORT_BITS 0x00000002 +#define I2C_IC_ENABLE_ABORT_MSB 1 +#define I2C_IC_ENABLE_ABORT_LSB 1 +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE 0x0 +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ENABLE +// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables +// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: +// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is +// active. However, it is important that care be taken to ensure +// that DW_apb_i2c is disabled properly. A recommended procedure +// is described in 'Disabling DW_apb_i2c'. +// +// When DW_apb_i2c is disabled, the following occurs: - The TX +// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT +// register are still active until DW_apb_i2c goes into IDLE +// state. If the module is transmitting, it stops as well as +// deletes the contents of the transmit buffer after the current +// transfer is complete. If the module is receiving, the +// DW_apb_i2c stops the current transfer at the end of the current +// byte and does not acknowledge the transfer. +// +// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE +// parameter set to asynchronous (1), there is a two ic_clk delay +// when enabling or disabling the DW_apb_i2c. For a detailed +// description on how to disable DW_apb_i2c, refer to 'Disabling +// DW_apb_i2c' +// +// Reset value: 0x0 +// 0x0 -> I2C is disabled +// 0x1 -> I2C is enabled +#define I2C_IC_ENABLE_ENABLE_RESET 0x0 +#define I2C_IC_ENABLE_ENABLE_BITS 0x00000001 +#define I2C_IC_ENABLE_ENABLE_MSB 0 +#define I2C_IC_ENABLE_ENABLE_LSB 0 +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED 0x0 +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_STATUS +// Description : I2C Status Register +// +// This is a read-only register used to indicate the current +// transfer status and FIFO status. The status register may be +// read at any time. None of the bits in this register request an +// interrupt. +// +// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE +// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set +// to 0 When the master or slave state machines goes to idle and +// ic_en=0: - Bits 5 and 6 are set to 0 +#define I2C_IC_STATUS_OFFSET 0x00000070 +#define I2C_IC_STATUS_BITS 0x0000007f +#define I2C_IC_STATUS_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_SLV_ACTIVITY +// Description : Slave FSM Activity Status. When the Slave Finite State Machine +// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM +// is in IDLE state so the Slave part of DW_apb_i2c is not Active +// - 1: Slave FSM is not in IDLE state so the Slave part of +// DW_apb_i2c is Active Reset value: 0x0 +// 0x0 -> Slave is idle +// 0x1 -> Slave not idle +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS 0x00000040 +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE 0x0 +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_MST_ACTIVITY +// Description : Master FSM Activity Status. When the Master Finite State +// Machine (FSM) is not in the IDLE state, this bit is set. - 0: +// Master FSM is in IDLE state so the Master part of DW_apb_i2c is +// not Active - 1: Master FSM is not in IDLE state so the Master +// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, +// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. +// +// Reset value: 0x0 +// 0x0 -> Master is idle +// 0x1 -> Master not idle +#define I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_MST_ACTIVITY_BITS 0x00000020 +#define I2C_IC_STATUS_MST_ACTIVITY_MSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_LSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE 0x0 +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFF +// Description : Receive FIFO Completely Full. When the receive FIFO is +// completely full, this bit is set. When the receive FIFO +// contains one or more empty location, this bit is cleared. - 0: +// Receive FIFO is not full - 1: Receive FIFO is full Reset value: +// 0x0 +// 0x0 -> Rx FIFO not full +// 0x1 -> Rx FIFO is full +#define I2C_IC_STATUS_RFF_RESET 0x0 +#define I2C_IC_STATUS_RFF_BITS 0x00000010 +#define I2C_IC_STATUS_RFF_MSB 4 +#define I2C_IC_STATUS_RFF_LSB 4 +#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL 0x0 +#define I2C_IC_STATUS_RFF_VALUE_FULL 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFNE +// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO +// contains one or more entries; it is cleared when the receive +// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is +// not empty Reset value: 0x0 +// 0x0 -> Rx FIFO is empty +// 0x1 -> Rx FIFO not empty +#define I2C_IC_STATUS_RFNE_RESET 0x0 +#define I2C_IC_STATUS_RFNE_BITS 0x00000008 +#define I2C_IC_STATUS_RFNE_MSB 3 +#define I2C_IC_STATUS_RFNE_LSB 3 +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY 0x0 +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFE +// Description : Transmit FIFO Completely Empty. When the transmit FIFO is +// completely empty, this bit is set. When it contains one or more +// valid entries, this bit is cleared. This bit field does not +// request an interrupt. - 0: Transmit FIFO is not empty - 1: +// Transmit FIFO is empty Reset value: 0x1 +// 0x0 -> Tx FIFO not empty +// 0x1 -> Tx FIFO is empty +#define I2C_IC_STATUS_TFE_RESET 0x1 +#define I2C_IC_STATUS_TFE_BITS 0x00000004 +#define I2C_IC_STATUS_TFE_MSB 2 +#define I2C_IC_STATUS_TFE_LSB 2 +#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY 0x0 +#define I2C_IC_STATUS_TFE_VALUE_EMPTY 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFNF +// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one +// or more empty locations, and is cleared when the FIFO is full. +// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset +// value: 0x1 +// 0x0 -> Tx FIFO is full +// 0x1 -> Tx FIFO not full +#define I2C_IC_STATUS_TFNF_RESET 0x1 +#define I2C_IC_STATUS_TFNF_BITS 0x00000002 +#define I2C_IC_STATUS_TFNF_MSB 1 +#define I2C_IC_STATUS_TFNF_LSB 1 +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL 0x0 +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_ACTIVITY +// Description : I2C Activity Status. Reset value: 0x0 +// 0x0 -> I2C is idle +// 0x1 -> I2C is active +#define I2C_IC_STATUS_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_ACTIVITY_BITS 0x00000001 +#define I2C_IC_STATUS_ACTIVITY_MSB 0 +#define I2C_IC_STATUS_ACTIVITY_LSB 0 +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_TXFLR +// Description : I2C Transmit FIFO Level Register This register contains the +// number of valid data entries in the transmit FIFO buffer. It is +// cleared whenever: - The I2C is disabled - There is a transmit +// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT +// register - The slave bulk transmit mode is aborted The register +// increments whenever data is placed into the transmit FIFO and +// decrements when data is taken from the transmit FIFO. +#define I2C_IC_TXFLR_OFFSET 0x00000074 +#define I2C_IC_TXFLR_BITS 0x0000001f +#define I2C_IC_TXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TXFLR_TXFLR +// Description : Transmit FIFO Level. Contains the number of valid data entries +// in the transmit FIFO. +// +// Reset value: 0x0 +#define I2C_IC_TXFLR_TXFLR_RESET 0x00 +#define I2C_IC_TXFLR_TXFLR_BITS 0x0000001f +#define I2C_IC_TXFLR_TXFLR_MSB 4 +#define I2C_IC_TXFLR_TXFLR_LSB 0 +#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_RXFLR +// Description : I2C Receive FIFO Level Register This register contains the +// number of valid data entries in the receive FIFO buffer. It is +// cleared whenever: - The I2C is disabled - Whenever there is a +// transmit abort caused by any of the events tracked in +// IC_TX_ABRT_SOURCE The register increments whenever data is +// placed into the receive FIFO and decrements when data is taken +// from the receive FIFO. +#define I2C_IC_RXFLR_OFFSET 0x00000078 +#define I2C_IC_RXFLR_BITS 0x0000001f +#define I2C_IC_RXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RXFLR_RXFLR +// Description : Receive FIFO Level. Contains the number of valid data entries +// in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_RXFLR_RXFLR_RESET 0x00 +#define I2C_IC_RXFLR_RXFLR_BITS 0x0000001f +#define I2C_IC_RXFLR_RXFLR_MSB 4 +#define I2C_IC_RXFLR_RXFLR_LSB 0 +#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_SDA_HOLD +// Description : I2C SDA Hold Time Length Register +// +// The bits [15:0] of this register are used to control the hold +// time of SDA during transmit in both slave and master mode +// (after SCL goes from HIGH to LOW). +// +// The bits [23:16] of this register are used to extend the SDA +// transition (if any) whenever SCL is HIGH in the receiver in +// either master or slave mode. +// +// Writes to this register succeed only when IC_ENABLE[0]=0. +// +// The values in this register are in units of ic_clk period. The +// value programmed in IC_SDA_TX_HOLD must be greater than the +// minimum hold time in each mode one cycle in master mode, seven +// cycles in slave mode for the value to be implemented. +// +// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) +// cannot exceed at any time the duration of the low part of scl. +// Therefore the programmed value cannot be larger than +// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of +// the scl period measured in ic_clk cycles. +#define I2C_IC_SDA_HOLD_OFFSET 0x0000007c +#define I2C_IC_SDA_HOLD_BITS 0x00ffffff +#define I2C_IC_SDA_HOLD_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a receiver. +// +// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x00 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS 0x00ff0000 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a transmitter. +// +// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x0001 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS 0x0000ffff +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_ABRT_SOURCE +// Description : I2C Transmit Abort Source Register +// +// This register has 32 bits that indicate the source of the +// TX_ABRT bit. Except for Bit 9, this register is cleared +// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR +// register is read. To clear Bit 9, the source of the +// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled +// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or +// the GC_OR_START bit must be cleared (IC_TAR[10]). +// +// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this +// bit can be cleared in the same manner as other bits in this +// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed +// before attempting to clear this bit, Bit 9 clears for one cycle +// and is then re-asserted. +#define I2C_IC_TX_ABRT_SOURCE_OFFSET 0x00000080 +#define I2C_IC_TX_ABRT_SOURCE_BITS 0xff81ffff +#define I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT +// Description : This field indicates the number of Tx FIFO Data Commands which +// are flushed due to TX_ABRT interrupt. It is cleared whenever +// I2C is disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x000 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS 0xff800000 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT +// Description : This is a master-mode-only bit. Master has detected the +// transfer abort (IC_ENABLE[1]) +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transfer abort detected by master- scenario not present +// 0x1 -> Transfer abort detected by master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS 0x00010000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX +// Description : 1: When the processor side responds to a slave mode request for +// data to be transmitted to a remote master and user writes a 1 +// in CMD (bit 8) of IC_DATA_CMD register. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave trying to transmit to remote master in read mode- +// scenario not present +// 0x1 -> Slave trying to transmit to remote master in read mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS 0x00008000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST +// Description : This field indicates that a Slave has lost the bus while +// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is +// set at the same time. Note: Even though the slave never 'owns' +// the bus, something could go wrong on the bus. This is a fail +// safe check. For instance, during a data transmission at the +// low-to-high transition of SCL, if what is on the data bus is +// not what is supposed to be transmitted, then DW_apb_i2c no +// longer own the bus. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave lost arbitration to remote master- scenario not +// present +// 0x1 -> Slave lost arbitration to remote master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS 0x00004000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO +// Description : This field specifies that the Slave has received a read command +// and some data exists in the TX FIFO, so the slave issues a +// TX_ABRT interrupt to flush old data in TX FIFO. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read +// command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read +// command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS 0x00002000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST +// Description : This field specifies that the Master has lost arbitration, or +// if IC_TX_ABRT_SOURCE[14] is also set, then the slave +// transmitter has lost arbitration. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario +// not present +// 0x1 -> Master or Slave-Transmitter lost arbitration +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS 0x00001000 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS +// Description : This field indicates that the User tries to initiate a Master +// operation with the Master mode disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User initiating master operation when MASTER disabled- +// scenario not present +// 0x1 -> User initiating master operation when MASTER disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS 0x00000800 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read +// command in 10-bit addressing mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Receiver +// 0x0 -> Master not trying to read in 10Bit addressing mode when +// RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when +// RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS 0x00000400 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT +// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be +// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL +// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must +// be cleared (IC_TAR[10]). Once the source of the +// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in +// the same manner as other bits in this register. If the source +// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to +// clear this bit, bit 9 clears for one cycle and then gets +// reasserted. When this field is set to 1, the restart is +// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is +// trying to send a START Byte. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> User trying to send START byte when RESTART disabled- +// scenario not present +// 0x1 -> User trying to send START byte when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS 0x00000200 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to +// use the master to transfer data in High Speed mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User trying to switch Master to HS mode when RESTART +// disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART +// disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS 0x00000100 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET +// Description : This field indicates that the Master has sent a START Byte and +// the START Byte was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> ACK detected for START byte- scenario not present +// 0x1 -> ACK detected for START byte +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS 0x00000080 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET +// Description : This field indicates that the Master is in High Speed mode and +// the High Speed Master code was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> HS Master code ACKed in HS Mode- scenario not present +// 0x1 -> HS Master code ACKed in HS Mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS 0x00000040 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ +// Description : This field indicates that DW_apb_i2c in the master mode has +// sent a General Call but the user programmed the byte following +// the General Call to be a read from the bus (IC_DATA_CMD[9] is +// set to 1). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL is followed by read from bus-scenario not present +// 0x1 -> GCALL is followed by read from bus +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS 0x00000020 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK +// Description : This field indicates that DW_apb_i2c in master mode has sent a +// General Call and no slave on the bus acknowledged the General +// Call. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL not ACKed by any slave-scenario not present +// 0x1 -> GCALL not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS 0x00000010 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK +// Description : This field indicates the master-mode only bit. When the master +// receives an acknowledgement for the address, but when it sends +// data byte(s) following the address, it did not receive an +// acknowledge from the remote slave(s). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario +// not present +// 0x1 -> Transmitted data not ACKed by addressed slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS 0x00000008 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and that the second address byte of the 10-bit address was not +// acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS 0x00000004 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and the first 10-bit address byte was not acknowledged by any +// slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS 0x00000002 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK +// Description : This field indicates that the Master is in 7-bit addressing +// mode and the address sent was not acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> This abort is generated because of NOACK for 7-bit +// address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS 0x00000001 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_SLV_DATA_NACK_ONLY +// Description : Generate Slave Data NACK Register +// +// The register is used to generate a NACK for the data part of a +// transfer when DW_apb_i2c is acting as a slave-receiver. This +// register only exists when the IC_SLV_DATA_NACK_ONLY parameter +// is set to 1. When this parameter disabled, this register does +// not exist and writing to the register's address has no effect. +// +// A write can occur on this register if both of the following +// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) +// - Slave part is inactive (IC_STATUS[6] = 0) Note: The +// IC_STATUS[6] is a register read-back location for the internal +// slv_activity signal; the user should poll this before writing +// the ic_slv_data_nack_only bit. +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x00000084 +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS 0x00000001 +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK +// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c +// is a slave-receiver. If this register is set to a value of 1, +// it can only generate a NACK after a data byte is received; +// hence, the data transfer is aborted and the data received is +// not pushed to the receive buffer. +// +// When the register is set to a value of 0, it generates +// NACK/ACK, depending on normal criteria. - 1: generate NACK +// after data byte received - 0: generate NACK/ACK normally Reset +// value: 0x0 +// 0x0 -> Slave receiver generates NACK normally +// 0x1 -> Slave receiver generates NACK upon data reception only +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS 0x00000001 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED 0x0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_DMA_CR +// Description : DMA Control Register +// +// The register is used to enable the DMA Controller interface +// operation. There is a separate bit for transmit and receive. +// This can be programmed regardless of the state of IC_ENABLE. +#define I2C_IC_DMA_CR_OFFSET 0x00000088 +#define I2C_IC_DMA_CR_BITS 0x00000003 +#define I2C_IC_DMA_CR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_TDMAE +// Description : Transmit DMA Enable. This bit enables/disables the transmit +// FIFO DMA channel. Reset value: 0x0 +// 0x0 -> transmit FIFO DMA channel disabled +// 0x1 -> Transmit FIFO DMA channel enabled +#define I2C_IC_DMA_CR_TDMAE_RESET 0x0 +#define I2C_IC_DMA_CR_TDMAE_BITS 0x00000002 +#define I2C_IC_DMA_CR_TDMAE_MSB 1 +#define I2C_IC_DMA_CR_TDMAE_LSB 1 +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED 0x0 +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_RDMAE +// Description : Receive DMA Enable. This bit enables/disables the receive FIFO +// DMA channel. Reset value: 0x0 +// 0x0 -> Receive FIFO DMA channel disabled +// 0x1 -> Receive FIFO DMA channel enabled +#define I2C_IC_DMA_CR_RDMAE_RESET 0x0 +#define I2C_IC_DMA_CR_RDMAE_BITS 0x00000001 +#define I2C_IC_DMA_CR_RDMAE_MSB 0 +#define I2C_IC_DMA_CR_RDMAE_LSB 0 +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED 0x0 +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_DMA_TDLR +// Description : DMA Transmit Data Level Register +#define I2C_IC_DMA_TDLR_OFFSET 0x0000008c +#define I2C_IC_DMA_TDLR_BITS 0x0000000f +#define I2C_IC_DMA_TDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_TDLR_DMATDL +// Description : Transmit Data Level. This bit field controls the level at which +// a DMA request is made by the transmit logic. It is equal to the +// watermark level; that is, the dma_tx_req signal is generated +// when the number of valid data entries in the transmit FIFO is +// equal to or below this field value, and TDMAE = 1. +// +// Reset value: 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_BITS 0x0000000f +#define I2C_IC_DMA_TDLR_DMATDL_MSB 3 +#define I2C_IC_DMA_TDLR_DMATDL_LSB 0 +#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DMA_RDLR +// Description : I2C Receive Data Level Register +#define I2C_IC_DMA_RDLR_OFFSET 0x00000090 +#define I2C_IC_DMA_RDLR_BITS 0x0000000f +#define I2C_IC_DMA_RDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_RDLR_DMARDL +// Description : Receive Data Level. This bit field controls the level at which +// a DMA request is made by the receive logic. The watermark level +// = DMARDL+1; that is, dma_rx_req is generated when the number of +// valid data entries in the receive FIFO is equal to or more than +// this field value + 1, and RDMAE =1. For instance, when DMARDL +// is 0, then dma_rx_req is asserted when 1 or more data entries +// are present in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_BITS 0x0000000f +#define I2C_IC_DMA_RDLR_DMARDL_MSB 3 +#define I2C_IC_DMA_RDLR_DMARDL_LSB 0 +#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SDA_SETUP +// Description : I2C SDA Setup Register +// +// This register controls the amount of time delay (in terms of +// number of ic_clk clock periods) introduced in the rising edge +// of SCL - relative to SDA changing - when DW_apb_i2c services a +// read request in a slave-transmitter operation. The relevant I2C +// requirement is tSU:DAT (note 4) as detailed in the I2C Bus +// Specification. This register must be programmed with a value +// equal to or greater than 2. +// +// Writes to this register succeed only when IC_ENABLE[0] = 0. +// +// Note: The length of setup time is calculated using +// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires +// 10 ic_clk periods of setup time, they should program a value of +// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c +// when operating as a slave transmitter. +#define I2C_IC_SDA_SETUP_OFFSET 0x00000094 +#define I2C_IC_SDA_SETUP_BITS 0x000000ff +#define I2C_IC_SDA_SETUP_RESET 0x00000064 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_SETUP_SDA_SETUP +// Description : SDA Setup. It is recommended that if the required delay is +// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP +// should be programmed to a value of 11. IC_SDA_SETUP must be +// programmed with a minimum value of 2. +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64 +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS 0x000000ff +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7 +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0 +#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_ACK_GENERAL_CALL +// Description : I2C ACK General Call Register +// +// The register controls whether DW_apb_i2c responds with a ACK or +// NACK when it receives an I2C General Call address. +// +// This register is applicable only when the DW_apb_i2c is in +// slave mode. +#define I2C_IC_ACK_GENERAL_CALL_OFFSET 0x00000098 +#define I2C_IC_ACK_GENERAL_CALL_BITS 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL +// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK +// (by asserting ic_data_oe) when it receives a General Call. +// Otherwise, DW_apb_i2c responds with a NACK (by negating +// ic_data_oe). +// 0x0 -> Generate NACK for a General Call +// 0x1 -> Generate ACK for a General Call +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED 0x0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_ENABLE_STATUS +// Description : I2C Enable Status Register +// +// The register is used to report the DW_apb_i2c hardware status +// when the IC_ENABLE[0] register is set from 1 to 0; that is, +// when DW_apb_i2c is disabled. +// +// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, +// and bit 0 is forced to 1. +// +// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as +// soon as bit 0 is read as '0'. +// +// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for +// bit 0 to be read as 0 because disabling the DW_apb_i2c depends +// on I2C bus activities. +#define I2C_IC_ENABLE_STATUS_OFFSET 0x0000009c +#define I2C_IC_ENABLE_STATUS_BITS 0x00000007 +#define I2C_IC_ENABLE_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST +// Description : Slave Received Data Lost. This bit indicates if a +// Slave-Receiver operation has been aborted with at least one +// data byte received from an I2C transfer due to the setting bit +// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is +// deemed to have been actively engaged in an aborted I2C transfer +// (with matching address) and the data phase of the I2C transfer +// has been entered, even though a data byte has been responded +// with a NACK. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit is +// also set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled +// without being actively involved in the data phase of a +// Slave-Receiver transfer. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave RX Data is not lost +// 0x1 -> Slave RX Data is lost +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS 0x00000004 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY +// Description : Slave Disabled While Busy (Transmit, Receive). This bit +// indicates if a potential or active Slave operation has been +// aborted due to the setting bit 0 of the IC_ENABLE register from +// 1 to 0. This bit is set when the CPU writes a 0 to the +// IC_ENABLE register while: +// +// (a) DW_apb_i2c is receiving the address byte of the +// Slave-Transmitter operation from a remote master; +// +// OR, +// +// (b) address and data bytes of the Slave-Receiver operation from +// a remote master. +// +// When read as 1, DW_apb_i2c is deemed to have forced a NACK +// during any part of an I2C transfer, irrespective of whether the +// I2C address matches the slave address set in DW_apb_i2c (IC_SAR +// register) OR if the transfer is completed before IC_ENABLE is +// set to 0 but has not taken effect. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit +// will also be set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled when +// there is master activity, or when the I2C bus is idle. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave is disabled when it is idle +// 0x1 -> Slave is disabled when it is active +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS 0x00000002 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_IC_EN +// Description : ic_en Status. This bit always reflects the value driven on the +// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be +// in an enabled state. - When read as 0, DW_apb_i2c is deemed +// completely inactive. Note: The CPU can safely read this bit +// anytime. When this bit is read as 0, the CPU can safely read +// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). +// +// Reset value: 0x0 +// 0x0 -> I2C disabled +// 0x1 -> I2C enabled +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS 0x00000001 +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED 0x0 +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_FS_SPKLEN +// Description : I2C SS, FS or FM+ spike suppression limit +// +// This register is used to store the duration, measured in ic_clk +// cycles, of the longest spike that is filtered out by the spike +// suppression logic when the component is operating in SS, FS or +// FM+ modes. The relevant I2C requirement is tSP (table 4) as +// detailed in the I2C Bus Specification. This register must be +// programmed with a minimum value of 1. +#define I2C_IC_FS_SPKLEN_OFFSET 0x000000a0 +#define I2C_IC_FS_SPKLEN_BITS 0x000000ff +#define I2C_IC_FS_SPKLEN_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN +// Description : This register must be set before any I2C bus transaction can +// take place to ensure stable operation. This register sets the +// duration, measured in ic_clk cycles, of the longest spike in +// the SCL or SDA lines that will be filtered out by the spike +// suppression logic. This register can be written only when the +// I2C interface is disabled which corresponds to the IC_ENABLE[0] +// register being set to 0. Writes at other times have no effect. +// The minimum valid value is 1; hardware prevents values less +// than this being written, and if attempted results in 1 being +// set. or more information, refer to 'Spike Suppression'. +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x07 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS 0x000000ff +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_RESTART_DET +// Description : Clear RESTART_DET Interrupt Register +#define I2C_IC_CLR_RESTART_DET_OFFSET 0x000000a8 +#define I2C_IC_CLR_RESTART_DET_BITS 0x00000001 +#define I2C_IC_CLR_RESTART_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET +// Description : Read this register to clear the RESTART_DET interrupt (bit 12) +// of IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS 0x00000001 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_PARAM_1 +// Description : Component Parameter Register 1 +// +// Note This register is not implemented and therefore reads as 0. +// If it was implemented it would be a constant read-only register +// that contains encoded information about the component's +// parameter settings. Fields shown below are the settings for +// those parameters +#define I2C_IC_COMP_PARAM_1_OFFSET 0x000000f4 +#define I2C_IC_COMP_PARAM_1_BITS 0x00ffffff +#define I2C_IC_COMP_PARAM_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH +// Description : TX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x00 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS 0x00ff0000 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH +// Description : RX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x00 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS 0x0000ff00 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS +// Description : Encoded parameters not visible +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS 0x00000080 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HAS_DMA +// Description : DMA handshaking signals are enabled +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS 0x00000040 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_INTR_IO +// Description : COMBINED Interrupt outputs +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS 0x00000020 +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES +// Description : Programmable count values for each mode. +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS 0x00000010 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE +// Description : MAX SPEED MODE = FAST MODE +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS 0x0000000c +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH +// Description : APB data bus width is 32 bits +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS 0x00000003 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_VERSION +// Description : I2C Component Version Register +#define I2C_IC_COMP_VERSION_OFFSET 0x000000f8 +#define I2C_IC_COMP_VERSION_BITS 0xffffffff +#define I2C_IC_COMP_VERSION_RESET 0x3230312a +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION +// Description : None +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230312a +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS 0xffffffff +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_TYPE +// Description : I2C Component Type Register +#define I2C_IC_COMP_TYPE_OFFSET 0x000000fc +#define I2C_IC_COMP_TYPE_BITS 0xffffffff +#define I2C_IC_COMP_TYPE_RESET 0x44570140 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE +// Description : Designware Component Type number = 0x44_57_01_40. This assigned +// unique hex value is constant and is derived from the two ASCII +// letters 'DW' followed by a 16-bit unsigned number. +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS 0xffffffff +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_I2C_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h new file mode 100644 index 00000000000..dec7e36eaf9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/intctrl.h @@ -0,0 +1,63 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H_ +#define _INTCTRL_H_ + +#define TIMER_IRQ_0 0 +#define TIMER_IRQ_1 1 +#define TIMER_IRQ_2 2 +#define TIMER_IRQ_3 3 +#define PWM_IRQ_WRAP 4 +#define USBCTRL_IRQ 5 +#define XIP_IRQ 6 +#define PIO0_IRQ_0 7 +#define PIO0_IRQ_1 8 +#define PIO1_IRQ_0 9 +#define PIO1_IRQ_1 10 +#define DMA_IRQ_0 11 +#define DMA_IRQ_1 12 +#define IO_IRQ_BANK0 13 +#define IO_IRQ_QSPI 14 +#define SIO_IRQ_PROC0 15 +#define SIO_IRQ_PROC1 16 +#define CLOCKS_IRQ 17 +#define SPI0_IRQ 18 +#define SPI1_IRQ 19 +#define UART0_IRQ 20 +#define UART1_IRQ 21 +#define ADC_IRQ_FIFO 22 +#define I2C0_IRQ 23 +#define I2C1_IRQ 24 +#define RTC_IRQ 25 + +#define isr_timer_0 isr_irq0 +#define isr_timer_1 isr_irq1 +#define isr_timer_2 isr_irq2 +#define isr_timer_3 isr_irq3 +#define isr_pwm_wrap isr_irq4 +#define isr_usbctrl isr_irq5 +#define isr_xip isr_irq6 +#define isr_pio0_0 isr_irq7 +#define isr_pio0_1 isr_irq8 +#define isr_pio1_0 isr_irq9 +#define isr_pio1_1 isr_irq10 +#define isr_dma_0 isr_irq11 +#define isr_dma_1 isr_irq12 +#define isr_io_bank0 isr_irq13 +#define isr_io_qspi isr_irq14 +#define isr_sio_proc0 isr_irq15 +#define isr_sio_proc1 isr_irq16 +#define isr_clocks isr_irq17 +#define isr_spi0 isr_irq18 +#define isr_spi1 isr_irq19 +#define isr_uart0 isr_irq20 +#define isr_uart1 isr_irq21 +#define isr_adc_fifo isr_irq22 +#define isr_i2c0 isr_irq23 +#define isr_i2c1 isr_irq24 +#define isr_rtc isr_irq25 + +#endif // _INTCTRL_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h new file mode 100644 index 00000000000..f7b15610c3a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h @@ -0,0 +1,14937 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_BANK0 +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_IO_BANK0_DEFINED +#define HARDWARE_REGS_IO_BANK0_DEFINED +// ============================================================================= +// Register : IO_BANK0_GPIO0_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO0_STATUS_OFFSET 0x00000000 +#define IO_BANK0_GPIO0_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO0_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO0_CTRL_OFFSET 0x00000004 +#define IO_BANK0_GPIO0_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO0_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tck +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> sio_0 +// 0x06 -> pio0_0 +// 0x07 -> pio1_0 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK 0x00 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 0x05 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 0x06 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 0x07 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO1_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO1_STATUS_OFFSET 0x00000008 +#define IO_BANK0_GPIO1_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO1_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO1_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO1_CTRL_OFFSET 0x0000000c +#define IO_BANK0_GPIO1_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO1_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tms +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> sio_1 +// 0x06 -> pio0_1 +// 0x07 -> pio1_1 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS 0x00 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 0x05 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 0x06 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 0x07 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO2_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO2_STATUS_OFFSET 0x00000010 +#define IO_BANK0_GPIO2_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO2_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO2_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO2_CTRL_OFFSET 0x00000014 +#define IO_BANK0_GPIO2_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO2_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdi +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> sio_2 +// 0x06 -> pio0_2 +// 0x07 -> pio1_2 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI 0x00 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 0x05 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 0x06 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 0x07 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO3_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO3_STATUS_OFFSET 0x00000018 +#define IO_BANK0_GPIO3_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO3_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO3_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO3_CTRL_OFFSET 0x0000001c +#define IO_BANK0_GPIO3_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO3_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdo +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> sio_3 +// 0x06 -> pio0_3 +// 0x07 -> pio1_3 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO 0x00 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 0x05 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 0x06 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 0x07 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO4_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO4_STATUS_OFFSET 0x00000020 +#define IO_BANK0_GPIO4_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO4_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO4_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO4_CTRL_OFFSET 0x00000024 +#define IO_BANK0_GPIO4_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO4_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> sio_4 +// 0x06 -> pio0_4 +// 0x07 -> pio1_4 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 0x05 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 0x06 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 0x07 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO5_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO5_STATUS_OFFSET 0x00000028 +#define IO_BANK0_GPIO5_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO5_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO5_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO5_CTRL_OFFSET 0x0000002c +#define IO_BANK0_GPIO5_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO5_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> sio_5 +// 0x06 -> pio0_5 +// 0x07 -> pio1_5 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 0x05 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 0x06 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 0x07 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO6_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO6_STATUS_OFFSET 0x00000030 +#define IO_BANK0_GPIO6_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO6_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO6_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO6_CTRL_OFFSET 0x00000034 +#define IO_BANK0_GPIO6_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO6_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> sio_6 +// 0x06 -> pio0_6 +// 0x07 -> pio1_6 +// 0x08 -> usb_muxing_extphy_softcon +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 0x05 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 0x06 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 0x07 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON 0x08 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO7_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO7_STATUS_OFFSET 0x00000038 +#define IO_BANK0_GPIO7_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO7_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO7_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO7_CTRL_OFFSET 0x0000003c +#define IO_BANK0_GPIO7_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO7_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> sio_7 +// 0x06 -> pio0_7 +// 0x07 -> pio1_7 +// 0x08 -> usb_muxing_extphy_oe_n +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 0x05 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 0x06 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 0x07 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N 0x08 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO8_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO8_STATUS_OFFSET 0x00000040 +#define IO_BANK0_GPIO8_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO8_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO8_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO8_CTRL_OFFSET 0x00000044 +#define IO_BANK0_GPIO8_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO8_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> sio_8 +// 0x06 -> pio0_8 +// 0x07 -> pio1_8 +// 0x08 -> usb_muxing_extphy_rcv +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 0x05 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 0x06 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 0x07 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV 0x08 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO9_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO9_STATUS_OFFSET 0x00000048 +#define IO_BANK0_GPIO9_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO9_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO9_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO9_CTRL_OFFSET 0x0000004c +#define IO_BANK0_GPIO9_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO9_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> sio_9 +// 0x06 -> pio0_9 +// 0x07 -> pio1_9 +// 0x08 -> usb_muxing_extphy_vp +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 0x05 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 0x06 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 0x07 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP 0x08 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO10_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO10_STATUS_OFFSET 0x00000050 +#define IO_BANK0_GPIO10_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO10_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO10_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO10_CTRL_OFFSET 0x00000054 +#define IO_BANK0_GPIO10_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO10_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> sio_10 +// 0x06 -> pio0_10 +// 0x07 -> pio1_10 +// 0x08 -> usb_muxing_extphy_vm +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 0x05 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 0x06 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 0x07 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM 0x08 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO11_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO11_STATUS_OFFSET 0x00000058 +#define IO_BANK0_GPIO11_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO11_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO11_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO11_CTRL_OFFSET 0x0000005c +#define IO_BANK0_GPIO11_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO11_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> sio_11 +// 0x06 -> pio0_11 +// 0x07 -> pio1_11 +// 0x08 -> usb_muxing_extphy_suspnd +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 0x05 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 0x06 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 0x07 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND 0x08 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO12_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO12_STATUS_OFFSET 0x00000060 +#define IO_BANK0_GPIO12_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO12_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO12_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO12_CTRL_OFFSET 0x00000064 +#define IO_BANK0_GPIO12_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO12_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> sio_12 +// 0x06 -> pio0_12 +// 0x07 -> pio1_12 +// 0x08 -> usb_muxing_extphy_speed +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 0x05 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 0x06 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 0x07 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED 0x08 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO13_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO13_STATUS_OFFSET 0x00000068 +#define IO_BANK0_GPIO13_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO13_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO13_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO13_CTRL_OFFSET 0x0000006c +#define IO_BANK0_GPIO13_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO13_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> sio_13 +// 0x06 -> pio0_13 +// 0x07 -> pio1_13 +// 0x08 -> usb_muxing_extphy_vpo +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 0x05 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 0x06 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 0x07 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO 0x08 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO14_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO14_STATUS_OFFSET 0x00000070 +#define IO_BANK0_GPIO14_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO14_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO14_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO14_CTRL_OFFSET 0x00000074 +#define IO_BANK0_GPIO14_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO14_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> sio_14 +// 0x06 -> pio0_14 +// 0x07 -> pio1_14 +// 0x08 -> usb_muxing_extphy_vmo +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 0x04 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 0x05 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 0x06 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 0x07 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO 0x08 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO15_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO15_STATUS_OFFSET 0x00000078 +#define IO_BANK0_GPIO15_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO15_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO15_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO15_CTRL_OFFSET 0x0000007c +#define IO_BANK0_GPIO15_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO15_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> sio_15 +// 0x06 -> pio0_15 +// 0x07 -> pio1_15 +// 0x08 -> usb_muxing_digital_dp +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 0x04 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 0x05 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 0x06 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 0x07 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP 0x08 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO16_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO16_STATUS_OFFSET 0x00000080 +#define IO_BANK0_GPIO16_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO16_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO16_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO16_CTRL_OFFSET 0x00000084 +#define IO_BANK0_GPIO16_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO16_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> sio_16 +// 0x06 -> pio0_16 +// 0x07 -> pio1_16 +// 0x08 -> usb_muxing_digital_dm +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 0x05 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 0x06 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 0x07 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM 0x08 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO17_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO17_STATUS_OFFSET 0x00000088 +#define IO_BANK0_GPIO17_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO17_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO17_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO17_CTRL_OFFSET 0x0000008c +#define IO_BANK0_GPIO17_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO17_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> sio_17 +// 0x06 -> pio0_17 +// 0x07 -> pio1_17 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 0x05 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 0x06 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 0x07 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO18_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO18_STATUS_OFFSET 0x00000090 +#define IO_BANK0_GPIO18_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO18_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO18_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO18_CTRL_OFFSET 0x00000094 +#define IO_BANK0_GPIO18_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO18_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> sio_18 +// 0x06 -> pio0_18 +// 0x07 -> pio1_18 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 0x05 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 0x06 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 0x07 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO19_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO19_STATUS_OFFSET 0x00000098 +#define IO_BANK0_GPIO19_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO19_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO19_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO19_CTRL_OFFSET 0x0000009c +#define IO_BANK0_GPIO19_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO19_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> sio_19 +// 0x06 -> pio0_19 +// 0x07 -> pio1_19 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 0x05 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 0x06 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 0x07 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO20_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO20_STATUS_OFFSET 0x000000a0 +#define IO_BANK0_GPIO20_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO20_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO20_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO20_CTRL_OFFSET 0x000000a4 +#define IO_BANK0_GPIO20_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO20_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> sio_20 +// 0x06 -> pio0_20 +// 0x07 -> pio1_20 +// 0x08 -> clocks_gpin_0 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 0x05 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 0x06 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 0x07 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 0x08 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO21_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO21_STATUS_OFFSET 0x000000a8 +#define IO_BANK0_GPIO21_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO21_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO21_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO21_CTRL_OFFSET 0x000000ac +#define IO_BANK0_GPIO21_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO21_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> sio_21 +// 0x06 -> pio0_21 +// 0x07 -> pio1_21 +// 0x08 -> clocks_gpout_0 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 0x05 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 0x06 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 0x07 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 0x08 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO22_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO22_STATUS_OFFSET 0x000000b0 +#define IO_BANK0_GPIO22_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO22_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO22_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO22_CTRL_OFFSET 0x000000b4 +#define IO_BANK0_GPIO22_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO22_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> sio_22 +// 0x06 -> pio0_22 +// 0x07 -> pio1_22 +// 0x08 -> clocks_gpin_1 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 0x05 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 0x06 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 0x07 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 0x08 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO23_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO23_STATUS_OFFSET 0x000000b8 +#define IO_BANK0_GPIO23_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO23_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO23_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO23_CTRL_OFFSET 0x000000bc +#define IO_BANK0_GPIO23_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO23_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> sio_23 +// 0x06 -> pio0_23 +// 0x07 -> pio1_23 +// 0x08 -> clocks_gpout_1 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 0x05 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 0x06 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 0x07 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 0x08 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO24_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO24_STATUS_OFFSET 0x000000c0 +#define IO_BANK0_GPIO24_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO24_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO24_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO24_CTRL_OFFSET 0x000000c4 +#define IO_BANK0_GPIO24_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO24_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> sio_24 +// 0x06 -> pio0_24 +// 0x07 -> pio1_24 +// 0x08 -> clocks_gpout_2 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 0x05 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 0x06 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 0x07 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 0x08 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO25_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO25_STATUS_OFFSET 0x000000c8 +#define IO_BANK0_GPIO25_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO25_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO25_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO25_CTRL_OFFSET 0x000000cc +#define IO_BANK0_GPIO25_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO25_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> sio_25 +// 0x06 -> pio0_25 +// 0x07 -> pio1_25 +// 0x08 -> clocks_gpout_3 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 0x05 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 0x06 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 0x07 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 0x08 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO26_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO26_STATUS_OFFSET 0x000000d0 +#define IO_BANK0_GPIO26_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO26_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO26_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO26_CTRL_OFFSET 0x000000d4 +#define IO_BANK0_GPIO26_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO26_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> sio_26 +// 0x06 -> pio0_26 +// 0x07 -> pio1_26 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 0x05 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 0x06 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 0x07 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO27_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO27_STATUS_OFFSET 0x000000d8 +#define IO_BANK0_GPIO27_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO27_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO27_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO27_CTRL_OFFSET 0x000000dc +#define IO_BANK0_GPIO27_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO27_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> sio_27 +// 0x06 -> pio0_27 +// 0x07 -> pio1_27 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 0x05 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 0x06 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 0x07 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO28_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO28_STATUS_OFFSET 0x000000e0 +#define IO_BANK0_GPIO28_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO28_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO28_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO28_CTRL_OFFSET 0x000000e4 +#define IO_BANK0_GPIO28_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO28_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> sio_28 +// 0x06 -> pio0_28 +// 0x07 -> pio1_28 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 0x05 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 0x06 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 0x07 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO29_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO29_STATUS_OFFSET 0x000000e8 +#define IO_BANK0_GPIO29_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO29_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO29_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO29_CTRL_OFFSET 0x000000ec +#define IO_BANK0_GPIO29_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO29_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> sio_29 +// 0x06 -> pio0_29 +// 0x07 -> pio1_29 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 0x05 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 0x06 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 0x07 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_INTR0 +// Description : Raw Interrupts +#define IO_BANK0_INTR0_OFFSET 0x000000f0 +#define IO_BANK0_INTR0_BITS 0xffffffff +#define IO_BANK0_INTR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR1 +// Description : Raw Interrupts +#define IO_BANK0_INTR1_OFFSET 0x000000f4 +#define IO_BANK0_INTR1_BITS 0xffffffff +#define IO_BANK0_INTR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR2 +// Description : Raw Interrupts +#define IO_BANK0_INTR2_OFFSET 0x000000f8 +#define IO_BANK0_INTR2_BITS 0xffffffff +#define IO_BANK0_INTR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR3 +// Description : Raw Interrupts +#define IO_BANK0_INTR3_OFFSET 0x000000fc +#define IO_BANK0_INTR3_BITS 0x00ffffff +#define IO_BANK0_INTR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE0 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE0_OFFSET 0x00000100 +#define IO_BANK0_PROC0_INTE0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE1 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE1_OFFSET 0x00000104 +#define IO_BANK0_PROC0_INTE1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE2 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE2_OFFSET 0x00000108 +#define IO_BANK0_PROC0_INTE2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE3 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE3_OFFSET 0x0000010c +#define IO_BANK0_PROC0_INTE3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF0 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF0_OFFSET 0x00000110 +#define IO_BANK0_PROC0_INTF0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF1 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF1_OFFSET 0x00000114 +#define IO_BANK0_PROC0_INTF1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF2 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF2_OFFSET 0x00000118 +#define IO_BANK0_PROC0_INTF2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF3 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF3_OFFSET 0x0000011c +#define IO_BANK0_PROC0_INTF3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS0 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS0_OFFSET 0x00000120 +#define IO_BANK0_PROC0_INTS0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS1 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS1_OFFSET 0x00000124 +#define IO_BANK0_PROC0_INTS1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS2 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS2_OFFSET 0x00000128 +#define IO_BANK0_PROC0_INTS2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS3 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS3_OFFSET 0x0000012c +#define IO_BANK0_PROC0_INTS3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE0 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE0_OFFSET 0x00000130 +#define IO_BANK0_PROC1_INTE0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE1 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE1_OFFSET 0x00000134 +#define IO_BANK0_PROC1_INTE1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE2 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE2_OFFSET 0x00000138 +#define IO_BANK0_PROC1_INTE2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE3 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE3_OFFSET 0x0000013c +#define IO_BANK0_PROC1_INTE3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF0 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF0_OFFSET 0x00000140 +#define IO_BANK0_PROC1_INTF0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF1 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF1_OFFSET 0x00000144 +#define IO_BANK0_PROC1_INTF1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF2 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF2_OFFSET 0x00000148 +#define IO_BANK0_PROC1_INTF2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF3 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF3_OFFSET 0x0000014c +#define IO_BANK0_PROC1_INTF3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS0 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS0_OFFSET 0x00000150 +#define IO_BANK0_PROC1_INTS0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS1 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS1_OFFSET 0x00000154 +#define IO_BANK0_PROC1_INTS1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS2 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS2_OFFSET 0x00000158 +#define IO_BANK0_PROC1_INTS2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS3 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS3_OFFSET 0x0000015c +#define IO_BANK0_PROC1_INTS3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE0 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET 0x00000160 +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE1 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET 0x00000164 +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE2 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET 0x00000168 +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE3 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET 0x0000016c +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF0 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET 0x00000170 +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF1 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET 0x00000174 +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF2 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET 0x00000178 +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF3 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET 0x0000017c +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS0 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET 0x00000180 +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS1 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET 0x00000184 +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS2 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET 0x00000188 +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS3 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET 0x0000018c +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_IO_BANK0_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h new file mode 100644 index 00000000000..0c7c88d5329 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h @@ -0,0 +1,2931 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_QSPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_IO_QSPI_DEFINED +#define HARDWARE_REGS_IO_QSPI_DEFINED +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET 0x00000004 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sclk +// 0x05 -> sio_30 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK 0x00 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 0x05 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET 0x00000008 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET 0x0000000c +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_ss_n +// 0x05 -> sio_31 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N 0x00 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 0x05 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET 0x00000010 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET 0x00000014 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd0 +// 0x05 -> sio_32 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 0x00 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 0x05 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET 0x00000018 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET 0x0000001c +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd1 +// 0x05 -> sio_33 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 0x00 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 0x05 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET 0x00000020 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET 0x00000024 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd2 +// 0x05 -> sio_34 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 0x00 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 0x05 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET 0x00000028 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET 0x0000002c +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd3 +// 0x05 -> sio_35 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 0x00 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 0x05 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_INTR +// Description : Raw Interrupts +#define IO_QSPI_INTR_OFFSET 0x00000030 +#define IO_QSPI_INTR_BITS 0x00ffffff +#define IO_QSPI_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTE +// Description : Interrupt Enable for proc0 +#define IO_QSPI_PROC0_INTE_OFFSET 0x00000034 +#define IO_QSPI_PROC0_INTE_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTF +// Description : Interrupt Force for proc0 +#define IO_QSPI_PROC0_INTF_OFFSET 0x00000038 +#define IO_QSPI_PROC0_INTF_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTS +// Description : Interrupt status after masking & forcing for proc0 +#define IO_QSPI_PROC0_INTS_OFFSET 0x0000003c +#define IO_QSPI_PROC0_INTS_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTE +// Description : Interrupt Enable for proc1 +#define IO_QSPI_PROC1_INTE_OFFSET 0x00000040 +#define IO_QSPI_PROC1_INTE_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTF +// Description : Interrupt Force for proc1 +#define IO_QSPI_PROC1_INTF_OFFSET 0x00000044 +#define IO_QSPI_PROC1_INTF_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTS +// Description : Interrupt status after masking & forcing for proc1 +#define IO_QSPI_PROC1_INTS_OFFSET 0x00000048 +#define IO_QSPI_PROC1_INTS_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTE +// Description : Interrupt Enable for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET 0x0000004c +#define IO_QSPI_DORMANT_WAKE_INTE_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTF +// Description : Interrupt Force for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET 0x00000050 +#define IO_QSPI_DORMANT_WAKE_INTF_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTS +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET 0x00000054 +#define IO_QSPI_DORMANT_WAKE_INTS_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_IO_QSPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h new file mode 100644 index 00000000000..fac8e8b55bc --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h @@ -0,0 +1,1149 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M0PLUS +// Version : 1 +// Bus type : ahbl +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_M0PLUS_DEFINED +#define HARDWARE_REGS_M0PLUS_DEFINED +// ============================================================================= +// Register : M0PLUS_SYST_CSR +// Description : Use the SysTick Control and Status Register to enable the +// SysTick features. +#define M0PLUS_SYST_CSR_OFFSET 0x0000e010 +#define M0PLUS_SYST_CSR_BITS 0x00010007 +#define M0PLUS_SYST_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_COUNTFLAG +// Description : Returns 1 if timer counted to 0 since last time this was read. +// Clears on read by application or debugger. +#define M0PLUS_SYST_CSR_COUNTFLAG_RESET 0x0 +#define M0PLUS_SYST_CSR_COUNTFLAG_BITS 0x00010000 +#define M0PLUS_SYST_CSR_COUNTFLAG_MSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_LSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_CLKSOURCE +// Description : SysTick clock source. Always reads as one if SYST_CALIB reports +// NOREF. +// Selects the SysTick timer clock source: +// 0 = External reference clock. +// 1 = Processor clock. +#define M0PLUS_SYST_CSR_CLKSOURCE_RESET 0x0 +#define M0PLUS_SYST_CSR_CLKSOURCE_BITS 0x00000004 +#define M0PLUS_SYST_CSR_CLKSOURCE_MSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_LSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_TICKINT +// Description : Enables SysTick exception request: +// 0 = Counting down to zero does not assert the SysTick exception +// request. +// 1 = Counting down to zero to asserts the SysTick exception +// request. +#define M0PLUS_SYST_CSR_TICKINT_RESET 0x0 +#define M0PLUS_SYST_CSR_TICKINT_BITS 0x00000002 +#define M0PLUS_SYST_CSR_TICKINT_MSB 1 +#define M0PLUS_SYST_CSR_TICKINT_LSB 1 +#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_ENABLE +// Description : Enable SysTick counter: +// 0 = Counter disabled. +// 1 = Counter enabled. +#define M0PLUS_SYST_CSR_ENABLE_RESET 0x0 +#define M0PLUS_SYST_CSR_ENABLE_BITS 0x00000001 +#define M0PLUS_SYST_CSR_ENABLE_MSB 0 +#define M0PLUS_SYST_CSR_ENABLE_LSB 0 +#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_RVR +// Description : Use the SysTick Reload Value Register to specify the start +// value to load into the current value register when the counter +// reaches 0. It can be any value between 0 and 0x00FFFFFF. A +// start value of 0 is possible, but has no effect because the +// SysTick interrupt and COUNTFLAG are activated when counting +// from 1 to 0. The reset value of this register is UNKNOWN. +// To generate a multi-shot timer with a period of N processor +// clock cycles, use a RELOAD value of N-1. For example, if the +// SysTick interrupt is required every 100 clock pulses, set +// RELOAD to 99. +#define M0PLUS_SYST_RVR_OFFSET 0x0000e014 +#define M0PLUS_SYST_RVR_BITS 0x00ffffff +#define M0PLUS_SYST_RVR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_RVR_RELOAD +// Description : Value to load into the SysTick Current Value Register when the +// counter reaches 0. +#define M0PLUS_SYST_RVR_RELOAD_RESET 0x000000 +#define M0PLUS_SYST_RVR_RELOAD_BITS 0x00ffffff +#define M0PLUS_SYST_RVR_RELOAD_MSB 23 +#define M0PLUS_SYST_RVR_RELOAD_LSB 0 +#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_CVR +// Description : Use the SysTick Current Value Register to find the current +// value in the register. The reset value of this register is +// UNKNOWN. +#define M0PLUS_SYST_CVR_OFFSET 0x0000e018 +#define M0PLUS_SYST_CVR_BITS 0x00ffffff +#define M0PLUS_SYST_CVR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CVR_CURRENT +// Description : Reads return the current value of the SysTick counter. This +// register is write-clear. Writing to it with any value clears +// the register to 0. Clearing this register also clears the +// COUNTFLAG bit of the SysTick Control and Status Register. +#define M0PLUS_SYST_CVR_CURRENT_RESET 0x000000 +#define M0PLUS_SYST_CVR_CURRENT_BITS 0x00ffffff +#define M0PLUS_SYST_CVR_CURRENT_MSB 23 +#define M0PLUS_SYST_CVR_CURRENT_LSB 0 +#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_CALIB +// Description : Use the SysTick Calibration Value Register to enable software +// to scale to any required speed using divide and multiply. +#define M0PLUS_SYST_CALIB_OFFSET 0x0000e01c +#define M0PLUS_SYST_CALIB_BITS 0xc0ffffff +#define M0PLUS_SYST_CALIB_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_NOREF +// Description : If reads as 1, the Reference clock is not provided - the +// CLKSOURCE bit of the SysTick Control and Status register will +// be forced to 1 and cannot be cleared to 0. +#define M0PLUS_SYST_CALIB_NOREF_RESET 0x0 +#define M0PLUS_SYST_CALIB_NOREF_BITS 0x80000000 +#define M0PLUS_SYST_CALIB_NOREF_MSB 31 +#define M0PLUS_SYST_CALIB_NOREF_LSB 31 +#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_SKEW +// Description : If reads as 1, the calibration value for 10ms is inexact (due +// to clock frequency). +#define M0PLUS_SYST_CALIB_SKEW_RESET 0x0 +#define M0PLUS_SYST_CALIB_SKEW_BITS 0x40000000 +#define M0PLUS_SYST_CALIB_SKEW_MSB 30 +#define M0PLUS_SYST_CALIB_SKEW_LSB 30 +#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_TENMS +// Description : An optional Reload value to be used for 10ms (100Hz) timing, +// subject to system clock skew errors. If the value reads as 0, +// the calibration value is not known. +#define M0PLUS_SYST_CALIB_TENMS_RESET 0x000000 +#define M0PLUS_SYST_CALIB_TENMS_BITS 0x00ffffff +#define M0PLUS_SYST_CALIB_TENMS_MSB 23 +#define M0PLUS_SYST_CALIB_TENMS_LSB 0 +#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_NVIC_ISER +// Description : Use the Interrupt Set-Enable Register to enable interrupts and +// determine which interrupts are currently enabled. +// If a pending interrupt is enabled, the NVIC activates the +// interrupt based on its priority. If an interrupt is not +// enabled, asserting its interrupt signal changes the interrupt +// state to pending, but the NVIC never activates the interrupt, +// regardless of its priority. +#define M0PLUS_NVIC_ISER_OFFSET 0x0000e100 +#define M0PLUS_NVIC_ISER_BITS 0xffffffff +#define M0PLUS_NVIC_ISER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ISER_SETENA +// Description : Interrupt set-enable bits. +// Write: +// 0 = No effect. +// 1 = Enable interrupt. +// Read: +// 0 = Interrupt disabled. +// 1 = Interrupt enabled. +#define M0PLUS_NVIC_ISER_SETENA_RESET 0x00000000 +#define M0PLUS_NVIC_ISER_SETENA_BITS 0xffffffff +#define M0PLUS_NVIC_ISER_SETENA_MSB 31 +#define M0PLUS_NVIC_ISER_SETENA_LSB 0 +#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ICER +// Description : Use the Interrupt Clear-Enable Registers to disable interrupts +// and determine which interrupts are currently enabled. +#define M0PLUS_NVIC_ICER_OFFSET 0x0000e180 +#define M0PLUS_NVIC_ICER_BITS 0xffffffff +#define M0PLUS_NVIC_ICER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ICER_CLRENA +// Description : Interrupt clear-enable bits. +// Write: +// 0 = No effect. +// 1 = Disable interrupt. +// Read: +// 0 = Interrupt disabled. +// 1 = Interrupt enabled. +#define M0PLUS_NVIC_ICER_CLRENA_RESET 0x00000000 +#define M0PLUS_NVIC_ICER_CLRENA_BITS 0xffffffff +#define M0PLUS_NVIC_ICER_CLRENA_MSB 31 +#define M0PLUS_NVIC_ICER_CLRENA_LSB 0 +#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ISPR +// Description : The NVIC_ISPR forces interrupts into the pending state, and +// shows which interrupts are pending. +#define M0PLUS_NVIC_ISPR_OFFSET 0x0000e200 +#define M0PLUS_NVIC_ISPR_BITS 0xffffffff +#define M0PLUS_NVIC_ISPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ISPR_SETPEND +// Description : Interrupt set-pending bits. +// Write: +// 0 = No effect. +// 1 = Changes interrupt state to pending. +// Read: +// 0 = Interrupt is not pending. +// 1 = Interrupt is pending. +// Note: Writing 1 to the NVIC_ISPR bit corresponding to: +// An interrupt that is pending has no effect. +// A disabled interrupt sets the state of that interrupt to +// pending. +#define M0PLUS_NVIC_ISPR_SETPEND_RESET 0x00000000 +#define M0PLUS_NVIC_ISPR_SETPEND_BITS 0xffffffff +#define M0PLUS_NVIC_ISPR_SETPEND_MSB 31 +#define M0PLUS_NVIC_ISPR_SETPEND_LSB 0 +#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ICPR +// Description : Use the Interrupt Clear-Pending Register to clear pending +// interrupts and determine which interrupts are currently +// pending. +#define M0PLUS_NVIC_ICPR_OFFSET 0x0000e280 +#define M0PLUS_NVIC_ICPR_BITS 0xffffffff +#define M0PLUS_NVIC_ICPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ICPR_CLRPEND +// Description : Interrupt clear-pending bits. +// Write: +// 0 = No effect. +// 1 = Removes pending state and interrupt. +// Read: +// 0 = Interrupt is not pending. +// 1 = Interrupt is pending. +#define M0PLUS_NVIC_ICPR_CLRPEND_RESET 0x00000000 +#define M0PLUS_NVIC_ICPR_CLRPEND_BITS 0xffffffff +#define M0PLUS_NVIC_ICPR_CLRPEND_MSB 31 +#define M0PLUS_NVIC_ICPR_CLRPEND_LSB 0 +#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR0 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +// Note: Writing 1 to an NVIC_ICPR bit does not affect the active +// state of the corresponding interrupt. +// These registers are only word-accessible +#define M0PLUS_NVIC_IPR0_OFFSET 0x0000e400 +#define M0PLUS_NVIC_IPR0_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_3 +// Description : Priority of interrupt 3 +#define M0PLUS_NVIC_IPR0_IP_3_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_3_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR0_IP_3_MSB 31 +#define M0PLUS_NVIC_IPR0_IP_3_LSB 30 +#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_2 +// Description : Priority of interrupt 2 +#define M0PLUS_NVIC_IPR0_IP_2_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_2_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR0_IP_2_MSB 23 +#define M0PLUS_NVIC_IPR0_IP_2_LSB 22 +#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_1 +// Description : Priority of interrupt 1 +#define M0PLUS_NVIC_IPR0_IP_1_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_1_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR0_IP_1_MSB 15 +#define M0PLUS_NVIC_IPR0_IP_1_LSB 14 +#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_0 +// Description : Priority of interrupt 0 +#define M0PLUS_NVIC_IPR0_IP_0_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_0_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR0_IP_0_MSB 7 +#define M0PLUS_NVIC_IPR0_IP_0_LSB 6 +#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR1 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR1_OFFSET 0x0000e404 +#define M0PLUS_NVIC_IPR1_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_7 +// Description : Priority of interrupt 7 +#define M0PLUS_NVIC_IPR1_IP_7_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_7_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR1_IP_7_MSB 31 +#define M0PLUS_NVIC_IPR1_IP_7_LSB 30 +#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_6 +// Description : Priority of interrupt 6 +#define M0PLUS_NVIC_IPR1_IP_6_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_6_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR1_IP_6_MSB 23 +#define M0PLUS_NVIC_IPR1_IP_6_LSB 22 +#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_5 +// Description : Priority of interrupt 5 +#define M0PLUS_NVIC_IPR1_IP_5_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_5_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR1_IP_5_MSB 15 +#define M0PLUS_NVIC_IPR1_IP_5_LSB 14 +#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_4 +// Description : Priority of interrupt 4 +#define M0PLUS_NVIC_IPR1_IP_4_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_4_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR1_IP_4_MSB 7 +#define M0PLUS_NVIC_IPR1_IP_4_LSB 6 +#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR2 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR2_OFFSET 0x0000e408 +#define M0PLUS_NVIC_IPR2_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_11 +// Description : Priority of interrupt 11 +#define M0PLUS_NVIC_IPR2_IP_11_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_11_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR2_IP_11_MSB 31 +#define M0PLUS_NVIC_IPR2_IP_11_LSB 30 +#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_10 +// Description : Priority of interrupt 10 +#define M0PLUS_NVIC_IPR2_IP_10_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_10_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR2_IP_10_MSB 23 +#define M0PLUS_NVIC_IPR2_IP_10_LSB 22 +#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_9 +// Description : Priority of interrupt 9 +#define M0PLUS_NVIC_IPR2_IP_9_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_9_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR2_IP_9_MSB 15 +#define M0PLUS_NVIC_IPR2_IP_9_LSB 14 +#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_8 +// Description : Priority of interrupt 8 +#define M0PLUS_NVIC_IPR2_IP_8_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_8_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR2_IP_8_MSB 7 +#define M0PLUS_NVIC_IPR2_IP_8_LSB 6 +#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR3 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR3_OFFSET 0x0000e40c +#define M0PLUS_NVIC_IPR3_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_15 +// Description : Priority of interrupt 15 +#define M0PLUS_NVIC_IPR3_IP_15_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_15_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR3_IP_15_MSB 31 +#define M0PLUS_NVIC_IPR3_IP_15_LSB 30 +#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_14 +// Description : Priority of interrupt 14 +#define M0PLUS_NVIC_IPR3_IP_14_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_14_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR3_IP_14_MSB 23 +#define M0PLUS_NVIC_IPR3_IP_14_LSB 22 +#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_13 +// Description : Priority of interrupt 13 +#define M0PLUS_NVIC_IPR3_IP_13_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_13_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR3_IP_13_MSB 15 +#define M0PLUS_NVIC_IPR3_IP_13_LSB 14 +#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_12 +// Description : Priority of interrupt 12 +#define M0PLUS_NVIC_IPR3_IP_12_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_12_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR3_IP_12_MSB 7 +#define M0PLUS_NVIC_IPR3_IP_12_LSB 6 +#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR4 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR4_OFFSET 0x0000e410 +#define M0PLUS_NVIC_IPR4_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_19 +// Description : Priority of interrupt 19 +#define M0PLUS_NVIC_IPR4_IP_19_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_19_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR4_IP_19_MSB 31 +#define M0PLUS_NVIC_IPR4_IP_19_LSB 30 +#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_18 +// Description : Priority of interrupt 18 +#define M0PLUS_NVIC_IPR4_IP_18_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_18_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR4_IP_18_MSB 23 +#define M0PLUS_NVIC_IPR4_IP_18_LSB 22 +#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_17 +// Description : Priority of interrupt 17 +#define M0PLUS_NVIC_IPR4_IP_17_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_17_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR4_IP_17_MSB 15 +#define M0PLUS_NVIC_IPR4_IP_17_LSB 14 +#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_16 +// Description : Priority of interrupt 16 +#define M0PLUS_NVIC_IPR4_IP_16_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_16_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR4_IP_16_MSB 7 +#define M0PLUS_NVIC_IPR4_IP_16_LSB 6 +#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR5 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR5_OFFSET 0x0000e414 +#define M0PLUS_NVIC_IPR5_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR5_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_23 +// Description : Priority of interrupt 23 +#define M0PLUS_NVIC_IPR5_IP_23_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_23_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR5_IP_23_MSB 31 +#define M0PLUS_NVIC_IPR5_IP_23_LSB 30 +#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_22 +// Description : Priority of interrupt 22 +#define M0PLUS_NVIC_IPR5_IP_22_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_22_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR5_IP_22_MSB 23 +#define M0PLUS_NVIC_IPR5_IP_22_LSB 22 +#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_21 +// Description : Priority of interrupt 21 +#define M0PLUS_NVIC_IPR5_IP_21_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_21_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR5_IP_21_MSB 15 +#define M0PLUS_NVIC_IPR5_IP_21_LSB 14 +#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_20 +// Description : Priority of interrupt 20 +#define M0PLUS_NVIC_IPR5_IP_20_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_20_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR5_IP_20_MSB 7 +#define M0PLUS_NVIC_IPR5_IP_20_LSB 6 +#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR6 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR6_OFFSET 0x0000e418 +#define M0PLUS_NVIC_IPR6_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR6_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_27 +// Description : Priority of interrupt 27 +#define M0PLUS_NVIC_IPR6_IP_27_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_27_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR6_IP_27_MSB 31 +#define M0PLUS_NVIC_IPR6_IP_27_LSB 30 +#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_26 +// Description : Priority of interrupt 26 +#define M0PLUS_NVIC_IPR6_IP_26_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_26_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR6_IP_26_MSB 23 +#define M0PLUS_NVIC_IPR6_IP_26_LSB 22 +#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_25 +// Description : Priority of interrupt 25 +#define M0PLUS_NVIC_IPR6_IP_25_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_25_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR6_IP_25_MSB 15 +#define M0PLUS_NVIC_IPR6_IP_25_LSB 14 +#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_24 +// Description : Priority of interrupt 24 +#define M0PLUS_NVIC_IPR6_IP_24_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_24_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR6_IP_24_MSB 7 +#define M0PLUS_NVIC_IPR6_IP_24_LSB 6 +#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR7 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR7_OFFSET 0x0000e41c +#define M0PLUS_NVIC_IPR7_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR7_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_31 +// Description : Priority of interrupt 31 +#define M0PLUS_NVIC_IPR7_IP_31_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_31_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR7_IP_31_MSB 31 +#define M0PLUS_NVIC_IPR7_IP_31_LSB 30 +#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_30 +// Description : Priority of interrupt 30 +#define M0PLUS_NVIC_IPR7_IP_30_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_30_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR7_IP_30_MSB 23 +#define M0PLUS_NVIC_IPR7_IP_30_LSB 22 +#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_29 +// Description : Priority of interrupt 29 +#define M0PLUS_NVIC_IPR7_IP_29_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_29_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR7_IP_29_MSB 15 +#define M0PLUS_NVIC_IPR7_IP_29_LSB 14 +#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_28 +// Description : Priority of interrupt 28 +#define M0PLUS_NVIC_IPR7_IP_28_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_28_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR7_IP_28_MSB 7 +#define M0PLUS_NVIC_IPR7_IP_28_LSB 6 +#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_CPUID +// Description : Read the CPU ID Base Register to determine: the ID number of +// the processor core, the version number of the processor core, +// the implementation details of the processor core. +#define M0PLUS_CPUID_OFFSET 0x0000ed00 +#define M0PLUS_CPUID_BITS 0xffffffff +#define M0PLUS_CPUID_RESET 0x410cc601 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_IMPLEMENTER +// Description : Implementor code: 0x41 = ARM +#define M0PLUS_CPUID_IMPLEMENTER_RESET 0x41 +#define M0PLUS_CPUID_IMPLEMENTER_BITS 0xff000000 +#define M0PLUS_CPUID_IMPLEMENTER_MSB 31 +#define M0PLUS_CPUID_IMPLEMENTER_LSB 24 +#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_VARIANT +// Description : Major revision number n in the rnpm revision status: +// 0x0 = Revision 0. +#define M0PLUS_CPUID_VARIANT_RESET 0x0 +#define M0PLUS_CPUID_VARIANT_BITS 0x00f00000 +#define M0PLUS_CPUID_VARIANT_MSB 23 +#define M0PLUS_CPUID_VARIANT_LSB 20 +#define M0PLUS_CPUID_VARIANT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_ARCHITECTURE +// Description : Constant that defines the architecture of the processor: +// 0xC = ARMv6-M architecture. +#define M0PLUS_CPUID_ARCHITECTURE_RESET 0xc +#define M0PLUS_CPUID_ARCHITECTURE_BITS 0x000f0000 +#define M0PLUS_CPUID_ARCHITECTURE_MSB 19 +#define M0PLUS_CPUID_ARCHITECTURE_LSB 16 +#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_PARTNO +// Description : Number of processor within family: 0xC60 = Cortex-M0+ +#define M0PLUS_CPUID_PARTNO_RESET 0xc60 +#define M0PLUS_CPUID_PARTNO_BITS 0x0000fff0 +#define M0PLUS_CPUID_PARTNO_MSB 15 +#define M0PLUS_CPUID_PARTNO_LSB 4 +#define M0PLUS_CPUID_PARTNO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_REVISION +// Description : Minor revision number m in the rnpm revision status: +// 0x1 = Patch 1. +#define M0PLUS_CPUID_REVISION_RESET 0x1 +#define M0PLUS_CPUID_REVISION_BITS 0x0000000f +#define M0PLUS_CPUID_REVISION_MSB 3 +#define M0PLUS_CPUID_REVISION_LSB 0 +#define M0PLUS_CPUID_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_ICSR +// Description : Use the Interrupt Control State Register to set a pending +// Non-Maskable Interrupt (NMI), set or clear a pending PendSV, +// set or clear a pending SysTick, check for pending exceptions, +// check the vector number of the highest priority pended +// exception, check the vector number of the active exception. +#define M0PLUS_ICSR_OFFSET 0x0000ed04 +#define M0PLUS_ICSR_BITS 0x9edff1ff +#define M0PLUS_ICSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_NMIPENDSET +// Description : Setting this bit will activate an NMI. Since NMI is the highest +// priority exception, it will activate as soon as it is +// registered. +// NMI set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes NMI exception state to pending. +// Read: +// 0 = NMI exception is not pending. +// 1 = NMI exception is pending. +// Because NMI is the highest-priority exception, normally the +// processor enters the NMI +// exception handler as soon as it detects a write of 1 to this +// bit. Entering the handler then clears +// this bit to 0. This means a read of this bit by the NMI +// exception handler returns 1 only if the +// NMI signal is reasserted while the processor is executing that +// handler. +#define M0PLUS_ICSR_NMIPENDSET_RESET 0x0 +#define M0PLUS_ICSR_NMIPENDSET_BITS 0x80000000 +#define M0PLUS_ICSR_NMIPENDSET_MSB 31 +#define M0PLUS_ICSR_NMIPENDSET_LSB 31 +#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSVSET +// Description : PendSV set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes PendSV exception state to pending. +// Read: +// 0 = PendSV exception is not pending. +// 1 = PendSV exception is pending. +// Writing 1 to this bit is the only way to set the PendSV +// exception state to pending. +#define M0PLUS_ICSR_PENDSVSET_RESET 0x0 +#define M0PLUS_ICSR_PENDSVSET_BITS 0x10000000 +#define M0PLUS_ICSR_PENDSVSET_MSB 28 +#define M0PLUS_ICSR_PENDSVSET_LSB 28 +#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSVCLR +// Description : PendSV clear-pending bit. +// Write: +// 0 = No effect. +// 1 = Removes the pending state from the PendSV exception. +#define M0PLUS_ICSR_PENDSVCLR_RESET 0x0 +#define M0PLUS_ICSR_PENDSVCLR_BITS 0x08000000 +#define M0PLUS_ICSR_PENDSVCLR_MSB 27 +#define M0PLUS_ICSR_PENDSVCLR_LSB 27 +#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSTSET +// Description : SysTick exception set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes SysTick exception state to pending. +// Read: +// 0 = SysTick exception is not pending. +// 1 = SysTick exception is pending. +#define M0PLUS_ICSR_PENDSTSET_RESET 0x0 +#define M0PLUS_ICSR_PENDSTSET_BITS 0x04000000 +#define M0PLUS_ICSR_PENDSTSET_MSB 26 +#define M0PLUS_ICSR_PENDSTSET_LSB 26 +#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSTCLR +// Description : SysTick exception clear-pending bit. +// Write: +// 0 = No effect. +// 1 = Removes the pending state from the SysTick exception. +// This bit is WO. On a register read its value is Unknown. +#define M0PLUS_ICSR_PENDSTCLR_RESET 0x0 +#define M0PLUS_ICSR_PENDSTCLR_BITS 0x02000000 +#define M0PLUS_ICSR_PENDSTCLR_MSB 25 +#define M0PLUS_ICSR_PENDSTCLR_LSB 25 +#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_ISRPREEMPT +// Description : The system can only access this bit when the core is halted. It +// indicates that a pending interrupt is to be taken in the next +// running cycle. If C_MASKINTS is clear in the Debug Halting +// Control and Status Register, the interrupt is serviced. +#define M0PLUS_ICSR_ISRPREEMPT_RESET 0x0 +#define M0PLUS_ICSR_ISRPREEMPT_BITS 0x00800000 +#define M0PLUS_ICSR_ISRPREEMPT_MSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_LSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_ISRPENDING +// Description : External interrupt pending flag +#define M0PLUS_ICSR_ISRPENDING_RESET 0x0 +#define M0PLUS_ICSR_ISRPENDING_BITS 0x00400000 +#define M0PLUS_ICSR_ISRPENDING_MSB 22 +#define M0PLUS_ICSR_ISRPENDING_LSB 22 +#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_VECTPENDING +// Description : Indicates the exception number for the highest priority pending +// exception: 0 = no pending exceptions. Non zero = The pending +// state includes the effect of memory-mapped enable and mask +// registers. It does not include the PRIMASK special-purpose +// register qualifier. +#define M0PLUS_ICSR_VECTPENDING_RESET 0x000 +#define M0PLUS_ICSR_VECTPENDING_BITS 0x001ff000 +#define M0PLUS_ICSR_VECTPENDING_MSB 20 +#define M0PLUS_ICSR_VECTPENDING_LSB 12 +#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_VECTACTIVE +// Description : Active exception number field. Reset clears the VECTACTIVE +// field. +#define M0PLUS_ICSR_VECTACTIVE_RESET 0x000 +#define M0PLUS_ICSR_VECTACTIVE_BITS 0x000001ff +#define M0PLUS_ICSR_VECTACTIVE_MSB 8 +#define M0PLUS_ICSR_VECTACTIVE_LSB 0 +#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_VTOR +// Description : The VTOR holds the vector table offset address. +#define M0PLUS_VTOR_OFFSET 0x0000ed08 +#define M0PLUS_VTOR_BITS 0xffffff00 +#define M0PLUS_VTOR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_VTOR_TBLOFF +// Description : Bits [31:8] of the indicate the vector table offset address. +#define M0PLUS_VTOR_TBLOFF_RESET 0x000000 +#define M0PLUS_VTOR_TBLOFF_BITS 0xffffff00 +#define M0PLUS_VTOR_TBLOFF_MSB 31 +#define M0PLUS_VTOR_TBLOFF_LSB 8 +#define M0PLUS_VTOR_TBLOFF_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_AIRCR +// Description : Use the Application Interrupt and Reset Control Register to: +// determine data endianness, clear all active state information +// from debug halt mode, request a system reset. +#define M0PLUS_AIRCR_OFFSET 0x0000ed0c +#define M0PLUS_AIRCR_BITS 0xffff8006 +#define M0PLUS_AIRCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_VECTKEY +// Description : Register key: +// Reads as Unknown +// On writes, write 0x05FA to VECTKEY, otherwise the write is +// ignored. +#define M0PLUS_AIRCR_VECTKEY_RESET 0x0000 +#define M0PLUS_AIRCR_VECTKEY_BITS 0xffff0000 +#define M0PLUS_AIRCR_VECTKEY_MSB 31 +#define M0PLUS_AIRCR_VECTKEY_LSB 16 +#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_ENDIANESS +// Description : Data endianness implemented: +// 0 = Little-endian. +#define M0PLUS_AIRCR_ENDIANESS_RESET 0x0 +#define M0PLUS_AIRCR_ENDIANESS_BITS 0x00008000 +#define M0PLUS_AIRCR_ENDIANESS_MSB 15 +#define M0PLUS_AIRCR_ENDIANESS_LSB 15 +#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_SYSRESETREQ +// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the +// outer system to be asserted to request a reset. The intention +// is to force a large system reset of all major components except +// for debug. The C_HALT bit in the DHCSR is cleared as a result +// of the system reset requested. The debugger does not lose +// contact with the device. +#define M0PLUS_AIRCR_SYSRESETREQ_RESET 0x0 +#define M0PLUS_AIRCR_SYSRESETREQ_BITS 0x00000004 +#define M0PLUS_AIRCR_SYSRESETREQ_MSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_LSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_VECTCLRACTIVE +// Description : Clears all active state information for fixed and configurable +// exceptions. This bit: is self-clearing, can only be set by the +// DAP when the core is halted. When set: clears all active +// exception status of the processor, forces a return to Thread +// mode, forces an IPSR of 0. A debugger must re-initialize the +// stack. +#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET 0x0 +#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS 0x00000002 +#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SCR +// Description : System Control Register. Use the System Control Register for +// power-management functions: signal to the system when the +// processor can enter a low power state, control how the +// processor enters and exits low power states. +#define M0PLUS_SCR_OFFSET 0x0000ed10 +#define M0PLUS_SCR_BITS 0x00000016 +#define M0PLUS_SCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SEVONPEND +// Description : Send Event on Pending bit: +// 0 = Only enabled interrupts or events can wakeup the processor, +// disabled interrupts are excluded. +// 1 = Enabled events and all interrupts, including disabled +// interrupts, can wakeup the processor. +// When an event or interrupt becomes pending, the event signal +// wakes up the processor from WFE. If the +// processor is not waiting for an event, the event is registered +// and affects the next WFE. +// The processor also wakes up on execution of an SEV instruction +// or an external event. +#define M0PLUS_SCR_SEVONPEND_RESET 0x0 +#define M0PLUS_SCR_SEVONPEND_BITS 0x00000010 +#define M0PLUS_SCR_SEVONPEND_MSB 4 +#define M0PLUS_SCR_SEVONPEND_LSB 4 +#define M0PLUS_SCR_SEVONPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SLEEPDEEP +// Description : Controls whether the processor uses sleep or deep sleep as its +// low power mode: +// 0 = Sleep. +// 1 = Deep sleep. +#define M0PLUS_SCR_SLEEPDEEP_RESET 0x0 +#define M0PLUS_SCR_SLEEPDEEP_BITS 0x00000004 +#define M0PLUS_SCR_SLEEPDEEP_MSB 2 +#define M0PLUS_SCR_SLEEPDEEP_LSB 2 +#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SLEEPONEXIT +// Description : Indicates sleep-on-exit when returning from Handler mode to +// Thread mode: +// 0 = Do not sleep when returning to Thread mode. +// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread +// mode. +// Setting this bit to 1 enables an interrupt driven application +// to avoid returning to an empty main application. +#define M0PLUS_SCR_SLEEPONEXIT_RESET 0x0 +#define M0PLUS_SCR_SLEEPONEXIT_BITS 0x00000002 +#define M0PLUS_SCR_SLEEPONEXIT_MSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_LSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_CCR +// Description : The Configuration and Control Register permanently enables +// stack alignment and causes unaligned accesses to result in a +// Hard Fault. +#define M0PLUS_CCR_OFFSET 0x0000ed14 +#define M0PLUS_CCR_BITS 0x00000208 +#define M0PLUS_CCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CCR_STKALIGN +// Description : Always reads as one, indicates 8-byte stack alignment on +// exception entry. On exception entry, the processor uses bit[9] +// of the stacked PSR to indicate the stack alignment. On return +// from the exception it uses this stacked bit to restore the +// correct stack alignment. +#define M0PLUS_CCR_STKALIGN_RESET 0x0 +#define M0PLUS_CCR_STKALIGN_BITS 0x00000200 +#define M0PLUS_CCR_STKALIGN_MSB 9 +#define M0PLUS_CCR_STKALIGN_LSB 9 +#define M0PLUS_CCR_STKALIGN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CCR_UNALIGN_TRP +// Description : Always reads as one, indicates that all unaligned accesses +// generate a HardFault. +#define M0PLUS_CCR_UNALIGN_TRP_RESET 0x0 +#define M0PLUS_CCR_UNALIGN_TRP_BITS 0x00000008 +#define M0PLUS_CCR_UNALIGN_TRP_MSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_LSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_SHPR2 +// Description : System handlers are a special class of exception handler that +// can have their priority set to any of the priority levels. Use +// the System Handler Priority Register 2 to set the priority of +// SVCall. +#define M0PLUS_SHPR2_OFFSET 0x0000ed1c +#define M0PLUS_SHPR2_BITS 0xc0000000 +#define M0PLUS_SHPR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR2_PRI_11 +// Description : Priority of system handler 11, SVCall +#define M0PLUS_SHPR2_PRI_11_RESET 0x0 +#define M0PLUS_SHPR2_PRI_11_BITS 0xc0000000 +#define M0PLUS_SHPR2_PRI_11_MSB 31 +#define M0PLUS_SHPR2_PRI_11_LSB 30 +#define M0PLUS_SHPR2_PRI_11_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SHPR3 +// Description : System handlers are a special class of exception handler that +// can have their priority set to any of the priority levels. Use +// the System Handler Priority Register 3 to set the priority of +// PendSV and SysTick. +#define M0PLUS_SHPR3_OFFSET 0x0000ed20 +#define M0PLUS_SHPR3_BITS 0xc0c00000 +#define M0PLUS_SHPR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR3_PRI_15 +// Description : Priority of system handler 15, SysTick +#define M0PLUS_SHPR3_PRI_15_RESET 0x0 +#define M0PLUS_SHPR3_PRI_15_BITS 0xc0000000 +#define M0PLUS_SHPR3_PRI_15_MSB 31 +#define M0PLUS_SHPR3_PRI_15_LSB 30 +#define M0PLUS_SHPR3_PRI_15_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR3_PRI_14 +// Description : Priority of system handler 14, PendSV +#define M0PLUS_SHPR3_PRI_14_RESET 0x0 +#define M0PLUS_SHPR3_PRI_14_BITS 0x00c00000 +#define M0PLUS_SHPR3_PRI_14_MSB 23 +#define M0PLUS_SHPR3_PRI_14_LSB 22 +#define M0PLUS_SHPR3_PRI_14_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SHCSR +// Description : Use the System Handler Control and State Register to determine +// or clear the pending status of SVCall. +#define M0PLUS_SHCSR_OFFSET 0x0000ed24 +#define M0PLUS_SHCSR_BITS 0x00008000 +#define M0PLUS_SHCSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHCSR_SVCALLPENDED +// Description : Reads as 1 if SVCall is Pending. Write 1 to set pending +// SVCall, write 0 to clear pending SVCall. +#define M0PLUS_SHCSR_SVCALLPENDED_RESET 0x0 +#define M0PLUS_SHCSR_SVCALLPENDED_BITS 0x00008000 +#define M0PLUS_SHCSR_SVCALLPENDED_MSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_LSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_TYPE +// Description : Read the MPU Type Register to determine if the processor +// implements an MPU, and how many regions the MPU supports. +#define M0PLUS_MPU_TYPE_OFFSET 0x0000ed90 +#define M0PLUS_MPU_TYPE_BITS 0x00ffff01 +#define M0PLUS_MPU_TYPE_RESET 0x00000800 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_IREGION +// Description : Instruction region. Reads as zero as ARMv6-M only supports a +// unified MPU. +#define M0PLUS_MPU_TYPE_IREGION_RESET 0x00 +#define M0PLUS_MPU_TYPE_IREGION_BITS 0x00ff0000 +#define M0PLUS_MPU_TYPE_IREGION_MSB 23 +#define M0PLUS_MPU_TYPE_IREGION_LSB 16 +#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_DREGION +// Description : Number of regions supported by the MPU. +#define M0PLUS_MPU_TYPE_DREGION_RESET 0x08 +#define M0PLUS_MPU_TYPE_DREGION_BITS 0x0000ff00 +#define M0PLUS_MPU_TYPE_DREGION_MSB 15 +#define M0PLUS_MPU_TYPE_DREGION_LSB 8 +#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_SEPARATE +// Description : Indicates support for separate instruction and data address +// maps. Reads as 0 as ARMv6-M only supports a unified MPU. +#define M0PLUS_MPU_TYPE_SEPARATE_RESET 0x0 +#define M0PLUS_MPU_TYPE_SEPARATE_BITS 0x00000001 +#define M0PLUS_MPU_TYPE_SEPARATE_MSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_LSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_MPU_CTRL +// Description : Use the MPU Control Register to enable and disable the MPU, and +// to control whether the default memory map is enabled as a +// background region for privileged accesses, and whether the MPU +// is enabled for HardFaults and NMIs. +#define M0PLUS_MPU_CTRL_OFFSET 0x0000ed94 +#define M0PLUS_MPU_CTRL_BITS 0x00000007 +#define M0PLUS_MPU_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_PRIVDEFENA +// Description : Controls whether the default memory map is enabled as a +// background region for privileged accesses. This bit is ignored +// when ENABLE is clear. +// 0 = If the MPU is enabled, disables use of the default memory +// map. Any memory access to a location not +// covered by any enabled region causes a fault. +// 1 = If the MPU is enabled, enables use of the default memory +// map as a background region for privileged software accesses. +// When enabled, the background region acts as if it is region +// number -1. Any region that is defined and enabled has priority +// over this default map. +#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET 0x0 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS 0x00000004 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_HFNMIENA +// Description : Controls the use of the MPU for HardFaults and NMIs. Setting +// this bit when ENABLE is clear results in UNPREDICTABLE +// behaviour. +// When the MPU is enabled: +// 0 = MPU is disabled during HardFault and NMI handlers, +// regardless of the value of the ENABLE bit. +// 1 = the MPU is enabled during HardFault and NMI handlers. +#define M0PLUS_MPU_CTRL_HFNMIENA_RESET 0x0 +#define M0PLUS_MPU_CTRL_HFNMIENA_BITS 0x00000002 +#define M0PLUS_MPU_CTRL_HFNMIENA_MSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_LSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_ENABLE +// Description : Enables the MPU. If the MPU is disabled, privileged and +// unprivileged accesses use the default memory map. +// 0 = MPU disabled. +// 1 = MPU enabled. +#define M0PLUS_MPU_CTRL_ENABLE_RESET 0x0 +#define M0PLUS_MPU_CTRL_ENABLE_BITS 0x00000001 +#define M0PLUS_MPU_CTRL_ENABLE_MSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_LSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RNR +// Description : Use the MPU Region Number Register to select the region +// currently accessed by MPU_RBAR and MPU_RASR. +#define M0PLUS_MPU_RNR_OFFSET 0x0000ed98 +#define M0PLUS_MPU_RNR_BITS 0x0000000f +#define M0PLUS_MPU_RNR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RNR_REGION +// Description : Indicates the MPU region referenced by the MPU_RBAR and +// MPU_RASR registers. +// The MPU supports 8 memory regions, so the permitted values of +// this field are 0-7. +#define M0PLUS_MPU_RNR_REGION_RESET 0x0 +#define M0PLUS_MPU_RNR_REGION_BITS 0x0000000f +#define M0PLUS_MPU_RNR_REGION_MSB 3 +#define M0PLUS_MPU_RNR_REGION_LSB 0 +#define M0PLUS_MPU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RBAR +// Description : Read the MPU Region Base Address Register to determine the base +// address of the region identified by MPU_RNR. Write to update +// the base address of said region or that of a specified region, +// with whose number MPU_RNR will also be updated. +#define M0PLUS_MPU_RBAR_OFFSET 0x0000ed9c +#define M0PLUS_MPU_RBAR_BITS 0xffffff1f +#define M0PLUS_MPU_RBAR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_ADDR +// Description : Base address of the region. +#define M0PLUS_MPU_RBAR_ADDR_RESET 0x000000 +#define M0PLUS_MPU_RBAR_ADDR_BITS 0xffffff00 +#define M0PLUS_MPU_RBAR_ADDR_MSB 31 +#define M0PLUS_MPU_RBAR_ADDR_LSB 8 +#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_VALID +// Description : On writes, indicates whether the write must update the base +// address of the region identified by the REGION field, updating +// the MPU_RNR to indicate this new region. +// Write: +// 0 = MPU_RNR not changed, and the processor: +// Updates the base address for the region specified in the +// MPU_RNR. +// Ignores the value of the REGION field. +// 1 = The processor: +// Updates the value of the MPU_RNR to the value of the REGION +// field. +// Updates the base address for the region specified in the REGION +// field. +// Always reads as zero. +#define M0PLUS_MPU_RBAR_VALID_RESET 0x0 +#define M0PLUS_MPU_RBAR_VALID_BITS 0x00000010 +#define M0PLUS_MPU_RBAR_VALID_MSB 4 +#define M0PLUS_MPU_RBAR_VALID_LSB 4 +#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_REGION +// Description : On writes, specifies the number of the region whose base +// address to update provided VALID is set written as 1. On reads, +// returns bits [3:0] of MPU_RNR. +#define M0PLUS_MPU_RBAR_REGION_RESET 0x0 +#define M0PLUS_MPU_RBAR_REGION_BITS 0x0000000f +#define M0PLUS_MPU_RBAR_REGION_MSB 3 +#define M0PLUS_MPU_RBAR_REGION_LSB 0 +#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RASR +// Description : Use the MPU Region Attribute and Size Register to define the +// size, access behaviour and memory type of the region identified +// by MPU_RNR, and enable that region. +#define M0PLUS_MPU_RASR_OFFSET 0x0000eda0 +#define M0PLUS_MPU_RASR_BITS 0xffffff3f +#define M0PLUS_MPU_RASR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_ATTRS +// Description : The MPU Region Attribute field. Use to define the region +// attribute control. +// 28 = XN: Instruction access disable bit: +// 0 = Instruction fetches enabled. +// 1 = Instruction fetches disabled. +// 26:24 = AP: Access permission field +// 18 = S: Shareable bit +// 17 = C: Cacheable bit +// 16 = B: Bufferable bit +#define M0PLUS_MPU_RASR_ATTRS_RESET 0x0000 +#define M0PLUS_MPU_RASR_ATTRS_BITS 0xffff0000 +#define M0PLUS_MPU_RASR_ATTRS_MSB 31 +#define M0PLUS_MPU_RASR_ATTRS_LSB 16 +#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_SRD +// Description : Subregion Disable. For regions of 256 bytes or larger, each bit +// of this field controls whether one of the eight equal +// subregions is enabled. +#define M0PLUS_MPU_RASR_SRD_RESET 0x00 +#define M0PLUS_MPU_RASR_SRD_BITS 0x0000ff00 +#define M0PLUS_MPU_RASR_SRD_MSB 15 +#define M0PLUS_MPU_RASR_SRD_LSB 8 +#define M0PLUS_MPU_RASR_SRD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_SIZE +// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). +// The minimum permitted value is 7 (b00111) = 256Bytes +#define M0PLUS_MPU_RASR_SIZE_RESET 0x00 +#define M0PLUS_MPU_RASR_SIZE_BITS 0x0000003e +#define M0PLUS_MPU_RASR_SIZE_MSB 5 +#define M0PLUS_MPU_RASR_SIZE_LSB 1 +#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_ENABLE +// Description : Enables the region. +#define M0PLUS_MPU_RASR_ENABLE_RESET 0x0 +#define M0PLUS_MPU_RASR_ENABLE_BITS 0x00000001 +#define M0PLUS_MPU_RASR_ENABLE_MSB 0 +#define M0PLUS_MPU_RASR_ENABLE_LSB 0 +#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_M0PLUS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h new file mode 100644 index 00000000000..92242bd44d5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h @@ -0,0 +1,2300 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_BANK0 +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED +#define HARDWARE_REGS_PADS_BANK0_DEFINED +// ============================================================================= +// Register : PADS_BANK0_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x00000000 +#define PADS_BANK0_VOLTAGE_SELECT_BITS 0x00000001 +#define PADS_BANK0_VOLTAGE_SELECT_RESET 0x00000000 +#define PADS_BANK0_VOLTAGE_SELECT_MSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_LSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 0x0 +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 0x1 +// ============================================================================= +// Register : PADS_BANK0_GPIO0 +// Description : Pad control register +#define PADS_BANK0_GPIO0_OFFSET 0x00000004 +#define PADS_BANK0_GPIO0_BITS 0x000000ff +#define PADS_BANK0_GPIO0_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO0_OD_RESET 0x0 +#define PADS_BANK0_GPIO0_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO0_OD_MSB 7 +#define PADS_BANK0_GPIO0_OD_LSB 7 +#define PADS_BANK0_GPIO0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_IE +// Description : Input enable +#define PADS_BANK0_GPIO0_IE_RESET 0x1 +#define PADS_BANK0_GPIO0_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO0_IE_MSB 6 +#define PADS_BANK0_GPIO0_IE_LSB 6 +#define PADS_BANK0_GPIO0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO0_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO0_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO0_DRIVE_MSB 5 +#define PADS_BANK0_GPIO0_DRIVE_LSB 4 +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO0_PUE_RESET 0x0 +#define PADS_BANK0_GPIO0_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO0_PUE_MSB 3 +#define PADS_BANK0_GPIO0_PUE_LSB 3 +#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO0_PDE_RESET 0x1 +#define PADS_BANK0_GPIO0_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO0_PDE_MSB 2 +#define PADS_BANK0_GPIO0_PDE_LSB 2 +#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO0_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO0_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO0_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO0_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO0_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO0_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO1 +// Description : Pad control register +#define PADS_BANK0_GPIO1_OFFSET 0x00000008 +#define PADS_BANK0_GPIO1_BITS 0x000000ff +#define PADS_BANK0_GPIO1_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO1_OD_RESET 0x0 +#define PADS_BANK0_GPIO1_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO1_OD_MSB 7 +#define PADS_BANK0_GPIO1_OD_LSB 7 +#define PADS_BANK0_GPIO1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_IE +// Description : Input enable +#define PADS_BANK0_GPIO1_IE_RESET 0x1 +#define PADS_BANK0_GPIO1_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO1_IE_MSB 6 +#define PADS_BANK0_GPIO1_IE_LSB 6 +#define PADS_BANK0_GPIO1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO1_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO1_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO1_DRIVE_MSB 5 +#define PADS_BANK0_GPIO1_DRIVE_LSB 4 +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO1_PUE_RESET 0x0 +#define PADS_BANK0_GPIO1_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO1_PUE_MSB 3 +#define PADS_BANK0_GPIO1_PUE_LSB 3 +#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO1_PDE_RESET 0x1 +#define PADS_BANK0_GPIO1_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO1_PDE_MSB 2 +#define PADS_BANK0_GPIO1_PDE_LSB 2 +#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO1_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO1_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO1_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO1_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO1_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO1_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO2 +// Description : Pad control register +#define PADS_BANK0_GPIO2_OFFSET 0x0000000c +#define PADS_BANK0_GPIO2_BITS 0x000000ff +#define PADS_BANK0_GPIO2_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO2_OD_RESET 0x0 +#define PADS_BANK0_GPIO2_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO2_OD_MSB 7 +#define PADS_BANK0_GPIO2_OD_LSB 7 +#define PADS_BANK0_GPIO2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_IE +// Description : Input enable +#define PADS_BANK0_GPIO2_IE_RESET 0x1 +#define PADS_BANK0_GPIO2_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO2_IE_MSB 6 +#define PADS_BANK0_GPIO2_IE_LSB 6 +#define PADS_BANK0_GPIO2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO2_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO2_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO2_DRIVE_MSB 5 +#define PADS_BANK0_GPIO2_DRIVE_LSB 4 +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO2_PUE_RESET 0x0 +#define PADS_BANK0_GPIO2_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO2_PUE_MSB 3 +#define PADS_BANK0_GPIO2_PUE_LSB 3 +#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO2_PDE_RESET 0x1 +#define PADS_BANK0_GPIO2_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO2_PDE_MSB 2 +#define PADS_BANK0_GPIO2_PDE_LSB 2 +#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO2_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO2_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO2_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO2_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO2_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO2_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO3 +// Description : Pad control register +#define PADS_BANK0_GPIO3_OFFSET 0x00000010 +#define PADS_BANK0_GPIO3_BITS 0x000000ff +#define PADS_BANK0_GPIO3_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO3_OD_RESET 0x0 +#define PADS_BANK0_GPIO3_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO3_OD_MSB 7 +#define PADS_BANK0_GPIO3_OD_LSB 7 +#define PADS_BANK0_GPIO3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_IE +// Description : Input enable +#define PADS_BANK0_GPIO3_IE_RESET 0x1 +#define PADS_BANK0_GPIO3_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO3_IE_MSB 6 +#define PADS_BANK0_GPIO3_IE_LSB 6 +#define PADS_BANK0_GPIO3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO3_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO3_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO3_DRIVE_MSB 5 +#define PADS_BANK0_GPIO3_DRIVE_LSB 4 +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO3_PUE_RESET 0x0 +#define PADS_BANK0_GPIO3_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO3_PUE_MSB 3 +#define PADS_BANK0_GPIO3_PUE_LSB 3 +#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO3_PDE_RESET 0x1 +#define PADS_BANK0_GPIO3_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO3_PDE_MSB 2 +#define PADS_BANK0_GPIO3_PDE_LSB 2 +#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO3_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO3_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO3_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO3_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO3_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO3_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO4 +// Description : Pad control register +#define PADS_BANK0_GPIO4_OFFSET 0x00000014 +#define PADS_BANK0_GPIO4_BITS 0x000000ff +#define PADS_BANK0_GPIO4_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO4_OD_RESET 0x0 +#define PADS_BANK0_GPIO4_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO4_OD_MSB 7 +#define PADS_BANK0_GPIO4_OD_LSB 7 +#define PADS_BANK0_GPIO4_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_IE +// Description : Input enable +#define PADS_BANK0_GPIO4_IE_RESET 0x1 +#define PADS_BANK0_GPIO4_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO4_IE_MSB 6 +#define PADS_BANK0_GPIO4_IE_LSB 6 +#define PADS_BANK0_GPIO4_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO4_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO4_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO4_DRIVE_MSB 5 +#define PADS_BANK0_GPIO4_DRIVE_LSB 4 +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO4_PUE_RESET 0x0 +#define PADS_BANK0_GPIO4_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO4_PUE_MSB 3 +#define PADS_BANK0_GPIO4_PUE_LSB 3 +#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO4_PDE_RESET 0x1 +#define PADS_BANK0_GPIO4_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO4_PDE_MSB 2 +#define PADS_BANK0_GPIO4_PDE_LSB 2 +#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO4_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO4_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO4_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO4_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO4_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO4_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO5 +// Description : Pad control register +#define PADS_BANK0_GPIO5_OFFSET 0x00000018 +#define PADS_BANK0_GPIO5_BITS 0x000000ff +#define PADS_BANK0_GPIO5_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO5_OD_RESET 0x0 +#define PADS_BANK0_GPIO5_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO5_OD_MSB 7 +#define PADS_BANK0_GPIO5_OD_LSB 7 +#define PADS_BANK0_GPIO5_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_IE +// Description : Input enable +#define PADS_BANK0_GPIO5_IE_RESET 0x1 +#define PADS_BANK0_GPIO5_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO5_IE_MSB 6 +#define PADS_BANK0_GPIO5_IE_LSB 6 +#define PADS_BANK0_GPIO5_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO5_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO5_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO5_DRIVE_MSB 5 +#define PADS_BANK0_GPIO5_DRIVE_LSB 4 +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO5_PUE_RESET 0x0 +#define PADS_BANK0_GPIO5_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO5_PUE_MSB 3 +#define PADS_BANK0_GPIO5_PUE_LSB 3 +#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO5_PDE_RESET 0x1 +#define PADS_BANK0_GPIO5_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO5_PDE_MSB 2 +#define PADS_BANK0_GPIO5_PDE_LSB 2 +#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO5_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO5_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO5_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO5_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO5_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO5_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO6 +// Description : Pad control register +#define PADS_BANK0_GPIO6_OFFSET 0x0000001c +#define PADS_BANK0_GPIO6_BITS 0x000000ff +#define PADS_BANK0_GPIO6_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO6_OD_RESET 0x0 +#define PADS_BANK0_GPIO6_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO6_OD_MSB 7 +#define PADS_BANK0_GPIO6_OD_LSB 7 +#define PADS_BANK0_GPIO6_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_IE +// Description : Input enable +#define PADS_BANK0_GPIO6_IE_RESET 0x1 +#define PADS_BANK0_GPIO6_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO6_IE_MSB 6 +#define PADS_BANK0_GPIO6_IE_LSB 6 +#define PADS_BANK0_GPIO6_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO6_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO6_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO6_DRIVE_MSB 5 +#define PADS_BANK0_GPIO6_DRIVE_LSB 4 +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO6_PUE_RESET 0x0 +#define PADS_BANK0_GPIO6_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO6_PUE_MSB 3 +#define PADS_BANK0_GPIO6_PUE_LSB 3 +#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO6_PDE_RESET 0x1 +#define PADS_BANK0_GPIO6_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO6_PDE_MSB 2 +#define PADS_BANK0_GPIO6_PDE_LSB 2 +#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO6_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO6_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO6_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO6_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO6_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO6_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO7 +// Description : Pad control register +#define PADS_BANK0_GPIO7_OFFSET 0x00000020 +#define PADS_BANK0_GPIO7_BITS 0x000000ff +#define PADS_BANK0_GPIO7_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO7_OD_RESET 0x0 +#define PADS_BANK0_GPIO7_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO7_OD_MSB 7 +#define PADS_BANK0_GPIO7_OD_LSB 7 +#define PADS_BANK0_GPIO7_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_IE +// Description : Input enable +#define PADS_BANK0_GPIO7_IE_RESET 0x1 +#define PADS_BANK0_GPIO7_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO7_IE_MSB 6 +#define PADS_BANK0_GPIO7_IE_LSB 6 +#define PADS_BANK0_GPIO7_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO7_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO7_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO7_DRIVE_MSB 5 +#define PADS_BANK0_GPIO7_DRIVE_LSB 4 +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO7_PUE_RESET 0x0 +#define PADS_BANK0_GPIO7_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO7_PUE_MSB 3 +#define PADS_BANK0_GPIO7_PUE_LSB 3 +#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO7_PDE_RESET 0x1 +#define PADS_BANK0_GPIO7_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO7_PDE_MSB 2 +#define PADS_BANK0_GPIO7_PDE_LSB 2 +#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO7_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO7_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO7_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO7_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO7_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO7_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO8 +// Description : Pad control register +#define PADS_BANK0_GPIO8_OFFSET 0x00000024 +#define PADS_BANK0_GPIO8_BITS 0x000000ff +#define PADS_BANK0_GPIO8_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO8_OD_RESET 0x0 +#define PADS_BANK0_GPIO8_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO8_OD_MSB 7 +#define PADS_BANK0_GPIO8_OD_LSB 7 +#define PADS_BANK0_GPIO8_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_IE +// Description : Input enable +#define PADS_BANK0_GPIO8_IE_RESET 0x1 +#define PADS_BANK0_GPIO8_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO8_IE_MSB 6 +#define PADS_BANK0_GPIO8_IE_LSB 6 +#define PADS_BANK0_GPIO8_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO8_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO8_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO8_DRIVE_MSB 5 +#define PADS_BANK0_GPIO8_DRIVE_LSB 4 +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO8_PUE_RESET 0x0 +#define PADS_BANK0_GPIO8_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO8_PUE_MSB 3 +#define PADS_BANK0_GPIO8_PUE_LSB 3 +#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO8_PDE_RESET 0x1 +#define PADS_BANK0_GPIO8_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO8_PDE_MSB 2 +#define PADS_BANK0_GPIO8_PDE_LSB 2 +#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO8_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO8_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO8_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO8_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO8_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO8_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO9 +// Description : Pad control register +#define PADS_BANK0_GPIO9_OFFSET 0x00000028 +#define PADS_BANK0_GPIO9_BITS 0x000000ff +#define PADS_BANK0_GPIO9_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO9_OD_RESET 0x0 +#define PADS_BANK0_GPIO9_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO9_OD_MSB 7 +#define PADS_BANK0_GPIO9_OD_LSB 7 +#define PADS_BANK0_GPIO9_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_IE +// Description : Input enable +#define PADS_BANK0_GPIO9_IE_RESET 0x1 +#define PADS_BANK0_GPIO9_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO9_IE_MSB 6 +#define PADS_BANK0_GPIO9_IE_LSB 6 +#define PADS_BANK0_GPIO9_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO9_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO9_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO9_DRIVE_MSB 5 +#define PADS_BANK0_GPIO9_DRIVE_LSB 4 +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO9_PUE_RESET 0x0 +#define PADS_BANK0_GPIO9_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO9_PUE_MSB 3 +#define PADS_BANK0_GPIO9_PUE_LSB 3 +#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO9_PDE_RESET 0x1 +#define PADS_BANK0_GPIO9_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO9_PDE_MSB 2 +#define PADS_BANK0_GPIO9_PDE_LSB 2 +#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO9_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO9_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO9_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO9_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO9_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO9_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO10 +// Description : Pad control register +#define PADS_BANK0_GPIO10_OFFSET 0x0000002c +#define PADS_BANK0_GPIO10_BITS 0x000000ff +#define PADS_BANK0_GPIO10_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO10_OD_RESET 0x0 +#define PADS_BANK0_GPIO10_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO10_OD_MSB 7 +#define PADS_BANK0_GPIO10_OD_LSB 7 +#define PADS_BANK0_GPIO10_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_IE +// Description : Input enable +#define PADS_BANK0_GPIO10_IE_RESET 0x1 +#define PADS_BANK0_GPIO10_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO10_IE_MSB 6 +#define PADS_BANK0_GPIO10_IE_LSB 6 +#define PADS_BANK0_GPIO10_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO10_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO10_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO10_DRIVE_MSB 5 +#define PADS_BANK0_GPIO10_DRIVE_LSB 4 +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO10_PUE_RESET 0x0 +#define PADS_BANK0_GPIO10_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO10_PUE_MSB 3 +#define PADS_BANK0_GPIO10_PUE_LSB 3 +#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO10_PDE_RESET 0x1 +#define PADS_BANK0_GPIO10_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO10_PDE_MSB 2 +#define PADS_BANK0_GPIO10_PDE_LSB 2 +#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO10_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO10_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO10_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO10_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO10_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO10_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO11 +// Description : Pad control register +#define PADS_BANK0_GPIO11_OFFSET 0x00000030 +#define PADS_BANK0_GPIO11_BITS 0x000000ff +#define PADS_BANK0_GPIO11_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO11_OD_RESET 0x0 +#define PADS_BANK0_GPIO11_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO11_OD_MSB 7 +#define PADS_BANK0_GPIO11_OD_LSB 7 +#define PADS_BANK0_GPIO11_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_IE +// Description : Input enable +#define PADS_BANK0_GPIO11_IE_RESET 0x1 +#define PADS_BANK0_GPIO11_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO11_IE_MSB 6 +#define PADS_BANK0_GPIO11_IE_LSB 6 +#define PADS_BANK0_GPIO11_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO11_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO11_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO11_DRIVE_MSB 5 +#define PADS_BANK0_GPIO11_DRIVE_LSB 4 +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO11_PUE_RESET 0x0 +#define PADS_BANK0_GPIO11_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO11_PUE_MSB 3 +#define PADS_BANK0_GPIO11_PUE_LSB 3 +#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO11_PDE_RESET 0x1 +#define PADS_BANK0_GPIO11_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO11_PDE_MSB 2 +#define PADS_BANK0_GPIO11_PDE_LSB 2 +#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO11_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO11_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO11_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO11_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO11_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO11_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO12 +// Description : Pad control register +#define PADS_BANK0_GPIO12_OFFSET 0x00000034 +#define PADS_BANK0_GPIO12_BITS 0x000000ff +#define PADS_BANK0_GPIO12_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO12_OD_RESET 0x0 +#define PADS_BANK0_GPIO12_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO12_OD_MSB 7 +#define PADS_BANK0_GPIO12_OD_LSB 7 +#define PADS_BANK0_GPIO12_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_IE +// Description : Input enable +#define PADS_BANK0_GPIO12_IE_RESET 0x1 +#define PADS_BANK0_GPIO12_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO12_IE_MSB 6 +#define PADS_BANK0_GPIO12_IE_LSB 6 +#define PADS_BANK0_GPIO12_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO12_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO12_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO12_DRIVE_MSB 5 +#define PADS_BANK0_GPIO12_DRIVE_LSB 4 +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO12_PUE_RESET 0x0 +#define PADS_BANK0_GPIO12_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO12_PUE_MSB 3 +#define PADS_BANK0_GPIO12_PUE_LSB 3 +#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO12_PDE_RESET 0x1 +#define PADS_BANK0_GPIO12_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO12_PDE_MSB 2 +#define PADS_BANK0_GPIO12_PDE_LSB 2 +#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO12_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO12_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO12_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO12_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO12_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO12_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO13 +// Description : Pad control register +#define PADS_BANK0_GPIO13_OFFSET 0x00000038 +#define PADS_BANK0_GPIO13_BITS 0x000000ff +#define PADS_BANK0_GPIO13_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO13_OD_RESET 0x0 +#define PADS_BANK0_GPIO13_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO13_OD_MSB 7 +#define PADS_BANK0_GPIO13_OD_LSB 7 +#define PADS_BANK0_GPIO13_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_IE +// Description : Input enable +#define PADS_BANK0_GPIO13_IE_RESET 0x1 +#define PADS_BANK0_GPIO13_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO13_IE_MSB 6 +#define PADS_BANK0_GPIO13_IE_LSB 6 +#define PADS_BANK0_GPIO13_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO13_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO13_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO13_DRIVE_MSB 5 +#define PADS_BANK0_GPIO13_DRIVE_LSB 4 +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO13_PUE_RESET 0x0 +#define PADS_BANK0_GPIO13_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO13_PUE_MSB 3 +#define PADS_BANK0_GPIO13_PUE_LSB 3 +#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO13_PDE_RESET 0x1 +#define PADS_BANK0_GPIO13_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO13_PDE_MSB 2 +#define PADS_BANK0_GPIO13_PDE_LSB 2 +#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO13_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO13_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO13_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO13_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO13_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO13_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO14 +// Description : Pad control register +#define PADS_BANK0_GPIO14_OFFSET 0x0000003c +#define PADS_BANK0_GPIO14_BITS 0x000000ff +#define PADS_BANK0_GPIO14_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO14_OD_RESET 0x0 +#define PADS_BANK0_GPIO14_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO14_OD_MSB 7 +#define PADS_BANK0_GPIO14_OD_LSB 7 +#define PADS_BANK0_GPIO14_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_IE +// Description : Input enable +#define PADS_BANK0_GPIO14_IE_RESET 0x1 +#define PADS_BANK0_GPIO14_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO14_IE_MSB 6 +#define PADS_BANK0_GPIO14_IE_LSB 6 +#define PADS_BANK0_GPIO14_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO14_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO14_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO14_DRIVE_MSB 5 +#define PADS_BANK0_GPIO14_DRIVE_LSB 4 +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO14_PUE_RESET 0x0 +#define PADS_BANK0_GPIO14_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO14_PUE_MSB 3 +#define PADS_BANK0_GPIO14_PUE_LSB 3 +#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO14_PDE_RESET 0x1 +#define PADS_BANK0_GPIO14_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO14_PDE_MSB 2 +#define PADS_BANK0_GPIO14_PDE_LSB 2 +#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO14_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO14_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO14_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO14_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO14_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO14_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO15 +// Description : Pad control register +#define PADS_BANK0_GPIO15_OFFSET 0x00000040 +#define PADS_BANK0_GPIO15_BITS 0x000000ff +#define PADS_BANK0_GPIO15_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO15_OD_RESET 0x0 +#define PADS_BANK0_GPIO15_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO15_OD_MSB 7 +#define PADS_BANK0_GPIO15_OD_LSB 7 +#define PADS_BANK0_GPIO15_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_IE +// Description : Input enable +#define PADS_BANK0_GPIO15_IE_RESET 0x1 +#define PADS_BANK0_GPIO15_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO15_IE_MSB 6 +#define PADS_BANK0_GPIO15_IE_LSB 6 +#define PADS_BANK0_GPIO15_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO15_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO15_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO15_DRIVE_MSB 5 +#define PADS_BANK0_GPIO15_DRIVE_LSB 4 +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO15_PUE_RESET 0x0 +#define PADS_BANK0_GPIO15_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO15_PUE_MSB 3 +#define PADS_BANK0_GPIO15_PUE_LSB 3 +#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO15_PDE_RESET 0x1 +#define PADS_BANK0_GPIO15_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO15_PDE_MSB 2 +#define PADS_BANK0_GPIO15_PDE_LSB 2 +#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO15_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO15_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO15_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO15_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO15_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO15_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO16 +// Description : Pad control register +#define PADS_BANK0_GPIO16_OFFSET 0x00000044 +#define PADS_BANK0_GPIO16_BITS 0x000000ff +#define PADS_BANK0_GPIO16_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO16_OD_RESET 0x0 +#define PADS_BANK0_GPIO16_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO16_OD_MSB 7 +#define PADS_BANK0_GPIO16_OD_LSB 7 +#define PADS_BANK0_GPIO16_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_IE +// Description : Input enable +#define PADS_BANK0_GPIO16_IE_RESET 0x1 +#define PADS_BANK0_GPIO16_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO16_IE_MSB 6 +#define PADS_BANK0_GPIO16_IE_LSB 6 +#define PADS_BANK0_GPIO16_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO16_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO16_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO16_DRIVE_MSB 5 +#define PADS_BANK0_GPIO16_DRIVE_LSB 4 +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO16_PUE_RESET 0x0 +#define PADS_BANK0_GPIO16_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO16_PUE_MSB 3 +#define PADS_BANK0_GPIO16_PUE_LSB 3 +#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO16_PDE_RESET 0x1 +#define PADS_BANK0_GPIO16_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO16_PDE_MSB 2 +#define PADS_BANK0_GPIO16_PDE_LSB 2 +#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO16_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO16_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO16_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO16_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO16_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO16_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO17 +// Description : Pad control register +#define PADS_BANK0_GPIO17_OFFSET 0x00000048 +#define PADS_BANK0_GPIO17_BITS 0x000000ff +#define PADS_BANK0_GPIO17_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO17_OD_RESET 0x0 +#define PADS_BANK0_GPIO17_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO17_OD_MSB 7 +#define PADS_BANK0_GPIO17_OD_LSB 7 +#define PADS_BANK0_GPIO17_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_IE +// Description : Input enable +#define PADS_BANK0_GPIO17_IE_RESET 0x1 +#define PADS_BANK0_GPIO17_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO17_IE_MSB 6 +#define PADS_BANK0_GPIO17_IE_LSB 6 +#define PADS_BANK0_GPIO17_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO17_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO17_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO17_DRIVE_MSB 5 +#define PADS_BANK0_GPIO17_DRIVE_LSB 4 +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO17_PUE_RESET 0x0 +#define PADS_BANK0_GPIO17_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO17_PUE_MSB 3 +#define PADS_BANK0_GPIO17_PUE_LSB 3 +#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO17_PDE_RESET 0x1 +#define PADS_BANK0_GPIO17_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO17_PDE_MSB 2 +#define PADS_BANK0_GPIO17_PDE_LSB 2 +#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO17_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO17_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO17_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO17_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO17_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO17_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO18 +// Description : Pad control register +#define PADS_BANK0_GPIO18_OFFSET 0x0000004c +#define PADS_BANK0_GPIO18_BITS 0x000000ff +#define PADS_BANK0_GPIO18_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO18_OD_RESET 0x0 +#define PADS_BANK0_GPIO18_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO18_OD_MSB 7 +#define PADS_BANK0_GPIO18_OD_LSB 7 +#define PADS_BANK0_GPIO18_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_IE +// Description : Input enable +#define PADS_BANK0_GPIO18_IE_RESET 0x1 +#define PADS_BANK0_GPIO18_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO18_IE_MSB 6 +#define PADS_BANK0_GPIO18_IE_LSB 6 +#define PADS_BANK0_GPIO18_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO18_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO18_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO18_DRIVE_MSB 5 +#define PADS_BANK0_GPIO18_DRIVE_LSB 4 +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO18_PUE_RESET 0x0 +#define PADS_BANK0_GPIO18_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO18_PUE_MSB 3 +#define PADS_BANK0_GPIO18_PUE_LSB 3 +#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO18_PDE_RESET 0x1 +#define PADS_BANK0_GPIO18_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO18_PDE_MSB 2 +#define PADS_BANK0_GPIO18_PDE_LSB 2 +#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO18_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO18_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO18_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO18_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO18_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO18_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO19 +// Description : Pad control register +#define PADS_BANK0_GPIO19_OFFSET 0x00000050 +#define PADS_BANK0_GPIO19_BITS 0x000000ff +#define PADS_BANK0_GPIO19_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO19_OD_RESET 0x0 +#define PADS_BANK0_GPIO19_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO19_OD_MSB 7 +#define PADS_BANK0_GPIO19_OD_LSB 7 +#define PADS_BANK0_GPIO19_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_IE +// Description : Input enable +#define PADS_BANK0_GPIO19_IE_RESET 0x1 +#define PADS_BANK0_GPIO19_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO19_IE_MSB 6 +#define PADS_BANK0_GPIO19_IE_LSB 6 +#define PADS_BANK0_GPIO19_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO19_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO19_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO19_DRIVE_MSB 5 +#define PADS_BANK0_GPIO19_DRIVE_LSB 4 +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO19_PUE_RESET 0x0 +#define PADS_BANK0_GPIO19_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO19_PUE_MSB 3 +#define PADS_BANK0_GPIO19_PUE_LSB 3 +#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO19_PDE_RESET 0x1 +#define PADS_BANK0_GPIO19_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO19_PDE_MSB 2 +#define PADS_BANK0_GPIO19_PDE_LSB 2 +#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO19_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO19_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO19_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO19_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO19_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO19_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO20 +// Description : Pad control register +#define PADS_BANK0_GPIO20_OFFSET 0x00000054 +#define PADS_BANK0_GPIO20_BITS 0x000000ff +#define PADS_BANK0_GPIO20_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO20_OD_RESET 0x0 +#define PADS_BANK0_GPIO20_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO20_OD_MSB 7 +#define PADS_BANK0_GPIO20_OD_LSB 7 +#define PADS_BANK0_GPIO20_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_IE +// Description : Input enable +#define PADS_BANK0_GPIO20_IE_RESET 0x1 +#define PADS_BANK0_GPIO20_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO20_IE_MSB 6 +#define PADS_BANK0_GPIO20_IE_LSB 6 +#define PADS_BANK0_GPIO20_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO20_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO20_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO20_DRIVE_MSB 5 +#define PADS_BANK0_GPIO20_DRIVE_LSB 4 +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO20_PUE_RESET 0x0 +#define PADS_BANK0_GPIO20_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO20_PUE_MSB 3 +#define PADS_BANK0_GPIO20_PUE_LSB 3 +#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO20_PDE_RESET 0x1 +#define PADS_BANK0_GPIO20_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO20_PDE_MSB 2 +#define PADS_BANK0_GPIO20_PDE_LSB 2 +#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO20_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO20_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO20_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO20_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO20_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO20_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO21 +// Description : Pad control register +#define PADS_BANK0_GPIO21_OFFSET 0x00000058 +#define PADS_BANK0_GPIO21_BITS 0x000000ff +#define PADS_BANK0_GPIO21_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO21_OD_RESET 0x0 +#define PADS_BANK0_GPIO21_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO21_OD_MSB 7 +#define PADS_BANK0_GPIO21_OD_LSB 7 +#define PADS_BANK0_GPIO21_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_IE +// Description : Input enable +#define PADS_BANK0_GPIO21_IE_RESET 0x1 +#define PADS_BANK0_GPIO21_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO21_IE_MSB 6 +#define PADS_BANK0_GPIO21_IE_LSB 6 +#define PADS_BANK0_GPIO21_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO21_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO21_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO21_DRIVE_MSB 5 +#define PADS_BANK0_GPIO21_DRIVE_LSB 4 +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO21_PUE_RESET 0x0 +#define PADS_BANK0_GPIO21_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO21_PUE_MSB 3 +#define PADS_BANK0_GPIO21_PUE_LSB 3 +#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO21_PDE_RESET 0x1 +#define PADS_BANK0_GPIO21_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO21_PDE_MSB 2 +#define PADS_BANK0_GPIO21_PDE_LSB 2 +#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO21_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO21_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO21_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO21_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO21_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO21_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO22 +// Description : Pad control register +#define PADS_BANK0_GPIO22_OFFSET 0x0000005c +#define PADS_BANK0_GPIO22_BITS 0x000000ff +#define PADS_BANK0_GPIO22_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO22_OD_RESET 0x0 +#define PADS_BANK0_GPIO22_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO22_OD_MSB 7 +#define PADS_BANK0_GPIO22_OD_LSB 7 +#define PADS_BANK0_GPIO22_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_IE +// Description : Input enable +#define PADS_BANK0_GPIO22_IE_RESET 0x1 +#define PADS_BANK0_GPIO22_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO22_IE_MSB 6 +#define PADS_BANK0_GPIO22_IE_LSB 6 +#define PADS_BANK0_GPIO22_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO22_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO22_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO22_DRIVE_MSB 5 +#define PADS_BANK0_GPIO22_DRIVE_LSB 4 +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO22_PUE_RESET 0x0 +#define PADS_BANK0_GPIO22_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO22_PUE_MSB 3 +#define PADS_BANK0_GPIO22_PUE_LSB 3 +#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO22_PDE_RESET 0x1 +#define PADS_BANK0_GPIO22_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO22_PDE_MSB 2 +#define PADS_BANK0_GPIO22_PDE_LSB 2 +#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO22_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO22_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO22_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO22_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO22_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO22_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO23 +// Description : Pad control register +#define PADS_BANK0_GPIO23_OFFSET 0x00000060 +#define PADS_BANK0_GPIO23_BITS 0x000000ff +#define PADS_BANK0_GPIO23_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO23_OD_RESET 0x0 +#define PADS_BANK0_GPIO23_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO23_OD_MSB 7 +#define PADS_BANK0_GPIO23_OD_LSB 7 +#define PADS_BANK0_GPIO23_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_IE +// Description : Input enable +#define PADS_BANK0_GPIO23_IE_RESET 0x1 +#define PADS_BANK0_GPIO23_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO23_IE_MSB 6 +#define PADS_BANK0_GPIO23_IE_LSB 6 +#define PADS_BANK0_GPIO23_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO23_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO23_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO23_DRIVE_MSB 5 +#define PADS_BANK0_GPIO23_DRIVE_LSB 4 +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO23_PUE_RESET 0x0 +#define PADS_BANK0_GPIO23_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO23_PUE_MSB 3 +#define PADS_BANK0_GPIO23_PUE_LSB 3 +#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO23_PDE_RESET 0x1 +#define PADS_BANK0_GPIO23_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO23_PDE_MSB 2 +#define PADS_BANK0_GPIO23_PDE_LSB 2 +#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO23_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO23_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO23_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO23_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO23_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO23_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO24 +// Description : Pad control register +#define PADS_BANK0_GPIO24_OFFSET 0x00000064 +#define PADS_BANK0_GPIO24_BITS 0x000000ff +#define PADS_BANK0_GPIO24_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO24_OD_RESET 0x0 +#define PADS_BANK0_GPIO24_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO24_OD_MSB 7 +#define PADS_BANK0_GPIO24_OD_LSB 7 +#define PADS_BANK0_GPIO24_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_IE +// Description : Input enable +#define PADS_BANK0_GPIO24_IE_RESET 0x1 +#define PADS_BANK0_GPIO24_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO24_IE_MSB 6 +#define PADS_BANK0_GPIO24_IE_LSB 6 +#define PADS_BANK0_GPIO24_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO24_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO24_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO24_DRIVE_MSB 5 +#define PADS_BANK0_GPIO24_DRIVE_LSB 4 +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO24_PUE_RESET 0x0 +#define PADS_BANK0_GPIO24_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO24_PUE_MSB 3 +#define PADS_BANK0_GPIO24_PUE_LSB 3 +#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO24_PDE_RESET 0x1 +#define PADS_BANK0_GPIO24_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO24_PDE_MSB 2 +#define PADS_BANK0_GPIO24_PDE_LSB 2 +#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO24_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO24_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO24_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO24_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO24_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO24_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO25 +// Description : Pad control register +#define PADS_BANK0_GPIO25_OFFSET 0x00000068 +#define PADS_BANK0_GPIO25_BITS 0x000000ff +#define PADS_BANK0_GPIO25_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO25_OD_RESET 0x0 +#define PADS_BANK0_GPIO25_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO25_OD_MSB 7 +#define PADS_BANK0_GPIO25_OD_LSB 7 +#define PADS_BANK0_GPIO25_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_IE +// Description : Input enable +#define PADS_BANK0_GPIO25_IE_RESET 0x1 +#define PADS_BANK0_GPIO25_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO25_IE_MSB 6 +#define PADS_BANK0_GPIO25_IE_LSB 6 +#define PADS_BANK0_GPIO25_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO25_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO25_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO25_DRIVE_MSB 5 +#define PADS_BANK0_GPIO25_DRIVE_LSB 4 +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO25_PUE_RESET 0x0 +#define PADS_BANK0_GPIO25_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO25_PUE_MSB 3 +#define PADS_BANK0_GPIO25_PUE_LSB 3 +#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO25_PDE_RESET 0x1 +#define PADS_BANK0_GPIO25_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO25_PDE_MSB 2 +#define PADS_BANK0_GPIO25_PDE_LSB 2 +#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO25_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO25_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO25_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO25_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO25_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO25_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO26 +// Description : Pad control register +#define PADS_BANK0_GPIO26_OFFSET 0x0000006c +#define PADS_BANK0_GPIO26_BITS 0x000000ff +#define PADS_BANK0_GPIO26_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO26_OD_RESET 0x0 +#define PADS_BANK0_GPIO26_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO26_OD_MSB 7 +#define PADS_BANK0_GPIO26_OD_LSB 7 +#define PADS_BANK0_GPIO26_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_IE +// Description : Input enable +#define PADS_BANK0_GPIO26_IE_RESET 0x1 +#define PADS_BANK0_GPIO26_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO26_IE_MSB 6 +#define PADS_BANK0_GPIO26_IE_LSB 6 +#define PADS_BANK0_GPIO26_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO26_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO26_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO26_DRIVE_MSB 5 +#define PADS_BANK0_GPIO26_DRIVE_LSB 4 +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO26_PUE_RESET 0x0 +#define PADS_BANK0_GPIO26_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO26_PUE_MSB 3 +#define PADS_BANK0_GPIO26_PUE_LSB 3 +#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO26_PDE_RESET 0x1 +#define PADS_BANK0_GPIO26_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO26_PDE_MSB 2 +#define PADS_BANK0_GPIO26_PDE_LSB 2 +#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO26_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO26_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO26_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO26_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO26_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO26_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO27 +// Description : Pad control register +#define PADS_BANK0_GPIO27_OFFSET 0x00000070 +#define PADS_BANK0_GPIO27_BITS 0x000000ff +#define PADS_BANK0_GPIO27_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO27_OD_RESET 0x0 +#define PADS_BANK0_GPIO27_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO27_OD_MSB 7 +#define PADS_BANK0_GPIO27_OD_LSB 7 +#define PADS_BANK0_GPIO27_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_IE +// Description : Input enable +#define PADS_BANK0_GPIO27_IE_RESET 0x1 +#define PADS_BANK0_GPIO27_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO27_IE_MSB 6 +#define PADS_BANK0_GPIO27_IE_LSB 6 +#define PADS_BANK0_GPIO27_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO27_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO27_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO27_DRIVE_MSB 5 +#define PADS_BANK0_GPIO27_DRIVE_LSB 4 +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO27_PUE_RESET 0x0 +#define PADS_BANK0_GPIO27_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO27_PUE_MSB 3 +#define PADS_BANK0_GPIO27_PUE_LSB 3 +#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO27_PDE_RESET 0x1 +#define PADS_BANK0_GPIO27_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO27_PDE_MSB 2 +#define PADS_BANK0_GPIO27_PDE_LSB 2 +#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO27_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO27_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO27_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO27_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO27_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO27_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO28 +// Description : Pad control register +#define PADS_BANK0_GPIO28_OFFSET 0x00000074 +#define PADS_BANK0_GPIO28_BITS 0x000000ff +#define PADS_BANK0_GPIO28_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO28_OD_RESET 0x0 +#define PADS_BANK0_GPIO28_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO28_OD_MSB 7 +#define PADS_BANK0_GPIO28_OD_LSB 7 +#define PADS_BANK0_GPIO28_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_IE +// Description : Input enable +#define PADS_BANK0_GPIO28_IE_RESET 0x1 +#define PADS_BANK0_GPIO28_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO28_IE_MSB 6 +#define PADS_BANK0_GPIO28_IE_LSB 6 +#define PADS_BANK0_GPIO28_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO28_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO28_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO28_DRIVE_MSB 5 +#define PADS_BANK0_GPIO28_DRIVE_LSB 4 +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO28_PUE_RESET 0x0 +#define PADS_BANK0_GPIO28_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO28_PUE_MSB 3 +#define PADS_BANK0_GPIO28_PUE_LSB 3 +#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO28_PDE_RESET 0x1 +#define PADS_BANK0_GPIO28_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO28_PDE_MSB 2 +#define PADS_BANK0_GPIO28_PDE_LSB 2 +#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO28_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO28_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO28_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO28_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO28_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO28_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO29 +// Description : Pad control register +#define PADS_BANK0_GPIO29_OFFSET 0x00000078 +#define PADS_BANK0_GPIO29_BITS 0x000000ff +#define PADS_BANK0_GPIO29_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO29_OD_RESET 0x0 +#define PADS_BANK0_GPIO29_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO29_OD_MSB 7 +#define PADS_BANK0_GPIO29_OD_LSB 7 +#define PADS_BANK0_GPIO29_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_IE +// Description : Input enable +#define PADS_BANK0_GPIO29_IE_RESET 0x1 +#define PADS_BANK0_GPIO29_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO29_IE_MSB 6 +#define PADS_BANK0_GPIO29_IE_LSB 6 +#define PADS_BANK0_GPIO29_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO29_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO29_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO29_DRIVE_MSB 5 +#define PADS_BANK0_GPIO29_DRIVE_LSB 4 +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO29_PUE_RESET 0x0 +#define PADS_BANK0_GPIO29_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO29_PUE_MSB 3 +#define PADS_BANK0_GPIO29_PUE_LSB 3 +#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO29_PDE_RESET 0x1 +#define PADS_BANK0_GPIO29_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO29_PDE_MSB 2 +#define PADS_BANK0_GPIO29_PDE_LSB 2 +#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO29_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO29_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO29_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO29_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO29_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO29_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWCLK +// Description : Pad control register +#define PADS_BANK0_SWCLK_OFFSET 0x0000007c +#define PADS_BANK0_SWCLK_BITS 0x000000ff +#define PADS_BANK0_SWCLK_RESET 0x000000da +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWCLK_OD_RESET 0x1 +#define PADS_BANK0_SWCLK_OD_BITS 0x00000080 +#define PADS_BANK0_SWCLK_OD_MSB 7 +#define PADS_BANK0_SWCLK_OD_LSB 7 +#define PADS_BANK0_SWCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_IE +// Description : Input enable +#define PADS_BANK0_SWCLK_IE_RESET 0x1 +#define PADS_BANK0_SWCLK_IE_BITS 0x00000040 +#define PADS_BANK0_SWCLK_IE_MSB 6 +#define PADS_BANK0_SWCLK_IE_LSB 6 +#define PADS_BANK0_SWCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWCLK_DRIVE_RESET 0x1 +#define PADS_BANK0_SWCLK_DRIVE_BITS 0x00000030 +#define PADS_BANK0_SWCLK_DRIVE_MSB 5 +#define PADS_BANK0_SWCLK_DRIVE_LSB 4 +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PUE +// Description : Pull up enable +#define PADS_BANK0_SWCLK_PUE_RESET 0x1 +#define PADS_BANK0_SWCLK_PUE_BITS 0x00000008 +#define PADS_BANK0_SWCLK_PUE_MSB 3 +#define PADS_BANK0_SWCLK_PUE_LSB 3 +#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PDE +// Description : Pull down enable +#define PADS_BANK0_SWCLK_PDE_RESET 0x0 +#define PADS_BANK0_SWCLK_PDE_BITS 0x00000004 +#define PADS_BANK0_SWCLK_PDE_MSB 2 +#define PADS_BANK0_SWCLK_PDE_LSB 2 +#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWCLK_SCHMITT_RESET 0x1 +#define PADS_BANK0_SWCLK_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_SWCLK_SCHMITT_MSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_LSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWCLK_SLEWFAST_RESET 0x0 +#define PADS_BANK0_SWCLK_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_SWCLK_SLEWFAST_MSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_LSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWD +// Description : Pad control register +#define PADS_BANK0_SWD_OFFSET 0x00000080 +#define PADS_BANK0_SWD_BITS 0x000000ff +#define PADS_BANK0_SWD_RESET 0x0000005a +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWD_OD_RESET 0x0 +#define PADS_BANK0_SWD_OD_BITS 0x00000080 +#define PADS_BANK0_SWD_OD_MSB 7 +#define PADS_BANK0_SWD_OD_LSB 7 +#define PADS_BANK0_SWD_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_IE +// Description : Input enable +#define PADS_BANK0_SWD_IE_RESET 0x1 +#define PADS_BANK0_SWD_IE_BITS 0x00000040 +#define PADS_BANK0_SWD_IE_MSB 6 +#define PADS_BANK0_SWD_IE_LSB 6 +#define PADS_BANK0_SWD_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWD_DRIVE_RESET 0x1 +#define PADS_BANK0_SWD_DRIVE_BITS 0x00000030 +#define PADS_BANK0_SWD_DRIVE_MSB 5 +#define PADS_BANK0_SWD_DRIVE_LSB 4 +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PUE +// Description : Pull up enable +#define PADS_BANK0_SWD_PUE_RESET 0x1 +#define PADS_BANK0_SWD_PUE_BITS 0x00000008 +#define PADS_BANK0_SWD_PUE_MSB 3 +#define PADS_BANK0_SWD_PUE_LSB 3 +#define PADS_BANK0_SWD_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PDE +// Description : Pull down enable +#define PADS_BANK0_SWD_PDE_RESET 0x0 +#define PADS_BANK0_SWD_PDE_BITS 0x00000004 +#define PADS_BANK0_SWD_PDE_MSB 2 +#define PADS_BANK0_SWD_PDE_LSB 2 +#define PADS_BANK0_SWD_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWD_SCHMITT_RESET 0x1 +#define PADS_BANK0_SWD_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_SWD_SCHMITT_MSB 1 +#define PADS_BANK0_SWD_SCHMITT_LSB 1 +#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWD_SLEWFAST_RESET 0x0 +#define PADS_BANK0_SWD_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_SWD_SLEWFAST_MSB 0 +#define PADS_BANK0_SWD_SLEWFAST_LSB 0 +#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PADS_BANK0_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h new file mode 100644 index 00000000000..7aba5e856a3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h @@ -0,0 +1,454 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_QSPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED +#define HARDWARE_REGS_PADS_QSPI_DEFINED +// ============================================================================= +// Register : PADS_QSPI_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000 +#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001 +#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000 +#define PADS_QSPI_VOLTAGE_SELECT_MSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_LSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0 +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1 +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SCLK +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD0 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD1 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c +#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD2 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010 +#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD3 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014 +#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SS +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018 +#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PADS_QSPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h new file mode 100644 index 00000000000..503aa094098 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h @@ -0,0 +1,2591 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PIO +// Version : 1 +// Bus type : ahbl +// Description : Programmable IO block +// ============================================================================= +#ifndef HARDWARE_REGS_PIO_DEFINED +#define HARDWARE_REGS_PIO_DEFINED +// ============================================================================= +// Register : PIO_CTRL +// Description : PIO control register +#define PIO_CTRL_OFFSET 0x00000000 +#define PIO_CTRL_BITS 0x00000fff +#define PIO_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_CLKDIV_RESTART +// Description : Force clock dividers to restart their count and clear +// fractional +// accumulators. Restart multiple dividers to synchronise them. +#define PIO_CTRL_CLKDIV_RESTART_RESET 0x0 +#define PIO_CTRL_CLKDIV_RESTART_BITS 0x00000f00 +#define PIO_CTRL_CLKDIV_RESTART_MSB 11 +#define PIO_CTRL_CLKDIV_RESTART_LSB 8 +#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_RESTART +// Description : Clear internal SM state which is otherwise difficult to access +// (e.g. shift counters). Self-clearing. +#define PIO_CTRL_SM_RESTART_RESET 0x0 +#define PIO_CTRL_SM_RESTART_BITS 0x000000f0 +#define PIO_CTRL_SM_RESTART_MSB 7 +#define PIO_CTRL_SM_RESTART_LSB 4 +#define PIO_CTRL_SM_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_ENABLE +// Description : Enable state machine +#define PIO_CTRL_SM_ENABLE_RESET 0x0 +#define PIO_CTRL_SM_ENABLE_BITS 0x0000000f +#define PIO_CTRL_SM_ENABLE_MSB 3 +#define PIO_CTRL_SM_ENABLE_LSB 0 +#define PIO_CTRL_SM_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : PIO_FSTAT +// Description : FIFO status register +#define PIO_FSTAT_OFFSET 0x00000004 +#define PIO_FSTAT_BITS 0x0f0f0f0f +#define PIO_FSTAT_RESET 0x0f000f00 +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXEMPTY +// Description : State machine TX FIFO is empty +#define PIO_FSTAT_TXEMPTY_RESET 0xf +#define PIO_FSTAT_TXEMPTY_BITS 0x0f000000 +#define PIO_FSTAT_TXEMPTY_MSB 27 +#define PIO_FSTAT_TXEMPTY_LSB 24 +#define PIO_FSTAT_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXFULL +// Description : State machine TX FIFO is full +#define PIO_FSTAT_TXFULL_RESET 0x0 +#define PIO_FSTAT_TXFULL_BITS 0x000f0000 +#define PIO_FSTAT_TXFULL_MSB 19 +#define PIO_FSTAT_TXFULL_LSB 16 +#define PIO_FSTAT_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXEMPTY +// Description : State machine RX FIFO is empty +#define PIO_FSTAT_RXEMPTY_RESET 0xf +#define PIO_FSTAT_RXEMPTY_BITS 0x00000f00 +#define PIO_FSTAT_RXEMPTY_MSB 11 +#define PIO_FSTAT_RXEMPTY_LSB 8 +#define PIO_FSTAT_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXFULL +// Description : State machine RX FIFO is full +#define PIO_FSTAT_RXFULL_RESET 0x0 +#define PIO_FSTAT_RXFULL_BITS 0x0000000f +#define PIO_FSTAT_RXFULL_MSB 3 +#define PIO_FSTAT_RXFULL_LSB 0 +#define PIO_FSTAT_RXFULL_ACCESS "RO" +// ============================================================================= +// Register : PIO_FDEBUG +// Description : FIFO debug register +#define PIO_FDEBUG_OFFSET 0x00000008 +#define PIO_FDEBUG_BITS 0x0f0f0f0f +#define PIO_FDEBUG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXSTALL +// Description : State machine has stalled on empty TX FIFO. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET 0x0 +#define PIO_FDEBUG_TXSTALL_BITS 0x0f000000 +#define PIO_FDEBUG_TXSTALL_MSB 27 +#define PIO_FDEBUG_TXSTALL_LSB 24 +#define PIO_FDEBUG_TXSTALL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXOVER +// Description : TX FIFO overflow has occurred. Write 1 to clear. +#define PIO_FDEBUG_TXOVER_RESET 0x0 +#define PIO_FDEBUG_TXOVER_BITS 0x000f0000 +#define PIO_FDEBUG_TXOVER_MSB 19 +#define PIO_FDEBUG_TXOVER_LSB 16 +#define PIO_FDEBUG_TXOVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXUNDER +// Description : RX FIFO underflow has occurred. Write 1 to clear. +#define PIO_FDEBUG_RXUNDER_RESET 0x0 +#define PIO_FDEBUG_RXUNDER_BITS 0x00000f00 +#define PIO_FDEBUG_RXUNDER_MSB 11 +#define PIO_FDEBUG_RXUNDER_LSB 8 +#define PIO_FDEBUG_RXUNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXSTALL +// Description : State machine has stalled on full RX FIFO. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET 0x0 +#define PIO_FDEBUG_RXSTALL_BITS 0x0000000f +#define PIO_FDEBUG_RXSTALL_MSB 3 +#define PIO_FDEBUG_RXSTALL_LSB 0 +#define PIO_FDEBUG_RXSTALL_ACCESS "WC" +// ============================================================================= +// Register : PIO_FLEVEL +// Description : FIFO levels +#define PIO_FLEVEL_OFFSET 0x0000000c +#define PIO_FLEVEL_BITS 0xffffffff +#define PIO_FLEVEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX3 +// Description : None +#define PIO_FLEVEL_RX3_RESET 0x0 +#define PIO_FLEVEL_RX3_BITS 0xf0000000 +#define PIO_FLEVEL_RX3_MSB 31 +#define PIO_FLEVEL_RX3_LSB 28 +#define PIO_FLEVEL_RX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX3 +// Description : None +#define PIO_FLEVEL_TX3_RESET 0x0 +#define PIO_FLEVEL_TX3_BITS 0x0f000000 +#define PIO_FLEVEL_TX3_MSB 27 +#define PIO_FLEVEL_TX3_LSB 24 +#define PIO_FLEVEL_TX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX2 +// Description : None +#define PIO_FLEVEL_RX2_RESET 0x0 +#define PIO_FLEVEL_RX2_BITS 0x00f00000 +#define PIO_FLEVEL_RX2_MSB 23 +#define PIO_FLEVEL_RX2_LSB 20 +#define PIO_FLEVEL_RX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX2 +// Description : None +#define PIO_FLEVEL_TX2_RESET 0x0 +#define PIO_FLEVEL_TX2_BITS 0x000f0000 +#define PIO_FLEVEL_TX2_MSB 19 +#define PIO_FLEVEL_TX2_LSB 16 +#define PIO_FLEVEL_TX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX1 +// Description : None +#define PIO_FLEVEL_RX1_RESET 0x0 +#define PIO_FLEVEL_RX1_BITS 0x0000f000 +#define PIO_FLEVEL_RX1_MSB 15 +#define PIO_FLEVEL_RX1_LSB 12 +#define PIO_FLEVEL_RX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX1 +// Description : None +#define PIO_FLEVEL_TX1_RESET 0x0 +#define PIO_FLEVEL_TX1_BITS 0x00000f00 +#define PIO_FLEVEL_TX1_MSB 11 +#define PIO_FLEVEL_TX1_LSB 8 +#define PIO_FLEVEL_TX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX0 +// Description : None +#define PIO_FLEVEL_RX0_RESET 0x0 +#define PIO_FLEVEL_RX0_BITS 0x000000f0 +#define PIO_FLEVEL_RX0_MSB 7 +#define PIO_FLEVEL_RX0_LSB 4 +#define PIO_FLEVEL_RX0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX0 +// Description : None +#define PIO_FLEVEL_TX0_RESET 0x0 +#define PIO_FLEVEL_TX0_BITS 0x0000000f +#define PIO_FLEVEL_TX0_MSB 3 +#define PIO_FLEVEL_TX0_LSB 0 +#define PIO_FLEVEL_TX0_ACCESS "RO" +// ============================================================================= +// Register : PIO_TXF0 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF0_OFFSET 0x00000010 +#define PIO_TXF0_BITS 0xffffffff +#define PIO_TXF0_RESET 0x00000000 +#define PIO_TXF0_MSB 31 +#define PIO_TXF0_LSB 0 +#define PIO_TXF0_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF1 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF1_OFFSET 0x00000014 +#define PIO_TXF1_BITS 0xffffffff +#define PIO_TXF1_RESET 0x00000000 +#define PIO_TXF1_MSB 31 +#define PIO_TXF1_LSB 0 +#define PIO_TXF1_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF2 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF2_OFFSET 0x00000018 +#define PIO_TXF2_BITS 0xffffffff +#define PIO_TXF2_RESET 0x00000000 +#define PIO_TXF2_MSB 31 +#define PIO_TXF2_LSB 0 +#define PIO_TXF2_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF3 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF3_OFFSET 0x0000001c +#define PIO_TXF3_BITS 0xffffffff +#define PIO_TXF3_RESET 0x00000000 +#define PIO_TXF3_MSB 31 +#define PIO_TXF3_LSB 0 +#define PIO_TXF3_ACCESS "WF" +// ============================================================================= +// Register : PIO_RXF0 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF0_OFFSET 0x00000020 +#define PIO_RXF0_BITS 0xffffffff +#define PIO_RXF0_RESET "-" +#define PIO_RXF0_MSB 31 +#define PIO_RXF0_LSB 0 +#define PIO_RXF0_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF1 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF1_OFFSET 0x00000024 +#define PIO_RXF1_BITS 0xffffffff +#define PIO_RXF1_RESET "-" +#define PIO_RXF1_MSB 31 +#define PIO_RXF1_LSB 0 +#define PIO_RXF1_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF2 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF2_OFFSET 0x00000028 +#define PIO_RXF2_BITS 0xffffffff +#define PIO_RXF2_RESET "-" +#define PIO_RXF2_MSB 31 +#define PIO_RXF2_LSB 0 +#define PIO_RXF2_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF3 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF3_OFFSET 0x0000002c +#define PIO_RXF3_BITS 0xffffffff +#define PIO_RXF3_RESET "-" +#define PIO_RXF3_MSB 31 +#define PIO_RXF3_LSB 0 +#define PIO_RXF3_ACCESS "RF" +// ============================================================================= +// Register : PIO_IRQ +// Description : Interrupt request register. Write 1 to clear +#define PIO_IRQ_OFFSET 0x00000030 +#define PIO_IRQ_BITS 0x000000ff +#define PIO_IRQ_RESET 0x00000000 +#define PIO_IRQ_MSB 7 +#define PIO_IRQ_LSB 0 +#define PIO_IRQ_ACCESS "WC" +// ============================================================================= +// Register : PIO_IRQ_FORCE +// Description : Writing a 1 to each of these bits will forcibly assert the +// corresponding IRQ. +// Note this is different to the INTF register: writing here +// affects PIO internal +// state. INTF just asserts the processor-facing IRQ signal for +// testing ISRs, +// and is not visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET 0x00000034 +#define PIO_IRQ_FORCE_BITS 0x000000ff +#define PIO_IRQ_FORCE_RESET 0x00000000 +#define PIO_IRQ_FORCE_MSB 7 +#define PIO_IRQ_FORCE_LSB 0 +#define PIO_IRQ_FORCE_ACCESS "WF" +// ============================================================================= +// Register : PIO_INPUT_SYNC_BYPASS +// Description : There is a 2-flipflop synchronizer on each GPIO input, which +// protects +// PIO logic from metastabilities. This increases input delay, and +// for fast +// synchronous IO (e.g. SPI) these synchronizers may need to be +// bypassed. +// Each bit in this register corresponds to one GPIO. +// 0 -> input is synchronized (default) +// 1 -> synchronizer is bypassed +// If in doubt, leave this register as all zeroes. +#define PIO_INPUT_SYNC_BYPASS_OFFSET 0x00000038 +#define PIO_INPUT_SYNC_BYPASS_BITS 0xffffffff +#define PIO_INPUT_SYNC_BYPASS_RESET 0x00000000 +#define PIO_INPUT_SYNC_BYPASS_MSB 31 +#define PIO_INPUT_SYNC_BYPASS_LSB 0 +#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : PIO_DBG_PADOUT +// Description : Read to sample the pad output values PIO is currently driving +// to the GPIOs. +#define PIO_DBG_PADOUT_OFFSET 0x0000003c +#define PIO_DBG_PADOUT_BITS 0xffffffff +#define PIO_DBG_PADOUT_RESET 0x00000000 +#define PIO_DBG_PADOUT_MSB 31 +#define PIO_DBG_PADOUT_LSB 0 +#define PIO_DBG_PADOUT_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_PADOE +// Description : Read to sample the pad output enables (direction) PIO is +// currently driving to the GPIOs. +#define PIO_DBG_PADOE_OFFSET 0x00000040 +#define PIO_DBG_PADOE_BITS 0xffffffff +#define PIO_DBG_PADOE_RESET 0x00000000 +#define PIO_DBG_PADOE_MSB 31 +#define PIO_DBG_PADOE_LSB 0 +#define PIO_DBG_PADOE_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_CFGINFO +// Description : The PIO hardware has some free parameters that may vary between +// chip products. +// These should be provided in the chip datasheet, but are also +// exposed here. +#define PIO_DBG_CFGINFO_OFFSET 0x00000044 +#define PIO_DBG_CFGINFO_BITS 0x003f0f3f +#define PIO_DBG_CFGINFO_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_IMEM_SIZE +// Description : The size of the instruction memory, measured in units of one +// instruction +#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS 0x003f0000 +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB 21 +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB 16 +#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_SM_COUNT +// Description : The number of state machines this PIO instance is equipped +// with. +#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" +#define PIO_DBG_CFGINFO_SM_COUNT_BITS 0x00000f00 +#define PIO_DBG_CFGINFO_SM_COUNT_MSB 11 +#define PIO_DBG_CFGINFO_SM_COUNT_LSB 8 +#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_FIFO_DEPTH +// Description : The depth of the state machine TX/RX FIFOs, measured in words. +// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double +// this depth. +#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS 0x0000003f +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB 5 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB 0 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" +// ============================================================================= +// Register : PIO_INSTR_MEM0 +// Description : Write-only access to instruction memory location 0 +#define PIO_INSTR_MEM0_OFFSET 0x00000048 +#define PIO_INSTR_MEM0_BITS 0x0000ffff +#define PIO_INSTR_MEM0_RESET 0x00000000 +#define PIO_INSTR_MEM0_MSB 15 +#define PIO_INSTR_MEM0_LSB 0 +#define PIO_INSTR_MEM0_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM1 +// Description : Write-only access to instruction memory location 1 +#define PIO_INSTR_MEM1_OFFSET 0x0000004c +#define PIO_INSTR_MEM1_BITS 0x0000ffff +#define PIO_INSTR_MEM1_RESET 0x00000000 +#define PIO_INSTR_MEM1_MSB 15 +#define PIO_INSTR_MEM1_LSB 0 +#define PIO_INSTR_MEM1_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM2 +// Description : Write-only access to instruction memory location 2 +#define PIO_INSTR_MEM2_OFFSET 0x00000050 +#define PIO_INSTR_MEM2_BITS 0x0000ffff +#define PIO_INSTR_MEM2_RESET 0x00000000 +#define PIO_INSTR_MEM2_MSB 15 +#define PIO_INSTR_MEM2_LSB 0 +#define PIO_INSTR_MEM2_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM3 +// Description : Write-only access to instruction memory location 3 +#define PIO_INSTR_MEM3_OFFSET 0x00000054 +#define PIO_INSTR_MEM3_BITS 0x0000ffff +#define PIO_INSTR_MEM3_RESET 0x00000000 +#define PIO_INSTR_MEM3_MSB 15 +#define PIO_INSTR_MEM3_LSB 0 +#define PIO_INSTR_MEM3_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM4 +// Description : Write-only access to instruction memory location 4 +#define PIO_INSTR_MEM4_OFFSET 0x00000058 +#define PIO_INSTR_MEM4_BITS 0x0000ffff +#define PIO_INSTR_MEM4_RESET 0x00000000 +#define PIO_INSTR_MEM4_MSB 15 +#define PIO_INSTR_MEM4_LSB 0 +#define PIO_INSTR_MEM4_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM5 +// Description : Write-only access to instruction memory location 5 +#define PIO_INSTR_MEM5_OFFSET 0x0000005c +#define PIO_INSTR_MEM5_BITS 0x0000ffff +#define PIO_INSTR_MEM5_RESET 0x00000000 +#define PIO_INSTR_MEM5_MSB 15 +#define PIO_INSTR_MEM5_LSB 0 +#define PIO_INSTR_MEM5_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM6 +// Description : Write-only access to instruction memory location 6 +#define PIO_INSTR_MEM6_OFFSET 0x00000060 +#define PIO_INSTR_MEM6_BITS 0x0000ffff +#define PIO_INSTR_MEM6_RESET 0x00000000 +#define PIO_INSTR_MEM6_MSB 15 +#define PIO_INSTR_MEM6_LSB 0 +#define PIO_INSTR_MEM6_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM7 +// Description : Write-only access to instruction memory location 7 +#define PIO_INSTR_MEM7_OFFSET 0x00000064 +#define PIO_INSTR_MEM7_BITS 0x0000ffff +#define PIO_INSTR_MEM7_RESET 0x00000000 +#define PIO_INSTR_MEM7_MSB 15 +#define PIO_INSTR_MEM7_LSB 0 +#define PIO_INSTR_MEM7_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM8 +// Description : Write-only access to instruction memory location 8 +#define PIO_INSTR_MEM8_OFFSET 0x00000068 +#define PIO_INSTR_MEM8_BITS 0x0000ffff +#define PIO_INSTR_MEM8_RESET 0x00000000 +#define PIO_INSTR_MEM8_MSB 15 +#define PIO_INSTR_MEM8_LSB 0 +#define PIO_INSTR_MEM8_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM9 +// Description : Write-only access to instruction memory location 9 +#define PIO_INSTR_MEM9_OFFSET 0x0000006c +#define PIO_INSTR_MEM9_BITS 0x0000ffff +#define PIO_INSTR_MEM9_RESET 0x00000000 +#define PIO_INSTR_MEM9_MSB 15 +#define PIO_INSTR_MEM9_LSB 0 +#define PIO_INSTR_MEM9_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM10 +// Description : Write-only access to instruction memory location 10 +#define PIO_INSTR_MEM10_OFFSET 0x00000070 +#define PIO_INSTR_MEM10_BITS 0x0000ffff +#define PIO_INSTR_MEM10_RESET 0x00000000 +#define PIO_INSTR_MEM10_MSB 15 +#define PIO_INSTR_MEM10_LSB 0 +#define PIO_INSTR_MEM10_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM11 +// Description : Write-only access to instruction memory location 11 +#define PIO_INSTR_MEM11_OFFSET 0x00000074 +#define PIO_INSTR_MEM11_BITS 0x0000ffff +#define PIO_INSTR_MEM11_RESET 0x00000000 +#define PIO_INSTR_MEM11_MSB 15 +#define PIO_INSTR_MEM11_LSB 0 +#define PIO_INSTR_MEM11_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM12 +// Description : Write-only access to instruction memory location 12 +#define PIO_INSTR_MEM12_OFFSET 0x00000078 +#define PIO_INSTR_MEM12_BITS 0x0000ffff +#define PIO_INSTR_MEM12_RESET 0x00000000 +#define PIO_INSTR_MEM12_MSB 15 +#define PIO_INSTR_MEM12_LSB 0 +#define PIO_INSTR_MEM12_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM13 +// Description : Write-only access to instruction memory location 13 +#define PIO_INSTR_MEM13_OFFSET 0x0000007c +#define PIO_INSTR_MEM13_BITS 0x0000ffff +#define PIO_INSTR_MEM13_RESET 0x00000000 +#define PIO_INSTR_MEM13_MSB 15 +#define PIO_INSTR_MEM13_LSB 0 +#define PIO_INSTR_MEM13_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM14 +// Description : Write-only access to instruction memory location 14 +#define PIO_INSTR_MEM14_OFFSET 0x00000080 +#define PIO_INSTR_MEM14_BITS 0x0000ffff +#define PIO_INSTR_MEM14_RESET 0x00000000 +#define PIO_INSTR_MEM14_MSB 15 +#define PIO_INSTR_MEM14_LSB 0 +#define PIO_INSTR_MEM14_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM15 +// Description : Write-only access to instruction memory location 15 +#define PIO_INSTR_MEM15_OFFSET 0x00000084 +#define PIO_INSTR_MEM15_BITS 0x0000ffff +#define PIO_INSTR_MEM15_RESET 0x00000000 +#define PIO_INSTR_MEM15_MSB 15 +#define PIO_INSTR_MEM15_LSB 0 +#define PIO_INSTR_MEM15_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM16 +// Description : Write-only access to instruction memory location 16 +#define PIO_INSTR_MEM16_OFFSET 0x00000088 +#define PIO_INSTR_MEM16_BITS 0x0000ffff +#define PIO_INSTR_MEM16_RESET 0x00000000 +#define PIO_INSTR_MEM16_MSB 15 +#define PIO_INSTR_MEM16_LSB 0 +#define PIO_INSTR_MEM16_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM17 +// Description : Write-only access to instruction memory location 17 +#define PIO_INSTR_MEM17_OFFSET 0x0000008c +#define PIO_INSTR_MEM17_BITS 0x0000ffff +#define PIO_INSTR_MEM17_RESET 0x00000000 +#define PIO_INSTR_MEM17_MSB 15 +#define PIO_INSTR_MEM17_LSB 0 +#define PIO_INSTR_MEM17_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM18 +// Description : Write-only access to instruction memory location 18 +#define PIO_INSTR_MEM18_OFFSET 0x00000090 +#define PIO_INSTR_MEM18_BITS 0x0000ffff +#define PIO_INSTR_MEM18_RESET 0x00000000 +#define PIO_INSTR_MEM18_MSB 15 +#define PIO_INSTR_MEM18_LSB 0 +#define PIO_INSTR_MEM18_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM19 +// Description : Write-only access to instruction memory location 19 +#define PIO_INSTR_MEM19_OFFSET 0x00000094 +#define PIO_INSTR_MEM19_BITS 0x0000ffff +#define PIO_INSTR_MEM19_RESET 0x00000000 +#define PIO_INSTR_MEM19_MSB 15 +#define PIO_INSTR_MEM19_LSB 0 +#define PIO_INSTR_MEM19_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM20 +// Description : Write-only access to instruction memory location 20 +#define PIO_INSTR_MEM20_OFFSET 0x00000098 +#define PIO_INSTR_MEM20_BITS 0x0000ffff +#define PIO_INSTR_MEM20_RESET 0x00000000 +#define PIO_INSTR_MEM20_MSB 15 +#define PIO_INSTR_MEM20_LSB 0 +#define PIO_INSTR_MEM20_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM21 +// Description : Write-only access to instruction memory location 21 +#define PIO_INSTR_MEM21_OFFSET 0x0000009c +#define PIO_INSTR_MEM21_BITS 0x0000ffff +#define PIO_INSTR_MEM21_RESET 0x00000000 +#define PIO_INSTR_MEM21_MSB 15 +#define PIO_INSTR_MEM21_LSB 0 +#define PIO_INSTR_MEM21_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM22 +// Description : Write-only access to instruction memory location 22 +#define PIO_INSTR_MEM22_OFFSET 0x000000a0 +#define PIO_INSTR_MEM22_BITS 0x0000ffff +#define PIO_INSTR_MEM22_RESET 0x00000000 +#define PIO_INSTR_MEM22_MSB 15 +#define PIO_INSTR_MEM22_LSB 0 +#define PIO_INSTR_MEM22_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM23 +// Description : Write-only access to instruction memory location 23 +#define PIO_INSTR_MEM23_OFFSET 0x000000a4 +#define PIO_INSTR_MEM23_BITS 0x0000ffff +#define PIO_INSTR_MEM23_RESET 0x00000000 +#define PIO_INSTR_MEM23_MSB 15 +#define PIO_INSTR_MEM23_LSB 0 +#define PIO_INSTR_MEM23_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM24 +// Description : Write-only access to instruction memory location 24 +#define PIO_INSTR_MEM24_OFFSET 0x000000a8 +#define PIO_INSTR_MEM24_BITS 0x0000ffff +#define PIO_INSTR_MEM24_RESET 0x00000000 +#define PIO_INSTR_MEM24_MSB 15 +#define PIO_INSTR_MEM24_LSB 0 +#define PIO_INSTR_MEM24_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM25 +// Description : Write-only access to instruction memory location 25 +#define PIO_INSTR_MEM25_OFFSET 0x000000ac +#define PIO_INSTR_MEM25_BITS 0x0000ffff +#define PIO_INSTR_MEM25_RESET 0x00000000 +#define PIO_INSTR_MEM25_MSB 15 +#define PIO_INSTR_MEM25_LSB 0 +#define PIO_INSTR_MEM25_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM26 +// Description : Write-only access to instruction memory location 26 +#define PIO_INSTR_MEM26_OFFSET 0x000000b0 +#define PIO_INSTR_MEM26_BITS 0x0000ffff +#define PIO_INSTR_MEM26_RESET 0x00000000 +#define PIO_INSTR_MEM26_MSB 15 +#define PIO_INSTR_MEM26_LSB 0 +#define PIO_INSTR_MEM26_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM27 +// Description : Write-only access to instruction memory location 27 +#define PIO_INSTR_MEM27_OFFSET 0x000000b4 +#define PIO_INSTR_MEM27_BITS 0x0000ffff +#define PIO_INSTR_MEM27_RESET 0x00000000 +#define PIO_INSTR_MEM27_MSB 15 +#define PIO_INSTR_MEM27_LSB 0 +#define PIO_INSTR_MEM27_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM28 +// Description : Write-only access to instruction memory location 28 +#define PIO_INSTR_MEM28_OFFSET 0x000000b8 +#define PIO_INSTR_MEM28_BITS 0x0000ffff +#define PIO_INSTR_MEM28_RESET 0x00000000 +#define PIO_INSTR_MEM28_MSB 15 +#define PIO_INSTR_MEM28_LSB 0 +#define PIO_INSTR_MEM28_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM29 +// Description : Write-only access to instruction memory location 29 +#define PIO_INSTR_MEM29_OFFSET 0x000000bc +#define PIO_INSTR_MEM29_BITS 0x0000ffff +#define PIO_INSTR_MEM29_RESET 0x00000000 +#define PIO_INSTR_MEM29_MSB 15 +#define PIO_INSTR_MEM29_LSB 0 +#define PIO_INSTR_MEM29_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM30 +// Description : Write-only access to instruction memory location 30 +#define PIO_INSTR_MEM30_OFFSET 0x000000c0 +#define PIO_INSTR_MEM30_BITS 0x0000ffff +#define PIO_INSTR_MEM30_RESET 0x00000000 +#define PIO_INSTR_MEM30_MSB 15 +#define PIO_INSTR_MEM30_LSB 0 +#define PIO_INSTR_MEM30_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM31 +// Description : Write-only access to instruction memory location 31 +#define PIO_INSTR_MEM31_OFFSET 0x000000c4 +#define PIO_INSTR_MEM31_BITS 0x0000ffff +#define PIO_INSTR_MEM31_RESET 0x00000000 +#define PIO_INSTR_MEM31_MSB 15 +#define PIO_INSTR_MEM31_LSB 0 +#define PIO_INSTR_MEM31_ACCESS "WO" +// ============================================================================= +// Register : PIO_SM0_CLKDIV +// Description : Clock divider register for state machine 0 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM0_CLKDIV_OFFSET 0x000000c8 +#define PIO_SM0_CLKDIV_BITS 0xffffff00 +#define PIO_SM0_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM0_CLKDIV_INT_RESET 0x0001 +#define PIO_SM0_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM0_CLKDIV_INT_MSB 31 +#define PIO_SM0_CLKDIV_INT_LSB 16 +#define PIO_SM0_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM0_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM0_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM0_CLKDIV_FRAC_MSB 15 +#define PIO_SM0_CLKDIV_FRAC_LSB 8 +#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_EXECCTRL +// Description : Execution/behavioural settings for state machine 0 +#define PIO_SM0_EXECCTRL_OFFSET 0x000000cc +#define PIO_SM0_EXECCTRL_BITS 0xffffff9f +#define PIO_SM0_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM0_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM0_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM0_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM0_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 0 +#define PIO_SM0_SHIFTCTRL_OFFSET 0x000000d0 +#define PIO_SM0_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM0_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_ADDR +// Description : Current instruction address of state machine 0 +#define PIO_SM0_ADDR_OFFSET 0x000000d4 +#define PIO_SM0_ADDR_BITS 0x0000001f +#define PIO_SM0_ADDR_RESET 0x00000000 +#define PIO_SM0_ADDR_MSB 4 +#define PIO_SM0_ADDR_LSB 0 +#define PIO_SM0_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM0_INSTR +// Description : Instruction currently being executed by state machine 0 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM0_INSTR_OFFSET 0x000000d8 +#define PIO_SM0_INSTR_BITS 0x0000ffff +#define PIO_SM0_INSTR_RESET "-" +#define PIO_SM0_INSTR_MSB 15 +#define PIO_SM0_INSTR_LSB 0 +#define PIO_SM0_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_PINCTRL +// Description : State machine pin control +#define PIO_SM0_PINCTRL_OFFSET 0x000000dc +#define PIO_SM0_PINCTRL_BITS 0xffffffff +#define PIO_SM0_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM0_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM0_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM0_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM0_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM0_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM0_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM0_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM0_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM0_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM0_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM0_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM0_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM0_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_CLKDIV +// Description : Clock divider register for state machine 1 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM1_CLKDIV_OFFSET 0x000000e0 +#define PIO_SM1_CLKDIV_BITS 0xffffff00 +#define PIO_SM1_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM1_CLKDIV_INT_RESET 0x0001 +#define PIO_SM1_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM1_CLKDIV_INT_MSB 31 +#define PIO_SM1_CLKDIV_INT_LSB 16 +#define PIO_SM1_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM1_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM1_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM1_CLKDIV_FRAC_MSB 15 +#define PIO_SM1_CLKDIV_FRAC_LSB 8 +#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_EXECCTRL +// Description : Execution/behavioural settings for state machine 1 +#define PIO_SM1_EXECCTRL_OFFSET 0x000000e4 +#define PIO_SM1_EXECCTRL_BITS 0xffffff9f +#define PIO_SM1_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM1_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM1_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM1_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM1_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 1 +#define PIO_SM1_SHIFTCTRL_OFFSET 0x000000e8 +#define PIO_SM1_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM1_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_ADDR +// Description : Current instruction address of state machine 1 +#define PIO_SM1_ADDR_OFFSET 0x000000ec +#define PIO_SM1_ADDR_BITS 0x0000001f +#define PIO_SM1_ADDR_RESET 0x00000000 +#define PIO_SM1_ADDR_MSB 4 +#define PIO_SM1_ADDR_LSB 0 +#define PIO_SM1_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM1_INSTR +// Description : Instruction currently being executed by state machine 1 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM1_INSTR_OFFSET 0x000000f0 +#define PIO_SM1_INSTR_BITS 0x0000ffff +#define PIO_SM1_INSTR_RESET "-" +#define PIO_SM1_INSTR_MSB 15 +#define PIO_SM1_INSTR_LSB 0 +#define PIO_SM1_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_PINCTRL +// Description : State machine pin control +#define PIO_SM1_PINCTRL_OFFSET 0x000000f4 +#define PIO_SM1_PINCTRL_BITS 0xffffffff +#define PIO_SM1_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM1_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM1_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM1_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM1_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM1_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM1_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM1_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM1_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM1_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM1_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM1_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM1_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM1_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_CLKDIV +// Description : Clock divider register for state machine 2 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM2_CLKDIV_OFFSET 0x000000f8 +#define PIO_SM2_CLKDIV_BITS 0xffffff00 +#define PIO_SM2_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM2_CLKDIV_INT_RESET 0x0001 +#define PIO_SM2_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM2_CLKDIV_INT_MSB 31 +#define PIO_SM2_CLKDIV_INT_LSB 16 +#define PIO_SM2_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM2_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM2_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM2_CLKDIV_FRAC_MSB 15 +#define PIO_SM2_CLKDIV_FRAC_LSB 8 +#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_EXECCTRL +// Description : Execution/behavioural settings for state machine 2 +#define PIO_SM2_EXECCTRL_OFFSET 0x000000fc +#define PIO_SM2_EXECCTRL_BITS 0xffffff9f +#define PIO_SM2_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM2_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM2_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM2_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM2_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 2 +#define PIO_SM2_SHIFTCTRL_OFFSET 0x00000100 +#define PIO_SM2_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM2_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_ADDR +// Description : Current instruction address of state machine 2 +#define PIO_SM2_ADDR_OFFSET 0x00000104 +#define PIO_SM2_ADDR_BITS 0x0000001f +#define PIO_SM2_ADDR_RESET 0x00000000 +#define PIO_SM2_ADDR_MSB 4 +#define PIO_SM2_ADDR_LSB 0 +#define PIO_SM2_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM2_INSTR +// Description : Instruction currently being executed by state machine 2 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM2_INSTR_OFFSET 0x00000108 +#define PIO_SM2_INSTR_BITS 0x0000ffff +#define PIO_SM2_INSTR_RESET "-" +#define PIO_SM2_INSTR_MSB 15 +#define PIO_SM2_INSTR_LSB 0 +#define PIO_SM2_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_PINCTRL +// Description : State machine pin control +#define PIO_SM2_PINCTRL_OFFSET 0x0000010c +#define PIO_SM2_PINCTRL_BITS 0xffffffff +#define PIO_SM2_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM2_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM2_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM2_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM2_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM2_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM2_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM2_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM2_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM2_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM2_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM2_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM2_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM2_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_CLKDIV +// Description : Clock divider register for state machine 3 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM3_CLKDIV_OFFSET 0x00000110 +#define PIO_SM3_CLKDIV_BITS 0xffffff00 +#define PIO_SM3_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM3_CLKDIV_INT_RESET 0x0001 +#define PIO_SM3_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM3_CLKDIV_INT_MSB 31 +#define PIO_SM3_CLKDIV_INT_LSB 16 +#define PIO_SM3_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM3_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM3_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM3_CLKDIV_FRAC_MSB 15 +#define PIO_SM3_CLKDIV_FRAC_LSB 8 +#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_EXECCTRL +// Description : Execution/behavioural settings for state machine 3 +#define PIO_SM3_EXECCTRL_OFFSET 0x00000114 +#define PIO_SM3_EXECCTRL_BITS 0xffffff9f +#define PIO_SM3_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM3_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM3_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM3_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM3_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 3 +#define PIO_SM3_SHIFTCTRL_OFFSET 0x00000118 +#define PIO_SM3_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM3_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_ADDR +// Description : Current instruction address of state machine 3 +#define PIO_SM3_ADDR_OFFSET 0x0000011c +#define PIO_SM3_ADDR_BITS 0x0000001f +#define PIO_SM3_ADDR_RESET 0x00000000 +#define PIO_SM3_ADDR_MSB 4 +#define PIO_SM3_ADDR_LSB 0 +#define PIO_SM3_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM3_INSTR +// Description : Instruction currently being executed by state machine 3 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM3_INSTR_OFFSET 0x00000120 +#define PIO_SM3_INSTR_BITS 0x0000ffff +#define PIO_SM3_INSTR_RESET "-" +#define PIO_SM3_INSTR_MSB 15 +#define PIO_SM3_INSTR_LSB 0 +#define PIO_SM3_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_PINCTRL +// Description : State machine pin control +#define PIO_SM3_PINCTRL_OFFSET 0x00000124 +#define PIO_SM3_PINCTRL_BITS 0xffffffff +#define PIO_SM3_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM3_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM3_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM3_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM3_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM3_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM3_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM3_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM3_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM3_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM3_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM3_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM3_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM3_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_INTR +// Description : Raw Interrupts +#define PIO_INTR_OFFSET 0x00000128 +#define PIO_INTR_BITS 0x00000fff +#define PIO_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3 +// Description : None +#define PIO_INTR_SM3_RESET 0x0 +#define PIO_INTR_SM3_BITS 0x00000800 +#define PIO_INTR_SM3_MSB 11 +#define PIO_INTR_SM3_LSB 11 +#define PIO_INTR_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2 +// Description : None +#define PIO_INTR_SM2_RESET 0x0 +#define PIO_INTR_SM2_BITS 0x00000400 +#define PIO_INTR_SM2_MSB 10 +#define PIO_INTR_SM2_LSB 10 +#define PIO_INTR_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1 +// Description : None +#define PIO_INTR_SM1_RESET 0x0 +#define PIO_INTR_SM1_BITS 0x00000200 +#define PIO_INTR_SM1_MSB 9 +#define PIO_INTR_SM1_LSB 9 +#define PIO_INTR_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0 +// Description : None +#define PIO_INTR_SM0_RESET 0x0 +#define PIO_INTR_SM0_BITS 0x00000100 +#define PIO_INTR_SM0_MSB 8 +#define PIO_INTR_SM0_LSB 8 +#define PIO_INTR_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_TXNFULL +// Description : None +#define PIO_INTR_SM3_TXNFULL_RESET 0x0 +#define PIO_INTR_SM3_TXNFULL_BITS 0x00000080 +#define PIO_INTR_SM3_TXNFULL_MSB 7 +#define PIO_INTR_SM3_TXNFULL_LSB 7 +#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_TXNFULL +// Description : None +#define PIO_INTR_SM2_TXNFULL_RESET 0x0 +#define PIO_INTR_SM2_TXNFULL_BITS 0x00000040 +#define PIO_INTR_SM2_TXNFULL_MSB 6 +#define PIO_INTR_SM2_TXNFULL_LSB 6 +#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_TXNFULL +// Description : None +#define PIO_INTR_SM1_TXNFULL_RESET 0x0 +#define PIO_INTR_SM1_TXNFULL_BITS 0x00000020 +#define PIO_INTR_SM1_TXNFULL_MSB 5 +#define PIO_INTR_SM1_TXNFULL_LSB 5 +#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_TXNFULL +// Description : None +#define PIO_INTR_SM0_TXNFULL_RESET 0x0 +#define PIO_INTR_SM0_TXNFULL_BITS 0x00000010 +#define PIO_INTR_SM0_TXNFULL_MSB 4 +#define PIO_INTR_SM0_TXNFULL_LSB 4 +#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_RXNEMPTY +// Description : None +#define PIO_INTR_SM3_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_INTR_SM3_RXNEMPTY_MSB 3 +#define PIO_INTR_SM3_RXNEMPTY_LSB 3 +#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_RXNEMPTY +// Description : None +#define PIO_INTR_SM2_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_INTR_SM2_RXNEMPTY_MSB 2 +#define PIO_INTR_SM2_RXNEMPTY_LSB 2 +#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_RXNEMPTY +// Description : None +#define PIO_INTR_SM1_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_INTR_SM1_RXNEMPTY_MSB 1 +#define PIO_INTR_SM1_RXNEMPTY_LSB 1 +#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_RXNEMPTY +// Description : None +#define PIO_INTR_SM0_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_INTR_SM0_RXNEMPTY_MSB 0 +#define PIO_INTR_SM0_RXNEMPTY_LSB 0 +#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PIO_IRQ0_INTE_OFFSET 0x0000012c +#define PIO_IRQ0_INTE_BITS 0x00000fff +#define PIO_IRQ0_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3 +// Description : None +#define PIO_IRQ0_INTE_SM3_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTE_SM3_MSB 11 +#define PIO_IRQ0_INTE_SM3_LSB 11 +#define PIO_IRQ0_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2 +// Description : None +#define PIO_IRQ0_INTE_SM2_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTE_SM2_MSB 10 +#define PIO_IRQ0_INTE_SM2_LSB 10 +#define PIO_IRQ0_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1 +// Description : None +#define PIO_IRQ0_INTE_SM1_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTE_SM1_MSB 9 +#define PIO_IRQ0_INTE_SM1_LSB 9 +#define PIO_IRQ0_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0 +// Description : None +#define PIO_IRQ0_INTE_SM0_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTE_SM0_MSB 8 +#define PIO_IRQ0_INTE_SM0_LSB 8 +#define PIO_IRQ0_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PIO_IRQ0_INTF_OFFSET 0x00000130 +#define PIO_IRQ0_INTF_BITS 0x00000fff +#define PIO_IRQ0_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3 +// Description : None +#define PIO_IRQ0_INTF_SM3_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTF_SM3_MSB 11 +#define PIO_IRQ0_INTF_SM3_LSB 11 +#define PIO_IRQ0_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2 +// Description : None +#define PIO_IRQ0_INTF_SM2_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTF_SM2_MSB 10 +#define PIO_IRQ0_INTF_SM2_LSB 10 +#define PIO_IRQ0_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1 +// Description : None +#define PIO_IRQ0_INTF_SM1_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTF_SM1_MSB 9 +#define PIO_IRQ0_INTF_SM1_LSB 9 +#define PIO_IRQ0_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0 +// Description : None +#define PIO_IRQ0_INTF_SM0_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTF_SM0_MSB 8 +#define PIO_IRQ0_INTF_SM0_LSB 8 +#define PIO_IRQ0_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PIO_IRQ0_INTS_OFFSET 0x00000134 +#define PIO_IRQ0_INTS_BITS 0x00000fff +#define PIO_IRQ0_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3 +// Description : None +#define PIO_IRQ0_INTS_SM3_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTS_SM3_MSB 11 +#define PIO_IRQ0_INTS_SM3_LSB 11 +#define PIO_IRQ0_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2 +// Description : None +#define PIO_IRQ0_INTS_SM2_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTS_SM2_MSB 10 +#define PIO_IRQ0_INTS_SM2_LSB 10 +#define PIO_IRQ0_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1 +// Description : None +#define PIO_IRQ0_INTS_SM1_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTS_SM1_MSB 9 +#define PIO_IRQ0_INTS_SM1_LSB 9 +#define PIO_IRQ0_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0 +// Description : None +#define PIO_IRQ0_INTS_SM0_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTS_SM0_MSB 8 +#define PIO_IRQ0_INTS_SM0_LSB 8 +#define PIO_IRQ0_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PIO_IRQ1_INTE_OFFSET 0x00000138 +#define PIO_IRQ1_INTE_BITS 0x00000fff +#define PIO_IRQ1_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3 +// Description : None +#define PIO_IRQ1_INTE_SM3_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTE_SM3_MSB 11 +#define PIO_IRQ1_INTE_SM3_LSB 11 +#define PIO_IRQ1_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2 +// Description : None +#define PIO_IRQ1_INTE_SM2_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTE_SM2_MSB 10 +#define PIO_IRQ1_INTE_SM2_LSB 10 +#define PIO_IRQ1_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1 +// Description : None +#define PIO_IRQ1_INTE_SM1_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTE_SM1_MSB 9 +#define PIO_IRQ1_INTE_SM1_LSB 9 +#define PIO_IRQ1_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0 +// Description : None +#define PIO_IRQ1_INTE_SM0_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTE_SM0_MSB 8 +#define PIO_IRQ1_INTE_SM0_LSB 8 +#define PIO_IRQ1_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PIO_IRQ1_INTF_OFFSET 0x0000013c +#define PIO_IRQ1_INTF_BITS 0x00000fff +#define PIO_IRQ1_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3 +// Description : None +#define PIO_IRQ1_INTF_SM3_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTF_SM3_MSB 11 +#define PIO_IRQ1_INTF_SM3_LSB 11 +#define PIO_IRQ1_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2 +// Description : None +#define PIO_IRQ1_INTF_SM2_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTF_SM2_MSB 10 +#define PIO_IRQ1_INTF_SM2_LSB 10 +#define PIO_IRQ1_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1 +// Description : None +#define PIO_IRQ1_INTF_SM1_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTF_SM1_MSB 9 +#define PIO_IRQ1_INTF_SM1_LSB 9 +#define PIO_IRQ1_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0 +// Description : None +#define PIO_IRQ1_INTF_SM0_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTF_SM0_MSB 8 +#define PIO_IRQ1_INTF_SM0_LSB 8 +#define PIO_IRQ1_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PIO_IRQ1_INTS_OFFSET 0x00000140 +#define PIO_IRQ1_INTS_BITS 0x00000fff +#define PIO_IRQ1_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3 +// Description : None +#define PIO_IRQ1_INTS_SM3_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTS_SM3_MSB 11 +#define PIO_IRQ1_INTS_SM3_LSB 11 +#define PIO_IRQ1_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2 +// Description : None +#define PIO_IRQ1_INTS_SM2_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTS_SM2_MSB 10 +#define PIO_IRQ1_INTS_SM2_LSB 10 +#define PIO_IRQ1_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1 +// Description : None +#define PIO_IRQ1_INTS_SM1_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTS_SM1_MSB 9 +#define PIO_IRQ1_INTS_SM1_LSB 9 +#define PIO_IRQ1_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0 +// Description : None +#define PIO_IRQ1_INTS_SM0_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTS_SM0_MSB 8 +#define PIO_IRQ1_INTS_SM0_LSB 8 +#define PIO_IRQ1_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PIO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h new file mode 100644 index 00000000000..6a21d5603fc --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PLL +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PLL_DEFINED +#define HARDWARE_REGS_PLL_DEFINED +// ============================================================================= +// Register : PLL_CS +// Description : Control and Status +// GENERAL CONSTRAINTS: +// Reference clock frequency min=5MHz, max=800MHz +// Feedback divider min=16, max=320 +// VCO frequency min=400MHz, max=1600MHz +#define PLL_CS_OFFSET 0x00000000 +#define PLL_CS_BITS 0x8000013f +#define PLL_CS_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK +// Description : PLL is locked +#define PLL_CS_LOCK_RESET 0x0 +#define PLL_CS_LOCK_BITS 0x80000000 +#define PLL_CS_LOCK_MSB 31 +#define PLL_CS_LOCK_LSB 31 +#define PLL_CS_LOCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_BYPASS +// Description : Passes the reference clock to the output instead of the divided +// VCO. The VCO continues to run so the user can switch between +// the reference clock and the divided VCO but the output will +// glitch when doing so. +#define PLL_CS_BYPASS_RESET 0x0 +#define PLL_CS_BYPASS_BITS 0x00000100 +#define PLL_CS_BYPASS_MSB 8 +#define PLL_CS_BYPASS_LSB 8 +#define PLL_CS_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_REFDIV +// Description : Divides the PLL input reference clock. +// Behaviour is undefined for div=0. +// PLL output will be unpredictable during refdiv changes, wait +// for lock=1 before using it. +#define PLL_CS_REFDIV_RESET 0x01 +#define PLL_CS_REFDIV_BITS 0x0000003f +#define PLL_CS_REFDIV_MSB 5 +#define PLL_CS_REFDIV_LSB 0 +#define PLL_CS_REFDIV_ACCESS "RW" +// ============================================================================= +// Register : PLL_PWR +// Description : Controls the PLL power modes. +#define PLL_PWR_OFFSET 0x00000004 +#define PLL_PWR_BITS 0x0000002d +#define PLL_PWR_RESET 0x0000002d +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_VCOPD +// Description : PLL VCO powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_VCOPD_RESET 0x1 +#define PLL_PWR_VCOPD_BITS 0x00000020 +#define PLL_PWR_VCOPD_MSB 5 +#define PLL_PWR_VCOPD_LSB 5 +#define PLL_PWR_VCOPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_POSTDIVPD +// Description : PLL post divider powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_POSTDIVPD_RESET 0x1 +#define PLL_PWR_POSTDIVPD_BITS 0x00000008 +#define PLL_PWR_POSTDIVPD_MSB 3 +#define PLL_PWR_POSTDIVPD_LSB 3 +#define PLL_PWR_POSTDIVPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_DSMPD +// Description : PLL DSM powerdown +// Nothing is achieved by setting this low. +#define PLL_PWR_DSMPD_RESET 0x1 +#define PLL_PWR_DSMPD_BITS 0x00000004 +#define PLL_PWR_DSMPD_MSB 2 +#define PLL_PWR_DSMPD_LSB 2 +#define PLL_PWR_DSMPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_PD +// Description : PLL powerdown +// To save power set high when PLL output not required. +#define PLL_PWR_PD_RESET 0x1 +#define PLL_PWR_PD_BITS 0x00000001 +#define PLL_PWR_PD_MSB 0 +#define PLL_PWR_PD_LSB 0 +#define PLL_PWR_PD_ACCESS "RW" +// ============================================================================= +// Register : PLL_FBDIV_INT +// Description : Feedback divisor +// (note: this PLL does not support fractional division) +// see ctrl reg description for constraints +#define PLL_FBDIV_INT_OFFSET 0x00000008 +#define PLL_FBDIV_INT_BITS 0x00000fff +#define PLL_FBDIV_INT_RESET 0x00000000 +#define PLL_FBDIV_INT_MSB 11 +#define PLL_FBDIV_INT_LSB 0 +#define PLL_FBDIV_INT_ACCESS "RW" +// ============================================================================= +// Register : PLL_PRIM +// Description : Controls the PLL post dividers for the primary output +// (note: this PLL does not have a secondary output) +// the primary output is driven from VCO divided by +// postdiv1*postdiv2 +#define PLL_PRIM_OFFSET 0x0000000c +#define PLL_PRIM_BITS 0x00077000 +#define PLL_PRIM_RESET 0x00077000 +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV1 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV1_RESET 0x7 +#define PLL_PRIM_POSTDIV1_BITS 0x00070000 +#define PLL_PRIM_POSTDIV1_MSB 18 +#define PLL_PRIM_POSTDIV1_LSB 16 +#define PLL_PRIM_POSTDIV1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV2 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV2_RESET 0x7 +#define PLL_PRIM_POSTDIV2_BITS 0x00007000 +#define PLL_PRIM_POSTDIV2_MSB 14 +#define PLL_PRIM_POSTDIV2_LSB 12 +#define PLL_PRIM_POSTDIV2_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PLL_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h new file mode 100644 index 00000000000..dacf36394ed --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h @@ -0,0 +1,584 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PSM +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PSM_DEFINED +#define HARDWARE_REGS_PSM_DEFINED +// ============================================================================= +// Register : PSM_FRCE_ON +// Description : Force block out of reset (i.e. power it on) +#define PSM_FRCE_ON_OFFSET 0x00000000 +#define PSM_FRCE_ON_BITS 0x0001ffff +#define PSM_FRCE_ON_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC1 +// Description : None +#define PSM_FRCE_ON_PROC1_RESET 0x0 +#define PSM_FRCE_ON_PROC1_BITS 0x00010000 +#define PSM_FRCE_ON_PROC1_MSB 16 +#define PSM_FRCE_ON_PROC1_LSB 16 +#define PSM_FRCE_ON_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC0 +// Description : None +#define PSM_FRCE_ON_PROC0_RESET 0x0 +#define PSM_FRCE_ON_PROC0_BITS 0x00008000 +#define PSM_FRCE_ON_PROC0_MSB 15 +#define PSM_FRCE_ON_PROC0_LSB 15 +#define PSM_FRCE_ON_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SIO +// Description : None +#define PSM_FRCE_ON_SIO_RESET 0x0 +#define PSM_FRCE_ON_SIO_BITS 0x00004000 +#define PSM_FRCE_ON_SIO_MSB 14 +#define PSM_FRCE_ON_SIO_LSB 14 +#define PSM_FRCE_ON_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET +// Description : None +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XIP +// Description : None +#define PSM_FRCE_ON_XIP_RESET 0x0 +#define PSM_FRCE_ON_XIP_BITS 0x00001000 +#define PSM_FRCE_ON_XIP_MSB 12 +#define PSM_FRCE_ON_XIP_LSB 12 +#define PSM_FRCE_ON_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM5 +// Description : None +#define PSM_FRCE_ON_SRAM5_RESET 0x0 +#define PSM_FRCE_ON_SRAM5_BITS 0x00000800 +#define PSM_FRCE_ON_SRAM5_MSB 11 +#define PSM_FRCE_ON_SRAM5_LSB 11 +#define PSM_FRCE_ON_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM4 +// Description : None +#define PSM_FRCE_ON_SRAM4_RESET 0x0 +#define PSM_FRCE_ON_SRAM4_BITS 0x00000400 +#define PSM_FRCE_ON_SRAM4_MSB 10 +#define PSM_FRCE_ON_SRAM4_LSB 10 +#define PSM_FRCE_ON_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM3 +// Description : None +#define PSM_FRCE_ON_SRAM3_RESET 0x0 +#define PSM_FRCE_ON_SRAM3_BITS 0x00000200 +#define PSM_FRCE_ON_SRAM3_MSB 9 +#define PSM_FRCE_ON_SRAM3_LSB 9 +#define PSM_FRCE_ON_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM2 +// Description : None +#define PSM_FRCE_ON_SRAM2_RESET 0x0 +#define PSM_FRCE_ON_SRAM2_BITS 0x00000100 +#define PSM_FRCE_ON_SRAM2_MSB 8 +#define PSM_FRCE_ON_SRAM2_LSB 8 +#define PSM_FRCE_ON_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM1 +// Description : None +#define PSM_FRCE_ON_SRAM1_RESET 0x0 +#define PSM_FRCE_ON_SRAM1_BITS 0x00000080 +#define PSM_FRCE_ON_SRAM1_MSB 7 +#define PSM_FRCE_ON_SRAM1_LSB 7 +#define PSM_FRCE_ON_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM0 +// Description : None +#define PSM_FRCE_ON_SRAM0_RESET 0x0 +#define PSM_FRCE_ON_SRAM0_BITS 0x00000040 +#define PSM_FRCE_ON_SRAM0_MSB 6 +#define PSM_FRCE_ON_SRAM0_LSB 6 +#define PSM_FRCE_ON_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROM +// Description : None +#define PSM_FRCE_ON_ROM_RESET 0x0 +#define PSM_FRCE_ON_ROM_BITS 0x00000020 +#define PSM_FRCE_ON_ROM_MSB 5 +#define PSM_FRCE_ON_ROM_LSB 5 +#define PSM_FRCE_ON_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BUSFABRIC +// Description : None +#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0 +#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010 +#define PSM_FRCE_ON_BUSFABRIC_MSB 4 +#define PSM_FRCE_ON_BUSFABRIC_LSB 4 +#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_RESETS +// Description : None +#define PSM_FRCE_ON_RESETS_RESET 0x0 +#define PSM_FRCE_ON_RESETS_BITS 0x00000008 +#define PSM_FRCE_ON_RESETS_MSB 3 +#define PSM_FRCE_ON_RESETS_LSB 3 +#define PSM_FRCE_ON_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_CLOCKS +// Description : None +#define PSM_FRCE_ON_CLOCKS_RESET 0x0 +#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004 +#define PSM_FRCE_ON_CLOCKS_MSB 2 +#define PSM_FRCE_ON_CLOCKS_LSB 2 +#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XOSC +// Description : None +#define PSM_FRCE_ON_XOSC_RESET 0x0 +#define PSM_FRCE_ON_XOSC_BITS 0x00000002 +#define PSM_FRCE_ON_XOSC_MSB 1 +#define PSM_FRCE_ON_XOSC_LSB 1 +#define PSM_FRCE_ON_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROSC +// Description : None +#define PSM_FRCE_ON_ROSC_RESET 0x0 +#define PSM_FRCE_ON_ROSC_BITS 0x00000001 +#define PSM_FRCE_ON_ROSC_MSB 0 +#define PSM_FRCE_ON_ROSC_LSB 0 +#define PSM_FRCE_ON_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_FRCE_OFF +// Description : Force into reset (i.e. power it off) +#define PSM_FRCE_OFF_OFFSET 0x00000004 +#define PSM_FRCE_OFF_BITS 0x0001ffff +#define PSM_FRCE_OFF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC1 +// Description : None +#define PSM_FRCE_OFF_PROC1_RESET 0x0 +#define PSM_FRCE_OFF_PROC1_BITS 0x00010000 +#define PSM_FRCE_OFF_PROC1_MSB 16 +#define PSM_FRCE_OFF_PROC1_LSB 16 +#define PSM_FRCE_OFF_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC0 +// Description : None +#define PSM_FRCE_OFF_PROC0_RESET 0x0 +#define PSM_FRCE_OFF_PROC0_BITS 0x00008000 +#define PSM_FRCE_OFF_PROC0_MSB 15 +#define PSM_FRCE_OFF_PROC0_LSB 15 +#define PSM_FRCE_OFF_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SIO +// Description : None +#define PSM_FRCE_OFF_SIO_RESET 0x0 +#define PSM_FRCE_OFF_SIO_BITS 0x00004000 +#define PSM_FRCE_OFF_SIO_MSB 14 +#define PSM_FRCE_OFF_SIO_LSB 14 +#define PSM_FRCE_OFF_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET +// Description : None +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XIP +// Description : None +#define PSM_FRCE_OFF_XIP_RESET 0x0 +#define PSM_FRCE_OFF_XIP_BITS 0x00001000 +#define PSM_FRCE_OFF_XIP_MSB 12 +#define PSM_FRCE_OFF_XIP_LSB 12 +#define PSM_FRCE_OFF_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM5 +// Description : None +#define PSM_FRCE_OFF_SRAM5_RESET 0x0 +#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800 +#define PSM_FRCE_OFF_SRAM5_MSB 11 +#define PSM_FRCE_OFF_SRAM5_LSB 11 +#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM4 +// Description : None +#define PSM_FRCE_OFF_SRAM4_RESET 0x0 +#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400 +#define PSM_FRCE_OFF_SRAM4_MSB 10 +#define PSM_FRCE_OFF_SRAM4_LSB 10 +#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM3 +// Description : None +#define PSM_FRCE_OFF_SRAM3_RESET 0x0 +#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200 +#define PSM_FRCE_OFF_SRAM3_MSB 9 +#define PSM_FRCE_OFF_SRAM3_LSB 9 +#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM2 +// Description : None +#define PSM_FRCE_OFF_SRAM2_RESET 0x0 +#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100 +#define PSM_FRCE_OFF_SRAM2_MSB 8 +#define PSM_FRCE_OFF_SRAM2_LSB 8 +#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM1 +// Description : None +#define PSM_FRCE_OFF_SRAM1_RESET 0x0 +#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080 +#define PSM_FRCE_OFF_SRAM1_MSB 7 +#define PSM_FRCE_OFF_SRAM1_LSB 7 +#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM0 +// Description : None +#define PSM_FRCE_OFF_SRAM0_RESET 0x0 +#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040 +#define PSM_FRCE_OFF_SRAM0_MSB 6 +#define PSM_FRCE_OFF_SRAM0_LSB 6 +#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROM +// Description : None +#define PSM_FRCE_OFF_ROM_RESET 0x0 +#define PSM_FRCE_OFF_ROM_BITS 0x00000020 +#define PSM_FRCE_OFF_ROM_MSB 5 +#define PSM_FRCE_OFF_ROM_LSB 5 +#define PSM_FRCE_OFF_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BUSFABRIC +// Description : None +#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0 +#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010 +#define PSM_FRCE_OFF_BUSFABRIC_MSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_LSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_RESETS +// Description : None +#define PSM_FRCE_OFF_RESETS_RESET 0x0 +#define PSM_FRCE_OFF_RESETS_BITS 0x00000008 +#define PSM_FRCE_OFF_RESETS_MSB 3 +#define PSM_FRCE_OFF_RESETS_LSB 3 +#define PSM_FRCE_OFF_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_CLOCKS +// Description : None +#define PSM_FRCE_OFF_CLOCKS_RESET 0x0 +#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004 +#define PSM_FRCE_OFF_CLOCKS_MSB 2 +#define PSM_FRCE_OFF_CLOCKS_LSB 2 +#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XOSC +// Description : None +#define PSM_FRCE_OFF_XOSC_RESET 0x0 +#define PSM_FRCE_OFF_XOSC_BITS 0x00000002 +#define PSM_FRCE_OFF_XOSC_MSB 1 +#define PSM_FRCE_OFF_XOSC_LSB 1 +#define PSM_FRCE_OFF_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROSC +// Description : None +#define PSM_FRCE_OFF_ROSC_RESET 0x0 +#define PSM_FRCE_OFF_ROSC_BITS 0x00000001 +#define PSM_FRCE_OFF_ROSC_MSB 0 +#define PSM_FRCE_OFF_ROSC_LSB 0 +#define PSM_FRCE_OFF_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_WDSEL +// Description : Set to 1 if this peripheral should be reset when the watchdog +// fires. +#define PSM_WDSEL_OFFSET 0x00000008 +#define PSM_WDSEL_BITS 0x0001ffff +#define PSM_WDSEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC1 +// Description : None +#define PSM_WDSEL_PROC1_RESET 0x0 +#define PSM_WDSEL_PROC1_BITS 0x00010000 +#define PSM_WDSEL_PROC1_MSB 16 +#define PSM_WDSEL_PROC1_LSB 16 +#define PSM_WDSEL_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC0 +// Description : None +#define PSM_WDSEL_PROC0_RESET 0x0 +#define PSM_WDSEL_PROC0_BITS 0x00008000 +#define PSM_WDSEL_PROC0_MSB 15 +#define PSM_WDSEL_PROC0_LSB 15 +#define PSM_WDSEL_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SIO +// Description : None +#define PSM_WDSEL_SIO_RESET 0x0 +#define PSM_WDSEL_SIO_BITS 0x00004000 +#define PSM_WDSEL_SIO_MSB 14 +#define PSM_WDSEL_SIO_LSB 14 +#define PSM_WDSEL_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_VREG_AND_CHIP_RESET +// Description : None +#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XIP +// Description : None +#define PSM_WDSEL_XIP_RESET 0x0 +#define PSM_WDSEL_XIP_BITS 0x00001000 +#define PSM_WDSEL_XIP_MSB 12 +#define PSM_WDSEL_XIP_LSB 12 +#define PSM_WDSEL_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM5 +// Description : None +#define PSM_WDSEL_SRAM5_RESET 0x0 +#define PSM_WDSEL_SRAM5_BITS 0x00000800 +#define PSM_WDSEL_SRAM5_MSB 11 +#define PSM_WDSEL_SRAM5_LSB 11 +#define PSM_WDSEL_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM4 +// Description : None +#define PSM_WDSEL_SRAM4_RESET 0x0 +#define PSM_WDSEL_SRAM4_BITS 0x00000400 +#define PSM_WDSEL_SRAM4_MSB 10 +#define PSM_WDSEL_SRAM4_LSB 10 +#define PSM_WDSEL_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM3 +// Description : None +#define PSM_WDSEL_SRAM3_RESET 0x0 +#define PSM_WDSEL_SRAM3_BITS 0x00000200 +#define PSM_WDSEL_SRAM3_MSB 9 +#define PSM_WDSEL_SRAM3_LSB 9 +#define PSM_WDSEL_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM2 +// Description : None +#define PSM_WDSEL_SRAM2_RESET 0x0 +#define PSM_WDSEL_SRAM2_BITS 0x00000100 +#define PSM_WDSEL_SRAM2_MSB 8 +#define PSM_WDSEL_SRAM2_LSB 8 +#define PSM_WDSEL_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM1 +// Description : None +#define PSM_WDSEL_SRAM1_RESET 0x0 +#define PSM_WDSEL_SRAM1_BITS 0x00000080 +#define PSM_WDSEL_SRAM1_MSB 7 +#define PSM_WDSEL_SRAM1_LSB 7 +#define PSM_WDSEL_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM0 +// Description : None +#define PSM_WDSEL_SRAM0_RESET 0x0 +#define PSM_WDSEL_SRAM0_BITS 0x00000040 +#define PSM_WDSEL_SRAM0_MSB 6 +#define PSM_WDSEL_SRAM0_LSB 6 +#define PSM_WDSEL_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROM +// Description : None +#define PSM_WDSEL_ROM_RESET 0x0 +#define PSM_WDSEL_ROM_BITS 0x00000020 +#define PSM_WDSEL_ROM_MSB 5 +#define PSM_WDSEL_ROM_LSB 5 +#define PSM_WDSEL_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BUSFABRIC +// Description : None +#define PSM_WDSEL_BUSFABRIC_RESET 0x0 +#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010 +#define PSM_WDSEL_BUSFABRIC_MSB 4 +#define PSM_WDSEL_BUSFABRIC_LSB 4 +#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_RESETS +// Description : None +#define PSM_WDSEL_RESETS_RESET 0x0 +#define PSM_WDSEL_RESETS_BITS 0x00000008 +#define PSM_WDSEL_RESETS_MSB 3 +#define PSM_WDSEL_RESETS_LSB 3 +#define PSM_WDSEL_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_CLOCKS +// Description : None +#define PSM_WDSEL_CLOCKS_RESET 0x0 +#define PSM_WDSEL_CLOCKS_BITS 0x00000004 +#define PSM_WDSEL_CLOCKS_MSB 2 +#define PSM_WDSEL_CLOCKS_LSB 2 +#define PSM_WDSEL_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XOSC +// Description : None +#define PSM_WDSEL_XOSC_RESET 0x0 +#define PSM_WDSEL_XOSC_BITS 0x00000002 +#define PSM_WDSEL_XOSC_MSB 1 +#define PSM_WDSEL_XOSC_LSB 1 +#define PSM_WDSEL_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROSC +// Description : None +#define PSM_WDSEL_ROSC_RESET 0x0 +#define PSM_WDSEL_ROSC_BITS 0x00000001 +#define PSM_WDSEL_ROSC_MSB 0 +#define PSM_WDSEL_ROSC_LSB 0 +#define PSM_WDSEL_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_DONE +// Description : Indicates the peripheral's registers are ready to access. +#define PSM_DONE_OFFSET 0x0000000c +#define PSM_DONE_BITS 0x0001ffff +#define PSM_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC1 +// Description : None +#define PSM_DONE_PROC1_RESET 0x0 +#define PSM_DONE_PROC1_BITS 0x00010000 +#define PSM_DONE_PROC1_MSB 16 +#define PSM_DONE_PROC1_LSB 16 +#define PSM_DONE_PROC1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC0 +// Description : None +#define PSM_DONE_PROC0_RESET 0x0 +#define PSM_DONE_PROC0_BITS 0x00008000 +#define PSM_DONE_PROC0_MSB 15 +#define PSM_DONE_PROC0_LSB 15 +#define PSM_DONE_PROC0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SIO +// Description : None +#define PSM_DONE_SIO_RESET 0x0 +#define PSM_DONE_SIO_BITS 0x00004000 +#define PSM_DONE_SIO_MSB 14 +#define PSM_DONE_SIO_LSB 14 +#define PSM_DONE_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_VREG_AND_CHIP_RESET +// Description : None +#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XIP +// Description : None +#define PSM_DONE_XIP_RESET 0x0 +#define PSM_DONE_XIP_BITS 0x00001000 +#define PSM_DONE_XIP_MSB 12 +#define PSM_DONE_XIP_LSB 12 +#define PSM_DONE_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM5 +// Description : None +#define PSM_DONE_SRAM5_RESET 0x0 +#define PSM_DONE_SRAM5_BITS 0x00000800 +#define PSM_DONE_SRAM5_MSB 11 +#define PSM_DONE_SRAM5_LSB 11 +#define PSM_DONE_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM4 +// Description : None +#define PSM_DONE_SRAM4_RESET 0x0 +#define PSM_DONE_SRAM4_BITS 0x00000400 +#define PSM_DONE_SRAM4_MSB 10 +#define PSM_DONE_SRAM4_LSB 10 +#define PSM_DONE_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM3 +// Description : None +#define PSM_DONE_SRAM3_RESET 0x0 +#define PSM_DONE_SRAM3_BITS 0x00000200 +#define PSM_DONE_SRAM3_MSB 9 +#define PSM_DONE_SRAM3_LSB 9 +#define PSM_DONE_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM2 +// Description : None +#define PSM_DONE_SRAM2_RESET 0x0 +#define PSM_DONE_SRAM2_BITS 0x00000100 +#define PSM_DONE_SRAM2_MSB 8 +#define PSM_DONE_SRAM2_LSB 8 +#define PSM_DONE_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM1 +// Description : None +#define PSM_DONE_SRAM1_RESET 0x0 +#define PSM_DONE_SRAM1_BITS 0x00000080 +#define PSM_DONE_SRAM1_MSB 7 +#define PSM_DONE_SRAM1_LSB 7 +#define PSM_DONE_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM0 +// Description : None +#define PSM_DONE_SRAM0_RESET 0x0 +#define PSM_DONE_SRAM0_BITS 0x00000040 +#define PSM_DONE_SRAM0_MSB 6 +#define PSM_DONE_SRAM0_LSB 6 +#define PSM_DONE_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROM +// Description : None +#define PSM_DONE_ROM_RESET 0x0 +#define PSM_DONE_ROM_BITS 0x00000020 +#define PSM_DONE_ROM_MSB 5 +#define PSM_DONE_ROM_LSB 5 +#define PSM_DONE_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BUSFABRIC +// Description : None +#define PSM_DONE_BUSFABRIC_RESET 0x0 +#define PSM_DONE_BUSFABRIC_BITS 0x00000010 +#define PSM_DONE_BUSFABRIC_MSB 4 +#define PSM_DONE_BUSFABRIC_LSB 4 +#define PSM_DONE_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_RESETS +// Description : None +#define PSM_DONE_RESETS_RESET 0x0 +#define PSM_DONE_RESETS_BITS 0x00000008 +#define PSM_DONE_RESETS_MSB 3 +#define PSM_DONE_RESETS_LSB 3 +#define PSM_DONE_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_CLOCKS +// Description : None +#define PSM_DONE_CLOCKS_RESET 0x0 +#define PSM_DONE_CLOCKS_BITS 0x00000004 +#define PSM_DONE_CLOCKS_MSB 2 +#define PSM_DONE_CLOCKS_LSB 2 +#define PSM_DONE_CLOCKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XOSC +// Description : None +#define PSM_DONE_XOSC_RESET 0x0 +#define PSM_DONE_XOSC_BITS 0x00000002 +#define PSM_DONE_XOSC_MSB 1 +#define PSM_DONE_XOSC_LSB 1 +#define PSM_DONE_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROSC +// Description : None +#define PSM_DONE_ROSC_RESET 0x0 +#define PSM_DONE_ROSC_BITS 0x00000001 +#define PSM_DONE_ROSC_MSB 0 +#define PSM_DONE_ROSC_LSB 0 +#define PSM_DONE_ROSC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PSM_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h new file mode 100644 index 00000000000..01e2e5c21fc --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h @@ -0,0 +1,1505 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PWM +// Version : 1 +// Bus type : apb +// Description : Simple PWM +// ============================================================================= +#ifndef HARDWARE_REGS_PWM_DEFINED +#define HARDWARE_REGS_PWM_DEFINED +// ============================================================================= +// Register : PWM_CH0_CSR +// Description : Control and status register +#define PWM_CH0_CSR_OFFSET 0x00000000 +#define PWM_CH0_CSR_BITS 0x000000ff +#define PWM_CH0_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH0_CSR_PH_ADV_RESET 0x0 +#define PWM_CH0_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH0_CSR_PH_ADV_MSB 7 +#define PWM_CH0_CSR_PH_ADV_LSB 7 +#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH0_CSR_PH_RET_RESET 0x0 +#define PWM_CH0_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH0_CSR_PH_RET_MSB 6 +#define PWM_CH0_CSR_PH_RET_LSB 6 +#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH0_CSR_DIVMODE_RESET 0x0 +#define PWM_CH0_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH0_CSR_DIVMODE_MSB 5 +#define PWM_CH0_CSR_DIVMODE_LSB 4 +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_B_INV +// Description : Invert output B +#define PWM_CH0_CSR_B_INV_RESET 0x0 +#define PWM_CH0_CSR_B_INV_BITS 0x00000008 +#define PWM_CH0_CSR_B_INV_MSB 3 +#define PWM_CH0_CSR_B_INV_LSB 3 +#define PWM_CH0_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_A_INV +// Description : Invert output A +#define PWM_CH0_CSR_A_INV_RESET 0x0 +#define PWM_CH0_CSR_A_INV_BITS 0x00000004 +#define PWM_CH0_CSR_A_INV_MSB 2 +#define PWM_CH0_CSR_A_INV_LSB 2 +#define PWM_CH0_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH0_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH0_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH0_CSR_PH_CORRECT_MSB 1 +#define PWM_CH0_CSR_PH_CORRECT_LSB 1 +#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH0_CSR_EN_RESET 0x0 +#define PWM_CH0_CSR_EN_BITS 0x00000001 +#define PWM_CH0_CSR_EN_MSB 0 +#define PWM_CH0_CSR_EN_LSB 0 +#define PWM_CH0_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH0_DIV_OFFSET 0x00000004 +#define PWM_CH0_DIV_BITS 0x00000fff +#define PWM_CH0_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_INT +// Description : None +#define PWM_CH0_DIV_INT_RESET 0x01 +#define PWM_CH0_DIV_INT_BITS 0x00000ff0 +#define PWM_CH0_DIV_INT_MSB 11 +#define PWM_CH0_DIV_INT_LSB 4 +#define PWM_CH0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_FRAC +// Description : None +#define PWM_CH0_DIV_FRAC_RESET 0x0 +#define PWM_CH0_DIV_FRAC_BITS 0x0000000f +#define PWM_CH0_DIV_FRAC_MSB 3 +#define PWM_CH0_DIV_FRAC_LSB 0 +#define PWM_CH0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CTR +// Description : Direct access to the PWM counter +#define PWM_CH0_CTR_OFFSET 0x00000008 +#define PWM_CH0_CTR_BITS 0x0000ffff +#define PWM_CH0_CTR_RESET 0x00000000 +#define PWM_CH0_CTR_MSB 15 +#define PWM_CH0_CTR_LSB 0 +#define PWM_CH0_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CC +// Description : Counter compare values +#define PWM_CH0_CC_OFFSET 0x0000000c +#define PWM_CH0_CC_BITS 0xffffffff +#define PWM_CH0_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_B +// Description : None +#define PWM_CH0_CC_B_RESET 0x0000 +#define PWM_CH0_CC_B_BITS 0xffff0000 +#define PWM_CH0_CC_B_MSB 31 +#define PWM_CH0_CC_B_LSB 16 +#define PWM_CH0_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_A +// Description : None +#define PWM_CH0_CC_A_RESET 0x0000 +#define PWM_CH0_CC_A_BITS 0x0000ffff +#define PWM_CH0_CC_A_MSB 15 +#define PWM_CH0_CC_A_LSB 0 +#define PWM_CH0_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_TOP +// Description : Counter wrap value +#define PWM_CH0_TOP_OFFSET 0x00000010 +#define PWM_CH0_TOP_BITS 0x0000ffff +#define PWM_CH0_TOP_RESET 0x0000ffff +#define PWM_CH0_TOP_MSB 15 +#define PWM_CH0_TOP_LSB 0 +#define PWM_CH0_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CSR +// Description : Control and status register +#define PWM_CH1_CSR_OFFSET 0x00000014 +#define PWM_CH1_CSR_BITS 0x000000ff +#define PWM_CH1_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH1_CSR_PH_ADV_RESET 0x0 +#define PWM_CH1_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH1_CSR_PH_ADV_MSB 7 +#define PWM_CH1_CSR_PH_ADV_LSB 7 +#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH1_CSR_PH_RET_RESET 0x0 +#define PWM_CH1_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH1_CSR_PH_RET_MSB 6 +#define PWM_CH1_CSR_PH_RET_LSB 6 +#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH1_CSR_DIVMODE_RESET 0x0 +#define PWM_CH1_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH1_CSR_DIVMODE_MSB 5 +#define PWM_CH1_CSR_DIVMODE_LSB 4 +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_B_INV +// Description : Invert output B +#define PWM_CH1_CSR_B_INV_RESET 0x0 +#define PWM_CH1_CSR_B_INV_BITS 0x00000008 +#define PWM_CH1_CSR_B_INV_MSB 3 +#define PWM_CH1_CSR_B_INV_LSB 3 +#define PWM_CH1_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_A_INV +// Description : Invert output A +#define PWM_CH1_CSR_A_INV_RESET 0x0 +#define PWM_CH1_CSR_A_INV_BITS 0x00000004 +#define PWM_CH1_CSR_A_INV_MSB 2 +#define PWM_CH1_CSR_A_INV_LSB 2 +#define PWM_CH1_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH1_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH1_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH1_CSR_PH_CORRECT_MSB 1 +#define PWM_CH1_CSR_PH_CORRECT_LSB 1 +#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH1_CSR_EN_RESET 0x0 +#define PWM_CH1_CSR_EN_BITS 0x00000001 +#define PWM_CH1_CSR_EN_MSB 0 +#define PWM_CH1_CSR_EN_LSB 0 +#define PWM_CH1_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH1_DIV_OFFSET 0x00000018 +#define PWM_CH1_DIV_BITS 0x00000fff +#define PWM_CH1_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_INT +// Description : None +#define PWM_CH1_DIV_INT_RESET 0x01 +#define PWM_CH1_DIV_INT_BITS 0x00000ff0 +#define PWM_CH1_DIV_INT_MSB 11 +#define PWM_CH1_DIV_INT_LSB 4 +#define PWM_CH1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_FRAC +// Description : None +#define PWM_CH1_DIV_FRAC_RESET 0x0 +#define PWM_CH1_DIV_FRAC_BITS 0x0000000f +#define PWM_CH1_DIV_FRAC_MSB 3 +#define PWM_CH1_DIV_FRAC_LSB 0 +#define PWM_CH1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CTR +// Description : Direct access to the PWM counter +#define PWM_CH1_CTR_OFFSET 0x0000001c +#define PWM_CH1_CTR_BITS 0x0000ffff +#define PWM_CH1_CTR_RESET 0x00000000 +#define PWM_CH1_CTR_MSB 15 +#define PWM_CH1_CTR_LSB 0 +#define PWM_CH1_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CC +// Description : Counter compare values +#define PWM_CH1_CC_OFFSET 0x00000020 +#define PWM_CH1_CC_BITS 0xffffffff +#define PWM_CH1_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_B +// Description : None +#define PWM_CH1_CC_B_RESET 0x0000 +#define PWM_CH1_CC_B_BITS 0xffff0000 +#define PWM_CH1_CC_B_MSB 31 +#define PWM_CH1_CC_B_LSB 16 +#define PWM_CH1_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_A +// Description : None +#define PWM_CH1_CC_A_RESET 0x0000 +#define PWM_CH1_CC_A_BITS 0x0000ffff +#define PWM_CH1_CC_A_MSB 15 +#define PWM_CH1_CC_A_LSB 0 +#define PWM_CH1_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_TOP +// Description : Counter wrap value +#define PWM_CH1_TOP_OFFSET 0x00000024 +#define PWM_CH1_TOP_BITS 0x0000ffff +#define PWM_CH1_TOP_RESET 0x0000ffff +#define PWM_CH1_TOP_MSB 15 +#define PWM_CH1_TOP_LSB 0 +#define PWM_CH1_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CSR +// Description : Control and status register +#define PWM_CH2_CSR_OFFSET 0x00000028 +#define PWM_CH2_CSR_BITS 0x000000ff +#define PWM_CH2_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH2_CSR_PH_ADV_RESET 0x0 +#define PWM_CH2_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH2_CSR_PH_ADV_MSB 7 +#define PWM_CH2_CSR_PH_ADV_LSB 7 +#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH2_CSR_PH_RET_RESET 0x0 +#define PWM_CH2_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH2_CSR_PH_RET_MSB 6 +#define PWM_CH2_CSR_PH_RET_LSB 6 +#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH2_CSR_DIVMODE_RESET 0x0 +#define PWM_CH2_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH2_CSR_DIVMODE_MSB 5 +#define PWM_CH2_CSR_DIVMODE_LSB 4 +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_B_INV +// Description : Invert output B +#define PWM_CH2_CSR_B_INV_RESET 0x0 +#define PWM_CH2_CSR_B_INV_BITS 0x00000008 +#define PWM_CH2_CSR_B_INV_MSB 3 +#define PWM_CH2_CSR_B_INV_LSB 3 +#define PWM_CH2_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_A_INV +// Description : Invert output A +#define PWM_CH2_CSR_A_INV_RESET 0x0 +#define PWM_CH2_CSR_A_INV_BITS 0x00000004 +#define PWM_CH2_CSR_A_INV_MSB 2 +#define PWM_CH2_CSR_A_INV_LSB 2 +#define PWM_CH2_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH2_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH2_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH2_CSR_PH_CORRECT_MSB 1 +#define PWM_CH2_CSR_PH_CORRECT_LSB 1 +#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH2_CSR_EN_RESET 0x0 +#define PWM_CH2_CSR_EN_BITS 0x00000001 +#define PWM_CH2_CSR_EN_MSB 0 +#define PWM_CH2_CSR_EN_LSB 0 +#define PWM_CH2_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH2_DIV_OFFSET 0x0000002c +#define PWM_CH2_DIV_BITS 0x00000fff +#define PWM_CH2_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_INT +// Description : None +#define PWM_CH2_DIV_INT_RESET 0x01 +#define PWM_CH2_DIV_INT_BITS 0x00000ff0 +#define PWM_CH2_DIV_INT_MSB 11 +#define PWM_CH2_DIV_INT_LSB 4 +#define PWM_CH2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_FRAC +// Description : None +#define PWM_CH2_DIV_FRAC_RESET 0x0 +#define PWM_CH2_DIV_FRAC_BITS 0x0000000f +#define PWM_CH2_DIV_FRAC_MSB 3 +#define PWM_CH2_DIV_FRAC_LSB 0 +#define PWM_CH2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CTR +// Description : Direct access to the PWM counter +#define PWM_CH2_CTR_OFFSET 0x00000030 +#define PWM_CH2_CTR_BITS 0x0000ffff +#define PWM_CH2_CTR_RESET 0x00000000 +#define PWM_CH2_CTR_MSB 15 +#define PWM_CH2_CTR_LSB 0 +#define PWM_CH2_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CC +// Description : Counter compare values +#define PWM_CH2_CC_OFFSET 0x00000034 +#define PWM_CH2_CC_BITS 0xffffffff +#define PWM_CH2_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_B +// Description : None +#define PWM_CH2_CC_B_RESET 0x0000 +#define PWM_CH2_CC_B_BITS 0xffff0000 +#define PWM_CH2_CC_B_MSB 31 +#define PWM_CH2_CC_B_LSB 16 +#define PWM_CH2_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_A +// Description : None +#define PWM_CH2_CC_A_RESET 0x0000 +#define PWM_CH2_CC_A_BITS 0x0000ffff +#define PWM_CH2_CC_A_MSB 15 +#define PWM_CH2_CC_A_LSB 0 +#define PWM_CH2_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_TOP +// Description : Counter wrap value +#define PWM_CH2_TOP_OFFSET 0x00000038 +#define PWM_CH2_TOP_BITS 0x0000ffff +#define PWM_CH2_TOP_RESET 0x0000ffff +#define PWM_CH2_TOP_MSB 15 +#define PWM_CH2_TOP_LSB 0 +#define PWM_CH2_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CSR +// Description : Control and status register +#define PWM_CH3_CSR_OFFSET 0x0000003c +#define PWM_CH3_CSR_BITS 0x000000ff +#define PWM_CH3_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH3_CSR_PH_ADV_RESET 0x0 +#define PWM_CH3_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH3_CSR_PH_ADV_MSB 7 +#define PWM_CH3_CSR_PH_ADV_LSB 7 +#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH3_CSR_PH_RET_RESET 0x0 +#define PWM_CH3_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH3_CSR_PH_RET_MSB 6 +#define PWM_CH3_CSR_PH_RET_LSB 6 +#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH3_CSR_DIVMODE_RESET 0x0 +#define PWM_CH3_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH3_CSR_DIVMODE_MSB 5 +#define PWM_CH3_CSR_DIVMODE_LSB 4 +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_B_INV +// Description : Invert output B +#define PWM_CH3_CSR_B_INV_RESET 0x0 +#define PWM_CH3_CSR_B_INV_BITS 0x00000008 +#define PWM_CH3_CSR_B_INV_MSB 3 +#define PWM_CH3_CSR_B_INV_LSB 3 +#define PWM_CH3_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_A_INV +// Description : Invert output A +#define PWM_CH3_CSR_A_INV_RESET 0x0 +#define PWM_CH3_CSR_A_INV_BITS 0x00000004 +#define PWM_CH3_CSR_A_INV_MSB 2 +#define PWM_CH3_CSR_A_INV_LSB 2 +#define PWM_CH3_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH3_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH3_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH3_CSR_PH_CORRECT_MSB 1 +#define PWM_CH3_CSR_PH_CORRECT_LSB 1 +#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH3_CSR_EN_RESET 0x0 +#define PWM_CH3_CSR_EN_BITS 0x00000001 +#define PWM_CH3_CSR_EN_MSB 0 +#define PWM_CH3_CSR_EN_LSB 0 +#define PWM_CH3_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH3_DIV_OFFSET 0x00000040 +#define PWM_CH3_DIV_BITS 0x00000fff +#define PWM_CH3_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_INT +// Description : None +#define PWM_CH3_DIV_INT_RESET 0x01 +#define PWM_CH3_DIV_INT_BITS 0x00000ff0 +#define PWM_CH3_DIV_INT_MSB 11 +#define PWM_CH3_DIV_INT_LSB 4 +#define PWM_CH3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_FRAC +// Description : None +#define PWM_CH3_DIV_FRAC_RESET 0x0 +#define PWM_CH3_DIV_FRAC_BITS 0x0000000f +#define PWM_CH3_DIV_FRAC_MSB 3 +#define PWM_CH3_DIV_FRAC_LSB 0 +#define PWM_CH3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CTR +// Description : Direct access to the PWM counter +#define PWM_CH3_CTR_OFFSET 0x00000044 +#define PWM_CH3_CTR_BITS 0x0000ffff +#define PWM_CH3_CTR_RESET 0x00000000 +#define PWM_CH3_CTR_MSB 15 +#define PWM_CH3_CTR_LSB 0 +#define PWM_CH3_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CC +// Description : Counter compare values +#define PWM_CH3_CC_OFFSET 0x00000048 +#define PWM_CH3_CC_BITS 0xffffffff +#define PWM_CH3_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_B +// Description : None +#define PWM_CH3_CC_B_RESET 0x0000 +#define PWM_CH3_CC_B_BITS 0xffff0000 +#define PWM_CH3_CC_B_MSB 31 +#define PWM_CH3_CC_B_LSB 16 +#define PWM_CH3_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_A +// Description : None +#define PWM_CH3_CC_A_RESET 0x0000 +#define PWM_CH3_CC_A_BITS 0x0000ffff +#define PWM_CH3_CC_A_MSB 15 +#define PWM_CH3_CC_A_LSB 0 +#define PWM_CH3_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_TOP +// Description : Counter wrap value +#define PWM_CH3_TOP_OFFSET 0x0000004c +#define PWM_CH3_TOP_BITS 0x0000ffff +#define PWM_CH3_TOP_RESET 0x0000ffff +#define PWM_CH3_TOP_MSB 15 +#define PWM_CH3_TOP_LSB 0 +#define PWM_CH3_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CSR +// Description : Control and status register +#define PWM_CH4_CSR_OFFSET 0x00000050 +#define PWM_CH4_CSR_BITS 0x000000ff +#define PWM_CH4_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH4_CSR_PH_ADV_RESET 0x0 +#define PWM_CH4_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH4_CSR_PH_ADV_MSB 7 +#define PWM_CH4_CSR_PH_ADV_LSB 7 +#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH4_CSR_PH_RET_RESET 0x0 +#define PWM_CH4_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH4_CSR_PH_RET_MSB 6 +#define PWM_CH4_CSR_PH_RET_LSB 6 +#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH4_CSR_DIVMODE_RESET 0x0 +#define PWM_CH4_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH4_CSR_DIVMODE_MSB 5 +#define PWM_CH4_CSR_DIVMODE_LSB 4 +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_B_INV +// Description : Invert output B +#define PWM_CH4_CSR_B_INV_RESET 0x0 +#define PWM_CH4_CSR_B_INV_BITS 0x00000008 +#define PWM_CH4_CSR_B_INV_MSB 3 +#define PWM_CH4_CSR_B_INV_LSB 3 +#define PWM_CH4_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_A_INV +// Description : Invert output A +#define PWM_CH4_CSR_A_INV_RESET 0x0 +#define PWM_CH4_CSR_A_INV_BITS 0x00000004 +#define PWM_CH4_CSR_A_INV_MSB 2 +#define PWM_CH4_CSR_A_INV_LSB 2 +#define PWM_CH4_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH4_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH4_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH4_CSR_PH_CORRECT_MSB 1 +#define PWM_CH4_CSR_PH_CORRECT_LSB 1 +#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH4_CSR_EN_RESET 0x0 +#define PWM_CH4_CSR_EN_BITS 0x00000001 +#define PWM_CH4_CSR_EN_MSB 0 +#define PWM_CH4_CSR_EN_LSB 0 +#define PWM_CH4_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH4_DIV_OFFSET 0x00000054 +#define PWM_CH4_DIV_BITS 0x00000fff +#define PWM_CH4_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_INT +// Description : None +#define PWM_CH4_DIV_INT_RESET 0x01 +#define PWM_CH4_DIV_INT_BITS 0x00000ff0 +#define PWM_CH4_DIV_INT_MSB 11 +#define PWM_CH4_DIV_INT_LSB 4 +#define PWM_CH4_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_FRAC +// Description : None +#define PWM_CH4_DIV_FRAC_RESET 0x0 +#define PWM_CH4_DIV_FRAC_BITS 0x0000000f +#define PWM_CH4_DIV_FRAC_MSB 3 +#define PWM_CH4_DIV_FRAC_LSB 0 +#define PWM_CH4_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CTR +// Description : Direct access to the PWM counter +#define PWM_CH4_CTR_OFFSET 0x00000058 +#define PWM_CH4_CTR_BITS 0x0000ffff +#define PWM_CH4_CTR_RESET 0x00000000 +#define PWM_CH4_CTR_MSB 15 +#define PWM_CH4_CTR_LSB 0 +#define PWM_CH4_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CC +// Description : Counter compare values +#define PWM_CH4_CC_OFFSET 0x0000005c +#define PWM_CH4_CC_BITS 0xffffffff +#define PWM_CH4_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_B +// Description : None +#define PWM_CH4_CC_B_RESET 0x0000 +#define PWM_CH4_CC_B_BITS 0xffff0000 +#define PWM_CH4_CC_B_MSB 31 +#define PWM_CH4_CC_B_LSB 16 +#define PWM_CH4_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_A +// Description : None +#define PWM_CH4_CC_A_RESET 0x0000 +#define PWM_CH4_CC_A_BITS 0x0000ffff +#define PWM_CH4_CC_A_MSB 15 +#define PWM_CH4_CC_A_LSB 0 +#define PWM_CH4_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_TOP +// Description : Counter wrap value +#define PWM_CH4_TOP_OFFSET 0x00000060 +#define PWM_CH4_TOP_BITS 0x0000ffff +#define PWM_CH4_TOP_RESET 0x0000ffff +#define PWM_CH4_TOP_MSB 15 +#define PWM_CH4_TOP_LSB 0 +#define PWM_CH4_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CSR +// Description : Control and status register +#define PWM_CH5_CSR_OFFSET 0x00000064 +#define PWM_CH5_CSR_BITS 0x000000ff +#define PWM_CH5_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH5_CSR_PH_ADV_RESET 0x0 +#define PWM_CH5_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH5_CSR_PH_ADV_MSB 7 +#define PWM_CH5_CSR_PH_ADV_LSB 7 +#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH5_CSR_PH_RET_RESET 0x0 +#define PWM_CH5_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH5_CSR_PH_RET_MSB 6 +#define PWM_CH5_CSR_PH_RET_LSB 6 +#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH5_CSR_DIVMODE_RESET 0x0 +#define PWM_CH5_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH5_CSR_DIVMODE_MSB 5 +#define PWM_CH5_CSR_DIVMODE_LSB 4 +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_B_INV +// Description : Invert output B +#define PWM_CH5_CSR_B_INV_RESET 0x0 +#define PWM_CH5_CSR_B_INV_BITS 0x00000008 +#define PWM_CH5_CSR_B_INV_MSB 3 +#define PWM_CH5_CSR_B_INV_LSB 3 +#define PWM_CH5_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_A_INV +// Description : Invert output A +#define PWM_CH5_CSR_A_INV_RESET 0x0 +#define PWM_CH5_CSR_A_INV_BITS 0x00000004 +#define PWM_CH5_CSR_A_INV_MSB 2 +#define PWM_CH5_CSR_A_INV_LSB 2 +#define PWM_CH5_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH5_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH5_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH5_CSR_PH_CORRECT_MSB 1 +#define PWM_CH5_CSR_PH_CORRECT_LSB 1 +#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH5_CSR_EN_RESET 0x0 +#define PWM_CH5_CSR_EN_BITS 0x00000001 +#define PWM_CH5_CSR_EN_MSB 0 +#define PWM_CH5_CSR_EN_LSB 0 +#define PWM_CH5_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH5_DIV_OFFSET 0x00000068 +#define PWM_CH5_DIV_BITS 0x00000fff +#define PWM_CH5_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_INT +// Description : None +#define PWM_CH5_DIV_INT_RESET 0x01 +#define PWM_CH5_DIV_INT_BITS 0x00000ff0 +#define PWM_CH5_DIV_INT_MSB 11 +#define PWM_CH5_DIV_INT_LSB 4 +#define PWM_CH5_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_FRAC +// Description : None +#define PWM_CH5_DIV_FRAC_RESET 0x0 +#define PWM_CH5_DIV_FRAC_BITS 0x0000000f +#define PWM_CH5_DIV_FRAC_MSB 3 +#define PWM_CH5_DIV_FRAC_LSB 0 +#define PWM_CH5_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CTR +// Description : Direct access to the PWM counter +#define PWM_CH5_CTR_OFFSET 0x0000006c +#define PWM_CH5_CTR_BITS 0x0000ffff +#define PWM_CH5_CTR_RESET 0x00000000 +#define PWM_CH5_CTR_MSB 15 +#define PWM_CH5_CTR_LSB 0 +#define PWM_CH5_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CC +// Description : Counter compare values +#define PWM_CH5_CC_OFFSET 0x00000070 +#define PWM_CH5_CC_BITS 0xffffffff +#define PWM_CH5_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_B +// Description : None +#define PWM_CH5_CC_B_RESET 0x0000 +#define PWM_CH5_CC_B_BITS 0xffff0000 +#define PWM_CH5_CC_B_MSB 31 +#define PWM_CH5_CC_B_LSB 16 +#define PWM_CH5_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_A +// Description : None +#define PWM_CH5_CC_A_RESET 0x0000 +#define PWM_CH5_CC_A_BITS 0x0000ffff +#define PWM_CH5_CC_A_MSB 15 +#define PWM_CH5_CC_A_LSB 0 +#define PWM_CH5_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_TOP +// Description : Counter wrap value +#define PWM_CH5_TOP_OFFSET 0x00000074 +#define PWM_CH5_TOP_BITS 0x0000ffff +#define PWM_CH5_TOP_RESET 0x0000ffff +#define PWM_CH5_TOP_MSB 15 +#define PWM_CH5_TOP_LSB 0 +#define PWM_CH5_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CSR +// Description : Control and status register +#define PWM_CH6_CSR_OFFSET 0x00000078 +#define PWM_CH6_CSR_BITS 0x000000ff +#define PWM_CH6_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH6_CSR_PH_ADV_RESET 0x0 +#define PWM_CH6_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH6_CSR_PH_ADV_MSB 7 +#define PWM_CH6_CSR_PH_ADV_LSB 7 +#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH6_CSR_PH_RET_RESET 0x0 +#define PWM_CH6_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH6_CSR_PH_RET_MSB 6 +#define PWM_CH6_CSR_PH_RET_LSB 6 +#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH6_CSR_DIVMODE_RESET 0x0 +#define PWM_CH6_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH6_CSR_DIVMODE_MSB 5 +#define PWM_CH6_CSR_DIVMODE_LSB 4 +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_B_INV +// Description : Invert output B +#define PWM_CH6_CSR_B_INV_RESET 0x0 +#define PWM_CH6_CSR_B_INV_BITS 0x00000008 +#define PWM_CH6_CSR_B_INV_MSB 3 +#define PWM_CH6_CSR_B_INV_LSB 3 +#define PWM_CH6_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_A_INV +// Description : Invert output A +#define PWM_CH6_CSR_A_INV_RESET 0x0 +#define PWM_CH6_CSR_A_INV_BITS 0x00000004 +#define PWM_CH6_CSR_A_INV_MSB 2 +#define PWM_CH6_CSR_A_INV_LSB 2 +#define PWM_CH6_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH6_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH6_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH6_CSR_PH_CORRECT_MSB 1 +#define PWM_CH6_CSR_PH_CORRECT_LSB 1 +#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH6_CSR_EN_RESET 0x0 +#define PWM_CH6_CSR_EN_BITS 0x00000001 +#define PWM_CH6_CSR_EN_MSB 0 +#define PWM_CH6_CSR_EN_LSB 0 +#define PWM_CH6_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH6_DIV_OFFSET 0x0000007c +#define PWM_CH6_DIV_BITS 0x00000fff +#define PWM_CH6_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_INT +// Description : None +#define PWM_CH6_DIV_INT_RESET 0x01 +#define PWM_CH6_DIV_INT_BITS 0x00000ff0 +#define PWM_CH6_DIV_INT_MSB 11 +#define PWM_CH6_DIV_INT_LSB 4 +#define PWM_CH6_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_FRAC +// Description : None +#define PWM_CH6_DIV_FRAC_RESET 0x0 +#define PWM_CH6_DIV_FRAC_BITS 0x0000000f +#define PWM_CH6_DIV_FRAC_MSB 3 +#define PWM_CH6_DIV_FRAC_LSB 0 +#define PWM_CH6_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CTR +// Description : Direct access to the PWM counter +#define PWM_CH6_CTR_OFFSET 0x00000080 +#define PWM_CH6_CTR_BITS 0x0000ffff +#define PWM_CH6_CTR_RESET 0x00000000 +#define PWM_CH6_CTR_MSB 15 +#define PWM_CH6_CTR_LSB 0 +#define PWM_CH6_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CC +// Description : Counter compare values +#define PWM_CH6_CC_OFFSET 0x00000084 +#define PWM_CH6_CC_BITS 0xffffffff +#define PWM_CH6_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_B +// Description : None +#define PWM_CH6_CC_B_RESET 0x0000 +#define PWM_CH6_CC_B_BITS 0xffff0000 +#define PWM_CH6_CC_B_MSB 31 +#define PWM_CH6_CC_B_LSB 16 +#define PWM_CH6_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_A +// Description : None +#define PWM_CH6_CC_A_RESET 0x0000 +#define PWM_CH6_CC_A_BITS 0x0000ffff +#define PWM_CH6_CC_A_MSB 15 +#define PWM_CH6_CC_A_LSB 0 +#define PWM_CH6_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_TOP +// Description : Counter wrap value +#define PWM_CH6_TOP_OFFSET 0x00000088 +#define PWM_CH6_TOP_BITS 0x0000ffff +#define PWM_CH6_TOP_RESET 0x0000ffff +#define PWM_CH6_TOP_MSB 15 +#define PWM_CH6_TOP_LSB 0 +#define PWM_CH6_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CSR +// Description : Control and status register +#define PWM_CH7_CSR_OFFSET 0x0000008c +#define PWM_CH7_CSR_BITS 0x000000ff +#define PWM_CH7_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH7_CSR_PH_ADV_RESET 0x0 +#define PWM_CH7_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH7_CSR_PH_ADV_MSB 7 +#define PWM_CH7_CSR_PH_ADV_LSB 7 +#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH7_CSR_PH_RET_RESET 0x0 +#define PWM_CH7_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH7_CSR_PH_RET_MSB 6 +#define PWM_CH7_CSR_PH_RET_LSB 6 +#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH7_CSR_DIVMODE_RESET 0x0 +#define PWM_CH7_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH7_CSR_DIVMODE_MSB 5 +#define PWM_CH7_CSR_DIVMODE_LSB 4 +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_B_INV +// Description : Invert output B +#define PWM_CH7_CSR_B_INV_RESET 0x0 +#define PWM_CH7_CSR_B_INV_BITS 0x00000008 +#define PWM_CH7_CSR_B_INV_MSB 3 +#define PWM_CH7_CSR_B_INV_LSB 3 +#define PWM_CH7_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_A_INV +// Description : Invert output A +#define PWM_CH7_CSR_A_INV_RESET 0x0 +#define PWM_CH7_CSR_A_INV_BITS 0x00000004 +#define PWM_CH7_CSR_A_INV_MSB 2 +#define PWM_CH7_CSR_A_INV_LSB 2 +#define PWM_CH7_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH7_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH7_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH7_CSR_PH_CORRECT_MSB 1 +#define PWM_CH7_CSR_PH_CORRECT_LSB 1 +#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH7_CSR_EN_RESET 0x0 +#define PWM_CH7_CSR_EN_BITS 0x00000001 +#define PWM_CH7_CSR_EN_MSB 0 +#define PWM_CH7_CSR_EN_LSB 0 +#define PWM_CH7_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH7_DIV_OFFSET 0x00000090 +#define PWM_CH7_DIV_BITS 0x00000fff +#define PWM_CH7_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_INT +// Description : None +#define PWM_CH7_DIV_INT_RESET 0x01 +#define PWM_CH7_DIV_INT_BITS 0x00000ff0 +#define PWM_CH7_DIV_INT_MSB 11 +#define PWM_CH7_DIV_INT_LSB 4 +#define PWM_CH7_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_FRAC +// Description : None +#define PWM_CH7_DIV_FRAC_RESET 0x0 +#define PWM_CH7_DIV_FRAC_BITS 0x0000000f +#define PWM_CH7_DIV_FRAC_MSB 3 +#define PWM_CH7_DIV_FRAC_LSB 0 +#define PWM_CH7_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CTR +// Description : Direct access to the PWM counter +#define PWM_CH7_CTR_OFFSET 0x00000094 +#define PWM_CH7_CTR_BITS 0x0000ffff +#define PWM_CH7_CTR_RESET 0x00000000 +#define PWM_CH7_CTR_MSB 15 +#define PWM_CH7_CTR_LSB 0 +#define PWM_CH7_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CC +// Description : Counter compare values +#define PWM_CH7_CC_OFFSET 0x00000098 +#define PWM_CH7_CC_BITS 0xffffffff +#define PWM_CH7_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_B +// Description : None +#define PWM_CH7_CC_B_RESET 0x0000 +#define PWM_CH7_CC_B_BITS 0xffff0000 +#define PWM_CH7_CC_B_MSB 31 +#define PWM_CH7_CC_B_LSB 16 +#define PWM_CH7_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_A +// Description : None +#define PWM_CH7_CC_A_RESET 0x0000 +#define PWM_CH7_CC_A_BITS 0x0000ffff +#define PWM_CH7_CC_A_MSB 15 +#define PWM_CH7_CC_A_LSB 0 +#define PWM_CH7_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_TOP +// Description : Counter wrap value +#define PWM_CH7_TOP_OFFSET 0x0000009c +#define PWM_CH7_TOP_BITS 0x0000ffff +#define PWM_CH7_TOP_RESET 0x0000ffff +#define PWM_CH7_TOP_MSB 15 +#define PWM_CH7_TOP_LSB 0 +#define PWM_CH7_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_EN +// Description : This register aliases the CSR_EN bits for all channels. +// Writing to this register allows multiple channels to be enabled +// or disabled simultaneously, so they can run in perfect sync. +// For each channel, there is only one physical EN register bit, +// which can be accessed through here or CHx_CSR. +#define PWM_EN_OFFSET 0x000000a0 +#define PWM_EN_BITS 0x000000ff +#define PWM_EN_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH7 +// Description : None +#define PWM_EN_CH7_RESET 0x0 +#define PWM_EN_CH7_BITS 0x00000080 +#define PWM_EN_CH7_MSB 7 +#define PWM_EN_CH7_LSB 7 +#define PWM_EN_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH6 +// Description : None +#define PWM_EN_CH6_RESET 0x0 +#define PWM_EN_CH6_BITS 0x00000040 +#define PWM_EN_CH6_MSB 6 +#define PWM_EN_CH6_LSB 6 +#define PWM_EN_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH5 +// Description : None +#define PWM_EN_CH5_RESET 0x0 +#define PWM_EN_CH5_BITS 0x00000020 +#define PWM_EN_CH5_MSB 5 +#define PWM_EN_CH5_LSB 5 +#define PWM_EN_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH4 +// Description : None +#define PWM_EN_CH4_RESET 0x0 +#define PWM_EN_CH4_BITS 0x00000010 +#define PWM_EN_CH4_MSB 4 +#define PWM_EN_CH4_LSB 4 +#define PWM_EN_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH3 +// Description : None +#define PWM_EN_CH3_RESET 0x0 +#define PWM_EN_CH3_BITS 0x00000008 +#define PWM_EN_CH3_MSB 3 +#define PWM_EN_CH3_LSB 3 +#define PWM_EN_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH2 +// Description : None +#define PWM_EN_CH2_RESET 0x0 +#define PWM_EN_CH2_BITS 0x00000004 +#define PWM_EN_CH2_MSB 2 +#define PWM_EN_CH2_LSB 2 +#define PWM_EN_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH1 +// Description : None +#define PWM_EN_CH1_RESET 0x0 +#define PWM_EN_CH1_BITS 0x00000002 +#define PWM_EN_CH1_MSB 1 +#define PWM_EN_CH1_LSB 1 +#define PWM_EN_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH0 +// Description : None +#define PWM_EN_CH0_RESET 0x0 +#define PWM_EN_CH0_BITS 0x00000001 +#define PWM_EN_CH0_MSB 0 +#define PWM_EN_CH0_LSB 0 +#define PWM_EN_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTR +// Description : Raw Interrupts +#define PWM_INTR_OFFSET 0x000000a4 +#define PWM_INTR_BITS 0x000000ff +#define PWM_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH7 +// Description : None +#define PWM_INTR_CH7_RESET 0x0 +#define PWM_INTR_CH7_BITS 0x00000080 +#define PWM_INTR_CH7_MSB 7 +#define PWM_INTR_CH7_LSB 7 +#define PWM_INTR_CH7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH6 +// Description : None +#define PWM_INTR_CH6_RESET 0x0 +#define PWM_INTR_CH6_BITS 0x00000040 +#define PWM_INTR_CH6_MSB 6 +#define PWM_INTR_CH6_LSB 6 +#define PWM_INTR_CH6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH5 +// Description : None +#define PWM_INTR_CH5_RESET 0x0 +#define PWM_INTR_CH5_BITS 0x00000020 +#define PWM_INTR_CH5_MSB 5 +#define PWM_INTR_CH5_LSB 5 +#define PWM_INTR_CH5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH4 +// Description : None +#define PWM_INTR_CH4_RESET 0x0 +#define PWM_INTR_CH4_BITS 0x00000010 +#define PWM_INTR_CH4_MSB 4 +#define PWM_INTR_CH4_LSB 4 +#define PWM_INTR_CH4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH3 +// Description : None +#define PWM_INTR_CH3_RESET 0x0 +#define PWM_INTR_CH3_BITS 0x00000008 +#define PWM_INTR_CH3_MSB 3 +#define PWM_INTR_CH3_LSB 3 +#define PWM_INTR_CH3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH2 +// Description : None +#define PWM_INTR_CH2_RESET 0x0 +#define PWM_INTR_CH2_BITS 0x00000004 +#define PWM_INTR_CH2_MSB 2 +#define PWM_INTR_CH2_LSB 2 +#define PWM_INTR_CH2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH1 +// Description : None +#define PWM_INTR_CH1_RESET 0x0 +#define PWM_INTR_CH1_BITS 0x00000002 +#define PWM_INTR_CH1_MSB 1 +#define PWM_INTR_CH1_LSB 1 +#define PWM_INTR_CH1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH0 +// Description : None +#define PWM_INTR_CH0_RESET 0x0 +#define PWM_INTR_CH0_BITS 0x00000001 +#define PWM_INTR_CH0_MSB 0 +#define PWM_INTR_CH0_LSB 0 +#define PWM_INTR_CH0_ACCESS "WC" +// ============================================================================= +// Register : PWM_INTE +// Description : Interrupt Enable +#define PWM_INTE_OFFSET 0x000000a8 +#define PWM_INTE_BITS 0x000000ff +#define PWM_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH7 +// Description : None +#define PWM_INTE_CH7_RESET 0x0 +#define PWM_INTE_CH7_BITS 0x00000080 +#define PWM_INTE_CH7_MSB 7 +#define PWM_INTE_CH7_LSB 7 +#define PWM_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH6 +// Description : None +#define PWM_INTE_CH6_RESET 0x0 +#define PWM_INTE_CH6_BITS 0x00000040 +#define PWM_INTE_CH6_MSB 6 +#define PWM_INTE_CH6_LSB 6 +#define PWM_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH5 +// Description : None +#define PWM_INTE_CH5_RESET 0x0 +#define PWM_INTE_CH5_BITS 0x00000020 +#define PWM_INTE_CH5_MSB 5 +#define PWM_INTE_CH5_LSB 5 +#define PWM_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH4 +// Description : None +#define PWM_INTE_CH4_RESET 0x0 +#define PWM_INTE_CH4_BITS 0x00000010 +#define PWM_INTE_CH4_MSB 4 +#define PWM_INTE_CH4_LSB 4 +#define PWM_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH3 +// Description : None +#define PWM_INTE_CH3_RESET 0x0 +#define PWM_INTE_CH3_BITS 0x00000008 +#define PWM_INTE_CH3_MSB 3 +#define PWM_INTE_CH3_LSB 3 +#define PWM_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH2 +// Description : None +#define PWM_INTE_CH2_RESET 0x0 +#define PWM_INTE_CH2_BITS 0x00000004 +#define PWM_INTE_CH2_MSB 2 +#define PWM_INTE_CH2_LSB 2 +#define PWM_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH1 +// Description : None +#define PWM_INTE_CH1_RESET 0x0 +#define PWM_INTE_CH1_BITS 0x00000002 +#define PWM_INTE_CH1_MSB 1 +#define PWM_INTE_CH1_LSB 1 +#define PWM_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH0 +// Description : None +#define PWM_INTE_CH0_RESET 0x0 +#define PWM_INTE_CH0_BITS 0x00000001 +#define PWM_INTE_CH0_MSB 0 +#define PWM_INTE_CH0_LSB 0 +#define PWM_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTF +// Description : Interrupt Force +#define PWM_INTF_OFFSET 0x000000ac +#define PWM_INTF_BITS 0x000000ff +#define PWM_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH7 +// Description : None +#define PWM_INTF_CH7_RESET 0x0 +#define PWM_INTF_CH7_BITS 0x00000080 +#define PWM_INTF_CH7_MSB 7 +#define PWM_INTF_CH7_LSB 7 +#define PWM_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH6 +// Description : None +#define PWM_INTF_CH6_RESET 0x0 +#define PWM_INTF_CH6_BITS 0x00000040 +#define PWM_INTF_CH6_MSB 6 +#define PWM_INTF_CH6_LSB 6 +#define PWM_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH5 +// Description : None +#define PWM_INTF_CH5_RESET 0x0 +#define PWM_INTF_CH5_BITS 0x00000020 +#define PWM_INTF_CH5_MSB 5 +#define PWM_INTF_CH5_LSB 5 +#define PWM_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH4 +// Description : None +#define PWM_INTF_CH4_RESET 0x0 +#define PWM_INTF_CH4_BITS 0x00000010 +#define PWM_INTF_CH4_MSB 4 +#define PWM_INTF_CH4_LSB 4 +#define PWM_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH3 +// Description : None +#define PWM_INTF_CH3_RESET 0x0 +#define PWM_INTF_CH3_BITS 0x00000008 +#define PWM_INTF_CH3_MSB 3 +#define PWM_INTF_CH3_LSB 3 +#define PWM_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH2 +// Description : None +#define PWM_INTF_CH2_RESET 0x0 +#define PWM_INTF_CH2_BITS 0x00000004 +#define PWM_INTF_CH2_MSB 2 +#define PWM_INTF_CH2_LSB 2 +#define PWM_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH1 +// Description : None +#define PWM_INTF_CH1_RESET 0x0 +#define PWM_INTF_CH1_BITS 0x00000002 +#define PWM_INTF_CH1_MSB 1 +#define PWM_INTF_CH1_LSB 1 +#define PWM_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH0 +// Description : None +#define PWM_INTF_CH0_RESET 0x0 +#define PWM_INTF_CH0_BITS 0x00000001 +#define PWM_INTF_CH0_MSB 0 +#define PWM_INTF_CH0_LSB 0 +#define PWM_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTS +// Description : Interrupt status after masking & forcing +#define PWM_INTS_OFFSET 0x000000b0 +#define PWM_INTS_BITS 0x000000ff +#define PWM_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH7 +// Description : None +#define PWM_INTS_CH7_RESET 0x0 +#define PWM_INTS_CH7_BITS 0x00000080 +#define PWM_INTS_CH7_MSB 7 +#define PWM_INTS_CH7_LSB 7 +#define PWM_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH6 +// Description : None +#define PWM_INTS_CH6_RESET 0x0 +#define PWM_INTS_CH6_BITS 0x00000040 +#define PWM_INTS_CH6_MSB 6 +#define PWM_INTS_CH6_LSB 6 +#define PWM_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH5 +// Description : None +#define PWM_INTS_CH5_RESET 0x0 +#define PWM_INTS_CH5_BITS 0x00000020 +#define PWM_INTS_CH5_MSB 5 +#define PWM_INTS_CH5_LSB 5 +#define PWM_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH4 +// Description : None +#define PWM_INTS_CH4_RESET 0x0 +#define PWM_INTS_CH4_BITS 0x00000010 +#define PWM_INTS_CH4_MSB 4 +#define PWM_INTS_CH4_LSB 4 +#define PWM_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH3 +// Description : None +#define PWM_INTS_CH3_RESET 0x0 +#define PWM_INTS_CH3_BITS 0x00000008 +#define PWM_INTS_CH3_MSB 3 +#define PWM_INTS_CH3_LSB 3 +#define PWM_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH2 +// Description : None +#define PWM_INTS_CH2_RESET 0x0 +#define PWM_INTS_CH2_BITS 0x00000004 +#define PWM_INTS_CH2_MSB 2 +#define PWM_INTS_CH2_LSB 2 +#define PWM_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH1 +// Description : None +#define PWM_INTS_CH1_RESET 0x0 +#define PWM_INTS_CH1_BITS 0x00000002 +#define PWM_INTS_CH1_MSB 1 +#define PWM_INTS_CH1_LSB 1 +#define PWM_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH0 +// Description : None +#define PWM_INTS_CH0_RESET 0x0 +#define PWM_INTS_CH0_BITS 0x00000001 +#define PWM_INTS_CH0_MSB 0 +#define PWM_INTS_CH0_LSB 0 +#define PWM_INTS_CH0_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PWM_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h new file mode 100644 index 00000000000..b512350376c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h @@ -0,0 +1,637 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RESETS +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_RESETS_DEFINED +#define HARDWARE_REGS_RESETS_DEFINED +// ============================================================================= +// Register : RESETS_RESET +// Description : Reset control. If a bit is set it means the peripheral is in +// reset. 0 means the peripheral's reset is deasserted. +#define RESETS_RESET_OFFSET 0x00000000 +#define RESETS_RESET_BITS 0x01ffffff +#define RESETS_RESET_RESET 0x01ffffff +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_USBCTRL +// Description : None +#define RESETS_RESET_USBCTRL_RESET 0x1 +#define RESETS_RESET_USBCTRL_BITS 0x01000000 +#define RESETS_RESET_USBCTRL_MSB 24 +#define RESETS_RESET_USBCTRL_LSB 24 +#define RESETS_RESET_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART1 +// Description : None +#define RESETS_RESET_UART1_RESET 0x1 +#define RESETS_RESET_UART1_BITS 0x00800000 +#define RESETS_RESET_UART1_MSB 23 +#define RESETS_RESET_UART1_LSB 23 +#define RESETS_RESET_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART0 +// Description : None +#define RESETS_RESET_UART0_RESET 0x1 +#define RESETS_RESET_UART0_BITS 0x00400000 +#define RESETS_RESET_UART0_MSB 22 +#define RESETS_RESET_UART0_LSB 22 +#define RESETS_RESET_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER +// Description : None +#define RESETS_RESET_TIMER_RESET 0x1 +#define RESETS_RESET_TIMER_BITS 0x00200000 +#define RESETS_RESET_TIMER_MSB 21 +#define RESETS_RESET_TIMER_LSB 21 +#define RESETS_RESET_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TBMAN +// Description : None +#define RESETS_RESET_TBMAN_RESET 0x1 +#define RESETS_RESET_TBMAN_BITS 0x00100000 +#define RESETS_RESET_TBMAN_MSB 20 +#define RESETS_RESET_TBMAN_LSB 20 +#define RESETS_RESET_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSINFO +// Description : None +#define RESETS_RESET_SYSINFO_RESET 0x1 +#define RESETS_RESET_SYSINFO_BITS 0x00080000 +#define RESETS_RESET_SYSINFO_MSB 19 +#define RESETS_RESET_SYSINFO_LSB 19 +#define RESETS_RESET_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSCFG +// Description : None +#define RESETS_RESET_SYSCFG_RESET 0x1 +#define RESETS_RESET_SYSCFG_BITS 0x00040000 +#define RESETS_RESET_SYSCFG_MSB 18 +#define RESETS_RESET_SYSCFG_LSB 18 +#define RESETS_RESET_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI1 +// Description : None +#define RESETS_RESET_SPI1_RESET 0x1 +#define RESETS_RESET_SPI1_BITS 0x00020000 +#define RESETS_RESET_SPI1_MSB 17 +#define RESETS_RESET_SPI1_LSB 17 +#define RESETS_RESET_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI0 +// Description : None +#define RESETS_RESET_SPI0_RESET 0x1 +#define RESETS_RESET_SPI0_BITS 0x00010000 +#define RESETS_RESET_SPI0_MSB 16 +#define RESETS_RESET_SPI0_LSB 16 +#define RESETS_RESET_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_RTC +// Description : None +#define RESETS_RESET_RTC_RESET 0x1 +#define RESETS_RESET_RTC_BITS 0x00008000 +#define RESETS_RESET_RTC_MSB 15 +#define RESETS_RESET_RTC_LSB 15 +#define RESETS_RESET_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PWM +// Description : None +#define RESETS_RESET_PWM_RESET 0x1 +#define RESETS_RESET_PWM_BITS 0x00004000 +#define RESETS_RESET_PWM_MSB 14 +#define RESETS_RESET_PWM_LSB 14 +#define RESETS_RESET_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_USB +// Description : None +#define RESETS_RESET_PLL_USB_RESET 0x1 +#define RESETS_RESET_PLL_USB_BITS 0x00002000 +#define RESETS_RESET_PLL_USB_MSB 13 +#define RESETS_RESET_PLL_USB_LSB 13 +#define RESETS_RESET_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_SYS +// Description : None +#define RESETS_RESET_PLL_SYS_RESET 0x1 +#define RESETS_RESET_PLL_SYS_BITS 0x00001000 +#define RESETS_RESET_PLL_SYS_MSB 12 +#define RESETS_RESET_PLL_SYS_LSB 12 +#define RESETS_RESET_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO1 +// Description : None +#define RESETS_RESET_PIO1_RESET 0x1 +#define RESETS_RESET_PIO1_BITS 0x00000800 +#define RESETS_RESET_PIO1_MSB 11 +#define RESETS_RESET_PIO1_LSB 11 +#define RESETS_RESET_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO0 +// Description : None +#define RESETS_RESET_PIO0_RESET 0x1 +#define RESETS_RESET_PIO0_BITS 0x00000400 +#define RESETS_RESET_PIO0_MSB 10 +#define RESETS_RESET_PIO0_LSB 10 +#define RESETS_RESET_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_QSPI +// Description : None +#define RESETS_RESET_PADS_QSPI_RESET 0x1 +#define RESETS_RESET_PADS_QSPI_BITS 0x00000200 +#define RESETS_RESET_PADS_QSPI_MSB 9 +#define RESETS_RESET_PADS_QSPI_LSB 9 +#define RESETS_RESET_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_BANK0 +// Description : None +#define RESETS_RESET_PADS_BANK0_RESET 0x1 +#define RESETS_RESET_PADS_BANK0_BITS 0x00000100 +#define RESETS_RESET_PADS_BANK0_MSB 8 +#define RESETS_RESET_PADS_BANK0_LSB 8 +#define RESETS_RESET_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_JTAG +// Description : None +#define RESETS_RESET_JTAG_RESET 0x1 +#define RESETS_RESET_JTAG_BITS 0x00000080 +#define RESETS_RESET_JTAG_MSB 7 +#define RESETS_RESET_JTAG_LSB 7 +#define RESETS_RESET_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_QSPI +// Description : None +#define RESETS_RESET_IO_QSPI_RESET 0x1 +#define RESETS_RESET_IO_QSPI_BITS 0x00000040 +#define RESETS_RESET_IO_QSPI_MSB 6 +#define RESETS_RESET_IO_QSPI_LSB 6 +#define RESETS_RESET_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_BANK0 +// Description : None +#define RESETS_RESET_IO_BANK0_RESET 0x1 +#define RESETS_RESET_IO_BANK0_BITS 0x00000020 +#define RESETS_RESET_IO_BANK0_MSB 5 +#define RESETS_RESET_IO_BANK0_LSB 5 +#define RESETS_RESET_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C1 +// Description : None +#define RESETS_RESET_I2C1_RESET 0x1 +#define RESETS_RESET_I2C1_BITS 0x00000010 +#define RESETS_RESET_I2C1_MSB 4 +#define RESETS_RESET_I2C1_LSB 4 +#define RESETS_RESET_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C0 +// Description : None +#define RESETS_RESET_I2C0_RESET 0x1 +#define RESETS_RESET_I2C0_BITS 0x00000008 +#define RESETS_RESET_I2C0_MSB 3 +#define RESETS_RESET_I2C0_LSB 3 +#define RESETS_RESET_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DMA +// Description : None +#define RESETS_RESET_DMA_RESET 0x1 +#define RESETS_RESET_DMA_BITS 0x00000004 +#define RESETS_RESET_DMA_MSB 2 +#define RESETS_RESET_DMA_LSB 2 +#define RESETS_RESET_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_BUSCTRL +// Description : None +#define RESETS_RESET_BUSCTRL_RESET 0x1 +#define RESETS_RESET_BUSCTRL_BITS 0x00000002 +#define RESETS_RESET_BUSCTRL_MSB 1 +#define RESETS_RESET_BUSCTRL_LSB 1 +#define RESETS_RESET_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_ADC +// Description : None +#define RESETS_RESET_ADC_RESET 0x1 +#define RESETS_RESET_ADC_BITS 0x00000001 +#define RESETS_RESET_ADC_MSB 0 +#define RESETS_RESET_ADC_LSB 0 +#define RESETS_RESET_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_WDSEL +// Description : Watchdog select. If a bit is set then the watchdog will reset +// this peripheral when the watchdog fires. +#define RESETS_WDSEL_OFFSET 0x00000004 +#define RESETS_WDSEL_BITS 0x01ffffff +#define RESETS_WDSEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_USBCTRL +// Description : None +#define RESETS_WDSEL_USBCTRL_RESET 0x0 +#define RESETS_WDSEL_USBCTRL_BITS 0x01000000 +#define RESETS_WDSEL_USBCTRL_MSB 24 +#define RESETS_WDSEL_USBCTRL_LSB 24 +#define RESETS_WDSEL_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART1 +// Description : None +#define RESETS_WDSEL_UART1_RESET 0x0 +#define RESETS_WDSEL_UART1_BITS 0x00800000 +#define RESETS_WDSEL_UART1_MSB 23 +#define RESETS_WDSEL_UART1_LSB 23 +#define RESETS_WDSEL_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART0 +// Description : None +#define RESETS_WDSEL_UART0_RESET 0x0 +#define RESETS_WDSEL_UART0_BITS 0x00400000 +#define RESETS_WDSEL_UART0_MSB 22 +#define RESETS_WDSEL_UART0_LSB 22 +#define RESETS_WDSEL_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER +// Description : None +#define RESETS_WDSEL_TIMER_RESET 0x0 +#define RESETS_WDSEL_TIMER_BITS 0x00200000 +#define RESETS_WDSEL_TIMER_MSB 21 +#define RESETS_WDSEL_TIMER_LSB 21 +#define RESETS_WDSEL_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TBMAN +// Description : None +#define RESETS_WDSEL_TBMAN_RESET 0x0 +#define RESETS_WDSEL_TBMAN_BITS 0x00100000 +#define RESETS_WDSEL_TBMAN_MSB 20 +#define RESETS_WDSEL_TBMAN_LSB 20 +#define RESETS_WDSEL_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSINFO +// Description : None +#define RESETS_WDSEL_SYSINFO_RESET 0x0 +#define RESETS_WDSEL_SYSINFO_BITS 0x00080000 +#define RESETS_WDSEL_SYSINFO_MSB 19 +#define RESETS_WDSEL_SYSINFO_LSB 19 +#define RESETS_WDSEL_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSCFG +// Description : None +#define RESETS_WDSEL_SYSCFG_RESET 0x0 +#define RESETS_WDSEL_SYSCFG_BITS 0x00040000 +#define RESETS_WDSEL_SYSCFG_MSB 18 +#define RESETS_WDSEL_SYSCFG_LSB 18 +#define RESETS_WDSEL_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI1 +// Description : None +#define RESETS_WDSEL_SPI1_RESET 0x0 +#define RESETS_WDSEL_SPI1_BITS 0x00020000 +#define RESETS_WDSEL_SPI1_MSB 17 +#define RESETS_WDSEL_SPI1_LSB 17 +#define RESETS_WDSEL_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI0 +// Description : None +#define RESETS_WDSEL_SPI0_RESET 0x0 +#define RESETS_WDSEL_SPI0_BITS 0x00010000 +#define RESETS_WDSEL_SPI0_MSB 16 +#define RESETS_WDSEL_SPI0_LSB 16 +#define RESETS_WDSEL_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_RTC +// Description : None +#define RESETS_WDSEL_RTC_RESET 0x0 +#define RESETS_WDSEL_RTC_BITS 0x00008000 +#define RESETS_WDSEL_RTC_MSB 15 +#define RESETS_WDSEL_RTC_LSB 15 +#define RESETS_WDSEL_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PWM +// Description : None +#define RESETS_WDSEL_PWM_RESET 0x0 +#define RESETS_WDSEL_PWM_BITS 0x00004000 +#define RESETS_WDSEL_PWM_MSB 14 +#define RESETS_WDSEL_PWM_LSB 14 +#define RESETS_WDSEL_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_USB +// Description : None +#define RESETS_WDSEL_PLL_USB_RESET 0x0 +#define RESETS_WDSEL_PLL_USB_BITS 0x00002000 +#define RESETS_WDSEL_PLL_USB_MSB 13 +#define RESETS_WDSEL_PLL_USB_LSB 13 +#define RESETS_WDSEL_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_SYS +// Description : None +#define RESETS_WDSEL_PLL_SYS_RESET 0x0 +#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000 +#define RESETS_WDSEL_PLL_SYS_MSB 12 +#define RESETS_WDSEL_PLL_SYS_LSB 12 +#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO1 +// Description : None +#define RESETS_WDSEL_PIO1_RESET 0x0 +#define RESETS_WDSEL_PIO1_BITS 0x00000800 +#define RESETS_WDSEL_PIO1_MSB 11 +#define RESETS_WDSEL_PIO1_LSB 11 +#define RESETS_WDSEL_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO0 +// Description : None +#define RESETS_WDSEL_PIO0_RESET 0x0 +#define RESETS_WDSEL_PIO0_BITS 0x00000400 +#define RESETS_WDSEL_PIO0_MSB 10 +#define RESETS_WDSEL_PIO0_LSB 10 +#define RESETS_WDSEL_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_QSPI +// Description : None +#define RESETS_WDSEL_PADS_QSPI_RESET 0x0 +#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200 +#define RESETS_WDSEL_PADS_QSPI_MSB 9 +#define RESETS_WDSEL_PADS_QSPI_LSB 9 +#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_BANK0 +// Description : None +#define RESETS_WDSEL_PADS_BANK0_RESET 0x0 +#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100 +#define RESETS_WDSEL_PADS_BANK0_MSB 8 +#define RESETS_WDSEL_PADS_BANK0_LSB 8 +#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_JTAG +// Description : None +#define RESETS_WDSEL_JTAG_RESET 0x0 +#define RESETS_WDSEL_JTAG_BITS 0x00000080 +#define RESETS_WDSEL_JTAG_MSB 7 +#define RESETS_WDSEL_JTAG_LSB 7 +#define RESETS_WDSEL_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_QSPI +// Description : None +#define RESETS_WDSEL_IO_QSPI_RESET 0x0 +#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040 +#define RESETS_WDSEL_IO_QSPI_MSB 6 +#define RESETS_WDSEL_IO_QSPI_LSB 6 +#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_BANK0 +// Description : None +#define RESETS_WDSEL_IO_BANK0_RESET 0x0 +#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020 +#define RESETS_WDSEL_IO_BANK0_MSB 5 +#define RESETS_WDSEL_IO_BANK0_LSB 5 +#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C1 +// Description : None +#define RESETS_WDSEL_I2C1_RESET 0x0 +#define RESETS_WDSEL_I2C1_BITS 0x00000010 +#define RESETS_WDSEL_I2C1_MSB 4 +#define RESETS_WDSEL_I2C1_LSB 4 +#define RESETS_WDSEL_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C0 +// Description : None +#define RESETS_WDSEL_I2C0_RESET 0x0 +#define RESETS_WDSEL_I2C0_BITS 0x00000008 +#define RESETS_WDSEL_I2C0_MSB 3 +#define RESETS_WDSEL_I2C0_LSB 3 +#define RESETS_WDSEL_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_DMA +// Description : None +#define RESETS_WDSEL_DMA_RESET 0x0 +#define RESETS_WDSEL_DMA_BITS 0x00000004 +#define RESETS_WDSEL_DMA_MSB 2 +#define RESETS_WDSEL_DMA_LSB 2 +#define RESETS_WDSEL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_BUSCTRL +// Description : None +#define RESETS_WDSEL_BUSCTRL_RESET 0x0 +#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002 +#define RESETS_WDSEL_BUSCTRL_MSB 1 +#define RESETS_WDSEL_BUSCTRL_LSB 1 +#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_ADC +// Description : None +#define RESETS_WDSEL_ADC_RESET 0x0 +#define RESETS_WDSEL_ADC_BITS 0x00000001 +#define RESETS_WDSEL_ADC_MSB 0 +#define RESETS_WDSEL_ADC_LSB 0 +#define RESETS_WDSEL_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_RESET_DONE +// Description : Reset done. If a bit is set then a reset done signal has been +// returned by the peripheral. This indicates that the +// peripheral's registers are ready to be accessed. +#define RESETS_RESET_DONE_OFFSET 0x00000008 +#define RESETS_RESET_DONE_BITS 0x01ffffff +#define RESETS_RESET_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_USBCTRL +// Description : None +#define RESETS_RESET_DONE_USBCTRL_RESET 0x0 +#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000 +#define RESETS_RESET_DONE_USBCTRL_MSB 24 +#define RESETS_RESET_DONE_USBCTRL_LSB 24 +#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART1 +// Description : None +#define RESETS_RESET_DONE_UART1_RESET 0x0 +#define RESETS_RESET_DONE_UART1_BITS 0x00800000 +#define RESETS_RESET_DONE_UART1_MSB 23 +#define RESETS_RESET_DONE_UART1_LSB 23 +#define RESETS_RESET_DONE_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART0 +// Description : None +#define RESETS_RESET_DONE_UART0_RESET 0x0 +#define RESETS_RESET_DONE_UART0_BITS 0x00400000 +#define RESETS_RESET_DONE_UART0_MSB 22 +#define RESETS_RESET_DONE_UART0_LSB 22 +#define RESETS_RESET_DONE_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER +// Description : None +#define RESETS_RESET_DONE_TIMER_RESET 0x0 +#define RESETS_RESET_DONE_TIMER_BITS 0x00200000 +#define RESETS_RESET_DONE_TIMER_MSB 21 +#define RESETS_RESET_DONE_TIMER_LSB 21 +#define RESETS_RESET_DONE_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TBMAN +// Description : None +#define RESETS_RESET_DONE_TBMAN_RESET 0x0 +#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000 +#define RESETS_RESET_DONE_TBMAN_MSB 20 +#define RESETS_RESET_DONE_TBMAN_LSB 20 +#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSINFO +// Description : None +#define RESETS_RESET_DONE_SYSINFO_RESET 0x0 +#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000 +#define RESETS_RESET_DONE_SYSINFO_MSB 19 +#define RESETS_RESET_DONE_SYSINFO_LSB 19 +#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSCFG +// Description : None +#define RESETS_RESET_DONE_SYSCFG_RESET 0x0 +#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000 +#define RESETS_RESET_DONE_SYSCFG_MSB 18 +#define RESETS_RESET_DONE_SYSCFG_LSB 18 +#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI1 +// Description : None +#define RESETS_RESET_DONE_SPI1_RESET 0x0 +#define RESETS_RESET_DONE_SPI1_BITS 0x00020000 +#define RESETS_RESET_DONE_SPI1_MSB 17 +#define RESETS_RESET_DONE_SPI1_LSB 17 +#define RESETS_RESET_DONE_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI0 +// Description : None +#define RESETS_RESET_DONE_SPI0_RESET 0x0 +#define RESETS_RESET_DONE_SPI0_BITS 0x00010000 +#define RESETS_RESET_DONE_SPI0_MSB 16 +#define RESETS_RESET_DONE_SPI0_LSB 16 +#define RESETS_RESET_DONE_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_RTC +// Description : None +#define RESETS_RESET_DONE_RTC_RESET 0x0 +#define RESETS_RESET_DONE_RTC_BITS 0x00008000 +#define RESETS_RESET_DONE_RTC_MSB 15 +#define RESETS_RESET_DONE_RTC_LSB 15 +#define RESETS_RESET_DONE_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PWM +// Description : None +#define RESETS_RESET_DONE_PWM_RESET 0x0 +#define RESETS_RESET_DONE_PWM_BITS 0x00004000 +#define RESETS_RESET_DONE_PWM_MSB 14 +#define RESETS_RESET_DONE_PWM_LSB 14 +#define RESETS_RESET_DONE_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_USB +// Description : None +#define RESETS_RESET_DONE_PLL_USB_RESET 0x0 +#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000 +#define RESETS_RESET_DONE_PLL_USB_MSB 13 +#define RESETS_RESET_DONE_PLL_USB_LSB 13 +#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_SYS +// Description : None +#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0 +#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000 +#define RESETS_RESET_DONE_PLL_SYS_MSB 12 +#define RESETS_RESET_DONE_PLL_SYS_LSB 12 +#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO1 +// Description : None +#define RESETS_RESET_DONE_PIO1_RESET 0x0 +#define RESETS_RESET_DONE_PIO1_BITS 0x00000800 +#define RESETS_RESET_DONE_PIO1_MSB 11 +#define RESETS_RESET_DONE_PIO1_LSB 11 +#define RESETS_RESET_DONE_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO0 +// Description : None +#define RESETS_RESET_DONE_PIO0_RESET 0x0 +#define RESETS_RESET_DONE_PIO0_BITS 0x00000400 +#define RESETS_RESET_DONE_PIO0_MSB 10 +#define RESETS_RESET_DONE_PIO0_LSB 10 +#define RESETS_RESET_DONE_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_QSPI +// Description : None +#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0 +#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200 +#define RESETS_RESET_DONE_PADS_QSPI_MSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_LSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_BANK0 +// Description : None +#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0 +#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100 +#define RESETS_RESET_DONE_PADS_BANK0_MSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_LSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_JTAG +// Description : None +#define RESETS_RESET_DONE_JTAG_RESET 0x0 +#define RESETS_RESET_DONE_JTAG_BITS 0x00000080 +#define RESETS_RESET_DONE_JTAG_MSB 7 +#define RESETS_RESET_DONE_JTAG_LSB 7 +#define RESETS_RESET_DONE_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_QSPI +// Description : None +#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0 +#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040 +#define RESETS_RESET_DONE_IO_QSPI_MSB 6 +#define RESETS_RESET_DONE_IO_QSPI_LSB 6 +#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_BANK0 +// Description : None +#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0 +#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020 +#define RESETS_RESET_DONE_IO_BANK0_MSB 5 +#define RESETS_RESET_DONE_IO_BANK0_LSB 5 +#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C1 +// Description : None +#define RESETS_RESET_DONE_I2C1_RESET 0x0 +#define RESETS_RESET_DONE_I2C1_BITS 0x00000010 +#define RESETS_RESET_DONE_I2C1_MSB 4 +#define RESETS_RESET_DONE_I2C1_LSB 4 +#define RESETS_RESET_DONE_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C0 +// Description : None +#define RESETS_RESET_DONE_I2C0_RESET 0x0 +#define RESETS_RESET_DONE_I2C0_BITS 0x00000008 +#define RESETS_RESET_DONE_I2C0_MSB 3 +#define RESETS_RESET_DONE_I2C0_LSB 3 +#define RESETS_RESET_DONE_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_DMA +// Description : None +#define RESETS_RESET_DONE_DMA_RESET 0x0 +#define RESETS_RESET_DONE_DMA_BITS 0x00000004 +#define RESETS_RESET_DONE_DMA_MSB 2 +#define RESETS_RESET_DONE_DMA_LSB 2 +#define RESETS_RESET_DONE_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_BUSCTRL +// Description : None +#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0 +#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002 +#define RESETS_RESET_DONE_BUSCTRL_MSB 1 +#define RESETS_RESET_DONE_BUSCTRL_LSB 1 +#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_ADC +// Description : None +#define RESETS_RESET_DONE_ADC_RESET 0x0 +#define RESETS_RESET_DONE_ADC_BITS 0x00000001 +#define RESETS_RESET_DONE_ADC_MSB 0 +#define RESETS_RESET_DONE_ADC_LSB 0 +#define RESETS_RESET_DONE_ADC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_RESETS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h new file mode 100644 index 00000000000..1f9e8ccc5e7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h @@ -0,0 +1,312 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ROSC +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_ROSC_DEFINED +#define HARDWARE_REGS_ROSC_DEFINED +// ============================================================================= +// Register : ROSC_CTRL +// Description : Ring Oscillator control +#define ROSC_CTRL_OFFSET 0x00000000 +#define ROSC_CTRL_BITS 0x00ffffff +#define ROSC_CTRL_RESET 0x00000aa0 +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_ENABLE +// Description : On power-up this field is initialised to ENABLE +// The system clock must be switched to another source before +// setting this field to DISABLE otherwise the chip will lock up +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS 0x00fff000 +#define ROSC_CTRL_ENABLE_MSB 23 +#define ROSC_CTRL_ENABLE_LSB 12 +#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e +#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_FREQ_RANGE +// Description : Controls the number of delay stages in the ROSC ring +// LOW uses stages 0 to 7 +// MEDIUM uses stages 0 to 5 +// HIGH uses stages 0 to 3 +// TOOHIGH uses stages 0 to 1 and should not be used because its +// frequency exceeds design specifications +// The clock output will not glitch when changing the range up one +// step at a time +// The clock output will glitch when changing the range down +// Note: the values here are gray coded which is why HIGH comes +// before TOOHIGH +// 0xfa4 -> LOW +// 0xfa5 -> MEDIUM +// 0xfa7 -> HIGH +// 0xfa6 -> TOOHIGH +#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0 +#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff +#define ROSC_CTRL_FREQ_RANGE_MSB 11 +#define ROSC_CTRL_FREQ_RANGE_LSB 0 +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4 +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5 +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7 +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6 +// ============================================================================= +// Register : ROSC_FREQA +// Description : The FREQA & FREQB registers control the frequency by +// controlling the drive strength of each stage +// The drive strength has 4 levels determined by the number of +// bits set +// Increasing the number of bits set increases the drive strength +// and increases the oscillation frequency +// 0 bits set is the default drive strength +// 1 bit set doubles the drive strength +// 2 bits set triples drive strength +// 3 bits set quadruples drive strength +#define ROSC_FREQA_OFFSET 0x00000004 +#define ROSC_FREQA_BITS 0xffff7777 +#define ROSC_FREQA_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQA_PASSWD_RESET 0x0000 +#define ROSC_FREQA_PASSWD_BITS 0xffff0000 +#define ROSC_FREQA_PASSWD_MSB 31 +#define ROSC_FREQA_PASSWD_LSB 16 +#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS3 +// Description : Stage 3 drive strength +#define ROSC_FREQA_DS3_RESET 0x0 +#define ROSC_FREQA_DS3_BITS 0x00007000 +#define ROSC_FREQA_DS3_MSB 14 +#define ROSC_FREQA_DS3_LSB 12 +#define ROSC_FREQA_DS3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS2 +// Description : Stage 2 drive strength +#define ROSC_FREQA_DS2_RESET 0x0 +#define ROSC_FREQA_DS2_BITS 0x00000700 +#define ROSC_FREQA_DS2_MSB 10 +#define ROSC_FREQA_DS2_LSB 8 +#define ROSC_FREQA_DS2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1 +// Description : Stage 1 drive strength +#define ROSC_FREQA_DS1_RESET 0x0 +#define ROSC_FREQA_DS1_BITS 0x00000070 +#define ROSC_FREQA_DS1_MSB 6 +#define ROSC_FREQA_DS1_LSB 4 +#define ROSC_FREQA_DS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0 +// Description : Stage 0 drive strength +#define ROSC_FREQA_DS0_RESET 0x0 +#define ROSC_FREQA_DS0_BITS 0x00000007 +#define ROSC_FREQA_DS0_MSB 2 +#define ROSC_FREQA_DS0_LSB 0 +#define ROSC_FREQA_DS0_ACCESS "RW" +// ============================================================================= +// Register : ROSC_FREQB +// Description : For a detailed description see freqa register +#define ROSC_FREQB_OFFSET 0x00000008 +#define ROSC_FREQB_BITS 0xffff7777 +#define ROSC_FREQB_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQB_PASSWD_RESET 0x0000 +#define ROSC_FREQB_PASSWD_BITS 0xffff0000 +#define ROSC_FREQB_PASSWD_MSB 31 +#define ROSC_FREQB_PASSWD_LSB 16 +#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS7 +// Description : Stage 7 drive strength +#define ROSC_FREQB_DS7_RESET 0x0 +#define ROSC_FREQB_DS7_BITS 0x00007000 +#define ROSC_FREQB_DS7_MSB 14 +#define ROSC_FREQB_DS7_LSB 12 +#define ROSC_FREQB_DS7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS6 +// Description : Stage 6 drive strength +#define ROSC_FREQB_DS6_RESET 0x0 +#define ROSC_FREQB_DS6_BITS 0x00000700 +#define ROSC_FREQB_DS6_MSB 10 +#define ROSC_FREQB_DS6_LSB 8 +#define ROSC_FREQB_DS6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS5 +// Description : Stage 5 drive strength +#define ROSC_FREQB_DS5_RESET 0x0 +#define ROSC_FREQB_DS5_BITS 0x00000070 +#define ROSC_FREQB_DS5_MSB 6 +#define ROSC_FREQB_DS5_LSB 4 +#define ROSC_FREQB_DS5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS4 +// Description : Stage 4 drive strength +#define ROSC_FREQB_DS4_RESET 0x0 +#define ROSC_FREQB_DS4_BITS 0x00000007 +#define ROSC_FREQB_DS4_MSB 2 +#define ROSC_FREQB_DS4_LSB 0 +#define ROSC_FREQB_DS4_ACCESS "RW" +// ============================================================================= +// Register : ROSC_DORMANT +// Description : Ring Oscillator pause control +// This is used to save power by pausing the ROSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT +// 0x77616b65 -> WAKE +#define ROSC_DORMANT_OFFSET 0x0000000c +#define ROSC_DORMANT_BITS 0xffffffff +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB 31 +#define ROSC_DORMANT_LSB 0 +#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61 +#define ROSC_DORMANT_VALUE_WAKE 0x77616b65 +// ============================================================================= +// Register : ROSC_DIV +// Description : Controls the output divider +// set to 0xaa0 + div where +// div = 0 divides by 32 +// div = 1-31 divides by div +// any other value sets div=0 and therefore divides by 32 +// this register resets to div=16 +// 0xaa0 -> PASS +#define ROSC_DIV_OFFSET 0x00000010 +#define ROSC_DIV_BITS 0x00000fff +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB 11 +#define ROSC_DIV_LSB 0 +#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_VALUE_PASS 0xaa0 +// ============================================================================= +// Register : ROSC_PHASE +// Description : Controls the phase shifted output +#define ROSC_PHASE_OFFSET 0x00000014 +#define ROSC_PHASE_BITS 0x00000fff +#define ROSC_PHASE_RESET 0x00000008 +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_PASSWD +// Description : set to 0xaa0 +// any other value enables the output with shift=0 +#define ROSC_PHASE_PASSWD_RESET 0x00 +#define ROSC_PHASE_PASSWD_BITS 0x00000ff0 +#define ROSC_PHASE_PASSWD_MSB 11 +#define ROSC_PHASE_PASSWD_LSB 4 +#define ROSC_PHASE_PASSWD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_ENABLE +// Description : enable the phase-shifted output +// this can be changed on-the-fly +#define ROSC_PHASE_ENABLE_RESET 0x1 +#define ROSC_PHASE_ENABLE_BITS 0x00000008 +#define ROSC_PHASE_ENABLE_MSB 3 +#define ROSC_PHASE_ENABLE_LSB 3 +#define ROSC_PHASE_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_FLIP +// Description : invert the phase-shifted output +// this is ignored when div=1 +#define ROSC_PHASE_FLIP_RESET 0x0 +#define ROSC_PHASE_FLIP_BITS 0x00000004 +#define ROSC_PHASE_FLIP_MSB 2 +#define ROSC_PHASE_FLIP_LSB 2 +#define ROSC_PHASE_FLIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_SHIFT +// Description : phase shift the phase-shifted output by SHIFT input clocks +// this can be changed on-the-fly +// must be set to 0 before setting div=1 +#define ROSC_PHASE_SHIFT_RESET 0x0 +#define ROSC_PHASE_SHIFT_BITS 0x00000003 +#define ROSC_PHASE_SHIFT_MSB 1 +#define ROSC_PHASE_SHIFT_LSB 0 +#define ROSC_PHASE_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : ROSC_STATUS +// Description : Ring Oscillator Status +#define ROSC_STATUS_OFFSET 0x00000018 +#define ROSC_STATUS_BITS 0x81011000 +#define ROSC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define ROSC_STATUS_STABLE_RESET 0x0 +#define ROSC_STATUS_STABLE_BITS 0x80000000 +#define ROSC_STATUS_STABLE_MSB 31 +#define ROSC_STATUS_STABLE_LSB 31 +#define ROSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT +#define ROSC_STATUS_BADWRITE_RESET 0x0 +#define ROSC_STATUS_BADWRITE_BITS 0x01000000 +#define ROSC_STATUS_BADWRITE_MSB 24 +#define ROSC_STATUS_BADWRITE_LSB 24 +#define ROSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_DIV_RUNNING +// Description : post-divider is running +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_DIV_RUNNING_RESET "-" +#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000 +#define ROSC_STATUS_DIV_RUNNING_MSB 16 +#define ROSC_STATUS_DIV_RUNNING_LSB 16 +#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_ENABLED_RESET "-" +#define ROSC_STATUS_ENABLED_BITS 0x00001000 +#define ROSC_STATUS_ENABLED_MSB 12 +#define ROSC_STATUS_ENABLED_LSB 12 +#define ROSC_STATUS_ENABLED_ACCESS "RO" +// ============================================================================= +// Register : ROSC_RANDOMBIT +// Description : This just reads the state of the oscillator output so +// randomness is compromised if the ring oscillator is stopped or +// run at a harmonic of the bus frequency +#define ROSC_RANDOMBIT_OFFSET 0x0000001c +#define ROSC_RANDOMBIT_BITS 0x00000001 +#define ROSC_RANDOMBIT_RESET 0x00000001 +#define ROSC_RANDOMBIT_MSB 0 +#define ROSC_RANDOMBIT_LSB 0 +#define ROSC_RANDOMBIT_ACCESS "RO" +// ============================================================================= +// Register : ROSC_COUNT +// Description : A down counter running at the ROSC frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define ROSC_COUNT_OFFSET 0x00000020 +#define ROSC_COUNT_BITS 0x000000ff +#define ROSC_COUNT_RESET 0x00000000 +#define ROSC_COUNT_MSB 7 +#define ROSC_COUNT_LSB 0 +#define ROSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_ROSC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h new file mode 100644 index 00000000000..1287d9023b7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h @@ -0,0 +1,398 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RTC +// Version : 1 +// Bus type : apb +// Description : Register block to control RTC +// ============================================================================= +#ifndef HARDWARE_REGS_RTC_DEFINED +#define HARDWARE_REGS_RTC_DEFINED +// ============================================================================= +// Register : RTC_CLKDIV_M1 +// Description : Divider minus 1 for the 1 second counter. Safe to change the +// value when RTC is not enabled. +#define RTC_CLKDIV_M1_OFFSET 0x00000000 +#define RTC_CLKDIV_M1_BITS 0x0000ffff +#define RTC_CLKDIV_M1_RESET 0x00000000 +#define RTC_CLKDIV_M1_MSB 15 +#define RTC_CLKDIV_M1_LSB 0 +#define RTC_CLKDIV_M1_ACCESS "RW" +// ============================================================================= +// Register : RTC_SETUP_0 +// Description : RTC setup register 0 +#define RTC_SETUP_0_OFFSET 0x00000004 +#define RTC_SETUP_0_BITS 0x00ffff1f +#define RTC_SETUP_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_YEAR +// Description : Year +#define RTC_SETUP_0_YEAR_RESET 0x000 +#define RTC_SETUP_0_YEAR_BITS 0x00fff000 +#define RTC_SETUP_0_YEAR_MSB 23 +#define RTC_SETUP_0_YEAR_LSB 12 +#define RTC_SETUP_0_YEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_MONTH +// Description : Month (1..12) +#define RTC_SETUP_0_MONTH_RESET 0x0 +#define RTC_SETUP_0_MONTH_BITS 0x00000f00 +#define RTC_SETUP_0_MONTH_MSB 11 +#define RTC_SETUP_0_MONTH_LSB 8 +#define RTC_SETUP_0_MONTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_DAY +// Description : Day of the month (1..31) +#define RTC_SETUP_0_DAY_RESET 0x00 +#define RTC_SETUP_0_DAY_BITS 0x0000001f +#define RTC_SETUP_0_DAY_MSB 4 +#define RTC_SETUP_0_DAY_LSB 0 +#define RTC_SETUP_0_DAY_ACCESS "RW" +// ============================================================================= +// Register : RTC_SETUP_1 +// Description : RTC setup register 1 +#define RTC_SETUP_1_OFFSET 0x00000008 +#define RTC_SETUP_1_BITS 0x071f3f3f +#define RTC_SETUP_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_DOTW +// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 +#define RTC_SETUP_1_DOTW_RESET 0x0 +#define RTC_SETUP_1_DOTW_BITS 0x07000000 +#define RTC_SETUP_1_DOTW_MSB 26 +#define RTC_SETUP_1_DOTW_LSB 24 +#define RTC_SETUP_1_DOTW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_HOUR +// Description : Hours +#define RTC_SETUP_1_HOUR_RESET 0x00 +#define RTC_SETUP_1_HOUR_BITS 0x001f0000 +#define RTC_SETUP_1_HOUR_MSB 20 +#define RTC_SETUP_1_HOUR_LSB 16 +#define RTC_SETUP_1_HOUR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_MIN +// Description : Minutes +#define RTC_SETUP_1_MIN_RESET 0x00 +#define RTC_SETUP_1_MIN_BITS 0x00003f00 +#define RTC_SETUP_1_MIN_MSB 13 +#define RTC_SETUP_1_MIN_LSB 8 +#define RTC_SETUP_1_MIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_SEC +// Description : Seconds +#define RTC_SETUP_1_SEC_RESET 0x00 +#define RTC_SETUP_1_SEC_BITS 0x0000003f +#define RTC_SETUP_1_SEC_MSB 5 +#define RTC_SETUP_1_SEC_LSB 0 +#define RTC_SETUP_1_SEC_ACCESS "RW" +// ============================================================================= +// Register : RTC_CTRL +// Description : RTC Control and status +#define RTC_CTRL_OFFSET 0x0000000c +#define RTC_CTRL_BITS 0x00000113 +#define RTC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_FORCE_NOTLEAPYEAR +// Description : If set, leapyear is forced off. +// Useful for years divisible by 100 but not by 400 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_LOAD +// Description : Load RTC +#define RTC_CTRL_LOAD_RESET 0x0 +#define RTC_CTRL_LOAD_BITS 0x00000010 +#define RTC_CTRL_LOAD_MSB 4 +#define RTC_CTRL_LOAD_LSB 4 +#define RTC_CTRL_LOAD_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_RTC_ACTIVE +// Description : RTC enabled (running) +#define RTC_CTRL_RTC_ACTIVE_RESET "-" +#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002 +#define RTC_CTRL_RTC_ACTIVE_MSB 1 +#define RTC_CTRL_RTC_ACTIVE_LSB 1 +#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_RTC_ENABLE +// Description : Enable RTC +#define RTC_CTRL_RTC_ENABLE_RESET 0x0 +#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001 +#define RTC_CTRL_RTC_ENABLE_MSB 0 +#define RTC_CTRL_RTC_ENABLE_LSB 0 +#define RTC_CTRL_RTC_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : RTC_IRQ_SETUP_0 +// Description : Interrupt setup register 0 +#define RTC_IRQ_SETUP_0_OFFSET 0x00000010 +#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f +#define RTC_IRQ_SETUP_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE +// Description : None +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MATCH_ENA +// Description : Global match enable. Don't change any other value while this +// one is enabled +#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000 +#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_YEAR_ENA +// Description : Enable year matching +#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000 +#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MONTH_ENA +// Description : Enable month matching +#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000 +#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_DAY_ENA +// Description : Enable day matching +#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000 +#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_YEAR +// Description : Year +#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000 +#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000 +#define RTC_IRQ_SETUP_0_YEAR_MSB 23 +#define RTC_IRQ_SETUP_0_YEAR_LSB 12 +#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MONTH +// Description : Month (1..12) +#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0 +#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00 +#define RTC_IRQ_SETUP_0_MONTH_MSB 11 +#define RTC_IRQ_SETUP_0_MONTH_LSB 8 +#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_DAY +// Description : Day of the month (1..31) +#define RTC_IRQ_SETUP_0_DAY_RESET 0x00 +#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f +#define RTC_IRQ_SETUP_0_DAY_MSB 4 +#define RTC_IRQ_SETUP_0_DAY_LSB 0 +#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" +// ============================================================================= +// Register : RTC_IRQ_SETUP_1 +// Description : Interrupt setup register 1 +#define RTC_IRQ_SETUP_1_OFFSET 0x00000014 +#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f +#define RTC_IRQ_SETUP_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_DOTW_ENA +// Description : Enable day of the week matching +#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000 +#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_HOUR_ENA +// Description : Enable hour matching +#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000 +#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_MIN_ENA +// Description : Enable minute matching +#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000 +#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_SEC_ENA +// Description : Enable second matching +#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000 +#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_DOTW +// Description : Day of the week +#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0 +#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000 +#define RTC_IRQ_SETUP_1_DOTW_MSB 26 +#define RTC_IRQ_SETUP_1_DOTW_LSB 24 +#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_HOUR +// Description : Hours +#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00 +#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000 +#define RTC_IRQ_SETUP_1_HOUR_MSB 20 +#define RTC_IRQ_SETUP_1_HOUR_LSB 16 +#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_MIN +// Description : Minutes +#define RTC_IRQ_SETUP_1_MIN_RESET 0x00 +#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00 +#define RTC_IRQ_SETUP_1_MIN_MSB 13 +#define RTC_IRQ_SETUP_1_MIN_LSB 8 +#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_SEC +// Description : Seconds +#define RTC_IRQ_SETUP_1_SEC_RESET 0x00 +#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f +#define RTC_IRQ_SETUP_1_SEC_MSB 5 +#define RTC_IRQ_SETUP_1_SEC_LSB 0 +#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" +// ============================================================================= +// Register : RTC_RTC_1 +// Description : RTC register 1. +#define RTC_RTC_1_OFFSET 0x00000018 +#define RTC_RTC_1_BITS 0x00ffff1f +#define RTC_RTC_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_YEAR +// Description : Year +#define RTC_RTC_1_YEAR_RESET "-" +#define RTC_RTC_1_YEAR_BITS 0x00fff000 +#define RTC_RTC_1_YEAR_MSB 23 +#define RTC_RTC_1_YEAR_LSB 12 +#define RTC_RTC_1_YEAR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_MONTH +// Description : Month (1..12) +#define RTC_RTC_1_MONTH_RESET "-" +#define RTC_RTC_1_MONTH_BITS 0x00000f00 +#define RTC_RTC_1_MONTH_MSB 11 +#define RTC_RTC_1_MONTH_LSB 8 +#define RTC_RTC_1_MONTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_DAY +// Description : Day of the month (1..31) +#define RTC_RTC_1_DAY_RESET "-" +#define RTC_RTC_1_DAY_BITS 0x0000001f +#define RTC_RTC_1_DAY_MSB 4 +#define RTC_RTC_1_DAY_LSB 0 +#define RTC_RTC_1_DAY_ACCESS "RO" +// ============================================================================= +// Register : RTC_RTC_0 +// Description : RTC register 0 +// Read this before RTC 1! +#define RTC_RTC_0_OFFSET 0x0000001c +#define RTC_RTC_0_BITS 0x071f3f3f +#define RTC_RTC_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_DOTW +// Description : Day of the week +#define RTC_RTC_0_DOTW_RESET "-" +#define RTC_RTC_0_DOTW_BITS 0x07000000 +#define RTC_RTC_0_DOTW_MSB 26 +#define RTC_RTC_0_DOTW_LSB 24 +#define RTC_RTC_0_DOTW_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_HOUR +// Description : Hours +#define RTC_RTC_0_HOUR_RESET "-" +#define RTC_RTC_0_HOUR_BITS 0x001f0000 +#define RTC_RTC_0_HOUR_MSB 20 +#define RTC_RTC_0_HOUR_LSB 16 +#define RTC_RTC_0_HOUR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_MIN +// Description : Minutes +#define RTC_RTC_0_MIN_RESET "-" +#define RTC_RTC_0_MIN_BITS 0x00003f00 +#define RTC_RTC_0_MIN_MSB 13 +#define RTC_RTC_0_MIN_LSB 8 +#define RTC_RTC_0_MIN_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_SEC +// Description : Seconds +#define RTC_RTC_0_SEC_RESET "-" +#define RTC_RTC_0_SEC_BITS 0x0000003f +#define RTC_RTC_0_SEC_MSB 5 +#define RTC_RTC_0_SEC_LSB 0 +#define RTC_RTC_0_SEC_ACCESS "RF" +// ============================================================================= +// Register : RTC_INTR +// Description : Raw Interrupts +#define RTC_INTR_OFFSET 0x00000020 +#define RTC_INTR_BITS 0x00000001 +#define RTC_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTR_RTC +// Description : None +#define RTC_INTR_RTC_RESET 0x0 +#define RTC_INTR_RTC_BITS 0x00000001 +#define RTC_INTR_RTC_MSB 0 +#define RTC_INTR_RTC_LSB 0 +#define RTC_INTR_RTC_ACCESS "RO" +// ============================================================================= +// Register : RTC_INTE +// Description : Interrupt Enable +#define RTC_INTE_OFFSET 0x00000024 +#define RTC_INTE_BITS 0x00000001 +#define RTC_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTE_RTC +// Description : None +#define RTC_INTE_RTC_RESET 0x0 +#define RTC_INTE_RTC_BITS 0x00000001 +#define RTC_INTE_RTC_MSB 0 +#define RTC_INTE_RTC_LSB 0 +#define RTC_INTE_RTC_ACCESS "RW" +// ============================================================================= +// Register : RTC_INTF +// Description : Interrupt Force +#define RTC_INTF_OFFSET 0x00000028 +#define RTC_INTF_BITS 0x00000001 +#define RTC_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTF_RTC +// Description : None +#define RTC_INTF_RTC_RESET 0x0 +#define RTC_INTF_RTC_BITS 0x00000001 +#define RTC_INTF_RTC_MSB 0 +#define RTC_INTF_RTC_LSB 0 +#define RTC_INTF_RTC_ACCESS "RW" +// ============================================================================= +// Register : RTC_INTS +// Description : Interrupt status after masking & forcing +#define RTC_INTS_OFFSET 0x0000002c +#define RTC_INTS_BITS 0x00000001 +#define RTC_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTS_RTC +// Description : None +#define RTC_INTS_RTC_RESET 0x0 +#define RTC_INTS_RTC_BITS 0x00000001 +#define RTC_INTS_RTC_MSB 0 +#define RTC_INTS_RTC_LSB 0 +#define RTC_INTS_RTC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_RTC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h new file mode 100644 index 00000000000..4480d76f08e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h @@ -0,0 +1,1656 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SIO +// Version : 1 +// Bus type : apb +// Description : Single-cycle IO block +// Provides core-local and inter-core hardware for the two +// processors, with single-cycle access. +// ============================================================================= +#ifndef HARDWARE_REGS_SIO_DEFINED +#define HARDWARE_REGS_SIO_DEFINED +// ============================================================================= +// Register : SIO_CPUID +// Description : Processor core identifier +// Value is 0 when read from processor core 0, and 1 when read +// from processor core 1. +#define SIO_CPUID_OFFSET 0x00000000 +#define SIO_CPUID_BITS 0xffffffff +#define SIO_CPUID_RESET "-" +#define SIO_CPUID_MSB 31 +#define SIO_CPUID_LSB 0 +#define SIO_CPUID_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_IN +// Description : Input value for GPIO pins +// Input value for GPIO0...29 +#define SIO_GPIO_IN_OFFSET 0x00000004 +#define SIO_GPIO_IN_BITS 0x3fffffff +#define SIO_GPIO_IN_RESET 0x00000000 +#define SIO_GPIO_IN_MSB 29 +#define SIO_GPIO_IN_LSB 0 +#define SIO_GPIO_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_HI_IN +// Description : Input value for QSPI pins +// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, +// SD3 +#define SIO_GPIO_HI_IN_OFFSET 0x00000008 +#define SIO_GPIO_HI_IN_BITS 0x0000003f +#define SIO_GPIO_HI_IN_RESET 0x00000000 +#define SIO_GPIO_HI_IN_MSB 5 +#define SIO_GPIO_HI_IN_LSB 0 +#define SIO_GPIO_HI_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_OUT +// Description : GPIO output value +// Set output level (1/0 -> high/low) for GPIO0...29. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_OUT simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OUT_OFFSET 0x00000010 +#define SIO_GPIO_OUT_BITS 0x3fffffff +#define SIO_GPIO_OUT_RESET 0x00000000 +#define SIO_GPIO_OUT_MSB 29 +#define SIO_GPIO_OUT_LSB 0 +#define SIO_GPIO_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_SET +// Description : GPIO output value set +// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` +#define SIO_GPIO_OUT_SET_OFFSET 0x00000014 +#define SIO_GPIO_OUT_SET_BITS 0x3fffffff +#define SIO_GPIO_OUT_SET_RESET 0x00000000 +#define SIO_GPIO_OUT_SET_MSB 29 +#define SIO_GPIO_OUT_SET_LSB 0 +#define SIO_GPIO_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_CLR +// Description : GPIO output value clear +// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= +// ~wdata` +#define SIO_GPIO_OUT_CLR_OFFSET 0x00000018 +#define SIO_GPIO_OUT_CLR_BITS 0x3fffffff +#define SIO_GPIO_OUT_CLR_RESET 0x00000000 +#define SIO_GPIO_OUT_CLR_MSB 29 +#define SIO_GPIO_OUT_CLR_LSB 0 +#define SIO_GPIO_OUT_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_XOR +// Description : GPIO output value XOR +// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= +// wdata` +#define SIO_GPIO_OUT_XOR_OFFSET 0x0000001c +#define SIO_GPIO_OUT_XOR_BITS 0x3fffffff +#define SIO_GPIO_OUT_XOR_RESET 0x00000000 +#define SIO_GPIO_OUT_XOR_MSB 29 +#define SIO_GPIO_OUT_XOR_LSB 0 +#define SIO_GPIO_OUT_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE +// Description : GPIO output enable +// Set output enable (1/0 -> output/input) for GPIO0...29. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_OE simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OE_OFFSET 0x00000020 +#define SIO_GPIO_OE_BITS 0x3fffffff +#define SIO_GPIO_OE_RESET 0x00000000 +#define SIO_GPIO_OE_MSB 29 +#define SIO_GPIO_OE_LSB 0 +#define SIO_GPIO_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_SET +// Description : GPIO output enable set +// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` +#define SIO_GPIO_OE_SET_OFFSET 0x00000024 +#define SIO_GPIO_OE_SET_BITS 0x3fffffff +#define SIO_GPIO_OE_SET_RESET 0x00000000 +#define SIO_GPIO_OE_SET_MSB 29 +#define SIO_GPIO_OE_SET_LSB 0 +#define SIO_GPIO_OE_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_CLR +// Description : GPIO output enable clear +// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= +// ~wdata` +#define SIO_GPIO_OE_CLR_OFFSET 0x00000028 +#define SIO_GPIO_OE_CLR_BITS 0x3fffffff +#define SIO_GPIO_OE_CLR_RESET 0x00000000 +#define SIO_GPIO_OE_CLR_MSB 29 +#define SIO_GPIO_OE_CLR_LSB 0 +#define SIO_GPIO_OE_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_XOR +// Description : GPIO output enable XOR +// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= +// wdata` +#define SIO_GPIO_OE_XOR_OFFSET 0x0000002c +#define SIO_GPIO_OE_XOR_BITS 0x3fffffff +#define SIO_GPIO_OE_XOR_RESET 0x00000000 +#define SIO_GPIO_OE_XOR_MSB 29 +#define SIO_GPIO_OE_XOR_LSB 0 +#define SIO_GPIO_OE_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT +// Description : QSPI output value +// Set output level (1/0 -> high/low) for QSPI IO0...5. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_HI_OUT simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OUT_OFFSET 0x00000030 +#define SIO_GPIO_HI_OUT_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_MSB 5 +#define SIO_GPIO_HI_OUT_LSB 0 +#define SIO_GPIO_HI_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_SET +// Description : QSPI output value set +// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= +// wdata` +#define SIO_GPIO_HI_OUT_SET_OFFSET 0x00000034 +#define SIO_GPIO_HI_OUT_SET_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_SET_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_SET_MSB 5 +#define SIO_GPIO_HI_OUT_SET_LSB 0 +#define SIO_GPIO_HI_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_CLR +// Description : QSPI output value clear +// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// &= ~wdata` +#define SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000038 +#define SIO_GPIO_HI_OUT_CLR_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_CLR_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_CLR_MSB 5 +#define SIO_GPIO_HI_OUT_CLR_LSB 0 +#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_XOR +// Description : QSPI output value XOR +// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// ^= wdata` +#define SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000003c +#define SIO_GPIO_HI_OUT_XOR_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_XOR_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_XOR_MSB 5 +#define SIO_GPIO_HI_OUT_XOR_LSB 0 +#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE +// Description : QSPI output enable +// Set output enable (1/0 -> output/input) for QSPI IO0...5. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_HI_OE simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OE_OFFSET 0x00000040 +#define SIO_GPIO_HI_OE_BITS 0x0000003f +#define SIO_GPIO_HI_OE_RESET 0x00000000 +#define SIO_GPIO_HI_OE_MSB 5 +#define SIO_GPIO_HI_OE_LSB 0 +#define SIO_GPIO_HI_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_SET +// Description : QSPI output enable set +// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= +// wdata` +#define SIO_GPIO_HI_OE_SET_OFFSET 0x00000044 +#define SIO_GPIO_HI_OE_SET_BITS 0x0000003f +#define SIO_GPIO_HI_OE_SET_RESET 0x00000000 +#define SIO_GPIO_HI_OE_SET_MSB 5 +#define SIO_GPIO_HI_OE_SET_LSB 0 +#define SIO_GPIO_HI_OE_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_CLR +// Description : QSPI output enable clear +// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= +// ~wdata` +#define SIO_GPIO_HI_OE_CLR_OFFSET 0x00000048 +#define SIO_GPIO_HI_OE_CLR_BITS 0x0000003f +#define SIO_GPIO_HI_OE_CLR_RESET 0x00000000 +#define SIO_GPIO_HI_OE_CLR_MSB 5 +#define SIO_GPIO_HI_OE_CLR_LSB 0 +#define SIO_GPIO_HI_OE_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_XOR +// Description : QSPI output enable XOR +// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE +// ^= wdata` +#define SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c +#define SIO_GPIO_HI_OE_XOR_BITS 0x0000003f +#define SIO_GPIO_HI_OE_XOR_RESET 0x00000000 +#define SIO_GPIO_HI_OE_XOR_MSB 5 +#define SIO_GPIO_HI_OE_XOR_LSB 0 +#define SIO_GPIO_HI_OE_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_FIFO_ST +// Description : Status register for inter-core FIFOs (mailboxes). +// There is one FIFO in the core 0 -> core 1 direction, and one +// core 1 -> core 0. Both are 32 bits wide and 8 words deep. +// Core 0 can see the read side of the 1->0 FIFO (RX), and the +// write side of 0->1 FIFO (TX). +// Core 1 can see the read side of the 0->1 FIFO (RX), and the +// write side of 1->0 FIFO (TX). +// The SIO IRQ for each core is the logical OR of the VLD, WOF and +// ROE fields of its FIFO_ST register. +#define SIO_FIFO_ST_OFFSET 0x00000050 +#define SIO_FIFO_ST_BITS 0x0000000f +#define SIO_FIFO_ST_RESET 0x00000002 +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_ROE +// Description : Sticky flag indicating the RX FIFO was read when empty. This +// read was ignored by the FIFO. +#define SIO_FIFO_ST_ROE_RESET 0x0 +#define SIO_FIFO_ST_ROE_BITS 0x00000008 +#define SIO_FIFO_ST_ROE_MSB 3 +#define SIO_FIFO_ST_ROE_LSB 3 +#define SIO_FIFO_ST_ROE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_WOF +// Description : Sticky flag indicating the TX FIFO was written when full. This +// write was ignored by the FIFO. +#define SIO_FIFO_ST_WOF_RESET 0x0 +#define SIO_FIFO_ST_WOF_BITS 0x00000004 +#define SIO_FIFO_ST_WOF_MSB 2 +#define SIO_FIFO_ST_WOF_LSB 2 +#define SIO_FIFO_ST_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_RDY +// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR +// is ready for more data) +#define SIO_FIFO_ST_RDY_RESET 0x1 +#define SIO_FIFO_ST_RDY_BITS 0x00000002 +#define SIO_FIFO_ST_RDY_MSB 1 +#define SIO_FIFO_ST_RDY_LSB 1 +#define SIO_FIFO_ST_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_VLD +// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD +// is valid) +#define SIO_FIFO_ST_VLD_RESET 0x0 +#define SIO_FIFO_ST_VLD_BITS 0x00000001 +#define SIO_FIFO_ST_VLD_MSB 0 +#define SIO_FIFO_ST_VLD_LSB 0 +#define SIO_FIFO_ST_VLD_ACCESS "RO" +// ============================================================================= +// Register : SIO_FIFO_WR +// Description : Write access to this core's TX FIFO +#define SIO_FIFO_WR_OFFSET 0x00000054 +#define SIO_FIFO_WR_BITS 0xffffffff +#define SIO_FIFO_WR_RESET 0x00000000 +#define SIO_FIFO_WR_MSB 31 +#define SIO_FIFO_WR_LSB 0 +#define SIO_FIFO_WR_ACCESS "WF" +// ============================================================================= +// Register : SIO_FIFO_RD +// Description : Read access to this core's RX FIFO +#define SIO_FIFO_RD_OFFSET 0x00000058 +#define SIO_FIFO_RD_BITS 0xffffffff +#define SIO_FIFO_RD_RESET "-" +#define SIO_FIFO_RD_MSB 31 +#define SIO_FIFO_RD_LSB 0 +#define SIO_FIFO_RD_ACCESS "RF" +// ============================================================================= +// Register : SIO_SPINLOCK_ST +// Description : Spinlock state +// A bitmap containing the state of all 32 spinlocks (1=locked). +// Mainly intended for debugging. +#define SIO_SPINLOCK_ST_OFFSET 0x0000005c +#define SIO_SPINLOCK_ST_BITS 0xffffffff +#define SIO_SPINLOCK_ST_RESET 0x00000000 +#define SIO_SPINLOCK_ST_MSB 31 +#define SIO_SPINLOCK_ST_LSB 0 +#define SIO_SPINLOCK_ST_ACCESS "RO" +// ============================================================================= +// Register : SIO_DIV_UDIVIDEND +// Description : Divider unsigned dividend +// Write to the DIVIDEND operand of the divider, i.e. the p in `p +// / q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVIDEND_OFFSET 0x00000060 +#define SIO_DIV_UDIVIDEND_BITS 0xffffffff +#define SIO_DIV_UDIVIDEND_RESET 0x00000000 +#define SIO_DIV_UDIVIDEND_MSB 31 +#define SIO_DIV_UDIVIDEND_LSB 0 +#define SIO_DIV_UDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_UDIVISOR +// Description : Divider unsigned divisor +// Write to the DIVISOR operand of the divider, i.e. the q in `p / +// q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVISOR_OFFSET 0x00000064 +#define SIO_DIV_UDIVISOR_BITS 0xffffffff +#define SIO_DIV_UDIVISOR_RESET 0x00000000 +#define SIO_DIV_UDIVISOR_MSB 31 +#define SIO_DIV_UDIVISOR_LSB 0 +#define SIO_DIV_UDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVIDEND +// Description : Divider signed dividend +// The same as UDIVIDEND, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVIDEND_OFFSET 0x00000068 +#define SIO_DIV_SDIVIDEND_BITS 0xffffffff +#define SIO_DIV_SDIVIDEND_RESET 0x00000000 +#define SIO_DIV_SDIVIDEND_MSB 31 +#define SIO_DIV_SDIVIDEND_LSB 0 +#define SIO_DIV_SDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVISOR +// Description : Divider signed divisor +// The same as UDIVISOR, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVISOR_OFFSET 0x0000006c +#define SIO_DIV_SDIVISOR_BITS 0xffffffff +#define SIO_DIV_SDIVISOR_RESET 0x00000000 +#define SIO_DIV_SDIVISOR_MSB 31 +#define SIO_DIV_SDIVISOR_LSB 0 +#define SIO_DIV_SDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_QUOTIENT +// Description : Divider result quotient +// The result of `DIVIDEND / DIVISOR` (division). Contents +// undefined while CSR_READY is low. +// For signed calculations, QUOTIENT is negative when the signs of +// DIVIDEND and DIVISOR differ. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read +// results in the order +// REMAINDER, QUOTIENT if CSR_DIRTY is used. +#define SIO_DIV_QUOTIENT_OFFSET 0x00000070 +#define SIO_DIV_QUOTIENT_BITS 0xffffffff +#define SIO_DIV_QUOTIENT_RESET 0x00000000 +#define SIO_DIV_QUOTIENT_MSB 31 +#define SIO_DIV_QUOTIENT_LSB 0 +#define SIO_DIV_QUOTIENT_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_REMAINDER +// Description : Divider result remainder +// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined +// while CSR_READY is low. +// For signed calculations, REMAINDER is negative only when +// DIVIDEND is negative. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +#define SIO_DIV_REMAINDER_OFFSET 0x00000074 +#define SIO_DIV_REMAINDER_BITS 0xffffffff +#define SIO_DIV_REMAINDER_RESET 0x00000000 +#define SIO_DIV_REMAINDER_MSB 31 +#define SIO_DIV_REMAINDER_LSB 0 +#define SIO_DIV_REMAINDER_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_CSR +// Description : Control and status register for divider. +#define SIO_DIV_CSR_OFFSET 0x00000078 +#define SIO_DIV_CSR_BITS 0x00000003 +#define SIO_DIV_CSR_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_DIRTY +// Description : Changes to 1 when any register is written, and back to 0 when +// QUOTIENT is read. +// Software can use this flag to make save/restore more efficient +// (skip if not DIRTY). +// If the flag is used in this way, it's recommended to either +// read QUOTIENT only, +// or REMAINDER and then QUOTIENT, to prevent data loss on context +// switch. +#define SIO_DIV_CSR_DIRTY_RESET 0x0 +#define SIO_DIV_CSR_DIRTY_BITS 0x00000002 +#define SIO_DIV_CSR_DIRTY_MSB 1 +#define SIO_DIV_CSR_DIRTY_LSB 1 +#define SIO_DIV_CSR_DIRTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_READY +// Description : Reads as 0 when a calculation is in progress, 1 otherwise. +// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start +// a new calculation, no +// matter if one is already in progress. +// Writing to a result register will immediately terminate any +// in-progress calculation +// and set the READY and DIRTY flags. +#define SIO_DIV_CSR_READY_RESET 0x1 +#define SIO_DIV_CSR_READY_BITS 0x00000001 +#define SIO_DIV_CSR_READY_MSB 0 +#define SIO_DIV_CSR_READY_LSB 0 +#define SIO_DIV_CSR_READY_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP0_ACCUM0_OFFSET 0x00000080 +#define SIO_INTERP0_ACCUM0_BITS 0xffffffff +#define SIO_INTERP0_ACCUM0_RESET 0x00000000 +#define SIO_INTERP0_ACCUM0_MSB 31 +#define SIO_INTERP0_ACCUM0_LSB 0 +#define SIO_INTERP0_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP0_ACCUM1_OFFSET 0x00000084 +#define SIO_INTERP0_ACCUM1_BITS 0xffffffff +#define SIO_INTERP0_ACCUM1_RESET 0x00000000 +#define SIO_INTERP0_ACCUM1_MSB 31 +#define SIO_INTERP0_ACCUM1_LSB 0 +#define SIO_INTERP0_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP0_BASE0_OFFSET 0x00000088 +#define SIO_INTERP0_BASE0_BITS 0xffffffff +#define SIO_INTERP0_BASE0_RESET 0x00000000 +#define SIO_INTERP0_BASE0_MSB 31 +#define SIO_INTERP0_BASE0_LSB 0 +#define SIO_INTERP0_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP0_BASE1_OFFSET 0x0000008c +#define SIO_INTERP0_BASE1_BITS 0xffffffff +#define SIO_INTERP0_BASE1_RESET 0x00000000 +#define SIO_INTERP0_BASE1_MSB 31 +#define SIO_INTERP0_BASE1_LSB 0 +#define SIO_INTERP0_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP0_BASE2_OFFSET 0x00000090 +#define SIO_INTERP0_BASE2_BITS 0xffffffff +#define SIO_INTERP0_BASE2_RESET 0x00000000 +#define SIO_INTERP0_BASE2_MSB 31 +#define SIO_INTERP0_BASE2_LSB 0 +#define SIO_INTERP0_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE0_OFFSET 0x00000094 +#define SIO_INTERP0_POP_LANE0_BITS 0xffffffff +#define SIO_INTERP0_POP_LANE0_RESET 0x00000000 +#define SIO_INTERP0_POP_LANE0_MSB 31 +#define SIO_INTERP0_POP_LANE0_LSB 0 +#define SIO_INTERP0_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE1_OFFSET 0x00000098 +#define SIO_INTERP0_POP_LANE1_BITS 0xffffffff +#define SIO_INTERP0_POP_LANE1_RESET 0x00000000 +#define SIO_INTERP0_POP_LANE1_MSB 31 +#define SIO_INTERP0_POP_LANE1_LSB 0 +#define SIO_INTERP0_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP0_POP_FULL_OFFSET 0x0000009c +#define SIO_INTERP0_POP_FULL_BITS 0xffffffff +#define SIO_INTERP0_POP_FULL_RESET 0x00000000 +#define SIO_INTERP0_POP_FULL_MSB 31 +#define SIO_INTERP0_POP_FULL_LSB 0 +#define SIO_INTERP0_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0 +#define SIO_INTERP0_PEEK_LANE0_BITS 0xffffffff +#define SIO_INTERP0_PEEK_LANE0_RESET 0x00000000 +#define SIO_INTERP0_PEEK_LANE0_MSB 31 +#define SIO_INTERP0_PEEK_LANE0_LSB 0 +#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4 +#define SIO_INTERP0_PEEK_LANE1_BITS 0xffffffff +#define SIO_INTERP0_PEEK_LANE1_RESET 0x00000000 +#define SIO_INTERP0_PEEK_LANE1_MSB 31 +#define SIO_INTERP0_PEEK_LANE1_LSB 0 +#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8 +#define SIO_INTERP0_PEEK_FULL_BITS 0xffffffff +#define SIO_INTERP0_PEEK_FULL_RESET 0x00000000 +#define SIO_INTERP0_PEEK_FULL_MSB 31 +#define SIO_INTERP0_PEEK_FULL_LSB 0 +#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac +#define SIO_INTERP0_CTRL_LANE0_BITS 0x03bfffff +#define SIO_INTERP0_CTRL_LANE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS 0x02000000 +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS 0x01000000 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS 0x00800000 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_BLEND +// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: +// - LANE1 result is a linear interpolation between BASE0 and +// BASE1, controlled +// by the 8 LSBs of lane 1 shift and mask value (a fractional +// number between +// 0 and 255/256ths) +// - LANE0 result does not have BASE0 added (yields only the 8 +// LSBs of lane 1 shift+mask value) +// - FULL result does not have lane 1 shift+mask value added +// (BASE2 + lane 0 shift+mask) +// LANE1 SIGNED flag controls whether the interpolation is signed +// or unsigned. +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS 0x00200000 +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB 20 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS 0x00008000 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB 14 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB 9 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS 0x0000001f +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB 4 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0 +#define SIO_INTERP0_CTRL_LANE1_BITS 0x001fffff +#define SIO_INTERP0_CTRL_LANE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB 20 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS 0x00008000 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB 14 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB 9 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS 0x0000001f +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB 4 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4 +#define SIO_INTERP0_ACCUM0_ADD_BITS 0x00ffffff +#define SIO_INTERP0_ACCUM0_ADD_RESET 0x00000000 +#define SIO_INTERP0_ACCUM0_ADD_MSB 23 +#define SIO_INTERP0_ACCUM0_ADD_LSB 0 +#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8 +#define SIO_INTERP0_ACCUM1_ADD_BITS 0x00ffffff +#define SIO_INTERP0_ACCUM1_ADD_RESET 0x00000000 +#define SIO_INTERP0_ACCUM1_ADD_MSB 23 +#define SIO_INTERP0_ACCUM1_ADD_LSB 0 +#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc +#define SIO_INTERP0_BASE_1AND0_BITS 0xffffffff +#define SIO_INTERP0_BASE_1AND0_RESET 0x00000000 +#define SIO_INTERP0_BASE_1AND0_MSB 31 +#define SIO_INTERP0_BASE_1AND0_LSB 0 +#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP1_ACCUM0_OFFSET 0x000000c0 +#define SIO_INTERP1_ACCUM0_BITS 0xffffffff +#define SIO_INTERP1_ACCUM0_RESET 0x00000000 +#define SIO_INTERP1_ACCUM0_MSB 31 +#define SIO_INTERP1_ACCUM0_LSB 0 +#define SIO_INTERP1_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP1_ACCUM1_OFFSET 0x000000c4 +#define SIO_INTERP1_ACCUM1_BITS 0xffffffff +#define SIO_INTERP1_ACCUM1_RESET 0x00000000 +#define SIO_INTERP1_ACCUM1_MSB 31 +#define SIO_INTERP1_ACCUM1_LSB 0 +#define SIO_INTERP1_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP1_BASE0_OFFSET 0x000000c8 +#define SIO_INTERP1_BASE0_BITS 0xffffffff +#define SIO_INTERP1_BASE0_RESET 0x00000000 +#define SIO_INTERP1_BASE0_MSB 31 +#define SIO_INTERP1_BASE0_LSB 0 +#define SIO_INTERP1_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP1_BASE1_OFFSET 0x000000cc +#define SIO_INTERP1_BASE1_BITS 0xffffffff +#define SIO_INTERP1_BASE1_RESET 0x00000000 +#define SIO_INTERP1_BASE1_MSB 31 +#define SIO_INTERP1_BASE1_LSB 0 +#define SIO_INTERP1_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP1_BASE2_OFFSET 0x000000d0 +#define SIO_INTERP1_BASE2_BITS 0xffffffff +#define SIO_INTERP1_BASE2_RESET 0x00000000 +#define SIO_INTERP1_BASE2_MSB 31 +#define SIO_INTERP1_BASE2_LSB 0 +#define SIO_INTERP1_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4 +#define SIO_INTERP1_POP_LANE0_BITS 0xffffffff +#define SIO_INTERP1_POP_LANE0_RESET 0x00000000 +#define SIO_INTERP1_POP_LANE0_MSB 31 +#define SIO_INTERP1_POP_LANE0_LSB 0 +#define SIO_INTERP1_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8 +#define SIO_INTERP1_POP_LANE1_BITS 0xffffffff +#define SIO_INTERP1_POP_LANE1_RESET 0x00000000 +#define SIO_INTERP1_POP_LANE1_MSB 31 +#define SIO_INTERP1_POP_LANE1_LSB 0 +#define SIO_INTERP1_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP1_POP_FULL_OFFSET 0x000000dc +#define SIO_INTERP1_POP_FULL_BITS 0xffffffff +#define SIO_INTERP1_POP_FULL_RESET 0x00000000 +#define SIO_INTERP1_POP_FULL_MSB 31 +#define SIO_INTERP1_POP_FULL_LSB 0 +#define SIO_INTERP1_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0 +#define SIO_INTERP1_PEEK_LANE0_BITS 0xffffffff +#define SIO_INTERP1_PEEK_LANE0_RESET 0x00000000 +#define SIO_INTERP1_PEEK_LANE0_MSB 31 +#define SIO_INTERP1_PEEK_LANE0_LSB 0 +#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4 +#define SIO_INTERP1_PEEK_LANE1_BITS 0xffffffff +#define SIO_INTERP1_PEEK_LANE1_RESET 0x00000000 +#define SIO_INTERP1_PEEK_LANE1_MSB 31 +#define SIO_INTERP1_PEEK_LANE1_LSB 0 +#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8 +#define SIO_INTERP1_PEEK_FULL_BITS 0xffffffff +#define SIO_INTERP1_PEEK_FULL_RESET 0x00000000 +#define SIO_INTERP1_PEEK_FULL_MSB 31 +#define SIO_INTERP1_PEEK_FULL_LSB 0 +#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec +#define SIO_INTERP1_CTRL_LANE0_BITS 0x03dfffff +#define SIO_INTERP1_CTRL_LANE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS 0x02000000 +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS 0x01000000 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS 0x00800000 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CLAMP +// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: +// - LANE0 result is shifted and masked ACCUM0, clamped by a lower +// bound of +// BASE0 and an upper bound of BASE1. +// - Signedness of these comparisons is determined by +// LANE0_CTRL_SIGNED +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS 0x00400000 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB 20 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS 0x00008000 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB 14 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB 9 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS 0x0000001f +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB 4 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0 +#define SIO_INTERP1_CTRL_LANE1_BITS 0x001fffff +#define SIO_INTERP1_CTRL_LANE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB 20 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS 0x00008000 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB 14 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB 9 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS 0x0000001f +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB 4 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4 +#define SIO_INTERP1_ACCUM0_ADD_BITS 0x00ffffff +#define SIO_INTERP1_ACCUM0_ADD_RESET 0x00000000 +#define SIO_INTERP1_ACCUM0_ADD_MSB 23 +#define SIO_INTERP1_ACCUM0_ADD_LSB 0 +#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8 +#define SIO_INTERP1_ACCUM1_ADD_BITS 0x00ffffff +#define SIO_INTERP1_ACCUM1_ADD_RESET 0x00000000 +#define SIO_INTERP1_ACCUM1_ADD_MSB 23 +#define SIO_INTERP1_ACCUM1_ADD_LSB 0 +#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc +#define SIO_INTERP1_BASE_1AND0_BITS 0xffffffff +#define SIO_INTERP1_BASE_1AND0_RESET 0x00000000 +#define SIO_INTERP1_BASE_1AND0_MSB 31 +#define SIO_INTERP1_BASE_1AND0_LSB 0 +#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_SPINLOCK0 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK0_OFFSET 0x00000100 +#define SIO_SPINLOCK0_BITS 0xffffffff +#define SIO_SPINLOCK0_RESET 0x00000000 +#define SIO_SPINLOCK0_MSB 31 +#define SIO_SPINLOCK0_LSB 0 +#define SIO_SPINLOCK0_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK1 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK1_OFFSET 0x00000104 +#define SIO_SPINLOCK1_BITS 0xffffffff +#define SIO_SPINLOCK1_RESET 0x00000000 +#define SIO_SPINLOCK1_MSB 31 +#define SIO_SPINLOCK1_LSB 0 +#define SIO_SPINLOCK1_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK2 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK2_OFFSET 0x00000108 +#define SIO_SPINLOCK2_BITS 0xffffffff +#define SIO_SPINLOCK2_RESET 0x00000000 +#define SIO_SPINLOCK2_MSB 31 +#define SIO_SPINLOCK2_LSB 0 +#define SIO_SPINLOCK2_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK3 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK3_OFFSET 0x0000010c +#define SIO_SPINLOCK3_BITS 0xffffffff +#define SIO_SPINLOCK3_RESET 0x00000000 +#define SIO_SPINLOCK3_MSB 31 +#define SIO_SPINLOCK3_LSB 0 +#define SIO_SPINLOCK3_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK4 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK4_OFFSET 0x00000110 +#define SIO_SPINLOCK4_BITS 0xffffffff +#define SIO_SPINLOCK4_RESET 0x00000000 +#define SIO_SPINLOCK4_MSB 31 +#define SIO_SPINLOCK4_LSB 0 +#define SIO_SPINLOCK4_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK5 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK5_OFFSET 0x00000114 +#define SIO_SPINLOCK5_BITS 0xffffffff +#define SIO_SPINLOCK5_RESET 0x00000000 +#define SIO_SPINLOCK5_MSB 31 +#define SIO_SPINLOCK5_LSB 0 +#define SIO_SPINLOCK5_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK6 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK6_OFFSET 0x00000118 +#define SIO_SPINLOCK6_BITS 0xffffffff +#define SIO_SPINLOCK6_RESET 0x00000000 +#define SIO_SPINLOCK6_MSB 31 +#define SIO_SPINLOCK6_LSB 0 +#define SIO_SPINLOCK6_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK7 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK7_OFFSET 0x0000011c +#define SIO_SPINLOCK7_BITS 0xffffffff +#define SIO_SPINLOCK7_RESET 0x00000000 +#define SIO_SPINLOCK7_MSB 31 +#define SIO_SPINLOCK7_LSB 0 +#define SIO_SPINLOCK7_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK8 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK8_OFFSET 0x00000120 +#define SIO_SPINLOCK8_BITS 0xffffffff +#define SIO_SPINLOCK8_RESET 0x00000000 +#define SIO_SPINLOCK8_MSB 31 +#define SIO_SPINLOCK8_LSB 0 +#define SIO_SPINLOCK8_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK9 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK9_OFFSET 0x00000124 +#define SIO_SPINLOCK9_BITS 0xffffffff +#define SIO_SPINLOCK9_RESET 0x00000000 +#define SIO_SPINLOCK9_MSB 31 +#define SIO_SPINLOCK9_LSB 0 +#define SIO_SPINLOCK9_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK10 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK10_OFFSET 0x00000128 +#define SIO_SPINLOCK10_BITS 0xffffffff +#define SIO_SPINLOCK10_RESET 0x00000000 +#define SIO_SPINLOCK10_MSB 31 +#define SIO_SPINLOCK10_LSB 0 +#define SIO_SPINLOCK10_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK11 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK11_OFFSET 0x0000012c +#define SIO_SPINLOCK11_BITS 0xffffffff +#define SIO_SPINLOCK11_RESET 0x00000000 +#define SIO_SPINLOCK11_MSB 31 +#define SIO_SPINLOCK11_LSB 0 +#define SIO_SPINLOCK11_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK12 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK12_OFFSET 0x00000130 +#define SIO_SPINLOCK12_BITS 0xffffffff +#define SIO_SPINLOCK12_RESET 0x00000000 +#define SIO_SPINLOCK12_MSB 31 +#define SIO_SPINLOCK12_LSB 0 +#define SIO_SPINLOCK12_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK13 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK13_OFFSET 0x00000134 +#define SIO_SPINLOCK13_BITS 0xffffffff +#define SIO_SPINLOCK13_RESET 0x00000000 +#define SIO_SPINLOCK13_MSB 31 +#define SIO_SPINLOCK13_LSB 0 +#define SIO_SPINLOCK13_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK14 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK14_OFFSET 0x00000138 +#define SIO_SPINLOCK14_BITS 0xffffffff +#define SIO_SPINLOCK14_RESET 0x00000000 +#define SIO_SPINLOCK14_MSB 31 +#define SIO_SPINLOCK14_LSB 0 +#define SIO_SPINLOCK14_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK15 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK15_OFFSET 0x0000013c +#define SIO_SPINLOCK15_BITS 0xffffffff +#define SIO_SPINLOCK15_RESET 0x00000000 +#define SIO_SPINLOCK15_MSB 31 +#define SIO_SPINLOCK15_LSB 0 +#define SIO_SPINLOCK15_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK16 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK16_OFFSET 0x00000140 +#define SIO_SPINLOCK16_BITS 0xffffffff +#define SIO_SPINLOCK16_RESET 0x00000000 +#define SIO_SPINLOCK16_MSB 31 +#define SIO_SPINLOCK16_LSB 0 +#define SIO_SPINLOCK16_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK17 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK17_OFFSET 0x00000144 +#define SIO_SPINLOCK17_BITS 0xffffffff +#define SIO_SPINLOCK17_RESET 0x00000000 +#define SIO_SPINLOCK17_MSB 31 +#define SIO_SPINLOCK17_LSB 0 +#define SIO_SPINLOCK17_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK18 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK18_OFFSET 0x00000148 +#define SIO_SPINLOCK18_BITS 0xffffffff +#define SIO_SPINLOCK18_RESET 0x00000000 +#define SIO_SPINLOCK18_MSB 31 +#define SIO_SPINLOCK18_LSB 0 +#define SIO_SPINLOCK18_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK19 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK19_OFFSET 0x0000014c +#define SIO_SPINLOCK19_BITS 0xffffffff +#define SIO_SPINLOCK19_RESET 0x00000000 +#define SIO_SPINLOCK19_MSB 31 +#define SIO_SPINLOCK19_LSB 0 +#define SIO_SPINLOCK19_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK20 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK20_OFFSET 0x00000150 +#define SIO_SPINLOCK20_BITS 0xffffffff +#define SIO_SPINLOCK20_RESET 0x00000000 +#define SIO_SPINLOCK20_MSB 31 +#define SIO_SPINLOCK20_LSB 0 +#define SIO_SPINLOCK20_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK21 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK21_OFFSET 0x00000154 +#define SIO_SPINLOCK21_BITS 0xffffffff +#define SIO_SPINLOCK21_RESET 0x00000000 +#define SIO_SPINLOCK21_MSB 31 +#define SIO_SPINLOCK21_LSB 0 +#define SIO_SPINLOCK21_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK22 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK22_OFFSET 0x00000158 +#define SIO_SPINLOCK22_BITS 0xffffffff +#define SIO_SPINLOCK22_RESET 0x00000000 +#define SIO_SPINLOCK22_MSB 31 +#define SIO_SPINLOCK22_LSB 0 +#define SIO_SPINLOCK22_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK23 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK23_OFFSET 0x0000015c +#define SIO_SPINLOCK23_BITS 0xffffffff +#define SIO_SPINLOCK23_RESET 0x00000000 +#define SIO_SPINLOCK23_MSB 31 +#define SIO_SPINLOCK23_LSB 0 +#define SIO_SPINLOCK23_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK24 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK24_OFFSET 0x00000160 +#define SIO_SPINLOCK24_BITS 0xffffffff +#define SIO_SPINLOCK24_RESET 0x00000000 +#define SIO_SPINLOCK24_MSB 31 +#define SIO_SPINLOCK24_LSB 0 +#define SIO_SPINLOCK24_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK25 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK25_OFFSET 0x00000164 +#define SIO_SPINLOCK25_BITS 0xffffffff +#define SIO_SPINLOCK25_RESET 0x00000000 +#define SIO_SPINLOCK25_MSB 31 +#define SIO_SPINLOCK25_LSB 0 +#define SIO_SPINLOCK25_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK26 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK26_OFFSET 0x00000168 +#define SIO_SPINLOCK26_BITS 0xffffffff +#define SIO_SPINLOCK26_RESET 0x00000000 +#define SIO_SPINLOCK26_MSB 31 +#define SIO_SPINLOCK26_LSB 0 +#define SIO_SPINLOCK26_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK27 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK27_OFFSET 0x0000016c +#define SIO_SPINLOCK27_BITS 0xffffffff +#define SIO_SPINLOCK27_RESET 0x00000000 +#define SIO_SPINLOCK27_MSB 31 +#define SIO_SPINLOCK27_LSB 0 +#define SIO_SPINLOCK27_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK28 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK28_OFFSET 0x00000170 +#define SIO_SPINLOCK28_BITS 0xffffffff +#define SIO_SPINLOCK28_RESET 0x00000000 +#define SIO_SPINLOCK28_MSB 31 +#define SIO_SPINLOCK28_LSB 0 +#define SIO_SPINLOCK28_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK29 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK29_OFFSET 0x00000174 +#define SIO_SPINLOCK29_BITS 0xffffffff +#define SIO_SPINLOCK29_RESET 0x00000000 +#define SIO_SPINLOCK29_MSB 31 +#define SIO_SPINLOCK29_LSB 0 +#define SIO_SPINLOCK29_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK30 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK30_OFFSET 0x00000178 +#define SIO_SPINLOCK30_BITS 0xffffffff +#define SIO_SPINLOCK30_RESET 0x00000000 +#define SIO_SPINLOCK30_MSB 31 +#define SIO_SPINLOCK30_LSB 0 +#define SIO_SPINLOCK30_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK31 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK31_OFFSET 0x0000017c +#define SIO_SPINLOCK31_BITS 0xffffffff +#define SIO_SPINLOCK31_RESET 0x00000000 +#define SIO_SPINLOCK31_MSB 31 +#define SIO_SPINLOCK31_LSB 0 +#define SIO_SPINLOCK31_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SIO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h new file mode 100644 index 00000000000..9670b830971 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h @@ -0,0 +1,521 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_SPI_DEFINED +#define HARDWARE_REGS_SPI_DEFINED +// ============================================================================= +// Register : SPI_SSPCR0 +// Description : Control register 0, SSPCR0 on page 3-4 +#define SPI_SSPCR0_OFFSET 0x00000000 +#define SPI_SSPCR0_BITS 0x0000ffff +#define SPI_SSPCR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SCR +// Description : Serial clock rate. The value SCR is used to generate the +// transmit and receive bit rate of the PrimeCell SSP. The bit +// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even +// value from 2-254, programmed through the SSPCPSR register and +// SCR is a value from 0-255. +#define SPI_SSPCR0_SCR_RESET 0x00 +#define SPI_SSPCR0_SCR_BITS 0x0000ff00 +#define SPI_SSPCR0_SCR_MSB 15 +#define SPI_SSPCR0_SCR_LSB 8 +#define SPI_SSPCR0_SCR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPH +// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. +// See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPH_RESET 0x0 +#define SPI_SSPCR0_SPH_BITS 0x00000080 +#define SPI_SSPCR0_SPH_MSB 7 +#define SPI_SSPCR0_SPH_LSB 7 +#define SPI_SSPCR0_SPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPO +// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format +// only. See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPO_RESET 0x0 +#define SPI_SSPCR0_SPO_BITS 0x00000040 +#define SPI_SSPCR0_SPO_MSB 6 +#define SPI_SSPCR0_SPO_LSB 6 +#define SPI_SSPCR0_SPO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_FRF +// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous +// serial frame format. 10 National Microwire frame format. 11 +// Reserved, undefined operation. +#define SPI_SSPCR0_FRF_RESET 0x0 +#define SPI_SSPCR0_FRF_BITS 0x00000030 +#define SPI_SSPCR0_FRF_MSB 5 +#define SPI_SSPCR0_FRF_LSB 4 +#define SPI_SSPCR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_DSS +// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 +// Reserved, undefined operation. 0010 Reserved, undefined +// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. +// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit +// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. +// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. +#define SPI_SSPCR0_DSS_RESET 0x0 +#define SPI_SSPCR0_DSS_BITS 0x0000000f +#define SPI_SSPCR0_DSS_MSB 3 +#define SPI_SSPCR0_DSS_LSB 0 +#define SPI_SSPCR0_DSS_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPCR1 +// Description : Control register 1, SSPCR1 on page 3-5 +#define SPI_SSPCR1_OFFSET 0x00000004 +#define SPI_SSPCR1_BITS 0x0000000f +#define SPI_SSPCR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SOD +// Description : Slave-mode output disable. This bit is relevant only in the +// slave mode, MS=1. In multiple-slave systems, it is possible for +// an PrimeCell SSP master to broadcast a message to all slaves in +// the system while ensuring that only one slave drives data onto +// its serial output line. In such systems the RXD lines from +// multiple slaves could be tied together. To operate in such +// systems, the SOD bit can be set if the PrimeCell SSP slave is +// not supposed to drive the SSPTXD line: 0 SSP can drive the +// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD +// output in slave mode. +#define SPI_SSPCR1_SOD_RESET 0x0 +#define SPI_SSPCR1_SOD_BITS 0x00000008 +#define SPI_SSPCR1_SOD_MSB 3 +#define SPI_SSPCR1_SOD_LSB 3 +#define SPI_SSPCR1_SOD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_MS +// Description : Master or slave mode select. This bit can be modified only when +// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as +// master, default. 1 Device configured as slave. +#define SPI_SSPCR1_MS_RESET 0x0 +#define SPI_SSPCR1_MS_BITS 0x00000004 +#define SPI_SSPCR1_MS_MSB 2 +#define SPI_SSPCR1_MS_LSB 2 +#define SPI_SSPCR1_MS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SSE +// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP +// operation enabled. +#define SPI_SSPCR1_SSE_RESET 0x0 +#define SPI_SSPCR1_SSE_BITS 0x00000002 +#define SPI_SSPCR1_SSE_MSB 1 +#define SPI_SSPCR1_SSE_LSB 1 +#define SPI_SSPCR1_SSE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_LBM +// Description : Loop back mode: 0 Normal serial port operation enabled. 1 +// Output of transmit serial shifter is connected to input of +// receive serial shifter internally. +#define SPI_SSPCR1_LBM_RESET 0x0 +#define SPI_SSPCR1_LBM_BITS 0x00000001 +#define SPI_SSPCR1_LBM_MSB 0 +#define SPI_SSPCR1_LBM_LSB 0 +#define SPI_SSPCR1_LBM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPDR +// Description : Data register, SSPDR on page 3-6 +#define SPI_SSPDR_OFFSET 0x00000008 +#define SPI_SSPDR_BITS 0x0000ffff +#define SPI_SSPDR_RESET "-" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDR_DATA +// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. +// You must right-justify data when the PrimeCell SSP is +// programmed for a data size that is less than 16 bits. Unused +// bits at the top are ignored by transmit logic. The receive +// logic automatically right-justifies. +#define SPI_SSPDR_DATA_RESET "-" +#define SPI_SSPDR_DATA_BITS 0x0000ffff +#define SPI_SSPDR_DATA_MSB 15 +#define SPI_SSPDR_DATA_LSB 0 +#define SPI_SSPDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : SPI_SSPSR +// Description : Status register, SSPSR on page 3-7 +#define SPI_SSPSR_OFFSET 0x0000000c +#define SPI_SSPSR_BITS 0x0000001f +#define SPI_SSPSR_RESET 0x00000003 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_BSY +// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently +// transmitting and/or receiving a frame or the transmit FIFO is +// not empty. +#define SPI_SSPSR_BSY_RESET 0x0 +#define SPI_SSPSR_BSY_BITS 0x00000010 +#define SPI_SSPSR_BSY_MSB 4 +#define SPI_SSPSR_BSY_LSB 4 +#define SPI_SSPSR_BSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RFF +// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive +// FIFO is full. +#define SPI_SSPSR_RFF_RESET 0x0 +#define SPI_SSPSR_RFF_BITS 0x00000008 +#define SPI_SSPSR_RFF_MSB 3 +#define SPI_SSPSR_RFF_LSB 3 +#define SPI_SSPSR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RNE +// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive +// FIFO is not empty. +#define SPI_SSPSR_RNE_RESET 0x0 +#define SPI_SSPSR_RNE_BITS 0x00000004 +#define SPI_SSPSR_RNE_MSB 2 +#define SPI_SSPSR_RNE_LSB 2 +#define SPI_SSPSR_RNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TNF +// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit +// FIFO is not full. +#define SPI_SSPSR_TNF_RESET 0x1 +#define SPI_SSPSR_TNF_BITS 0x00000002 +#define SPI_SSPSR_TNF_MSB 1 +#define SPI_SSPSR_TNF_LSB 1 +#define SPI_SSPSR_TNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TFE +// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 +// Transmit FIFO is empty. +#define SPI_SSPSR_TFE_RESET 0x1 +#define SPI_SSPSR_TFE_BITS 0x00000001 +#define SPI_SSPSR_TFE_MSB 0 +#define SPI_SSPSR_TFE_LSB 0 +#define SPI_SSPSR_TFE_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPCPSR +// Description : Clock prescale register, SSPCPSR on page 3-8 +#define SPI_SSPCPSR_OFFSET 0x00000010 +#define SPI_SSPCPSR_BITS 0x000000ff +#define SPI_SSPCPSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCPSR_CPSDVSR +// Description : Clock prescale divisor. Must be an even number from 2-254, +// depending on the frequency of SSPCLK. The least significant bit +// always returns zero on reads. +#define SPI_SSPCPSR_CPSDVSR_RESET 0x00 +#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff +#define SPI_SSPCPSR_CPSDVSR_MSB 7 +#define SPI_SSPCPSR_CPSDVSR_LSB 0 +#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPIMSC +// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 +#define SPI_SSPIMSC_OFFSET 0x00000014 +#define SPI_SSPIMSC_BITS 0x0000000f +#define SPI_SSPIMSC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_TXIM +// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or +// less condition interrupt is masked. 1 Transmit FIFO half empty +// or less condition interrupt is not masked. +#define SPI_SSPIMSC_TXIM_RESET 0x0 +#define SPI_SSPIMSC_TXIM_BITS 0x00000008 +#define SPI_SSPIMSC_TXIM_MSB 3 +#define SPI_SSPIMSC_TXIM_LSB 3 +#define SPI_SSPIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RXIM +// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less +// condition interrupt is masked. 1 Receive FIFO half full or less +// condition interrupt is not masked. +#define SPI_SSPIMSC_RXIM_RESET 0x0 +#define SPI_SSPIMSC_RXIM_BITS 0x00000004 +#define SPI_SSPIMSC_RXIM_MSB 2 +#define SPI_SSPIMSC_RXIM_LSB 2 +#define SPI_SSPIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RTIM +// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no +// read prior to timeout period interrupt is masked. 1 Receive +// FIFO not empty and no read prior to timeout period interrupt is +// not masked. +#define SPI_SSPIMSC_RTIM_RESET 0x0 +#define SPI_SSPIMSC_RTIM_BITS 0x00000002 +#define SPI_SSPIMSC_RTIM_MSB 1 +#define SPI_SSPIMSC_RTIM_LSB 1 +#define SPI_SSPIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RORIM +// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while +// full condition interrupt is masked. 1 Receive FIFO written to +// while full condition interrupt is not masked. +#define SPI_SSPIMSC_RORIM_RESET 0x0 +#define SPI_SSPIMSC_RORIM_BITS 0x00000001 +#define SPI_SSPIMSC_RORIM_MSB 0 +#define SPI_SSPIMSC_RORIM_LSB 0 +#define SPI_SSPIMSC_RORIM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPRIS +// Description : Raw interrupt status register, SSPRIS on page 3-10 +#define SPI_SSPRIS_OFFSET 0x00000018 +#define SPI_SSPRIS_BITS 0x0000000f +#define SPI_SSPRIS_RESET 0x00000008 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_TXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPTXINTR interrupt +#define SPI_SSPRIS_TXRIS_RESET 0x1 +#define SPI_SSPRIS_TXRIS_BITS 0x00000008 +#define SPI_SSPRIS_TXRIS_MSB 3 +#define SPI_SSPRIS_TXRIS_LSB 3 +#define SPI_SSPRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRXINTR interrupt +#define SPI_SSPRIS_RXRIS_RESET 0x0 +#define SPI_SSPRIS_RXRIS_BITS 0x00000004 +#define SPI_SSPRIS_RXRIS_MSB 2 +#define SPI_SSPRIS_RXRIS_LSB 2 +#define SPI_SSPRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RTRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRTINTR interrupt +#define SPI_SSPRIS_RTRIS_RESET 0x0 +#define SPI_SSPRIS_RTRIS_BITS 0x00000002 +#define SPI_SSPRIS_RTRIS_MSB 1 +#define SPI_SSPRIS_RTRIS_LSB 1 +#define SPI_SSPRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RORRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRORINTR interrupt +#define SPI_SSPRIS_RORRIS_RESET 0x0 +#define SPI_SSPRIS_RORRIS_BITS 0x00000001 +#define SPI_SSPRIS_RORRIS_MSB 0 +#define SPI_SSPRIS_RORRIS_LSB 0 +#define SPI_SSPRIS_RORRIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPMIS +// Description : Masked interrupt status register, SSPMIS on page 3-11 +#define SPI_SSPMIS_OFFSET 0x0000001c +#define SPI_SSPMIS_BITS 0x0000000f +#define SPI_SSPMIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_TXMIS +// Description : Gives the transmit FIFO masked interrupt state, after masking, +// of the SSPTXINTR interrupt +#define SPI_SSPMIS_TXMIS_RESET 0x0 +#define SPI_SSPMIS_TXMIS_BITS 0x00000008 +#define SPI_SSPMIS_TXMIS_MSB 3 +#define SPI_SSPMIS_TXMIS_LSB 3 +#define SPI_SSPMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RXMIS +// Description : Gives the receive FIFO masked interrupt state, after masking, +// of the SSPRXINTR interrupt +#define SPI_SSPMIS_RXMIS_RESET 0x0 +#define SPI_SSPMIS_RXMIS_BITS 0x00000004 +#define SPI_SSPMIS_RXMIS_MSB 2 +#define SPI_SSPMIS_RXMIS_LSB 2 +#define SPI_SSPMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RTMIS +// Description : Gives the receive timeout masked interrupt state, after +// masking, of the SSPRTINTR interrupt +#define SPI_SSPMIS_RTMIS_RESET 0x0 +#define SPI_SSPMIS_RTMIS_BITS 0x00000002 +#define SPI_SSPMIS_RTMIS_MSB 1 +#define SPI_SSPMIS_RTMIS_LSB 1 +#define SPI_SSPMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RORMIS +// Description : Gives the receive over run masked interrupt status, after +// masking, of the SSPRORINTR interrupt +#define SPI_SSPMIS_RORMIS_RESET 0x0 +#define SPI_SSPMIS_RORMIS_BITS 0x00000001 +#define SPI_SSPMIS_RORMIS_MSB 0 +#define SPI_SSPMIS_RORMIS_LSB 0 +#define SPI_SSPMIS_RORMIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPICR +// Description : Interrupt clear register, SSPICR on page 3-11 +#define SPI_SSPICR_OFFSET 0x00000020 +#define SPI_SSPICR_BITS 0x00000003 +#define SPI_SSPICR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RTIC +// Description : Clears the SSPRTINTR interrupt +#define SPI_SSPICR_RTIC_RESET 0x0 +#define SPI_SSPICR_RTIC_BITS 0x00000002 +#define SPI_SSPICR_RTIC_MSB 1 +#define SPI_SSPICR_RTIC_LSB 1 +#define SPI_SSPICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RORIC +// Description : Clears the SSPRORINTR interrupt +#define SPI_SSPICR_RORIC_RESET 0x0 +#define SPI_SSPICR_RORIC_BITS 0x00000001 +#define SPI_SSPICR_RORIC_MSB 0 +#define SPI_SSPICR_RORIC_LSB 0 +#define SPI_SSPICR_RORIC_ACCESS "WC" +// ============================================================================= +// Register : SPI_SSPDMACR +// Description : DMA control register, SSPDMACR on page 3-12 +#define SPI_SSPDMACR_OFFSET 0x00000024 +#define SPI_SSPDMACR_BITS 0x00000003 +#define SPI_SSPDMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_TXDMAE +// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define SPI_SSPDMACR_TXDMAE_RESET 0x0 +#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002 +#define SPI_SSPDMACR_TXDMAE_MSB 1 +#define SPI_SSPDMACR_TXDMAE_LSB 1 +#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_RXDMAE +// Description : Receive DMA Enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define SPI_SSPDMACR_RXDMAE_RESET 0x0 +#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001 +#define SPI_SSPDMACR_RXDMAE_MSB 0 +#define SPI_SSPDMACR_RXDMAE_LSB 0 +#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPPERIPHID0 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0 +#define SPI_SSPPERIPHID0_BITS 0x000000ff +#define SPI_SSPPERIPHID0_RESET 0x00000022 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7 +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0 +#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID1 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4 +#define SPI_SSPPERIPHID1_BITS 0x000000ff +#define SPI_SSPPERIPHID1_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0 +#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7 +#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4 +#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3 +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID2 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8 +#define SPI_SSPPERIPHID2_BITS 0x000000ff +#define SPI_SSPPERIPHID2_RESET 0x00000034 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_REVISION +// Description : These bits return the peripheral revision +#define SPI_SSPPERIPHID2_REVISION_RESET 0x3 +#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0 +#define SPI_SSPPERIPHID2_REVISION_MSB 7 +#define SPI_SSPPERIPHID2_REVISION_LSB 4 +#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f +#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3 +#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0 +#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID3 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID3_OFFSET 0x00000fec +#define SPI_SSPPERIPHID3_BITS 0x000000ff +#define SPI_SSPPERIPHID3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7 +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0 +#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID0 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID0_OFFSET 0x00000ff0 +#define SPI_SSPPCELLID0_BITS 0x000000ff +#define SPI_SSPPCELLID0_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID0_SSPPCELLID0 +// Description : These bits read back as 0x0D +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7 +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0 +#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID1 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID1_OFFSET 0x00000ff4 +#define SPI_SSPPCELLID1_BITS 0x000000ff +#define SPI_SSPPCELLID1_RESET 0x000000f0 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID1_SSPPCELLID1 +// Description : These bits read back as 0xF0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0 +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7 +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0 +#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID2 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID2_OFFSET 0x00000ff8 +#define SPI_SSPPCELLID2_BITS 0x000000ff +#define SPI_SSPPCELLID2_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID2_SSPPCELLID2 +// Description : These bits read back as 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7 +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0 +#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID3 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID3_OFFSET 0x00000ffc +#define SPI_SSPPCELLID3_BITS 0x000000ff +#define SPI_SSPPCELLID3_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID3_SSPPCELLID3 +// Description : These bits read back as 0xB1 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1 +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7 +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0 +#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h new file mode 100644 index 00000000000..04eeccaf507 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h @@ -0,0 +1,809 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SSI +// Version : 1 +// Bus type : apb +// Description : DW_apb_ssi has the following features: +// * APB interface – Allows for easy integration into a +// DesignWare Synthesizable Components for AMBA 2 +// implementation. +// * APB3 and APB4 protocol support. +// * Scalable APB data bus width – Supports APB data bus widths +// of 8, 16, and 32 bits. +// * Serial-master or serial-slave operation – Enables serial +// communication with serial-master or serial-slave peripheral +// devices. +// * Programmable Dual/Quad/Octal SPI support in Master Mode. +// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - +// Enables the DW_apb_ssi master to perform operations with the +// device in DDR and RDS modes when working in Dual/Quad/Octal +// mode of operation. +// * Data Mask Support - Enables the DW_apb_ssi to selectively +// update the bytes in the device. This feature is applicable +// only in enhanced SPI modes. +// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi +// master to behave as a memory mapped I/O and fetches the data +// from the device based on the APB read request. This feature +// is applicable only in enhanced SPI modes. +// * DMA Controller Interface – Enables the DW_apb_ssi to +// interface to a DMA controller over the bus using a +// handshaking interface for transfer requests. +// * Independent masking of interrupts – Master collision, +// transmit FIFO overflow, transmit FIFO empty, receive FIFO +// full, receive FIFO underflow, and receive FIFO overflow +// interrupts can all be masked independently. +// * Multi-master contention detection – Informs the processor +// of multiple serial-master accesses on the serial bus. +// * Bypass of meta-stability flip-flops for synchronous clocks +// – When the APB clock (pclk) and the DW_apb_ssi serial clock +// (ssi_clk) are synchronous, meta-stable flip-flops are not +// used when transferring control signals across these clock +// domains. +// * Programmable delay on the sample time of the received +// serial data bit (rxd); enables programmable control of +// routing delays resulting in higher serial data-bit rates. +// * Programmable features: +// - Serial interface operation – Choice of Motorola SPI, Texas +// Instruments Synchronous Serial Protocol or National +// Semiconductor Microwire. +// - Clock bit-rate – Dynamic control of the serial bit rate of +// the data transfer; used in only serial-master mode of +// operation. +// - Data Item size (4 to 32 bits) – Item size of each data +// transfer under the control of the programmer. +// * Configured features: +// - FIFO depth – 16 words deep. The FIFO width is fixed at 32 +// bits. +// - 1 slave select output. +// - Hardware slave-select – Dedicated hardware slave-select +// line. +// - Combined interrupt line - one combined interrupt line from +// the DW_apb_ssi to the interrupt controller. +// - Interrupt polarity – active high interrupt lines. +// - Serial clock polarity – low serial-clock polarity directly +// after reset. +// - Serial clock phase – capture on first edge of serial-clock +// directly after reset. +// ============================================================================= +#ifndef HARDWARE_REGS_SSI_DEFINED +#define HARDWARE_REGS_SSI_DEFINED +// ============================================================================= +// Register : SSI_CTRLR0 +// Description : Control register 0 +#define SSI_CTRLR0_OFFSET 0x00000000 +#define SSI_CTRLR0_BITS 0x017fffff +#define SSI_CTRLR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SSTE +// Description : Slave select toggle enable +#define SSI_CTRLR0_SSTE_RESET 0x0 +#define SSI_CTRLR0_SSTE_BITS 0x01000000 +#define SSI_CTRLR0_SSTE_MSB 24 +#define SSI_CTRLR0_SSTE_LSB 24 +#define SSI_CTRLR0_SSTE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SPI_FRF +// Description : SPI frame format +// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, +// full-duplex +// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex +// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex +#define SSI_CTRLR0_SPI_FRF_RESET 0x0 +#define SSI_CTRLR0_SPI_FRF_BITS 0x00600000 +#define SSI_CTRLR0_SPI_FRF_MSB 22 +#define SSI_CTRLR0_SPI_FRF_LSB 21 +#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" +#define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0 +#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1 +#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_DFS_32 +// Description : Data frame size in 32b transfer mode +// Value of n -> n+1 clocks per frame. +#define SSI_CTRLR0_DFS_32_RESET 0x00 +#define SSI_CTRLR0_DFS_32_BITS 0x001f0000 +#define SSI_CTRLR0_DFS_32_MSB 20 +#define SSI_CTRLR0_DFS_32_LSB 16 +#define SSI_CTRLR0_DFS_32_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_CFS +// Description : Control frame size +// Value of n -> n+1 clocks per frame. +#define SSI_CTRLR0_CFS_RESET 0x0 +#define SSI_CTRLR0_CFS_BITS 0x0000f000 +#define SSI_CTRLR0_CFS_MSB 15 +#define SSI_CTRLR0_CFS_LSB 12 +#define SSI_CTRLR0_CFS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SRL +// Description : Shift register loop (test mode) +#define SSI_CTRLR0_SRL_RESET 0x0 +#define SSI_CTRLR0_SRL_BITS 0x00000800 +#define SSI_CTRLR0_SRL_MSB 11 +#define SSI_CTRLR0_SRL_LSB 11 +#define SSI_CTRLR0_SRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SLV_OE +// Description : Slave output enable +#define SSI_CTRLR0_SLV_OE_RESET 0x0 +#define SSI_CTRLR0_SLV_OE_BITS 0x00000400 +#define SSI_CTRLR0_SLV_OE_MSB 10 +#define SSI_CTRLR0_SLV_OE_LSB 10 +#define SSI_CTRLR0_SLV_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_TMOD +// Description : Transfer mode +// 0x0 -> Both transmit and receive +// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) +// 0x2 -> Receive only (not for FRF == 0, standard SPI mode) +// 0x3 -> EEPROM read mode (TX then RX; RX starts after control +// data TX'd) +#define SSI_CTRLR0_TMOD_RESET 0x0 +#define SSI_CTRLR0_TMOD_BITS 0x00000300 +#define SSI_CTRLR0_TMOD_MSB 9 +#define SSI_CTRLR0_TMOD_LSB 8 +#define SSI_CTRLR0_TMOD_ACCESS "RW" +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1 +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2 +#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SCPOL +// Description : Serial clock polarity +#define SSI_CTRLR0_SCPOL_RESET 0x0 +#define SSI_CTRLR0_SCPOL_BITS 0x00000080 +#define SSI_CTRLR0_SCPOL_MSB 7 +#define SSI_CTRLR0_SCPOL_LSB 7 +#define SSI_CTRLR0_SCPOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SCPH +// Description : Serial clock phase +#define SSI_CTRLR0_SCPH_RESET 0x0 +#define SSI_CTRLR0_SCPH_BITS 0x00000040 +#define SSI_CTRLR0_SCPH_MSB 6 +#define SSI_CTRLR0_SCPH_LSB 6 +#define SSI_CTRLR0_SCPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_FRF +// Description : Frame format +#define SSI_CTRLR0_FRF_RESET 0x0 +#define SSI_CTRLR0_FRF_BITS 0x00000030 +#define SSI_CTRLR0_FRF_MSB 5 +#define SSI_CTRLR0_FRF_LSB 4 +#define SSI_CTRLR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_DFS +// Description : Data frame size +#define SSI_CTRLR0_DFS_RESET 0x0 +#define SSI_CTRLR0_DFS_BITS 0x0000000f +#define SSI_CTRLR0_DFS_MSB 3 +#define SSI_CTRLR0_DFS_LSB 0 +#define SSI_CTRLR0_DFS_ACCESS "RW" +// ============================================================================= +// Register : SSI_CTRLR1 +// Description : Master Control register 1 +#define SSI_CTRLR1_OFFSET 0x00000004 +#define SSI_CTRLR1_BITS 0x0000ffff +#define SSI_CTRLR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR1_NDF +// Description : Number of data frames +#define SSI_CTRLR1_NDF_RESET 0x0000 +#define SSI_CTRLR1_NDF_BITS 0x0000ffff +#define SSI_CTRLR1_NDF_MSB 15 +#define SSI_CTRLR1_NDF_LSB 0 +#define SSI_CTRLR1_NDF_ACCESS "RW" +// ============================================================================= +// Register : SSI_SSIENR +// Description : SSI Enable +#define SSI_SSIENR_OFFSET 0x00000008 +#define SSI_SSIENR_BITS 0x00000001 +#define SSI_SSIENR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SSIENR_SSI_EN +// Description : SSI enable +#define SSI_SSIENR_SSI_EN_RESET 0x0 +#define SSI_SSIENR_SSI_EN_BITS 0x00000001 +#define SSI_SSIENR_SSI_EN_MSB 0 +#define SSI_SSIENR_SSI_EN_LSB 0 +#define SSI_SSIENR_SSI_EN_ACCESS "RW" +// ============================================================================= +// Register : SSI_MWCR +// Description : Microwire Control +#define SSI_MWCR_OFFSET 0x0000000c +#define SSI_MWCR_BITS 0x00000007 +#define SSI_MWCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MHS +// Description : Microwire handshaking +#define SSI_MWCR_MHS_RESET 0x0 +#define SSI_MWCR_MHS_BITS 0x00000004 +#define SSI_MWCR_MHS_MSB 2 +#define SSI_MWCR_MHS_LSB 2 +#define SSI_MWCR_MHS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MDD +// Description : Microwire control +#define SSI_MWCR_MDD_RESET 0x0 +#define SSI_MWCR_MDD_BITS 0x00000002 +#define SSI_MWCR_MDD_MSB 1 +#define SSI_MWCR_MDD_LSB 1 +#define SSI_MWCR_MDD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MWMOD +// Description : Microwire transfer mode +#define SSI_MWCR_MWMOD_RESET 0x0 +#define SSI_MWCR_MWMOD_BITS 0x00000001 +#define SSI_MWCR_MWMOD_MSB 0 +#define SSI_MWCR_MWMOD_LSB 0 +#define SSI_MWCR_MWMOD_ACCESS "RW" +// ============================================================================= +// Register : SSI_SER +// Description : Slave enable +// For each bit: +// 0 -> slave not selected +// 1 -> slave selected +#define SSI_SER_OFFSET 0x00000010 +#define SSI_SER_BITS 0x00000001 +#define SSI_SER_RESET 0x00000000 +#define SSI_SER_MSB 0 +#define SSI_SER_LSB 0 +#define SSI_SER_ACCESS "RW" +// ============================================================================= +// Register : SSI_BAUDR +// Description : Baud rate +#define SSI_BAUDR_OFFSET 0x00000014 +#define SSI_BAUDR_BITS 0x0000ffff +#define SSI_BAUDR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_BAUDR_SCKDV +// Description : SSI clock divider +#define SSI_BAUDR_SCKDV_RESET 0x0000 +#define SSI_BAUDR_SCKDV_BITS 0x0000ffff +#define SSI_BAUDR_SCKDV_MSB 15 +#define SSI_BAUDR_SCKDV_LSB 0 +#define SSI_BAUDR_SCKDV_ACCESS "RW" +// ============================================================================= +// Register : SSI_TXFTLR +// Description : TX FIFO threshold level +#define SSI_TXFTLR_OFFSET 0x00000018 +#define SSI_TXFTLR_BITS 0x000000ff +#define SSI_TXFTLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXFTLR_TFT +// Description : Transmit FIFO threshold +#define SSI_TXFTLR_TFT_RESET 0x00 +#define SSI_TXFTLR_TFT_BITS 0x000000ff +#define SSI_TXFTLR_TFT_MSB 7 +#define SSI_TXFTLR_TFT_LSB 0 +#define SSI_TXFTLR_TFT_ACCESS "RW" +// ============================================================================= +// Register : SSI_RXFTLR +// Description : RX FIFO threshold level +#define SSI_RXFTLR_OFFSET 0x0000001c +#define SSI_RXFTLR_BITS 0x000000ff +#define SSI_RXFTLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RXFTLR_RFT +// Description : Receive FIFO threshold +#define SSI_RXFTLR_RFT_RESET 0x00 +#define SSI_RXFTLR_RFT_BITS 0x000000ff +#define SSI_RXFTLR_RFT_MSB 7 +#define SSI_RXFTLR_RFT_LSB 0 +#define SSI_RXFTLR_RFT_ACCESS "RW" +// ============================================================================= +// Register : SSI_TXFLR +// Description : TX FIFO level +#define SSI_TXFLR_OFFSET 0x00000020 +#define SSI_TXFLR_BITS 0x000000ff +#define SSI_TXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXFLR_TFTFL +// Description : Transmit FIFO level +#define SSI_TXFLR_TFTFL_RESET 0x00 +#define SSI_TXFLR_TFTFL_BITS 0x000000ff +#define SSI_TXFLR_TFTFL_MSB 7 +#define SSI_TXFLR_TFTFL_LSB 0 +#define SSI_TXFLR_TFTFL_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXFLR +// Description : RX FIFO level +#define SSI_RXFLR_OFFSET 0x00000024 +#define SSI_RXFLR_BITS 0x000000ff +#define SSI_RXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RXFLR_RXTFL +// Description : Receive FIFO level +#define SSI_RXFLR_RXTFL_RESET 0x00 +#define SSI_RXFLR_RXTFL_BITS 0x000000ff +#define SSI_RXFLR_RXTFL_MSB 7 +#define SSI_RXFLR_RXTFL_LSB 0 +#define SSI_RXFLR_RXTFL_ACCESS "RO" +// ============================================================================= +// Register : SSI_SR +// Description : Status register +#define SSI_SR_OFFSET 0x00000028 +#define SSI_SR_BITS 0x0000007f +#define SSI_SR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SR_DCOL +// Description : Data collision error +#define SSI_SR_DCOL_RESET 0x0 +#define SSI_SR_DCOL_BITS 0x00000040 +#define SSI_SR_DCOL_MSB 6 +#define SSI_SR_DCOL_LSB 6 +#define SSI_SR_DCOL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TXE +// Description : Transmission error +#define SSI_SR_TXE_RESET 0x0 +#define SSI_SR_TXE_BITS 0x00000020 +#define SSI_SR_TXE_MSB 5 +#define SSI_SR_TXE_LSB 5 +#define SSI_SR_TXE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_RFF +// Description : Receive FIFO full +#define SSI_SR_RFF_RESET 0x0 +#define SSI_SR_RFF_BITS 0x00000010 +#define SSI_SR_RFF_MSB 4 +#define SSI_SR_RFF_LSB 4 +#define SSI_SR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_RFNE +// Description : Receive FIFO not empty +#define SSI_SR_RFNE_RESET 0x0 +#define SSI_SR_RFNE_BITS 0x00000008 +#define SSI_SR_RFNE_MSB 3 +#define SSI_SR_RFNE_LSB 3 +#define SSI_SR_RFNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TFE +// Description : Transmit FIFO empty +#define SSI_SR_TFE_RESET 0x0 +#define SSI_SR_TFE_BITS 0x00000004 +#define SSI_SR_TFE_MSB 2 +#define SSI_SR_TFE_LSB 2 +#define SSI_SR_TFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TFNF +// Description : Transmit FIFO not full +#define SSI_SR_TFNF_RESET 0x0 +#define SSI_SR_TFNF_BITS 0x00000002 +#define SSI_SR_TFNF_MSB 1 +#define SSI_SR_TFNF_LSB 1 +#define SSI_SR_TFNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_BUSY +// Description : SSI busy flag +#define SSI_SR_BUSY_RESET 0x0 +#define SSI_SR_BUSY_BITS 0x00000001 +#define SSI_SR_BUSY_MSB 0 +#define SSI_SR_BUSY_LSB 0 +#define SSI_SR_BUSY_ACCESS "RO" +// ============================================================================= +// Register : SSI_IMR +// Description : Interrupt mask +#define SSI_IMR_OFFSET 0x0000002c +#define SSI_IMR_BITS 0x0000003f +#define SSI_IMR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_MSTIM +// Description : Multi-master contention interrupt mask +#define SSI_IMR_MSTIM_RESET 0x0 +#define SSI_IMR_MSTIM_BITS 0x00000020 +#define SSI_IMR_MSTIM_MSB 5 +#define SSI_IMR_MSTIM_LSB 5 +#define SSI_IMR_MSTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXFIM +// Description : Receive FIFO full interrupt mask +#define SSI_IMR_RXFIM_RESET 0x0 +#define SSI_IMR_RXFIM_BITS 0x00000010 +#define SSI_IMR_RXFIM_MSB 4 +#define SSI_IMR_RXFIM_LSB 4 +#define SSI_IMR_RXFIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXOIM +// Description : Receive FIFO overflow interrupt mask +#define SSI_IMR_RXOIM_RESET 0x0 +#define SSI_IMR_RXOIM_BITS 0x00000008 +#define SSI_IMR_RXOIM_MSB 3 +#define SSI_IMR_RXOIM_LSB 3 +#define SSI_IMR_RXOIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXUIM +// Description : Receive FIFO underflow interrupt mask +#define SSI_IMR_RXUIM_RESET 0x0 +#define SSI_IMR_RXUIM_BITS 0x00000004 +#define SSI_IMR_RXUIM_MSB 2 +#define SSI_IMR_RXUIM_LSB 2 +#define SSI_IMR_RXUIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_TXOIM +// Description : Transmit FIFO overflow interrupt mask +#define SSI_IMR_TXOIM_RESET 0x0 +#define SSI_IMR_TXOIM_BITS 0x00000002 +#define SSI_IMR_TXOIM_MSB 1 +#define SSI_IMR_TXOIM_LSB 1 +#define SSI_IMR_TXOIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_TXEIM +// Description : Transmit FIFO empty interrupt mask +#define SSI_IMR_TXEIM_RESET 0x0 +#define SSI_IMR_TXEIM_BITS 0x00000001 +#define SSI_IMR_TXEIM_MSB 0 +#define SSI_IMR_TXEIM_LSB 0 +#define SSI_IMR_TXEIM_ACCESS "RW" +// ============================================================================= +// Register : SSI_ISR +// Description : Interrupt status +#define SSI_ISR_OFFSET 0x00000030 +#define SSI_ISR_BITS 0x0000003f +#define SSI_ISR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_MSTIS +// Description : Multi-master contention interrupt status +#define SSI_ISR_MSTIS_RESET 0x0 +#define SSI_ISR_MSTIS_BITS 0x00000020 +#define SSI_ISR_MSTIS_MSB 5 +#define SSI_ISR_MSTIS_LSB 5 +#define SSI_ISR_MSTIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXFIS +// Description : Receive FIFO full interrupt status +#define SSI_ISR_RXFIS_RESET 0x0 +#define SSI_ISR_RXFIS_BITS 0x00000010 +#define SSI_ISR_RXFIS_MSB 4 +#define SSI_ISR_RXFIS_LSB 4 +#define SSI_ISR_RXFIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXOIS +// Description : Receive FIFO overflow interrupt status +#define SSI_ISR_RXOIS_RESET 0x0 +#define SSI_ISR_RXOIS_BITS 0x00000008 +#define SSI_ISR_RXOIS_MSB 3 +#define SSI_ISR_RXOIS_LSB 3 +#define SSI_ISR_RXOIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXUIS +// Description : Receive FIFO underflow interrupt status +#define SSI_ISR_RXUIS_RESET 0x0 +#define SSI_ISR_RXUIS_BITS 0x00000004 +#define SSI_ISR_RXUIS_MSB 2 +#define SSI_ISR_RXUIS_LSB 2 +#define SSI_ISR_RXUIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_TXOIS +// Description : Transmit FIFO overflow interrupt status +#define SSI_ISR_TXOIS_RESET 0x0 +#define SSI_ISR_TXOIS_BITS 0x00000002 +#define SSI_ISR_TXOIS_MSB 1 +#define SSI_ISR_TXOIS_LSB 1 +#define SSI_ISR_TXOIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_TXEIS +// Description : Transmit FIFO empty interrupt status +#define SSI_ISR_TXEIS_RESET 0x0 +#define SSI_ISR_TXEIS_BITS 0x00000001 +#define SSI_ISR_TXEIS_MSB 0 +#define SSI_ISR_TXEIS_LSB 0 +#define SSI_ISR_TXEIS_ACCESS "RO" +// ============================================================================= +// Register : SSI_RISR +// Description : Raw interrupt status +#define SSI_RISR_OFFSET 0x00000034 +#define SSI_RISR_BITS 0x0000003f +#define SSI_RISR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_MSTIR +// Description : Multi-master contention raw interrupt status +#define SSI_RISR_MSTIR_RESET 0x0 +#define SSI_RISR_MSTIR_BITS 0x00000020 +#define SSI_RISR_MSTIR_MSB 5 +#define SSI_RISR_MSTIR_LSB 5 +#define SSI_RISR_MSTIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXFIR +// Description : Receive FIFO full raw interrupt status +#define SSI_RISR_RXFIR_RESET 0x0 +#define SSI_RISR_RXFIR_BITS 0x00000010 +#define SSI_RISR_RXFIR_MSB 4 +#define SSI_RISR_RXFIR_LSB 4 +#define SSI_RISR_RXFIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXOIR +// Description : Receive FIFO overflow raw interrupt status +#define SSI_RISR_RXOIR_RESET 0x0 +#define SSI_RISR_RXOIR_BITS 0x00000008 +#define SSI_RISR_RXOIR_MSB 3 +#define SSI_RISR_RXOIR_LSB 3 +#define SSI_RISR_RXOIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXUIR +// Description : Receive FIFO underflow raw interrupt status +#define SSI_RISR_RXUIR_RESET 0x0 +#define SSI_RISR_RXUIR_BITS 0x00000004 +#define SSI_RISR_RXUIR_MSB 2 +#define SSI_RISR_RXUIR_LSB 2 +#define SSI_RISR_RXUIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_TXOIR +// Description : Transmit FIFO overflow raw interrupt status +#define SSI_RISR_TXOIR_RESET 0x0 +#define SSI_RISR_TXOIR_BITS 0x00000002 +#define SSI_RISR_TXOIR_MSB 1 +#define SSI_RISR_TXOIR_LSB 1 +#define SSI_RISR_TXOIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_TXEIR +// Description : Transmit FIFO empty raw interrupt status +#define SSI_RISR_TXEIR_RESET 0x0 +#define SSI_RISR_TXEIR_BITS 0x00000001 +#define SSI_RISR_TXEIR_MSB 0 +#define SSI_RISR_TXEIR_LSB 0 +#define SSI_RISR_TXEIR_ACCESS "RO" +// ============================================================================= +// Register : SSI_TXOICR +// Description : TX FIFO overflow interrupt clear +// Clear-on-read transmit FIFO overflow interrupt +#define SSI_TXOICR_OFFSET 0x00000038 +#define SSI_TXOICR_BITS 0x00000001 +#define SSI_TXOICR_RESET 0x00000000 +#define SSI_TXOICR_MSB 0 +#define SSI_TXOICR_LSB 0 +#define SSI_TXOICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXOICR +// Description : RX FIFO overflow interrupt clear +// Clear-on-read receive FIFO overflow interrupt +#define SSI_RXOICR_OFFSET 0x0000003c +#define SSI_RXOICR_BITS 0x00000001 +#define SSI_RXOICR_RESET 0x00000000 +#define SSI_RXOICR_MSB 0 +#define SSI_RXOICR_LSB 0 +#define SSI_RXOICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXUICR +// Description : RX FIFO underflow interrupt clear +// Clear-on-read receive FIFO underflow interrupt +#define SSI_RXUICR_OFFSET 0x00000040 +#define SSI_RXUICR_BITS 0x00000001 +#define SSI_RXUICR_RESET 0x00000000 +#define SSI_RXUICR_MSB 0 +#define SSI_RXUICR_LSB 0 +#define SSI_RXUICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_MSTICR +// Description : Multi-master interrupt clear +// Clear-on-read multi-master contention interrupt +#define SSI_MSTICR_OFFSET 0x00000044 +#define SSI_MSTICR_BITS 0x00000001 +#define SSI_MSTICR_RESET 0x00000000 +#define SSI_MSTICR_MSB 0 +#define SSI_MSTICR_LSB 0 +#define SSI_MSTICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_ICR +// Description : Interrupt clear +// Clear-on-read all active interrupts +#define SSI_ICR_OFFSET 0x00000048 +#define SSI_ICR_BITS 0x00000001 +#define SSI_ICR_RESET 0x00000000 +#define SSI_ICR_MSB 0 +#define SSI_ICR_LSB 0 +#define SSI_ICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_DMACR +// Description : DMA control +#define SSI_DMACR_OFFSET 0x0000004c +#define SSI_DMACR_BITS 0x00000003 +#define SSI_DMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMACR_TDMAE +// Description : Transmit DMA enable +#define SSI_DMACR_TDMAE_RESET 0x0 +#define SSI_DMACR_TDMAE_BITS 0x00000002 +#define SSI_DMACR_TDMAE_MSB 1 +#define SSI_DMACR_TDMAE_LSB 1 +#define SSI_DMACR_TDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_DMACR_RDMAE +// Description : Receive DMA enable +#define SSI_DMACR_RDMAE_RESET 0x0 +#define SSI_DMACR_RDMAE_BITS 0x00000001 +#define SSI_DMACR_RDMAE_MSB 0 +#define SSI_DMACR_RDMAE_LSB 0 +#define SSI_DMACR_RDMAE_ACCESS "RW" +// ============================================================================= +// Register : SSI_DMATDLR +// Description : DMA TX data level +#define SSI_DMATDLR_OFFSET 0x00000050 +#define SSI_DMATDLR_BITS 0x000000ff +#define SSI_DMATDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMATDLR_DMATDL +// Description : Transmit data watermark level +#define SSI_DMATDLR_DMATDL_RESET 0x00 +#define SSI_DMATDLR_DMATDL_BITS 0x000000ff +#define SSI_DMATDLR_DMATDL_MSB 7 +#define SSI_DMATDLR_DMATDL_LSB 0 +#define SSI_DMATDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : SSI_DMARDLR +// Description : DMA RX data level +#define SSI_DMARDLR_OFFSET 0x00000054 +#define SSI_DMARDLR_BITS 0x000000ff +#define SSI_DMARDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMARDLR_DMARDL +// Description : Receive data watermark level (DMARDLR+1) +#define SSI_DMARDLR_DMARDL_RESET 0x00 +#define SSI_DMARDLR_DMARDL_BITS 0x000000ff +#define SSI_DMARDLR_DMARDL_MSB 7 +#define SSI_DMARDLR_DMARDL_LSB 0 +#define SSI_DMARDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : SSI_IDR +// Description : Identification register +#define SSI_IDR_OFFSET 0x00000058 +#define SSI_IDR_BITS 0xffffffff +#define SSI_IDR_RESET 0x51535049 +// ----------------------------------------------------------------------------- +// Field : SSI_IDR_IDCODE +// Description : Peripheral dentification code +#define SSI_IDR_IDCODE_RESET 0x51535049 +#define SSI_IDR_IDCODE_BITS 0xffffffff +#define SSI_IDR_IDCODE_MSB 31 +#define SSI_IDR_IDCODE_LSB 0 +#define SSI_IDR_IDCODE_ACCESS "RO" +// ============================================================================= +// Register : SSI_SSI_VERSION_ID +// Description : Version ID +#define SSI_SSI_VERSION_ID_OFFSET 0x0000005c +#define SSI_SSI_VERSION_ID_BITS 0xffffffff +#define SSI_SSI_VERSION_ID_RESET 0x3430312a +// ----------------------------------------------------------------------------- +// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION +// Description : SNPS component version (format X.YY) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : SSI_DR0 +// Description : Data Register 0 (of 36) +#define SSI_DR0_OFFSET 0x00000060 +#define SSI_DR0_BITS 0xffffffff +#define SSI_DR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DR0_DR +// Description : First data register of 36 +#define SSI_DR0_DR_RESET 0x00000000 +#define SSI_DR0_DR_BITS 0xffffffff +#define SSI_DR0_DR_MSB 31 +#define SSI_DR0_DR_LSB 0 +#define SSI_DR0_DR_ACCESS "RW" +// ============================================================================= +// Register : SSI_RX_SAMPLE_DLY +// Description : RX sample delay +#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 +#define SSI_RX_SAMPLE_DLY_BITS 0x000000ff +#define SSI_RX_SAMPLE_DLY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RX_SAMPLE_DLY_RSD +// Description : RXD sample delay (in SCLK cycles) +#define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00 +#define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff +#define SSI_RX_SAMPLE_DLY_RSD_MSB 7 +#define SSI_RX_SAMPLE_DLY_RSD_LSB 0 +#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" +// ============================================================================= +// Register : SSI_SPI_CTRLR0 +// Description : SPI control +#define SSI_SPI_CTRLR0_OFFSET 0x000000f4 +#define SSI_SPI_CTRLR0_BITS 0xff07fb3f +#define SSI_SPI_CTRLR0_RESET 0x03000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_XIP_CMD +// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append +// to Address (INST_L = 0-bit) +#define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03 +#define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000 +#define SSI_SPI_CTRLR0_XIP_CMD_MSB 31 +#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 +#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN +// Description : Read data strobe enable +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_INST_DDR_EN +// Description : Instruction DDR transfer enable +#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000 +#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_SPI_DDR_EN +// Description : SPI DDR transfer enable +#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_WAIT_CYCLES +// Description : Wait cycles between control frame transmit and data reception +// (in SCLK cycles) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_INST_L +// Description : Instruction length (0/4/8/16b) +// 0x0 -> No instruction +// 0x1 -> 4-bit instruction +// 0x2 -> 8-bit instruction +// 0x3 -> 16-bit instruction +#define SSI_SPI_CTRLR0_INST_L_RESET 0x0 +#define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300 +#define SSI_SPI_CTRLR0_INST_L_MSB 9 +#define SSI_SPI_CTRLR0_INST_L_LSB 8 +#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" +#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1 +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3 +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_ADDR_L +// Description : Address length (0b-60b in 4b increments) +#define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0 +#define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c +#define SSI_SPI_CTRLR0_ADDR_L_MSB 5 +#define SSI_SPI_CTRLR0_ADDR_L_LSB 2 +#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_TRANS_TYPE +// Description : Address and instruction transfer format +// 0x0 -> Command and address both in standard SPI frame format +// 0x1 -> Command in standard SPI format, address in format +// specified by FRF +// 0x2 -> Command and address both in format specified by FRF +// (e.g. Dual-SPI) +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003 +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1 +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 +// ============================================================================= +// Register : SSI_TXD_DRIVE_EDGE +// Description : TX drive edge +#define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8 +#define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff +#define SSI_TXD_DRIVE_EDGE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXD_DRIVE_EDGE_TDE +// Description : TXD drive edge +#define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00 +#define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff +#define SSI_TXD_DRIVE_EDGE_TDE_MSB 7 +#define SSI_TXD_DRIVE_EDGE_TDE_LSB 0 +#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_SSI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h new file mode 100644 index 00000000000..c1bcaf9dc8b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h @@ -0,0 +1,257 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSCFG +// Version : 1 +// Bus type : apb +// Description : Register block for various chip control signals +// ============================================================================= +#ifndef HARDWARE_REGS_SYSCFG_DEFINED +#define HARDWARE_REGS_SYSCFG_DEFINED +// ============================================================================= +// Register : SYSCFG_PROC0_NMI_MASK +// Description : Processor core 0 NMI source mask +// Set a bit high to enable NMI from that IRQ +#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000 +#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff +#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000 +#define SYSCFG_PROC0_NMI_MASK_MSB 31 +#define SYSCFG_PROC0_NMI_MASK_LSB 0 +#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC1_NMI_MASK +// Description : Processor core 1 NMI source mask +// Set a bit high to enable NMI from that IRQ +#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004 +#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff +#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000 +#define SYSCFG_PROC1_NMI_MASK_MSB 31 +#define SYSCFG_PROC1_NMI_MASK_LSB 0 +#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_CONFIG +// Description : Configuration for processors +#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008 +#define SYSCFG_PROC_CONFIG_BITS 0xff000003 +#define SYSCFG_PROC_CONFIG_RESET 0x10000000 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID +// Description : Configure proc1 DAP instance ID. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +// WARNING: do not set to 15 as this is reserved for RescueDP +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID +// Description : Configure proc0 DAP instance ID. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +// WARNING: do not set to 15 as this is reserved for RescueDP +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED +// Description : Indication that proc1 has halted +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED +// Description : Indication that proc0 has halted +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 0...29. +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000 +#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29 +#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 30...35 (the QSPI IOs). +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_DBGFORCE +// Description : Directly control the SWD debug port of either processor +#define SYSCFG_DBGFORCE_OFFSET 0x00000014 +#define SYSCFG_DBGFORCE_BITS 0x000000ff +#define SYSCFG_DBGFORCE_RESET 0x00000066 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_ATTACH +// Description : Attach processor 1 debug port to syscfg controls, and +// disconnect it from external SWD pads. +#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWCLK +// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set +#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWDI +// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set +#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020 +#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWDO +// Description : Observe the value of processor 1 SWDIO output. +#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010 +#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_ATTACH +// Description : Attach processor 0 debug port to syscfg controls, and +// disconnect it from external SWD pads. +#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWCLK +// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set +#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWDI +// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set +#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002 +#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWDO +// Description : Observe the value of processor 0 SWDIO output. +#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001 +#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_MEMPOWERDOWN +// Description : Control power downs to memories. Set high to power down +// memories. +// Use with extreme caution +#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018 +#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff +#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_ROM +// Description : None +#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080 +#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_USB +// Description : None +#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040 +#define SYSCFG_MEMPOWERDOWN_USB_MSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_LSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM5 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020 +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM4 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010 +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM3 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008 +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM2 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004 +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM1 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002 +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM0 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001 +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_SYSCFG_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h new file mode 100644 index 00000000000..7a460374c05 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h @@ -0,0 +1,77 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSINFO +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_SYSINFO_DEFINED +#define HARDWARE_REGS_SYSINFO_DEFINED +// ============================================================================= +// Register : SYSINFO_CHIP_ID +// Description : JEDEC JEP-106 compliant chip identifier. +#define SYSINFO_CHIP_ID_OFFSET 0x00000000 +#define SYSINFO_CHIP_ID_BITS 0xffffffff +#define SYSINFO_CHIP_ID_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_REVISION +// Description : None +#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000 +#define SYSINFO_CHIP_ID_REVISION_MSB 31 +#define SYSINFO_CHIP_ID_REVISION_LSB 28 +#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_PART +// Description : None +#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000 +#define SYSINFO_CHIP_ID_PART_MSB 27 +#define SYSINFO_CHIP_ID_PART_LSB 12 +#define SYSINFO_CHIP_ID_PART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_MANUFACTURER +// Description : None +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11 +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0 +#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PLATFORM +// Description : Platform register. Allows software to know what environment it +// is running in. +#define SYSINFO_PLATFORM_OFFSET 0x00000004 +#define SYSINFO_PLATFORM_BITS 0x00000003 +#define SYSINFO_PLATFORM_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_ASIC +// Description : None +#define SYSINFO_PLATFORM_ASIC_RESET 0x0 +#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002 +#define SYSINFO_PLATFORM_ASIC_MSB 1 +#define SYSINFO_PLATFORM_ASIC_LSB 1 +#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_FPGA +// Description : None +#define SYSINFO_PLATFORM_FPGA_RESET 0x0 +#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001 +#define SYSINFO_PLATFORM_FPGA_MSB 0 +#define SYSINFO_PLATFORM_FPGA_LSB 0 +#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_GITREF_RP2040 +// Description : Git hash of the chip source. Used to identify chip version. +#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040 +#define SYSINFO_GITREF_RP2040_BITS 0xffffffff +#define SYSINFO_GITREF_RP2040_RESET "-" +#define SYSINFO_GITREF_RP2040_MSB 31 +#define SYSINFO_GITREF_RP2040_LSB 0 +#define SYSINFO_GITREF_RP2040_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SYSINFO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h new file mode 100644 index 00000000000..6bf9b2959bd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h @@ -0,0 +1,38 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TBMAN +// Version : 1 +// Bus type : apb +// Description : Testbench manager. Allows the programmer to know what +// platform their software is running on. +// ============================================================================= +#ifndef HARDWARE_REGS_TBMAN_DEFINED +#define HARDWARE_REGS_TBMAN_DEFINED +// ============================================================================= +// Register : TBMAN_PLATFORM +// Description : Indicates the type of platform in use +#define TBMAN_PLATFORM_OFFSET 0x00000000 +#define TBMAN_PLATFORM_BITS 0x00000003 +#define TBMAN_PLATFORM_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_FPGA +// Description : Indicates the platform is an FPGA +#define TBMAN_PLATFORM_FPGA_RESET 0x0 +#define TBMAN_PLATFORM_FPGA_BITS 0x00000002 +#define TBMAN_PLATFORM_FPGA_MSB 1 +#define TBMAN_PLATFORM_FPGA_LSB 1 +#define TBMAN_PLATFORM_FPGA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_ASIC +// Description : Indicates the platform is an ASIC +#define TBMAN_PLATFORM_ASIC_RESET 0x1 +#define TBMAN_PLATFORM_ASIC_BITS 0x00000001 +#define TBMAN_PLATFORM_ASIC_MSB 0 +#define TBMAN_PLATFORM_ASIC_LSB 0 +#define TBMAN_PLATFORM_ASIC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_TBMAN_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h new file mode 100644 index 00000000000..a2209b690a9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h @@ -0,0 +1,332 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TIMER +// Version : 1 +// Bus type : apb +// Description : Controls time and alarms +// time is a 64 bit value indicating the time in usec since +// power-on +// timeh is the top 32 bits of time & timel is the bottom 32 +// bits +// to change time write to timelw before timehw +// to read time read from timelr before timehr +// An alarm is set by setting alarm_enable and writing to the +// corresponding alarm register +// When an alarm is pending, the corresponding alarm_running +// signal will be high +// An alarm can be cancelled before it has finished by clearing +// the alarm_enable +// When an alarm fires, the corresponding alarm_irq is set and +// alarm_running is cleared +// To clear the interrupt write a 1 to the corresponding +// alarm_irq +// ============================================================================= +#ifndef HARDWARE_REGS_TIMER_DEFINED +#define HARDWARE_REGS_TIMER_DEFINED +// ============================================================================= +// Register : TIMER_TIMEHW +// Description : Write to bits 63:32 of time +// always write timelw before timehw +#define TIMER_TIMEHW_OFFSET 0x00000000 +#define TIMER_TIMEHW_BITS 0xffffffff +#define TIMER_TIMEHW_RESET 0x00000000 +#define TIMER_TIMEHW_MSB 31 +#define TIMER_TIMEHW_LSB 0 +#define TIMER_TIMEHW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMELW +// Description : Write to bits 31:0 of time +// writes do not get copied to time until timehw is written +#define TIMER_TIMELW_OFFSET 0x00000004 +#define TIMER_TIMELW_BITS 0xffffffff +#define TIMER_TIMELW_RESET 0x00000000 +#define TIMER_TIMELW_MSB 31 +#define TIMER_TIMELW_LSB 0 +#define TIMER_TIMELW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMEHR +// Description : Read from bits 63:32 of time +// always read timelr before timehr +#define TIMER_TIMEHR_OFFSET 0x00000008 +#define TIMER_TIMEHR_BITS 0xffffffff +#define TIMER_TIMEHR_RESET 0x00000000 +#define TIMER_TIMEHR_MSB 31 +#define TIMER_TIMEHR_LSB 0 +#define TIMER_TIMEHR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMELR +// Description : Read from bits 31:0 of time +#define TIMER_TIMELR_OFFSET 0x0000000c +#define TIMER_TIMELR_BITS 0xffffffff +#define TIMER_TIMELR_RESET 0x00000000 +#define TIMER_TIMELR_MSB 31 +#define TIMER_TIMELR_LSB 0 +#define TIMER_TIMELR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_ALARM0 +// Description : Arm alarm 0, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM0_OFFSET 0x00000010 +#define TIMER_ALARM0_BITS 0xffffffff +#define TIMER_ALARM0_RESET 0x00000000 +#define TIMER_ALARM0_MSB 31 +#define TIMER_ALARM0_LSB 0 +#define TIMER_ALARM0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM1 +// Description : Arm alarm 1, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM1_OFFSET 0x00000014 +#define TIMER_ALARM1_BITS 0xffffffff +#define TIMER_ALARM1_RESET 0x00000000 +#define TIMER_ALARM1_MSB 31 +#define TIMER_ALARM1_LSB 0 +#define TIMER_ALARM1_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM2 +// Description : Arm alarm 2, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM2_OFFSET 0x00000018 +#define TIMER_ALARM2_BITS 0xffffffff +#define TIMER_ALARM2_RESET 0x00000000 +#define TIMER_ALARM2_MSB 31 +#define TIMER_ALARM2_LSB 0 +#define TIMER_ALARM2_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM3 +// Description : Arm alarm 3, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM3_OFFSET 0x0000001c +#define TIMER_ALARM3_BITS 0xffffffff +#define TIMER_ALARM3_RESET 0x00000000 +#define TIMER_ALARM3_MSB 31 +#define TIMER_ALARM3_LSB 0 +#define TIMER_ALARM3_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ARMED +// Description : Indicates the armed/disarmed status of each alarm. +// A write to the corresponding ALARMx register arms the alarm. +// Alarms automatically disarm upon firing, but writing ones here +// will disarm immediately without waiting to fire. +#define TIMER_ARMED_OFFSET 0x00000020 +#define TIMER_ARMED_BITS 0x0000000f +#define TIMER_ARMED_RESET 0x00000000 +#define TIMER_ARMED_MSB 3 +#define TIMER_ARMED_LSB 0 +#define TIMER_ARMED_ACCESS "WC" +// ============================================================================= +// Register : TIMER_TIMERAWH +// Description : Raw read from bits 63:32 of time (no side effects) +#define TIMER_TIMERAWH_OFFSET 0x00000024 +#define TIMER_TIMERAWH_BITS 0xffffffff +#define TIMER_TIMERAWH_RESET 0x00000000 +#define TIMER_TIMERAWH_MSB 31 +#define TIMER_TIMERAWH_LSB 0 +#define TIMER_TIMERAWH_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMERAWL +// Description : Raw read from bits 31:0 of time (no side effects) +#define TIMER_TIMERAWL_OFFSET 0x00000028 +#define TIMER_TIMERAWL_BITS 0xffffffff +#define TIMER_TIMERAWL_RESET 0x00000000 +#define TIMER_TIMERAWL_MSB 31 +#define TIMER_TIMERAWL_LSB 0 +#define TIMER_TIMERAWL_ACCESS "RO" +// ============================================================================= +// Register : TIMER_DBGPAUSE +// Description : Set bits high to enable pause when the corresponding debug +// ports are active +#define TIMER_DBGPAUSE_OFFSET 0x0000002c +#define TIMER_DBGPAUSE_BITS 0x00000006 +#define TIMER_DBGPAUSE_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG1 +// Description : Pause when processor 1 is in debug mode +#define TIMER_DBGPAUSE_DBG1_RESET 0x1 +#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004 +#define TIMER_DBGPAUSE_DBG1_MSB 2 +#define TIMER_DBGPAUSE_DBG1_LSB 2 +#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG0 +// Description : Pause when processor 0 is in debug mode +#define TIMER_DBGPAUSE_DBG0_RESET 0x1 +#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002 +#define TIMER_DBGPAUSE_DBG0_MSB 1 +#define TIMER_DBGPAUSE_DBG0_LSB 1 +#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_PAUSE +// Description : Set high to pause the timer +#define TIMER_PAUSE_OFFSET 0x00000030 +#define TIMER_PAUSE_BITS 0x00000001 +#define TIMER_PAUSE_RESET 0x00000000 +#define TIMER_PAUSE_MSB 0 +#define TIMER_PAUSE_LSB 0 +#define TIMER_PAUSE_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTR +// Description : Raw Interrupts +#define TIMER_INTR_OFFSET 0x00000034 +#define TIMER_INTR_BITS 0x0000000f +#define TIMER_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_3 +// Description : None +#define TIMER_INTR_ALARM_3_RESET 0x0 +#define TIMER_INTR_ALARM_3_BITS 0x00000008 +#define TIMER_INTR_ALARM_3_MSB 3 +#define TIMER_INTR_ALARM_3_LSB 3 +#define TIMER_INTR_ALARM_3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_2 +// Description : None +#define TIMER_INTR_ALARM_2_RESET 0x0 +#define TIMER_INTR_ALARM_2_BITS 0x00000004 +#define TIMER_INTR_ALARM_2_MSB 2 +#define TIMER_INTR_ALARM_2_LSB 2 +#define TIMER_INTR_ALARM_2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_1 +// Description : None +#define TIMER_INTR_ALARM_1_RESET 0x0 +#define TIMER_INTR_ALARM_1_BITS 0x00000002 +#define TIMER_INTR_ALARM_1_MSB 1 +#define TIMER_INTR_ALARM_1_LSB 1 +#define TIMER_INTR_ALARM_1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_0 +// Description : None +#define TIMER_INTR_ALARM_0_RESET 0x0 +#define TIMER_INTR_ALARM_0_BITS 0x00000001 +#define TIMER_INTR_ALARM_0_MSB 0 +#define TIMER_INTR_ALARM_0_LSB 0 +#define TIMER_INTR_ALARM_0_ACCESS "WC" +// ============================================================================= +// Register : TIMER_INTE +// Description : Interrupt Enable +#define TIMER_INTE_OFFSET 0x00000038 +#define TIMER_INTE_BITS 0x0000000f +#define TIMER_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_3 +// Description : None +#define TIMER_INTE_ALARM_3_RESET 0x0 +#define TIMER_INTE_ALARM_3_BITS 0x00000008 +#define TIMER_INTE_ALARM_3_MSB 3 +#define TIMER_INTE_ALARM_3_LSB 3 +#define TIMER_INTE_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_2 +// Description : None +#define TIMER_INTE_ALARM_2_RESET 0x0 +#define TIMER_INTE_ALARM_2_BITS 0x00000004 +#define TIMER_INTE_ALARM_2_MSB 2 +#define TIMER_INTE_ALARM_2_LSB 2 +#define TIMER_INTE_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_1 +// Description : None +#define TIMER_INTE_ALARM_1_RESET 0x0 +#define TIMER_INTE_ALARM_1_BITS 0x00000002 +#define TIMER_INTE_ALARM_1_MSB 1 +#define TIMER_INTE_ALARM_1_LSB 1 +#define TIMER_INTE_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_0 +// Description : None +#define TIMER_INTE_ALARM_0_RESET 0x0 +#define TIMER_INTE_ALARM_0_BITS 0x00000001 +#define TIMER_INTE_ALARM_0_MSB 0 +#define TIMER_INTE_ALARM_0_LSB 0 +#define TIMER_INTE_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTF +// Description : Interrupt Force +#define TIMER_INTF_OFFSET 0x0000003c +#define TIMER_INTF_BITS 0x0000000f +#define TIMER_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_3 +// Description : None +#define TIMER_INTF_ALARM_3_RESET 0x0 +#define TIMER_INTF_ALARM_3_BITS 0x00000008 +#define TIMER_INTF_ALARM_3_MSB 3 +#define TIMER_INTF_ALARM_3_LSB 3 +#define TIMER_INTF_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_2 +// Description : None +#define TIMER_INTF_ALARM_2_RESET 0x0 +#define TIMER_INTF_ALARM_2_BITS 0x00000004 +#define TIMER_INTF_ALARM_2_MSB 2 +#define TIMER_INTF_ALARM_2_LSB 2 +#define TIMER_INTF_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_1 +// Description : None +#define TIMER_INTF_ALARM_1_RESET 0x0 +#define TIMER_INTF_ALARM_1_BITS 0x00000002 +#define TIMER_INTF_ALARM_1_MSB 1 +#define TIMER_INTF_ALARM_1_LSB 1 +#define TIMER_INTF_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_0 +// Description : None +#define TIMER_INTF_ALARM_0_RESET 0x0 +#define TIMER_INTF_ALARM_0_BITS 0x00000001 +#define TIMER_INTF_ALARM_0_MSB 0 +#define TIMER_INTF_ALARM_0_LSB 0 +#define TIMER_INTF_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTS +// Description : Interrupt status after masking & forcing +#define TIMER_INTS_OFFSET 0x00000040 +#define TIMER_INTS_BITS 0x0000000f +#define TIMER_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_3 +// Description : None +#define TIMER_INTS_ALARM_3_RESET 0x0 +#define TIMER_INTS_ALARM_3_BITS 0x00000008 +#define TIMER_INTS_ALARM_3_MSB 3 +#define TIMER_INTS_ALARM_3_LSB 3 +#define TIMER_INTS_ALARM_3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_2 +// Description : None +#define TIMER_INTS_ALARM_2_RESET 0x0 +#define TIMER_INTS_ALARM_2_BITS 0x00000004 +#define TIMER_INTS_ALARM_2_MSB 2 +#define TIMER_INTS_ALARM_2_LSB 2 +#define TIMER_INTS_ALARM_2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_1 +// Description : None +#define TIMER_INTS_ALARM_1_RESET 0x0 +#define TIMER_INTS_ALARM_1_BITS 0x00000002 +#define TIMER_INTS_ALARM_1_MSB 1 +#define TIMER_INTS_ALARM_1_LSB 1 +#define TIMER_INTS_ALARM_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_0 +// Description : None +#define TIMER_INTS_ALARM_0_RESET 0x0 +#define TIMER_INTS_ALARM_0_BITS 0x00000001 +#define TIMER_INTS_ALARM_0_MSB 0 +#define TIMER_INTS_ALARM_0_LSB 0 +#define TIMER_INTS_ALARM_0_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_TIMER_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h new file mode 100644 index 00000000000..8fde5d19738 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h @@ -0,0 +1,1148 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : UART +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_UART_DEFINED +#define HARDWARE_REGS_UART_DEFINED +// ============================================================================= +// Register : UART_UARTDR +// Description : Data Register, UARTDR +#define UART_UARTDR_OFFSET 0x00000000 +#define UART_UARTDR_BITS 0x00000fff +#define UART_UARTDR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// receive FIFO is already full. This is cleared to 0 once there +// is an empty space in the FIFO and a new character can be +// written to it. +#define UART_UARTDR_OE_RESET "-" +#define UART_UARTDR_OE_BITS 0x00000800 +#define UART_UARTDR_OE_MSB 11 +#define UART_UARTDR_OE_LSB 11 +#define UART_UARTDR_OE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity and stop bits). In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state), and the next valid start bit is +// received. +#define UART_UARTDR_BE_RESET "-" +#define UART_UARTDR_BE_BITS 0x00000400 +#define UART_UARTDR_BE_MSB 10 +#define UART_UARTDR_BE_LSB 10 +#define UART_UARTDR_BE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. In +// FIFO mode, this error is associated with the character at the +// top of the FIFO. +#define UART_UARTDR_PE_RESET "-" +#define UART_UARTDR_PE_BITS 0x00000200 +#define UART_UARTDR_PE_MSB 9 +#define UART_UARTDR_PE_LSB 9 +#define UART_UARTDR_PE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). In FIFO mode, this error is associated with the character +// at the top of the FIFO. +#define UART_UARTDR_FE_RESET "-" +#define UART_UARTDR_FE_BITS 0x00000100 +#define UART_UARTDR_FE_MSB 8 +#define UART_UARTDR_FE_LSB 8 +#define UART_UARTDR_FE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_DATA +// Description : Receive (read) data character. Transmit (write) data character. +#define UART_UARTDR_DATA_RESET "-" +#define UART_UARTDR_DATA_BITS 0x000000ff +#define UART_UARTDR_DATA_MSB 7 +#define UART_UARTDR_DATA_LSB 0 +#define UART_UARTDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : UART_UARTRSR +// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR +#define UART_UARTRSR_OFFSET 0x00000004 +#define UART_UARTRSR_BITS 0x0000000f +#define UART_UARTRSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// FIFO is already full. This bit is cleared to 0 by a write to +// UARTECR. The FIFO contents remain valid because no more data is +// written when the FIFO is full, only the contents of the shift +// register are overwritten. The CPU must now read the data, to +// empty the FIFO. +#define UART_UARTRSR_OE_RESET 0x0 +#define UART_UARTRSR_OE_BITS 0x00000008 +#define UART_UARTRSR_OE_MSB 3 +#define UART_UARTRSR_OE_LSB 3 +#define UART_UARTRSR_OE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity, and stop bits). This bit is cleared to 0 +// after a write to UARTECR. In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state) and the next valid start bit is +// received. +#define UART_UARTRSR_BE_RESET 0x0 +#define UART_UARTRSR_BE_BITS 0x00000004 +#define UART_UARTRSR_BE_MSB 2 +#define UART_UARTRSR_BE_LSB 2 +#define UART_UARTRSR_BE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. This +// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this +// error is associated with the character at the top of the FIFO. +#define UART_UARTRSR_PE_RESET 0x0 +#define UART_UARTRSR_PE_BITS 0x00000002 +#define UART_UARTRSR_PE_MSB 1 +#define UART_UARTRSR_PE_LSB 1 +#define UART_UARTRSR_PE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO +// mode, this error is associated with the character at the top of +// the FIFO. +#define UART_UARTRSR_FE_RESET 0x0 +#define UART_UARTRSR_FE_BITS 0x00000001 +#define UART_UARTRSR_FE_MSB 0 +#define UART_UARTRSR_FE_LSB 0 +#define UART_UARTRSR_FE_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTFR +// Description : Flag Register, UARTFR +#define UART_UARTFR_OFFSET 0x00000018 +#define UART_UARTFR_BITS 0x000001ff +#define UART_UARTFR_RESET 0x00000090 +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RI +// Description : Ring indicator. This bit is the complement of the UART ring +// indicator, nUARTRI, modem status input. That is, the bit is 1 +// when nUARTRI is LOW. +#define UART_UARTFR_RI_RESET "-" +#define UART_UARTFR_RI_BITS 0x00000100 +#define UART_UARTFR_RI_MSB 8 +#define UART_UARTFR_RI_LSB 8 +#define UART_UARTFR_RI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFE +// Description : Transmit FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the Line Control Register, UARTLCR_H. +// If the FIFO is disabled, this bit is set when the transmit +// holding register is empty. If the FIFO is enabled, the TXFE bit +// is set when the transmit FIFO is empty. This bit does not +// indicate if there is data in the transmit shift register. +#define UART_UARTFR_TXFE_RESET 0x1 +#define UART_UARTFR_TXFE_BITS 0x00000080 +#define UART_UARTFR_TXFE_MSB 7 +#define UART_UARTFR_TXFE_LSB 7 +#define UART_UARTFR_TXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFF +// Description : Receive FIFO full. The meaning of this bit depends on the state +// of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// full. If the FIFO is enabled, the RXFF bit is set when the +// receive FIFO is full. +#define UART_UARTFR_RXFF_RESET 0x0 +#define UART_UARTFR_RXFF_BITS 0x00000040 +#define UART_UARTFR_RXFF_MSB 6 +#define UART_UARTFR_RXFF_LSB 6 +#define UART_UARTFR_RXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFF +// Description : Transmit FIFO full. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the transmit holding register is +// full. If the FIFO is enabled, the TXFF bit is set when the +// transmit FIFO is full. +#define UART_UARTFR_TXFF_RESET 0x0 +#define UART_UARTFR_TXFF_BITS 0x00000020 +#define UART_UARTFR_TXFF_MSB 5 +#define UART_UARTFR_TXFF_LSB 5 +#define UART_UARTFR_TXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFE +// Description : Receive FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// empty. If the FIFO is enabled, the RXFE bit is set when the +// receive FIFO is empty. +#define UART_UARTFR_RXFE_RESET 0x1 +#define UART_UARTFR_RXFE_BITS 0x00000010 +#define UART_UARTFR_RXFE_MSB 4 +#define UART_UARTFR_RXFE_LSB 4 +#define UART_UARTFR_RXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_BUSY +// Description : UART busy. If this bit is set to 1, the UART is busy +// transmitting data. This bit remains set until the complete +// byte, including all the stop bits, has been sent from the shift +// register. This bit is set as soon as the transmit FIFO becomes +// non-empty, regardless of whether the UART is enabled or not. +#define UART_UARTFR_BUSY_RESET 0x0 +#define UART_UARTFR_BUSY_BITS 0x00000008 +#define UART_UARTFR_BUSY_MSB 3 +#define UART_UARTFR_BUSY_LSB 3 +#define UART_UARTFR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DCD +// Description : Data carrier detect. This bit is the complement of the UART +// data carrier detect, nUARTDCD, modem status input. That is, the +// bit is 1 when nUARTDCD is LOW. +#define UART_UARTFR_DCD_RESET "-" +#define UART_UARTFR_DCD_BITS 0x00000004 +#define UART_UARTFR_DCD_MSB 2 +#define UART_UARTFR_DCD_LSB 2 +#define UART_UARTFR_DCD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DSR +// Description : Data set ready. This bit is the complement of the UART data set +// ready, nUARTDSR, modem status input. That is, the bit is 1 when +// nUARTDSR is LOW. +#define UART_UARTFR_DSR_RESET "-" +#define UART_UARTFR_DSR_BITS 0x00000002 +#define UART_UARTFR_DSR_MSB 1 +#define UART_UARTFR_DSR_LSB 1 +#define UART_UARTFR_DSR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_CTS +// Description : Clear to send. This bit is the complement of the UART clear to +// send, nUARTCTS, modem status input. That is, the bit is 1 when +// nUARTCTS is LOW. +#define UART_UARTFR_CTS_RESET "-" +#define UART_UARTFR_CTS_BITS 0x00000001 +#define UART_UARTFR_CTS_MSB 0 +#define UART_UARTFR_CTS_LSB 0 +#define UART_UARTFR_CTS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTILPR +// Description : IrDA Low-Power Counter Register, UARTILPR +#define UART_UARTILPR_OFFSET 0x00000020 +#define UART_UARTILPR_BITS 0x000000ff +#define UART_UARTILPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTILPR_ILPDVSR +// Description : 8-bit low-power divisor value. These bits are cleared to 0 at +// reset. +#define UART_UARTILPR_ILPDVSR_RESET 0x00 +#define UART_UARTILPR_ILPDVSR_BITS 0x000000ff +#define UART_UARTILPR_ILPDVSR_MSB 7 +#define UART_UARTILPR_ILPDVSR_LSB 0 +#define UART_UARTILPR_ILPDVSR_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIBRD +// Description : Integer Baud Rate Register, UARTIBRD +#define UART_UARTIBRD_OFFSET 0x00000024 +#define UART_UARTIBRD_BITS 0x0000ffff +#define UART_UARTIBRD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIBRD_BAUD_DIVINT +// Description : The integer baud rate divisor. These bits are cleared to 0 on +// reset. +#define UART_UARTIBRD_BAUD_DIVINT_RESET 0x0000 +#define UART_UARTIBRD_BAUD_DIVINT_BITS 0x0000ffff +#define UART_UARTIBRD_BAUD_DIVINT_MSB 15 +#define UART_UARTIBRD_BAUD_DIVINT_LSB 0 +#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTFBRD +// Description : Fractional Baud Rate Register, UARTFBRD +#define UART_UARTFBRD_OFFSET 0x00000028 +#define UART_UARTFBRD_BITS 0x0000003f +#define UART_UARTFBRD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTFBRD_BAUD_DIVFRAC +// Description : The fractional baud rate divisor. These bits are cleared to 0 +// on reset. +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET 0x00 +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS 0x0000003f +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB 5 +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB 0 +#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTLCR_H +// Description : Line Control Register, UARTLCR_H +#define UART_UARTLCR_H_OFFSET 0x0000002c +#define UART_UARTLCR_H_BITS 0x000000ff +#define UART_UARTLCR_H_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_SPS +// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * +// if the EPS bit is 0 then the parity bit is transmitted and +// checked as a 1 * if the EPS bit is 1 then the parity bit is +// transmitted and checked as a 0. This bit has no effect when the +// PEN bit disables parity checking and generation. +#define UART_UARTLCR_H_SPS_RESET 0x0 +#define UART_UARTLCR_H_SPS_BITS 0x00000080 +#define UART_UARTLCR_H_SPS_MSB 7 +#define UART_UARTLCR_H_SPS_LSB 7 +#define UART_UARTLCR_H_SPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_WLEN +// Description : Word length. These bits indicate the number of data bits +// transmitted or received in a frame as follows: b11 = 8 bits b10 +// = 7 bits b01 = 6 bits b00 = 5 bits. +#define UART_UARTLCR_H_WLEN_RESET 0x0 +#define UART_UARTLCR_H_WLEN_BITS 0x00000060 +#define UART_UARTLCR_H_WLEN_MSB 6 +#define UART_UARTLCR_H_WLEN_LSB 5 +#define UART_UARTLCR_H_WLEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_FEN +// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, +// the FIFOs become 1-byte-deep holding registers 1 = transmit and +// receive FIFO buffers are enabled (FIFO mode). +#define UART_UARTLCR_H_FEN_RESET 0x0 +#define UART_UARTLCR_H_FEN_BITS 0x00000010 +#define UART_UARTLCR_H_FEN_MSB 4 +#define UART_UARTLCR_H_FEN_LSB 4 +#define UART_UARTLCR_H_FEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_STP2 +// Description : Two stop bits select. If this bit is set to 1, two stop bits +// are transmitted at the end of the frame. The receive logic does +// not check for two stop bits being received. +#define UART_UARTLCR_H_STP2_RESET 0x0 +#define UART_UARTLCR_H_STP2_BITS 0x00000008 +#define UART_UARTLCR_H_STP2_MSB 3 +#define UART_UARTLCR_H_STP2_LSB 3 +#define UART_UARTLCR_H_STP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_EPS +// Description : Even parity select. Controls the type of parity the UART uses +// during transmission and reception: 0 = odd parity. The UART +// generates or checks for an odd number of 1s in the data and +// parity bits. 1 = even parity. The UART generates or checks for +// an even number of 1s in the data and parity bits. This bit has +// no effect when the PEN bit disables parity checking and +// generation. +#define UART_UARTLCR_H_EPS_RESET 0x0 +#define UART_UARTLCR_H_EPS_BITS 0x00000004 +#define UART_UARTLCR_H_EPS_MSB 2 +#define UART_UARTLCR_H_EPS_LSB 2 +#define UART_UARTLCR_H_EPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_PEN +// Description : Parity enable: 0 = parity is disabled and no parity bit added +// to the data frame 1 = parity checking and generation is +// enabled. +#define UART_UARTLCR_H_PEN_RESET 0x0 +#define UART_UARTLCR_H_PEN_BITS 0x00000002 +#define UART_UARTLCR_H_PEN_MSB 1 +#define UART_UARTLCR_H_PEN_LSB 1 +#define UART_UARTLCR_H_PEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_BRK +// Description : Send break. If this bit is set to 1, a low-level is continually +// output on the UARTTXD output, after completing transmission of +// the current character. For the proper execution of the break +// command, the software must set this bit for at least two +// complete frames. For normal use, this bit must be cleared to 0. +#define UART_UARTLCR_H_BRK_RESET 0x0 +#define UART_UARTLCR_H_BRK_BITS 0x00000001 +#define UART_UARTLCR_H_BRK_MSB 0 +#define UART_UARTLCR_H_BRK_LSB 0 +#define UART_UARTLCR_H_BRK_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTCR +// Description : Control Register, UARTCR +#define UART_UARTCR_OFFSET 0x00000030 +#define UART_UARTCR_BITS 0x0000ff87 +#define UART_UARTCR_RESET 0x00000300 +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_CTSEN +// Description : CTS hardware flow control enable. If this bit is set to 1, CTS +// hardware flow control is enabled. Data is only transmitted when +// the nUARTCTS signal is asserted. +#define UART_UARTCR_CTSEN_RESET 0x0 +#define UART_UARTCR_CTSEN_BITS 0x00008000 +#define UART_UARTCR_CTSEN_MSB 15 +#define UART_UARTCR_CTSEN_LSB 15 +#define UART_UARTCR_CTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTSEN +// Description : RTS hardware flow control enable. If this bit is set to 1, RTS +// hardware flow control is enabled. Data is only requested when +// there is space in the receive FIFO for it to be received. +#define UART_UARTCR_RTSEN_RESET 0x0 +#define UART_UARTCR_RTSEN_BITS 0x00004000 +#define UART_UARTCR_RTSEN_MSB 14 +#define UART_UARTCR_RTSEN_LSB 14 +#define UART_UARTCR_RTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT2 +// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem +// status output. That is, when the bit is programmed to a 1, the +// output is 0. For DTE this can be used as Ring Indicator (RI). +#define UART_UARTCR_OUT2_RESET 0x0 +#define UART_UARTCR_OUT2_BITS 0x00002000 +#define UART_UARTCR_OUT2_MSB 13 +#define UART_UARTCR_OUT2_LSB 13 +#define UART_UARTCR_OUT2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT1 +// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem +// status output. That is, when the bit is programmed to a 1 the +// output is 0. For DTE this can be used as Data Carrier Detect +// (DCD). +#define UART_UARTCR_OUT1_RESET 0x0 +#define UART_UARTCR_OUT1_BITS 0x00001000 +#define UART_UARTCR_OUT1_MSB 12 +#define UART_UARTCR_OUT1_LSB 12 +#define UART_UARTCR_OUT1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTS +// Description : Request to send. This bit is the complement of the UART request +// to send, nUARTRTS, modem status output. That is, when the bit +// is programmed to a 1 then nUARTRTS is LOW. +#define UART_UARTCR_RTS_RESET 0x0 +#define UART_UARTCR_RTS_BITS 0x00000800 +#define UART_UARTCR_RTS_MSB 11 +#define UART_UARTCR_RTS_LSB 11 +#define UART_UARTCR_RTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_DTR +// Description : Data transmit ready. This bit is the complement of the UART +// data transmit ready, nUARTDTR, modem status output. That is, +// when the bit is programmed to a 1 then nUARTDTR is LOW. +#define UART_UARTCR_DTR_RESET 0x0 +#define UART_UARTCR_DTR_BITS 0x00000400 +#define UART_UARTCR_DTR_MSB 10 +#define UART_UARTCR_DTR_LSB 10 +#define UART_UARTCR_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RXE +// Description : Receive enable. If this bit is set to 1, the receive section of +// the UART is enabled. Data reception occurs for either UART +// signals or SIR signals depending on the setting of the SIREN +// bit. When the UART is disabled in the middle of reception, it +// completes the current character before stopping. +#define UART_UARTCR_RXE_RESET 0x1 +#define UART_UARTCR_RXE_BITS 0x00000200 +#define UART_UARTCR_RXE_MSB 9 +#define UART_UARTCR_RXE_LSB 9 +#define UART_UARTCR_RXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_TXE +// Description : Transmit enable. If this bit is set to 1, the transmit section +// of the UART is enabled. Data transmission occurs for either +// UART signals, or SIR signals depending on the setting of the +// SIREN bit. When the UART is disabled in the middle of +// transmission, it completes the current character before +// stopping. +#define UART_UARTCR_TXE_RESET 0x1 +#define UART_UARTCR_TXE_BITS 0x00000100 +#define UART_UARTCR_TXE_MSB 8 +#define UART_UARTCR_TXE_LSB 8 +#define UART_UARTCR_TXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_LBE +// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is +// set to 1 and the SIRTEST bit in the Test Control Register, +// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed +// through to the SIRIN path. The SIRTEST bit in the test register +// must be set to 1 to override the normal half-duplex SIR +// operation. This must be the requirement for accessing the test +// registers during normal operation, and SIRTEST must be cleared +// to 0 when loopback testing is finished. This feature reduces +// the amount of external coupling required during system test. If +// this bit is set to 1, and the SIRTEST bit is set to 0, the +// UARTTXD path is fed through to the UARTRXD path. In either SIR +// mode or UART mode, when this bit is set, the modem outputs are +// also fed through to the modem inputs. This bit is cleared to 0 +// on reset, to disable loopback. +#define UART_UARTCR_LBE_RESET 0x0 +#define UART_UARTCR_LBE_BITS 0x00000080 +#define UART_UARTCR_LBE_MSB 7 +#define UART_UARTCR_LBE_LSB 7 +#define UART_UARTCR_LBE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIRLP +// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding +// mode. If this bit is cleared to 0, low-level bits are +// transmitted as an active high pulse with a width of 3 / 16th of +// the bit period. If this bit is set to 1, low-level bits are +// transmitted with a pulse width that is 3 times the period of +// the IrLPBaud16 input signal, regardless of the selected bit +// rate. Setting this bit uses less power, but might reduce +// transmission distances. +#define UART_UARTCR_SIRLP_RESET 0x0 +#define UART_UARTCR_SIRLP_BITS 0x00000004 +#define UART_UARTCR_SIRLP_MSB 2 +#define UART_UARTCR_SIRLP_LSB 2 +#define UART_UARTCR_SIRLP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIREN +// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW +// (no light pulse generated), and signal transitions on SIRIN +// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is +// transmitted and received on nSIROUT and SIRIN. UARTTXD remains +// HIGH, in the marking state. Signal transitions on UARTRXD or +// modem status inputs have no effect. This bit has no effect if +// the UARTEN bit disables the UART. +#define UART_UARTCR_SIREN_RESET 0x0 +#define UART_UARTCR_SIREN_BITS 0x00000002 +#define UART_UARTCR_SIREN_MSB 1 +#define UART_UARTCR_SIREN_LSB 1 +#define UART_UARTCR_SIREN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_UARTEN +// Description : UART enable: 0 = UART is disabled. If the UART is disabled in +// the middle of transmission or reception, it completes the +// current character before stopping. 1 = the UART is enabled. +// Data transmission and reception occurs for either UART signals +// or SIR signals depending on the setting of the SIREN bit. +#define UART_UARTCR_UARTEN_RESET 0x0 +#define UART_UARTCR_UARTEN_BITS 0x00000001 +#define UART_UARTCR_UARTEN_MSB 0 +#define UART_UARTCR_UARTEN_LSB 0 +#define UART_UARTCR_UARTEN_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIFLS +// Description : Interrupt FIFO Level Select Register, UARTIFLS +#define UART_UARTIFLS_OFFSET 0x00000034 +#define UART_UARTIFLS_BITS 0x0000003f +#define UART_UARTIFLS_RESET 0x00000012 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_RXIFLSEL +// Description : Receive interrupt FIFO level select. The trigger points for the +// receive interrupt are as follows: b000 = Receive FIFO becomes +// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = +// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes +// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full +// b101-b111 = reserved. +#define UART_UARTIFLS_RXIFLSEL_RESET 0x2 +#define UART_UARTIFLS_RXIFLSEL_BITS 0x00000038 +#define UART_UARTIFLS_RXIFLSEL_MSB 5 +#define UART_UARTIFLS_RXIFLSEL_LSB 3 +#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_TXIFLSEL +// Description : Transmit interrupt FIFO level select. The trigger points for +// the transmit interrupt are as follows: b000 = Transmit FIFO +// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 +// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit +// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / +// 8 full b101-b111 = reserved. +#define UART_UARTIFLS_TXIFLSEL_RESET 0x2 +#define UART_UARTIFLS_TXIFLSEL_BITS 0x00000007 +#define UART_UARTIFLS_TXIFLSEL_MSB 2 +#define UART_UARTIFLS_TXIFLSEL_LSB 0 +#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIMSC +// Description : Interrupt Mask Set/Clear Register, UARTIMSC +#define UART_UARTIMSC_OFFSET 0x00000038 +#define UART_UARTIMSC_BITS 0x000007ff +#define UART_UARTIMSC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_OEIM +// Description : Overrun error interrupt mask. A read returns the current mask +// for the UARTOEINTR interrupt. On a write of 1, the mask of the +// UARTOEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_OEIM_RESET 0x0 +#define UART_UARTIMSC_OEIM_BITS 0x00000400 +#define UART_UARTIMSC_OEIM_MSB 10 +#define UART_UARTIMSC_OEIM_LSB 10 +#define UART_UARTIMSC_OEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_BEIM +// Description : Break error interrupt mask. A read returns the current mask for +// the UARTBEINTR interrupt. On a write of 1, the mask of the +// UARTBEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_BEIM_RESET 0x0 +#define UART_UARTIMSC_BEIM_BITS 0x00000200 +#define UART_UARTIMSC_BEIM_MSB 9 +#define UART_UARTIMSC_BEIM_LSB 9 +#define UART_UARTIMSC_BEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_PEIM +// Description : Parity error interrupt mask. A read returns the current mask +// for the UARTPEINTR interrupt. On a write of 1, the mask of the +// UARTPEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_PEIM_RESET 0x0 +#define UART_UARTIMSC_PEIM_BITS 0x00000100 +#define UART_UARTIMSC_PEIM_MSB 8 +#define UART_UARTIMSC_PEIM_LSB 8 +#define UART_UARTIMSC_PEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_FEIM +// Description : Framing error interrupt mask. A read returns the current mask +// for the UARTFEINTR interrupt. On a write of 1, the mask of the +// UARTFEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_FEIM_RESET 0x0 +#define UART_UARTIMSC_FEIM_BITS 0x00000080 +#define UART_UARTIMSC_FEIM_MSB 7 +#define UART_UARTIMSC_FEIM_LSB 7 +#define UART_UARTIMSC_FEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RTIM +// Description : Receive timeout interrupt mask. A read returns the current mask +// for the UARTRTINTR interrupt. On a write of 1, the mask of the +// UARTRTINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RTIM_RESET 0x0 +#define UART_UARTIMSC_RTIM_BITS 0x00000040 +#define UART_UARTIMSC_RTIM_MSB 6 +#define UART_UARTIMSC_RTIM_LSB 6 +#define UART_UARTIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_TXIM +// Description : Transmit interrupt mask. A read returns the current mask for +// the UARTTXINTR interrupt. On a write of 1, the mask of the +// UARTTXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_TXIM_RESET 0x0 +#define UART_UARTIMSC_TXIM_BITS 0x00000020 +#define UART_UARTIMSC_TXIM_MSB 5 +#define UART_UARTIMSC_TXIM_LSB 5 +#define UART_UARTIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RXIM +// Description : Receive interrupt mask. A read returns the current mask for the +// UARTRXINTR interrupt. On a write of 1, the mask of the +// UARTRXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RXIM_RESET 0x0 +#define UART_UARTIMSC_RXIM_BITS 0x00000010 +#define UART_UARTIMSC_RXIM_MSB 4 +#define UART_UARTIMSC_RXIM_LSB 4 +#define UART_UARTIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DSRMIM +// Description : nUARTDSR modem interrupt mask. A read returns the current mask +// for the UARTDSRINTR interrupt. On a write of 1, the mask of the +// UARTDSRINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DSRMIM_RESET 0x0 +#define UART_UARTIMSC_DSRMIM_BITS 0x00000008 +#define UART_UARTIMSC_DSRMIM_MSB 3 +#define UART_UARTIMSC_DSRMIM_LSB 3 +#define UART_UARTIMSC_DSRMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DCDMIM +// Description : nUARTDCD modem interrupt mask. A read returns the current mask +// for the UARTDCDINTR interrupt. On a write of 1, the mask of the +// UARTDCDINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DCDMIM_RESET 0x0 +#define UART_UARTIMSC_DCDMIM_BITS 0x00000004 +#define UART_UARTIMSC_DCDMIM_MSB 2 +#define UART_UARTIMSC_DCDMIM_LSB 2 +#define UART_UARTIMSC_DCDMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_CTSMIM +// Description : nUARTCTS modem interrupt mask. A read returns the current mask +// for the UARTCTSINTR interrupt. On a write of 1, the mask of the +// UARTCTSINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_CTSMIM_RESET 0x0 +#define UART_UARTIMSC_CTSMIM_BITS 0x00000002 +#define UART_UARTIMSC_CTSMIM_MSB 1 +#define UART_UARTIMSC_CTSMIM_LSB 1 +#define UART_UARTIMSC_CTSMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RIMIM +// Description : nUARTRI modem interrupt mask. A read returns the current mask +// for the UARTRIINTR interrupt. On a write of 1, the mask of the +// UARTRIINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RIMIM_RESET 0x0 +#define UART_UARTIMSC_RIMIM_BITS 0x00000001 +#define UART_UARTIMSC_RIMIM_MSB 0 +#define UART_UARTIMSC_RIMIM_LSB 0 +#define UART_UARTIMSC_RIMIM_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTRIS +// Description : Raw Interrupt Status Register, UARTRIS +#define UART_UARTRIS_OFFSET 0x0000003c +#define UART_UARTRIS_BITS 0x000007ff +#define UART_UARTRIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_OERIS +// Description : Overrun error interrupt status. Returns the raw interrupt state +// of the UARTOEINTR interrupt. +#define UART_UARTRIS_OERIS_RESET 0x0 +#define UART_UARTRIS_OERIS_BITS 0x00000400 +#define UART_UARTRIS_OERIS_MSB 10 +#define UART_UARTRIS_OERIS_LSB 10 +#define UART_UARTRIS_OERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_BERIS +// Description : Break error interrupt status. Returns the raw interrupt state +// of the UARTBEINTR interrupt. +#define UART_UARTRIS_BERIS_RESET 0x0 +#define UART_UARTRIS_BERIS_BITS 0x00000200 +#define UART_UARTRIS_BERIS_MSB 9 +#define UART_UARTRIS_BERIS_LSB 9 +#define UART_UARTRIS_BERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_PERIS +// Description : Parity error interrupt status. Returns the raw interrupt state +// of the UARTPEINTR interrupt. +#define UART_UARTRIS_PERIS_RESET 0x0 +#define UART_UARTRIS_PERIS_BITS 0x00000100 +#define UART_UARTRIS_PERIS_MSB 8 +#define UART_UARTRIS_PERIS_LSB 8 +#define UART_UARTRIS_PERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_FERIS +// Description : Framing error interrupt status. Returns the raw interrupt state +// of the UARTFEINTR interrupt. +#define UART_UARTRIS_FERIS_RESET 0x0 +#define UART_UARTRIS_FERIS_BITS 0x00000080 +#define UART_UARTRIS_FERIS_MSB 7 +#define UART_UARTRIS_FERIS_LSB 7 +#define UART_UARTRIS_FERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RTRIS +// Description : Receive timeout interrupt status. Returns the raw interrupt +// state of the UARTRTINTR interrupt. a +#define UART_UARTRIS_RTRIS_RESET 0x0 +#define UART_UARTRIS_RTRIS_BITS 0x00000040 +#define UART_UARTRIS_RTRIS_MSB 6 +#define UART_UARTRIS_RTRIS_LSB 6 +#define UART_UARTRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_TXRIS +// Description : Transmit interrupt status. Returns the raw interrupt state of +// the UARTTXINTR interrupt. +#define UART_UARTRIS_TXRIS_RESET 0x0 +#define UART_UARTRIS_TXRIS_BITS 0x00000020 +#define UART_UARTRIS_TXRIS_MSB 5 +#define UART_UARTRIS_TXRIS_LSB 5 +#define UART_UARTRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RXRIS +// Description : Receive interrupt status. Returns the raw interrupt state of +// the UARTRXINTR interrupt. +#define UART_UARTRIS_RXRIS_RESET 0x0 +#define UART_UARTRIS_RXRIS_BITS 0x00000010 +#define UART_UARTRIS_RXRIS_MSB 4 +#define UART_UARTRIS_RXRIS_LSB 4 +#define UART_UARTRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DSRRMIS +// Description : nUARTDSR modem interrupt status. Returns the raw interrupt +// state of the UARTDSRINTR interrupt. +#define UART_UARTRIS_DSRRMIS_RESET "-" +#define UART_UARTRIS_DSRRMIS_BITS 0x00000008 +#define UART_UARTRIS_DSRRMIS_MSB 3 +#define UART_UARTRIS_DSRRMIS_LSB 3 +#define UART_UARTRIS_DSRRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DCDRMIS +// Description : nUARTDCD modem interrupt status. Returns the raw interrupt +// state of the UARTDCDINTR interrupt. +#define UART_UARTRIS_DCDRMIS_RESET "-" +#define UART_UARTRIS_DCDRMIS_BITS 0x00000004 +#define UART_UARTRIS_DCDRMIS_MSB 2 +#define UART_UARTRIS_DCDRMIS_LSB 2 +#define UART_UARTRIS_DCDRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_CTSRMIS +// Description : nUARTCTS modem interrupt status. Returns the raw interrupt +// state of the UARTCTSINTR interrupt. +#define UART_UARTRIS_CTSRMIS_RESET "-" +#define UART_UARTRIS_CTSRMIS_BITS 0x00000002 +#define UART_UARTRIS_CTSRMIS_MSB 1 +#define UART_UARTRIS_CTSRMIS_LSB 1 +#define UART_UARTRIS_CTSRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RIRMIS +// Description : nUARTRI modem interrupt status. Returns the raw interrupt state +// of the UARTRIINTR interrupt. +#define UART_UARTRIS_RIRMIS_RESET "-" +#define UART_UARTRIS_RIRMIS_BITS 0x00000001 +#define UART_UARTRIS_RIRMIS_MSB 0 +#define UART_UARTRIS_RIRMIS_LSB 0 +#define UART_UARTRIS_RIRMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTMIS +// Description : Masked Interrupt Status Register, UARTMIS +#define UART_UARTMIS_OFFSET 0x00000040 +#define UART_UARTMIS_BITS 0x000007ff +#define UART_UARTMIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_OEMIS +// Description : Overrun error masked interrupt status. Returns the masked +// interrupt state of the UARTOEINTR interrupt. +#define UART_UARTMIS_OEMIS_RESET 0x0 +#define UART_UARTMIS_OEMIS_BITS 0x00000400 +#define UART_UARTMIS_OEMIS_MSB 10 +#define UART_UARTMIS_OEMIS_LSB 10 +#define UART_UARTMIS_OEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_BEMIS +// Description : Break error masked interrupt status. Returns the masked +// interrupt state of the UARTBEINTR interrupt. +#define UART_UARTMIS_BEMIS_RESET 0x0 +#define UART_UARTMIS_BEMIS_BITS 0x00000200 +#define UART_UARTMIS_BEMIS_MSB 9 +#define UART_UARTMIS_BEMIS_LSB 9 +#define UART_UARTMIS_BEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_PEMIS +// Description : Parity error masked interrupt status. Returns the masked +// interrupt state of the UARTPEINTR interrupt. +#define UART_UARTMIS_PEMIS_RESET 0x0 +#define UART_UARTMIS_PEMIS_BITS 0x00000100 +#define UART_UARTMIS_PEMIS_MSB 8 +#define UART_UARTMIS_PEMIS_LSB 8 +#define UART_UARTMIS_PEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_FEMIS +// Description : Framing error masked interrupt status. Returns the masked +// interrupt state of the UARTFEINTR interrupt. +#define UART_UARTMIS_FEMIS_RESET 0x0 +#define UART_UARTMIS_FEMIS_BITS 0x00000080 +#define UART_UARTMIS_FEMIS_MSB 7 +#define UART_UARTMIS_FEMIS_LSB 7 +#define UART_UARTMIS_FEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RTMIS +// Description : Receive timeout masked interrupt status. Returns the masked +// interrupt state of the UARTRTINTR interrupt. +#define UART_UARTMIS_RTMIS_RESET 0x0 +#define UART_UARTMIS_RTMIS_BITS 0x00000040 +#define UART_UARTMIS_RTMIS_MSB 6 +#define UART_UARTMIS_RTMIS_LSB 6 +#define UART_UARTMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_TXMIS +// Description : Transmit masked interrupt status. Returns the masked interrupt +// state of the UARTTXINTR interrupt. +#define UART_UARTMIS_TXMIS_RESET 0x0 +#define UART_UARTMIS_TXMIS_BITS 0x00000020 +#define UART_UARTMIS_TXMIS_MSB 5 +#define UART_UARTMIS_TXMIS_LSB 5 +#define UART_UARTMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RXMIS +// Description : Receive masked interrupt status. Returns the masked interrupt +// state of the UARTRXINTR interrupt. +#define UART_UARTMIS_RXMIS_RESET 0x0 +#define UART_UARTMIS_RXMIS_BITS 0x00000010 +#define UART_UARTMIS_RXMIS_MSB 4 +#define UART_UARTMIS_RXMIS_LSB 4 +#define UART_UARTMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DSRMMIS +// Description : nUARTDSR modem masked interrupt status. Returns the masked +// interrupt state of the UARTDSRINTR interrupt. +#define UART_UARTMIS_DSRMMIS_RESET "-" +#define UART_UARTMIS_DSRMMIS_BITS 0x00000008 +#define UART_UARTMIS_DSRMMIS_MSB 3 +#define UART_UARTMIS_DSRMMIS_LSB 3 +#define UART_UARTMIS_DSRMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DCDMMIS +// Description : nUARTDCD modem masked interrupt status. Returns the masked +// interrupt state of the UARTDCDINTR interrupt. +#define UART_UARTMIS_DCDMMIS_RESET "-" +#define UART_UARTMIS_DCDMMIS_BITS 0x00000004 +#define UART_UARTMIS_DCDMMIS_MSB 2 +#define UART_UARTMIS_DCDMMIS_LSB 2 +#define UART_UARTMIS_DCDMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_CTSMMIS +// Description : nUARTCTS modem masked interrupt status. Returns the masked +// interrupt state of the UARTCTSINTR interrupt. +#define UART_UARTMIS_CTSMMIS_RESET "-" +#define UART_UARTMIS_CTSMMIS_BITS 0x00000002 +#define UART_UARTMIS_CTSMMIS_MSB 1 +#define UART_UARTMIS_CTSMMIS_LSB 1 +#define UART_UARTMIS_CTSMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RIMMIS +// Description : nUARTRI modem masked interrupt status. Returns the masked +// interrupt state of the UARTRIINTR interrupt. +#define UART_UARTMIS_RIMMIS_RESET "-" +#define UART_UARTMIS_RIMMIS_BITS 0x00000001 +#define UART_UARTMIS_RIMMIS_MSB 0 +#define UART_UARTMIS_RIMMIS_LSB 0 +#define UART_UARTMIS_RIMMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTICR +// Description : Interrupt Clear Register, UARTICR +#define UART_UARTICR_OFFSET 0x00000044 +#define UART_UARTICR_BITS 0x000007ff +#define UART_UARTICR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_OEIC +// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. +#define UART_UARTICR_OEIC_RESET "-" +#define UART_UARTICR_OEIC_BITS 0x00000400 +#define UART_UARTICR_OEIC_MSB 10 +#define UART_UARTICR_OEIC_LSB 10 +#define UART_UARTICR_OEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_BEIC +// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. +#define UART_UARTICR_BEIC_RESET "-" +#define UART_UARTICR_BEIC_BITS 0x00000200 +#define UART_UARTICR_BEIC_MSB 9 +#define UART_UARTICR_BEIC_LSB 9 +#define UART_UARTICR_BEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_PEIC +// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. +#define UART_UARTICR_PEIC_RESET "-" +#define UART_UARTICR_PEIC_BITS 0x00000100 +#define UART_UARTICR_PEIC_MSB 8 +#define UART_UARTICR_PEIC_LSB 8 +#define UART_UARTICR_PEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_FEIC +// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. +#define UART_UARTICR_FEIC_RESET "-" +#define UART_UARTICR_FEIC_BITS 0x00000080 +#define UART_UARTICR_FEIC_MSB 7 +#define UART_UARTICR_FEIC_LSB 7 +#define UART_UARTICR_FEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RTIC +// Description : Receive timeout interrupt clear. Clears the UARTRTINTR +// interrupt. +#define UART_UARTICR_RTIC_RESET "-" +#define UART_UARTICR_RTIC_BITS 0x00000040 +#define UART_UARTICR_RTIC_MSB 6 +#define UART_UARTICR_RTIC_LSB 6 +#define UART_UARTICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_TXIC +// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. +#define UART_UARTICR_TXIC_RESET "-" +#define UART_UARTICR_TXIC_BITS 0x00000020 +#define UART_UARTICR_TXIC_MSB 5 +#define UART_UARTICR_TXIC_LSB 5 +#define UART_UARTICR_TXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RXIC +// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. +#define UART_UARTICR_RXIC_RESET "-" +#define UART_UARTICR_RXIC_BITS 0x00000010 +#define UART_UARTICR_RXIC_MSB 4 +#define UART_UARTICR_RXIC_LSB 4 +#define UART_UARTICR_RXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DSRMIC +// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR +// interrupt. +#define UART_UARTICR_DSRMIC_RESET "-" +#define UART_UARTICR_DSRMIC_BITS 0x00000008 +#define UART_UARTICR_DSRMIC_MSB 3 +#define UART_UARTICR_DSRMIC_LSB 3 +#define UART_UARTICR_DSRMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DCDMIC +// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR +// interrupt. +#define UART_UARTICR_DCDMIC_RESET "-" +#define UART_UARTICR_DCDMIC_BITS 0x00000004 +#define UART_UARTICR_DCDMIC_MSB 2 +#define UART_UARTICR_DCDMIC_LSB 2 +#define UART_UARTICR_DCDMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_CTSMIC +// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR +// interrupt. +#define UART_UARTICR_CTSMIC_RESET "-" +#define UART_UARTICR_CTSMIC_BITS 0x00000002 +#define UART_UARTICR_CTSMIC_MSB 1 +#define UART_UARTICR_CTSMIC_LSB 1 +#define UART_UARTICR_CTSMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RIMIC +// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. +#define UART_UARTICR_RIMIC_RESET "-" +#define UART_UARTICR_RIMIC_BITS 0x00000001 +#define UART_UARTICR_RIMIC_MSB 0 +#define UART_UARTICR_RIMIC_LSB 0 +#define UART_UARTICR_RIMIC_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTDMACR +// Description : DMA Control Register, UARTDMACR +#define UART_UARTDMACR_OFFSET 0x00000048 +#define UART_UARTDMACR_BITS 0x00000007 +#define UART_UARTDMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_DMAONERR +// Description : DMA on error. If this bit is set to 1, the DMA receive request +// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the +// UART error interrupt is asserted. +#define UART_UARTDMACR_DMAONERR_RESET 0x0 +#define UART_UARTDMACR_DMAONERR_BITS 0x00000004 +#define UART_UARTDMACR_DMAONERR_MSB 2 +#define UART_UARTDMACR_DMAONERR_LSB 2 +#define UART_UARTDMACR_DMAONERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_TXDMAE +// Description : Transmit DMA enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define UART_UARTDMACR_TXDMAE_RESET 0x0 +#define UART_UARTDMACR_TXDMAE_BITS 0x00000002 +#define UART_UARTDMACR_TXDMAE_MSB 1 +#define UART_UARTDMACR_TXDMAE_LSB 1 +#define UART_UARTDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_RXDMAE +// Description : Receive DMA enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define UART_UARTDMACR_RXDMAE_RESET 0x0 +#define UART_UARTDMACR_RXDMAE_BITS 0x00000001 +#define UART_UARTDMACR_RXDMAE_MSB 0 +#define UART_UARTDMACR_RXDMAE_LSB 0 +#define UART_UARTDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTPERIPHID0 +// Description : UARTPeriphID0 Register +#define UART_UARTPERIPHID0_OFFSET 0x00000fe0 +#define UART_UARTPERIPHID0_BITS 0x000000ff +#define UART_UARTPERIPHID0_RESET 0x00000011 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS 0x000000ff +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB 7 +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB 0 +#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID1 +// Description : UARTPeriphID1 Register +#define UART_UARTPERIPHID1_OFFSET 0x00000fe4 +#define UART_UARTPERIPHID1_BITS 0x000000ff +#define UART_UARTPERIPHID1_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_RESET 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_BITS 0x000000f0 +#define UART_UARTPERIPHID1_DESIGNER0_MSB 7 +#define UART_UARTPERIPHID1_DESIGNER0_LSB 4 +#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS 0x0000000f +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB 3 +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB 0 +#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID2 +// Description : UARTPeriphID2 Register +#define UART_UARTPERIPHID2_OFFSET 0x00000fe8 +#define UART_UARTPERIPHID2_BITS 0x000000ff +#define UART_UARTPERIPHID2_RESET 0x00000034 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_REVISION +// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 +// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 +#define UART_UARTPERIPHID2_REVISION_RESET 0x3 +#define UART_UARTPERIPHID2_REVISION_BITS 0x000000f0 +#define UART_UARTPERIPHID2_REVISION_MSB 7 +#define UART_UARTPERIPHID2_REVISION_LSB 4 +#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_RESET 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_BITS 0x0000000f +#define UART_UARTPERIPHID2_DESIGNER1_MSB 3 +#define UART_UARTPERIPHID2_DESIGNER1_LSB 0 +#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID3 +// Description : UARTPeriphID3 Register +#define UART_UARTPERIPHID3_OFFSET 0x00000fec +#define UART_UARTPERIPHID3_BITS 0x000000ff +#define UART_UARTPERIPHID3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_BITS 0x000000ff +#define UART_UARTPERIPHID3_CONFIGURATION_MSB 7 +#define UART_UARTPERIPHID3_CONFIGURATION_LSB 0 +#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID0 +// Description : UARTPCellID0 Register +#define UART_UARTPCELLID0_OFFSET 0x00000ff0 +#define UART_UARTPCELLID0_BITS 0x000000ff +#define UART_UARTPCELLID0_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID0_UARTPCELLID0 +// Description : These bits read back as 0x0D +#define UART_UARTPCELLID0_UARTPCELLID0_RESET 0x0d +#define UART_UARTPCELLID0_UARTPCELLID0_BITS 0x000000ff +#define UART_UARTPCELLID0_UARTPCELLID0_MSB 7 +#define UART_UARTPCELLID0_UARTPCELLID0_LSB 0 +#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID1 +// Description : UARTPCellID1 Register +#define UART_UARTPCELLID1_OFFSET 0x00000ff4 +#define UART_UARTPCELLID1_BITS 0x000000ff +#define UART_UARTPCELLID1_RESET 0x000000f0 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID1_UARTPCELLID1 +// Description : These bits read back as 0xF0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET 0xf0 +#define UART_UARTPCELLID1_UARTPCELLID1_BITS 0x000000ff +#define UART_UARTPCELLID1_UARTPCELLID1_MSB 7 +#define UART_UARTPCELLID1_UARTPCELLID1_LSB 0 +#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID2 +// Description : UARTPCellID2 Register +#define UART_UARTPCELLID2_OFFSET 0x00000ff8 +#define UART_UARTPCELLID2_BITS 0x000000ff +#define UART_UARTPCELLID2_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID2_UARTPCELLID2 +// Description : These bits read back as 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_BITS 0x000000ff +#define UART_UARTPCELLID2_UARTPCELLID2_MSB 7 +#define UART_UARTPCELLID2_UARTPCELLID2_LSB 0 +#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID3 +// Description : UARTPCellID3 Register +#define UART_UARTPCELLID3_OFFSET 0x00000ffc +#define UART_UARTPCELLID3_BITS 0x000000ff +#define UART_UARTPCELLID3_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID3_UARTPCELLID3 +// Description : These bits read back as 0xB1 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET 0xb1 +#define UART_UARTPCELLID3_UARTPCELLID3_BITS 0x000000ff +#define UART_UARTPCELLID3_UARTPCELLID3_MSB 7 +#define UART_UARTPCELLID3_UARTPCELLID3_LSB 0 +#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_UART_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h new file mode 100644 index 00000000000..6693205f964 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h @@ -0,0 +1,3603 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB +// Version : 1 +// Bus type : ahbl +// Description : USB FS/LS controller device registers +// ============================================================================= +#ifndef HARDWARE_REGS_USB_DEFINED +#define HARDWARE_REGS_USB_DEFINED +// ============================================================================= +// Register : USB_ADDR_ENDP +// Description : Device address and endpoint control +#define USB_ADDR_ENDP_OFFSET 0x00000000 +#define USB_ADDR_ENDP_BITS 0x000f007f +#define USB_ADDR_ENDP_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ENDPOINT +// Description : Device endpoint to send data to. Only valid for HOST mode. +#define USB_ADDR_ENDP_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ADDRESS +// Description : In device mode, the address that the device should respond to. +// Set in response to a SET_ADDR setup packet from the host. In +// host mode set to the address of the device to communicate with. +#define USB_ADDR_ENDP_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP_ADDRESS_MSB 6 +#define USB_ADDR_ENDP_ADDRESS_LSB 0 +#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP1 +// Description : Interrupt endpoint 1. Only valid for HOST mode. +#define USB_ADDR_ENDP1_OFFSET 0x00000004 +#define USB_ADDR_ENDP1_BITS 0x060f007f +#define USB_ADDR_ENDP1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP1_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP1_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP1_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP1_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP1_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP1_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP1_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP1_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP1_ADDRESS_MSB 6 +#define USB_ADDR_ENDP1_ADDRESS_LSB 0 +#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP2 +// Description : Interrupt endpoint 2. Only valid for HOST mode. +#define USB_ADDR_ENDP2_OFFSET 0x00000008 +#define USB_ADDR_ENDP2_BITS 0x060f007f +#define USB_ADDR_ENDP2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP2_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP2_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP2_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP2_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP2_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP2_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP2_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP2_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP2_ADDRESS_MSB 6 +#define USB_ADDR_ENDP2_ADDRESS_LSB 0 +#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP3 +// Description : Interrupt endpoint 3. Only valid for HOST mode. +#define USB_ADDR_ENDP3_OFFSET 0x0000000c +#define USB_ADDR_ENDP3_BITS 0x060f007f +#define USB_ADDR_ENDP3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP3_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP3_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP3_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP3_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP3_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP3_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP3_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP3_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP3_ADDRESS_MSB 6 +#define USB_ADDR_ENDP3_ADDRESS_LSB 0 +#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP4 +// Description : Interrupt endpoint 4. Only valid for HOST mode. +#define USB_ADDR_ENDP4_OFFSET 0x00000010 +#define USB_ADDR_ENDP4_BITS 0x060f007f +#define USB_ADDR_ENDP4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP4_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP4_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP4_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP4_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP4_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP4_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP4_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP4_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP4_ADDRESS_MSB 6 +#define USB_ADDR_ENDP4_ADDRESS_LSB 0 +#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP5 +// Description : Interrupt endpoint 5. Only valid for HOST mode. +#define USB_ADDR_ENDP5_OFFSET 0x00000014 +#define USB_ADDR_ENDP5_BITS 0x060f007f +#define USB_ADDR_ENDP5_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP5_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP5_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP5_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP5_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP5_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP5_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP5_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP5_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP5_ADDRESS_MSB 6 +#define USB_ADDR_ENDP5_ADDRESS_LSB 0 +#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP6 +// Description : Interrupt endpoint 6. Only valid for HOST mode. +#define USB_ADDR_ENDP6_OFFSET 0x00000018 +#define USB_ADDR_ENDP6_BITS 0x060f007f +#define USB_ADDR_ENDP6_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP6_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP6_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP6_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP6_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP6_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP6_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP6_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP6_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP6_ADDRESS_MSB 6 +#define USB_ADDR_ENDP6_ADDRESS_LSB 0 +#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP7 +// Description : Interrupt endpoint 7. Only valid for HOST mode. +#define USB_ADDR_ENDP7_OFFSET 0x0000001c +#define USB_ADDR_ENDP7_BITS 0x060f007f +#define USB_ADDR_ENDP7_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP7_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP7_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP7_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP7_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP7_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP7_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP7_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP7_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP7_ADDRESS_MSB 6 +#define USB_ADDR_ENDP7_ADDRESS_LSB 0 +#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP8 +// Description : Interrupt endpoint 8. Only valid for HOST mode. +#define USB_ADDR_ENDP8_OFFSET 0x00000020 +#define USB_ADDR_ENDP8_BITS 0x060f007f +#define USB_ADDR_ENDP8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP8_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP8_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP8_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP8_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP8_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP8_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP8_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP8_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP8_ADDRESS_MSB 6 +#define USB_ADDR_ENDP8_ADDRESS_LSB 0 +#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP9 +// Description : Interrupt endpoint 9. Only valid for HOST mode. +#define USB_ADDR_ENDP9_OFFSET 0x00000024 +#define USB_ADDR_ENDP9_BITS 0x060f007f +#define USB_ADDR_ENDP9_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP9_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP9_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP9_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP9_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP9_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP9_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP9_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP9_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP9_ADDRESS_MSB 6 +#define USB_ADDR_ENDP9_ADDRESS_LSB 0 +#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP10 +// Description : Interrupt endpoint 10. Only valid for HOST mode. +#define USB_ADDR_ENDP10_OFFSET 0x00000028 +#define USB_ADDR_ENDP10_BITS 0x060f007f +#define USB_ADDR_ENDP10_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP10_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP10_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP10_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP10_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP10_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP10_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP10_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP10_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP10_ADDRESS_MSB 6 +#define USB_ADDR_ENDP10_ADDRESS_LSB 0 +#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP11 +// Description : Interrupt endpoint 11. Only valid for HOST mode. +#define USB_ADDR_ENDP11_OFFSET 0x0000002c +#define USB_ADDR_ENDP11_BITS 0x060f007f +#define USB_ADDR_ENDP11_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP11_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP11_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP11_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP11_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP11_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP11_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP11_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP11_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP11_ADDRESS_MSB 6 +#define USB_ADDR_ENDP11_ADDRESS_LSB 0 +#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP12 +// Description : Interrupt endpoint 12. Only valid for HOST mode. +#define USB_ADDR_ENDP12_OFFSET 0x00000030 +#define USB_ADDR_ENDP12_BITS 0x060f007f +#define USB_ADDR_ENDP12_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP12_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP12_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP12_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP12_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP12_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP12_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP12_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP12_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP12_ADDRESS_MSB 6 +#define USB_ADDR_ENDP12_ADDRESS_LSB 0 +#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP13 +// Description : Interrupt endpoint 13. Only valid for HOST mode. +#define USB_ADDR_ENDP13_OFFSET 0x00000034 +#define USB_ADDR_ENDP13_BITS 0x060f007f +#define USB_ADDR_ENDP13_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP13_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP13_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP13_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP13_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP13_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP13_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP13_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP13_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP13_ADDRESS_MSB 6 +#define USB_ADDR_ENDP13_ADDRESS_LSB 0 +#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP14 +// Description : Interrupt endpoint 14. Only valid for HOST mode. +#define USB_ADDR_ENDP14_OFFSET 0x00000038 +#define USB_ADDR_ENDP14_BITS 0x060f007f +#define USB_ADDR_ENDP14_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP14_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP14_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP14_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP14_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP14_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP14_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP14_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP14_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP14_ADDRESS_MSB 6 +#define USB_ADDR_ENDP14_ADDRESS_LSB 0 +#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP15 +// Description : Interrupt endpoint 15. Only valid for HOST mode. +#define USB_ADDR_ENDP15_OFFSET 0x0000003c +#define USB_ADDR_ENDP15_BITS 0x060f007f +#define USB_ADDR_ENDP15_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP15_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP15_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP15_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP15_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP15_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP15_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP15_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP15_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP15_ADDRESS_MSB 6 +#define USB_ADDR_ENDP15_ADDRESS_LSB 0 +#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_MAIN_CTRL +// Description : Main control register +#define USB_MAIN_CTRL_OFFSET 0x00000040 +#define USB_MAIN_CTRL_BITS 0x80000003 +#define USB_MAIN_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_SIM_TIMING +// Description : Reduced timings for simulation +#define USB_MAIN_CTRL_SIM_TIMING_RESET 0x0 +#define USB_MAIN_CTRL_SIM_TIMING_BITS 0x80000000 +#define USB_MAIN_CTRL_SIM_TIMING_MSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_LSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_HOST_NDEVICE +// Description : Device mode = 0, Host mode = 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET 0x0 +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS 0x00000002 +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_CONTROLLER_EN +// Description : Enable controller +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET 0x0 +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS 0x00000001 +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_SOF_WR +// Description : Set the SOF (Start of Frame) frame number in the host +// controller. The SOF packet is sent every 1ms and the host will +// increment the frame number by 1 each time. +#define USB_SOF_WR_OFFSET 0x00000044 +#define USB_SOF_WR_BITS 0x000007ff +#define USB_SOF_WR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SOF_WR_COUNT +// Description : None +#define USB_SOF_WR_COUNT_RESET 0x000 +#define USB_SOF_WR_COUNT_BITS 0x000007ff +#define USB_SOF_WR_COUNT_MSB 10 +#define USB_SOF_WR_COUNT_LSB 0 +#define USB_SOF_WR_COUNT_ACCESS "WF" +// ============================================================================= +// Register : USB_SOF_RD +// Description : Read the last SOF (Start of Frame) frame number seen. In device +// mode the last SOF received from the host. In host mode the last +// SOF sent by the host. +#define USB_SOF_RD_OFFSET 0x00000048 +#define USB_SOF_RD_BITS 0x000007ff +#define USB_SOF_RD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SOF_RD_COUNT +// Description : None +#define USB_SOF_RD_COUNT_RESET 0x000 +#define USB_SOF_RD_COUNT_BITS 0x000007ff +#define USB_SOF_RD_COUNT_MSB 10 +#define USB_SOF_RD_COUNT_LSB 0 +#define USB_SOF_RD_COUNT_ACCESS "RO" +// ============================================================================= +// Register : USB_SIE_CTRL +// Description : SIE control register +#define USB_SIE_CTRL_OFFSET 0x0000004c +#define USB_SIE_CTRL_BITS 0xff07bf5f +#define USB_SIE_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_STALL +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL +#define USB_SIE_CTRL_EP0_INT_STALL_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_STALL_BITS 0x80000000 +#define USB_SIE_CTRL_EP0_INT_STALL_MSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_LSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF +// Description : Device: EP0 single buffered = 0, double buffered = 1 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS 0x40000000 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_1BUF +// Description : Device: Set bit in BUFF_STATUS for every buffer completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS 0x20000000 +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_2BUF +// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS 0x10000000 +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_NAK +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK +#define USB_SIE_CTRL_EP0_INT_NAK_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_NAK_BITS 0x08000000 +#define USB_SIE_CTRL_EP0_INT_NAK_MSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_LSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_EN +// Description : Direct bus drive enable +#define USB_SIE_CTRL_DIRECT_EN_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_EN_BITS 0x04000000 +#define USB_SIE_CTRL_DIRECT_EN_MSB 26 +#define USB_SIE_CTRL_DIRECT_EN_LSB 26 +#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DP +// Description : Direct control of DP +#define USB_SIE_CTRL_DIRECT_DP_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_DP_BITS 0x02000000 +#define USB_SIE_CTRL_DIRECT_DP_MSB 25 +#define USB_SIE_CTRL_DIRECT_DP_LSB 25 +#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DM +// Description : Direct control of DM +#define USB_SIE_CTRL_DIRECT_DM_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_DM_BITS 0x01000000 +#define USB_SIE_CTRL_DIRECT_DM_MSB 24 +#define USB_SIE_CTRL_DIRECT_DM_LSB 24 +#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_TRANSCEIVER_PD +// Description : Power down bus transceiver +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET 0x0 +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS 0x00040000 +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RPU_OPT +// Description : Device: Pull-up strength (0=1K2, 1=2k3) +#define USB_SIE_CTRL_RPU_OPT_RESET 0x0 +#define USB_SIE_CTRL_RPU_OPT_BITS 0x00020000 +#define USB_SIE_CTRL_RPU_OPT_MSB 17 +#define USB_SIE_CTRL_RPU_OPT_LSB 17 +#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLUP_EN +// Description : Device: Enable pull up resistor +#define USB_SIE_CTRL_PULLUP_EN_RESET 0x0 +#define USB_SIE_CTRL_PULLUP_EN_BITS 0x00010000 +#define USB_SIE_CTRL_PULLUP_EN_MSB 16 +#define USB_SIE_CTRL_PULLUP_EN_LSB 16 +#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLDOWN_EN +// Description : Host: Enable pull down resistors +#define USB_SIE_CTRL_PULLDOWN_EN_RESET 0x0 +#define USB_SIE_CTRL_PULLDOWN_EN_BITS 0x00008000 +#define USB_SIE_CTRL_PULLDOWN_EN_MSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_LSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESET_BUS +// Description : Host: Reset bus +#define USB_SIE_CTRL_RESET_BUS_RESET 0x0 +#define USB_SIE_CTRL_RESET_BUS_BITS 0x00002000 +#define USB_SIE_CTRL_RESET_BUS_MSB 13 +#define USB_SIE_CTRL_RESET_BUS_LSB 13 +#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESUME +// Description : Device: Remote wakeup. Device can initiate its own resume after +// suspend. +#define USB_SIE_CTRL_RESUME_RESET 0x0 +#define USB_SIE_CTRL_RESUME_BITS 0x00001000 +#define USB_SIE_CTRL_RESUME_MSB 12 +#define USB_SIE_CTRL_RESUME_LSB 12 +#define USB_SIE_CTRL_RESUME_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_VBUS_EN +// Description : Host: Enable VBUS +#define USB_SIE_CTRL_VBUS_EN_RESET 0x0 +#define USB_SIE_CTRL_VBUS_EN_BITS 0x00000800 +#define USB_SIE_CTRL_VBUS_EN_MSB 11 +#define USB_SIE_CTRL_VBUS_EN_LSB 11 +#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_KEEP_ALIVE_EN +// Description : Host: Enable keep alive packet (for low speed bus) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET 0x0 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS 0x00000400 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_EN +// Description : Host: Enable SOF generation (for full speed bus) +#define USB_SIE_CTRL_SOF_EN_RESET 0x0 +#define USB_SIE_CTRL_SOF_EN_BITS 0x00000200 +#define USB_SIE_CTRL_SOF_EN_MSB 9 +#define USB_SIE_CTRL_SOF_EN_LSB 9 +#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_SYNC +// Description : Host: Delay packet(s) until after SOF +#define USB_SIE_CTRL_SOF_SYNC_RESET 0x0 +#define USB_SIE_CTRL_SOF_SYNC_BITS 0x00000100 +#define USB_SIE_CTRL_SOF_SYNC_MSB 8 +#define USB_SIE_CTRL_SOF_SYNC_LSB 8 +#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PREAMBLE_EN +// Description : Host: Preable enable for LS device on FS hub +#define USB_SIE_CTRL_PREAMBLE_EN_RESET 0x0 +#define USB_SIE_CTRL_PREAMBLE_EN_BITS 0x00000040 +#define USB_SIE_CTRL_PREAMBLE_EN_MSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_LSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_STOP_TRANS +// Description : Host: Stop transaction +#define USB_SIE_CTRL_STOP_TRANS_RESET 0x0 +#define USB_SIE_CTRL_STOP_TRANS_BITS 0x00000010 +#define USB_SIE_CTRL_STOP_TRANS_MSB 4 +#define USB_SIE_CTRL_STOP_TRANS_LSB 4 +#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RECEIVE_DATA +// Description : Host: Receive transaction (IN to host) +#define USB_SIE_CTRL_RECEIVE_DATA_RESET 0x0 +#define USB_SIE_CTRL_RECEIVE_DATA_BITS 0x00000008 +#define USB_SIE_CTRL_RECEIVE_DATA_MSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_LSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_DATA +// Description : Host: Send transaction (OUT from host) +#define USB_SIE_CTRL_SEND_DATA_RESET 0x0 +#define USB_SIE_CTRL_SEND_DATA_BITS 0x00000004 +#define USB_SIE_CTRL_SEND_DATA_MSB 2 +#define USB_SIE_CTRL_SEND_DATA_LSB 2 +#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_SETUP +// Description : Host: Send Setup packet +#define USB_SIE_CTRL_SEND_SETUP_RESET 0x0 +#define USB_SIE_CTRL_SEND_SETUP_BITS 0x00000002 +#define USB_SIE_CTRL_SEND_SETUP_MSB 1 +#define USB_SIE_CTRL_SEND_SETUP_LSB 1 +#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_START_TRANS +// Description : Host: Start transaction +#define USB_SIE_CTRL_START_TRANS_RESET 0x0 +#define USB_SIE_CTRL_START_TRANS_BITS 0x00000001 +#define USB_SIE_CTRL_START_TRANS_MSB 0 +#define USB_SIE_CTRL_START_TRANS_LSB 0 +#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" +// ============================================================================= +// Register : USB_SIE_STATUS +// Description : SIE status register +#define USB_SIE_STATUS_OFFSET 0x00000050 +#define USB_SIE_STATUS_BITS 0xff0f0f1d +#define USB_SIE_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_DATA_SEQ_ERROR +// Description : Data Sequence Error. +// +// The device can raise a sequence error in the following +// conditions: +// +// * A SETUP packet is received followed by a DATA1 packet (data +// phase should always be DATA0) * An OUT packet is received from +// the host but doesn't match the data pid in the buffer control +// register read from DPSRAM +// +// The host can raise a data sequence error in the following +// conditions: +// +// * An IN packet from the device has the wrong data PID +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET 0x0 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS 0x80000000 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ACK_REC +// Description : ACK received. Raised by both host and device. +#define USB_SIE_STATUS_ACK_REC_RESET 0x0 +#define USB_SIE_STATUS_ACK_REC_BITS 0x40000000 +#define USB_SIE_STATUS_ACK_REC_MSB 30 +#define USB_SIE_STATUS_ACK_REC_LSB 30 +#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_STALL_REC +// Description : Host: STALL received +#define USB_SIE_STATUS_STALL_REC_RESET 0x0 +#define USB_SIE_STATUS_STALL_REC_BITS 0x20000000 +#define USB_SIE_STATUS_STALL_REC_MSB 29 +#define USB_SIE_STATUS_STALL_REC_LSB 29 +#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_NAK_REC +// Description : Host: NAK received +#define USB_SIE_STATUS_NAK_REC_RESET 0x0 +#define USB_SIE_STATUS_NAK_REC_BITS 0x10000000 +#define USB_SIE_STATUS_NAK_REC_MSB 28 +#define USB_SIE_STATUS_NAK_REC_LSB 28 +#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_TIMEOUT +// Description : RX timeout is raised by both the host and device if an ACK is +// not received in the maximum time specified by the USB spec. +#define USB_SIE_STATUS_RX_TIMEOUT_RESET 0x0 +#define USB_SIE_STATUS_RX_TIMEOUT_BITS 0x08000000 +#define USB_SIE_STATUS_RX_TIMEOUT_MSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_LSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_OVERFLOW +// Description : RX overflow is raised by the Serial RX engine if the incoming +// data is too fast. +#define USB_SIE_STATUS_RX_OVERFLOW_RESET 0x0 +#define USB_SIE_STATUS_RX_OVERFLOW_BITS 0x04000000 +#define USB_SIE_STATUS_RX_OVERFLOW_MSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_LSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BIT_STUFF_ERROR +// Description : Bit Stuff Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET 0x0 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS 0x02000000 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CRC_ERROR +// Description : CRC Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_CRC_ERROR_RESET 0x0 +#define USB_SIE_STATUS_CRC_ERROR_BITS 0x01000000 +#define USB_SIE_STATUS_CRC_ERROR_MSB 24 +#define USB_SIE_STATUS_CRC_ERROR_LSB 24 +#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BUS_RESET +// Description : Device: bus reset received +#define USB_SIE_STATUS_BUS_RESET_RESET 0x0 +#define USB_SIE_STATUS_BUS_RESET_BITS 0x00080000 +#define USB_SIE_STATUS_BUS_RESET_MSB 19 +#define USB_SIE_STATUS_BUS_RESET_LSB 19 +#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_TRANS_COMPLETE +// Description : Transaction complete. +// +// Raised by device if: +// +// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in +// the buffer control register +// +// Raised by host if: +// +// * A setup packet is sent when no data in or data out +// transaction follows * An IN packet is received and the +// `LAST_BUFF` bit is set in the buffer control register * An IN +// packet is received with zero length * An OUT packet is sent and +// the `LAST_BUFF` bit is set +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET 0x0 +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS 0x00040000 +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SETUP_REC +// Description : Device: Setup packet received +#define USB_SIE_STATUS_SETUP_REC_RESET 0x0 +#define USB_SIE_STATUS_SETUP_REC_BITS 0x00020000 +#define USB_SIE_STATUS_SETUP_REC_MSB 17 +#define USB_SIE_STATUS_SETUP_REC_LSB 17 +#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CONNECTED +// Description : Device: connected +#define USB_SIE_STATUS_CONNECTED_RESET 0x0 +#define USB_SIE_STATUS_CONNECTED_BITS 0x00010000 +#define USB_SIE_STATUS_CONNECTED_MSB 16 +#define USB_SIE_STATUS_CONNECTED_LSB 16 +#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RESUME +// Description : Host: Device has initiated a remote resume. Device: host has +// initiated a resume. +#define USB_SIE_STATUS_RESUME_RESET 0x0 +#define USB_SIE_STATUS_RESUME_BITS 0x00000800 +#define USB_SIE_STATUS_RESUME_MSB 11 +#define USB_SIE_STATUS_RESUME_LSB 11 +#define USB_SIE_STATUS_RESUME_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_OVER_CURR +// Description : VBUS over current detected +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET 0x0 +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS 0x00000400 +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SPEED +// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 +#define USB_SIE_STATUS_SPEED_RESET 0x0 +#define USB_SIE_STATUS_SPEED_BITS 0x00000300 +#define USB_SIE_STATUS_SPEED_MSB 9 +#define USB_SIE_STATUS_SPEED_LSB 8 +#define USB_SIE_STATUS_SPEED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SUSPENDED +// Description : Bus in suspended state. Valid for device and host. Host and +// device will go into suspend if neither Keep Alive / SOF frames +// are enabled. +#define USB_SIE_STATUS_SUSPENDED_RESET 0x0 +#define USB_SIE_STATUS_SUSPENDED_BITS 0x00000010 +#define USB_SIE_STATUS_SUSPENDED_MSB 4 +#define USB_SIE_STATUS_SUSPENDED_LSB 4 +#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_LINE_STATE +// Description : USB bus line state +#define USB_SIE_STATUS_LINE_STATE_RESET 0x0 +#define USB_SIE_STATUS_LINE_STATE_BITS 0x0000000c +#define USB_SIE_STATUS_LINE_STATE_MSB 3 +#define USB_SIE_STATUS_LINE_STATE_LSB 2 +#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_DETECTED +// Description : Device: VBUS Detected +#define USB_SIE_STATUS_VBUS_DETECTED_RESET 0x0 +#define USB_SIE_STATUS_VBUS_DETECTED_BITS 0x00000001 +#define USB_SIE_STATUS_VBUS_DETECTED_MSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_LSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" +// ============================================================================= +// Register : USB_INT_EP_CTRL +// Description : interrupt endpoint control register +#define USB_INT_EP_CTRL_OFFSET 0x00000054 +#define USB_INT_EP_CTRL_BITS 0x0000fffe +#define USB_INT_EP_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE +// Description : Host: Enable interrupt endpoint 1 -> 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET 0x0000 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS 0x0000fffe +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB 1 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : USB_BUFF_STATUS +// Description : Buffer status register. A bit set here indicates that a buffer +// has completed on the endpoint (if the buffer interrupt is +// enabled). It is possible for 2 buffers to be completed, so +// clearing the buffer status bit may instantly re set it on the +// next clock cycle. +#define USB_BUFF_STATUS_OFFSET 0x00000058 +#define USB_BUFF_STATUS_BITS 0xffffffff +#define USB_BUFF_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_OUT +// Description : None +#define USB_BUFF_STATUS_EP15_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP15_OUT_BITS 0x80000000 +#define USB_BUFF_STATUS_EP15_OUT_MSB 31 +#define USB_BUFF_STATUS_EP15_OUT_LSB 31 +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_IN +// Description : None +#define USB_BUFF_STATUS_EP15_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP15_IN_BITS 0x40000000 +#define USB_BUFF_STATUS_EP15_IN_MSB 30 +#define USB_BUFF_STATUS_EP15_IN_LSB 30 +#define USB_BUFF_STATUS_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_OUT +// Description : None +#define USB_BUFF_STATUS_EP14_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP14_OUT_BITS 0x20000000 +#define USB_BUFF_STATUS_EP14_OUT_MSB 29 +#define USB_BUFF_STATUS_EP14_OUT_LSB 29 +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_IN +// Description : None +#define USB_BUFF_STATUS_EP14_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP14_IN_BITS 0x10000000 +#define USB_BUFF_STATUS_EP14_IN_MSB 28 +#define USB_BUFF_STATUS_EP14_IN_LSB 28 +#define USB_BUFF_STATUS_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_OUT +// Description : None +#define USB_BUFF_STATUS_EP13_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP13_OUT_BITS 0x08000000 +#define USB_BUFF_STATUS_EP13_OUT_MSB 27 +#define USB_BUFF_STATUS_EP13_OUT_LSB 27 +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_IN +// Description : None +#define USB_BUFF_STATUS_EP13_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP13_IN_BITS 0x04000000 +#define USB_BUFF_STATUS_EP13_IN_MSB 26 +#define USB_BUFF_STATUS_EP13_IN_LSB 26 +#define USB_BUFF_STATUS_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_OUT +// Description : None +#define USB_BUFF_STATUS_EP12_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP12_OUT_BITS 0x02000000 +#define USB_BUFF_STATUS_EP12_OUT_MSB 25 +#define USB_BUFF_STATUS_EP12_OUT_LSB 25 +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_IN +// Description : None +#define USB_BUFF_STATUS_EP12_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP12_IN_BITS 0x01000000 +#define USB_BUFF_STATUS_EP12_IN_MSB 24 +#define USB_BUFF_STATUS_EP12_IN_LSB 24 +#define USB_BUFF_STATUS_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_OUT +// Description : None +#define USB_BUFF_STATUS_EP11_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP11_OUT_BITS 0x00800000 +#define USB_BUFF_STATUS_EP11_OUT_MSB 23 +#define USB_BUFF_STATUS_EP11_OUT_LSB 23 +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_IN +// Description : None +#define USB_BUFF_STATUS_EP11_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP11_IN_BITS 0x00400000 +#define USB_BUFF_STATUS_EP11_IN_MSB 22 +#define USB_BUFF_STATUS_EP11_IN_LSB 22 +#define USB_BUFF_STATUS_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_OUT +// Description : None +#define USB_BUFF_STATUS_EP10_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP10_OUT_BITS 0x00200000 +#define USB_BUFF_STATUS_EP10_OUT_MSB 21 +#define USB_BUFF_STATUS_EP10_OUT_LSB 21 +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_IN +// Description : None +#define USB_BUFF_STATUS_EP10_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP10_IN_BITS 0x00100000 +#define USB_BUFF_STATUS_EP10_IN_MSB 20 +#define USB_BUFF_STATUS_EP10_IN_LSB 20 +#define USB_BUFF_STATUS_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_OUT +// Description : None +#define USB_BUFF_STATUS_EP9_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP9_OUT_BITS 0x00080000 +#define USB_BUFF_STATUS_EP9_OUT_MSB 19 +#define USB_BUFF_STATUS_EP9_OUT_LSB 19 +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_IN +// Description : None +#define USB_BUFF_STATUS_EP9_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP9_IN_BITS 0x00040000 +#define USB_BUFF_STATUS_EP9_IN_MSB 18 +#define USB_BUFF_STATUS_EP9_IN_LSB 18 +#define USB_BUFF_STATUS_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_OUT +// Description : None +#define USB_BUFF_STATUS_EP8_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP8_OUT_BITS 0x00020000 +#define USB_BUFF_STATUS_EP8_OUT_MSB 17 +#define USB_BUFF_STATUS_EP8_OUT_LSB 17 +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_IN +// Description : None +#define USB_BUFF_STATUS_EP8_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP8_IN_BITS 0x00010000 +#define USB_BUFF_STATUS_EP8_IN_MSB 16 +#define USB_BUFF_STATUS_EP8_IN_LSB 16 +#define USB_BUFF_STATUS_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_OUT +// Description : None +#define USB_BUFF_STATUS_EP7_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP7_OUT_BITS 0x00008000 +#define USB_BUFF_STATUS_EP7_OUT_MSB 15 +#define USB_BUFF_STATUS_EP7_OUT_LSB 15 +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_IN +// Description : None +#define USB_BUFF_STATUS_EP7_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP7_IN_BITS 0x00004000 +#define USB_BUFF_STATUS_EP7_IN_MSB 14 +#define USB_BUFF_STATUS_EP7_IN_LSB 14 +#define USB_BUFF_STATUS_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_OUT +// Description : None +#define USB_BUFF_STATUS_EP6_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP6_OUT_BITS 0x00002000 +#define USB_BUFF_STATUS_EP6_OUT_MSB 13 +#define USB_BUFF_STATUS_EP6_OUT_LSB 13 +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_IN +// Description : None +#define USB_BUFF_STATUS_EP6_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP6_IN_BITS 0x00001000 +#define USB_BUFF_STATUS_EP6_IN_MSB 12 +#define USB_BUFF_STATUS_EP6_IN_LSB 12 +#define USB_BUFF_STATUS_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_OUT +// Description : None +#define USB_BUFF_STATUS_EP5_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP5_OUT_BITS 0x00000800 +#define USB_BUFF_STATUS_EP5_OUT_MSB 11 +#define USB_BUFF_STATUS_EP5_OUT_LSB 11 +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_IN +// Description : None +#define USB_BUFF_STATUS_EP5_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP5_IN_BITS 0x00000400 +#define USB_BUFF_STATUS_EP5_IN_MSB 10 +#define USB_BUFF_STATUS_EP5_IN_LSB 10 +#define USB_BUFF_STATUS_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_OUT +// Description : None +#define USB_BUFF_STATUS_EP4_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP4_OUT_BITS 0x00000200 +#define USB_BUFF_STATUS_EP4_OUT_MSB 9 +#define USB_BUFF_STATUS_EP4_OUT_LSB 9 +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_IN +// Description : None +#define USB_BUFF_STATUS_EP4_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP4_IN_BITS 0x00000100 +#define USB_BUFF_STATUS_EP4_IN_MSB 8 +#define USB_BUFF_STATUS_EP4_IN_LSB 8 +#define USB_BUFF_STATUS_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_OUT +// Description : None +#define USB_BUFF_STATUS_EP3_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP3_OUT_BITS 0x00000080 +#define USB_BUFF_STATUS_EP3_OUT_MSB 7 +#define USB_BUFF_STATUS_EP3_OUT_LSB 7 +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_IN +// Description : None +#define USB_BUFF_STATUS_EP3_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP3_IN_BITS 0x00000040 +#define USB_BUFF_STATUS_EP3_IN_MSB 6 +#define USB_BUFF_STATUS_EP3_IN_LSB 6 +#define USB_BUFF_STATUS_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_OUT +// Description : None +#define USB_BUFF_STATUS_EP2_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP2_OUT_BITS 0x00000020 +#define USB_BUFF_STATUS_EP2_OUT_MSB 5 +#define USB_BUFF_STATUS_EP2_OUT_LSB 5 +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_IN +// Description : None +#define USB_BUFF_STATUS_EP2_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP2_IN_BITS 0x00000010 +#define USB_BUFF_STATUS_EP2_IN_MSB 4 +#define USB_BUFF_STATUS_EP2_IN_LSB 4 +#define USB_BUFF_STATUS_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_OUT +// Description : None +#define USB_BUFF_STATUS_EP1_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP1_OUT_BITS 0x00000008 +#define USB_BUFF_STATUS_EP1_OUT_MSB 3 +#define USB_BUFF_STATUS_EP1_OUT_LSB 3 +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_IN +// Description : None +#define USB_BUFF_STATUS_EP1_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP1_IN_BITS 0x00000004 +#define USB_BUFF_STATUS_EP1_IN_MSB 2 +#define USB_BUFF_STATUS_EP1_IN_LSB 2 +#define USB_BUFF_STATUS_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_OUT +// Description : None +#define USB_BUFF_STATUS_EP0_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP0_OUT_BITS 0x00000002 +#define USB_BUFF_STATUS_EP0_OUT_MSB 1 +#define USB_BUFF_STATUS_EP0_OUT_LSB 1 +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_IN +// Description : None +#define USB_BUFF_STATUS_EP0_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP0_IN_BITS 0x00000001 +#define USB_BUFF_STATUS_EP0_IN_MSB 0 +#define USB_BUFF_STATUS_EP0_IN_LSB 0 +#define USB_BUFF_STATUS_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_BUFF_CPU_SHOULD_HANDLE +// Description : Which of the double buffers should be handled. Only valid if +// using an interrupt per buffer (i.e. not per 2 buffers). Not +// valid for host interrupt endpoint polling because they are only +// single buffered. +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x0000005c +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS 0xffffffff +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS 0x80000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS 0x40000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS 0x20000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS 0x10000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS 0x08000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS 0x04000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS 0x02000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS 0x01000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS 0x00800000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS 0x00400000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS 0x00200000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS 0x00100000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS 0x00080000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS 0x00040000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS 0x00020000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS 0x00010000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS 0x00008000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS 0x00004000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS 0x00002000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS 0x00001000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS 0x00000800 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS 0x00000400 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS 0x00000200 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS 0x00000100 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS 0x00000080 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS 0x00000040 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS 0x00000020 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS 0x00000010 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS 0x00000008 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS 0x00000004 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS 0x00000002 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS 0x00000001 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_ABORT +// Description : Device only: Can be set to ignore the buffer control register +// for this endpoint in case you would like to revoke a buffer. A +// NAK will be sent for every access to the endpoint until this +// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set +// when it is safe to modify the buffer control register. +#define USB_EP_ABORT_OFFSET 0x00000060 +#define USB_EP_ABORT_BITS 0xffffffff +#define USB_EP_ABORT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_OUT +// Description : None +#define USB_EP_ABORT_EP15_OUT_RESET 0x0 +#define USB_EP_ABORT_EP15_OUT_BITS 0x80000000 +#define USB_EP_ABORT_EP15_OUT_MSB 31 +#define USB_EP_ABORT_EP15_OUT_LSB 31 +#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_IN +// Description : None +#define USB_EP_ABORT_EP15_IN_RESET 0x0 +#define USB_EP_ABORT_EP15_IN_BITS 0x40000000 +#define USB_EP_ABORT_EP15_IN_MSB 30 +#define USB_EP_ABORT_EP15_IN_LSB 30 +#define USB_EP_ABORT_EP15_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_OUT +// Description : None +#define USB_EP_ABORT_EP14_OUT_RESET 0x0 +#define USB_EP_ABORT_EP14_OUT_BITS 0x20000000 +#define USB_EP_ABORT_EP14_OUT_MSB 29 +#define USB_EP_ABORT_EP14_OUT_LSB 29 +#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_IN +// Description : None +#define USB_EP_ABORT_EP14_IN_RESET 0x0 +#define USB_EP_ABORT_EP14_IN_BITS 0x10000000 +#define USB_EP_ABORT_EP14_IN_MSB 28 +#define USB_EP_ABORT_EP14_IN_LSB 28 +#define USB_EP_ABORT_EP14_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_OUT +// Description : None +#define USB_EP_ABORT_EP13_OUT_RESET 0x0 +#define USB_EP_ABORT_EP13_OUT_BITS 0x08000000 +#define USB_EP_ABORT_EP13_OUT_MSB 27 +#define USB_EP_ABORT_EP13_OUT_LSB 27 +#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_IN +// Description : None +#define USB_EP_ABORT_EP13_IN_RESET 0x0 +#define USB_EP_ABORT_EP13_IN_BITS 0x04000000 +#define USB_EP_ABORT_EP13_IN_MSB 26 +#define USB_EP_ABORT_EP13_IN_LSB 26 +#define USB_EP_ABORT_EP13_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_OUT +// Description : None +#define USB_EP_ABORT_EP12_OUT_RESET 0x0 +#define USB_EP_ABORT_EP12_OUT_BITS 0x02000000 +#define USB_EP_ABORT_EP12_OUT_MSB 25 +#define USB_EP_ABORT_EP12_OUT_LSB 25 +#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_IN +// Description : None +#define USB_EP_ABORT_EP12_IN_RESET 0x0 +#define USB_EP_ABORT_EP12_IN_BITS 0x01000000 +#define USB_EP_ABORT_EP12_IN_MSB 24 +#define USB_EP_ABORT_EP12_IN_LSB 24 +#define USB_EP_ABORT_EP12_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_OUT +// Description : None +#define USB_EP_ABORT_EP11_OUT_RESET 0x0 +#define USB_EP_ABORT_EP11_OUT_BITS 0x00800000 +#define USB_EP_ABORT_EP11_OUT_MSB 23 +#define USB_EP_ABORT_EP11_OUT_LSB 23 +#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_IN +// Description : None +#define USB_EP_ABORT_EP11_IN_RESET 0x0 +#define USB_EP_ABORT_EP11_IN_BITS 0x00400000 +#define USB_EP_ABORT_EP11_IN_MSB 22 +#define USB_EP_ABORT_EP11_IN_LSB 22 +#define USB_EP_ABORT_EP11_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_OUT +// Description : None +#define USB_EP_ABORT_EP10_OUT_RESET 0x0 +#define USB_EP_ABORT_EP10_OUT_BITS 0x00200000 +#define USB_EP_ABORT_EP10_OUT_MSB 21 +#define USB_EP_ABORT_EP10_OUT_LSB 21 +#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_IN +// Description : None +#define USB_EP_ABORT_EP10_IN_RESET 0x0 +#define USB_EP_ABORT_EP10_IN_BITS 0x00100000 +#define USB_EP_ABORT_EP10_IN_MSB 20 +#define USB_EP_ABORT_EP10_IN_LSB 20 +#define USB_EP_ABORT_EP10_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_OUT +// Description : None +#define USB_EP_ABORT_EP9_OUT_RESET 0x0 +#define USB_EP_ABORT_EP9_OUT_BITS 0x00080000 +#define USB_EP_ABORT_EP9_OUT_MSB 19 +#define USB_EP_ABORT_EP9_OUT_LSB 19 +#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_IN +// Description : None +#define USB_EP_ABORT_EP9_IN_RESET 0x0 +#define USB_EP_ABORT_EP9_IN_BITS 0x00040000 +#define USB_EP_ABORT_EP9_IN_MSB 18 +#define USB_EP_ABORT_EP9_IN_LSB 18 +#define USB_EP_ABORT_EP9_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_OUT +// Description : None +#define USB_EP_ABORT_EP8_OUT_RESET 0x0 +#define USB_EP_ABORT_EP8_OUT_BITS 0x00020000 +#define USB_EP_ABORT_EP8_OUT_MSB 17 +#define USB_EP_ABORT_EP8_OUT_LSB 17 +#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_IN +// Description : None +#define USB_EP_ABORT_EP8_IN_RESET 0x0 +#define USB_EP_ABORT_EP8_IN_BITS 0x00010000 +#define USB_EP_ABORT_EP8_IN_MSB 16 +#define USB_EP_ABORT_EP8_IN_LSB 16 +#define USB_EP_ABORT_EP8_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_OUT +// Description : None +#define USB_EP_ABORT_EP7_OUT_RESET 0x0 +#define USB_EP_ABORT_EP7_OUT_BITS 0x00008000 +#define USB_EP_ABORT_EP7_OUT_MSB 15 +#define USB_EP_ABORT_EP7_OUT_LSB 15 +#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_IN +// Description : None +#define USB_EP_ABORT_EP7_IN_RESET 0x0 +#define USB_EP_ABORT_EP7_IN_BITS 0x00004000 +#define USB_EP_ABORT_EP7_IN_MSB 14 +#define USB_EP_ABORT_EP7_IN_LSB 14 +#define USB_EP_ABORT_EP7_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_OUT +// Description : None +#define USB_EP_ABORT_EP6_OUT_RESET 0x0 +#define USB_EP_ABORT_EP6_OUT_BITS 0x00002000 +#define USB_EP_ABORT_EP6_OUT_MSB 13 +#define USB_EP_ABORT_EP6_OUT_LSB 13 +#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_IN +// Description : None +#define USB_EP_ABORT_EP6_IN_RESET 0x0 +#define USB_EP_ABORT_EP6_IN_BITS 0x00001000 +#define USB_EP_ABORT_EP6_IN_MSB 12 +#define USB_EP_ABORT_EP6_IN_LSB 12 +#define USB_EP_ABORT_EP6_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_OUT +// Description : None +#define USB_EP_ABORT_EP5_OUT_RESET 0x0 +#define USB_EP_ABORT_EP5_OUT_BITS 0x00000800 +#define USB_EP_ABORT_EP5_OUT_MSB 11 +#define USB_EP_ABORT_EP5_OUT_LSB 11 +#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_IN +// Description : None +#define USB_EP_ABORT_EP5_IN_RESET 0x0 +#define USB_EP_ABORT_EP5_IN_BITS 0x00000400 +#define USB_EP_ABORT_EP5_IN_MSB 10 +#define USB_EP_ABORT_EP5_IN_LSB 10 +#define USB_EP_ABORT_EP5_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_OUT +// Description : None +#define USB_EP_ABORT_EP4_OUT_RESET 0x0 +#define USB_EP_ABORT_EP4_OUT_BITS 0x00000200 +#define USB_EP_ABORT_EP4_OUT_MSB 9 +#define USB_EP_ABORT_EP4_OUT_LSB 9 +#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_IN +// Description : None +#define USB_EP_ABORT_EP4_IN_RESET 0x0 +#define USB_EP_ABORT_EP4_IN_BITS 0x00000100 +#define USB_EP_ABORT_EP4_IN_MSB 8 +#define USB_EP_ABORT_EP4_IN_LSB 8 +#define USB_EP_ABORT_EP4_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_OUT +// Description : None +#define USB_EP_ABORT_EP3_OUT_RESET 0x0 +#define USB_EP_ABORT_EP3_OUT_BITS 0x00000080 +#define USB_EP_ABORT_EP3_OUT_MSB 7 +#define USB_EP_ABORT_EP3_OUT_LSB 7 +#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_IN +// Description : None +#define USB_EP_ABORT_EP3_IN_RESET 0x0 +#define USB_EP_ABORT_EP3_IN_BITS 0x00000040 +#define USB_EP_ABORT_EP3_IN_MSB 6 +#define USB_EP_ABORT_EP3_IN_LSB 6 +#define USB_EP_ABORT_EP3_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_OUT +// Description : None +#define USB_EP_ABORT_EP2_OUT_RESET 0x0 +#define USB_EP_ABORT_EP2_OUT_BITS 0x00000020 +#define USB_EP_ABORT_EP2_OUT_MSB 5 +#define USB_EP_ABORT_EP2_OUT_LSB 5 +#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_IN +// Description : None +#define USB_EP_ABORT_EP2_IN_RESET 0x0 +#define USB_EP_ABORT_EP2_IN_BITS 0x00000010 +#define USB_EP_ABORT_EP2_IN_MSB 4 +#define USB_EP_ABORT_EP2_IN_LSB 4 +#define USB_EP_ABORT_EP2_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_OUT +// Description : None +#define USB_EP_ABORT_EP1_OUT_RESET 0x0 +#define USB_EP_ABORT_EP1_OUT_BITS 0x00000008 +#define USB_EP_ABORT_EP1_OUT_MSB 3 +#define USB_EP_ABORT_EP1_OUT_LSB 3 +#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_IN +// Description : None +#define USB_EP_ABORT_EP1_IN_RESET 0x0 +#define USB_EP_ABORT_EP1_IN_BITS 0x00000004 +#define USB_EP_ABORT_EP1_IN_MSB 2 +#define USB_EP_ABORT_EP1_IN_LSB 2 +#define USB_EP_ABORT_EP1_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_OUT +// Description : None +#define USB_EP_ABORT_EP0_OUT_RESET 0x0 +#define USB_EP_ABORT_EP0_OUT_BITS 0x00000002 +#define USB_EP_ABORT_EP0_OUT_MSB 1 +#define USB_EP_ABORT_EP0_OUT_LSB 1 +#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_IN +// Description : None +#define USB_EP_ABORT_EP0_IN_RESET 0x0 +#define USB_EP_ABORT_EP0_IN_BITS 0x00000001 +#define USB_EP_ABORT_EP0_IN_MSB 0 +#define USB_EP_ABORT_EP0_IN_LSB 0 +#define USB_EP_ABORT_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_ABORT_DONE +// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an +// endpoint is idle so the programmer knows it is safe to modify +// the buffer control register. +#define USB_EP_ABORT_DONE_OFFSET 0x00000064 +#define USB_EP_ABORT_DONE_BITS 0xffffffff +#define USB_EP_ABORT_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP15_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP15_OUT_BITS 0x80000000 +#define USB_EP_ABORT_DONE_EP15_OUT_MSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_LSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_IN +// Description : None +#define USB_EP_ABORT_DONE_EP15_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP15_IN_BITS 0x40000000 +#define USB_EP_ABORT_DONE_EP15_IN_MSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_LSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP14_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP14_OUT_BITS 0x20000000 +#define USB_EP_ABORT_DONE_EP14_OUT_MSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_LSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_IN +// Description : None +#define USB_EP_ABORT_DONE_EP14_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP14_IN_BITS 0x10000000 +#define USB_EP_ABORT_DONE_EP14_IN_MSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_LSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP13_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP13_OUT_BITS 0x08000000 +#define USB_EP_ABORT_DONE_EP13_OUT_MSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_LSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_IN +// Description : None +#define USB_EP_ABORT_DONE_EP13_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP13_IN_BITS 0x04000000 +#define USB_EP_ABORT_DONE_EP13_IN_MSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_LSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP12_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP12_OUT_BITS 0x02000000 +#define USB_EP_ABORT_DONE_EP12_OUT_MSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_LSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_IN +// Description : None +#define USB_EP_ABORT_DONE_EP12_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP12_IN_BITS 0x01000000 +#define USB_EP_ABORT_DONE_EP12_IN_MSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_LSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP11_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP11_OUT_BITS 0x00800000 +#define USB_EP_ABORT_DONE_EP11_OUT_MSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_LSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_IN +// Description : None +#define USB_EP_ABORT_DONE_EP11_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP11_IN_BITS 0x00400000 +#define USB_EP_ABORT_DONE_EP11_IN_MSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_LSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP10_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP10_OUT_BITS 0x00200000 +#define USB_EP_ABORT_DONE_EP10_OUT_MSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_LSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_IN +// Description : None +#define USB_EP_ABORT_DONE_EP10_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP10_IN_BITS 0x00100000 +#define USB_EP_ABORT_DONE_EP10_IN_MSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_LSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP9_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP9_OUT_BITS 0x00080000 +#define USB_EP_ABORT_DONE_EP9_OUT_MSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_LSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_IN +// Description : None +#define USB_EP_ABORT_DONE_EP9_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP9_IN_BITS 0x00040000 +#define USB_EP_ABORT_DONE_EP9_IN_MSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_LSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP8_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP8_OUT_BITS 0x00020000 +#define USB_EP_ABORT_DONE_EP8_OUT_MSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_LSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_IN +// Description : None +#define USB_EP_ABORT_DONE_EP8_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP8_IN_BITS 0x00010000 +#define USB_EP_ABORT_DONE_EP8_IN_MSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_LSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP7_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP7_OUT_BITS 0x00008000 +#define USB_EP_ABORT_DONE_EP7_OUT_MSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_LSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_IN +// Description : None +#define USB_EP_ABORT_DONE_EP7_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP7_IN_BITS 0x00004000 +#define USB_EP_ABORT_DONE_EP7_IN_MSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_LSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP6_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP6_OUT_BITS 0x00002000 +#define USB_EP_ABORT_DONE_EP6_OUT_MSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_LSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_IN +// Description : None +#define USB_EP_ABORT_DONE_EP6_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP6_IN_BITS 0x00001000 +#define USB_EP_ABORT_DONE_EP6_IN_MSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_LSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP5_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP5_OUT_BITS 0x00000800 +#define USB_EP_ABORT_DONE_EP5_OUT_MSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_LSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_IN +// Description : None +#define USB_EP_ABORT_DONE_EP5_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP5_IN_BITS 0x00000400 +#define USB_EP_ABORT_DONE_EP5_IN_MSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_LSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP4_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP4_OUT_BITS 0x00000200 +#define USB_EP_ABORT_DONE_EP4_OUT_MSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_LSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_IN +// Description : None +#define USB_EP_ABORT_DONE_EP4_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP4_IN_BITS 0x00000100 +#define USB_EP_ABORT_DONE_EP4_IN_MSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_LSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP3_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP3_OUT_BITS 0x00000080 +#define USB_EP_ABORT_DONE_EP3_OUT_MSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_LSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_IN +// Description : None +#define USB_EP_ABORT_DONE_EP3_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP3_IN_BITS 0x00000040 +#define USB_EP_ABORT_DONE_EP3_IN_MSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_LSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP2_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP2_OUT_BITS 0x00000020 +#define USB_EP_ABORT_DONE_EP2_OUT_MSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_LSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_IN +// Description : None +#define USB_EP_ABORT_DONE_EP2_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP2_IN_BITS 0x00000010 +#define USB_EP_ABORT_DONE_EP2_IN_MSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_LSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP1_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP1_OUT_BITS 0x00000008 +#define USB_EP_ABORT_DONE_EP1_OUT_MSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_LSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_IN +// Description : None +#define USB_EP_ABORT_DONE_EP1_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP1_IN_BITS 0x00000004 +#define USB_EP_ABORT_DONE_EP1_IN_MSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_LSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP0_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP0_OUT_BITS 0x00000002 +#define USB_EP_ABORT_DONE_EP0_OUT_MSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_LSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_IN +// Description : None +#define USB_EP_ABORT_DONE_EP0_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP0_IN_BITS 0x00000001 +#define USB_EP_ABORT_DONE_EP0_IN_MSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_LSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_STALL_ARM +// Description : Device: this bit must be set in conjunction with the `STALL` +// bit in the buffer control register to send a STALL on EP0. The +// device controller clears these bits when a SETUP packet is +// received because the USB spec requires that a STALL condition +// is cleared when a SETUP packet is received. +#define USB_EP_STALL_ARM_OFFSET 0x00000068 +#define USB_EP_STALL_ARM_BITS 0x00000003 +#define USB_EP_STALL_ARM_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_OUT +// Description : None +#define USB_EP_STALL_ARM_EP0_OUT_RESET 0x0 +#define USB_EP_STALL_ARM_EP0_OUT_BITS 0x00000002 +#define USB_EP_STALL_ARM_EP0_OUT_MSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_LSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_IN +// Description : None +#define USB_EP_STALL_ARM_EP0_IN_RESET 0x0 +#define USB_EP_STALL_ARM_EP0_IN_BITS 0x00000001 +#define USB_EP_STALL_ARM_EP0_IN_MSB 0 +#define USB_EP_STALL_ARM_EP0_IN_LSB 0 +#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_NAK_POLL +// Description : Used by the host controller. Sets the wait time in microseconds +// before trying again if the device replies with a NAK. +#define USB_NAK_POLL_OFFSET 0x0000006c +#define USB_NAK_POLL_BITS 0x03ff03ff +#define USB_NAK_POLL_RESET 0x00100010 +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_FS +// Description : NAK polling interval for a full speed device +#define USB_NAK_POLL_DELAY_FS_RESET 0x010 +#define USB_NAK_POLL_DELAY_FS_BITS 0x03ff0000 +#define USB_NAK_POLL_DELAY_FS_MSB 25 +#define USB_NAK_POLL_DELAY_FS_LSB 16 +#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_LS +// Description : NAK polling interval for a low speed device +#define USB_NAK_POLL_DELAY_LS_RESET 0x010 +#define USB_NAK_POLL_DELAY_LS_BITS 0x000003ff +#define USB_NAK_POLL_DELAY_LS_MSB 9 +#define USB_NAK_POLL_DELAY_LS_LSB 0 +#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_STATUS_STALL_NAK +// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` +// bits are set. For EP0 this comes from `SIE_CTRL`. For all other +// endpoints it comes from the endpoint control register. +#define USB_EP_STATUS_STALL_NAK_OFFSET 0x00000070 +#define USB_EP_STATUS_STALL_NAK_BITS 0xffffffff +#define USB_EP_STATUS_STALL_NAK_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS 0x80000000 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS 0x40000000 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS 0x20000000 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS 0x10000000 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS 0x08000000 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS 0x04000000 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS 0x02000000 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS 0x01000000 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS 0x00800000 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS 0x00400000 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS 0x00200000 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS 0x00100000 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS 0x00080000 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS 0x00040000 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS 0x00020000 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS 0x00010000 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS 0x00008000 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS 0x00004000 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS 0x00002000 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS 0x00001000 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS 0x00000800 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS 0x00000400 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS 0x00000200 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS 0x00000100 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS 0x00000080 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS 0x00000040 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS 0x00000020 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS 0x00000010 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS 0x00000008 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS 0x00000004 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS 0x00000002 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS 0x00000001 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_USB_MUXING +// Description : Where to connect the USB controller. Should be to_phy by +// default. +#define USB_USB_MUXING_OFFSET 0x00000074 +#define USB_USB_MUXING_BITS 0x0000000f +#define USB_USB_MUXING_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SOFTCON +// Description : None +#define USB_USB_MUXING_SOFTCON_RESET 0x0 +#define USB_USB_MUXING_SOFTCON_BITS 0x00000008 +#define USB_USB_MUXING_SOFTCON_MSB 3 +#define USB_USB_MUXING_SOFTCON_LSB 3 +#define USB_USB_MUXING_SOFTCON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_DIGITAL_PAD +// Description : None +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET 0x0 +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS 0x00000004 +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_EXTPHY +// Description : None +#define USB_USB_MUXING_TO_EXTPHY_RESET 0x0 +#define USB_USB_MUXING_TO_EXTPHY_BITS 0x00000002 +#define USB_USB_MUXING_TO_EXTPHY_MSB 1 +#define USB_USB_MUXING_TO_EXTPHY_LSB 1 +#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_PHY +// Description : None +#define USB_USB_MUXING_TO_PHY_RESET 0x0 +#define USB_USB_MUXING_TO_PHY_BITS 0x00000001 +#define USB_USB_MUXING_TO_PHY_MSB 0 +#define USB_USB_MUXING_TO_PHY_LSB 0 +#define USB_USB_MUXING_TO_PHY_ACCESS "RW" +// ============================================================================= +// Register : USB_USB_PWR +// Description : Overrides for the power signals in the event that the VBUS +// signals are not hooked up to GPIO. Set the value of the +// override and then the override enable to switch over to the +// override value. +#define USB_USB_PWR_OFFSET 0x00000078 +#define USB_USB_PWR_BITS 0x0000003f +#define USB_USB_PWR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT_EN +// Description : None +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET 0x0 +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS 0x00000020 +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT +// Description : None +#define USB_USB_PWR_OVERCURR_DETECT_RESET 0x0 +#define USB_USB_PWR_OVERCURR_DETECT_BITS 0x00000010 +#define USB_USB_PWR_OVERCURR_DETECT_MSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_LSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN +// Description : None +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS 0x00000008 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT +// Description : None +#define USB_USB_PWR_VBUS_DETECT_RESET 0x0 +#define USB_USB_PWR_VBUS_DETECT_BITS 0x00000004 +#define USB_USB_PWR_VBUS_DETECT_MSB 2 +#define USB_USB_PWR_VBUS_DETECT_LSB 2 +#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN +// Description : None +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS 0x00000002 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN +// Description : None +#define USB_USB_PWR_VBUS_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_EN_BITS 0x00000001 +#define USB_USB_PWR_VBUS_EN_MSB 0 +#define USB_USB_PWR_VBUS_EN_LSB 0 +#define USB_USB_PWR_VBUS_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT +// Description : This register allows for direct control of the USB phy. Use in +// conjunction with usbphy_direct_override register to enable each +// override bit. +#define USB_USBPHY_DIRECT_OFFSET 0x0000007c +#define USB_USBPHY_DIRECT_BITS 0x007fff77 +#define USB_USBPHY_DIRECT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVV +// Description : DM over voltage +#define USB_USBPHY_DIRECT_DM_OVV_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_OVV_BITS 0x00400000 +#define USB_USBPHY_DIRECT_DM_OVV_MSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_LSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVV +// Description : DP over voltage +#define USB_USBPHY_DIRECT_DP_OVV_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_OVV_BITS 0x00200000 +#define USB_USBPHY_DIRECT_DP_OVV_MSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_LSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVCN +// Description : DM overcurrent +#define USB_USBPHY_DIRECT_DM_OVCN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_OVCN_BITS 0x00100000 +#define USB_USBPHY_DIRECT_DM_OVCN_MSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_LSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVCN +// Description : DP overcurrent +#define USB_USBPHY_DIRECT_DP_OVCN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_OVCN_BITS 0x00080000 +#define USB_USBPHY_DIRECT_DP_OVCN_MSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_LSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM +// Description : DPM pin state +#define USB_USBPHY_DIRECT_RX_DM_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DM_BITS 0x00040000 +#define USB_USBPHY_DIRECT_RX_DM_MSB 18 +#define USB_USBPHY_DIRECT_RX_DM_LSB 18 +#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP +// Description : DPP pin state +#define USB_USBPHY_DIRECT_RX_DP_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DP_BITS 0x00020000 +#define USB_USBPHY_DIRECT_RX_DP_MSB 17 +#define USB_USBPHY_DIRECT_RX_DP_LSB 17 +#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD +// Description : Differential RX +#define USB_USBPHY_DIRECT_RX_DD_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DD_BITS 0x00010000 +#define USB_USBPHY_DIRECT_RX_DD_MSB 16 +#define USB_USBPHY_DIRECT_RX_DD_LSB 16 +#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DIFFMODE +// Description : TX_DIFFMODE=0: Single ended mode +// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE +// ignored) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS 0x00008000 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_FSSLEW +// Description : TX_FSSLEW=0: Low speed slew rate +// TX_FSSLEW=1: Full speed slew rate +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS 0x00004000 +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_PD +// Description : TX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_TX_PD_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_PD_BITS 0x00002000 +#define USB_USBPHY_DIRECT_TX_PD_MSB 13 +#define USB_USBPHY_DIRECT_TX_PD_LSB 13 +#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_PD +// Description : RX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_RX_PD_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_PD_BITS 0x00001000 +#define USB_USBPHY_DIRECT_RX_PD_MSB 12 +#define USB_USBPHY_DIRECT_RX_PD_LSB 12 +#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM +// Description : Output data. TX_DIFFMODE=1, Ignored +// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// DPM=TX_DM +#define USB_USBPHY_DIRECT_TX_DM_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DM_BITS 0x00000800 +#define USB_USBPHY_DIRECT_TX_DM_MSB 11 +#define USB_USBPHY_DIRECT_TX_DM_LSB 11 +#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP +// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. +// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP +// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// DPP=TX_DP +#define USB_USBPHY_DIRECT_TX_DP_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DP_BITS 0x00000400 +#define USB_USBPHY_DIRECT_TX_DP_MSB 10 +#define USB_USBPHY_DIRECT_TX_DP_LSB 10 +#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM_OE +// Description : Output enable. If TX_DIFFMODE=1, Ignored. +// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - +// DPM driving +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS 0x00000200 +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP_OE +// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - +// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving +// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - +// DPP driving +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS 0x00000100 +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN +// Description : DM pull down enable +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS 0x00000040 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN +// Description : DM pull up enable +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS 0x00000020 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL +// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS 0x00000010 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN +// Description : DP pull down enable +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS 0x00000004 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN +// Description : DP pull up enable +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS 0x00000002 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL +// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS 0x00000001 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT_OVERRIDE +// Description : Override enable for each control in usbphy_direct +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET 0x00000080 +#define USB_USBPHY_DIRECT_OVERRIDE_BITS 0x00009fff +#define USB_USBPHY_DIRECT_OVERRIDE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS 0x00008000 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS 0x00001000 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS 0x00000800 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS 0x00000400 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS 0x00000200 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS 0x00000100 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS 0x00000080 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS 0x00000040 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS 0x00000020 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS 0x00000010 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS 0x00000008 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS 0x00000004 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000002 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000001 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_TRIM +// Description : Used to adjust trim values of USB phy pull down resistors. +#define USB_USBPHY_TRIM_OFFSET 0x00000084 +#define USB_USBPHY_TRIM_BITS 0x00001f1f +#define USB_USBPHY_TRIM_RESET 0x00001f1f +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DM pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET 0x1f +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS 0x00001f00 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB 12 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB 8 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DP pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET 0x1f +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS 0x0000001f +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB 4 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB 0 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" +// ============================================================================= +// Register : USB_INTR +// Description : Raw Interrupts +#define USB_INTR_OFFSET 0x0000008c +#define USB_INTR_BITS 0x000fffff +#define USB_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTR_EP_STALL_NAK_RESET 0x0 +#define USB_INTR_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTR_EP_STALL_NAK_MSB 19 +#define USB_INTR_EP_STALL_NAK_LSB 19 +#define USB_INTR_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTR_ABORT_DONE_RESET 0x0 +#define USB_INTR_ABORT_DONE_BITS 0x00040000 +#define USB_INTR_ABORT_DONE_MSB 18 +#define USB_INTR_ABORT_DONE_LSB 18 +#define USB_INTR_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTR_DEV_SOF_RESET 0x0 +#define USB_INTR_DEV_SOF_BITS 0x00020000 +#define USB_INTR_DEV_SOF_MSB 17 +#define USB_INTR_DEV_SOF_LSB 17 +#define USB_INTR_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTR_SETUP_REQ_RESET 0x0 +#define USB_INTR_SETUP_REQ_BITS 0x00010000 +#define USB_INTR_SETUP_REQ_MSB 16 +#define USB_INTR_SETUP_REQ_LSB 16 +#define USB_INTR_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTR_DEV_SUSPEND_RESET 0x0 +#define USB_INTR_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTR_DEV_SUSPEND_MSB 14 +#define USB_INTR_DEV_SUSPEND_LSB 14 +#define USB_INTR_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTR_DEV_CONN_DIS_RESET 0x0 +#define USB_INTR_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTR_DEV_CONN_DIS_MSB 13 +#define USB_INTR_DEV_CONN_DIS_LSB 13 +#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTR_BUS_RESET_RESET 0x0 +#define USB_INTR_BUS_RESET_BITS 0x00001000 +#define USB_INTR_BUS_RESET_MSB 12 +#define USB_INTR_BUS_RESET_LSB 12 +#define USB_INTR_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTR_VBUS_DETECT_RESET 0x0 +#define USB_INTR_VBUS_DETECT_BITS 0x00000800 +#define USB_INTR_VBUS_DETECT_MSB 11 +#define USB_INTR_VBUS_DETECT_LSB 11 +#define USB_INTR_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTR_STALL_RESET 0x0 +#define USB_INTR_STALL_BITS 0x00000400 +#define USB_INTR_STALL_MSB 10 +#define USB_INTR_STALL_LSB 10 +#define USB_INTR_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTR_ERROR_CRC_RESET 0x0 +#define USB_INTR_ERROR_CRC_BITS 0x00000200 +#define USB_INTR_ERROR_CRC_MSB 9 +#define USB_INTR_ERROR_CRC_LSB 9 +#define USB_INTR_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTR_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTR_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTR_ERROR_BIT_STUFF_MSB 8 +#define USB_INTR_ERROR_BIT_STUFF_LSB 8 +#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTR_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTR_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTR_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTR_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTR_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTR_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTR_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTR_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTR_ERROR_DATA_SEQ_MSB 5 +#define USB_INTR_ERROR_DATA_SEQ_LSB 5 +#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTR_BUFF_STATUS_RESET 0x0 +#define USB_INTR_BUFF_STATUS_BITS 0x00000010 +#define USB_INTR_BUFF_STATUS_MSB 4 +#define USB_INTR_BUFF_STATUS_LSB 4 +#define USB_INTR_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTR_TRANS_COMPLETE_RESET 0x0 +#define USB_INTR_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTR_TRANS_COMPLETE_MSB 3 +#define USB_INTR_TRANS_COMPLETE_LSB 3 +#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTR_HOST_SOF_RESET 0x0 +#define USB_INTR_HOST_SOF_BITS 0x00000004 +#define USB_INTR_HOST_SOF_MSB 2 +#define USB_INTR_HOST_SOF_LSB 2 +#define USB_INTR_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_HOST_RESUME_RESET 0x0 +#define USB_INTR_HOST_RESUME_BITS 0x00000002 +#define USB_INTR_HOST_RESUME_MSB 1 +#define USB_INTR_HOST_RESUME_LSB 1 +#define USB_INTR_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTR_HOST_CONN_DIS_RESET 0x0 +#define USB_INTR_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTR_HOST_CONN_DIS_MSB 0 +#define USB_INTR_HOST_CONN_DIS_LSB 0 +#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_INTE +// Description : Interrupt Enable +#define USB_INTE_OFFSET 0x00000090 +#define USB_INTE_BITS 0x000fffff +#define USB_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTE_EP_STALL_NAK_RESET 0x0 +#define USB_INTE_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTE_EP_STALL_NAK_MSB 19 +#define USB_INTE_EP_STALL_NAK_LSB 19 +#define USB_INTE_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTE_ABORT_DONE_RESET 0x0 +#define USB_INTE_ABORT_DONE_BITS 0x00040000 +#define USB_INTE_ABORT_DONE_MSB 18 +#define USB_INTE_ABORT_DONE_LSB 18 +#define USB_INTE_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTE_DEV_SOF_RESET 0x0 +#define USB_INTE_DEV_SOF_BITS 0x00020000 +#define USB_INTE_DEV_SOF_MSB 17 +#define USB_INTE_DEV_SOF_LSB 17 +#define USB_INTE_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTE_SETUP_REQ_RESET 0x0 +#define USB_INTE_SETUP_REQ_BITS 0x00010000 +#define USB_INTE_SETUP_REQ_MSB 16 +#define USB_INTE_SETUP_REQ_LSB 16 +#define USB_INTE_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTE_DEV_SUSPEND_RESET 0x0 +#define USB_INTE_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTE_DEV_SUSPEND_MSB 14 +#define USB_INTE_DEV_SUSPEND_LSB 14 +#define USB_INTE_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTE_DEV_CONN_DIS_RESET 0x0 +#define USB_INTE_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTE_DEV_CONN_DIS_MSB 13 +#define USB_INTE_DEV_CONN_DIS_LSB 13 +#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTE_BUS_RESET_RESET 0x0 +#define USB_INTE_BUS_RESET_BITS 0x00001000 +#define USB_INTE_BUS_RESET_MSB 12 +#define USB_INTE_BUS_RESET_LSB 12 +#define USB_INTE_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTE_VBUS_DETECT_RESET 0x0 +#define USB_INTE_VBUS_DETECT_BITS 0x00000800 +#define USB_INTE_VBUS_DETECT_MSB 11 +#define USB_INTE_VBUS_DETECT_LSB 11 +#define USB_INTE_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTE_STALL_RESET 0x0 +#define USB_INTE_STALL_BITS 0x00000400 +#define USB_INTE_STALL_MSB 10 +#define USB_INTE_STALL_LSB 10 +#define USB_INTE_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTE_ERROR_CRC_RESET 0x0 +#define USB_INTE_ERROR_CRC_BITS 0x00000200 +#define USB_INTE_ERROR_CRC_MSB 9 +#define USB_INTE_ERROR_CRC_LSB 9 +#define USB_INTE_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTE_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTE_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTE_ERROR_BIT_STUFF_MSB 8 +#define USB_INTE_ERROR_BIT_STUFF_LSB 8 +#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTE_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTE_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTE_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTE_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTE_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTE_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTE_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTE_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTE_ERROR_DATA_SEQ_MSB 5 +#define USB_INTE_ERROR_DATA_SEQ_LSB 5 +#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTE_BUFF_STATUS_RESET 0x0 +#define USB_INTE_BUFF_STATUS_BITS 0x00000010 +#define USB_INTE_BUFF_STATUS_MSB 4 +#define USB_INTE_BUFF_STATUS_LSB 4 +#define USB_INTE_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTE_TRANS_COMPLETE_RESET 0x0 +#define USB_INTE_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTE_TRANS_COMPLETE_MSB 3 +#define USB_INTE_TRANS_COMPLETE_LSB 3 +#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTE_HOST_SOF_RESET 0x0 +#define USB_INTE_HOST_SOF_BITS 0x00000004 +#define USB_INTE_HOST_SOF_MSB 2 +#define USB_INTE_HOST_SOF_LSB 2 +#define USB_INTE_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_HOST_RESUME_RESET 0x0 +#define USB_INTE_HOST_RESUME_BITS 0x00000002 +#define USB_INTE_HOST_RESUME_MSB 1 +#define USB_INTE_HOST_RESUME_LSB 1 +#define USB_INTE_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTE_HOST_CONN_DIS_RESET 0x0 +#define USB_INTE_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTE_HOST_CONN_DIS_MSB 0 +#define USB_INTE_HOST_CONN_DIS_LSB 0 +#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTF +// Description : Interrupt Force +#define USB_INTF_OFFSET 0x00000094 +#define USB_INTF_BITS 0x000fffff +#define USB_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTF_EP_STALL_NAK_RESET 0x0 +#define USB_INTF_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTF_EP_STALL_NAK_MSB 19 +#define USB_INTF_EP_STALL_NAK_LSB 19 +#define USB_INTF_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTF_ABORT_DONE_RESET 0x0 +#define USB_INTF_ABORT_DONE_BITS 0x00040000 +#define USB_INTF_ABORT_DONE_MSB 18 +#define USB_INTF_ABORT_DONE_LSB 18 +#define USB_INTF_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTF_DEV_SOF_RESET 0x0 +#define USB_INTF_DEV_SOF_BITS 0x00020000 +#define USB_INTF_DEV_SOF_MSB 17 +#define USB_INTF_DEV_SOF_LSB 17 +#define USB_INTF_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTF_SETUP_REQ_RESET 0x0 +#define USB_INTF_SETUP_REQ_BITS 0x00010000 +#define USB_INTF_SETUP_REQ_MSB 16 +#define USB_INTF_SETUP_REQ_LSB 16 +#define USB_INTF_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTF_DEV_SUSPEND_RESET 0x0 +#define USB_INTF_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTF_DEV_SUSPEND_MSB 14 +#define USB_INTF_DEV_SUSPEND_LSB 14 +#define USB_INTF_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTF_DEV_CONN_DIS_RESET 0x0 +#define USB_INTF_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTF_DEV_CONN_DIS_MSB 13 +#define USB_INTF_DEV_CONN_DIS_LSB 13 +#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTF_BUS_RESET_RESET 0x0 +#define USB_INTF_BUS_RESET_BITS 0x00001000 +#define USB_INTF_BUS_RESET_MSB 12 +#define USB_INTF_BUS_RESET_LSB 12 +#define USB_INTF_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTF_VBUS_DETECT_RESET 0x0 +#define USB_INTF_VBUS_DETECT_BITS 0x00000800 +#define USB_INTF_VBUS_DETECT_MSB 11 +#define USB_INTF_VBUS_DETECT_LSB 11 +#define USB_INTF_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTF_STALL_RESET 0x0 +#define USB_INTF_STALL_BITS 0x00000400 +#define USB_INTF_STALL_MSB 10 +#define USB_INTF_STALL_LSB 10 +#define USB_INTF_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTF_ERROR_CRC_RESET 0x0 +#define USB_INTF_ERROR_CRC_BITS 0x00000200 +#define USB_INTF_ERROR_CRC_MSB 9 +#define USB_INTF_ERROR_CRC_LSB 9 +#define USB_INTF_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTF_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTF_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTF_ERROR_BIT_STUFF_MSB 8 +#define USB_INTF_ERROR_BIT_STUFF_LSB 8 +#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTF_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTF_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTF_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTF_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTF_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTF_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTF_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTF_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTF_ERROR_DATA_SEQ_MSB 5 +#define USB_INTF_ERROR_DATA_SEQ_LSB 5 +#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTF_BUFF_STATUS_RESET 0x0 +#define USB_INTF_BUFF_STATUS_BITS 0x00000010 +#define USB_INTF_BUFF_STATUS_MSB 4 +#define USB_INTF_BUFF_STATUS_LSB 4 +#define USB_INTF_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTF_TRANS_COMPLETE_RESET 0x0 +#define USB_INTF_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTF_TRANS_COMPLETE_MSB 3 +#define USB_INTF_TRANS_COMPLETE_LSB 3 +#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTF_HOST_SOF_RESET 0x0 +#define USB_INTF_HOST_SOF_BITS 0x00000004 +#define USB_INTF_HOST_SOF_MSB 2 +#define USB_INTF_HOST_SOF_LSB 2 +#define USB_INTF_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_HOST_RESUME_RESET 0x0 +#define USB_INTF_HOST_RESUME_BITS 0x00000002 +#define USB_INTF_HOST_RESUME_MSB 1 +#define USB_INTF_HOST_RESUME_LSB 1 +#define USB_INTF_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTF_HOST_CONN_DIS_RESET 0x0 +#define USB_INTF_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTF_HOST_CONN_DIS_MSB 0 +#define USB_INTF_HOST_CONN_DIS_LSB 0 +#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTS +// Description : Interrupt status after masking & forcing +#define USB_INTS_OFFSET 0x00000098 +#define USB_INTS_BITS 0x000fffff +#define USB_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTS_EP_STALL_NAK_RESET 0x0 +#define USB_INTS_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTS_EP_STALL_NAK_MSB 19 +#define USB_INTS_EP_STALL_NAK_LSB 19 +#define USB_INTS_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTS_ABORT_DONE_RESET 0x0 +#define USB_INTS_ABORT_DONE_BITS 0x00040000 +#define USB_INTS_ABORT_DONE_MSB 18 +#define USB_INTS_ABORT_DONE_LSB 18 +#define USB_INTS_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTS_DEV_SOF_RESET 0x0 +#define USB_INTS_DEV_SOF_BITS 0x00020000 +#define USB_INTS_DEV_SOF_MSB 17 +#define USB_INTS_DEV_SOF_LSB 17 +#define USB_INTS_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTS_SETUP_REQ_RESET 0x0 +#define USB_INTS_SETUP_REQ_BITS 0x00010000 +#define USB_INTS_SETUP_REQ_MSB 16 +#define USB_INTS_SETUP_REQ_LSB 16 +#define USB_INTS_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTS_DEV_SUSPEND_RESET 0x0 +#define USB_INTS_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTS_DEV_SUSPEND_MSB 14 +#define USB_INTS_DEV_SUSPEND_LSB 14 +#define USB_INTS_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTS_DEV_CONN_DIS_RESET 0x0 +#define USB_INTS_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTS_DEV_CONN_DIS_MSB 13 +#define USB_INTS_DEV_CONN_DIS_LSB 13 +#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTS_BUS_RESET_RESET 0x0 +#define USB_INTS_BUS_RESET_BITS 0x00001000 +#define USB_INTS_BUS_RESET_MSB 12 +#define USB_INTS_BUS_RESET_LSB 12 +#define USB_INTS_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTS_VBUS_DETECT_RESET 0x0 +#define USB_INTS_VBUS_DETECT_BITS 0x00000800 +#define USB_INTS_VBUS_DETECT_MSB 11 +#define USB_INTS_VBUS_DETECT_LSB 11 +#define USB_INTS_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTS_STALL_RESET 0x0 +#define USB_INTS_STALL_BITS 0x00000400 +#define USB_INTS_STALL_MSB 10 +#define USB_INTS_STALL_LSB 10 +#define USB_INTS_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTS_ERROR_CRC_RESET 0x0 +#define USB_INTS_ERROR_CRC_BITS 0x00000200 +#define USB_INTS_ERROR_CRC_MSB 9 +#define USB_INTS_ERROR_CRC_LSB 9 +#define USB_INTS_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTS_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTS_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTS_ERROR_BIT_STUFF_MSB 8 +#define USB_INTS_ERROR_BIT_STUFF_LSB 8 +#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTS_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTS_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTS_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTS_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTS_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTS_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTS_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTS_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTS_ERROR_DATA_SEQ_MSB 5 +#define USB_INTS_ERROR_DATA_SEQ_LSB 5 +#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTS_BUFF_STATUS_RESET 0x0 +#define USB_INTS_BUFF_STATUS_BITS 0x00000010 +#define USB_INTS_BUFF_STATUS_MSB 4 +#define USB_INTS_BUFF_STATUS_LSB 4 +#define USB_INTS_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTS_TRANS_COMPLETE_RESET 0x0 +#define USB_INTS_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTS_TRANS_COMPLETE_MSB 3 +#define USB_INTS_TRANS_COMPLETE_LSB 3 +#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTS_HOST_SOF_RESET 0x0 +#define USB_INTS_HOST_SOF_BITS 0x00000004 +#define USB_INTS_HOST_SOF_MSB 2 +#define USB_INTS_HOST_SOF_LSB 2 +#define USB_INTS_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_HOST_RESUME_RESET 0x0 +#define USB_INTS_HOST_RESUME_BITS 0x00000002 +#define USB_INTS_HOST_RESUME_MSB 1 +#define USB_INTS_HOST_RESUME_LSB 1 +#define USB_INTS_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTS_HOST_CONN_DIS_RESET 0x0 +#define USB_INTS_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTS_HOST_CONN_DIS_MSB 0 +#define USB_INTS_HOST_CONN_DIS_LSB 0 +#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_USB_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h new file mode 100644 index 00000000000..34ca1ba5c0f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h @@ -0,0 +1,151 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : VREG_AND_CHIP_RESET +// Version : 1 +// Bus type : apb +// Description : control and status for on-chip voltage regulator and chip +// level reset subsystem +// ============================================================================= +#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_VREG +// Description : Voltage regulator control and status +#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000 +#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3 +#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_ROK +// Description : regulation status +// 0=not in regulation, 1=in regulation +#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0 +#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000 +#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_VSEL +// Description : output voltage select +// 0000 to 0101 - 0.80V +// 0110 - 0.85V +// 0111 - 0.90V +// 1000 - 0.95V +// 1001 - 1.00V +// 1010 - 1.05V +// 1011 - 1.10V (default) +// 1100 - 1.15V +// 1101 - 1.20V +// 1110 - 1.25V +// 1111 - 1.30V +#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb +#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0 +#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7 +#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0 +#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002 +#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_EN +// Description : enable +// 0=not enabled, 1=enabled +#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1 +#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001 +#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_BOD +// Description : brown-out detection control +#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004 +#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1 +#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_BOD_VSEL +// Description : threshold select +// 0000 - 0.473V +// 0001 - 0.516V +// 0010 - 0.559V +// 0011 - 0.602V +// 0100 - 0.645V +// 0101 - 0.688V +// 0110 - 0.731V +// 0111 - 0.774V +// 1000 - 0.817V +// 1001 - 0.860V (default) +// 1010 - 0.903V +// 1011 - 0.946V +// 1100 - 0.989V +// 1101 - 1.032V +// 1110 - 1.075V +// 1111 - 1.118V +#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9 +#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0 +#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7 +#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_BOD_EN +// Description : enable +// 0=not enabled, 1=enabled +#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1 +#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001 +#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_CHIP_RESET +// Description : Chip reset control and status +#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008 +#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100 +#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG +// Description : This is set by psm_restart from the debugger. +// Its purpose is to branch bootcode to a safe mode when the +// debugger has issued a psm_restart in order to recover from a +// boot lock-up. +// In the safe mode the debugger can repair the boot code, clear +// this flag then reboot the processor. +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART +// Description : Last reset was from the debug port +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN +// Description : Last reset was from the RUN pin +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR +// Description : Last reset was from the power-on reset or brown-out detection +// blocks +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h new file mode 100644 index 00000000000..f415c9c25ec --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h @@ -0,0 +1,226 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : WATCHDOG +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_WATCHDOG_DEFINED +#define HARDWARE_REGS_WATCHDOG_DEFINED +// ============================================================================= +// Register : WATCHDOG_CTRL +// Description : Watchdog control +// The rst_wdsel register determines which subsystems are reset +// when the watchdog is triggered. +// The watchdog can be triggered in software. +#define WATCHDOG_CTRL_OFFSET 0x00000000 +#define WATCHDOG_CTRL_BITS 0xc7ffffff +#define WATCHDOG_CTRL_RESET 0x07000000 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TRIGGER +// Description : Trigger a watchdog reset +#define WATCHDOG_CTRL_TRIGGER_RESET 0x0 +#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000 +#define WATCHDOG_CTRL_TRIGGER_MSB 31 +#define WATCHDOG_CTRL_TRIGGER_LSB 31 +#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_ENABLE +// Description : When not enabled the watchdog timer is paused +#define WATCHDOG_CTRL_ENABLE_RESET 0x0 +#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000 +#define WATCHDOG_CTRL_ENABLE_MSB 30 +#define WATCHDOG_CTRL_ENABLE_LSB 30 +#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG1 +// Description : Pause the watchdog timer when processor 1 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000 +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG0 +// Description : Pause the watchdog timer when processor 0 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000 +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_JTAG +// Description : Pause the watchdog timer when JTAG is accessing the bus fabric +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000 +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TIME +// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before +// a watchdog reset will be triggered +#define WATCHDOG_CTRL_TIME_RESET 0x000000 +#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff +#define WATCHDOG_CTRL_TIME_MSB 23 +#define WATCHDOG_CTRL_TIME_LSB 0 +#define WATCHDOG_CTRL_TIME_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_LOAD +// Description : Load the watchdog timer. The maximum setting is 0xffffff which +// corresponds to 0xffffff / 2 ticks before triggering a watchdog +// reset (see errata RP2040-E1). +#define WATCHDOG_LOAD_OFFSET 0x00000004 +#define WATCHDOG_LOAD_BITS 0x00ffffff +#define WATCHDOG_LOAD_RESET 0x00000000 +#define WATCHDOG_LOAD_MSB 23 +#define WATCHDOG_LOAD_LSB 0 +#define WATCHDOG_LOAD_ACCESS "WF" +// ============================================================================= +// Register : WATCHDOG_REASON +// Description : Logs the reason for the last reset. Both bits are zero for the +// case of a hardware reset. +#define WATCHDOG_REASON_OFFSET 0x00000008 +#define WATCHDOG_REASON_BITS 0x00000003 +#define WATCHDOG_REASON_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_FORCE +// Description : None +#define WATCHDOG_REASON_FORCE_RESET 0x0 +#define WATCHDOG_REASON_FORCE_BITS 0x00000002 +#define WATCHDOG_REASON_FORCE_MSB 1 +#define WATCHDOG_REASON_FORCE_LSB 1 +#define WATCHDOG_REASON_FORCE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_TIMER +// Description : None +#define WATCHDOG_REASON_TIMER_RESET 0x0 +#define WATCHDOG_REASON_TIMER_BITS 0x00000001 +#define WATCHDOG_REASON_TIMER_MSB 0 +#define WATCHDOG_REASON_TIMER_LSB 0 +#define WATCHDOG_REASON_TIMER_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_SCRATCH0 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c +#define WATCHDOG_SCRATCH0_BITS 0xffffffff +#define WATCHDOG_SCRATCH0_RESET 0x00000000 +#define WATCHDOG_SCRATCH0_MSB 31 +#define WATCHDOG_SCRATCH0_LSB 0 +#define WATCHDOG_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH1 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH1_OFFSET 0x00000010 +#define WATCHDOG_SCRATCH1_BITS 0xffffffff +#define WATCHDOG_SCRATCH1_RESET 0x00000000 +#define WATCHDOG_SCRATCH1_MSB 31 +#define WATCHDOG_SCRATCH1_LSB 0 +#define WATCHDOG_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH2 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH2_OFFSET 0x00000014 +#define WATCHDOG_SCRATCH2_BITS 0xffffffff +#define WATCHDOG_SCRATCH2_RESET 0x00000000 +#define WATCHDOG_SCRATCH2_MSB 31 +#define WATCHDOG_SCRATCH2_LSB 0 +#define WATCHDOG_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH3 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH3_OFFSET 0x00000018 +#define WATCHDOG_SCRATCH3_BITS 0xffffffff +#define WATCHDOG_SCRATCH3_RESET 0x00000000 +#define WATCHDOG_SCRATCH3_MSB 31 +#define WATCHDOG_SCRATCH3_LSB 0 +#define WATCHDOG_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH4 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c +#define WATCHDOG_SCRATCH4_BITS 0xffffffff +#define WATCHDOG_SCRATCH4_RESET 0x00000000 +#define WATCHDOG_SCRATCH4_MSB 31 +#define WATCHDOG_SCRATCH4_LSB 0 +#define WATCHDOG_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH5 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH5_OFFSET 0x00000020 +#define WATCHDOG_SCRATCH5_BITS 0xffffffff +#define WATCHDOG_SCRATCH5_RESET 0x00000000 +#define WATCHDOG_SCRATCH5_MSB 31 +#define WATCHDOG_SCRATCH5_LSB 0 +#define WATCHDOG_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH6 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH6_OFFSET 0x00000024 +#define WATCHDOG_SCRATCH6_BITS 0xffffffff +#define WATCHDOG_SCRATCH6_RESET 0x00000000 +#define WATCHDOG_SCRATCH6_MSB 31 +#define WATCHDOG_SCRATCH6_LSB 0 +#define WATCHDOG_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH7 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH7_OFFSET 0x00000028 +#define WATCHDOG_SCRATCH7_BITS 0xffffffff +#define WATCHDOG_SCRATCH7_RESET 0x00000000 +#define WATCHDOG_SCRATCH7_MSB 31 +#define WATCHDOG_SCRATCH7_LSB 0 +#define WATCHDOG_SCRATCH7_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_TICK +// Description : Controls the tick generator +#define WATCHDOG_TICK_OFFSET 0x0000002c +#define WATCHDOG_TICK_BITS 0x000fffff +#define WATCHDOG_TICK_RESET 0x00000200 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_COUNT +// Description : Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define WATCHDOG_TICK_COUNT_RESET "-" +#define WATCHDOG_TICK_COUNT_BITS 0x000ff800 +#define WATCHDOG_TICK_COUNT_MSB 19 +#define WATCHDOG_TICK_COUNT_LSB 11 +#define WATCHDOG_TICK_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_RUNNING +// Description : Is the tick generator running? +#define WATCHDOG_TICK_RUNNING_RESET "-" +#define WATCHDOG_TICK_RUNNING_BITS 0x00000400 +#define WATCHDOG_TICK_RUNNING_MSB 10 +#define WATCHDOG_TICK_RUNNING_LSB 10 +#define WATCHDOG_TICK_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_ENABLE +// Description : start / stop tick generation +#define WATCHDOG_TICK_ENABLE_RESET 0x1 +#define WATCHDOG_TICK_ENABLE_BITS 0x00000200 +#define WATCHDOG_TICK_ENABLE_MSB 9 +#define WATCHDOG_TICK_ENABLE_LSB 9 +#define WATCHDOG_TICK_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_CYCLES +// Description : Total number of clk_tick cycles before the next tick. +#define WATCHDOG_TICK_CYCLES_RESET 0x000 +#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff +#define WATCHDOG_TICK_CYCLES_MSB 8 +#define WATCHDOG_TICK_CYCLES_LSB 0 +#define WATCHDOG_TICK_CYCLES_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_WATCHDOG_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h new file mode 100644 index 00000000000..59487e46043 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h @@ -0,0 +1,187 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP +// Version : 1 +// Bus type : ahb +// Description : QSPI flash execute-in-place block +// ============================================================================= +#ifndef HARDWARE_REGS_XIP_DEFINED +#define HARDWARE_REGS_XIP_DEFINED +// ============================================================================= +// Register : XIP_CTRL +// Description : Cache control +#define XIP_CTRL_OFFSET 0x00000000 +#define XIP_CTRL_BITS 0x0000000b +#define XIP_CTRL_RESET 0x00000003 +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_POWER_DOWN +// Description : When 1, the cache memories are powered down. They retain state, +// but can not be accessed. This reduces static power dissipation. +// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache +// cannot +// be enabled when powered down. +// Cache-as-SRAM accesses will produce a bus error response when +// the cache is powered down. +#define XIP_CTRL_POWER_DOWN_RESET 0x0 +#define XIP_CTRL_POWER_DOWN_BITS 0x00000008 +#define XIP_CTRL_POWER_DOWN_MSB 3 +#define XIP_CTRL_POWER_DOWN_LSB 3 +#define XIP_CTRL_POWER_DOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_ERR_BADWRITE +// Description : When 1, writes to any alias other than 0x0 (caching, +// allocating) +// will produce a bus fault. When 0, these writes are silently +// ignored. +// In either case, writes to the 0x0 alias will deallocate on tag +// match, +// as usual. +#define XIP_CTRL_ERR_BADWRITE_RESET 0x1 +#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002 +#define XIP_CTRL_ERR_BADWRITE_MSB 1 +#define XIP_CTRL_ERR_BADWRITE_LSB 1 +#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN +// Description : When 1, enable the cache. When the cache is disabled, all XIP +// accesses +// will go straight to the flash, without querying the cache. When +// enabled, +// cacheable XIP accesses will query the cache, and the flash will +// not be accessed if the tag matches and the valid bit is set. +// +// If the cache is enabled, cache-as-SRAM accesses have no effect +// on the +// cache data RAM, and will produce a bus error response. +#define XIP_CTRL_EN_RESET 0x1 +#define XIP_CTRL_EN_BITS 0x00000001 +#define XIP_CTRL_EN_MSB 0 +#define XIP_CTRL_EN_LSB 0 +#define XIP_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : XIP_FLUSH +// Description : Cache Flush control +// Write 1 to flush the cache. This clears the tag memory, but +// the data memory retains its contents. (This means cache-as-SRAM +// contents is not affected by flush or reset.) +// Reading will hold the bus (stall the processor) until the flush +// completes. Alternatively STAT can be polled until completion. +#define XIP_FLUSH_OFFSET 0x00000004 +#define XIP_FLUSH_BITS 0x00000001 +#define XIP_FLUSH_RESET 0x00000000 +#define XIP_FLUSH_MSB 0 +#define XIP_FLUSH_LSB 0 +#define XIP_FLUSH_ACCESS "SC" +// ============================================================================= +// Register : XIP_STAT +// Description : Cache Status +#define XIP_STAT_OFFSET 0x00000008 +#define XIP_STAT_BITS 0x00000007 +#define XIP_STAT_RESET 0x00000002 +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_FULL +// Description : When 1, indicates the XIP streaming FIFO is completely full. +// The streaming FIFO is 2 entries deep, so the full and empty +// flag allow its level to be ascertained. +#define XIP_STAT_FIFO_FULL_RESET 0x0 +#define XIP_STAT_FIFO_FULL_BITS 0x00000004 +#define XIP_STAT_FIFO_FULL_MSB 2 +#define XIP_STAT_FIFO_FULL_LSB 2 +#define XIP_STAT_FIFO_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_EMPTY +// Description : When 1, indicates the XIP streaming FIFO is completely empty. +#define XIP_STAT_FIFO_EMPTY_RESET 0x1 +#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002 +#define XIP_STAT_FIFO_EMPTY_MSB 1 +#define XIP_STAT_FIFO_EMPTY_LSB 1 +#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FLUSH_READY +// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. +// The cache is flushed whenever the XIP block is reset, and also +// when requested via the FLUSH register. +#define XIP_STAT_FLUSH_READY_RESET 0x0 +#define XIP_STAT_FLUSH_READY_BITS 0x00000001 +#define XIP_STAT_FLUSH_READY_MSB 0 +#define XIP_STAT_FLUSH_READY_LSB 0 +#define XIP_STAT_FLUSH_READY_ACCESS "RO" +// ============================================================================= +// Register : XIP_CTR_HIT +// Description : Cache Hit counter +// A 32 bit saturating counter that increments upon each cache +// hit, +// i.e. when an XIP access is serviced directly from cached data. +// Write any value to clear. +#define XIP_CTR_HIT_OFFSET 0x0000000c +#define XIP_CTR_HIT_BITS 0xffffffff +#define XIP_CTR_HIT_RESET 0x00000000 +#define XIP_CTR_HIT_MSB 31 +#define XIP_CTR_HIT_LSB 0 +#define XIP_CTR_HIT_ACCESS "WC" +// ============================================================================= +// Register : XIP_CTR_ACC +// Description : Cache Access counter +// A 32 bit saturating counter that increments upon each XIP +// access, +// whether the cache is hit or not. This includes noncacheable +// accesses. +// Write any value to clear. +#define XIP_CTR_ACC_OFFSET 0x00000010 +#define XIP_CTR_ACC_BITS 0xffffffff +#define XIP_CTR_ACC_RESET 0x00000000 +#define XIP_CTR_ACC_MSB 31 +#define XIP_CTR_ACC_LSB 0 +#define XIP_CTR_ACC_ACCESS "WC" +// ============================================================================= +// Register : XIP_STREAM_ADDR +// Description : FIFO stream address +// The address of the next word to be streamed from flash to the +// streaming FIFO. +// Increments automatically after each flash access. +// Write the initial access address here before starting a +// streaming read. +#define XIP_STREAM_ADDR_OFFSET 0x00000014 +#define XIP_STREAM_ADDR_BITS 0xfffffffc +#define XIP_STREAM_ADDR_RESET 0x00000000 +#define XIP_STREAM_ADDR_MSB 31 +#define XIP_STREAM_ADDR_LSB 2 +#define XIP_STREAM_ADDR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_CTR +// Description : FIFO stream control +// Write a nonzero value to start a streaming read. This will then +// progress in the background, using flash idle cycles to transfer +// a linear data block from flash to the streaming FIFO. +// Decrements automatically (1 at a time) as the stream +// progresses, and halts on reaching 0. +// Write 0 to halt an in-progress stream, and discard any +// in-flight +// read, so that a new stream can immediately be started (after +// draining the FIFO and reinitialising STREAM_ADDR) +#define XIP_STREAM_CTR_OFFSET 0x00000018 +#define XIP_STREAM_CTR_BITS 0x003fffff +#define XIP_STREAM_CTR_RESET 0x00000000 +#define XIP_STREAM_CTR_MSB 21 +#define XIP_STREAM_CTR_LSB 0 +#define XIP_STREAM_CTR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_FIFO +// Description : FIFO stream data +// Streamed data is buffered here, for retrieval by the system +// DMA. +// This FIFO can also be accessed via the XIP_AUX slave, to avoid +// exposing +// the DMA to bus stalls caused by other XIP traffic. +#define XIP_STREAM_FIFO_OFFSET 0x0000001c +#define XIP_STREAM_FIFO_BITS 0xffffffff +#define XIP_STREAM_FIFO_RESET 0x00000000 +#define XIP_STREAM_FIFO_MSB 31 +#define XIP_STREAM_FIFO_LSB 0 +#define XIP_STREAM_FIFO_ACCESS "RF" +// ============================================================================= +#endif // HARDWARE_REGS_XIP_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h new file mode 100644 index 00000000000..89d036b86b1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h @@ -0,0 +1,159 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XOSC +// Version : 1 +// Bus type : apb +// Description : Controls the crystal oscillator +// ============================================================================= +#ifndef HARDWARE_REGS_XOSC_DEFINED +#define HARDWARE_REGS_XOSC_DEFINED +// ============================================================================= +// Register : XOSC_CTRL +// Description : Crystal Oscillator Control +#define XOSC_CTRL_OFFSET 0x00000000 +#define XOSC_CTRL_BITS 0x00ffffff +#define XOSC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_ENABLE +// Description : On power-up this field is initialised to DISABLE and the chip +// runs from the ROSC. +// If the chip has subsequently been programmed to run from the +// XOSC then setting this field to DISABLE may lock-up the chip. +// If this is a concern then run the clk_ref from the ROSC and +// enable the clk_sys RESUS feature. +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS 0x00fff000 +#define XOSC_CTRL_ENABLE_MSB 23 +#define XOSC_CTRL_ENABLE_LSB 12 +#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e +#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_FREQ_RANGE +// Description : Frequency range. This resets to 0xAA0 and cannot be changed. +// 0xaa0 -> 1_15MHZ +// 0xaa1 -> RESERVED_1 +// 0xaa2 -> RESERVED_2 +// 0xaa3 -> RESERVED_3 +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff +#define XOSC_CTRL_FREQ_RANGE_MSB 11 +#define XOSC_CTRL_FREQ_RANGE_LSB 0 +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3 +// ============================================================================= +// Register : XOSC_STATUS +// Description : Crystal Oscillator Status +#define XOSC_STATUS_OFFSET 0x00000004 +#define XOSC_STATUS_BITS 0x81001003 +#define XOSC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define XOSC_STATUS_STABLE_RESET 0x0 +#define XOSC_STATUS_STABLE_BITS 0x80000000 +#define XOSC_STATUS_STABLE_MSB 31 +#define XOSC_STATUS_STABLE_LSB 31 +#define XOSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or DORMANT +#define XOSC_STATUS_BADWRITE_RESET 0x0 +#define XOSC_STATUS_BADWRITE_BITS 0x01000000 +#define XOSC_STATUS_BADWRITE_MSB 24 +#define XOSC_STATUS_BADWRITE_LSB 24 +#define XOSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable, +// resets to 0 +#define XOSC_STATUS_ENABLED_RESET "-" +#define XOSC_STATUS_ENABLED_BITS 0x00001000 +#define XOSC_STATUS_ENABLED_MSB 12 +#define XOSC_STATUS_ENABLED_LSB 12 +#define XOSC_STATUS_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_FREQ_RANGE +// Description : The current frequency range setting, always reads 0 +// 0x0 -> 1_15MHZ +// 0x1 -> RESERVED_1 +// 0x2 -> RESERVED_2 +// 0x3 -> RESERVED_3 +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003 +#define XOSC_STATUS_FREQ_RANGE_MSB 1 +#define XOSC_STATUS_FREQ_RANGE_LSB 0 +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3 +// ============================================================================= +// Register : XOSC_DORMANT +// Description : Crystal Oscillator pause control +// This is used to save power by pausing the XOSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// WARNING: stop the PLLs before selecting dormant mode +// WARNING: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT +// 0x77616b65 -> WAKE +#define XOSC_DORMANT_OFFSET 0x00000008 +#define XOSC_DORMANT_BITS 0xffffffff +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB 31 +#define XOSC_DORMANT_LSB 0 +#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61 +#define XOSC_DORMANT_VALUE_WAKE 0x77616b65 +// ============================================================================= +// Register : XOSC_STARTUP +// Description : Controls the startup delay +#define XOSC_STARTUP_OFFSET 0x0000000c +#define XOSC_STARTUP_BITS 0x00103fff +#define XOSC_STARTUP_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_X4 +// Description : Multiplies the startup_delay by 4. This is of little value to +// the user given that the delay can be programmed directly +#define XOSC_STARTUP_X4_RESET "-" +#define XOSC_STARTUP_X4_BITS 0x00100000 +#define XOSC_STARTUP_X4_MSB 20 +#define XOSC_STARTUP_X4_LSB 20 +#define XOSC_STARTUP_X4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_DELAY +// Description : in multiples of 256*xtal_period +#define XOSC_STARTUP_DELAY_RESET "-" +#define XOSC_STARTUP_DELAY_BITS 0x00003fff +#define XOSC_STARTUP_DELAY_MSB 13 +#define XOSC_STARTUP_DELAY_LSB 0 +#define XOSC_STARTUP_DELAY_ACCESS "RW" +// ============================================================================= +// Register : XOSC_COUNT +// Description : A down counter running at the xosc frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define XOSC_COUNT_OFFSET 0x0000001c +#define XOSC_COUNT_BITS 0x000000ff +#define XOSC_COUNT_RESET 0x00000000 +#define XOSC_COUNT_MSB 7 +#define XOSC_COUNT_LSB 0 +#define XOSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_XOSC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd new file mode 100644 index 00000000000..d5acb9748a9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd @@ -0,0 +1,40408 @@ + + + + 8 + Raspberry Pi + RP2040 + + Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n + \n + SPDX-License-Identifier: BSD-3-Clause + + 0.1 + 32 + + CM0PLUS + r0p1 + little + true + false + 2 + false + 26 + + + + + 0 + 0x0020 + registers + + 0x14000000 + QSPI flash execute-in-place block + + XIP_IRQ + 6 + + XIP_CTRL + + + 0x0000 + Cache control + + + read-write + [3:3] + When 1, the cache memories are powered down. They retain state,\n + but can not be accessed. This reduces static power dissipation.\n + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n + be enabled when powered down.\n + Cache-as-SRAM accesses will produce a bus error response when\n + the cache is powered down. + POWER_DOWN + + + read-write + [1:1] + When 1, writes to any alias other than 0x0 (caching, allocating)\n + will produce a bus fault. When 0, these writes are silently ignored.\n + In either case, writes to the 0x0 alias will deallocate on tag match,\n + as usual. + ERR_BADWRITE + + + read-write + [0:0] + When 1, enable the cache. When the cache is disabled, all XIP accesses\n + will go straight to the flash, without querying the cache. When enabled,\n + cacheable XIP accesses will query the cache, and the flash will\n + not be accessed if the tag matches and the valid bit is set.\n\n + If the cache is enabled, cache-as-SRAM accesses have no effect on the\n + cache data RAM, and will produce a bus error response. + EN + + + CTRL + 0x00000003 + + + 0x0004 + Cache Flush control + + + read-write + [0:0] + Write 1 to flush the cache. This clears the tag memory, but\n + the data memory retains its contents. (This means cache-as-SRAM\n + contents is not affected by flush or reset.)\n + Reading will hold the bus (stall the processor) until the flush\n + completes. Alternatively STAT can be polled until completion. + clear + FLUSH + + + FLUSH + 0x00000000 + + + 0x0008 + Cache Status + + + read-only + [2:2] + When 1, indicates the XIP streaming FIFO is completely full.\n + The streaming FIFO is 2 entries deep, so the full and empty\n + flag allow its level to be ascertained. + FIFO_FULL + + + read-only + [1:1] + When 1, indicates the XIP streaming FIFO is completely empty. + FIFO_EMPTY + + + read-only + [0:0] + Reads as 0 while a cache flush is in progress, and 1 otherwise.\n + The cache is flushed whenever the XIP block is reset, and also\n + when requested via the FLUSH register. + FLUSH_READY + + + STAT + 0x00000002 + + + read-write + 0x000c + Cache Hit counter\n + A 32 bit saturating counter that increments upon each cache hit,\n + i.e. when an XIP access is serviced directly from cached data.\n + Write any value to clear. + oneToClear + CTR_HIT + 0x00000000 + + + read-write + 0x0010 + Cache Access counter\n + A 32 bit saturating counter that increments upon each XIP access,\n + whether the cache is hit or not. This includes noncacheable accesses.\n + Write any value to clear. + oneToClear + CTR_ACC + 0x00000000 + + + 0x0014 + FIFO stream address + + + read-write + [31:2] + The address of the next word to be streamed from flash to the streaming FIFO.\n + Increments automatically after each flash access.\n + Write the initial access address here before starting a streaming read. + STREAM_ADDR + + + STREAM_ADDR + 0x00000000 + + + 0x0018 + FIFO stream control + + + read-write + [21:0] + Write a nonzero value to start a streaming read. This will then\n + progress in the background, using flash idle cycles to transfer\n + a linear data block from flash to the streaming FIFO.\n + Decrements automatically (1 at a time) as the stream\n + progresses, and halts on reaching 0.\n + Write 0 to halt an in-progress stream, and discard any in-flight\n + read, so that a new stream can immediately be started (after\n + draining the FIFO and reinitialising STREAM_ADDR) + STREAM_CTR + + + STREAM_CTR + 0x00000000 + + + read-only + 0x001c + FIFO stream data\n + Streamed data is buffered here, for retrieval by the system DMA.\n + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n + the DMA to bus stalls caused by other XIP traffic. + STREAM_FIFO + 0x00000000 + + + 32 + 1 + + + + 0 + 0x0100 + registers + + 0x18000000 + DW_apb_ssi has the following features:\n + * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n + * APB3 and APB4 protocol support.\n + * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n + * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n + * Programmable Dual/Quad/Octal SPI support in Master Mode.\n + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n + * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n + * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n + * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n + * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n + * Programmable features:\n + - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n + - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n + - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n + * Configured features:\n + - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n + - 1 slave select output.\n + - Hardware slave-select – Dedicated hardware slave-select line.\n + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n + - Interrupt polarity – active high interrupt lines.\n + - Serial clock polarity – low serial-clock polarity directly after reset.\n + - Serial clock phase – capture on first edge of serial-clock directly after reset. + XIP_SSI + + + 0x0000 + Control register 0 + + + read-write + [24:24] + Slave select toggle enable + SSTE + + + read-write + [22:21] + SPI frame format + + + Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex + STD + 0 + + + Dual-SPI frame format; two bits per SCK, half-duplex + DUAL + 1 + + + Quad-SPI frame format; four bits per SCK, half-duplex + QUAD + 2 + + + SPI_FRF + + + read-write + [20:16] + Data frame size in 32b transfer mode\n + Value of n -> n+1 clocks per frame. + DFS_32 + + + read-write + [15:12] + Control frame size\n + Value of n -> n+1 clocks per frame. + CFS + + + read-write + [11:11] + Shift register loop (test mode) + SRL + + + read-write + [10:10] + Slave output enable + SLV_OE + + + read-write + [9:8] + Transfer mode + + + Both transmit and receive + TX_AND_RX + 0 + + + Transmit only (not for FRF == 0, standard SPI mode) + TX_ONLY + 1 + + + Receive only (not for FRF == 0, standard SPI mode) + RX_ONLY + 2 + + + EEPROM read mode (TX then RX; RX starts after control data TX'd) + EEPROM_READ + 3 + + + TMOD + + + read-write + [7:7] + Serial clock polarity + SCPOL + + + read-write + [6:6] + Serial clock phase + SCPH + + + read-write + [5:4] + Frame format + FRF + + + read-write + [3:0] + Data frame size + DFS + + + CTRLR0 + 0x00000000 + + + 0x0004 + Master Control register 1 + + + read-write + [15:0] + Number of data frames + NDF + + + CTRLR1 + 0x00000000 + + + 0x0008 + SSI Enable + + + read-write + [0:0] + SSI enable + SSI_EN + + + SSIENR + 0x00000000 + + + 0x000c + Microwire Control + + + read-write + [2:2] + Microwire handshaking + MHS + + + read-write + [1:1] + Microwire control + MDD + + + read-write + [0:0] + Microwire transfer mode + MWMOD + + + MWCR + 0x00000000 + + + 0x0010 + Slave enable + + + read-write + [0:0] + For each bit:\n + 0 -> slave not selected\n + 1 -> slave selected + SER + + + SER + 0x00000000 + + + 0x0014 + Baud rate + + + read-write + [15:0] + SSI clock divider + SCKDV + + + BAUDR + 0x00000000 + + + 0x0018 + TX FIFO threshold level + + + read-write + [7:0] + Transmit FIFO threshold + TFT + + + TXFTLR + 0x00000000 + + + 0x001c + RX FIFO threshold level + + + read-write + [7:0] + Receive FIFO threshold + RFT + + + RXFTLR + 0x00000000 + + + 0x0020 + TX FIFO level + + + read-only + [7:0] + Transmit FIFO level + TFTFL + + + TXFLR + 0x00000000 + + + 0x0024 + RX FIFO level + + + read-only + [7:0] + Receive FIFO level + RXTFL + + + RXFLR + 0x00000000 + + + 0x0028 + Status register + + + read-only + [6:6] + Data collision error + DCOL + + + read-only + [5:5] + Transmission error + TXE + + + read-only + [4:4] + Receive FIFO full + RFF + + + read-only + [3:3] + Receive FIFO not empty + RFNE + + + read-only + [2:2] + Transmit FIFO empty + TFE + + + read-only + [1:1] + Transmit FIFO not full + TFNF + + + read-only + [0:0] + SSI busy flag + BUSY + + + SR + 0x00000000 + + + 0x002c + Interrupt mask + + + read-write + [5:5] + Multi-master contention interrupt mask + MSTIM + + + read-write + [4:4] + Receive FIFO full interrupt mask + RXFIM + + + read-write + [3:3] + Receive FIFO overflow interrupt mask + RXOIM + + + read-write + [2:2] + Receive FIFO underflow interrupt mask + RXUIM + + + read-write + [1:1] + Transmit FIFO overflow interrupt mask + TXOIM + + + read-write + [0:0] + Transmit FIFO empty interrupt mask + TXEIM + + + IMR + 0x00000000 + + + 0x0030 + Interrupt status + + + read-only + [5:5] + Multi-master contention interrupt status + MSTIS + + + read-only + [4:4] + Receive FIFO full interrupt status + RXFIS + + + read-only + [3:3] + Receive FIFO overflow interrupt status + RXOIS + + + read-only + [2:2] + Receive FIFO underflow interrupt status + RXUIS + + + read-only + [1:1] + Transmit FIFO overflow interrupt status + TXOIS + + + read-only + [0:0] + Transmit FIFO empty interrupt status + TXEIS + + + ISR + 0x00000000 + + + 0x0034 + Raw interrupt status + + + read-only + [5:5] + Multi-master contention raw interrupt status + MSTIR + + + read-only + [4:4] + Receive FIFO full raw interrupt status + RXFIR + + + read-only + [3:3] + Receive FIFO overflow raw interrupt status + RXOIR + + + read-only + [2:2] + Receive FIFO underflow raw interrupt status + RXUIR + + + read-only + [1:1] + Transmit FIFO overflow raw interrupt status + TXOIR + + + read-only + [0:0] + Transmit FIFO empty raw interrupt status + TXEIR + + + RISR + 0x00000000 + + + 0x0038 + TX FIFO overflow interrupt clear + + + read-only + [0:0] + Clear-on-read transmit FIFO overflow interrupt + TXOICR + + + TXOICR + 0x00000000 + + + 0x003c + RX FIFO overflow interrupt clear + + + read-only + [0:0] + Clear-on-read receive FIFO overflow interrupt + RXOICR + + + RXOICR + 0x00000000 + + + 0x0040 + RX FIFO underflow interrupt clear + + + read-only + [0:0] + Clear-on-read receive FIFO underflow interrupt + RXUICR + + + RXUICR + 0x00000000 + + + 0x0044 + Multi-master interrupt clear + + + read-only + [0:0] + Clear-on-read multi-master contention interrupt + MSTICR + + + MSTICR + 0x00000000 + + + 0x0048 + Interrupt clear + + + read-only + [0:0] + Clear-on-read all active interrupts + ICR + + + ICR + 0x00000000 + + + 0x004c + DMA control + + + read-write + [1:1] + Transmit DMA enable + TDMAE + + + read-write + [0:0] + Receive DMA enable + RDMAE + + + DMACR + 0x00000000 + + + 0x0050 + DMA TX data level + + + read-write + [7:0] + Transmit data watermark level + DMATDL + + + DMATDLR + 0x00000000 + + + 0x0054 + DMA RX data level + + + read-write + [7:0] + Receive data watermark level (DMARDLR+1) + DMARDL + + + DMARDLR + 0x00000000 + + + 0x0058 + Identification register + + + read-only + [31:0] + Peripheral dentification code + IDCODE + + + IDR + 0x51535049 + + + 0x005c + Version ID + + + read-only + [31:0] + SNPS component version (format X.YY) + SSI_COMP_VERSION + + + SSI_VERSION_ID + 0x3430312a + + + 0x0060 + Data Register 0 (of 36) + + + read-write + [31:0] + First data register of 36 + DR + + + DR0 + 0x00000000 + + + 0x00f0 + RX sample delay + + + read-write + [7:0] + RXD sample delay (in SCLK cycles) + RSD + + + RX_SAMPLE_DLY + 0x00000000 + + + 0x00f4 + SPI control + + + read-write + [31:24] + SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + XIP_CMD + + + read-write + [18:18] + Read data strobe enable + SPI_RXDS_EN + + + read-write + [17:17] + Instruction DDR transfer enable + INST_DDR_EN + + + read-write + [16:16] + SPI DDR transfer enable + SPI_DDR_EN + + + read-write + [15:11] + Wait cycles between control frame transmit and data reception (in SCLK cycles) + WAIT_CYCLES + + + read-write + [9:8] + Instruction length (0/4/8/16b) + + + No instruction + NONE + 0 + + + 4-bit instruction + 4B + 1 + + + 8-bit instruction + 8B + 2 + + + 16-bit instruction + 16B + 3 + + + INST_L + + + read-write + [5:2] + Address length (0b-60b in 4b increments) + ADDR_L + + + read-write + [1:0] + Address and instruction transfer format + + + Command and address both in standard SPI frame format + 1C1A + 0 + + + Command in standard SPI format, address in format specified by FRF + 1C2A + 1 + + + Command and address both in format specified by FRF (e.g. Dual-SPI) + 2C2A + 2 + + + TRANS_TYPE + + + SPI_CTRLR0 + 0x03000000 + + + 0x00f8 + TX drive edge + + + read-write + [7:0] + TXD drive edge + TDE + + + TXD_DRIVE_EDGE + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40000000 + SYSINFO + + + 0x0000 + JEDEC JEP-106 compliant chip identifier. + + + read-only + [31:28] + REVISION + + + read-only + [27:12] + PART + + + read-only + [11:0] + MANUFACTURER + + + CHIP_ID + 0x00000000 + + + 0x0004 + Platform register. Allows software to know what environment it is running in. + + + read-only + [1:1] + ASIC + + + read-only + [0:0] + FPGA + + + PLATFORM + 0x00000000 + + + read-only + 0x0040 + Git hash of the chip source. Used to identify chip version. + GITREF_RP2040 + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40004000 + Register block for various chip control signals + SYSCFG + + + read-write + 0x0000 + Processor core 0 NMI source mask\n + Set a bit high to enable NMI from that IRQ + PROC0_NMI_MASK + 0x00000000 + + + read-write + 0x0004 + Processor core 1 NMI source mask\n + Set a bit high to enable NMI from that IRQ + PROC1_NMI_MASK + 0x00000000 + + + 0x0008 + Configuration for processors + + + read-write + [31:28] + Configure proc1 DAP instance ID.\n + Recommend that this is NOT changed until you require debug access in multi-chip environment\n + WARNING: do not set to 15 as this is reserved for RescueDP + PROC1_DAP_INSTID + + + read-write + [27:24] + Configure proc0 DAP instance ID.\n + Recommend that this is NOT changed until you require debug access in multi-chip environment\n + WARNING: do not set to 15 as this is reserved for RescueDP + PROC0_DAP_INSTID + + + read-only + [1:1] + Indication that proc1 has halted + PROC1_HALTED + + + read-only + [0:0] + Indication that proc0 has halted + PROC0_HALTED + + + PROC_CONFIG + 0x10000000 + + + 0x000c + For each bit, if 1, bypass the input synchronizer between that GPIO\n + and the GPIO input register in the SIO. The input synchronizers should\n + generally be unbypassed, to avoid injecting metastabilities into processors.\n + If you're feeling brave, you can bypass to save two cycles of input\n + latency. This register applies to GPIO 0...29. + + + read-write + [29:0] + PROC_IN_SYNC_BYPASS + + + PROC_IN_SYNC_BYPASS + 0x00000000 + + + 0x0010 + For each bit, if 1, bypass the input synchronizer between that GPIO\n + and the GPIO input register in the SIO. The input synchronizers should\n + generally be unbypassed, to avoid injecting metastabilities into processors.\n + If you're feeling brave, you can bypass to save two cycles of input\n + latency. This register applies to GPIO 30...35 (the QSPI IOs). + + + read-write + [5:0] + PROC_IN_SYNC_BYPASS_HI + + + PROC_IN_SYNC_BYPASS_HI + 0x00000000 + + + 0x0014 + Directly control the SWD debug port of either processor + + + read-write + [7:7] + Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. + PROC1_ATTACH + + + read-write + [6:6] + Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + PROC1_SWCLK + + + read-write + [5:5] + Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + PROC1_SWDI + + + read-only + [4:4] + Observe the value of processor 1 SWDIO output. + PROC1_SWDO + + + read-write + [3:3] + Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. + PROC0_ATTACH + + + read-write + [2:2] + Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + PROC0_SWCLK + + + read-write + [1:1] + Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + PROC0_SWDI + + + read-only + [0:0] + Observe the value of processor 0 SWDIO output. + PROC0_SWDO + + + DBGFORCE + 0x00000066 + + + 0x0018 + Control power downs to memories. Set high to power down memories.\n + Use with extreme caution + + + read-write + [7:7] + ROM + + + read-write + [6:6] + USB + + + read-write + [5:5] + SRAM5 + + + read-write + [4:4] + SRAM4 + + + read-write + [3:3] + SRAM3 + + + read-write + [2:2] + SRAM2 + + + read-write + [1:1] + SRAM1 + + + read-write + [0:0] + SRAM0 + + + MEMPOWERDOWN + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40008000 + + CLOCKS_IRQ + 17 + + CLOCKS + + + 0x0000 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [12:12] + Enables duty cycle correction for odd divisors + DC50 + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [8:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + AUXSRC + + + CLK_GPOUT0_CTRL + 0x00000000 + + + 0x0004 + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_GPOUT0_DIV + 0x00000100 + + + read-only + 0x0008 + Indicates which src is currently selected (one-hot) + CLK_GPOUT0_SELECTED + 0x00000001 + + + 0x000c + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [12:12] + Enables duty cycle correction for odd divisors + DC50 + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [8:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + AUXSRC + + + CLK_GPOUT1_CTRL + 0x00000000 + + + 0x0010 + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_GPOUT1_DIV + 0x00000100 + + + read-only + 0x0014 + Indicates which src is currently selected (one-hot) + CLK_GPOUT1_SELECTED + 0x00000001 + + + 0x0018 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [12:12] + Enables duty cycle correction for odd divisors + DC50 + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [8:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + AUXSRC + + + CLK_GPOUT2_CTRL + 0x00000000 + + + 0x001c + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_GPOUT2_DIV + 0x00000100 + + + read-only + 0x0020 + Indicates which src is currently selected (one-hot) + CLK_GPOUT2_SELECTED + 0x00000001 + + + 0x0024 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [12:12] + Enables duty cycle correction for odd divisors + DC50 + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [8:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + AUXSRC + + + CLK_GPOUT3_CTRL + 0x00000000 + + + 0x0028 + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_GPOUT3_DIV + 0x00000100 + + + read-only + 0x002c + Indicates which src is currently selected (one-hot) + CLK_GPOUT3_SELECTED + 0x00000001 + + + 0x0030 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [6:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + AUXSRC + + + read-write + [1:0] + Selects the clock source glitchlessly, can be changed on-the-fly + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + SRC + + + CLK_REF_CTRL + 0x00000000 + + + 0x0034 + Clock divisor, can be changed on-the-fly + + + read-write + [9:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + CLK_REF_DIV + 0x00000100 + + + read-only + 0x0038 + Indicates which src is currently selected (one-hot) + CLK_REF_SELECTED + 0x00000001 + + + 0x003c + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [7:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + AUXSRC + + + read-write + [0:0] + Selects the clock source glitchlessly, can be changed on-the-fly + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + SRC + + + CLK_SYS_CTRL + 0x00000000 + + + 0x0040 + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_SYS_DIV + 0x00000100 + + + read-only + 0x0044 + Indicates which src is currently selected (one-hot) + CLK_SYS_SELECTED + 0x00000001 + + + 0x0048 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [7:5] + Selects the auxiliary clock source, will glitch when switching + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + AUXSRC + + + CLK_PERI_CTRL + 0x00000000 + + + read-only + 0x0050 + Indicates which src is currently selected (one-hot) + CLK_PERI_SELECTED + 0x00000001 + + + 0x0054 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [7:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + AUXSRC + + + CLK_USB_CTRL + 0x00000000 + + + 0x0058 + Clock divisor, can be changed on-the-fly + + + read-write + [9:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + CLK_USB_DIV + 0x00000100 + + + read-only + 0x005c + Indicates which src is currently selected (one-hot) + CLK_USB_SELECTED + 0x00000001 + + + 0x0060 + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [7:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + AUXSRC + + + CLK_ADC_CTRL + 0x00000000 + + + 0x0064 + Clock divisor, can be changed on-the-fly + + + read-write + [9:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + CLK_ADC_DIV + 0x00000100 + + + read-only + 0x0068 + Indicates which src is currently selected (one-hot) + CLK_ADC_SELECTED + 0x00000001 + + + 0x006c + Clock control, can be changed on-the-fly (except for auxsrc) + + + read-write + [20:20] + An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n + This can be done at any time + NUDGE + + + read-write + [17:16] + This delays the enable signal by up to 3 cycles of the input clock\n + This must be set before the clock is enabled to have any effect + PHASE + + + read-write + [11:11] + Starts and stops the clock generator cleanly + ENABLE + + + read-write + [10:10] + Asynchronously kills the clock generator + KILL + + + read-write + [7:5] + Selects the auxiliary clock source, will glitch when switching + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + AUXSRC + + + CLK_RTC_CTRL + 0x00000000 + + + 0x0070 + Clock divisor, can be changed on-the-fly + + + read-write + [31:8] + Integer component of the divisor, 0 -> divide by 2^16 + INT + + + read-write + [7:0] + Fractional component of the divisor + FRAC + + + CLK_RTC_DIV + 0x00000100 + + + read-only + 0x0074 + Indicates which src is currently selected (one-hot) + CLK_RTC_SELECTED + 0x00000001 + + + 0x0078 + + + read-write + [16:16] + For clearing the resus after the fault that triggered it has been corrected + CLEAR + + + read-write + [12:12] + Force a resus, for test purposes only + FRCE + + + read-write + [8:8] + Enable resus + ENABLE + + + read-write + [7:0] + This is expressed as a number of clk_ref cycles\n + and must be >= 2x clk_ref_freq/min_clk_tst_freq + TIMEOUT + + + CLK_SYS_RESUS_CTRL + 0x000000ff + + + 0x007c + + + read-only + [0:0] + Clock has been resuscitated, correct the error then send ctrl_clear=1 + RESUSSED + + + CLK_SYS_RESUS_STATUS + 0x00000000 + + + 0x0080 + Reference clock frequency in kHz + + + read-write + [19:0] + FC0_REF_KHZ + + + FC0_REF_KHZ + 0x00000000 + + + 0x0084 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + + + read-write + [24:0] + FC0_MIN_KHZ + + + FC0_MIN_KHZ + 0x00000000 + + + 0x0088 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + + + read-write + [24:0] + FC0_MAX_KHZ + + + FC0_MAX_KHZ + 0x01ffffff + + + 0x008c + Delays the start of frequency counting to allow the mux to settle\n + Delay is measured in multiples of the reference clock period + + + read-write + [2:0] + FC0_DELAY + + + FC0_DELAY + 0x00000001 + + + 0x0090 + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n + The default gives a test interval of 250us + + + read-write + [3:0] + FC0_INTERVAL + + + FC0_INTERVAL + 0x00000008 + + + 0x0094 + Clock sent to frequency counter, set to 0 when not required\n + Writing to this register initiates the frequency count + + + read-write + [7:0] + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_rtc + 13 + + + FC0_SRC + + + FC0_SRC + 0x00000000 + + + 0x0098 + Frequency counter status + + + read-only + [28:28] + Test clock stopped during test + DIED + + + read-only + [24:24] + Test clock faster than expected, only valid when status_done=1 + FAST + + + read-only + [20:20] + Test clock slower than expected, only valid when status_done=1 + SLOW + + + read-only + [16:16] + Test failed + FAIL + + + read-only + [12:12] + Waiting for test clock to start + WAITING + + + read-only + [8:8] + Test running + RUNNING + + + read-only + [4:4] + Test complete + DONE + + + read-only + [0:0] + Test passed + PASS + + + FC0_STATUS + 0x00000000 + + + 0x009c + Result of frequency measurement, only valid when status_done=1 + + + read-only + [29:5] + KHZ + + + read-only + [4:0] + FRAC + + + FC0_RESULT + 0x00000000 + + + 0x00a0 + enable clock in wake mode + + + read-write + [31:31] + clk_sys_sram3 + + + read-write + [30:30] + clk_sys_sram2 + + + read-write + [29:29] + clk_sys_sram1 + + + read-write + [28:28] + clk_sys_sram0 + + + read-write + [27:27] + clk_sys_spi1 + + + read-write + [26:26] + clk_peri_spi1 + + + read-write + [25:25] + clk_sys_spi0 + + + read-write + [24:24] + clk_peri_spi0 + + + read-write + [23:23] + clk_sys_sio + + + read-write + [22:22] + clk_sys_rtc + + + read-write + [21:21] + clk_rtc_rtc + + + read-write + [20:20] + clk_sys_rosc + + + read-write + [19:19] + clk_sys_rom + + + read-write + [18:18] + clk_sys_resets + + + read-write + [17:17] + clk_sys_pwm + + + read-write + [16:16] + clk_sys_psm + + + read-write + [15:15] + clk_sys_pll_usb + + + read-write + [14:14] + clk_sys_pll_sys + + + read-write + [13:13] + clk_sys_pio1 + + + read-write + [12:12] + clk_sys_pio0 + + + read-write + [11:11] + clk_sys_pads + + + read-write + [10:10] + clk_sys_vreg_and_chip_reset + + + read-write + [9:9] + clk_sys_jtag + + + read-write + [8:8] + clk_sys_io + + + read-write + [7:7] + clk_sys_i2c1 + + + read-write + [6:6] + clk_sys_i2c0 + + + read-write + [5:5] + clk_sys_dma + + + read-write + [4:4] + clk_sys_busfabric + + + read-write + [3:3] + clk_sys_busctrl + + + read-write + [2:2] + clk_sys_adc + + + read-write + [1:1] + clk_adc_adc + + + read-write + [0:0] + clk_sys_clocks + + + WAKE_EN0 + 0xffffffff + + + 0x00a4 + enable clock in wake mode + + + read-write + [14:14] + clk_sys_xosc + + + read-write + [13:13] + clk_sys_xip + + + read-write + [12:12] + clk_sys_watchdog + + + read-write + [11:11] + clk_usb_usbctrl + + + read-write + [10:10] + clk_sys_usbctrl + + + read-write + [9:9] + clk_sys_uart1 + + + read-write + [8:8] + clk_peri_uart1 + + + read-write + [7:7] + clk_sys_uart0 + + + read-write + [6:6] + clk_peri_uart0 + + + read-write + [5:5] + clk_sys_timer + + + read-write + [4:4] + clk_sys_tbman + + + read-write + [3:3] + clk_sys_sysinfo + + + read-write + [2:2] + clk_sys_syscfg + + + read-write + [1:1] + clk_sys_sram5 + + + read-write + [0:0] + clk_sys_sram4 + + + WAKE_EN1 + 0x00007fff + + + 0x00a8 + enable clock in sleep mode + + + read-write + [31:31] + clk_sys_sram3 + + + read-write + [30:30] + clk_sys_sram2 + + + read-write + [29:29] + clk_sys_sram1 + + + read-write + [28:28] + clk_sys_sram0 + + + read-write + [27:27] + clk_sys_spi1 + + + read-write + [26:26] + clk_peri_spi1 + + + read-write + [25:25] + clk_sys_spi0 + + + read-write + [24:24] + clk_peri_spi0 + + + read-write + [23:23] + clk_sys_sio + + + read-write + [22:22] + clk_sys_rtc + + + read-write + [21:21] + clk_rtc_rtc + + + read-write + [20:20] + clk_sys_rosc + + + read-write + [19:19] + clk_sys_rom + + + read-write + [18:18] + clk_sys_resets + + + read-write + [17:17] + clk_sys_pwm + + + read-write + [16:16] + clk_sys_psm + + + read-write + [15:15] + clk_sys_pll_usb + + + read-write + [14:14] + clk_sys_pll_sys + + + read-write + [13:13] + clk_sys_pio1 + + + read-write + [12:12] + clk_sys_pio0 + + + read-write + [11:11] + clk_sys_pads + + + read-write + [10:10] + clk_sys_vreg_and_chip_reset + + + read-write + [9:9] + clk_sys_jtag + + + read-write + [8:8] + clk_sys_io + + + read-write + [7:7] + clk_sys_i2c1 + + + read-write + [6:6] + clk_sys_i2c0 + + + read-write + [5:5] + clk_sys_dma + + + read-write + [4:4] + clk_sys_busfabric + + + read-write + [3:3] + clk_sys_busctrl + + + read-write + [2:2] + clk_sys_adc + + + read-write + [1:1] + clk_adc_adc + + + read-write + [0:0] + clk_sys_clocks + + + SLEEP_EN0 + 0xffffffff + + + 0x00ac + enable clock in sleep mode + + + read-write + [14:14] + clk_sys_xosc + + + read-write + [13:13] + clk_sys_xip + + + read-write + [12:12] + clk_sys_watchdog + + + read-write + [11:11] + clk_usb_usbctrl + + + read-write + [10:10] + clk_sys_usbctrl + + + read-write + [9:9] + clk_sys_uart1 + + + read-write + [8:8] + clk_peri_uart1 + + + read-write + [7:7] + clk_sys_uart0 + + + read-write + [6:6] + clk_peri_uart0 + + + read-write + [5:5] + clk_sys_timer + + + read-write + [4:4] + clk_sys_tbman + + + read-write + [3:3] + clk_sys_sysinfo + + + read-write + [2:2] + clk_sys_syscfg + + + read-write + [1:1] + clk_sys_sram5 + + + read-write + [0:0] + clk_sys_sram4 + + + SLEEP_EN1 + 0x00007fff + + + 0x00b0 + indicates the state of the clock enable + + + read-only + [31:31] + clk_sys_sram3 + + + read-only + [30:30] + clk_sys_sram2 + + + read-only + [29:29] + clk_sys_sram1 + + + read-only + [28:28] + clk_sys_sram0 + + + read-only + [27:27] + clk_sys_spi1 + + + read-only + [26:26] + clk_peri_spi1 + + + read-only + [25:25] + clk_sys_spi0 + + + read-only + [24:24] + clk_peri_spi0 + + + read-only + [23:23] + clk_sys_sio + + + read-only + [22:22] + clk_sys_rtc + + + read-only + [21:21] + clk_rtc_rtc + + + read-only + [20:20] + clk_sys_rosc + + + read-only + [19:19] + clk_sys_rom + + + read-only + [18:18] + clk_sys_resets + + + read-only + [17:17] + clk_sys_pwm + + + read-only + [16:16] + clk_sys_psm + + + read-only + [15:15] + clk_sys_pll_usb + + + read-only + [14:14] + clk_sys_pll_sys + + + read-only + [13:13] + clk_sys_pio1 + + + read-only + [12:12] + clk_sys_pio0 + + + read-only + [11:11] + clk_sys_pads + + + read-only + [10:10] + clk_sys_vreg_and_chip_reset + + + read-only + [9:9] + clk_sys_jtag + + + read-only + [8:8] + clk_sys_io + + + read-only + [7:7] + clk_sys_i2c1 + + + read-only + [6:6] + clk_sys_i2c0 + + + read-only + [5:5] + clk_sys_dma + + + read-only + [4:4] + clk_sys_busfabric + + + read-only + [3:3] + clk_sys_busctrl + + + read-only + [2:2] + clk_sys_adc + + + read-only + [1:1] + clk_adc_adc + + + read-only + [0:0] + clk_sys_clocks + + + ENABLED0 + 0x00000000 + + + 0x00b4 + indicates the state of the clock enable + + + read-only + [14:14] + clk_sys_xosc + + + read-only + [13:13] + clk_sys_xip + + + read-only + [12:12] + clk_sys_watchdog + + + read-only + [11:11] + clk_usb_usbctrl + + + read-only + [10:10] + clk_sys_usbctrl + + + read-only + [9:9] + clk_sys_uart1 + + + read-only + [8:8] + clk_peri_uart1 + + + read-only + [7:7] + clk_sys_uart0 + + + read-only + [6:6] + clk_peri_uart0 + + + read-only + [5:5] + clk_sys_timer + + + read-only + [4:4] + clk_sys_tbman + + + read-only + [3:3] + clk_sys_sysinfo + + + read-only + [2:2] + clk_sys_syscfg + + + read-only + [1:1] + clk_sys_sram5 + + + read-only + [0:0] + clk_sys_sram4 + + + ENABLED1 + 0x00000000 + + + 0x00b8 + Raw Interrupts + + + read-only + [0:0] + CLK_SYS_RESUS + + + INTR + 0x00000000 + + + 0x00bc + Interrupt Enable + + + read-write + [0:0] + CLK_SYS_RESUS + + + INTE + 0x00000000 + + + 0x00c0 + Interrupt Force + + + read-write + [0:0] + CLK_SYS_RESUS + + + INTF + 0x00000000 + + + 0x00c4 + Interrupt status after masking & forcing + + + read-only + [0:0] + CLK_SYS_RESUS + + + INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x4000c000 + RESETS + + + 0x0000 + Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. + + + read-write + [24:24] + usbctrl + + + read-write + [23:23] + uart1 + + + read-write + [22:22] + uart0 + + + read-write + [21:21] + timer + + + read-write + [20:20] + tbman + + + read-write + [19:19] + sysinfo + + + read-write + [18:18] + syscfg + + + read-write + [17:17] + spi1 + + + read-write + [16:16] + spi0 + + + read-write + [15:15] + rtc + + + read-write + [14:14] + pwm + + + read-write + [13:13] + pll_usb + + + read-write + [12:12] + pll_sys + + + read-write + [11:11] + pio1 + + + read-write + [10:10] + pio0 + + + read-write + [9:9] + pads_qspi + + + read-write + [8:8] + pads_bank0 + + + read-write + [7:7] + jtag + + + read-write + [6:6] + io_qspi + + + read-write + [5:5] + io_bank0 + + + read-write + [4:4] + i2c1 + + + read-write + [3:3] + i2c0 + + + read-write + [2:2] + dma + + + read-write + [1:1] + busctrl + + + read-write + [0:0] + adc + + + RESET + 0x01ffffff + + + 0x0004 + Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. + + + read-write + [24:24] + usbctrl + + + read-write + [23:23] + uart1 + + + read-write + [22:22] + uart0 + + + read-write + [21:21] + timer + + + read-write + [20:20] + tbman + + + read-write + [19:19] + sysinfo + + + read-write + [18:18] + syscfg + + + read-write + [17:17] + spi1 + + + read-write + [16:16] + spi0 + + + read-write + [15:15] + rtc + + + read-write + [14:14] + pwm + + + read-write + [13:13] + pll_usb + + + read-write + [12:12] + pll_sys + + + read-write + [11:11] + pio1 + + + read-write + [10:10] + pio0 + + + read-write + [9:9] + pads_qspi + + + read-write + [8:8] + pads_bank0 + + + read-write + [7:7] + jtag + + + read-write + [6:6] + io_qspi + + + read-write + [5:5] + io_bank0 + + + read-write + [4:4] + i2c1 + + + read-write + [3:3] + i2c0 + + + read-write + [2:2] + dma + + + read-write + [1:1] + busctrl + + + read-write + [0:0] + adc + + + WDSEL + 0x00000000 + + + 0x0008 + Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. + + + read-only + [24:24] + usbctrl + + + read-only + [23:23] + uart1 + + + read-only + [22:22] + uart0 + + + read-only + [21:21] + timer + + + read-only + [20:20] + tbman + + + read-only + [19:19] + sysinfo + + + read-only + [18:18] + syscfg + + + read-only + [17:17] + spi1 + + + read-only + [16:16] + spi0 + + + read-only + [15:15] + rtc + + + read-only + [14:14] + pwm + + + read-only + [13:13] + pll_usb + + + read-only + [12:12] + pll_sys + + + read-only + [11:11] + pio1 + + + read-only + [10:10] + pio0 + + + read-only + [9:9] + pads_qspi + + + read-only + [8:8] + pads_bank0 + + + read-only + [7:7] + jtag + + + read-only + [6:6] + io_qspi + + + read-only + [5:5] + io_bank0 + + + read-only + [4:4] + i2c1 + + + read-only + [3:3] + i2c0 + + + read-only + [2:2] + dma + + + read-only + [1:1] + busctrl + + + read-only + [0:0] + adc + + + RESET_DONE + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40010000 + PSM + + + 0x0000 + Force block out of reset (i.e. power it on) + + + read-write + [16:16] + proc1 + + + read-write + [15:15] + proc0 + + + read-write + [14:14] + sio + + + read-write + [13:13] + vreg_and_chip_reset + + + read-write + [12:12] + xip + + + read-write + [11:11] + sram5 + + + read-write + [10:10] + sram4 + + + read-write + [9:9] + sram3 + + + read-write + [8:8] + sram2 + + + read-write + [7:7] + sram1 + + + read-write + [6:6] + sram0 + + + read-write + [5:5] + rom + + + read-write + [4:4] + busfabric + + + read-write + [3:3] + resets + + + read-write + [2:2] + clocks + + + read-write + [1:1] + xosc + + + read-write + [0:0] + rosc + + + FRCE_ON + 0x00000000 + + + 0x0004 + Force into reset (i.e. power it off) + + + read-write + [16:16] + proc1 + + + read-write + [15:15] + proc0 + + + read-write + [14:14] + sio + + + read-write + [13:13] + vreg_and_chip_reset + + + read-write + [12:12] + xip + + + read-write + [11:11] + sram5 + + + read-write + [10:10] + sram4 + + + read-write + [9:9] + sram3 + + + read-write + [8:8] + sram2 + + + read-write + [7:7] + sram1 + + + read-write + [6:6] + sram0 + + + read-write + [5:5] + rom + + + read-write + [4:4] + busfabric + + + read-write + [3:3] + resets + + + read-write + [2:2] + clocks + + + read-write + [1:1] + xosc + + + read-write + [0:0] + rosc + + + FRCE_OFF + 0x00000000 + + + 0x0008 + Set to 1 if this peripheral should be reset when the watchdog fires. + + + read-write + [16:16] + proc1 + + + read-write + [15:15] + proc0 + + + read-write + [14:14] + sio + + + read-write + [13:13] + vreg_and_chip_reset + + + read-write + [12:12] + xip + + + read-write + [11:11] + sram5 + + + read-write + [10:10] + sram4 + + + read-write + [9:9] + sram3 + + + read-write + [8:8] + sram2 + + + read-write + [7:7] + sram1 + + + read-write + [6:6] + sram0 + + + read-write + [5:5] + rom + + + read-write + [4:4] + busfabric + + + read-write + [3:3] + resets + + + read-write + [2:2] + clocks + + + read-write + [1:1] + xosc + + + read-write + [0:0] + rosc + + + WDSEL + 0x00000000 + + + 0x000c + Indicates the peripheral's registers are ready to access. + + + read-only + [16:16] + proc1 + + + read-only + [15:15] + proc0 + + + read-only + [14:14] + sio + + + read-only + [13:13] + vreg_and_chip_reset + + + read-only + [12:12] + xip + + + read-only + [11:11] + sram5 + + + read-only + [10:10] + sram4 + + + read-only + [9:9] + sram3 + + + read-only + [8:8] + sram2 + + + read-only + [7:7] + sram1 + + + read-only + [6:6] + sram0 + + + read-only + [5:5] + rom + + + read-only + [4:4] + busfabric + + + read-only + [3:3] + resets + + + read-only + [2:2] + clocks + + + read-only + [1:1] + xosc + + + read-only + [0:0] + rosc + + + DONE + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40014000 + + IO_IRQ_BANK0 + 13 + + IO_BANK0 + + + 0x0000 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO0_STATUS + 0x00000000 + + + 0x0004 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO0_CTRL + 0x0000001f + + + 0x0008 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO1_STATUS + 0x00000000 + + + 0x000c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO1_CTRL + 0x0000001f + + + 0x0010 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO2_STATUS + 0x00000000 + + + 0x0014 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO2_CTRL + 0x0000001f + + + 0x0018 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO3_STATUS + 0x00000000 + + + 0x001c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO3_CTRL + 0x0000001f + + + 0x0020 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO4_STATUS + 0x00000000 + + + 0x0024 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO4_CTRL + 0x0000001f + + + 0x0028 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO5_STATUS + 0x00000000 + + + 0x002c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO5_CTRL + 0x0000001f + + + 0x0030 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO6_STATUS + 0x00000000 + + + 0x0034 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + usb_muxing_extphy_softcon + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO6_CTRL + 0x0000001f + + + 0x0038 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO7_STATUS + 0x00000000 + + + 0x003c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + usb_muxing_extphy_oe_n + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO7_CTRL + 0x0000001f + + + 0x0040 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO8_STATUS + 0x00000000 + + + 0x0044 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + usb_muxing_extphy_rcv + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO8_CTRL + 0x0000001f + + + 0x0048 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO9_STATUS + 0x00000000 + + + 0x004c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + usb_muxing_extphy_vp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO9_CTRL + 0x0000001f + + + 0x0050 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO10_STATUS + 0x00000000 + + + 0x0054 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + usb_muxing_extphy_vm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO10_CTRL + 0x0000001f + + + 0x0058 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO11_STATUS + 0x00000000 + + + 0x005c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + usb_muxing_extphy_suspnd + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO11_CTRL + 0x0000001f + + + 0x0060 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO12_STATUS + 0x00000000 + + + 0x0064 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + usb_muxing_extphy_speed + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO12_CTRL + 0x0000001f + + + 0x0068 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO13_STATUS + 0x00000000 + + + 0x006c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + usb_muxing_extphy_vpo + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO13_CTRL + 0x0000001f + + + 0x0070 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO14_STATUS + 0x00000000 + + + 0x0074 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + sio_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + usb_muxing_extphy_vmo + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO14_CTRL + 0x0000001f + + + 0x0078 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO15_STATUS + 0x00000000 + + + 0x007c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + sio_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + usb_muxing_digital_dp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO15_CTRL + 0x0000001f + + + 0x0080 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO16_STATUS + 0x00000000 + + + 0x0084 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + usb_muxing_digital_dm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO16_CTRL + 0x0000001f + + + 0x0088 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO17_STATUS + 0x00000000 + + + 0x008c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO17_CTRL + 0x0000001f + + + 0x0090 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO18_STATUS + 0x00000000 + + + 0x0094 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO18_CTRL + 0x0000001f + + + 0x0098 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO19_STATUS + 0x00000000 + + + 0x009c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO19_CTRL + 0x0000001f + + + 0x00a0 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO20_STATUS + 0x00000000 + + + 0x00a4 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + clocks_gpin_0 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO20_CTRL + 0x0000001f + + + 0x00a8 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO21_STATUS + 0x00000000 + + + 0x00ac + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + clocks_gpout_0 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO21_CTRL + 0x0000001f + + + 0x00b0 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO22_STATUS + 0x00000000 + + + 0x00b4 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + clocks_gpin_1 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO22_CTRL + 0x0000001f + + + 0x00b8 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO23_STATUS + 0x00000000 + + + 0x00bc + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + clocks_gpout_1 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO23_CTRL + 0x0000001f + + + 0x00c0 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO24_STATUS + 0x00000000 + + + 0x00c4 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + clocks_gpout_2 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO24_CTRL + 0x0000001f + + + 0x00c8 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO25_STATUS + 0x00000000 + + + 0x00cc + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + clocks_gpout_3 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO25_CTRL + 0x0000001f + + + 0x00d0 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO26_STATUS + 0x00000000 + + + 0x00d4 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO26_CTRL + 0x0000001f + + + 0x00d8 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO27_STATUS + 0x00000000 + + + 0x00dc + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO27_CTRL + 0x0000001f + + + 0x00e0 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO28_STATUS + 0x00000000 + + + 0x00e4 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + FUNCSEL + + + GPIO28_CTRL + 0x0000001f + + + 0x00e8 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO29_STATUS + 0x00000000 + + + 0x00ec + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + FUNCSEL + + + GPIO29_CTRL + 0x0000001f + + + 0x00f0 + Raw Interrupts + + + read-write + [31:31] + oneToClear + GPIO7_EDGE_HIGH + + + read-write + [30:30] + oneToClear + GPIO7_EDGE_LOW + + + read-only + [29:29] + GPIO7_LEVEL_HIGH + + + read-only + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + oneToClear + GPIO6_EDGE_HIGH + + + read-write + [26:26] + oneToClear + GPIO6_EDGE_LOW + + + read-only + [25:25] + GPIO6_LEVEL_HIGH + + + read-only + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + oneToClear + GPIO5_EDGE_HIGH + + + read-write + [22:22] + oneToClear + GPIO5_EDGE_LOW + + + read-only + [21:21] + GPIO5_LEVEL_HIGH + + + read-only + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + oneToClear + GPIO4_EDGE_HIGH + + + read-write + [18:18] + oneToClear + GPIO4_EDGE_LOW + + + read-only + [17:17] + GPIO4_LEVEL_HIGH + + + read-only + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + oneToClear + GPIO3_EDGE_HIGH + + + read-write + [14:14] + oneToClear + GPIO3_EDGE_LOW + + + read-only + [13:13] + GPIO3_LEVEL_HIGH + + + read-only + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + oneToClear + GPIO2_EDGE_HIGH + + + read-write + [10:10] + oneToClear + GPIO2_EDGE_LOW + + + read-only + [9:9] + GPIO2_LEVEL_HIGH + + + read-only + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + oneToClear + GPIO1_EDGE_HIGH + + + read-write + [6:6] + oneToClear + GPIO1_EDGE_LOW + + + read-only + [5:5] + GPIO1_LEVEL_HIGH + + + read-only + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + oneToClear + GPIO0_EDGE_HIGH + + + read-write + [2:2] + oneToClear + GPIO0_EDGE_LOW + + + read-only + [1:1] + GPIO0_LEVEL_HIGH + + + read-only + [0:0] + GPIO0_LEVEL_LOW + + + INTR0 + 0x00000000 + + + 0x00f4 + Raw Interrupts + + + read-write + [31:31] + oneToClear + GPIO15_EDGE_HIGH + + + read-write + [30:30] + oneToClear + GPIO15_EDGE_LOW + + + read-only + [29:29] + GPIO15_LEVEL_HIGH + + + read-only + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + oneToClear + GPIO14_EDGE_HIGH + + + read-write + [26:26] + oneToClear + GPIO14_EDGE_LOW + + + read-only + [25:25] + GPIO14_LEVEL_HIGH + + + read-only + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + oneToClear + GPIO13_EDGE_HIGH + + + read-write + [22:22] + oneToClear + GPIO13_EDGE_LOW + + + read-only + [21:21] + GPIO13_LEVEL_HIGH + + + read-only + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + oneToClear + GPIO12_EDGE_HIGH + + + read-write + [18:18] + oneToClear + GPIO12_EDGE_LOW + + + read-only + [17:17] + GPIO12_LEVEL_HIGH + + + read-only + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + oneToClear + GPIO11_EDGE_HIGH + + + read-write + [14:14] + oneToClear + GPIO11_EDGE_LOW + + + read-only + [13:13] + GPIO11_LEVEL_HIGH + + + read-only + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + oneToClear + GPIO10_EDGE_HIGH + + + read-write + [10:10] + oneToClear + GPIO10_EDGE_LOW + + + read-only + [9:9] + GPIO10_LEVEL_HIGH + + + read-only + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + oneToClear + GPIO9_EDGE_HIGH + + + read-write + [6:6] + oneToClear + GPIO9_EDGE_LOW + + + read-only + [5:5] + GPIO9_LEVEL_HIGH + + + read-only + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + oneToClear + GPIO8_EDGE_HIGH + + + read-write + [2:2] + oneToClear + GPIO8_EDGE_LOW + + + read-only + [1:1] + GPIO8_LEVEL_HIGH + + + read-only + [0:0] + GPIO8_LEVEL_LOW + + + INTR1 + 0x00000000 + + + 0x00f8 + Raw Interrupts + + + read-write + [31:31] + oneToClear + GPIO23_EDGE_HIGH + + + read-write + [30:30] + oneToClear + GPIO23_EDGE_LOW + + + read-only + [29:29] + GPIO23_LEVEL_HIGH + + + read-only + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + oneToClear + GPIO22_EDGE_HIGH + + + read-write + [26:26] + oneToClear + GPIO22_EDGE_LOW + + + read-only + [25:25] + GPIO22_LEVEL_HIGH + + + read-only + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + oneToClear + GPIO21_EDGE_HIGH + + + read-write + [22:22] + oneToClear + GPIO21_EDGE_LOW + + + read-only + [21:21] + GPIO21_LEVEL_HIGH + + + read-only + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + oneToClear + GPIO20_EDGE_HIGH + + + read-write + [18:18] + oneToClear + GPIO20_EDGE_LOW + + + read-only + [17:17] + GPIO20_LEVEL_HIGH + + + read-only + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + oneToClear + GPIO19_EDGE_HIGH + + + read-write + [14:14] + oneToClear + GPIO19_EDGE_LOW + + + read-only + [13:13] + GPIO19_LEVEL_HIGH + + + read-only + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + oneToClear + GPIO18_EDGE_HIGH + + + read-write + [10:10] + oneToClear + GPIO18_EDGE_LOW + + + read-only + [9:9] + GPIO18_LEVEL_HIGH + + + read-only + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + oneToClear + GPIO17_EDGE_HIGH + + + read-write + [6:6] + oneToClear + GPIO17_EDGE_LOW + + + read-only + [5:5] + GPIO17_LEVEL_HIGH + + + read-only + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + oneToClear + GPIO16_EDGE_HIGH + + + read-write + [2:2] + oneToClear + GPIO16_EDGE_LOW + + + read-only + [1:1] + GPIO16_LEVEL_HIGH + + + read-only + [0:0] + GPIO16_LEVEL_LOW + + + INTR2 + 0x00000000 + + + 0x00fc + Raw Interrupts + + + read-write + [23:23] + oneToClear + GPIO29_EDGE_HIGH + + + read-write + [22:22] + oneToClear + GPIO29_EDGE_LOW + + + read-only + [21:21] + GPIO29_LEVEL_HIGH + + + read-only + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + oneToClear + GPIO28_EDGE_HIGH + + + read-write + [18:18] + oneToClear + GPIO28_EDGE_LOW + + + read-only + [17:17] + GPIO28_LEVEL_HIGH + + + read-only + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + oneToClear + GPIO27_EDGE_HIGH + + + read-write + [14:14] + oneToClear + GPIO27_EDGE_LOW + + + read-only + [13:13] + GPIO27_LEVEL_HIGH + + + read-only + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + oneToClear + GPIO26_EDGE_HIGH + + + read-write + [10:10] + oneToClear + GPIO26_EDGE_LOW + + + read-only + [9:9] + GPIO26_LEVEL_HIGH + + + read-only + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + oneToClear + GPIO25_EDGE_HIGH + + + read-write + [6:6] + oneToClear + GPIO25_EDGE_LOW + + + read-only + [5:5] + GPIO25_LEVEL_HIGH + + + read-only + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + oneToClear + GPIO24_EDGE_HIGH + + + read-write + [2:2] + oneToClear + GPIO24_EDGE_LOW + + + read-only + [1:1] + GPIO24_LEVEL_HIGH + + + read-only + [0:0] + GPIO24_LEVEL_LOW + + + INTR3 + 0x00000000 + + + 0x0100 + Interrupt Enable for proc0 + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + PROC0_INTE0 + 0x00000000 + + + 0x0104 + Interrupt Enable for proc0 + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + PROC0_INTE1 + 0x00000000 + + + 0x0108 + Interrupt Enable for proc0 + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + PROC0_INTE2 + 0x00000000 + + + 0x010c + Interrupt Enable for proc0 + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + PROC0_INTE3 + 0x00000000 + + + 0x0110 + Interrupt Force for proc0 + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + PROC0_INTF0 + 0x00000000 + + + 0x0114 + Interrupt Force for proc0 + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + PROC0_INTF1 + 0x00000000 + + + 0x0118 + Interrupt Force for proc0 + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + PROC0_INTF2 + 0x00000000 + + + 0x011c + Interrupt Force for proc0 + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + PROC0_INTF3 + 0x00000000 + + + 0x0120 + Interrupt status after masking & forcing for proc0 + + + read-only + [31:31] + GPIO7_EDGE_HIGH + + + read-only + [30:30] + GPIO7_EDGE_LOW + + + read-only + [29:29] + GPIO7_LEVEL_HIGH + + + read-only + [28:28] + GPIO7_LEVEL_LOW + + + read-only + [27:27] + GPIO6_EDGE_HIGH + + + read-only + [26:26] + GPIO6_EDGE_LOW + + + read-only + [25:25] + GPIO6_LEVEL_HIGH + + + read-only + [24:24] + GPIO6_LEVEL_LOW + + + read-only + [23:23] + GPIO5_EDGE_HIGH + + + read-only + [22:22] + GPIO5_EDGE_LOW + + + read-only + [21:21] + GPIO5_LEVEL_HIGH + + + read-only + [20:20] + GPIO5_LEVEL_LOW + + + read-only + [19:19] + GPIO4_EDGE_HIGH + + + read-only + [18:18] + GPIO4_EDGE_LOW + + + read-only + [17:17] + GPIO4_LEVEL_HIGH + + + read-only + [16:16] + GPIO4_LEVEL_LOW + + + read-only + [15:15] + GPIO3_EDGE_HIGH + + + read-only + [14:14] + GPIO3_EDGE_LOW + + + read-only + [13:13] + GPIO3_LEVEL_HIGH + + + read-only + [12:12] + GPIO3_LEVEL_LOW + + + read-only + [11:11] + GPIO2_EDGE_HIGH + + + read-only + [10:10] + GPIO2_EDGE_LOW + + + read-only + [9:9] + GPIO2_LEVEL_HIGH + + + read-only + [8:8] + GPIO2_LEVEL_LOW + + + read-only + [7:7] + GPIO1_EDGE_HIGH + + + read-only + [6:6] + GPIO1_EDGE_LOW + + + read-only + [5:5] + GPIO1_LEVEL_HIGH + + + read-only + [4:4] + GPIO1_LEVEL_LOW + + + read-only + [3:3] + GPIO0_EDGE_HIGH + + + read-only + [2:2] + GPIO0_EDGE_LOW + + + read-only + [1:1] + GPIO0_LEVEL_HIGH + + + read-only + [0:0] + GPIO0_LEVEL_LOW + + + PROC0_INTS0 + 0x00000000 + + + 0x0124 + Interrupt status after masking & forcing for proc0 + + + read-only + [31:31] + GPIO15_EDGE_HIGH + + + read-only + [30:30] + GPIO15_EDGE_LOW + + + read-only + [29:29] + GPIO15_LEVEL_HIGH + + + read-only + [28:28] + GPIO15_LEVEL_LOW + + + read-only + [27:27] + GPIO14_EDGE_HIGH + + + read-only + [26:26] + GPIO14_EDGE_LOW + + + read-only + [25:25] + GPIO14_LEVEL_HIGH + + + read-only + [24:24] + GPIO14_LEVEL_LOW + + + read-only + [23:23] + GPIO13_EDGE_HIGH + + + read-only + [22:22] + GPIO13_EDGE_LOW + + + read-only + [21:21] + GPIO13_LEVEL_HIGH + + + read-only + [20:20] + GPIO13_LEVEL_LOW + + + read-only + [19:19] + GPIO12_EDGE_HIGH + + + read-only + [18:18] + GPIO12_EDGE_LOW + + + read-only + [17:17] + GPIO12_LEVEL_HIGH + + + read-only + [16:16] + GPIO12_LEVEL_LOW + + + read-only + [15:15] + GPIO11_EDGE_HIGH + + + read-only + [14:14] + GPIO11_EDGE_LOW + + + read-only + [13:13] + GPIO11_LEVEL_HIGH + + + read-only + [12:12] + GPIO11_LEVEL_LOW + + + read-only + [11:11] + GPIO10_EDGE_HIGH + + + read-only + [10:10] + GPIO10_EDGE_LOW + + + read-only + [9:9] + GPIO10_LEVEL_HIGH + + + read-only + [8:8] + GPIO10_LEVEL_LOW + + + read-only + [7:7] + GPIO9_EDGE_HIGH + + + read-only + [6:6] + GPIO9_EDGE_LOW + + + read-only + [5:5] + GPIO9_LEVEL_HIGH + + + read-only + [4:4] + GPIO9_LEVEL_LOW + + + read-only + [3:3] + GPIO8_EDGE_HIGH + + + read-only + [2:2] + GPIO8_EDGE_LOW + + + read-only + [1:1] + GPIO8_LEVEL_HIGH + + + read-only + [0:0] + GPIO8_LEVEL_LOW + + + PROC0_INTS1 + 0x00000000 + + + 0x0128 + Interrupt status after masking & forcing for proc0 + + + read-only + [31:31] + GPIO23_EDGE_HIGH + + + read-only + [30:30] + GPIO23_EDGE_LOW + + + read-only + [29:29] + GPIO23_LEVEL_HIGH + + + read-only + [28:28] + GPIO23_LEVEL_LOW + + + read-only + [27:27] + GPIO22_EDGE_HIGH + + + read-only + [26:26] + GPIO22_EDGE_LOW + + + read-only + [25:25] + GPIO22_LEVEL_HIGH + + + read-only + [24:24] + GPIO22_LEVEL_LOW + + + read-only + [23:23] + GPIO21_EDGE_HIGH + + + read-only + [22:22] + GPIO21_EDGE_LOW + + + read-only + [21:21] + GPIO21_LEVEL_HIGH + + + read-only + [20:20] + GPIO21_LEVEL_LOW + + + read-only + [19:19] + GPIO20_EDGE_HIGH + + + read-only + [18:18] + GPIO20_EDGE_LOW + + + read-only + [17:17] + GPIO20_LEVEL_HIGH + + + read-only + [16:16] + GPIO20_LEVEL_LOW + + + read-only + [15:15] + GPIO19_EDGE_HIGH + + + read-only + [14:14] + GPIO19_EDGE_LOW + + + read-only + [13:13] + GPIO19_LEVEL_HIGH + + + read-only + [12:12] + GPIO19_LEVEL_LOW + + + read-only + [11:11] + GPIO18_EDGE_HIGH + + + read-only + [10:10] + GPIO18_EDGE_LOW + + + read-only + [9:9] + GPIO18_LEVEL_HIGH + + + read-only + [8:8] + GPIO18_LEVEL_LOW + + + read-only + [7:7] + GPIO17_EDGE_HIGH + + + read-only + [6:6] + GPIO17_EDGE_LOW + + + read-only + [5:5] + GPIO17_LEVEL_HIGH + + + read-only + [4:4] + GPIO17_LEVEL_LOW + + + read-only + [3:3] + GPIO16_EDGE_HIGH + + + read-only + [2:2] + GPIO16_EDGE_LOW + + + read-only + [1:1] + GPIO16_LEVEL_HIGH + + + read-only + [0:0] + GPIO16_LEVEL_LOW + + + PROC0_INTS2 + 0x00000000 + + + 0x012c + Interrupt status after masking & forcing for proc0 + + + read-only + [23:23] + GPIO29_EDGE_HIGH + + + read-only + [22:22] + GPIO29_EDGE_LOW + + + read-only + [21:21] + GPIO29_LEVEL_HIGH + + + read-only + [20:20] + GPIO29_LEVEL_LOW + + + read-only + [19:19] + GPIO28_EDGE_HIGH + + + read-only + [18:18] + GPIO28_EDGE_LOW + + + read-only + [17:17] + GPIO28_LEVEL_HIGH + + + read-only + [16:16] + GPIO28_LEVEL_LOW + + + read-only + [15:15] + GPIO27_EDGE_HIGH + + + read-only + [14:14] + GPIO27_EDGE_LOW + + + read-only + [13:13] + GPIO27_LEVEL_HIGH + + + read-only + [12:12] + GPIO27_LEVEL_LOW + + + read-only + [11:11] + GPIO26_EDGE_HIGH + + + read-only + [10:10] + GPIO26_EDGE_LOW + + + read-only + [9:9] + GPIO26_LEVEL_HIGH + + + read-only + [8:8] + GPIO26_LEVEL_LOW + + + read-only + [7:7] + GPIO25_EDGE_HIGH + + + read-only + [6:6] + GPIO25_EDGE_LOW + + + read-only + [5:5] + GPIO25_LEVEL_HIGH + + + read-only + [4:4] + GPIO25_LEVEL_LOW + + + read-only + [3:3] + GPIO24_EDGE_HIGH + + + read-only + [2:2] + GPIO24_EDGE_LOW + + + read-only + [1:1] + GPIO24_LEVEL_HIGH + + + read-only + [0:0] + GPIO24_LEVEL_LOW + + + PROC0_INTS3 + 0x00000000 + + + 0x0130 + Interrupt Enable for proc1 + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + PROC1_INTE0 + 0x00000000 + + + 0x0134 + Interrupt Enable for proc1 + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + PROC1_INTE1 + 0x00000000 + + + 0x0138 + Interrupt Enable for proc1 + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + PROC1_INTE2 + 0x00000000 + + + 0x013c + Interrupt Enable for proc1 + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + PROC1_INTE3 + 0x00000000 + + + 0x0140 + Interrupt Force for proc1 + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + PROC1_INTF0 + 0x00000000 + + + 0x0144 + Interrupt Force for proc1 + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + PROC1_INTF1 + 0x00000000 + + + 0x0148 + Interrupt Force for proc1 + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + PROC1_INTF2 + 0x00000000 + + + 0x014c + Interrupt Force for proc1 + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + PROC1_INTF3 + 0x00000000 + + + 0x0150 + Interrupt status after masking & forcing for proc1 + + + read-only + [31:31] + GPIO7_EDGE_HIGH + + + read-only + [30:30] + GPIO7_EDGE_LOW + + + read-only + [29:29] + GPIO7_LEVEL_HIGH + + + read-only + [28:28] + GPIO7_LEVEL_LOW + + + read-only + [27:27] + GPIO6_EDGE_HIGH + + + read-only + [26:26] + GPIO6_EDGE_LOW + + + read-only + [25:25] + GPIO6_LEVEL_HIGH + + + read-only + [24:24] + GPIO6_LEVEL_LOW + + + read-only + [23:23] + GPIO5_EDGE_HIGH + + + read-only + [22:22] + GPIO5_EDGE_LOW + + + read-only + [21:21] + GPIO5_LEVEL_HIGH + + + read-only + [20:20] + GPIO5_LEVEL_LOW + + + read-only + [19:19] + GPIO4_EDGE_HIGH + + + read-only + [18:18] + GPIO4_EDGE_LOW + + + read-only + [17:17] + GPIO4_LEVEL_HIGH + + + read-only + [16:16] + GPIO4_LEVEL_LOW + + + read-only + [15:15] + GPIO3_EDGE_HIGH + + + read-only + [14:14] + GPIO3_EDGE_LOW + + + read-only + [13:13] + GPIO3_LEVEL_HIGH + + + read-only + [12:12] + GPIO3_LEVEL_LOW + + + read-only + [11:11] + GPIO2_EDGE_HIGH + + + read-only + [10:10] + GPIO2_EDGE_LOW + + + read-only + [9:9] + GPIO2_LEVEL_HIGH + + + read-only + [8:8] + GPIO2_LEVEL_LOW + + + read-only + [7:7] + GPIO1_EDGE_HIGH + + + read-only + [6:6] + GPIO1_EDGE_LOW + + + read-only + [5:5] + GPIO1_LEVEL_HIGH + + + read-only + [4:4] + GPIO1_LEVEL_LOW + + + read-only + [3:3] + GPIO0_EDGE_HIGH + + + read-only + [2:2] + GPIO0_EDGE_LOW + + + read-only + [1:1] + GPIO0_LEVEL_HIGH + + + read-only + [0:0] + GPIO0_LEVEL_LOW + + + PROC1_INTS0 + 0x00000000 + + + 0x0154 + Interrupt status after masking & forcing for proc1 + + + read-only + [31:31] + GPIO15_EDGE_HIGH + + + read-only + [30:30] + GPIO15_EDGE_LOW + + + read-only + [29:29] + GPIO15_LEVEL_HIGH + + + read-only + [28:28] + GPIO15_LEVEL_LOW + + + read-only + [27:27] + GPIO14_EDGE_HIGH + + + read-only + [26:26] + GPIO14_EDGE_LOW + + + read-only + [25:25] + GPIO14_LEVEL_HIGH + + + read-only + [24:24] + GPIO14_LEVEL_LOW + + + read-only + [23:23] + GPIO13_EDGE_HIGH + + + read-only + [22:22] + GPIO13_EDGE_LOW + + + read-only + [21:21] + GPIO13_LEVEL_HIGH + + + read-only + [20:20] + GPIO13_LEVEL_LOW + + + read-only + [19:19] + GPIO12_EDGE_HIGH + + + read-only + [18:18] + GPIO12_EDGE_LOW + + + read-only + [17:17] + GPIO12_LEVEL_HIGH + + + read-only + [16:16] + GPIO12_LEVEL_LOW + + + read-only + [15:15] + GPIO11_EDGE_HIGH + + + read-only + [14:14] + GPIO11_EDGE_LOW + + + read-only + [13:13] + GPIO11_LEVEL_HIGH + + + read-only + [12:12] + GPIO11_LEVEL_LOW + + + read-only + [11:11] + GPIO10_EDGE_HIGH + + + read-only + [10:10] + GPIO10_EDGE_LOW + + + read-only + [9:9] + GPIO10_LEVEL_HIGH + + + read-only + [8:8] + GPIO10_LEVEL_LOW + + + read-only + [7:7] + GPIO9_EDGE_HIGH + + + read-only + [6:6] + GPIO9_EDGE_LOW + + + read-only + [5:5] + GPIO9_LEVEL_HIGH + + + read-only + [4:4] + GPIO9_LEVEL_LOW + + + read-only + [3:3] + GPIO8_EDGE_HIGH + + + read-only + [2:2] + GPIO8_EDGE_LOW + + + read-only + [1:1] + GPIO8_LEVEL_HIGH + + + read-only + [0:0] + GPIO8_LEVEL_LOW + + + PROC1_INTS1 + 0x00000000 + + + 0x0158 + Interrupt status after masking & forcing for proc1 + + + read-only + [31:31] + GPIO23_EDGE_HIGH + + + read-only + [30:30] + GPIO23_EDGE_LOW + + + read-only + [29:29] + GPIO23_LEVEL_HIGH + + + read-only + [28:28] + GPIO23_LEVEL_LOW + + + read-only + [27:27] + GPIO22_EDGE_HIGH + + + read-only + [26:26] + GPIO22_EDGE_LOW + + + read-only + [25:25] + GPIO22_LEVEL_HIGH + + + read-only + [24:24] + GPIO22_LEVEL_LOW + + + read-only + [23:23] + GPIO21_EDGE_HIGH + + + read-only + [22:22] + GPIO21_EDGE_LOW + + + read-only + [21:21] + GPIO21_LEVEL_HIGH + + + read-only + [20:20] + GPIO21_LEVEL_LOW + + + read-only + [19:19] + GPIO20_EDGE_HIGH + + + read-only + [18:18] + GPIO20_EDGE_LOW + + + read-only + [17:17] + GPIO20_LEVEL_HIGH + + + read-only + [16:16] + GPIO20_LEVEL_LOW + + + read-only + [15:15] + GPIO19_EDGE_HIGH + + + read-only + [14:14] + GPIO19_EDGE_LOW + + + read-only + [13:13] + GPIO19_LEVEL_HIGH + + + read-only + [12:12] + GPIO19_LEVEL_LOW + + + read-only + [11:11] + GPIO18_EDGE_HIGH + + + read-only + [10:10] + GPIO18_EDGE_LOW + + + read-only + [9:9] + GPIO18_LEVEL_HIGH + + + read-only + [8:8] + GPIO18_LEVEL_LOW + + + read-only + [7:7] + GPIO17_EDGE_HIGH + + + read-only + [6:6] + GPIO17_EDGE_LOW + + + read-only + [5:5] + GPIO17_LEVEL_HIGH + + + read-only + [4:4] + GPIO17_LEVEL_LOW + + + read-only + [3:3] + GPIO16_EDGE_HIGH + + + read-only + [2:2] + GPIO16_EDGE_LOW + + + read-only + [1:1] + GPIO16_LEVEL_HIGH + + + read-only + [0:0] + GPIO16_LEVEL_LOW + + + PROC1_INTS2 + 0x00000000 + + + 0x015c + Interrupt status after masking & forcing for proc1 + + + read-only + [23:23] + GPIO29_EDGE_HIGH + + + read-only + [22:22] + GPIO29_EDGE_LOW + + + read-only + [21:21] + GPIO29_LEVEL_HIGH + + + read-only + [20:20] + GPIO29_LEVEL_LOW + + + read-only + [19:19] + GPIO28_EDGE_HIGH + + + read-only + [18:18] + GPIO28_EDGE_LOW + + + read-only + [17:17] + GPIO28_LEVEL_HIGH + + + read-only + [16:16] + GPIO28_LEVEL_LOW + + + read-only + [15:15] + GPIO27_EDGE_HIGH + + + read-only + [14:14] + GPIO27_EDGE_LOW + + + read-only + [13:13] + GPIO27_LEVEL_HIGH + + + read-only + [12:12] + GPIO27_LEVEL_LOW + + + read-only + [11:11] + GPIO26_EDGE_HIGH + + + read-only + [10:10] + GPIO26_EDGE_LOW + + + read-only + [9:9] + GPIO26_LEVEL_HIGH + + + read-only + [8:8] + GPIO26_LEVEL_LOW + + + read-only + [7:7] + GPIO25_EDGE_HIGH + + + read-only + [6:6] + GPIO25_EDGE_LOW + + + read-only + [5:5] + GPIO25_LEVEL_HIGH + + + read-only + [4:4] + GPIO25_LEVEL_LOW + + + read-only + [3:3] + GPIO24_EDGE_HIGH + + + read-only + [2:2] + GPIO24_EDGE_LOW + + + read-only + [1:1] + GPIO24_LEVEL_HIGH + + + read-only + [0:0] + GPIO24_LEVEL_LOW + + + PROC1_INTS3 + 0x00000000 + + + 0x0160 + Interrupt Enable for dormant_wake + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + DORMANT_WAKE_INTE0 + 0x00000000 + + + 0x0164 + Interrupt Enable for dormant_wake + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + DORMANT_WAKE_INTE1 + 0x00000000 + + + 0x0168 + Interrupt Enable for dormant_wake + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + DORMANT_WAKE_INTE2 + 0x00000000 + + + 0x016c + Interrupt Enable for dormant_wake + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + DORMANT_WAKE_INTE3 + 0x00000000 + + + 0x0170 + Interrupt Force for dormant_wake + + + read-write + [31:31] + GPIO7_EDGE_HIGH + + + read-write + [30:30] + GPIO7_EDGE_LOW + + + read-write + [29:29] + GPIO7_LEVEL_HIGH + + + read-write + [28:28] + GPIO7_LEVEL_LOW + + + read-write + [27:27] + GPIO6_EDGE_HIGH + + + read-write + [26:26] + GPIO6_EDGE_LOW + + + read-write + [25:25] + GPIO6_LEVEL_HIGH + + + read-write + [24:24] + GPIO6_LEVEL_LOW + + + read-write + [23:23] + GPIO5_EDGE_HIGH + + + read-write + [22:22] + GPIO5_EDGE_LOW + + + read-write + [21:21] + GPIO5_LEVEL_HIGH + + + read-write + [20:20] + GPIO5_LEVEL_LOW + + + read-write + [19:19] + GPIO4_EDGE_HIGH + + + read-write + [18:18] + GPIO4_EDGE_LOW + + + read-write + [17:17] + GPIO4_LEVEL_HIGH + + + read-write + [16:16] + GPIO4_LEVEL_LOW + + + read-write + [15:15] + GPIO3_EDGE_HIGH + + + read-write + [14:14] + GPIO3_EDGE_LOW + + + read-write + [13:13] + GPIO3_LEVEL_HIGH + + + read-write + [12:12] + GPIO3_LEVEL_LOW + + + read-write + [11:11] + GPIO2_EDGE_HIGH + + + read-write + [10:10] + GPIO2_EDGE_LOW + + + read-write + [9:9] + GPIO2_LEVEL_HIGH + + + read-write + [8:8] + GPIO2_LEVEL_LOW + + + read-write + [7:7] + GPIO1_EDGE_HIGH + + + read-write + [6:6] + GPIO1_EDGE_LOW + + + read-write + [5:5] + GPIO1_LEVEL_HIGH + + + read-write + [4:4] + GPIO1_LEVEL_LOW + + + read-write + [3:3] + GPIO0_EDGE_HIGH + + + read-write + [2:2] + GPIO0_EDGE_LOW + + + read-write + [1:1] + GPIO0_LEVEL_HIGH + + + read-write + [0:0] + GPIO0_LEVEL_LOW + + + DORMANT_WAKE_INTF0 + 0x00000000 + + + 0x0174 + Interrupt Force for dormant_wake + + + read-write + [31:31] + GPIO15_EDGE_HIGH + + + read-write + [30:30] + GPIO15_EDGE_LOW + + + read-write + [29:29] + GPIO15_LEVEL_HIGH + + + read-write + [28:28] + GPIO15_LEVEL_LOW + + + read-write + [27:27] + GPIO14_EDGE_HIGH + + + read-write + [26:26] + GPIO14_EDGE_LOW + + + read-write + [25:25] + GPIO14_LEVEL_HIGH + + + read-write + [24:24] + GPIO14_LEVEL_LOW + + + read-write + [23:23] + GPIO13_EDGE_HIGH + + + read-write + [22:22] + GPIO13_EDGE_LOW + + + read-write + [21:21] + GPIO13_LEVEL_HIGH + + + read-write + [20:20] + GPIO13_LEVEL_LOW + + + read-write + [19:19] + GPIO12_EDGE_HIGH + + + read-write + [18:18] + GPIO12_EDGE_LOW + + + read-write + [17:17] + GPIO12_LEVEL_HIGH + + + read-write + [16:16] + GPIO12_LEVEL_LOW + + + read-write + [15:15] + GPIO11_EDGE_HIGH + + + read-write + [14:14] + GPIO11_EDGE_LOW + + + read-write + [13:13] + GPIO11_LEVEL_HIGH + + + read-write + [12:12] + GPIO11_LEVEL_LOW + + + read-write + [11:11] + GPIO10_EDGE_HIGH + + + read-write + [10:10] + GPIO10_EDGE_LOW + + + read-write + [9:9] + GPIO10_LEVEL_HIGH + + + read-write + [8:8] + GPIO10_LEVEL_LOW + + + read-write + [7:7] + GPIO9_EDGE_HIGH + + + read-write + [6:6] + GPIO9_EDGE_LOW + + + read-write + [5:5] + GPIO9_LEVEL_HIGH + + + read-write + [4:4] + GPIO9_LEVEL_LOW + + + read-write + [3:3] + GPIO8_EDGE_HIGH + + + read-write + [2:2] + GPIO8_EDGE_LOW + + + read-write + [1:1] + GPIO8_LEVEL_HIGH + + + read-write + [0:0] + GPIO8_LEVEL_LOW + + + DORMANT_WAKE_INTF1 + 0x00000000 + + + 0x0178 + Interrupt Force for dormant_wake + + + read-write + [31:31] + GPIO23_EDGE_HIGH + + + read-write + [30:30] + GPIO23_EDGE_LOW + + + read-write + [29:29] + GPIO23_LEVEL_HIGH + + + read-write + [28:28] + GPIO23_LEVEL_LOW + + + read-write + [27:27] + GPIO22_EDGE_HIGH + + + read-write + [26:26] + GPIO22_EDGE_LOW + + + read-write + [25:25] + GPIO22_LEVEL_HIGH + + + read-write + [24:24] + GPIO22_LEVEL_LOW + + + read-write + [23:23] + GPIO21_EDGE_HIGH + + + read-write + [22:22] + GPIO21_EDGE_LOW + + + read-write + [21:21] + GPIO21_LEVEL_HIGH + + + read-write + [20:20] + GPIO21_LEVEL_LOW + + + read-write + [19:19] + GPIO20_EDGE_HIGH + + + read-write + [18:18] + GPIO20_EDGE_LOW + + + read-write + [17:17] + GPIO20_LEVEL_HIGH + + + read-write + [16:16] + GPIO20_LEVEL_LOW + + + read-write + [15:15] + GPIO19_EDGE_HIGH + + + read-write + [14:14] + GPIO19_EDGE_LOW + + + read-write + [13:13] + GPIO19_LEVEL_HIGH + + + read-write + [12:12] + GPIO19_LEVEL_LOW + + + read-write + [11:11] + GPIO18_EDGE_HIGH + + + read-write + [10:10] + GPIO18_EDGE_LOW + + + read-write + [9:9] + GPIO18_LEVEL_HIGH + + + read-write + [8:8] + GPIO18_LEVEL_LOW + + + read-write + [7:7] + GPIO17_EDGE_HIGH + + + read-write + [6:6] + GPIO17_EDGE_LOW + + + read-write + [5:5] + GPIO17_LEVEL_HIGH + + + read-write + [4:4] + GPIO17_LEVEL_LOW + + + read-write + [3:3] + GPIO16_EDGE_HIGH + + + read-write + [2:2] + GPIO16_EDGE_LOW + + + read-write + [1:1] + GPIO16_LEVEL_HIGH + + + read-write + [0:0] + GPIO16_LEVEL_LOW + + + DORMANT_WAKE_INTF2 + 0x00000000 + + + 0x017c + Interrupt Force for dormant_wake + + + read-write + [23:23] + GPIO29_EDGE_HIGH + + + read-write + [22:22] + GPIO29_EDGE_LOW + + + read-write + [21:21] + GPIO29_LEVEL_HIGH + + + read-write + [20:20] + GPIO29_LEVEL_LOW + + + read-write + [19:19] + GPIO28_EDGE_HIGH + + + read-write + [18:18] + GPIO28_EDGE_LOW + + + read-write + [17:17] + GPIO28_LEVEL_HIGH + + + read-write + [16:16] + GPIO28_LEVEL_LOW + + + read-write + [15:15] + GPIO27_EDGE_HIGH + + + read-write + [14:14] + GPIO27_EDGE_LOW + + + read-write + [13:13] + GPIO27_LEVEL_HIGH + + + read-write + [12:12] + GPIO27_LEVEL_LOW + + + read-write + [11:11] + GPIO26_EDGE_HIGH + + + read-write + [10:10] + GPIO26_EDGE_LOW + + + read-write + [9:9] + GPIO26_LEVEL_HIGH + + + read-write + [8:8] + GPIO26_LEVEL_LOW + + + read-write + [7:7] + GPIO25_EDGE_HIGH + + + read-write + [6:6] + GPIO25_EDGE_LOW + + + read-write + [5:5] + GPIO25_LEVEL_HIGH + + + read-write + [4:4] + GPIO25_LEVEL_LOW + + + read-write + [3:3] + GPIO24_EDGE_HIGH + + + read-write + [2:2] + GPIO24_EDGE_LOW + + + read-write + [1:1] + GPIO24_LEVEL_HIGH + + + read-write + [0:0] + GPIO24_LEVEL_LOW + + + DORMANT_WAKE_INTF3 + 0x00000000 + + + 0x0180 + Interrupt status after masking & forcing for dormant_wake + + + read-only + [31:31] + GPIO7_EDGE_HIGH + + + read-only + [30:30] + GPIO7_EDGE_LOW + + + read-only + [29:29] + GPIO7_LEVEL_HIGH + + + read-only + [28:28] + GPIO7_LEVEL_LOW + + + read-only + [27:27] + GPIO6_EDGE_HIGH + + + read-only + [26:26] + GPIO6_EDGE_LOW + + + read-only + [25:25] + GPIO6_LEVEL_HIGH + + + read-only + [24:24] + GPIO6_LEVEL_LOW + + + read-only + [23:23] + GPIO5_EDGE_HIGH + + + read-only + [22:22] + GPIO5_EDGE_LOW + + + read-only + [21:21] + GPIO5_LEVEL_HIGH + + + read-only + [20:20] + GPIO5_LEVEL_LOW + + + read-only + [19:19] + GPIO4_EDGE_HIGH + + + read-only + [18:18] + GPIO4_EDGE_LOW + + + read-only + [17:17] + GPIO4_LEVEL_HIGH + + + read-only + [16:16] + GPIO4_LEVEL_LOW + + + read-only + [15:15] + GPIO3_EDGE_HIGH + + + read-only + [14:14] + GPIO3_EDGE_LOW + + + read-only + [13:13] + GPIO3_LEVEL_HIGH + + + read-only + [12:12] + GPIO3_LEVEL_LOW + + + read-only + [11:11] + GPIO2_EDGE_HIGH + + + read-only + [10:10] + GPIO2_EDGE_LOW + + + read-only + [9:9] + GPIO2_LEVEL_HIGH + + + read-only + [8:8] + GPIO2_LEVEL_LOW + + + read-only + [7:7] + GPIO1_EDGE_HIGH + + + read-only + [6:6] + GPIO1_EDGE_LOW + + + read-only + [5:5] + GPIO1_LEVEL_HIGH + + + read-only + [4:4] + GPIO1_LEVEL_LOW + + + read-only + [3:3] + GPIO0_EDGE_HIGH + + + read-only + [2:2] + GPIO0_EDGE_LOW + + + read-only + [1:1] + GPIO0_LEVEL_HIGH + + + read-only + [0:0] + GPIO0_LEVEL_LOW + + + DORMANT_WAKE_INTS0 + 0x00000000 + + + 0x0184 + Interrupt status after masking & forcing for dormant_wake + + + read-only + [31:31] + GPIO15_EDGE_HIGH + + + read-only + [30:30] + GPIO15_EDGE_LOW + + + read-only + [29:29] + GPIO15_LEVEL_HIGH + + + read-only + [28:28] + GPIO15_LEVEL_LOW + + + read-only + [27:27] + GPIO14_EDGE_HIGH + + + read-only + [26:26] + GPIO14_EDGE_LOW + + + read-only + [25:25] + GPIO14_LEVEL_HIGH + + + read-only + [24:24] + GPIO14_LEVEL_LOW + + + read-only + [23:23] + GPIO13_EDGE_HIGH + + + read-only + [22:22] + GPIO13_EDGE_LOW + + + read-only + [21:21] + GPIO13_LEVEL_HIGH + + + read-only + [20:20] + GPIO13_LEVEL_LOW + + + read-only + [19:19] + GPIO12_EDGE_HIGH + + + read-only + [18:18] + GPIO12_EDGE_LOW + + + read-only + [17:17] + GPIO12_LEVEL_HIGH + + + read-only + [16:16] + GPIO12_LEVEL_LOW + + + read-only + [15:15] + GPIO11_EDGE_HIGH + + + read-only + [14:14] + GPIO11_EDGE_LOW + + + read-only + [13:13] + GPIO11_LEVEL_HIGH + + + read-only + [12:12] + GPIO11_LEVEL_LOW + + + read-only + [11:11] + GPIO10_EDGE_HIGH + + + read-only + [10:10] + GPIO10_EDGE_LOW + + + read-only + [9:9] + GPIO10_LEVEL_HIGH + + + read-only + [8:8] + GPIO10_LEVEL_LOW + + + read-only + [7:7] + GPIO9_EDGE_HIGH + + + read-only + [6:6] + GPIO9_EDGE_LOW + + + read-only + [5:5] + GPIO9_LEVEL_HIGH + + + read-only + [4:4] + GPIO9_LEVEL_LOW + + + read-only + [3:3] + GPIO8_EDGE_HIGH + + + read-only + [2:2] + GPIO8_EDGE_LOW + + + read-only + [1:1] + GPIO8_LEVEL_HIGH + + + read-only + [0:0] + GPIO8_LEVEL_LOW + + + DORMANT_WAKE_INTS1 + 0x00000000 + + + 0x0188 + Interrupt status after masking & forcing for dormant_wake + + + read-only + [31:31] + GPIO23_EDGE_HIGH + + + read-only + [30:30] + GPIO23_EDGE_LOW + + + read-only + [29:29] + GPIO23_LEVEL_HIGH + + + read-only + [28:28] + GPIO23_LEVEL_LOW + + + read-only + [27:27] + GPIO22_EDGE_HIGH + + + read-only + [26:26] + GPIO22_EDGE_LOW + + + read-only + [25:25] + GPIO22_LEVEL_HIGH + + + read-only + [24:24] + GPIO22_LEVEL_LOW + + + read-only + [23:23] + GPIO21_EDGE_HIGH + + + read-only + [22:22] + GPIO21_EDGE_LOW + + + read-only + [21:21] + GPIO21_LEVEL_HIGH + + + read-only + [20:20] + GPIO21_LEVEL_LOW + + + read-only + [19:19] + GPIO20_EDGE_HIGH + + + read-only + [18:18] + GPIO20_EDGE_LOW + + + read-only + [17:17] + GPIO20_LEVEL_HIGH + + + read-only + [16:16] + GPIO20_LEVEL_LOW + + + read-only + [15:15] + GPIO19_EDGE_HIGH + + + read-only + [14:14] + GPIO19_EDGE_LOW + + + read-only + [13:13] + GPIO19_LEVEL_HIGH + + + read-only + [12:12] + GPIO19_LEVEL_LOW + + + read-only + [11:11] + GPIO18_EDGE_HIGH + + + read-only + [10:10] + GPIO18_EDGE_LOW + + + read-only + [9:9] + GPIO18_LEVEL_HIGH + + + read-only + [8:8] + GPIO18_LEVEL_LOW + + + read-only + [7:7] + GPIO17_EDGE_HIGH + + + read-only + [6:6] + GPIO17_EDGE_LOW + + + read-only + [5:5] + GPIO17_LEVEL_HIGH + + + read-only + [4:4] + GPIO17_LEVEL_LOW + + + read-only + [3:3] + GPIO16_EDGE_HIGH + + + read-only + [2:2] + GPIO16_EDGE_LOW + + + read-only + [1:1] + GPIO16_LEVEL_HIGH + + + read-only + [0:0] + GPIO16_LEVEL_LOW + + + DORMANT_WAKE_INTS2 + 0x00000000 + + + 0x018c + Interrupt status after masking & forcing for dormant_wake + + + read-only + [23:23] + GPIO29_EDGE_HIGH + + + read-only + [22:22] + GPIO29_EDGE_LOW + + + read-only + [21:21] + GPIO29_LEVEL_HIGH + + + read-only + [20:20] + GPIO29_LEVEL_LOW + + + read-only + [19:19] + GPIO28_EDGE_HIGH + + + read-only + [18:18] + GPIO28_EDGE_LOW + + + read-only + [17:17] + GPIO28_LEVEL_HIGH + + + read-only + [16:16] + GPIO28_LEVEL_LOW + + + read-only + [15:15] + GPIO27_EDGE_HIGH + + + read-only + [14:14] + GPIO27_EDGE_LOW + + + read-only + [13:13] + GPIO27_LEVEL_HIGH + + + read-only + [12:12] + GPIO27_LEVEL_LOW + + + read-only + [11:11] + GPIO26_EDGE_HIGH + + + read-only + [10:10] + GPIO26_EDGE_LOW + + + read-only + [9:9] + GPIO26_LEVEL_HIGH + + + read-only + [8:8] + GPIO26_LEVEL_LOW + + + read-only + [7:7] + GPIO25_EDGE_HIGH + + + read-only + [6:6] + GPIO25_EDGE_LOW + + + read-only + [5:5] + GPIO25_LEVEL_HIGH + + + read-only + [4:4] + GPIO25_LEVEL_LOW + + + read-only + [3:3] + GPIO24_EDGE_HIGH + + + read-only + [2:2] + GPIO24_EDGE_LOW + + + read-only + [1:1] + GPIO24_LEVEL_HIGH + + + read-only + [0:0] + GPIO24_LEVEL_LOW + + + DORMANT_WAKE_INTS3 + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40018000 + + IO_IRQ_QSPI + 14 + + IO_QSPI + + + 0x0000 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SCLK_STATUS + 0x00000000 + + + 0x0004 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_sclk + 0 + + + sio_30 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SCLK_CTRL + 0x0000001f + + + 0x0008 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SS_STATUS + 0x00000000 + + + 0x000c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_ss_n + 0 + + + sio_31 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SS_CTRL + 0x0000001f + + + 0x0010 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SD0_STATUS + 0x00000000 + + + 0x0014 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_sd0 + 0 + + + sio_32 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SD0_CTRL + 0x0000001f + + + 0x0018 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SD1_STATUS + 0x00000000 + + + 0x001c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_sd1 + 0 + + + sio_33 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SD1_CTRL + 0x0000001f + + + 0x0020 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SD2_STATUS + 0x00000000 + + + 0x0024 + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_sd2 + 0 + + + sio_34 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SD2_CTRL + 0x0000001f + + + 0x0028 + GPIO status + + + read-only + [26:26] + interrupt to processors, after override is applied + IRQTOPROC + + + read-only + [24:24] + interrupt from pad before override is applied + IRQFROMPAD + + + read-only + [19:19] + input signal to peripheral, after override is applied + INTOPERI + + + read-only + [17:17] + input signal from pad, before override is applied + INFROMPAD + + + read-only + [13:13] + output enable to pad after register override is applied + OETOPAD + + + read-only + [12:12] + output enable from selected peripheral, before register override is applied + OEFROMPERI + + + read-only + [9:9] + output signal to pad after register override is applied + OUTTOPAD + + + read-only + [8:8] + output signal from selected peripheral, before register override is applied + OUTFROMPERI + + + GPIO_QSPI_SD3_STATUS + 0x00000000 + + + 0x002c + GPIO control including function select and overrides. + + + read-write + [29:28] + + + don't invert the interrupt + NORMAL + 0 + + + invert the interrupt + INVERT + 1 + + + drive interrupt low + LOW + 2 + + + drive interrupt high + HIGH + 3 + + + IRQOVER + + + read-write + [17:16] + + + don't invert the peri input + NORMAL + 0 + + + invert the peri input + INVERT + 1 + + + drive peri input low + LOW + 2 + + + drive peri input high + HIGH + 3 + + + INOVER + + + read-write + [13:12] + + + drive output enable from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output enable from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + disable output + DISABLE + 2 + + + enable output + ENABLE + 3 + + + OEOVER + + + read-write + [9:8] + + + drive output from peripheral signal selected by funcsel + NORMAL + 0 + + + drive output from inverse of peripheral signal selected by funcsel + INVERT + 1 + + + drive output low + LOW + 2 + + + drive output high + HIGH + 3 + + + OUTOVER + + + read-write + [4:0] + 0-31 -> selects pin function according to the gpio table\n + 31 == NULL + + + xip_sd3 + 0 + + + sio_35 + 5 + + + null + 31 + + + FUNCSEL + + + GPIO_QSPI_SD3_CTRL + 0x0000001f + + + 0x0030 + Raw Interrupts + + + read-write + [23:23] + oneToClear + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + oneToClear + GPIO_QSPI_SD3_EDGE_LOW + + + read-only + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-only + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + oneToClear + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + oneToClear + GPIO_QSPI_SD2_EDGE_LOW + + + read-only + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-only + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + oneToClear + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + oneToClear + GPIO_QSPI_SD1_EDGE_LOW + + + read-only + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-only + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + oneToClear + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + oneToClear + GPIO_QSPI_SD0_EDGE_LOW + + + read-only + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-only + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + oneToClear + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + oneToClear + GPIO_QSPI_SS_EDGE_LOW + + + read-only + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-only + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + oneToClear + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + oneToClear + GPIO_QSPI_SCLK_EDGE_LOW + + + read-only + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-only + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + INTR + 0x00000000 + + + 0x0034 + Interrupt Enable for proc0 + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC0_INTE + 0x00000000 + + + 0x0038 + Interrupt Force for proc0 + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC0_INTF + 0x00000000 + + + 0x003c + Interrupt status after masking & forcing for proc0 + + + read-only + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-only + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-only + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-only + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-only + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-only + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-only + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-only + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-only + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-only + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-only + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-only + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-only + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-only + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-only + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-only + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-only + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-only + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-only + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-only + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-only + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-only + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-only + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-only + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC0_INTS + 0x00000000 + + + 0x0040 + Interrupt Enable for proc1 + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC1_INTE + 0x00000000 + + + 0x0044 + Interrupt Force for proc1 + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC1_INTF + 0x00000000 + + + 0x0048 + Interrupt status after masking & forcing for proc1 + + + read-only + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-only + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-only + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-only + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-only + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-only + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-only + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-only + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-only + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-only + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-only + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-only + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-only + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-only + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-only + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-only + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-only + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-only + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-only + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-only + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-only + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-only + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-only + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-only + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + PROC1_INTS + 0x00000000 + + + 0x004c + Interrupt Enable for dormant_wake + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + DORMANT_WAKE_INTE + 0x00000000 + + + 0x0050 + Interrupt Force for dormant_wake + + + read-write + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-write + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-write + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-write + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-write + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-write + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-write + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-write + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-write + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-write + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-write + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-write + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-write + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-write + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-write + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-write + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-write + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-write + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-write + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-write + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-write + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-write + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-write + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-write + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + DORMANT_WAKE_INTF + 0x00000000 + + + 0x0054 + Interrupt status after masking & forcing for dormant_wake + + + read-only + [23:23] + GPIO_QSPI_SD3_EDGE_HIGH + + + read-only + [22:22] + GPIO_QSPI_SD3_EDGE_LOW + + + read-only + [21:21] + GPIO_QSPI_SD3_LEVEL_HIGH + + + read-only + [20:20] + GPIO_QSPI_SD3_LEVEL_LOW + + + read-only + [19:19] + GPIO_QSPI_SD2_EDGE_HIGH + + + read-only + [18:18] + GPIO_QSPI_SD2_EDGE_LOW + + + read-only + [17:17] + GPIO_QSPI_SD2_LEVEL_HIGH + + + read-only + [16:16] + GPIO_QSPI_SD2_LEVEL_LOW + + + read-only + [15:15] + GPIO_QSPI_SD1_EDGE_HIGH + + + read-only + [14:14] + GPIO_QSPI_SD1_EDGE_LOW + + + read-only + [13:13] + GPIO_QSPI_SD1_LEVEL_HIGH + + + read-only + [12:12] + GPIO_QSPI_SD1_LEVEL_LOW + + + read-only + [11:11] + GPIO_QSPI_SD0_EDGE_HIGH + + + read-only + [10:10] + GPIO_QSPI_SD0_EDGE_LOW + + + read-only + [9:9] + GPIO_QSPI_SD0_LEVEL_HIGH + + + read-only + [8:8] + GPIO_QSPI_SD0_LEVEL_LOW + + + read-only + [7:7] + GPIO_QSPI_SS_EDGE_HIGH + + + read-only + [6:6] + GPIO_QSPI_SS_EDGE_LOW + + + read-only + [5:5] + GPIO_QSPI_SS_LEVEL_HIGH + + + read-only + [4:4] + GPIO_QSPI_SS_LEVEL_LOW + + + read-only + [3:3] + GPIO_QSPI_SCLK_EDGE_HIGH + + + read-only + [2:2] + GPIO_QSPI_SCLK_EDGE_LOW + + + read-only + [1:1] + GPIO_QSPI_SCLK_LEVEL_HIGH + + + read-only + [0:0] + GPIO_QSPI_SCLK_LEVEL_LOW + + + DORMANT_WAKE_INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x4001c000 + PADS_BANK0 + + + 0x0000 + Voltage select. Per bank control + + + read-write + [0:0] + + + Set voltage to 3.3V (DVDD >= 2V5) + 3v3 + 0 + + + Set voltage to 1.8V (DVDD <= 1V8) + 1v8 + 1 + + + VOLTAGE_SELECT + + + VOLTAGE_SELECT + 0x00000000 + + + 0x0004 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO0 + 0x00000056 + + + 0x0008 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO1 + 0x00000056 + + + 0x000c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO2 + 0x00000056 + + + 0x0010 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO3 + 0x00000056 + + + 0x0014 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO4 + 0x00000056 + + + 0x0018 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO5 + 0x00000056 + + + 0x001c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO6 + 0x00000056 + + + 0x0020 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO7 + 0x00000056 + + + 0x0024 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO8 + 0x00000056 + + + 0x0028 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO9 + 0x00000056 + + + 0x002c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO10 + 0x00000056 + + + 0x0030 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO11 + 0x00000056 + + + 0x0034 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO12 + 0x00000056 + + + 0x0038 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO13 + 0x00000056 + + + 0x003c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO14 + 0x00000056 + + + 0x0040 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO15 + 0x00000056 + + + 0x0044 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO16 + 0x00000056 + + + 0x0048 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO17 + 0x00000056 + + + 0x004c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO18 + 0x00000056 + + + 0x0050 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO19 + 0x00000056 + + + 0x0054 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO20 + 0x00000056 + + + 0x0058 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO21 + 0x00000056 + + + 0x005c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO22 + 0x00000056 + + + 0x0060 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO23 + 0x00000056 + + + 0x0064 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO24 + 0x00000056 + + + 0x0068 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO25 + 0x00000056 + + + 0x006c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO26 + 0x00000056 + + + 0x0070 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO27 + 0x00000056 + + + 0x0074 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO28 + 0x00000056 + + + 0x0078 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO29 + 0x00000056 + + + 0x007c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + SWCLK + 0x000000da + + + 0x0080 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + SWD + 0x0000005a + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40020000 + PADS_QSPI + + + 0x0000 + Voltage select. Per bank control + + + read-write + [0:0] + + + Set voltage to 3.3V (DVDD >= 2V5) + 3v3 + 0 + + + Set voltage to 1.8V (DVDD <= 1V8) + 1v8 + 1 + + + VOLTAGE_SELECT + + + VOLTAGE_SELECT + 0x00000000 + + + 0x0004 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SCLK + 0x00000056 + + + 0x0008 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SD0 + 0x00000052 + + + 0x000c + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SD1 + 0x00000052 + + + 0x0010 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SD2 + 0x00000052 + + + 0x0014 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SD3 + 0x00000052 + + + 0x0018 + Pad control register + + + read-write + [7:7] + Output disable. Has priority over output enable from peripherals + OD + + + read-write + [6:6] + Input enable + IE + + + read-write + [5:4] + Drive strength. + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + DRIVE + + + read-write + [3:3] + Pull up enable + PUE + + + read-write + [2:2] + Pull down enable + PDE + + + read-write + [1:1] + Enable schmitt trigger + SCHMITT + + + read-write + [0:0] + Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST + + + GPIO_QSPI_SS + 0x0000005a + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40024000 + Controls the crystal oscillator + XOSC + + + 0x0000 + Crystal Oscillator Control + + + read-write + [23:12] + On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + + + DISABLE + 3358 + + + ENABLE + 4011 + + + ENABLE + + + read-write + [11:0] + Frequency range. This resets to 0xAA0 and cannot be changed. + + + 1_15MHZ + 2720 + + + RESERVED_1 + 2721 + + + RESERVED_2 + 2722 + + + RESERVED_3 + 2723 + + + FREQ_RANGE + + + CTRL + 0x00000000 + + + 0x0004 + Crystal Oscillator Status + + + read-only + [31:31] + Oscillator is running and stable + STABLE + + + read-write + [24:24] + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + oneToClear + BADWRITE + + + read-only + [12:12] + Oscillator is enabled but not necessarily running and stable, resets to 0 + ENABLED + + + read-only + [1:0] + The current frequency range setting, always reads 0 + + + 1_15MHZ + 0 + + + RESERVED_1 + 1 + + + RESERVED_2 + 2 + + + RESERVED_3 + 3 + + + FREQ_RANGE + + + STATUS + 0x00000000 + + + read-write + 0x0008 + Crystal Oscillator pause control\n + This is used to save power by pausing the XOSC\n + On power-up this field is initialised to WAKE\n + An invalid write will also select WAKE\n + WARNING: stop the PLLs before selecting dormant mode\n + WARNING: setup the irq before selecting dormant mode + DORMANT + 0x00000000 + + + 0x000c + Controls the startup delay + + + read-write + [20:20] + Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly + X4 + + + read-write + [13:0] + in multiples of 256*xtal_period + DELAY + + + STARTUP + 0x00000000 + + + 0x001c + A down counter running at the xosc frequency which counts to zero and stops.\n + To start the counter write a non-zero value.\n + Can be used for short software pauses when setting up time sensitive hardware. + + + read-write + [7:0] + COUNT + + + COUNT + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40028000 + PLL_SYS + + + 0x0000 + Control and Status\n + GENERAL CONSTRAINTS:\n + Reference clock frequency min=5MHz, max=800MHz\n + Feedback divider min=16, max=320\n + VCO frequency min=400MHz, max=1600MHz + + + read-only + [31:31] + PLL is locked + LOCK + + + read-write + [8:8] + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + BYPASS + + + read-write + [5:0] + Divides the PLL input reference clock.\n + Behaviour is undefined for div=0.\n + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + REFDIV + + + CS + 0x00000001 + + + 0x0004 + Controls the PLL power modes. + + + read-write + [5:5] + PLL VCO powerdown\n + To save power set high when PLL output not required or bypass=1. + VCOPD + + + read-write + [3:3] + PLL post divider powerdown\n + To save power set high when PLL output not required or bypass=1. + POSTDIVPD + + + read-write + [2:2] + PLL DSM powerdown\n + Nothing is achieved by setting this low. + DSMPD + + + read-write + [0:0] + PLL powerdown\n + To save power set high when PLL output not required. + PD + + + PWR + 0x0000002d + + + 0x0008 + Feedback divisor\n + (note: this PLL does not support fractional division) + + + read-write + [11:0] + see ctrl reg description for constraints + FBDIV_INT + + + FBDIV_INT + 0x00000000 + + + 0x000c + Controls the PLL post dividers for the primary output\n + (note: this PLL does not have a secondary output)\n + the primary output is driven from VCO divided by postdiv1*postdiv2 + + + read-write + [18:16] + divide by 1-7 + POSTDIV1 + + + read-write + [14:12] + divide by 1-7 + POSTDIV2 + + + PRIM + 0x00077000 + + + 32 + 1 + + + 0x4002c000 + PLL_USB + + + + 0 + 0x1000 + registers + + 0x40030000 + Register block for busfabric control signals and performance counters + BUSCTRL + + + 0x0000 + Set the priority of each master for bus arbitration. + + + read-write + [12:12] + 0 - low priority, 1 - high priority + DMA_W + + + read-write + [8:8] + 0 - low priority, 1 - high priority + DMA_R + + + read-write + [4:4] + 0 - low priority, 1 - high priority + PROC1 + + + read-write + [0:0] + 0 - low priority, 1 - high priority + PROC0 + + + BUS_PRIORITY + 0x00000000 + + + 0x0004 + Bus priority acknowledge + + + read-only + [0:0] + Goes to 1 once all arbiters have registered the new global priority levels.\n + Arbiters update their local priority when servicing a new nonsequential access.\n + In normal circumstances this will happen almost immediately. + BUS_PRIORITY_ACK + + + BUS_PRIORITY_ACK + 0x00000000 + + + 0x0008 + Bus fabric performance counter 0 + + + read-write + [23:0] + Busfabric saturating performance counter 0\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL0 + oneToClear + PERFCTR0 + + + PERFCTR0 + 0x00000000 + + + 0x000c + Bus fabric performance event select for PERFCTR0 + + + read-write + [4:0] + Select a performance event for PERFCTR0 + PERFSEL0 + + + PERFSEL0 + 0x0000001f + + + 0x0010 + Bus fabric performance counter 1 + + + read-write + [23:0] + Busfabric saturating performance counter 1\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL1 + oneToClear + PERFCTR1 + + + PERFCTR1 + 0x00000000 + + + 0x0014 + Bus fabric performance event select for PERFCTR1 + + + read-write + [4:0] + Select a performance event for PERFCTR1 + PERFSEL1 + + + PERFSEL1 + 0x0000001f + + + 0x0018 + Bus fabric performance counter 2 + + + read-write + [23:0] + Busfabric saturating performance counter 2\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL2 + oneToClear + PERFCTR2 + + + PERFCTR2 + 0x00000000 + + + 0x001c + Bus fabric performance event select for PERFCTR2 + + + read-write + [4:0] + Select a performance event for PERFCTR2 + PERFSEL2 + + + PERFSEL2 + 0x0000001f + + + 0x0020 + Bus fabric performance counter 3 + + + read-write + [23:0] + Busfabric saturating performance counter 3\n + Count some event signal from the busfabric arbiters.\n + Write any value to clear. Select an event to count using PERFSEL3 + oneToClear + PERFCTR3 + + + PERFCTR3 + 0x00000000 + + + 0x0024 + Bus fabric performance event select for PERFCTR3 + + + read-write + [4:0] + Select a performance event for PERFCTR3 + PERFSEL3 + + + PERFSEL3 + 0x0000001f + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40034000 + + UART0_IRQ + 20 + + UART0 + + + 0x0000 + Data Register, UARTDR + + + read-only + [11:11] + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + OE + + + read-only + [10:10] + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + BE + + + read-only + [9:9] + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + PE + + + read-only + [8:8] + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + FE + + + read-write + [7:0] + Receive (read) data character. Transmit (write) data character. + DATA + + + UARTDR + 0x00000000 + + + 0x0004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + + + read-write + [3:3] + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + oneToClear + OE + + + read-write + [2:2] + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + oneToClear + BE + + + read-write + [1:1] + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + oneToClear + PE + + + read-write + [0:0] + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + oneToClear + FE + + + UARTRSR + 0x00000000 + + + 0x0018 + Flag Register, UARTFR + + + read-only + [8:8] + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + RI + + + read-only + [7:7] + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + TXFE + + + read-only + [6:6] + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + RXFF + + + read-only + [5:5] + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + TXFF + + + read-only + [4:4] + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + RXFE + + + read-only + [3:3] + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + BUSY + + + read-only + [2:2] + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + DCD + + + read-only + [1:1] + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + DSR + + + read-only + [0:0] + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + CTS + + + UARTFR + 0x00000090 + + + 0x0020 + IrDA Low-Power Counter Register, UARTILPR + + + read-write + [7:0] + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + ILPDVSR + + + UARTILPR + 0x00000000 + + + 0x0024 + Integer Baud Rate Register, UARTIBRD + + + read-write + [15:0] + The integer baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVINT + + + UARTIBRD + 0x00000000 + + + 0x0028 + Fractional Baud Rate Register, UARTFBRD + + + read-write + [5:0] + The fractional baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVFRAC + + + UARTFBRD + 0x00000000 + + + 0x002c + Line Control Register, UARTLCR_H + + + read-write + [7:7] + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + SPS + + + read-write + [6:5] + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + WLEN + + + read-write + [4:4] + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + FEN + + + read-write + [3:3] + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + STP2 + + + read-write + [2:2] + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + EPS + + + read-write + [1:1] + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + PEN + + + read-write + [0:0] + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + BRK + + + UARTLCR_H + 0x00000000 + + + 0x0030 + Control Register, UARTCR + + + read-write + [15:15] + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + CTSEN + + + read-write + [14:14] + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + RTSEN + + + read-write + [13:13] + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + OUT2 + + + read-write + [12:12] + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + OUT1 + + + read-write + [11:11] + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + RTS + + + read-write + [10:10] + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + DTR + + + read-write + [9:9] + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + RXE + + + read-write + [8:8] + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + TXE + + + read-write + [7:7] + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + LBE + + + read-write + [2:2] + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + SIRLP + + + read-write + [1:1] + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + SIREN + + + read-write + [0:0] + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + UARTEN + + + UARTCR + 0x00000300 + + + 0x0034 + Interrupt FIFO Level Select Register, UARTIFLS + + + read-write + [5:3] + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + RXIFLSEL + + + read-write + [2:0] + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + TXIFLSEL + + + UARTIFLS + 0x00000012 + + + 0x0038 + Interrupt Mask Set/Clear Register, UARTIMSC + + + read-write + [10:10] + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + OEIM + + + read-write + [9:9] + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + BEIM + + + read-write + [8:8] + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + PEIM + + + read-write + [7:7] + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + FEIM + + + read-write + [6:6] + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + RTIM + + + read-write + [5:5] + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + TXIM + + + read-write + [4:4] + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + RXIM + + + read-write + [3:3] + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + DSRMIM + + + read-write + [2:2] + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + DCDMIM + + + read-write + [1:1] + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + CTSMIM + + + read-write + [0:0] + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + RIMIM + + + UARTIMSC + 0x00000000 + + + 0x003c + Raw Interrupt Status Register, UARTRIS + + + read-only + [10:10] + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + OERIS + + + read-only + [9:9] + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + BERIS + + + read-only + [8:8] + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + PERIS + + + read-only + [7:7] + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + FERIS + + + read-only + [6:6] + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + RTRIS + + + read-only + [5:5] + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + TXRIS + + + read-only + [4:4] + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + RXRIS + + + read-only + [3:3] + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + DSRRMIS + + + read-only + [2:2] + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + DCDRMIS + + + read-only + [1:1] + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + CTSRMIS + + + read-only + [0:0] + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + RIRMIS + + + UARTRIS + 0x00000000 + + + 0x0040 + Masked Interrupt Status Register, UARTMIS + + + read-only + [10:10] + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + OEMIS + + + read-only + [9:9] + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + BEMIS + + + read-only + [8:8] + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + PEMIS + + + read-only + [7:7] + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + FEMIS + + + read-only + [6:6] + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + RTMIS + + + read-only + [5:5] + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + TXMIS + + + read-only + [4:4] + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + RXMIS + + + read-only + [3:3] + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + DSRMMIS + + + read-only + [2:2] + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + DCDMMIS + + + read-only + [1:1] + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + CTSMMIS + + + read-only + [0:0] + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + RIMMIS + + + UARTMIS + 0x00000000 + + + 0x0044 + Interrupt Clear Register, UARTICR + + + read-write + [10:10] + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + oneToClear + OEIC + + + read-write + [9:9] + Break error interrupt clear. Clears the UARTBEINTR interrupt. + oneToClear + BEIC + + + read-write + [8:8] + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + oneToClear + PEIC + + + read-write + [7:7] + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + oneToClear + FEIC + + + read-write + [6:6] + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + oneToClear + RTIC + + + read-write + [5:5] + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + oneToClear + TXIC + + + read-write + [4:4] + Receive interrupt clear. Clears the UARTRXINTR interrupt. + oneToClear + RXIC + + + read-write + [3:3] + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + oneToClear + DSRMIC + + + read-write + [2:2] + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + oneToClear + DCDMIC + + + read-write + [1:1] + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + oneToClear + CTSMIC + + + read-write + [0:0] + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + oneToClear + RIMIC + + + UARTICR + 0x00000000 + + + 0x0048 + DMA Control Register, UARTDMACR + + + read-write + [2:2] + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + DMAONERR + + + read-write + [1:1] + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + TXDMAE + + + read-write + [0:0] + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + RXDMAE + + + UARTDMACR + 0x00000000 + + + 0x0fe0 + UARTPeriphID0 Register + + + read-only + [7:0] + These bits read back as 0x11 + PARTNUMBER0 + + + UARTPERIPHID0 + 0x00000011 + + + 0x0fe4 + UARTPeriphID1 Register + + + read-only + [7:4] + These bits read back as 0x1 + DESIGNER0 + + + read-only + [3:0] + These bits read back as 0x0 + PARTNUMBER1 + + + UARTPERIPHID1 + 0x00000010 + + + 0x0fe8 + UARTPeriphID2 Register + + + read-only + [7:4] + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + REVISION + + + read-only + [3:0] + These bits read back as 0x4 + DESIGNER1 + + + UARTPERIPHID2 + 0x00000034 + + + 0x0fec + UARTPeriphID3 Register + + + read-only + [7:0] + These bits read back as 0x00 + CONFIGURATION + + + UARTPERIPHID3 + 0x00000000 + + + 0x0ff0 + UARTPCellID0 Register + + + read-only + [7:0] + These bits read back as 0x0D + UARTPCELLID0 + + + UARTPCELLID0 + 0x0000000d + + + 0x0ff4 + UARTPCellID1 Register + + + read-only + [7:0] + These bits read back as 0xF0 + UARTPCELLID1 + + + UARTPCELLID1 + 0x000000f0 + + + 0x0ff8 + UARTPCellID2 Register + + + read-only + [7:0] + These bits read back as 0x05 + UARTPCELLID2 + + + UARTPCELLID2 + 0x00000005 + + + 0x0ffc + UARTPCellID3 Register + + + read-only + [7:0] + These bits read back as 0xB1 + UARTPCELLID3 + + + UARTPCELLID3 + 0x000000b1 + + + 32 + 1 + + + 0x40038000 + + UART1_IRQ + 21 + + UART1 + + + + 0 + 0x1000 + registers + + 0x4003c000 + + SPI0_IRQ + 18 + + SPI0 + + + 0x0000 + Control register 0, SSPCR0 on page 3-4 + + + read-write + [15:8] + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + SCR + + + read-write + [7:7] + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + SPH + + + read-write + [6:6] + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + SPO + + + read-write + [5:4] + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + FRF + + + read-write + [3:0] + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + DSS + + + SSPCR0 + 0x00000000 + + + 0x0004 + Control register 1, SSPCR1 on page 3-5 + + + read-write + [3:3] + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + SOD + + + read-write + [2:2] + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + MS + + + read-write + [1:1] + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + SSE + + + read-write + [0:0] + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + LBM + + + SSPCR1 + 0x00000000 + + + 0x0008 + Data register, SSPDR on page 3-6 + + + read-write + [15:0] + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + DATA + + + SSPDR + 0x00000000 + + + 0x000c + Status register, SSPSR on page 3-7 + + + read-only + [4:4] + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + BSY + + + read-only + [3:3] + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + RFF + + + read-only + [2:2] + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + RNE + + + read-only + [1:1] + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + TNF + + + read-only + [0:0] + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + TFE + + + SSPSR + 0x00000003 + + + 0x0010 + Clock prescale register, SSPCPSR on page 3-8 + + + read-write + [7:0] + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + CPSDVSR + + + SSPCPSR + 0x00000000 + + + 0x0014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + + + read-write + [3:3] + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + TXIM + + + read-write + [2:2] + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + RXIM + + + read-write + [1:1] + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + RTIM + + + read-write + [0:0] + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + RORIM + + + SSPIMSC + 0x00000000 + + + 0x0018 + Raw interrupt status register, SSPRIS on page 3-10 + + + read-only + [3:3] + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + TXRIS + + + read-only + [2:2] + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + RXRIS + + + read-only + [1:1] + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + RTRIS + + + read-only + [0:0] + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + RORRIS + + + SSPRIS + 0x00000008 + + + 0x001c + Masked interrupt status register, SSPMIS on page 3-11 + + + read-only + [3:3] + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + TXMIS + + + read-only + [2:2] + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + RXMIS + + + read-only + [1:1] + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + RTMIS + + + read-only + [0:0] + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + RORMIS + + + SSPMIS + 0x00000000 + + + 0x0020 + Interrupt clear register, SSPICR on page 3-11 + + + read-write + [1:1] + Clears the SSPRTINTR interrupt + oneToClear + RTIC + + + read-write + [0:0] + Clears the SSPRORINTR interrupt + oneToClear + RORIC + + + SSPICR + 0x00000000 + + + 0x0024 + DMA control register, SSPDMACR on page 3-12 + + + read-write + [1:1] + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + TXDMAE + + + read-write + [0:0] + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + RXDMAE + + + SSPDMACR + 0x00000000 + + + 0x0fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + + + read-only + [7:0] + These bits read back as 0x22 + PARTNUMBER0 + + + SSPPERIPHID0 + 0x00000022 + + + 0x0fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + + + read-only + [7:4] + These bits read back as 0x1 + DESIGNER0 + + + read-only + [3:0] + These bits read back as 0x0 + PARTNUMBER1 + + + SSPPERIPHID1 + 0x00000010 + + + 0x0fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + + + read-only + [7:4] + These bits return the peripheral revision + REVISION + + + read-only + [3:0] + These bits read back as 0x4 + DESIGNER1 + + + SSPPERIPHID2 + 0x00000034 + + + 0x0fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + + + read-only + [7:0] + These bits read back as 0x00 + CONFIGURATION + + + SSPPERIPHID3 + 0x00000000 + + + 0x0ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + + + read-only + [7:0] + These bits read back as 0x0D + SSPPCELLID0 + + + SSPPCELLID0 + 0x0000000d + + + 0x0ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + + + read-only + [7:0] + These bits read back as 0xF0 + SSPPCELLID1 + + + SSPPCELLID1 + 0x000000f0 + + + 0x0ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + + + read-only + [7:0] + These bits read back as 0x05 + SSPPCELLID2 + + + SSPPCELLID2 + 0x00000005 + + + 0x0ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + + + read-only + [7:0] + These bits read back as 0xB1 + SSPPCELLID3 + + + SSPPCELLID3 + 0x000000b1 + + + 32 + 1 + + + 0x40040000 + + SPI1_IRQ + 19 + + SPI1 + + + + 0 + 0x0100 + registers + + 0x40044000 + DW_apb_i2c address block + + I2C0_IRQ + 23 + + I2C0 + + + 0x0000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + + + read-only + [10:10] + Master issues the STOP_DET interrupt irrespective of whether master is active or not + STOP_DET_IF_MASTER_ACTIVE + + + read-write + [9:9] + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n + Reset value: 0x0. + + + Overflow when RX_FIFO is full + DISABLED + 0 + + + Hold bus when RX_FIFO is full + ENABLED + 1 + + + RX_FIFO_FULL_HLD_CTRL + + + read-write + [8:8] + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0. + + + Default behaviour of TX_EMPTY interrupt + DISABLED + 0 + + + Controlled generation of TX_EMPTY interrupt + ENABLED + 1 + + + TX_EMPTY_CTRL + + + read-write + [7:7] + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + + + slave issues STOP_DET intr always + DISABLED + 0 + + + slave issues STOP_DET intr only if addressed + ENABLED + 1 + + + STOP_DET_IFADDRESSED + + + read-write + [6:6] + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + + + Slave mode is enabled + SLAVE_ENABLED + 0 + + + Slave mode is disabled + SLAVE_DISABLED + 1 + + + IC_SLAVE_DISABLE + + + read-write + [5:5] + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n + Reset value: ENABLED + + + Master restart disabled + DISABLED + 0 + + + Master restart enabled + ENABLED + 1 + + + IC_RESTART_EN + + + read-write + [4:4] + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + + + Master 7Bit addressing mode + ADDR_7BITS + 0 + + + Master 10Bit addressing mode + ADDR_10BITS + 1 + + + IC_10BITADDR_MASTER + + + read-write + [3:3] + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + + + Slave 7Bit addressing + ADDR_7BITS + 0 + + + Slave 10Bit addressing + ADDR_10BITS + 1 + + + IC_10BITADDR_SLAVE + + + read-write + [2:1] + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n + 1: standard mode (100 kbit/s)\n\n + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n + 3: high speed mode (3.4 Mbit/s)\n\n + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + + + Standard Speed mode of operation + STANDARD + 1 + + + Fast or Fast Plus mode of operation + FAST + 2 + + + High Speed mode of operation + HIGH + 3 + + + SPEED + + + read-write + [0:0] + This bit controls whether the DW_apb_i2c master is enabled.\n\n + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + + + Master mode is disabled + DISABLED + 0 + + + Master mode is enabled + ENABLED + 1 + + + MASTER_MODE + + + IC_CON + 0x00000065 + + + 0x0004 + I2C Target Address Register\n\n + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + + + read-write + [11:11] + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + + + Disables programming of GENERAL_CALL or START_BYTE transmission + DISABLED + 0 + + + Enables programming of GENERAL_CALL or START_BYTE transmission + ENABLED + 1 + + + SPECIAL + + + read-write + [10:10] + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + + + GENERAL_CALL byte transmission + GENERAL_CALL + 0 + + + START byte transmission + START_BYTE + 1 + + + GC_OR_START + + + read-write + [9:0] + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + IC_TAR + + + IC_TAR + 0x00000055 + + + 0x0008 + I2C Slave Address Register + + + read-write + [9:0] + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + IC_SAR + + + IC_SAR + 0x00000055 + + + 0x0010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n + The size of the register changes as follows:\n\n + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + + + read-only + [11:11] + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n + Reset value : 0x0\n\n + NOTE: In case of APB_DATA_WIDTH=8,\n\n + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + + + Sequential data byte received + INACTIVE + 0 + + + Non sequential data byte received + ACTIVE + 1 + + + FIRST_DATA_BYTE + + + read-write + [10:10] + This bit controls whether a RESTART is issued before the byte is sent or received.\n\n + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n + Reset value: 0x0 + + + Don't Issue RESTART before this command + DISABLE + 0 + + + Issue RESTART before this command + ENABLE + 1 + + + clear + RESTART + + + read-write + [9:9] + This bit controls whether a STOP is issued after the byte is sent or received.\n\n + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + + + Don't Issue STOP after this command + DISABLE + 0 + + + Issue STOP after this command + ENABLE + 1 + + + clear + STOP + + + read-write + [8:8] + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n + Reset value: 0x0 + + + Master Write Command + WRITE + 0 + + + Master Read Command + READ + 1 + + + clear + CMD + + + read-write + [7:0] + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n + Reset value: 0x0 + DAT + + + IC_DATA_CMD + 0x00000000 + + + 0x0014 + Standard Speed I2C Clock SCL High Count Register + + + read-write + [15:0] + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + IC_SS_SCL_HCNT + + + IC_SS_SCL_HCNT + 0x00000028 + + + 0x0018 + Standard Speed I2C Clock SCL Low Count Register + + + read-write + [15:0] + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + IC_SS_SCL_LCNT + + + IC_SS_SCL_LCNT + 0x0000002f + + + 0x001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + + + read-write + [15:0] + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + IC_FS_SCL_HCNT + + + IC_FS_SCL_HCNT + 0x00000006 + + + 0x0020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + + + read-write + [15:0] + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + IC_FS_SCL_LCNT + + + IC_FS_SCL_LCNT + 0x0000000d + + + 0x002c + I2C Interrupt Status Register\n\n + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + + + read-only + [13:13] + See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n + Reset value: 0x0 + + + R_MASTER_ON_HOLD interrupt is inactive + INACTIVE + 0 + + + R_MASTER_ON_HOLD interrupt is active + ACTIVE + 1 + + + R_MASTER_ON_HOLD + + + read-only + [12:12] + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n + Reset value: 0x0 + + + R_RESTART_DET interrupt is inactive + INACTIVE + 0 + + + R_RESTART_DET interrupt is active + ACTIVE + 1 + + + R_RESTART_DET + + + read-only + [11:11] + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n + Reset value: 0x0 + + + R_GEN_CALL interrupt is inactive + INACTIVE + 0 + + + R_GEN_CALL interrupt is active + ACTIVE + 1 + + + R_GEN_CALL + + + read-only + [10:10] + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n + Reset value: 0x0 + + + R_START_DET interrupt is inactive + INACTIVE + 0 + + + R_START_DET interrupt is active + ACTIVE + 1 + + + R_START_DET + + + read-only + [9:9] + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n + Reset value: 0x0 + + + R_STOP_DET interrupt is inactive + INACTIVE + 0 + + + R_STOP_DET interrupt is active + ACTIVE + 1 + + + R_STOP_DET + + + read-only + [8:8] + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n + Reset value: 0x0 + + + R_ACTIVITY interrupt is inactive + INACTIVE + 0 + + + R_ACTIVITY interrupt is active + ACTIVE + 1 + + + R_ACTIVITY + + + read-only + [7:7] + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n + Reset value: 0x0 + + + R_RX_DONE interrupt is inactive + INACTIVE + 0 + + + R_RX_DONE interrupt is active + ACTIVE + 1 + + + R_RX_DONE + + + read-only + [6:6] + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n + Reset value: 0x0 + + + R_TX_ABRT interrupt is inactive + INACTIVE + 0 + + + R_TX_ABRT interrupt is active + ACTIVE + 1 + + + R_TX_ABRT + + + read-only + [5:5] + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n + Reset value: 0x0 + + + R_RD_REQ interrupt is inactive + INACTIVE + 0 + + + R_RD_REQ interrupt is active + ACTIVE + 1 + + + R_RD_REQ + + + read-only + [4:4] + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n + Reset value: 0x0 + + + R_TX_EMPTY interrupt is inactive + INACTIVE + 0 + + + R_TX_EMPTY interrupt is active + ACTIVE + 1 + + + R_TX_EMPTY + + + read-only + [3:3] + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n + Reset value: 0x0 + + + R_TX_OVER interrupt is inactive + INACTIVE + 0 + + + R_TX_OVER interrupt is active + ACTIVE + 1 + + + R_TX_OVER + + + read-only + [2:2] + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n + Reset value: 0x0 + + + R_RX_FULL interrupt is inactive + INACTIVE + 0 + + + R_RX_FULL interrupt is active + ACTIVE + 1 + + + R_RX_FULL + + + read-only + [1:1] + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n + Reset value: 0x0 + + + R_RX_OVER interrupt is inactive + INACTIVE + 0 + + + R_RX_OVER interrupt is active + ACTIVE + 1 + + + R_RX_OVER + + + read-only + [0:0] + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n + Reset value: 0x0 + + + RX_UNDER interrupt is inactive + INACTIVE + 0 + + + RX_UNDER interrupt is active + ACTIVE + 1 + + + R_RX_UNDER + + + IC_INTR_STAT + 0x00000000 + + + 0x0030 + I2C Interrupt Mask Register.\n\n + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + + + read-only + [13:13] + This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + + + MASTER_ON_HOLD interrupt is masked + ENABLED + 0 + + + MASTER_ON_HOLD interrupt is unmasked + DISABLED + 1 + + + M_MASTER_ON_HOLD_READ_ONLY + + + read-write + [12:12] + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + + + RESTART_DET interrupt is masked + ENABLED + 0 + + + RESTART_DET interrupt is unmasked + DISABLED + 1 + + + M_RESTART_DET + + + read-write + [11:11] + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + GEN_CALL interrupt is masked + ENABLED + 0 + + + GEN_CALL interrupt is unmasked + DISABLED + 1 + + + M_GEN_CALL + + + read-write + [10:10] + This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + + + START_DET interrupt is masked + ENABLED + 0 + + + START_DET interrupt is unmasked + DISABLED + 1 + + + M_START_DET + + + read-write + [9:9] + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + + + STOP_DET interrupt is masked + ENABLED + 0 + + + STOP_DET interrupt is unmasked + DISABLED + 1 + + + M_STOP_DET + + + read-write + [8:8] + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x0 + + + ACTIVITY interrupt is masked + ENABLED + 0 + + + ACTIVITY interrupt is unmasked + DISABLED + 1 + + + M_ACTIVITY + + + read-write + [7:7] + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + RX_DONE interrupt is masked + ENABLED + 0 + + + RX_DONE interrupt is unmasked + DISABLED + 1 + + + M_RX_DONE + + + read-write + [6:6] + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + TX_ABORT interrupt is masked + ENABLED + 0 + + + TX_ABORT interrupt is unmasked + DISABLED + 1 + + + M_TX_ABRT + + + read-write + [5:5] + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + RD_REQ interrupt is masked + ENABLED + 0 + + + RD_REQ interrupt is unmasked + DISABLED + 1 + + + M_RD_REQ + + + read-write + [4:4] + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + TX_EMPTY interrupt is masked + ENABLED + 0 + + + TX_EMPTY interrupt is unmasked + DISABLED + 1 + + + M_TX_EMPTY + + + read-write + [3:3] + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + TX_OVER interrupt is masked + ENABLED + 0 + + + TX_OVER interrupt is unmasked + DISABLED + 1 + + + M_TX_OVER + + + read-write + [2:2] + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + RX_FULL interrupt is masked + ENABLED + 0 + + + RX_FULL interrupt is unmasked + DISABLED + 1 + + + M_RX_FULL + + + read-write + [1:1] + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + RX_OVER interrupt is masked + ENABLED + 0 + + + RX_OVER interrupt is unmasked + DISABLED + 1 + + + M_RX_OVER + + + read-write + [0:0] + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n + Reset value: 0x1 + + + RX_UNDER interrupt is masked + ENABLED + 0 + + + RX_UNDER interrupt is unmasked + DISABLED + 1 + + + M_RX_UNDER + + + IC_INTR_MASK + 0x000008ff + + + 0x0034 + I2C Raw Interrupt Status Register\n\n + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + + + read-only + [13:13] + Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n + Reset value: 0x0 + + + MASTER_ON_HOLD interrupt is inactive + INACTIVE + 0 + + + MASTER_ON_HOLD interrupt is active + ACTIVE + 1 + + + MASTER_ON_HOLD + + + read-only + [12:12] + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n + Reset value: 0x0 + + + RESTART_DET interrupt is inactive + INACTIVE + 0 + + + RESTART_DET interrupt is active + ACTIVE + 1 + + + RESTART_DET + + + read-only + [11:11] + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n + Reset value: 0x0 + + + GEN_CALL interrupt is inactive + INACTIVE + 0 + + + GEN_CALL interrupt is active + ACTIVE + 1 + + + GEN_CALL + + + read-only + [10:10] + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + Reset value: 0x0 + + + START_DET interrupt is inactive + INACTIVE + 0 + + + START_DET interrupt is active + ACTIVE + 1 + + + START_DET + + + read-only + [9:9] + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + + + STOP_DET interrupt is inactive + INACTIVE + 0 + + + STOP_DET interrupt is active + ACTIVE + 1 + + + STOP_DET + + + read-only + [8:8] + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n + Reset value: 0x0 + + + RAW_INTR_ACTIVITY interrupt is inactive + INACTIVE + 0 + + + RAW_INTR_ACTIVITY interrupt is active + ACTIVE + 1 + + + ACTIVITY + + + read-only + [7:7] + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n + Reset value: 0x0 + + + RX_DONE interrupt is inactive + INACTIVE + 0 + + + RX_DONE interrupt is active + ACTIVE + 1 + + + RX_DONE + + + read-only + [6:6] + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n + Reset value: 0x0 + + + TX_ABRT interrupt is inactive + INACTIVE + 0 + + + TX_ABRT interrupt is active + ACTIVE + 1 + + + TX_ABRT + + + read-only + [5:5] + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n + Reset value: 0x0 + + + RD_REQ interrupt is inactive + INACTIVE + 0 + + + RD_REQ interrupt is active + ACTIVE + 1 + + + RD_REQ + + + read-only + [4:4] + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n + Reset value: 0x0. + + + TX_EMPTY interrupt is inactive + INACTIVE + 0 + + + TX_EMPTY interrupt is active + ACTIVE + 1 + + + TX_EMPTY + + + read-only + [3:3] + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Reset value: 0x0 + + + TX_OVER interrupt is inactive + INACTIVE + 0 + + + TX_OVER interrupt is active + ACTIVE + 1 + + + TX_OVER + + + read-only + [2:2] + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n + Reset value: 0x0 + + + RX_FULL interrupt is inactive + INACTIVE + 0 + + + RX_FULL interrupt is active + ACTIVE + 1 + + + RX_FULL + + + read-only + [1:1] + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n + Reset value: 0x0 + + + RX_OVER interrupt is inactive + INACTIVE + 0 + + + RX_OVER interrupt is active + ACTIVE + 1 + + + RX_OVER + + + read-only + [0:0] + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + Reset value: 0x0 + + + RX_UNDER interrupt is inactive + INACTIVE + 0 + + + RX_UNDER interrupt is active + ACTIVE + 1 + + + RX_UNDER + + + IC_RAW_INTR_STAT + 0x00000000 + + + 0x0038 + I2C Receive FIFO Threshold Register + + + read-write + [7:0] + Receive FIFO Threshold Level.\n\n + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + RX_TL + + + IC_RX_TL + 0x00000000 + + + 0x003c + I2C Transmit FIFO Threshold Register + + + read-write + [7:0] + Transmit FIFO Threshold Level.\n\n + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + TX_TL + + + IC_TX_TL + 0x00000000 + + + 0x0040 + Clear Combined and Individual Interrupt Register + + + read-only + [0:0] + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + Reset value: 0x0 + CLR_INTR + + + IC_CLR_INTR + 0x00000000 + + + 0x0044 + Clear RX_UNDER Interrupt Register + + + read-only + [0:0] + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_RX_UNDER + + + IC_CLR_RX_UNDER + 0x00000000 + + + 0x0048 + Clear RX_OVER Interrupt Register + + + read-only + [0:0] + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_RX_OVER + + + IC_CLR_RX_OVER + 0x00000000 + + + 0x004c + Clear TX_OVER Interrupt Register + + + read-only + [0:0] + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_TX_OVER + + + IC_CLR_TX_OVER + 0x00000000 + + + 0x0050 + Clear RD_REQ Interrupt Register + + + read-only + [0:0] + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_RD_REQ + + + IC_CLR_RD_REQ + 0x00000000 + + + 0x0054 + Clear TX_ABRT Interrupt Register + + + read-only + [0:0] + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + Reset value: 0x0 + CLR_TX_ABRT + + + IC_CLR_TX_ABRT + 0x00000000 + + + 0x0058 + Clear RX_DONE Interrupt Register + + + read-only + [0:0] + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_RX_DONE + + + IC_CLR_RX_DONE + 0x00000000 + + + 0x005c + Clear ACTIVITY Interrupt Register + + + read-only + [0:0] + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_ACTIVITY + + + IC_CLR_ACTIVITY + 0x00000000 + + + 0x0060 + Clear STOP_DET Interrupt Register + + + read-only + [0:0] + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_STOP_DET + + + IC_CLR_STOP_DET + 0x00000000 + + + 0x0064 + Clear START_DET Interrupt Register + + + read-only + [0:0] + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_START_DET + + + IC_CLR_START_DET + 0x00000000 + + + 0x0068 + Clear GEN_CALL Interrupt Register + + + read-only + [0:0] + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_GEN_CALL + + + IC_CLR_GEN_CALL + 0x00000000 + + + 0x006c + I2C Enable Register + + + read-write + [2:2] + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + + + Tx Command execution not blocked + NOT_BLOCKED + 0 + + + Tx Command execution blocked + BLOCKED + 1 + + + TX_CMD_BLOCK + + + read-write + [1:1] + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n + Reset value: 0x0 + + + ABORT operation not in progress + DISABLE + 0 + + + ABORT operation in progress + ENABLED + 1 + + + ABORT + + + read-write + [0:0] + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n + Reset value: 0x0 + + + I2C is disabled + DISABLED + 0 + + + I2C is enabled + ENABLED + 1 + + + ENABLE + + + IC_ENABLE + 0x00000000 + + + 0x0070 + I2C Status Register\n\n + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + + + read-only + [6:6] + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + + + Slave is idle + IDLE + 0 + + + Slave not idle + ACTIVE + 1 + + + SLV_ACTIVITY + + + read-only + [5:5] + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n + Reset value: 0x0 + + + Master is idle + IDLE + 0 + + + Master not idle + ACTIVE + 1 + + + MST_ACTIVITY + + + read-only + [4:4] + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + + + Rx FIFO not full + NOT_FULL + 0 + + + Rx FIFO is full + FULL + 1 + + + RFF + + + read-only + [3:3] + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + + + Rx FIFO is empty + EMPTY + 0 + + + Rx FIFO not empty + NOT_EMPTY + 1 + + + RFNE + + + read-only + [2:2] + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + + + Tx FIFO not empty + NON_EMPTY + 0 + + + Tx FIFO is empty + EMPTY + 1 + + + TFE + + + read-only + [1:1] + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + + + Tx FIFO is full + FULL + 0 + + + Tx FIFO not full + NOT_FULL + 1 + + + TFNF + + + read-only + [0:0] + I2C Activity Status. Reset value: 0x0 + + + I2C is idle + INACTIVE + 0 + + + I2C is active + ACTIVE + 1 + + + ACTIVITY + + + IC_STATUS + 0x00000006 + + + 0x0074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + + + read-only + [4:0] + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n + Reset value: 0x0 + TXFLR + + + IC_TXFLR + 0x00000000 + + + 0x0078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + + + read-only + [4:0] + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n + Reset value: 0x0 + RXFLR + + + IC_RXFLR + 0x00000000 + + + 0x007c + I2C SDA Hold Time Length Register\n\n + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n + Writes to this register succeed only when IC_ENABLE[0]=0.\n\n + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + + + read-write + [23:16] + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + IC_SDA_RX_HOLD + + + read-write + [15:0] + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + IC_SDA_TX_HOLD + + + IC_SDA_HOLD + 0x00000001 + + + 0x0080 + I2C Transmit Abort Source Register\n\n + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + + + read-only + [31:23] + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + TX_FLUSH_CNT + + + read-only + [16:16] + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + + + Transfer abort detected by master- scenario not present + ABRT_USER_ABRT_VOID + 0 + + + Transfer abort detected by master + ABRT_USER_ABRT_GENERATED + 1 + + + ABRT_USER_ABRT + + + read-only + [15:15] + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + + + Slave trying to transmit to remote master in read mode- scenario not present + ABRT_SLVRD_INTX_VOID + 0 + + + Slave trying to transmit to remote master in read mode + ABRT_SLVRD_INTX_GENERATED + 1 + + + ABRT_SLVRD_INTX + + + read-only + [14:14] + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + + + Slave lost arbitration to remote master- scenario not present + ABRT_SLV_ARBLOST_VOID + 0 + + + Slave lost arbitration to remote master + ABRT_SLV_ARBLOST_GENERATED + 1 + + + ABRT_SLV_ARBLOST + + + read-only + [13:13] + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Slave-Transmitter + + + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + + + Slave flushes existing data in TX-FIFO upon getting read command + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + + + ABRT_SLVFLUSH_TXFIFO + + + read-only + [12:12] + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + + + Master or Slave-Transmitter lost arbitration- scenario not present + ABRT_LOST_VOID + 0 + + + Master or Slave-Transmitter lost arbitration + ABRT_LOST_GENERATED + 1 + + + ARB_LOST + + + read-only + [11:11] + This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + + + User initiating master operation when MASTER disabled- scenario not present + ABRT_MASTER_DIS_VOID + 0 + + + User initiating master operation when MASTER disabled + ABRT_MASTER_DIS_GENERATED + 1 + + + ABRT_MASTER_DIS + + + read-only + [10:10] + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Receiver + + + Master not trying to read in 10Bit addressing mode when RESTART disabled + ABRT_10B_RD_VOID + 0 + + + Master trying to read in 10Bit addressing mode when RESTART disabled + ABRT_10B_RD_GENERATED + 1 + + + ABRT_10B_RD_NORSTRT + + + read-only + [9:9] + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + + + User trying to send START byte when RESTART disabled- scenario not present + ABRT_SBYTE_NORSTRT_VOID + 0 + + + User trying to send START byte when RESTART disabled + ABRT_SBYTE_NORSTRT_GENERATED + 1 + + + ABRT_SBYTE_NORSTRT + + + read-only + [8:8] + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + + + User trying to switch Master to HS mode when RESTART disabled- scenario not present + ABRT_HS_NORSTRT_VOID + 0 + + + User trying to switch Master to HS mode when RESTART disabled + ABRT_HS_NORSTRT_GENERATED + 1 + + + ABRT_HS_NORSTRT + + + read-only + [7:7] + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + + + ACK detected for START byte- scenario not present + ABRT_SBYTE_ACKDET_VOID + 0 + + + ACK detected for START byte + ABRT_SBYTE_ACKDET_GENERATED + 1 + + + ABRT_SBYTE_ACKDET + + + read-only + [6:6] + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master + + + HS Master code ACKed in HS Mode- scenario not present + ABRT_HS_ACK_VOID + 0 + + + HS Master code ACKed in HS Mode + ABRT_HS_ACK_GENERATED + 1 + + + ABRT_HS_ACKDET + + + read-only + [5:5] + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + + + GCALL is followed by read from bus-scenario not present + ABRT_GCALL_READ_VOID + 0 + + + GCALL is followed by read from bus + ABRT_GCALL_READ_GENERATED + 1 + + + ABRT_GCALL_READ + + + read-only + [4:4] + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + + + GCALL not ACKed by any slave-scenario not present + ABRT_GCALL_NOACK_VOID + 0 + + + GCALL not ACKed by any slave + ABRT_GCALL_NOACK_GENERATED + 1 + + + ABRT_GCALL_NOACK + + + read-only + [3:3] + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter + + + Transmitted data non-ACKed by addressed slave-scenario not present + ABRT_TXDATA_NOACK_VOID + 0 + + + Transmitted data not ACKed by addressed slave + ABRT_TXDATA_NOACK_GENERATED + 1 + + + ABRT_TXDATA_NOACK + + + read-only + [2:2] + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + + + This abort is not generated + INACTIVE + 0 + + + Byte 2 of 10Bit Address not ACKed by any slave + ACTIVE + 1 + + + ABRT_10ADDR2_NOACK + + + read-only + [1:1] + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + + + This abort is not generated + INACTIVE + 0 + + + Byte 1 of 10Bit Address not ACKed by any slave + ACTIVE + 1 + + + ABRT_10ADDR1_NOACK + + + read-only + [0:0] + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n + Reset value: 0x0\n\n + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + + + This abort is not generated + INACTIVE + 0 + + + This abort is generated because of NOACK for 7-bit address + ACTIVE + 1 + + + ABRT_7B_ADDR_NOACK + + + IC_TX_ABRT_SOURCE + 0x00000000 + + + 0x0084 + Generate Slave Data NACK Register\n\n + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + + + read-write + [0:0] + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + + + Slave receiver generates NACK normally + DISABLED + 0 + + + Slave receiver generates NACK upon data reception only + ENABLED + 1 + + + NACK + + + IC_SLV_DATA_NACK_ONLY + 0x00000000 + + + 0x0088 + DMA Control Register\n\n + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + + + read-write + [1:1] + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + + + transmit FIFO DMA channel disabled + DISABLED + 0 + + + Transmit FIFO DMA channel enabled + ENABLED + 1 + + + TDMAE + + + read-write + [0:0] + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + + + Receive FIFO DMA channel disabled + DISABLED + 0 + + + Receive FIFO DMA channel enabled + ENABLED + 1 + + + RDMAE + + + IC_DMA_CR + 0x00000000 + + + 0x008c + DMA Transmit Data Level Register + + + read-write + [3:0] + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n + Reset value: 0x0 + DMATDL + + + IC_DMA_TDLR + 0x00000000 + + + 0x0090 + I2C Receive Data Level Register + + + read-write + [3:0] + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n + Reset value: 0x0 + DMARDL + + + IC_DMA_RDLR + 0x00000000 + + + 0x0094 + I2C SDA Setup Register\n\n + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n + Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + + + read-write + [7:0] + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + SDA_SETUP + + + IC_SDA_SETUP + 0x00000064 + + + 0x0098 + I2C ACK General Call Register\n\n + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n + This register is applicable only when the DW_apb_i2c is in slave mode. + + + read-write + [0:0] + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + + + Generate NACK for a General Call + DISABLED + 0 + + + Generate ACK for a General Call + ENABLED + 1 + + + ACK_GEN_CALL + + + IC_ACK_GENERAL_CALL + 0x00000001 + + + 0x009c + I2C Enable Status Register\n\n + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + + + read-only + [2:2] + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + Reset value: 0x0 + + + Slave RX Data is not lost + INACTIVE + 0 + + + Slave RX Data is lost + ACTIVE + 1 + + + SLV_RX_DATA_LOST + + + read-only + [1:1] + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n + OR,\n\n + (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + Reset value: 0x0 + + + Slave is disabled when it is idle + INACTIVE + 0 + + + Slave is disabled when it is active + ACTIVE + 1 + + + SLV_DISABLED_WHILE_BUSY + + + read-only + [0:0] + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n + Reset value: 0x0 + + + I2C disabled + DISABLED + 0 + + + I2C enabled + ENABLED + 1 + + + IC_EN + + + IC_ENABLE_STATUS + 0x00000000 + + + 0x00a0 + I2C SS, FS or FM+ spike suppression limit\n\n + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + + + read-write + [7:0] + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + IC_FS_SPKLEN + + + IC_FS_SPKLEN + 0x00000007 + + + 0x00a8 + Clear RESTART_DET Interrupt Register + + + read-only + [0:0] + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n + Reset value: 0x0 + CLR_RESTART_DET + + + IC_CLR_RESTART_DET + 0x00000000 + + + 0x00f4 + Component Parameter Register 1\n\n + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + + + read-only + [23:16] + TX Buffer Depth = 16 + TX_BUFFER_DEPTH + + + read-only + [15:8] + RX Buffer Depth = 16 + RX_BUFFER_DEPTH + + + read-only + [7:7] + Encoded parameters not visible + ADD_ENCODED_PARAMS + + + read-only + [6:6] + DMA handshaking signals are enabled + HAS_DMA + + + read-only + [5:5] + COMBINED Interrupt outputs + INTR_IO + + + read-only + [4:4] + Programmable count values for each mode. + HC_COUNT_VALUES + + + read-only + [3:2] + MAX SPEED MODE = FAST MODE + MAX_SPEED_MODE + + + read-only + [1:0] + APB data bus width is 32 bits + APB_DATA_WIDTH + + + IC_COMP_PARAM_1 + 0x00000000 + + + 0x00f8 + I2C Component Version Register + + + read-only + [31:0] + IC_COMP_VERSION + + + IC_COMP_VERSION + 0x3230312a + + + 0x00fc + I2C Component Type Register + + + read-only + [31:0] + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + IC_COMP_TYPE + + + IC_COMP_TYPE + 0x44570140 + + + 32 + 1 + + + 0x40048000 + + I2C1_IRQ + 24 + + I2C1 + + + + 0 + 0x1000 + registers + + 0x4004c000 + Control and data interface to SAR ADC + + ADC_IRQ_FIFO + 22 + + ADC + + + 0x0000 + ADC Control and Status + + + read-write + [20:16] + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n + The first channel to be sampled will be the one currently indicated by AINSEL.\n + AINSEL will be updated after each conversion with the newly-selected channel. + RROBIN + + + read-write + [14:12] + Select analog mux input. Updated automatically in round-robin mode. + AINSEL + + + read-write + [10:10] + Some past ADC conversion encountered an error. Write 1 to clear. + oneToClear + ERR_STICKY + + + read-only + [9:9] + The most recent ADC conversion encountered an error; result is undefined or noisy. + ERR + + + read-only + [8:8] + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n + 0 whilst conversion in progress. + READY + + + read-write + [3:3] + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + START_MANY + + + read-write + [2:2] + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + clear + START_ONCE + + + read-write + [1:1] + Power on temperature sensor. 1 - enabled. 0 - disabled. + TS_EN + + + read-write + [0:0] + Power on ADC and enable its clock.\n + 1 - enabled. 0 - disabled. + EN + + + CS + 0x00000000 + + + 0x0004 + Result of most recent ADC conversion + + + read-only + [11:0] + RESULT + + + RESULT + 0x00000000 + + + 0x0008 + FIFO control and status + + + read-write + [27:24] + DREQ/IRQ asserted when level >= threshold + THRESH + + + read-only + [19:16] + The number of conversion results currently waiting in the FIFO + LEVEL + + + read-write + [11:11] + 1 if the FIFO has been overflowed. Write 1 to clear. + oneToClear + OVER + + + read-write + [10:10] + 1 if the FIFO has been underflowed. Write 1 to clear. + oneToClear + UNDER + + + read-only + [9:9] + FULL + + + read-only + [8:8] + EMPTY + + + read-write + [3:3] + If 1: assert DMA requests when FIFO contains data + DREQ_EN + + + read-write + [2:2] + If 1: conversion error bit appears in the FIFO alongside the result + ERR + + + read-write + [1:1] + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + SHIFT + + + read-write + [0:0] + If 1: write result to the FIFO after each conversion. + EN + + + FCS + 0x00000000 + + + 0x000c + Conversion result FIFO + + + read-only + [15:15] + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + ERR + + + read-only + [11:0] + VAL + + + FIFO + 0x00000000 + + + 0x0010 + Clock divider. If non-zero, CS_START_MANY will start conversions\n + at regular intervals rather than back-to-back.\n + The divider is reset when either of these fields are written.\n + Total period is 1 + INT + FRAC / 256 + + + read-write + [23:8] + Integer part of clock divisor. + INT + + + read-write + [7:0] + Fractional part of clock divisor. First-order delta-sigma. + FRAC + + + DIV + 0x00000000 + + + 0x0014 + Raw Interrupts + + + read-only + [0:0] + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + FIFO + + + INTR + 0x00000000 + + + 0x0018 + Interrupt Enable + + + read-write + [0:0] + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + FIFO + + + INTE + 0x00000000 + + + 0x001c + Interrupt Force + + + read-write + [0:0] + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + FIFO + + + INTF + 0x00000000 + + + 0x0020 + Interrupt status after masking & forcing + + + read-only + [0:0] + Triggered when the sample FIFO reaches a certain level.\n + This level can be programmed via the FCS_THRESH field. + FIFO + + + INTS + 0x00000000 + + + 32 + 2 + + + + 0 + 0x1000 + registers + + 0x40050000 + Simple PWM + + PWM_IRQ_WRAP + 4 + + PWM + + + 0x0000 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH0_CSR + 0x00000000 + + + 0x0004 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH0_DIV + 0x00000010 + + + 0x0008 + Direct access to the PWM counter + + + read-write + [15:0] + CH0_CTR + + + CH0_CTR + 0x00000000 + + + 0x000c + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH0_CC + 0x00000000 + + + 0x0010 + Counter wrap value + + + read-write + [15:0] + CH0_TOP + + + CH0_TOP + 0x0000ffff + + + 0x0014 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH1_CSR + 0x00000000 + + + 0x0018 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH1_DIV + 0x00000010 + + + 0x001c + Direct access to the PWM counter + + + read-write + [15:0] + CH1_CTR + + + CH1_CTR + 0x00000000 + + + 0x0020 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH1_CC + 0x00000000 + + + 0x0024 + Counter wrap value + + + read-write + [15:0] + CH1_TOP + + + CH1_TOP + 0x0000ffff + + + 0x0028 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH2_CSR + 0x00000000 + + + 0x002c + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH2_DIV + 0x00000010 + + + 0x0030 + Direct access to the PWM counter + + + read-write + [15:0] + CH2_CTR + + + CH2_CTR + 0x00000000 + + + 0x0034 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH2_CC + 0x00000000 + + + 0x0038 + Counter wrap value + + + read-write + [15:0] + CH2_TOP + + + CH2_TOP + 0x0000ffff + + + 0x003c + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH3_CSR + 0x00000000 + + + 0x0040 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH3_DIV + 0x00000010 + + + 0x0044 + Direct access to the PWM counter + + + read-write + [15:0] + CH3_CTR + + + CH3_CTR + 0x00000000 + + + 0x0048 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH3_CC + 0x00000000 + + + 0x004c + Counter wrap value + + + read-write + [15:0] + CH3_TOP + + + CH3_TOP + 0x0000ffff + + + 0x0050 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH4_CSR + 0x00000000 + + + 0x0054 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH4_DIV + 0x00000010 + + + 0x0058 + Direct access to the PWM counter + + + read-write + [15:0] + CH4_CTR + + + CH4_CTR + 0x00000000 + + + 0x005c + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH4_CC + 0x00000000 + + + 0x0060 + Counter wrap value + + + read-write + [15:0] + CH4_TOP + + + CH4_TOP + 0x0000ffff + + + 0x0064 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH5_CSR + 0x00000000 + + + 0x0068 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH5_DIV + 0x00000010 + + + 0x006c + Direct access to the PWM counter + + + read-write + [15:0] + CH5_CTR + + + CH5_CTR + 0x00000000 + + + 0x0070 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH5_CC + 0x00000000 + + + 0x0074 + Counter wrap value + + + read-write + [15:0] + CH5_TOP + + + CH5_TOP + 0x0000ffff + + + 0x0078 + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH6_CSR + 0x00000000 + + + 0x007c + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH6_DIV + 0x00000010 + + + 0x0080 + Direct access to the PWM counter + + + read-write + [15:0] + CH6_CTR + + + CH6_CTR + 0x00000000 + + + 0x0084 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH6_CC + 0x00000000 + + + 0x0088 + Counter wrap value + + + read-write + [15:0] + CH6_TOP + + + CH6_TOP + 0x0000ffff + + + 0x008c + Control and status register + + + read-write + [7:7] + Advance the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running\n + at less than full speed (div_int + div_frac / 16 > 1) + clear + PH_ADV + + + read-write + [6:6] + Retard the phase of the counter by 1 count, while it is running.\n + Self-clearing. Write a 1, and poll until low. Counter must be running. + clear + PH_RET + + + read-write + [5:4] + + + Free-running counting at rate dictated by fractional divider + div + 0 + + + Fractional divider operation is gated by the PWM B pin. + level + 1 + + + Counter advances with each rising edge of the PWM B pin. + rise + 2 + + + Counter advances with each falling edge of the PWM B pin. + fall + 3 + + + DIVMODE + + + read-write + [3:3] + Invert output B + B_INV + + + read-write + [2:2] + Invert output A + A_INV + + + read-write + [1:1] + 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT + + + read-write + [0:0] + Enable the PWM channel. + EN + + + CH7_CSR + 0x00000000 + + + 0x0090 + INT and FRAC form a fixed-point fractional number.\n + Counting rate is system clock frequency divided by this number.\n + Fractional division uses simple 1st-order sigma-delta. + + + read-write + [11:4] + INT + + + read-write + [3:0] + FRAC + + + CH7_DIV + 0x00000010 + + + 0x0094 + Direct access to the PWM counter + + + read-write + [15:0] + CH7_CTR + + + CH7_CTR + 0x00000000 + + + 0x0098 + Counter compare values + + + read-write + [31:16] + B + + + read-write + [15:0] + A + + + CH7_CC + 0x00000000 + + + 0x009c + Counter wrap value + + + read-write + [15:0] + CH7_TOP + + + CH7_TOP + 0x0000ffff + + + 0x00a0 + This register aliases the CSR_EN bits for all channels.\n + Writing to this register allows multiple channels to be enabled\n + or disabled simultaneously, so they can run in perfect sync.\n + For each channel, there is only one physical EN register bit,\n + which can be accessed through here or CHx_CSR. + + + read-write + [7:7] + CH7 + + + read-write + [6:6] + CH6 + + + read-write + [5:5] + CH5 + + + read-write + [4:4] + CH4 + + + read-write + [3:3] + CH3 + + + read-write + [2:2] + CH2 + + + read-write + [1:1] + CH1 + + + read-write + [0:0] + CH0 + + + EN + 0x00000000 + + + 0x00a4 + Raw Interrupts + + + read-write + [7:7] + oneToClear + CH7 + + + read-write + [6:6] + oneToClear + CH6 + + + read-write + [5:5] + oneToClear + CH5 + + + read-write + [4:4] + oneToClear + CH4 + + + read-write + [3:3] + oneToClear + CH3 + + + read-write + [2:2] + oneToClear + CH2 + + + read-write + [1:1] + oneToClear + CH1 + + + read-write + [0:0] + oneToClear + CH0 + + + INTR + 0x00000000 + + + 0x00a8 + Interrupt Enable + + + read-write + [7:7] + CH7 + + + read-write + [6:6] + CH6 + + + read-write + [5:5] + CH5 + + + read-write + [4:4] + CH4 + + + read-write + [3:3] + CH3 + + + read-write + [2:2] + CH2 + + + read-write + [1:1] + CH1 + + + read-write + [0:0] + CH0 + + + INTE + 0x00000000 + + + 0x00ac + Interrupt Force + + + read-write + [7:7] + CH7 + + + read-write + [6:6] + CH6 + + + read-write + [5:5] + CH5 + + + read-write + [4:4] + CH4 + + + read-write + [3:3] + CH3 + + + read-write + [2:2] + CH2 + + + read-write + [1:1] + CH1 + + + read-write + [0:0] + CH0 + + + INTF + 0x00000000 + + + 0x00b0 + Interrupt status after masking & forcing + + + read-only + [7:7] + CH7 + + + read-only + [6:6] + CH6 + + + read-only + [5:5] + CH5 + + + read-only + [4:4] + CH4 + + + read-only + [3:3] + CH3 + + + read-only + [2:2] + CH2 + + + read-only + [1:1] + CH1 + + + read-only + [0:0] + CH0 + + + INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40054000 + Controls time and alarms\n + time is a 64 bit value indicating the time in usec since power-on\n + timeh is the top 32 bits of time & timel is the bottom 32 bits\n + to change time write to timelw before timehw\n + to read time read from timelr before timehr\n + An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n + When an alarm is pending, the corresponding alarm_running signal will be high\n + An alarm can be cancelled before it has finished by clearing the alarm_enable\n + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n + To clear the interrupt write a 1 to the corresponding alarm_irq + + TIMER_IRQ_0 + 0 + + + TIMER_IRQ_1 + 1 + + + TIMER_IRQ_2 + 2 + + + TIMER_IRQ_3 + 3 + + TIMER + + + write-only + 0x0000 + Write to bits 63:32 of time\n + always write timelw before timehw + TIMEHW + 0x00000000 + + + write-only + 0x0004 + Write to bits 31:0 of time\n + writes do not get copied to time until timehw is written + TIMELW + 0x00000000 + + + read-only + 0x0008 + Read from bits 63:32 of time\n + always read timelr before timehr + TIMEHR + 0x00000000 + + + read-only + 0x000c + Read from bits 31:0 of time + TIMELR + 0x00000000 + + + read-write + 0x0010 + Arm alarm 0, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + ALARM0 + 0x00000000 + + + read-write + 0x0014 + Arm alarm 1, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + ALARM1 + 0x00000000 + + + read-write + 0x0018 + Arm alarm 2, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + ALARM2 + 0x00000000 + + + read-write + 0x001c + Arm alarm 3, and configure the time it will fire.\n + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n + The alarm will disarm itself once it fires, and can\n + be disarmed early using the ARMED status register. + ALARM3 + 0x00000000 + + + 0x0020 + Indicates the armed/disarmed status of each alarm.\n + A write to the corresponding ALARMx register arms the alarm.\n + Alarms automatically disarm upon firing, but writing ones here\n + will disarm immediately without waiting to fire. + + + read-write + [3:0] + oneToClear + ARMED + + + ARMED + 0x00000000 + + + read-only + 0x0024 + Raw read from bits 63:32 of time (no side effects) + TIMERAWH + 0x00000000 + + + read-only + 0x0028 + Raw read from bits 31:0 of time (no side effects) + TIMERAWL + 0x00000000 + + + 0x002c + Set bits high to enable pause when the corresponding debug ports are active + + + read-write + [2:2] + Pause when processor 1 is in debug mode + DBG1 + + + read-write + [1:1] + Pause when processor 0 is in debug mode + DBG0 + + + DBGPAUSE + 0x00000007 + + + 0x0030 + Set high to pause the timer + + + read-write + [0:0] + PAUSE + + + PAUSE + 0x00000000 + + + 0x0034 + Raw Interrupts + + + read-write + [3:3] + oneToClear + ALARM_3 + + + read-write + [2:2] + oneToClear + ALARM_2 + + + read-write + [1:1] + oneToClear + ALARM_1 + + + read-write + [0:0] + oneToClear + ALARM_0 + + + INTR + 0x00000000 + + + 0x0038 + Interrupt Enable + + + read-write + [3:3] + ALARM_3 + + + read-write + [2:2] + ALARM_2 + + + read-write + [1:1] + ALARM_1 + + + read-write + [0:0] + ALARM_0 + + + INTE + 0x00000000 + + + 0x003c + Interrupt Force + + + read-write + [3:3] + ALARM_3 + + + read-write + [2:2] + ALARM_2 + + + read-write + [1:1] + ALARM_1 + + + read-write + [0:0] + ALARM_0 + + + INTF + 0x00000000 + + + 0x0040 + Interrupt status after masking & forcing + + + read-only + [3:3] + ALARM_3 + + + read-only + [2:2] + ALARM_2 + + + read-only + [1:1] + ALARM_1 + + + read-only + [0:0] + ALARM_0 + + + INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40058000 + WATCHDOG + + + 0x0000 + Watchdog control\n + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n + The watchdog can be triggered in software. + + + read-write + [31:31] + Trigger a watchdog reset + clear + TRIGGER + + + read-write + [30:30] + When not enabled the watchdog timer is paused + ENABLE + + + read-write + [26:26] + Pause the watchdog timer when processor 1 is in debug mode + PAUSE_DBG1 + + + read-write + [25:25] + Pause the watchdog timer when processor 0 is in debug mode + PAUSE_DBG0 + + + read-write + [24:24] + Pause the watchdog timer when JTAG is accessing the bus fabric + PAUSE_JTAG + + + read-only + [23:0] + Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered + TIME + + + CTRL + 0x07000000 + + + 0x0004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + + + write-only + [23:0] + LOAD + + + LOAD + 0x00000000 + + + 0x0008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + + read-only + [1:1] + FORCE + + + read-only + [0:0] + TIMER + + + REASON + 0x00000000 + + + read-write + 0x000c + Scratch register. Information persists through soft reset of the chip. + SCRATCH0 + 0x00000000 + + + read-write + 0x0010 + Scratch register. Information persists through soft reset of the chip. + SCRATCH1 + 0x00000000 + + + read-write + 0x0014 + Scratch register. Information persists through soft reset of the chip. + SCRATCH2 + 0x00000000 + + + read-write + 0x0018 + Scratch register. Information persists through soft reset of the chip. + SCRATCH3 + 0x00000000 + + + read-write + 0x001c + Scratch register. Information persists through soft reset of the chip. + SCRATCH4 + 0x00000000 + + + read-write + 0x0020 + Scratch register. Information persists through soft reset of the chip. + SCRATCH5 + 0x00000000 + + + read-write + 0x0024 + Scratch register. Information persists through soft reset of the chip. + SCRATCH6 + 0x00000000 + + + read-write + 0x0028 + Scratch register. Information persists through soft reset of the chip. + SCRATCH7 + 0x00000000 + + + 0x002c + Controls the tick generator + + + read-only + [19:11] + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + COUNT + + + read-only + [10:10] + Is the tick generator running? + RUNNING + + + read-write + [9:9] + start / stop tick generation + ENABLE + + + read-write + [8:0] + Total number of clk_tick cycles before the next tick. + CYCLES + + + TICK + 0x00000200 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x4005c000 + Register block to control RTC + + RTC_IRQ + 25 + + RTC + + + 0x0000 + Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. + + + read-write + [15:0] + CLKDIV_M1 + + + CLKDIV_M1 + 0x00000000 + + + 0x0004 + RTC setup register 0 + + + read-write + [23:12] + Year + YEAR + + + read-write + [11:8] + Month (1..12) + MONTH + + + read-write + [4:0] + Day of the month (1..31) + DAY + + + SETUP_0 + 0x00000000 + + + 0x0008 + RTC setup register 1 + + + read-write + [26:24] + Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 + DOTW + + + read-write + [20:16] + Hours + HOUR + + + read-write + [13:8] + Minutes + MIN + + + read-write + [5:0] + Seconds + SEC + + + SETUP_1 + 0x00000000 + + + 0x000c + RTC Control and status + + + read-write + [8:8] + If set, leapyear is forced off.\n + Useful for years divisible by 100 but not by 400 + FORCE_NOTLEAPYEAR + + + read-write + [4:4] + Load RTC + clear + LOAD + + + read-only + [1:1] + RTC enabled (running) + RTC_ACTIVE + + + read-write + [0:0] + Enable RTC + RTC_ENABLE + + + CTRL + 0x00000000 + + + 0x0010 + Interrupt setup register 0 + + + read-only + [29:29] + MATCH_ACTIVE + + + read-write + [28:28] + Global match enable. Don't change any other value while this one is enabled + MATCH_ENA + + + read-write + [26:26] + Enable year matching + YEAR_ENA + + + read-write + [25:25] + Enable month matching + MONTH_ENA + + + read-write + [24:24] + Enable day matching + DAY_ENA + + + read-write + [23:12] + Year + YEAR + + + read-write + [11:8] + Month (1..12) + MONTH + + + read-write + [4:0] + Day of the month (1..31) + DAY + + + IRQ_SETUP_0 + 0x00000000 + + + 0x0014 + Interrupt setup register 1 + + + read-write + [31:31] + Enable day of the week matching + DOTW_ENA + + + read-write + [30:30] + Enable hour matching + HOUR_ENA + + + read-write + [29:29] + Enable minute matching + MIN_ENA + + + read-write + [28:28] + Enable second matching + SEC_ENA + + + read-write + [26:24] + Day of the week + DOTW + + + read-write + [20:16] + Hours + HOUR + + + read-write + [13:8] + Minutes + MIN + + + read-write + [5:0] + Seconds + SEC + + + IRQ_SETUP_1 + 0x00000000 + + + 0x0018 + RTC register 1. + + + read-only + [23:12] + Year + YEAR + + + read-only + [11:8] + Month (1..12) + MONTH + + + read-only + [4:0] + Day of the month (1..31) + DAY + + + RTC_1 + 0x00000000 + + + 0x001c + RTC register 0\n + Read this before RTC 1! + + + read-only + [26:24] + Day of the week + DOTW + + + read-only + [20:16] + Hours + HOUR + + + read-only + [13:8] + Minutes + MIN + + + read-only + [5:0] + Seconds + SEC + + + RTC_0 + 0x00000000 + + + 0x0020 + Raw Interrupts + + + read-only + [0:0] + RTC + + + INTR + 0x00000000 + + + 0x0024 + Interrupt Enable + + + read-write + [0:0] + RTC + + + INTE + 0x00000000 + + + 0x0028 + Interrupt Force + + + read-write + [0:0] + RTC + + + INTF + 0x00000000 + + + 0x002c + Interrupt status after masking & forcing + + + read-only + [0:0] + RTC + + + INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40060000 + ROSC + + + 0x0000 + Ring Oscillator control + + + read-write + [23:12] + On power-up this field is initialised to ENABLE\n + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + + + DISABLE + 3358 + + + ENABLE + 4011 + + + ENABLE + + + read-write + [11:0] + Controls the number of delay stages in the ROSC ring\n + LOW uses stages 0 to 7\n + MEDIUM uses stages 0 to 5\n + HIGH uses stages 0 to 3\n + TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n + The clock output will not glitch when changing the range up one step at a time\n + The clock output will glitch when changing the range down\n + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + FREQ_RANGE + + + CTRL + 0x00000aa0 + + + 0x0004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n + The drive strength has 4 levels determined by the number of bits set\n + Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n + 0 bits set is the default drive strength\n + 1 bit set doubles the drive strength\n + 2 bits set triples drive strength\n + 3 bits set quadruples drive strength + + + read-write + [31:16] + Set to 0x9696 to apply the settings\n + Any other value in this field will set all drive strengths to 0 + + + PASS + 38550 + + + PASSWD + + + read-write + [14:12] + Stage 3 drive strength + DS3 + + + read-write + [10:8] + Stage 2 drive strength + DS2 + + + read-write + [6:4] + Stage 1 drive strength + DS1 + + + read-write + [2:0] + Stage 0 drive strength + DS0 + + + FREQA + 0x00000000 + + + 0x0008 + For a detailed description see freqa register + + + read-write + [31:16] + Set to 0x9696 to apply the settings\n + Any other value in this field will set all drive strengths to 0 + + + PASS + 38550 + + + PASSWD + + + read-write + [14:12] + Stage 7 drive strength + DS7 + + + read-write + [10:8] + Stage 6 drive strength + DS6 + + + read-write + [6:4] + Stage 5 drive strength + DS5 + + + read-write + [2:0] + Stage 4 drive strength + DS4 + + + FREQB + 0x00000000 + + + read-write + 0x000c + Ring Oscillator pause control\n + This is used to save power by pausing the ROSC\n + On power-up this field is initialised to WAKE\n + An invalid write will also select WAKE\n + Warning: setup the irq before selecting dormant mode + DORMANT + 0x00000000 + + + 0x0010 + Controls the output divider + + + read-write + [11:0] + set to 0xaa0 + div where\n + div = 0 divides by 32\n + div = 1-31 divides by div\n + any other value sets div=0 and therefore divides by 32\n + this register resets to div=16 + + + PASS + 2720 + + + DIV + + + DIV + 0x00000000 + + + 0x0014 + Controls the phase shifted output + + + read-write + [11:4] + set to 0xaa0\n + any other value enables the output with shift=0 + PASSWD + + + read-write + [3:3] + enable the phase-shifted output\n + this can be changed on-the-fly + ENABLE + + + read-write + [2:2] + invert the phase-shifted output\n + this is ignored when div=1 + FLIP + + + read-write + [1:0] + phase shift the phase-shifted output by SHIFT input clocks\n + this can be changed on-the-fly\n + must be set to 0 before setting div=1 + SHIFT + + + PHASE + 0x00000008 + + + 0x0018 + Ring Oscillator Status + + + read-only + [31:31] + Oscillator is running and stable + STABLE + + + read-write + [24:24] + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT + oneToClear + BADWRITE + + + read-only + [16:16] + post-divider is running\n + this resets to 0 but transitions to 1 during chip startup + DIV_RUNNING + + + read-only + [12:12] + Oscillator is enabled but not necessarily running and stable\n + this resets to 0 but transitions to 1 during chip startup + ENABLED + + + STATUS + 0x00000000 + + + 0x001c + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + + + read-only + [0:0] + RANDOMBIT + + + RANDOMBIT + 0x00000001 + + + 0x0020 + A down counter running at the ROSC frequency which counts to zero and stops.\n + To start the counter write a non-zero value.\n + Can be used for short software pauses when setting up time sensitive hardware. + + + read-write + [7:0] + COUNT + + + COUNT + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x40064000 + control and status for on-chip voltage regulator and chip level reset subsystem + VREG_AND_CHIP_RESET + + + 0x0000 + Voltage regulator control and status + + + read-only + [12:12] + regulation status\n + 0=not in regulation, 1=in regulation + ROK + + + read-write + [7:4] + output voltage select\n + 0000 to 0101 - 0.80V\n + 0110 - 0.85V\n + 0111 - 0.90V\n + 1000 - 0.95V\n + 1001 - 1.00V\n + 1010 - 1.05V\n + 1011 - 1.10V (default)\n + 1100 - 1.15V\n + 1101 - 1.20V\n + 1110 - 1.25V\n + 1111 - 1.30V + VSEL + + + read-write + [1:1] + high impedance mode select\n + 0=not in high impedance mode, 1=in high impedance mode + HIZ + + + read-write + [0:0] + enable\n + 0=not enabled, 1=enabled + EN + + + VREG + 0x000000b1 + + + 0x0004 + brown-out detection control + + + read-write + [7:4] + threshold select\n + 0000 - 0.473V\n + 0001 - 0.516V\n + 0010 - 0.559V\n + 0011 - 0.602V\n + 0100 - 0.645V\n + 0101 - 0.688V\n + 0110 - 0.731V\n + 0111 - 0.774V\n + 1000 - 0.817V\n + 1001 - 0.860V (default)\n + 1010 - 0.903V\n + 1011 - 0.946V\n + 1100 - 0.989V\n + 1101 - 1.032V\n + 1110 - 1.075V\n + 1111 - 1.118V + VSEL + + + read-write + [0:0] + enable\n + 0=not enabled, 1=enabled + EN + + + BOD + 0x00000091 + + + 0x0008 + Chip reset control and status + + + read-write + [24:24] + This is set by psm_restart from the debugger.\n + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. + oneToClear + PSM_RESTART_FLAG + + + read-only + [20:20] + Last reset was from the debug port + HAD_PSM_RESTART + + + read-only + [16:16] + Last reset was from the RUN pin + HAD_RUN + + + read-only + [8:8] + Last reset was from the power-on reset or brown-out detection blocks + HAD_POR + + + CHIP_RESET + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x4006c000 + Testbench manager. Allows the programmer to know what platform their software is running on. + TBMAN + + + 0x0000 + Indicates the type of platform in use + + + read-only + [1:1] + Indicates the platform is an FPGA + FPGA + + + read-only + [0:0] + Indicates the platform is an ASIC + ASIC + + + PLATFORM + 0x00000005 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x50000000 + DMA with separate read and write masters + + DMA_IRQ_0 + 11 + + + DMA_IRQ_1 + 12 + + DMA + + + read-write + 0x0000 + DMA Channel 0 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH0_READ_ADDR + 0x00000000 + + + read-write + 0x0004 + DMA Channel 0 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH0_WRITE_ADDR + 0x00000000 + + + read-write + 0x0008 + DMA Channel 0 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH0_TRANS_COUNT + 0x00000000 + + + 0x000c + DMA Channel 0 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (0). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH0_CTRL_TRIG + 0x00000000 + + + read-only + 0x0010 + Alias for channel 0 CTRL register + CH0_AL1_CTRL + 0x00000000 + + + read-only + 0x0014 + Alias for channel 0 READ_ADDR register + CH0_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0018 + Alias for channel 0 WRITE_ADDR register + CH0_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x001c + Alias for channel 0 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH0_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0020 + Alias for channel 0 CTRL register + CH0_AL2_CTRL + 0x00000000 + + + read-only + 0x0024 + Alias for channel 0 TRANS_COUNT register + CH0_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0028 + Alias for channel 0 READ_ADDR register + CH0_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x002c + Alias for channel 0 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH0_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0030 + Alias for channel 0 CTRL register + CH0_AL3_CTRL + 0x00000000 + + + read-only + 0x0034 + Alias for channel 0 WRITE_ADDR register + CH0_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0038 + Alias for channel 0 TRANS_COUNT register + CH0_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x003c + Alias for channel 0 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH0_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0040 + DMA Channel 1 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH1_READ_ADDR + 0x00000000 + + + read-write + 0x0044 + DMA Channel 1 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH1_WRITE_ADDR + 0x00000000 + + + read-write + 0x0048 + DMA Channel 1 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH1_TRANS_COUNT + 0x00000000 + + + 0x004c + DMA Channel 1 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (1). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH1_CTRL_TRIG + 0x00000800 + + + read-only + 0x0050 + Alias for channel 1 CTRL register + CH1_AL1_CTRL + 0x00000000 + + + read-only + 0x0054 + Alias for channel 1 READ_ADDR register + CH1_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0058 + Alias for channel 1 WRITE_ADDR register + CH1_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x005c + Alias for channel 1 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH1_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0060 + Alias for channel 1 CTRL register + CH1_AL2_CTRL + 0x00000000 + + + read-only + 0x0064 + Alias for channel 1 TRANS_COUNT register + CH1_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0068 + Alias for channel 1 READ_ADDR register + CH1_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x006c + Alias for channel 1 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH1_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0070 + Alias for channel 1 CTRL register + CH1_AL3_CTRL + 0x00000000 + + + read-only + 0x0074 + Alias for channel 1 WRITE_ADDR register + CH1_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0078 + Alias for channel 1 TRANS_COUNT register + CH1_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x007c + Alias for channel 1 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH1_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0080 + DMA Channel 2 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH2_READ_ADDR + 0x00000000 + + + read-write + 0x0084 + DMA Channel 2 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH2_WRITE_ADDR + 0x00000000 + + + read-write + 0x0088 + DMA Channel 2 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH2_TRANS_COUNT + 0x00000000 + + + 0x008c + DMA Channel 2 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (2). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH2_CTRL_TRIG + 0x00001000 + + + read-only + 0x0090 + Alias for channel 2 CTRL register + CH2_AL1_CTRL + 0x00000000 + + + read-only + 0x0094 + Alias for channel 2 READ_ADDR register + CH2_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0098 + Alias for channel 2 WRITE_ADDR register + CH2_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x009c + Alias for channel 2 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH2_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x00a0 + Alias for channel 2 CTRL register + CH2_AL2_CTRL + 0x00000000 + + + read-only + 0x00a4 + Alias for channel 2 TRANS_COUNT register + CH2_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x00a8 + Alias for channel 2 READ_ADDR register + CH2_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x00ac + Alias for channel 2 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH2_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x00b0 + Alias for channel 2 CTRL register + CH2_AL3_CTRL + 0x00000000 + + + read-only + 0x00b4 + Alias for channel 2 WRITE_ADDR register + CH2_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x00b8 + Alias for channel 2 TRANS_COUNT register + CH2_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x00bc + Alias for channel 2 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH2_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x00c0 + DMA Channel 3 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH3_READ_ADDR + 0x00000000 + + + read-write + 0x00c4 + DMA Channel 3 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH3_WRITE_ADDR + 0x00000000 + + + read-write + 0x00c8 + DMA Channel 3 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH3_TRANS_COUNT + 0x00000000 + + + 0x00cc + DMA Channel 3 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (3). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH3_CTRL_TRIG + 0x00001800 + + + read-only + 0x00d0 + Alias for channel 3 CTRL register + CH3_AL1_CTRL + 0x00000000 + + + read-only + 0x00d4 + Alias for channel 3 READ_ADDR register + CH3_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x00d8 + Alias for channel 3 WRITE_ADDR register + CH3_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x00dc + Alias for channel 3 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH3_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x00e0 + Alias for channel 3 CTRL register + CH3_AL2_CTRL + 0x00000000 + + + read-only + 0x00e4 + Alias for channel 3 TRANS_COUNT register + CH3_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x00e8 + Alias for channel 3 READ_ADDR register + CH3_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x00ec + Alias for channel 3 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH3_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x00f0 + Alias for channel 3 CTRL register + CH3_AL3_CTRL + 0x00000000 + + + read-only + 0x00f4 + Alias for channel 3 WRITE_ADDR register + CH3_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x00f8 + Alias for channel 3 TRANS_COUNT register + CH3_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x00fc + Alias for channel 3 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH3_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0100 + DMA Channel 4 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH4_READ_ADDR + 0x00000000 + + + read-write + 0x0104 + DMA Channel 4 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH4_WRITE_ADDR + 0x00000000 + + + read-write + 0x0108 + DMA Channel 4 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH4_TRANS_COUNT + 0x00000000 + + + 0x010c + DMA Channel 4 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (4). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH4_CTRL_TRIG + 0x00002000 + + + read-only + 0x0110 + Alias for channel 4 CTRL register + CH4_AL1_CTRL + 0x00000000 + + + read-only + 0x0114 + Alias for channel 4 READ_ADDR register + CH4_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0118 + Alias for channel 4 WRITE_ADDR register + CH4_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x011c + Alias for channel 4 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH4_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0120 + Alias for channel 4 CTRL register + CH4_AL2_CTRL + 0x00000000 + + + read-only + 0x0124 + Alias for channel 4 TRANS_COUNT register + CH4_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0128 + Alias for channel 4 READ_ADDR register + CH4_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x012c + Alias for channel 4 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH4_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0130 + Alias for channel 4 CTRL register + CH4_AL3_CTRL + 0x00000000 + + + read-only + 0x0134 + Alias for channel 4 WRITE_ADDR register + CH4_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0138 + Alias for channel 4 TRANS_COUNT register + CH4_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x013c + Alias for channel 4 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH4_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0140 + DMA Channel 5 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH5_READ_ADDR + 0x00000000 + + + read-write + 0x0144 + DMA Channel 5 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH5_WRITE_ADDR + 0x00000000 + + + read-write + 0x0148 + DMA Channel 5 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH5_TRANS_COUNT + 0x00000000 + + + 0x014c + DMA Channel 5 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (5). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH5_CTRL_TRIG + 0x00002800 + + + read-only + 0x0150 + Alias for channel 5 CTRL register + CH5_AL1_CTRL + 0x00000000 + + + read-only + 0x0154 + Alias for channel 5 READ_ADDR register + CH5_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0158 + Alias for channel 5 WRITE_ADDR register + CH5_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x015c + Alias for channel 5 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH5_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0160 + Alias for channel 5 CTRL register + CH5_AL2_CTRL + 0x00000000 + + + read-only + 0x0164 + Alias for channel 5 TRANS_COUNT register + CH5_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0168 + Alias for channel 5 READ_ADDR register + CH5_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x016c + Alias for channel 5 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH5_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0170 + Alias for channel 5 CTRL register + CH5_AL3_CTRL + 0x00000000 + + + read-only + 0x0174 + Alias for channel 5 WRITE_ADDR register + CH5_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0178 + Alias for channel 5 TRANS_COUNT register + CH5_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x017c + Alias for channel 5 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH5_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0180 + DMA Channel 6 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH6_READ_ADDR + 0x00000000 + + + read-write + 0x0184 + DMA Channel 6 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH6_WRITE_ADDR + 0x00000000 + + + read-write + 0x0188 + DMA Channel 6 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH6_TRANS_COUNT + 0x00000000 + + + 0x018c + DMA Channel 6 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (6). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH6_CTRL_TRIG + 0x00003000 + + + read-only + 0x0190 + Alias for channel 6 CTRL register + CH6_AL1_CTRL + 0x00000000 + + + read-only + 0x0194 + Alias for channel 6 READ_ADDR register + CH6_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0198 + Alias for channel 6 WRITE_ADDR register + CH6_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x019c + Alias for channel 6 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH6_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x01a0 + Alias for channel 6 CTRL register + CH6_AL2_CTRL + 0x00000000 + + + read-only + 0x01a4 + Alias for channel 6 TRANS_COUNT register + CH6_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x01a8 + Alias for channel 6 READ_ADDR register + CH6_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x01ac + Alias for channel 6 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH6_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x01b0 + Alias for channel 6 CTRL register + CH6_AL3_CTRL + 0x00000000 + + + read-only + 0x01b4 + Alias for channel 6 WRITE_ADDR register + CH6_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x01b8 + Alias for channel 6 TRANS_COUNT register + CH6_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x01bc + Alias for channel 6 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH6_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x01c0 + DMA Channel 7 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH7_READ_ADDR + 0x00000000 + + + read-write + 0x01c4 + DMA Channel 7 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH7_WRITE_ADDR + 0x00000000 + + + read-write + 0x01c8 + DMA Channel 7 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH7_TRANS_COUNT + 0x00000000 + + + 0x01cc + DMA Channel 7 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (7). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH7_CTRL_TRIG + 0x00003800 + + + read-only + 0x01d0 + Alias for channel 7 CTRL register + CH7_AL1_CTRL + 0x00000000 + + + read-only + 0x01d4 + Alias for channel 7 READ_ADDR register + CH7_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x01d8 + Alias for channel 7 WRITE_ADDR register + CH7_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x01dc + Alias for channel 7 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH7_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x01e0 + Alias for channel 7 CTRL register + CH7_AL2_CTRL + 0x00000000 + + + read-only + 0x01e4 + Alias for channel 7 TRANS_COUNT register + CH7_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x01e8 + Alias for channel 7 READ_ADDR register + CH7_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x01ec + Alias for channel 7 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH7_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x01f0 + Alias for channel 7 CTRL register + CH7_AL3_CTRL + 0x00000000 + + + read-only + 0x01f4 + Alias for channel 7 WRITE_ADDR register + CH7_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x01f8 + Alias for channel 7 TRANS_COUNT register + CH7_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x01fc + Alias for channel 7 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH7_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0200 + DMA Channel 8 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH8_READ_ADDR + 0x00000000 + + + read-write + 0x0204 + DMA Channel 8 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH8_WRITE_ADDR + 0x00000000 + + + read-write + 0x0208 + DMA Channel 8 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH8_TRANS_COUNT + 0x00000000 + + + 0x020c + DMA Channel 8 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (8). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH8_CTRL_TRIG + 0x00004000 + + + read-only + 0x0210 + Alias for channel 8 CTRL register + CH8_AL1_CTRL + 0x00000000 + + + read-only + 0x0214 + Alias for channel 8 READ_ADDR register + CH8_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0218 + Alias for channel 8 WRITE_ADDR register + CH8_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x021c + Alias for channel 8 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH8_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0220 + Alias for channel 8 CTRL register + CH8_AL2_CTRL + 0x00000000 + + + read-only + 0x0224 + Alias for channel 8 TRANS_COUNT register + CH8_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0228 + Alias for channel 8 READ_ADDR register + CH8_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x022c + Alias for channel 8 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH8_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0230 + Alias for channel 8 CTRL register + CH8_AL3_CTRL + 0x00000000 + + + read-only + 0x0234 + Alias for channel 8 WRITE_ADDR register + CH8_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0238 + Alias for channel 8 TRANS_COUNT register + CH8_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x023c + Alias for channel 8 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH8_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0240 + DMA Channel 9 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH9_READ_ADDR + 0x00000000 + + + read-write + 0x0244 + DMA Channel 9 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH9_WRITE_ADDR + 0x00000000 + + + read-write + 0x0248 + DMA Channel 9 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH9_TRANS_COUNT + 0x00000000 + + + 0x024c + DMA Channel 9 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (9). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH9_CTRL_TRIG + 0x00004800 + + + read-only + 0x0250 + Alias for channel 9 CTRL register + CH9_AL1_CTRL + 0x00000000 + + + read-only + 0x0254 + Alias for channel 9 READ_ADDR register + CH9_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0258 + Alias for channel 9 WRITE_ADDR register + CH9_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x025c + Alias for channel 9 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH9_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x0260 + Alias for channel 9 CTRL register + CH9_AL2_CTRL + 0x00000000 + + + read-only + 0x0264 + Alias for channel 9 TRANS_COUNT register + CH9_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x0268 + Alias for channel 9 READ_ADDR register + CH9_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x026c + Alias for channel 9 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH9_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x0270 + Alias for channel 9 CTRL register + CH9_AL3_CTRL + 0x00000000 + + + read-only + 0x0274 + Alias for channel 9 WRITE_ADDR register + CH9_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x0278 + Alias for channel 9 TRANS_COUNT register + CH9_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x027c + Alias for channel 9 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH9_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x0280 + DMA Channel 10 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH10_READ_ADDR + 0x00000000 + + + read-write + 0x0284 + DMA Channel 10 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH10_WRITE_ADDR + 0x00000000 + + + read-write + 0x0288 + DMA Channel 10 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH10_TRANS_COUNT + 0x00000000 + + + 0x028c + DMA Channel 10 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (10). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH10_CTRL_TRIG + 0x00005000 + + + read-only + 0x0290 + Alias for channel 10 CTRL register + CH10_AL1_CTRL + 0x00000000 + + + read-only + 0x0294 + Alias for channel 10 READ_ADDR register + CH10_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x0298 + Alias for channel 10 WRITE_ADDR register + CH10_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x029c + Alias for channel 10 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH10_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x02a0 + Alias for channel 10 CTRL register + CH10_AL2_CTRL + 0x00000000 + + + read-only + 0x02a4 + Alias for channel 10 TRANS_COUNT register + CH10_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x02a8 + Alias for channel 10 READ_ADDR register + CH10_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x02ac + Alias for channel 10 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH10_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x02b0 + Alias for channel 10 CTRL register + CH10_AL3_CTRL + 0x00000000 + + + read-only + 0x02b4 + Alias for channel 10 WRITE_ADDR register + CH10_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x02b8 + Alias for channel 10 TRANS_COUNT register + CH10_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x02bc + Alias for channel 10 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH10_AL3_READ_ADDR_TRIG + 0x00000000 + + + read-write + 0x02c0 + DMA Channel 11 Read Address pointer\n + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + CH11_READ_ADDR + 0x00000000 + + + read-write + 0x02c4 + DMA Channel 11 Write Address pointer\n + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + CH11_WRITE_ADDR + 0x00000000 + + + read-write + 0x02c8 + DMA Channel 11 Transfer Count\n + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + CH11_TRANS_COUNT + 0x00000000 + + + 0x02cc + DMA Channel 11 Control and Status + + + read-only + [31:31] + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR + + + read-write + [30:30] + If 1, the channel received a read bus error. Write one to clear.\n + READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) + oneToClear + READ_ERROR + + + read-write + [29:29] + If 1, the channel received a write bus error. Write one to clear.\n + WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) + oneToClear + WRITE_ERROR + + + read-only + [24:24] + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY + + + read-write + [23:23] + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n + This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN + + + read-write + [22:22] + Apply byte-swap transformation to DMA data.\n + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + BSWAP + + + read-write + [21:21] + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + IRQ_QUIET + + + read-write + [20:15] + Select a Transfer Request signal.\n + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n + 0x0 to 0x3a -> select DREQ n as TREQ + + + Select Timer 0 as TREQ + TIMER0 + 59 + + + Select Timer 1 as TREQ + TIMER1 + 60 + + + Select Timer 2 as TREQ (Optional) + TIMER2 + 61 + + + Select Timer 3 as TREQ (Optional) + TIMER3 + 62 + + + Permanent request, for unpaced transfers. + PERMANENT + 63 + + + TREQ_SEL + + + read-write + [14:11] + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n + Reset value is equal to channel number (11). + CHAIN_TO + + + read-write + [10:10] + Select whether RING_SIZE applies to read or write addresses.\n + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + RING_SEL + + + read-write + [9:6] + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + + + RING_NONE + 0 + + + RING_SIZE + + + read-write + [5:5] + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n + Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE + + + read-write + [4:4] + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n + Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ + + + read-write + [3:2] + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + DATA_SIZE + + + read-write + [1:1] + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY + + + read-write + [0:0] + DMA Channel Enable.\n + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + EN + + + CH11_CTRL_TRIG + 0x00005800 + + + read-only + 0x02d0 + Alias for channel 11 CTRL register + CH11_AL1_CTRL + 0x00000000 + + + read-only + 0x02d4 + Alias for channel 11 READ_ADDR register + CH11_AL1_READ_ADDR + 0x00000000 + + + read-only + 0x02d8 + Alias for channel 11 WRITE_ADDR register + CH11_AL1_WRITE_ADDR + 0x00000000 + + + read-only + 0x02dc + Alias for channel 11 TRANS_COUNT register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH11_AL1_TRANS_COUNT_TRIG + 0x00000000 + + + read-only + 0x02e0 + Alias for channel 11 CTRL register + CH11_AL2_CTRL + 0x00000000 + + + read-only + 0x02e4 + Alias for channel 11 TRANS_COUNT register + CH11_AL2_TRANS_COUNT + 0x00000000 + + + read-only + 0x02e8 + Alias for channel 11 READ_ADDR register + CH11_AL2_READ_ADDR + 0x00000000 + + + read-only + 0x02ec + Alias for channel 11 WRITE_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH11_AL2_WRITE_ADDR_TRIG + 0x00000000 + + + read-only + 0x02f0 + Alias for channel 11 CTRL register + CH11_AL3_CTRL + 0x00000000 + + + read-only + 0x02f4 + Alias for channel 11 WRITE_ADDR register + CH11_AL3_WRITE_ADDR + 0x00000000 + + + read-only + 0x02f8 + Alias for channel 11 TRANS_COUNT register + CH11_AL3_TRANS_COUNT + 0x00000000 + + + read-only + 0x02fc + Alias for channel 11 READ_ADDR register\n + This is a trigger register (0xc). Writing a nonzero value will\n + reload the channel counter and start the channel. + CH11_AL3_READ_ADDR_TRIG + 0x00000000 + + + 0x0400 + Interrupt Status (raw) + + + read-only + [15:0] + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + INTR + + + INTR + 0x00000000 + + + 0x0404 + Interrupt Enables for IRQ 0 + + + read-write + [15:0] + Set bit n to pass interrupts from channel n to DMA IRQ 0. + INTE0 + + + INTE0 + 0x00000000 + + + 0x0408 + Force Interrupts + + + read-write + [15:0] + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + INTF0 + + + INTF0 + 0x00000000 + + + 0x040c + Interrupt Status for IRQ 0 + + + read-write + [15:0] + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n + Channel interrupts can be cleared by writing a bit mask here. + oneToClear + INTS0 + + + INTS0 + 0x00000000 + + + 0x0414 + Interrupt Enables for IRQ 1 + + + read-write + [15:0] + Set bit n to pass interrupts from channel n to DMA IRQ 1. + INTE1 + + + INTE1 + 0x00000000 + + + 0x0418 + Force Interrupts for IRQ 1 + + + read-write + [15:0] + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + INTF1 + + + INTF1 + 0x00000000 + + + 0x041c + Interrupt Status (masked) for IRQ 1 + + + read-write + [15:0] + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n + Channel interrupts can be cleared by writing a bit mask here. + oneToClear + INTS1 + + + INTS1 + 0x00000000 + + + 0x0420 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER0 + 0x00000000 + + + 0x0424 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER1 + 0x00000000 + + + 0x0428 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER2 + 0x00000000 + + + 0x042c + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER3 + 0x00000000 + + + 0x0430 + Trigger one or more channels simultaneously + + + read-write + [15:0] + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + clear + MULTI_CHAN_TRIGGER + + + MULTI_CHAN_TRIGGER + 0x00000000 + + + 0x0434 + Sniffer Control + + + read-write + [11:11] + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + OUT_INV + + + read-write + [10:10] + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + OUT_REV + + + read-write + [9:9] + Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + BSWAP + + + read-write + [8:5] + + + Calculate a CRC-32 (IEEE802.3 polynomial) + CRC32 + 0 + + + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + CRC32R + 1 + + + Calculate a CRC-16-CCITT + CRC16 + 2 + + + Calculate a CRC-16-CCITT with bit reversed data + CRC16R + 3 + + + XOR reduction over all data. == 1 if the total 1 population count is odd. + EVEN + 14 + + + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + SUM + 15 + + + CALC + + + read-write + [4:1] + DMA channel for Sniffer to observe + DMACH + + + read-write + [0:0] + Enable sniffer + EN + + + SNIFF_CTRL + 0x00000000 + + + read-write + 0x0438 + Data accumulator for sniff hardware\n + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + SNIFF_DATA + 0x00000000 + + + 0x0440 + Debug RAF, WAF, TDF levels + + + read-only + [23:16] + Current Read-Address-FIFO fill level + RAF_LVL + + + read-only + [15:8] + Current Write-Address-FIFO fill level + WAF_LVL + + + read-only + [7:0] + Current Transfer-Data-FIFO fill level + TDF_LVL + + + FIFO_LEVELS + 0x00000000 + + + 0x0444 + Abort an in-progress transfer sequence on one or more channels + + + read-write + [15:0] + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + clear + CHAN_ABORT + + + CHAN_ABORT + 0x00000000 + + + 0x0448 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + + + read-only + [4:0] + N_CHANNELS + + + N_CHANNELS + 0x00000000 + + + 0x0800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH0_DBG_CTDREQ + + + CH0_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH0_DBG_TCR + 0x00000000 + + + 0x0840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH1_DBG_CTDREQ + + + CH1_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH1_DBG_TCR + 0x00000000 + + + 0x0880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH2_DBG_CTDREQ + + + CH2_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH2_DBG_TCR + 0x00000000 + + + 0x08c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH3_DBG_CTDREQ + + + CH3_DBG_CTDREQ + 0x00000000 + + + read-only + 0x08c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH3_DBG_TCR + 0x00000000 + + + 0x0900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH4_DBG_CTDREQ + + + CH4_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH4_DBG_TCR + 0x00000000 + + + 0x0940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH5_DBG_CTDREQ + + + CH5_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH5_DBG_TCR + 0x00000000 + + + 0x0980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH6_DBG_CTDREQ + + + CH6_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH6_DBG_TCR + 0x00000000 + + + 0x09c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH7_DBG_CTDREQ + + + CH7_DBG_CTDREQ + 0x00000000 + + + read-only + 0x09c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH7_DBG_TCR + 0x00000000 + + + 0x0a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH8_DBG_CTDREQ + + + CH8_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH8_DBG_TCR + 0x00000000 + + + 0x0a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH9_DBG_CTDREQ + + + CH9_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH9_DBG_TCR + 0x00000000 + + + 0x0a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH10_DBG_CTDREQ + + + CH10_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH10_DBG_TCR + 0x00000000 + + + 0x0ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + + + read-only + [5:0] + CH11_DBG_CTDREQ + + + CH11_DBG_CTDREQ + 0x00000000 + + + read-only + 0x0ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + CH11_DBG_TCR + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x50110000 + USB FS/LS controller device registers + + USBCTRL_IRQ + 5 + + USBCTRL_REGS + + + 0x0000 + Device address and endpoint control + + + read-write + [19:16] + Device endpoint to send data to. Only valid for HOST mode. + ENDPOINT + + + read-write + [6:0] + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + ADDRESS + + + ADDR_ENDP + 0x00000000 + + + 0x0004 + Interrupt endpoint 1. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP1 + 0x00000000 + + + 0x0008 + Interrupt endpoint 2. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP2 + 0x00000000 + + + 0x000c + Interrupt endpoint 3. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP3 + 0x00000000 + + + 0x0010 + Interrupt endpoint 4. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP4 + 0x00000000 + + + 0x0014 + Interrupt endpoint 5. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP5 + 0x00000000 + + + 0x0018 + Interrupt endpoint 6. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP6 + 0x00000000 + + + 0x001c + Interrupt endpoint 7. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP7 + 0x00000000 + + + 0x0020 + Interrupt endpoint 8. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP8 + 0x00000000 + + + 0x0024 + Interrupt endpoint 9. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP9 + 0x00000000 + + + 0x0028 + Interrupt endpoint 10. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP10 + 0x00000000 + + + 0x002c + Interrupt endpoint 11. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP11 + 0x00000000 + + + 0x0030 + Interrupt endpoint 12. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP12 + 0x00000000 + + + 0x0034 + Interrupt endpoint 13. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP13 + 0x00000000 + + + 0x0038 + Interrupt endpoint 14. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP14 + 0x00000000 + + + 0x003c + Interrupt endpoint 15. Only valid for HOST mode. + + + read-write + [26:26] + Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE + + + read-write + [25:25] + Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR + + + read-write + [19:16] + Endpoint number of the interrupt endpoint + ENDPOINT + + + read-write + [6:0] + Device address + ADDRESS + + + ADDR_ENDP15 + 0x00000000 + + + 0x0040 + Main control register + + + read-write + [31:31] + Reduced timings for simulation + SIM_TIMING + + + read-write + [1:1] + Device mode = 0, Host mode = 1 + HOST_NDEVICE + + + read-write + [0:0] + Enable controller + CONTROLLER_EN + + + MAIN_CTRL + 0x00000000 + + + 0x0044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + + + write-only + [10:0] + COUNT + + + SOF_WR + 0x00000000 + + + 0x0048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + + + read-only + [10:0] + COUNT + + + SOF_RD + 0x00000000 + + + 0x004c + SIE control register + + + read-write + [31:31] + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + EP0_INT_STALL + + + read-write + [30:30] + Device: EP0 single buffered = 0, double buffered = 1 + EP0_DOUBLE_BUF + + + read-write + [29:29] + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + EP0_INT_1BUF + + + read-write + [28:28] + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + EP0_INT_2BUF + + + read-write + [27:27] + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + EP0_INT_NAK + + + read-write + [26:26] + Direct bus drive enable + DIRECT_EN + + + read-write + [25:25] + Direct control of DP + DIRECT_DP + + + read-write + [24:24] + Direct control of DM + DIRECT_DM + + + read-write + [18:18] + Power down bus transceiver + TRANSCEIVER_PD + + + read-write + [17:17] + Device: Pull-up strength (0=1K2, 1=2k3) + RPU_OPT + + + read-write + [16:16] + Device: Enable pull up resistor + PULLUP_EN + + + read-write + [15:15] + Host: Enable pull down resistors + PULLDOWN_EN + + + read-write + [13:13] + Host: Reset bus + clear + RESET_BUS + + + read-write + [12:12] + Device: Remote wakeup. Device can initiate its own resume after suspend. + clear + RESUME + + + read-write + [11:11] + Host: Enable VBUS + VBUS_EN + + + read-write + [10:10] + Host: Enable keep alive packet (for low speed bus) + KEEP_ALIVE_EN + + + read-write + [9:9] + Host: Enable SOF generation (for full speed bus) + SOF_EN + + + read-write + [8:8] + Host: Delay packet(s) until after SOF + SOF_SYNC + + + read-write + [6:6] + Host: Preable enable for LS device on FS hub + PREAMBLE_EN + + + read-write + [4:4] + Host: Stop transaction + clear + STOP_TRANS + + + read-write + [3:3] + Host: Receive transaction (IN to host) + RECEIVE_DATA + + + read-write + [2:2] + Host: Send transaction (OUT from host) + SEND_DATA + + + read-write + [1:1] + Host: Send Setup packet + SEND_SETUP + + + read-write + [0:0] + Host: Start transaction + clear + START_TRANS + + + SIE_CTRL + 0x00000000 + + + 0x0050 + SIE status register + + + read-write + [31:31] + Data Sequence Error.\n\n + The device can raise a sequence error in the following conditions:\n\n + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n + The host can raise a data sequence error in the following conditions:\n\n + * An IN packet from the device has the wrong data PID + oneToClear + DATA_SEQ_ERROR + + + read-write + [30:30] + ACK received. Raised by both host and device. + oneToClear + ACK_REC + + + read-write + [29:29] + Host: STALL received + oneToClear + STALL_REC + + + read-write + [28:28] + Host: NAK received + oneToClear + NAK_REC + + + read-write + [27:27] + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + oneToClear + RX_TIMEOUT + + + read-write + [26:26] + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + oneToClear + RX_OVERFLOW + + + read-write + [25:25] + Bit Stuff Error. Raised by the Serial RX engine. + oneToClear + BIT_STUFF_ERROR + + + read-write + [24:24] + CRC Error. Raised by the Serial RX engine. + oneToClear + CRC_ERROR + + + read-write + [19:19] + Device: bus reset received + oneToClear + BUS_RESET + + + read-write + [18:18] + Transaction complete.\n\n + Raised by device if:\n\n + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n + Raised by host if:\n\n + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + oneToClear + TRANS_COMPLETE + + + read-write + [17:17] + Device: Setup packet received + oneToClear + SETUP_REC + + + read-only + [16:16] + Device: connected + CONNECTED + + + read-write + [11:11] + Host: Device has initiated a remote resume. Device: host has initiated a resume. + oneToClear + RESUME + + + read-only + [10:10] + VBUS over current detected + VBUS_OVER_CURR + + + read-only + [9:8] + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + SPEED + + + read-only + [4:4] + Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + SUSPENDED + + + read-only + [3:2] + USB bus line state + LINE_STATE + + + read-only + [0:0] + Device: VBUS Detected + VBUS_DETECTED + + + SIE_STATUS + 0x00000000 + + + 0x0054 + interrupt endpoint control register + + + read-write + [15:1] + Host: Enable interrupt endpoint 1 -> 15 + INT_EP_ACTIVE + + + INT_EP_CTRL + 0x00000000 + + + 0x0058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + + + read-only + [31:31] + EP15_OUT + + + read-only + [30:30] + EP15_IN + + + read-only + [29:29] + EP14_OUT + + + read-only + [28:28] + EP14_IN + + + read-only + [27:27] + EP13_OUT + + + read-only + [26:26] + EP13_IN + + + read-only + [25:25] + EP12_OUT + + + read-only + [24:24] + EP12_IN + + + read-only + [23:23] + EP11_OUT + + + read-only + [22:22] + EP11_IN + + + read-only + [21:21] + EP10_OUT + + + read-only + [20:20] + EP10_IN + + + read-only + [19:19] + EP9_OUT + + + read-only + [18:18] + EP9_IN + + + read-only + [17:17] + EP8_OUT + + + read-only + [16:16] + EP8_IN + + + read-only + [15:15] + EP7_OUT + + + read-only + [14:14] + EP7_IN + + + read-only + [13:13] + EP6_OUT + + + read-only + [12:12] + EP6_IN + + + read-only + [11:11] + EP5_OUT + + + read-only + [10:10] + EP5_IN + + + read-only + [9:9] + EP4_OUT + + + read-only + [8:8] + EP4_IN + + + read-only + [7:7] + EP3_OUT + + + read-only + [6:6] + EP3_IN + + + read-only + [5:5] + EP2_OUT + + + read-only + [4:4] + EP2_IN + + + read-only + [3:3] + EP1_OUT + + + read-only + [2:2] + EP1_IN + + + read-only + [1:1] + EP0_OUT + + + read-only + [0:0] + EP0_IN + + + BUFF_STATUS + 0x00000000 + + + 0x005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + + + read-only + [31:31] + EP15_OUT + + + read-only + [30:30] + EP15_IN + + + read-only + [29:29] + EP14_OUT + + + read-only + [28:28] + EP14_IN + + + read-only + [27:27] + EP13_OUT + + + read-only + [26:26] + EP13_IN + + + read-only + [25:25] + EP12_OUT + + + read-only + [24:24] + EP12_IN + + + read-only + [23:23] + EP11_OUT + + + read-only + [22:22] + EP11_IN + + + read-only + [21:21] + EP10_OUT + + + read-only + [20:20] + EP10_IN + + + read-only + [19:19] + EP9_OUT + + + read-only + [18:18] + EP9_IN + + + read-only + [17:17] + EP8_OUT + + + read-only + [16:16] + EP8_IN + + + read-only + [15:15] + EP7_OUT + + + read-only + [14:14] + EP7_IN + + + read-only + [13:13] + EP6_OUT + + + read-only + [12:12] + EP6_IN + + + read-only + [11:11] + EP5_OUT + + + read-only + [10:10] + EP5_IN + + + read-only + [9:9] + EP4_OUT + + + read-only + [8:8] + EP4_IN + + + read-only + [7:7] + EP3_OUT + + + read-only + [6:6] + EP3_IN + + + read-only + [5:5] + EP2_OUT + + + read-only + [4:4] + EP2_IN + + + read-only + [3:3] + EP1_OUT + + + read-only + [2:2] + EP1_IN + + + read-only + [1:1] + EP0_OUT + + + read-only + [0:0] + EP0_IN + + + BUFF_CPU_SHOULD_HANDLE + 0x00000000 + + + 0x0060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + + + read-write + [31:31] + EP15_OUT + + + read-write + [30:30] + EP15_IN + + + read-write + [29:29] + EP14_OUT + + + read-write + [28:28] + EP14_IN + + + read-write + [27:27] + EP13_OUT + + + read-write + [26:26] + EP13_IN + + + read-write + [25:25] + EP12_OUT + + + read-write + [24:24] + EP12_IN + + + read-write + [23:23] + EP11_OUT + + + read-write + [22:22] + EP11_IN + + + read-write + [21:21] + EP10_OUT + + + read-write + [20:20] + EP10_IN + + + read-write + [19:19] + EP9_OUT + + + read-write + [18:18] + EP9_IN + + + read-write + [17:17] + EP8_OUT + + + read-write + [16:16] + EP8_IN + + + read-write + [15:15] + EP7_OUT + + + read-write + [14:14] + EP7_IN + + + read-write + [13:13] + EP6_OUT + + + read-write + [12:12] + EP6_IN + + + read-write + [11:11] + EP5_OUT + + + read-write + [10:10] + EP5_IN + + + read-write + [9:9] + EP4_OUT + + + read-write + [8:8] + EP4_IN + + + read-write + [7:7] + EP3_OUT + + + read-write + [6:6] + EP3_IN + + + read-write + [5:5] + EP2_OUT + + + read-write + [4:4] + EP2_IN + + + read-write + [3:3] + EP1_OUT + + + read-write + [2:2] + EP1_IN + + + read-write + [1:1] + EP0_OUT + + + read-write + [0:0] + EP0_IN + + + EP_ABORT + 0x00000000 + + + 0x0064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + + + read-write + [31:31] + oneToClear + EP15_OUT + + + read-write + [30:30] + oneToClear + EP15_IN + + + read-write + [29:29] + oneToClear + EP14_OUT + + + read-write + [28:28] + oneToClear + EP14_IN + + + read-write + [27:27] + oneToClear + EP13_OUT + + + read-write + [26:26] + oneToClear + EP13_IN + + + read-write + [25:25] + oneToClear + EP12_OUT + + + read-write + [24:24] + oneToClear + EP12_IN + + + read-write + [23:23] + oneToClear + EP11_OUT + + + read-write + [22:22] + oneToClear + EP11_IN + + + read-write + [21:21] + oneToClear + EP10_OUT + + + read-write + [20:20] + oneToClear + EP10_IN + + + read-write + [19:19] + oneToClear + EP9_OUT + + + read-write + [18:18] + oneToClear + EP9_IN + + + read-write + [17:17] + oneToClear + EP8_OUT + + + read-write + [16:16] + oneToClear + EP8_IN + + + read-write + [15:15] + oneToClear + EP7_OUT + + + read-write + [14:14] + oneToClear + EP7_IN + + + read-write + [13:13] + oneToClear + EP6_OUT + + + read-write + [12:12] + oneToClear + EP6_IN + + + read-write + [11:11] + oneToClear + EP5_OUT + + + read-write + [10:10] + oneToClear + EP5_IN + + + read-write + [9:9] + oneToClear + EP4_OUT + + + read-write + [8:8] + oneToClear + EP4_IN + + + read-write + [7:7] + oneToClear + EP3_OUT + + + read-write + [6:6] + oneToClear + EP3_IN + + + read-write + [5:5] + oneToClear + EP2_OUT + + + read-write + [4:4] + oneToClear + EP2_IN + + + read-write + [3:3] + oneToClear + EP1_OUT + + + read-write + [2:2] + oneToClear + EP1_IN + + + read-write + [1:1] + oneToClear + EP0_OUT + + + read-write + [0:0] + oneToClear + EP0_IN + + + EP_ABORT_DONE + 0x00000000 + + + 0x0068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + + + read-write + [1:1] + EP0_OUT + + + read-write + [0:0] + EP0_IN + + + EP_STALL_ARM + 0x00000000 + + + 0x006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + + + read-write + [25:16] + NAK polling interval for a full speed device + DELAY_FS + + + read-write + [9:0] + NAK polling interval for a low speed device + DELAY_LS + + + NAK_POLL + 0x00100010 + + + 0x0070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + + + read-write + [31:31] + oneToClear + EP15_OUT + + + read-write + [30:30] + oneToClear + EP15_IN + + + read-write + [29:29] + oneToClear + EP14_OUT + + + read-write + [28:28] + oneToClear + EP14_IN + + + read-write + [27:27] + oneToClear + EP13_OUT + + + read-write + [26:26] + oneToClear + EP13_IN + + + read-write + [25:25] + oneToClear + EP12_OUT + + + read-write + [24:24] + oneToClear + EP12_IN + + + read-write + [23:23] + oneToClear + EP11_OUT + + + read-write + [22:22] + oneToClear + EP11_IN + + + read-write + [21:21] + oneToClear + EP10_OUT + + + read-write + [20:20] + oneToClear + EP10_IN + + + read-write + [19:19] + oneToClear + EP9_OUT + + + read-write + [18:18] + oneToClear + EP9_IN + + + read-write + [17:17] + oneToClear + EP8_OUT + + + read-write + [16:16] + oneToClear + EP8_IN + + + read-write + [15:15] + oneToClear + EP7_OUT + + + read-write + [14:14] + oneToClear + EP7_IN + + + read-write + [13:13] + oneToClear + EP6_OUT + + + read-write + [12:12] + oneToClear + EP6_IN + + + read-write + [11:11] + oneToClear + EP5_OUT + + + read-write + [10:10] + oneToClear + EP5_IN + + + read-write + [9:9] + oneToClear + EP4_OUT + + + read-write + [8:8] + oneToClear + EP4_IN + + + read-write + [7:7] + oneToClear + EP3_OUT + + + read-write + [6:6] + oneToClear + EP3_IN + + + read-write + [5:5] + oneToClear + EP2_OUT + + + read-write + [4:4] + oneToClear + EP2_IN + + + read-write + [3:3] + oneToClear + EP1_OUT + + + read-write + [2:2] + oneToClear + EP1_IN + + + read-write + [1:1] + oneToClear + EP0_OUT + + + read-write + [0:0] + oneToClear + EP0_IN + + + EP_STATUS_STALL_NAK + 0x00000000 + + + 0x0074 + Where to connect the USB controller. Should be to_phy by default. + + + read-write + [3:3] + SOFTCON + + + read-write + [2:2] + TO_DIGITAL_PAD + + + read-write + [1:1] + TO_EXTPHY + + + read-write + [0:0] + TO_PHY + + + USB_MUXING + 0x00000000 + + + 0x0078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + + + read-write + [5:5] + OVERCURR_DETECT_EN + + + read-write + [4:4] + OVERCURR_DETECT + + + read-write + [3:3] + VBUS_DETECT_OVERRIDE_EN + + + read-write + [2:2] + VBUS_DETECT + + + read-write + [1:1] + VBUS_EN_OVERRIDE_EN + + + read-write + [0:0] + VBUS_EN + + + USB_PWR + 0x00000000 + + + 0x007c + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + + + read-only + [22:22] + DM over voltage + DM_OVV + + + read-only + [21:21] + DP over voltage + DP_OVV + + + read-only + [20:20] + DM overcurrent + DM_OVCN + + + read-only + [19:19] + DP overcurrent + DP_OVCN + + + read-only + [18:18] + DPM pin state + RX_DM + + + read-only + [17:17] + DPP pin state + RX_DP + + + read-only + [16:16] + Differential RX + RX_DD + + + read-write + [15:15] + TX_DIFFMODE=0: Single ended mode\n + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + TX_DIFFMODE + + + read-write + [14:14] + TX_FSSLEW=0: Low speed slew rate\n + TX_FSSLEW=1: Full speed slew rate + TX_FSSLEW + + + read-write + [13:13] + TX power down override (if override enable is set). 1 = powered down. + TX_PD + + + read-write + [12:12] + RX power down override (if override enable is set). 1 = powered down. + RX_PD + + + read-write + [11:11] + Output data. TX_DIFFMODE=1, Ignored\n + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + TX_DM + + + read-write + [10:10] + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + TX_DP + + + read-write + [9:9] + Output enable. If TX_DIFFMODE=1, Ignored.\n + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + TX_DM_OE + + + read-write + [8:8] + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + TX_DP_OE + + + read-write + [6:6] + DM pull down enable + DM_PULLDN_EN + + + read-write + [5:5] + DM pull up enable + DM_PULLUP_EN + + + read-write + [4:4] + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + DM_PULLUP_HISEL + + + read-write + [2:2] + DP pull down enable + DP_PULLDN_EN + + + read-write + [1:1] + DP pull up enable + DP_PULLUP_EN + + + read-write + [0:0] + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + DP_PULLUP_HISEL + + + USBPHY_DIRECT + 0x00000000 + + + 0x0080 + Override enable for each control in usbphy_direct + + + read-write + [15:15] + TX_DIFFMODE_OVERRIDE_EN + + + read-write + [12:12] + DM_PULLUP_OVERRIDE_EN + + + read-write + [11:11] + TX_FSSLEW_OVERRIDE_EN + + + read-write + [10:10] + TX_PD_OVERRIDE_EN + + + read-write + [9:9] + RX_PD_OVERRIDE_EN + + + read-write + [8:8] + TX_DM_OVERRIDE_EN + + + read-write + [7:7] + TX_DP_OVERRIDE_EN + + + read-write + [6:6] + TX_DM_OE_OVERRIDE_EN + + + read-write + [5:5] + TX_DP_OE_OVERRIDE_EN + + + read-write + [4:4] + DM_PULLDN_EN_OVERRIDE_EN + + + read-write + [3:3] + DP_PULLDN_EN_OVERRIDE_EN + + + read-write + [2:2] + DP_PULLUP_EN_OVERRIDE_EN + + + read-write + [1:1] + DM_PULLUP_HISEL_OVERRIDE_EN + + + read-write + [0:0] + DP_PULLUP_HISEL_OVERRIDE_EN + + + USBPHY_DIRECT_OVERRIDE + 0x00000000 + + + 0x0084 + Used to adjust trim values of USB phy pull down resistors. + + + read-write + [12:8] + Value to drive to USB PHY\n + DM pulldown resistor trim control\n + Experimental data suggests that the reset value will work, but this register allows adjustment if required + DM_PULLDN_TRIM + + + read-write + [4:0] + Value to drive to USB PHY\n + DP pulldown resistor trim control\n + Experimental data suggests that the reset value will work, but this register allows adjustment if required + DP_PULLDN_TRIM + + + USBPHY_TRIM + 0x00001f1f + + + 0x008c + Raw Interrupts + + + read-only + [19:19] + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK + + + read-only + [18:18] + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + ABORT_DONE + + + read-only + [17:17] + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + DEV_SOF + + + read-only + [16:16] + Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ + + + read-only + [15:15] + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST + + + read-only + [14:14] + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND + + + read-only + [13:13] + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS + + + read-only + [12:12] + Source: SIE_STATUS.BUS_RESET + BUS_RESET + + + read-only + [11:11] + Source: SIE_STATUS.VBUS_DETECT + VBUS_DETECT + + + read-only + [10:10] + Source: SIE_STATUS.STALL_REC + STALL + + + read-only + [9:9] + Source: SIE_STATUS.CRC_ERROR + ERROR_CRC + + + read-only + [8:8] + Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF + + + read-only + [7:7] + Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW + + + read-only + [6:6] + Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT + + + read-only + [5:5] + Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ + + + read-only + [4:4] + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + BUFF_STATUS + + + read-only + [3:3] + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + TRANS_COMPLETE + + + read-only + [2:2] + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + HOST_SOF + + + read-only + [1:1] + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + HOST_RESUME + + + read-only + [0:0] + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS + + + INTR + 0x00000000 + + + 0x0090 + Interrupt Enable + + + read-write + [19:19] + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK + + + read-write + [18:18] + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + ABORT_DONE + + + read-write + [17:17] + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + DEV_SOF + + + read-write + [16:16] + Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ + + + read-write + [15:15] + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST + + + read-write + [14:14] + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND + + + read-write + [13:13] + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS + + + read-write + [12:12] + Source: SIE_STATUS.BUS_RESET + BUS_RESET + + + read-write + [11:11] + Source: SIE_STATUS.VBUS_DETECT + VBUS_DETECT + + + read-write + [10:10] + Source: SIE_STATUS.STALL_REC + STALL + + + read-write + [9:9] + Source: SIE_STATUS.CRC_ERROR + ERROR_CRC + + + read-write + [8:8] + Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF + + + read-write + [7:7] + Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW + + + read-write + [6:6] + Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT + + + read-write + [5:5] + Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ + + + read-write + [4:4] + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + BUFF_STATUS + + + read-write + [3:3] + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + TRANS_COMPLETE + + + read-write + [2:2] + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + HOST_SOF + + + read-write + [1:1] + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + HOST_RESUME + + + read-write + [0:0] + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS + + + INTE + 0x00000000 + + + 0x0094 + Interrupt Force + + + read-write + [19:19] + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK + + + read-write + [18:18] + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + ABORT_DONE + + + read-write + [17:17] + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + DEV_SOF + + + read-write + [16:16] + Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ + + + read-write + [15:15] + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST + + + read-write + [14:14] + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND + + + read-write + [13:13] + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS + + + read-write + [12:12] + Source: SIE_STATUS.BUS_RESET + BUS_RESET + + + read-write + [11:11] + Source: SIE_STATUS.VBUS_DETECT + VBUS_DETECT + + + read-write + [10:10] + Source: SIE_STATUS.STALL_REC + STALL + + + read-write + [9:9] + Source: SIE_STATUS.CRC_ERROR + ERROR_CRC + + + read-write + [8:8] + Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF + + + read-write + [7:7] + Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW + + + read-write + [6:6] + Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT + + + read-write + [5:5] + Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ + + + read-write + [4:4] + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + BUFF_STATUS + + + read-write + [3:3] + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + TRANS_COMPLETE + + + read-write + [2:2] + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + HOST_SOF + + + read-write + [1:1] + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + HOST_RESUME + + + read-write + [0:0] + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS + + + INTF + 0x00000000 + + + 0x0098 + Interrupt status after masking & forcing + + + read-only + [19:19] + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK + + + read-only + [18:18] + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + ABORT_DONE + + + read-only + [17:17] + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + DEV_SOF + + + read-only + [16:16] + Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ + + + read-only + [15:15] + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST + + + read-only + [14:14] + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND + + + read-only + [13:13] + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS + + + read-only + [12:12] + Source: SIE_STATUS.BUS_RESET + BUS_RESET + + + read-only + [11:11] + Source: SIE_STATUS.VBUS_DETECT + VBUS_DETECT + + + read-only + [10:10] + Source: SIE_STATUS.STALL_REC + STALL + + + read-only + [9:9] + Source: SIE_STATUS.CRC_ERROR + ERROR_CRC + + + read-only + [8:8] + Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF + + + read-only + [7:7] + Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW + + + read-only + [6:6] + Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT + + + read-only + [5:5] + Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ + + + read-only + [4:4] + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + BUFF_STATUS + + + read-only + [3:3] + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + TRANS_COMPLETE + + + read-only + [2:2] + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + HOST_SOF + + + read-only + [1:1] + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + HOST_RESUME + + + read-only + [0:0] + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS + + + INTS + 0x00000000 + + + 32 + 1 + + + + 0 + 0x1000 + registers + + 0x50200000 + Programmable IO block + + PIO0_IRQ_0 + 7 + + + PIO0_IRQ_1 + 8 + + PIO0 + + + 0x0000 + PIO control register + + + read-write + [11:8] + Force clock dividers to restart their count and clear fractional\n + accumulators. Restart multiple dividers to synchronise them. + clear + CLKDIV_RESTART + + + read-write + [7:4] + Clear internal SM state which is otherwise difficult to access\n + (e.g. shift counters). Self-clearing. + clear + SM_RESTART + + + read-write + [3:0] + Enable state machine + SM_ENABLE + + + CTRL + 0x00000000 + + + 0x0004 + FIFO status register + + + read-only + [27:24] + State machine TX FIFO is empty + TXEMPTY + + + read-only + [19:16] + State machine TX FIFO is full + TXFULL + + + read-only + [11:8] + State machine RX FIFO is empty + RXEMPTY + + + read-only + [3:0] + State machine RX FIFO is full + RXFULL + + + FSTAT + 0x0f000f00 + + + 0x0008 + FIFO debug register + + + read-write + [27:24] + State machine has stalled on empty TX FIFO. Write 1 to clear. + oneToClear + TXSTALL + + + read-write + [19:16] + TX FIFO overflow has occurred. Write 1 to clear. + oneToClear + TXOVER + + + read-write + [11:8] + RX FIFO underflow has occurred. Write 1 to clear. + oneToClear + RXUNDER + + + read-write + [3:0] + State machine has stalled on full RX FIFO. Write 1 to clear. + oneToClear + RXSTALL + + + FDEBUG + 0x00000000 + + + 0x000c + FIFO levels + + + read-only + [31:28] + RX3 + + + read-only + [27:24] + TX3 + + + read-only + [23:20] + RX2 + + + read-only + [19:16] + TX2 + + + read-only + [15:12] + RX1 + + + read-only + [11:8] + TX1 + + + read-only + [7:4] + RX0 + + + read-only + [3:0] + TX0 + + + FLEVEL + 0x00000000 + + + write-only + 0x0010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + TXF0 + 0x00000000 + + + write-only + 0x0014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + TXF1 + 0x00000000 + + + write-only + 0x0018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + TXF2 + 0x00000000 + + + write-only + 0x001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + TXF3 + 0x00000000 + + + read-only + 0x0020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + RXF0 + 0x00000000 + + + read-only + 0x0024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + RXF1 + 0x00000000 + + + read-only + 0x0028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + RXF2 + 0x00000000 + + + read-only + 0x002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + RXF3 + 0x00000000 + + + 0x0030 + Interrupt request register. Write 1 to clear + + + read-write + [7:0] + oneToClear + IRQ + + + IRQ + 0x00000000 + + + 0x0034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.\n + Note this is different to the INTF register: writing here affects PIO internal\n + state. INTF just asserts the processor-facing IRQ signal for testing ISRs,\n + and is not visible to the state machines. + + + write-only + [7:0] + IRQ_FORCE + + + IRQ_FORCE + 0x00000000 + + + read-write + 0x0038 + There is a 2-flipflop synchronizer on each GPIO input, which protects\n + PIO logic from metastabilities. This increases input delay, and for fast\n + synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n + Each bit in this register corresponds to one GPIO.\n + 0 -> input is synchronized (default)\n + 1 -> synchronizer is bypassed\n + If in doubt, leave this register as all zeroes. + INPUT_SYNC_BYPASS + 0x00000000 + + + read-only + 0x003c + Read to sample the pad output values PIO is currently driving to the GPIOs. + DBG_PADOUT + 0x00000000 + + + read-only + 0x0040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. + DBG_PADOE + 0x00000000 + + + 0x0044 + The PIO hardware has some free parameters that may vary between chip products.\n + These should be provided in the chip datasheet, but are also exposed here. + + + read-only + [21:16] + The size of the instruction memory, measured in units of one instruction + IMEM_SIZE + + + read-only + [11:8] + The number of state machines this PIO instance is equipped with. + SM_COUNT + + + read-only + [5:0] + The depth of the state machine TX/RX FIFOs, measured in words.\n + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n + this depth. + FIFO_DEPTH + + + DBG_CFGINFO + 0x00000000 + + + 0x0048 + Write-only access to instruction memory location 0 + + + read-write + [15:0] + INSTR_MEM0 + + + INSTR_MEM0 + 0x00000000 + + + 0x004c + Write-only access to instruction memory location 1 + + + read-write + [15:0] + INSTR_MEM1 + + + INSTR_MEM1 + 0x00000000 + + + 0x0050 + Write-only access to instruction memory location 2 + + + read-write + [15:0] + INSTR_MEM2 + + + INSTR_MEM2 + 0x00000000 + + + 0x0054 + Write-only access to instruction memory location 3 + + + read-write + [15:0] + INSTR_MEM3 + + + INSTR_MEM3 + 0x00000000 + + + 0x0058 + Write-only access to instruction memory location 4 + + + read-write + [15:0] + INSTR_MEM4 + + + INSTR_MEM4 + 0x00000000 + + + 0x005c + Write-only access to instruction memory location 5 + + + read-write + [15:0] + INSTR_MEM5 + + + INSTR_MEM5 + 0x00000000 + + + 0x0060 + Write-only access to instruction memory location 6 + + + read-write + [15:0] + INSTR_MEM6 + + + INSTR_MEM6 + 0x00000000 + + + 0x0064 + Write-only access to instruction memory location 7 + + + read-write + [15:0] + INSTR_MEM7 + + + INSTR_MEM7 + 0x00000000 + + + 0x0068 + Write-only access to instruction memory location 8 + + + read-write + [15:0] + INSTR_MEM8 + + + INSTR_MEM8 + 0x00000000 + + + 0x006c + Write-only access to instruction memory location 9 + + + read-write + [15:0] + INSTR_MEM9 + + + INSTR_MEM9 + 0x00000000 + + + 0x0070 + Write-only access to instruction memory location 10 + + + read-write + [15:0] + INSTR_MEM10 + + + INSTR_MEM10 + 0x00000000 + + + 0x0074 + Write-only access to instruction memory location 11 + + + read-write + [15:0] + INSTR_MEM11 + + + INSTR_MEM11 + 0x00000000 + + + 0x0078 + Write-only access to instruction memory location 12 + + + read-write + [15:0] + INSTR_MEM12 + + + INSTR_MEM12 + 0x00000000 + + + 0x007c + Write-only access to instruction memory location 13 + + + read-write + [15:0] + INSTR_MEM13 + + + INSTR_MEM13 + 0x00000000 + + + 0x0080 + Write-only access to instruction memory location 14 + + + read-write + [15:0] + INSTR_MEM14 + + + INSTR_MEM14 + 0x00000000 + + + 0x0084 + Write-only access to instruction memory location 15 + + + read-write + [15:0] + INSTR_MEM15 + + + INSTR_MEM15 + 0x00000000 + + + 0x0088 + Write-only access to instruction memory location 16 + + + read-write + [15:0] + INSTR_MEM16 + + + INSTR_MEM16 + 0x00000000 + + + 0x008c + Write-only access to instruction memory location 17 + + + read-write + [15:0] + INSTR_MEM17 + + + INSTR_MEM17 + 0x00000000 + + + 0x0090 + Write-only access to instruction memory location 18 + + + read-write + [15:0] + INSTR_MEM18 + + + INSTR_MEM18 + 0x00000000 + + + 0x0094 + Write-only access to instruction memory location 19 + + + read-write + [15:0] + INSTR_MEM19 + + + INSTR_MEM19 + 0x00000000 + + + 0x0098 + Write-only access to instruction memory location 20 + + + read-write + [15:0] + INSTR_MEM20 + + + INSTR_MEM20 + 0x00000000 + + + 0x009c + Write-only access to instruction memory location 21 + + + read-write + [15:0] + INSTR_MEM21 + + + INSTR_MEM21 + 0x00000000 + + + 0x00a0 + Write-only access to instruction memory location 22 + + + read-write + [15:0] + INSTR_MEM22 + + + INSTR_MEM22 + 0x00000000 + + + 0x00a4 + Write-only access to instruction memory location 23 + + + read-write + [15:0] + INSTR_MEM23 + + + INSTR_MEM23 + 0x00000000 + + + 0x00a8 + Write-only access to instruction memory location 24 + + + read-write + [15:0] + INSTR_MEM24 + + + INSTR_MEM24 + 0x00000000 + + + 0x00ac + Write-only access to instruction memory location 25 + + + read-write + [15:0] + INSTR_MEM25 + + + INSTR_MEM25 + 0x00000000 + + + 0x00b0 + Write-only access to instruction memory location 26 + + + read-write + [15:0] + INSTR_MEM26 + + + INSTR_MEM26 + 0x00000000 + + + 0x00b4 + Write-only access to instruction memory location 27 + + + read-write + [15:0] + INSTR_MEM27 + + + INSTR_MEM27 + 0x00000000 + + + 0x00b8 + Write-only access to instruction memory location 28 + + + read-write + [15:0] + INSTR_MEM28 + + + INSTR_MEM28 + 0x00000000 + + + 0x00bc + Write-only access to instruction memory location 29 + + + read-write + [15:0] + INSTR_MEM29 + + + INSTR_MEM29 + 0x00000000 + + + 0x00c0 + Write-only access to instruction memory location 30 + + + read-write + [15:0] + INSTR_MEM30 + + + INSTR_MEM30 + 0x00000000 + + + 0x00c4 + Write-only access to instruction memory location 31 + + + read-write + [15:0] + INSTR_MEM31 + + + INSTR_MEM31 + 0x00000000 + + + 0x00c8 + Clock divider register for state machine 0\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + + + read-write + [31:16] + Effective frequency is sysclk/int.\n + Value of 0 is interpreted as max possible value + INT + + + read-write + [15:8] + Fractional part of clock divider + FRAC + + + SM0_CLKDIV + 0x00010000 + + + 0x00cc + Execution/behavioural settings for state machine 0 + + + read-only + [31:31] + An instruction written to SMx_INSTR is stalled, and latched by the\n + state machine. Will clear once the instruction completes. + EXEC_STALLED + + + read-write + [30:30] + If 1, the delay MSB is used as side-set enable, rather than a\n + side-set data bit. This allows instructions to perform side-set optionally,\n + rather than on every instruction. + SIDE_EN + + + read-write + [29:29] + Side-set data is asserted to pin OEs instead of pin values + SIDE_PINDIR + + + read-write + [28:24] + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN + + + read-write + [23:19] + Which data bit to use for inline OUT enable + OUT_EN_SEL + + + read-write + [18:18] + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN + + + read-write + [17:17] + Continuously assert the most recent OUT/SET to the pins + OUT_STICKY + + + read-write + [16:12] + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + WRAP_TOP + + + read-write + [11:7] + After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM + + + read-write + [4:4] + Comparison used for the MOV x, STATUS instruction. + + + All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL + 0 + + + All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL + 1 + + + STATUS_SEL + + + read-write + [3:0] + Comparison level for the MOV x, STATUS instruction + STATUS_N + + + SM0_EXECCTRL + 0x0001f000 + + + 0x00d0 + Control behaviour of the input/output shift registers for state machine 0 + + + read-write + [31:31] + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_RX + + + read-write + [30:30] + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_TX + + + read-write + [29:25] + Number of bits shifted out of TXSR before autopull or conditional pull.\n + Write 0 for value of 32. + PULL_THRESH + + + read-write + [24:20] + Number of bits shifted into RXSR before autopush or conditional push.\n + Write 0 for value of 32. + PUSH_THRESH + + + read-write + [19:19] + 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR + + + read-write + [18:18] + 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR + + + read-write + [17:17] + Pull automatically when the output shift register is emptied + AUTOPULL + + + read-write + [16:16] + Push automatically when the input shift register is filled + AUTOPUSH + + + SM0_SHIFTCTRL + 0x000c0000 + + + 0x00d4 + Current instruction address of state machine 0 + + + read-only + [4:0] + SM0_ADDR + + + SM0_ADDR + 0x00000000 + + + 0x00d8 + Instruction currently being executed by state machine 0\n + Write to execute an instruction immediately (including jumps) and then resume execution. + + + read-write + [15:0] + SM0_INSTR + + + SM0_INSTR + 0x00000000 + + + 0x00dc + State machine pin control + + + read-write + [31:29] + The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + SIDESET_COUNT + + + read-write + [28:26] + The number of pins asserted by a SET. Max of 5 + SET_COUNT + + + read-write + [25:20] + The number of pins asserted by an OUT. Value of 0 -> 32 pins + OUT_COUNT + + + read-write + [19:15] + The virtual pin corresponding to IN bit 0 + IN_BASE + + + read-write + [14:10] + The virtual pin corresponding to delay field bit 0 + SIDESET_BASE + + + read-write + [9:5] + The virtual pin corresponding to SET bit 0 + SET_BASE + + + read-write + [4:0] + The virtual pin corresponding to OUT bit 0 + OUT_BASE + + + SM0_PINCTRL + 0x14000000 + + + 0x00e0 + Clock divider register for state machine 1\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + + + read-write + [31:16] + Effective frequency is sysclk/int.\n + Value of 0 is interpreted as max possible value + INT + + + read-write + [15:8] + Fractional part of clock divider + FRAC + + + SM1_CLKDIV + 0x00010000 + + + 0x00e4 + Execution/behavioural settings for state machine 1 + + + read-only + [31:31] + An instruction written to SMx_INSTR is stalled, and latched by the\n + state machine. Will clear once the instruction completes. + EXEC_STALLED + + + read-write + [30:30] + If 1, the delay MSB is used as side-set enable, rather than a\n + side-set data bit. This allows instructions to perform side-set optionally,\n + rather than on every instruction. + SIDE_EN + + + read-write + [29:29] + Side-set data is asserted to pin OEs instead of pin values + SIDE_PINDIR + + + read-write + [28:24] + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN + + + read-write + [23:19] + Which data bit to use for inline OUT enable + OUT_EN_SEL + + + read-write + [18:18] + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN + + + read-write + [17:17] + Continuously assert the most recent OUT/SET to the pins + OUT_STICKY + + + read-write + [16:12] + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + WRAP_TOP + + + read-write + [11:7] + After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM + + + read-write + [4:4] + Comparison used for the MOV x, STATUS instruction. + + + All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL + 0 + + + All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL + 1 + + + STATUS_SEL + + + read-write + [3:0] + Comparison level for the MOV x, STATUS instruction + STATUS_N + + + SM1_EXECCTRL + 0x0001f000 + + + 0x00e8 + Control behaviour of the input/output shift registers for state machine 1 + + + read-write + [31:31] + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_RX + + + read-write + [30:30] + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_TX + + + read-write + [29:25] + Number of bits shifted out of TXSR before autopull or conditional pull.\n + Write 0 for value of 32. + PULL_THRESH + + + read-write + [24:20] + Number of bits shifted into RXSR before autopush or conditional push.\n + Write 0 for value of 32. + PUSH_THRESH + + + read-write + [19:19] + 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR + + + read-write + [18:18] + 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR + + + read-write + [17:17] + Pull automatically when the output shift register is emptied + AUTOPULL + + + read-write + [16:16] + Push automatically when the input shift register is filled + AUTOPUSH + + + SM1_SHIFTCTRL + 0x000c0000 + + + 0x00ec + Current instruction address of state machine 1 + + + read-only + [4:0] + SM1_ADDR + + + SM1_ADDR + 0x00000000 + + + 0x00f0 + Instruction currently being executed by state machine 1\n + Write to execute an instruction immediately (including jumps) and then resume execution. + + + read-write + [15:0] + SM1_INSTR + + + SM1_INSTR + 0x00000000 + + + 0x00f4 + State machine pin control + + + read-write + [31:29] + The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + SIDESET_COUNT + + + read-write + [28:26] + The number of pins asserted by a SET. Max of 5 + SET_COUNT + + + read-write + [25:20] + The number of pins asserted by an OUT. Value of 0 -> 32 pins + OUT_COUNT + + + read-write + [19:15] + The virtual pin corresponding to IN bit 0 + IN_BASE + + + read-write + [14:10] + The virtual pin corresponding to delay field bit 0 + SIDESET_BASE + + + read-write + [9:5] + The virtual pin corresponding to SET bit 0 + SET_BASE + + + read-write + [4:0] + The virtual pin corresponding to OUT bit 0 + OUT_BASE + + + SM1_PINCTRL + 0x14000000 + + + 0x00f8 + Clock divider register for state machine 2\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + + + read-write + [31:16] + Effective frequency is sysclk/int.\n + Value of 0 is interpreted as max possible value + INT + + + read-write + [15:8] + Fractional part of clock divider + FRAC + + + SM2_CLKDIV + 0x00010000 + + + 0x00fc + Execution/behavioural settings for state machine 2 + + + read-only + [31:31] + An instruction written to SMx_INSTR is stalled, and latched by the\n + state machine. Will clear once the instruction completes. + EXEC_STALLED + + + read-write + [30:30] + If 1, the delay MSB is used as side-set enable, rather than a\n + side-set data bit. This allows instructions to perform side-set optionally,\n + rather than on every instruction. + SIDE_EN + + + read-write + [29:29] + Side-set data is asserted to pin OEs instead of pin values + SIDE_PINDIR + + + read-write + [28:24] + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN + + + read-write + [23:19] + Which data bit to use for inline OUT enable + OUT_EN_SEL + + + read-write + [18:18] + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN + + + read-write + [17:17] + Continuously assert the most recent OUT/SET to the pins + OUT_STICKY + + + read-write + [16:12] + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + WRAP_TOP + + + read-write + [11:7] + After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM + + + read-write + [4:4] + Comparison used for the MOV x, STATUS instruction. + + + All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL + 0 + + + All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL + 1 + + + STATUS_SEL + + + read-write + [3:0] + Comparison level for the MOV x, STATUS instruction + STATUS_N + + + SM2_EXECCTRL + 0x0001f000 + + + 0x0100 + Control behaviour of the input/output shift registers for state machine 2 + + + read-write + [31:31] + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_RX + + + read-write + [30:30] + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_TX + + + read-write + [29:25] + Number of bits shifted out of TXSR before autopull or conditional pull.\n + Write 0 for value of 32. + PULL_THRESH + + + read-write + [24:20] + Number of bits shifted into RXSR before autopush or conditional push.\n + Write 0 for value of 32. + PUSH_THRESH + + + read-write + [19:19] + 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR + + + read-write + [18:18] + 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR + + + read-write + [17:17] + Pull automatically when the output shift register is emptied + AUTOPULL + + + read-write + [16:16] + Push automatically when the input shift register is filled + AUTOPUSH + + + SM2_SHIFTCTRL + 0x000c0000 + + + 0x0104 + Current instruction address of state machine 2 + + + read-only + [4:0] + SM2_ADDR + + + SM2_ADDR + 0x00000000 + + + 0x0108 + Instruction currently being executed by state machine 2\n + Write to execute an instruction immediately (including jumps) and then resume execution. + + + read-write + [15:0] + SM2_INSTR + + + SM2_INSTR + 0x00000000 + + + 0x010c + State machine pin control + + + read-write + [31:29] + The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + SIDESET_COUNT + + + read-write + [28:26] + The number of pins asserted by a SET. Max of 5 + SET_COUNT + + + read-write + [25:20] + The number of pins asserted by an OUT. Value of 0 -> 32 pins + OUT_COUNT + + + read-write + [19:15] + The virtual pin corresponding to IN bit 0 + IN_BASE + + + read-write + [14:10] + The virtual pin corresponding to delay field bit 0 + SIDESET_BASE + + + read-write + [9:5] + The virtual pin corresponding to SET bit 0 + SET_BASE + + + read-write + [4:0] + The virtual pin corresponding to OUT bit 0 + OUT_BASE + + + SM2_PINCTRL + 0x14000000 + + + 0x0110 + Clock divider register for state machine 3\n + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + + + read-write + [31:16] + Effective frequency is sysclk/int.\n + Value of 0 is interpreted as max possible value + INT + + + read-write + [15:8] + Fractional part of clock divider + FRAC + + + SM3_CLKDIV + 0x00010000 + + + 0x0114 + Execution/behavioural settings for state machine 3 + + + read-only + [31:31] + An instruction written to SMx_INSTR is stalled, and latched by the\n + state machine. Will clear once the instruction completes. + EXEC_STALLED + + + read-write + [30:30] + If 1, the delay MSB is used as side-set enable, rather than a\n + side-set data bit. This allows instructions to perform side-set optionally,\n + rather than on every instruction. + SIDE_EN + + + read-write + [29:29] + Side-set data is asserted to pin OEs instead of pin values + SIDE_PINDIR + + + read-write + [28:24] + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN + + + read-write + [23:19] + Which data bit to use for inline OUT enable + OUT_EN_SEL + + + read-write + [18:18] + If 1, use a bit of OUT data as an auxiliary write enable\n + When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + deassert the latest pin write. This can create useful masking/override behaviour\n + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN + + + read-write + [17:17] + Continuously assert the most recent OUT/SET to the pins + OUT_STICKY + + + read-write + [16:12] + After reaching this address, execution is wrapped to wrap_bottom.\n + If the instruction is a jump, and the jump condition is true, the jump takes priority. + WRAP_TOP + + + read-write + [11:7] + After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM + + + read-write + [4:4] + Comparison used for the MOV x, STATUS instruction. + + + All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL + 0 + + + All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL + 1 + + + STATUS_SEL + + + read-write + [3:0] + Comparison level for the MOV x, STATUS instruction + STATUS_N + + + SM3_EXECCTRL + 0x0001f000 + + + 0x0118 + Control behaviour of the input/output shift registers for state machine 3 + + + read-write + [31:31] + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + TX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_RX + + + read-write + [30:30] + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + RX FIFO is disabled as a result (always reads as both full and empty).\n + FIFOs are flushed when this bit is changed. + FJOIN_TX + + + read-write + [29:25] + Number of bits shifted out of TXSR before autopull or conditional pull.\n + Write 0 for value of 32. + PULL_THRESH + + + read-write + [24:20] + Number of bits shifted into RXSR before autopush or conditional push.\n + Write 0 for value of 32. + PUSH_THRESH + + + read-write + [19:19] + 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR + + + read-write + [18:18] + 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR + + + read-write + [17:17] + Pull automatically when the output shift register is emptied + AUTOPULL + + + read-write + [16:16] + Push automatically when the input shift register is filled + AUTOPUSH + + + SM3_SHIFTCTRL + 0x000c0000 + + + 0x011c + Current instruction address of state machine 3 + + + read-only + [4:0] + SM3_ADDR + + + SM3_ADDR + 0x00000000 + + + 0x0120 + Instruction currently being executed by state machine 3\n + Write to execute an instruction immediately (including jumps) and then resume execution. + + + read-write + [15:0] + SM3_INSTR + + + SM3_INSTR + 0x00000000 + + + 0x0124 + State machine pin control + + + read-write + [31:29] + The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + SIDESET_COUNT + + + read-write + [28:26] + The number of pins asserted by a SET. Max of 5 + SET_COUNT + + + read-write + [25:20] + The number of pins asserted by an OUT. Value of 0 -> 32 pins + OUT_COUNT + + + read-write + [19:15] + The virtual pin corresponding to IN bit 0 + IN_BASE + + + read-write + [14:10] + The virtual pin corresponding to delay field bit 0 + SIDESET_BASE + + + read-write + [9:5] + The virtual pin corresponding to SET bit 0 + SET_BASE + + + read-write + [4:0] + The virtual pin corresponding to OUT bit 0 + OUT_BASE + + + SM3_PINCTRL + 0x14000000 + + + 0x0128 + Raw Interrupts + + + read-only + [11:11] + SM3 + + + read-only + [10:10] + SM2 + + + read-only + [9:9] + SM1 + + + read-only + [8:8] + SM0 + + + read-only + [7:7] + SM3_TXNFULL + + + read-only + [6:6] + SM2_TXNFULL + + + read-only + [5:5] + SM1_TXNFULL + + + read-only + [4:4] + SM0_TXNFULL + + + read-only + [3:3] + SM3_RXNEMPTY + + + read-only + [2:2] + SM2_RXNEMPTY + + + read-only + [1:1] + SM1_RXNEMPTY + + + read-only + [0:0] + SM0_RXNEMPTY + + + INTR + 0x00000000 + + + 0x012c + Interrupt Enable for irq0 + + + read-write + [11:11] + SM3 + + + read-write + [10:10] + SM2 + + + read-write + [9:9] + SM1 + + + read-write + [8:8] + SM0 + + + read-write + [7:7] + SM3_TXNFULL + + + read-write + [6:6] + SM2_TXNFULL + + + read-write + [5:5] + SM1_TXNFULL + + + read-write + [4:4] + SM0_TXNFULL + + + read-write + [3:3] + SM3_RXNEMPTY + + + read-write + [2:2] + SM2_RXNEMPTY + + + read-write + [1:1] + SM1_RXNEMPTY + + + read-write + [0:0] + SM0_RXNEMPTY + + + IRQ0_INTE + 0x00000000 + + + 0x0130 + Interrupt Force for irq0 + + + read-write + [11:11] + SM3 + + + read-write + [10:10] + SM2 + + + read-write + [9:9] + SM1 + + + read-write + [8:8] + SM0 + + + read-write + [7:7] + SM3_TXNFULL + + + read-write + [6:6] + SM2_TXNFULL + + + read-write + [5:5] + SM1_TXNFULL + + + read-write + [4:4] + SM0_TXNFULL + + + read-write + [3:3] + SM3_RXNEMPTY + + + read-write + [2:2] + SM2_RXNEMPTY + + + read-write + [1:1] + SM1_RXNEMPTY + + + read-write + [0:0] + SM0_RXNEMPTY + + + IRQ0_INTF + 0x00000000 + + + 0x0134 + Interrupt status after masking & forcing for irq0 + + + read-only + [11:11] + SM3 + + + read-only + [10:10] + SM2 + + + read-only + [9:9] + SM1 + + + read-only + [8:8] + SM0 + + + read-only + [7:7] + SM3_TXNFULL + + + read-only + [6:6] + SM2_TXNFULL + + + read-only + [5:5] + SM1_TXNFULL + + + read-only + [4:4] + SM0_TXNFULL + + + read-only + [3:3] + SM3_RXNEMPTY + + + read-only + [2:2] + SM2_RXNEMPTY + + + read-only + [1:1] + SM1_RXNEMPTY + + + read-only + [0:0] + SM0_RXNEMPTY + + + IRQ0_INTS + 0x00000000 + + + 0x0138 + Interrupt Enable for irq1 + + + read-write + [11:11] + SM3 + + + read-write + [10:10] + SM2 + + + read-write + [9:9] + SM1 + + + read-write + [8:8] + SM0 + + + read-write + [7:7] + SM3_TXNFULL + + + read-write + [6:6] + SM2_TXNFULL + + + read-write + [5:5] + SM1_TXNFULL + + + read-write + [4:4] + SM0_TXNFULL + + + read-write + [3:3] + SM3_RXNEMPTY + + + read-write + [2:2] + SM2_RXNEMPTY + + + read-write + [1:1] + SM1_RXNEMPTY + + + read-write + [0:0] + SM0_RXNEMPTY + + + IRQ1_INTE + 0x00000000 + + + 0x013c + Interrupt Force for irq1 + + + read-write + [11:11] + SM3 + + + read-write + [10:10] + SM2 + + + read-write + [9:9] + SM1 + + + read-write + [8:8] + SM0 + + + read-write + [7:7] + SM3_TXNFULL + + + read-write + [6:6] + SM2_TXNFULL + + + read-write + [5:5] + SM1_TXNFULL + + + read-write + [4:4] + SM0_TXNFULL + + + read-write + [3:3] + SM3_RXNEMPTY + + + read-write + [2:2] + SM2_RXNEMPTY + + + read-write + [1:1] + SM1_RXNEMPTY + + + read-write + [0:0] + SM0_RXNEMPTY + + + IRQ1_INTF + 0x00000000 + + + 0x0140 + Interrupt status after masking & forcing for irq1 + + + read-only + [11:11] + SM3 + + + read-only + [10:10] + SM2 + + + read-only + [9:9] + SM1 + + + read-only + [8:8] + SM0 + + + read-only + [7:7] + SM3_TXNFULL + + + read-only + [6:6] + SM2_TXNFULL + + + read-only + [5:5] + SM1_TXNFULL + + + read-only + [4:4] + SM0_TXNFULL + + + read-only + [3:3] + SM3_RXNEMPTY + + + read-only + [2:2] + SM2_RXNEMPTY + + + read-only + [1:1] + SM1_RXNEMPTY + + + read-only + [0:0] + SM0_RXNEMPTY + + + IRQ1_INTS + 0x00000000 + + + 32 + 1 + + + 0x50300000 + + PIO1_IRQ_0 + 9 + + + PIO1_IRQ_1 + 10 + + PIO1 + + + + 0 + 0x0200 + registers + + 0xd0000000 + Single-cycle IO block\n + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + + SIO_IRQ_PROC0 + 15 + + + SIO_IRQ_PROC1 + 16 + + SIO + + + read-only + 0x0000 + Processor core identifier\n + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + CPUID + 0x00000000 + + + 0x0004 + Input value for GPIO pins + + + read-only + [29:0] + Input value for GPIO0...29 + GPIO_IN + + + GPIO_IN + 0x00000000 + + + 0x0008 + Input value for QSPI pins + + + read-only + [5:0] + Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 + GPIO_HI_IN + + + GPIO_HI_IN + 0x00000000 + + + 0x0010 + GPIO output value + + + read-write + [29:0] + Set output level (1/0 -> high/low) for GPIO0...29.\n + Reading back gives the last value written, NOT the input value from the pins.\n + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + GPIO_OUT + + + GPIO_OUT + 0x00000000 + + + 0x0014 + GPIO output value set + + + read-write + [29:0] + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + GPIO_OUT_SET + + + GPIO_OUT_SET + 0x00000000 + + + 0x0018 + GPIO output value clear + + + read-write + [29:0] + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + GPIO_OUT_CLR + + + GPIO_OUT_CLR + 0x00000000 + + + 0x001c + GPIO output value XOR + + + read-write + [29:0] + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + GPIO_OUT_XOR + + + GPIO_OUT_XOR + 0x00000000 + + + 0x0020 + GPIO output enable + + + read-write + [29:0] + Set output enable (1/0 -> output/input) for GPIO0...29.\n + Reading back gives the last value written.\n + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + GPIO_OE + + + GPIO_OE + 0x00000000 + + + 0x0024 + GPIO output enable set + + + read-write + [29:0] + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + GPIO_OE_SET + + + GPIO_OE_SET + 0x00000000 + + + 0x0028 + GPIO output enable clear + + + read-write + [29:0] + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + GPIO_OE_CLR + + + GPIO_OE_CLR + 0x00000000 + + + 0x002c + GPIO output enable XOR + + + read-write + [29:0] + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + GPIO_OE_XOR + + + GPIO_OE_XOR + 0x00000000 + + + 0x0030 + QSPI output value + + + read-write + [5:0] + Set output level (1/0 -> high/low) for QSPI IO0...5.\n + Reading back gives the last value written, NOT the input value from the pins.\n + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + GPIO_HI_OUT + + + GPIO_HI_OUT + 0x00000000 + + + 0x0034 + QSPI output value set + + + read-write + [5:0] + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + GPIO_HI_OUT_SET + + + GPIO_HI_OUT_SET + 0x00000000 + + + 0x0038 + QSPI output value clear + + + read-write + [5:0] + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + GPIO_HI_OUT_CLR + + + GPIO_HI_OUT_CLR + 0x00000000 + + + 0x003c + QSPI output value XOR + + + read-write + [5:0] + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + GPIO_HI_OUT_XOR + + + GPIO_HI_OUT_XOR + 0x00000000 + + + 0x0040 + QSPI output enable + + + read-write + [5:0] + Set output enable (1/0 -> output/input) for QSPI IO0...5.\n + Reading back gives the last value written.\n + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n + the result is as though the write from core 0 took place first,\n + and the write from core 1 was then applied to that intermediate result. + GPIO_HI_OE + + + GPIO_HI_OE + 0x00000000 + + + 0x0044 + QSPI output enable set + + + read-write + [5:0] + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + GPIO_HI_OE_SET + + + GPIO_HI_OE_SET + 0x00000000 + + + 0x0048 + QSPI output enable clear + + + read-write + [5:0] + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + GPIO_HI_OE_CLR + + + GPIO_HI_OE_CLR + 0x00000000 + + + 0x004c + QSPI output enable XOR + + + read-write + [5:0] + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + GPIO_HI_OE_XOR + + + GPIO_HI_OE_XOR + 0x00000000 + + + 0x0050 + Status register for inter-core FIFOs (mailboxes).\n + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + + + read-write + [3:3] + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + oneToClear + ROE + + + read-write + [2:2] + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + oneToClear + WOF + + + read-only + [1:1] + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + RDY + + + read-only + [0:0] + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + VLD + + + FIFO_ST + 0x00000002 + + + write-only + 0x0054 + Write access to this core's TX FIFO + FIFO_WR + 0x00000000 + + + read-only + 0x0058 + Read access to this core's RX FIFO + FIFO_RD + 0x00000000 + + + read-only + 0x005c + Spinlock state\n + A bitmap containing the state of all 32 spinlocks (1=locked).\n + Mainly intended for debugging. + SPINLOCK_ST + 0x00000000 + + + read-write + 0x0060 + Divider unsigned dividend\n + Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n + unsigned calculation, and the S alias starts a signed calculation. + DIV_UDIVIDEND + 0x00000000 + + + read-write + 0x0064 + Divider unsigned divisor\n + Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n + unsigned calculation, and the S alias starts a signed calculation. + DIV_UDIVISOR + 0x00000000 + + + read-write + 0x0068 + Divider signed dividend\n + The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + DIV_SDIVIDEND + 0x00000000 + + + read-write + 0x006c + Divider signed divisor\n + The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + DIV_SDIVISOR + 0x00000000 + + + read-write + 0x0070 + Divider result quotient\n + The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n + For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n + This register can be written to directly, for context save/restore purposes. This halts any\n + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n + Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n + REMAINDER, QUOTIENT if CSR_DIRTY is used. + DIV_QUOTIENT + 0x00000000 + + + read-write + 0x0074 + Divider result remainder\n + The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n + For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n + This register can be written to directly, for context save/restore purposes. This halts any\n + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + DIV_REMAINDER + 0x00000000 + + + 0x0078 + Control and status register for divider. + + + read-only + [1:1] + Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n + Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n + If the flag is used in this way, it's recommended to either read QUOTIENT only,\n + or REMAINDER and then QUOTIENT, to prevent data loss on context switch. + DIRTY + + + read-only + [0:0] + Reads as 0 when a calculation is in progress, 1 otherwise.\n + Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n + matter if one is already in progress.\n + Writing to a result register will immediately terminate any in-progress calculation\n + and set the READY and DIRTY flags. + READY + + + DIV_CSR + 0x00000001 + + + read-write + 0x0080 + Read/write access to accumulator 0 + INTERP0_ACCUM0 + 0x00000000 + + + read-write + 0x0084 + Read/write access to accumulator 1 + INTERP0_ACCUM1 + 0x00000000 + + + read-write + 0x0088 + Read/write access to BASE0 register. + INTERP0_BASE0 + 0x00000000 + + + read-write + 0x008c + Read/write access to BASE1 register. + INTERP0_BASE1 + 0x00000000 + + + read-write + 0x0090 + Read/write access to BASE2 register. + INTERP0_BASE2 + 0x00000000 + + + read-only + 0x0094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + INTERP0_POP_LANE0 + 0x00000000 + + + read-only + 0x0098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + INTERP0_POP_LANE1 + 0x00000000 + + + read-only + 0x009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + INTERP0_POP_FULL + 0x00000000 + + + read-only + 0x00a0 + Read LANE0 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE0 + 0x00000000 + + + read-only + 0x00a4 + Read LANE1 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE1 + 0x00000000 + + + read-only + 0x00a8 + Read FULL result, without altering any internal state (PEEK). + INTERP0_PEEK_FULL + 0x00000000 + + + 0x00ac + Control register for lane 0 + + + read-only + [25:25] + Set if either OVERF0 or OVERF1 is set. + OVERF + + + read-only + [24:24] + Indicates if any masked-off MSBs in ACCUM1 are set. + OVERF1 + + + read-only + [23:23] + Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF0 + + + read-write + [21:21] + Only present on INTERP0 on each core. If BLEND mode is enabled:\n + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n + by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n + 0 and 255/256ths)\n + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + BLEND + + + read-write + [20:19] + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + FORCE_MSB + + + read-write + [18:18] + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + ADD_RAW + + + read-write + [17:17] + If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT + + + read-write + [16:16] + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + CROSS_INPUT + + + read-write + [15:15] + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + SIGNED + + + read-write + [14:10] + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB + + + read-write + [9:5] + The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB + + + read-write + [4:0] + Logical right-shift applied to accumulator before masking + SHIFT + + + INTERP0_CTRL_LANE0 + 0x00000000 + + + 0x00b0 + Control register for lane 1 + + + read-write + [20:19] + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + FORCE_MSB + + + read-write + [18:18] + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + ADD_RAW + + + read-write + [17:17] + If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT + + + read-write + [16:16] + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + CROSS_INPUT + + + read-write + [15:15] + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + SIGNED + + + read-write + [14:10] + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB + + + read-write + [9:5] + The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB + + + read-write + [4:0] + Logical right-shift applied to accumulator before masking + SHIFT + + + INTERP0_CTRL_LANE1 + 0x00000000 + + + 0x00b4 + Values written here are atomically added to ACCUM0\n + Reading yields lane 0's raw shift and mask value (BASE0 not added). + + + read-write + [23:0] + INTERP0_ACCUM0_ADD + + + INTERP0_ACCUM0_ADD + 0x00000000 + + + 0x00b8 + Values written here are atomically added to ACCUM1\n + Reading yields lane 1's raw shift and mask value (BASE1 not added). + + + read-write + [23:0] + INTERP0_ACCUM1_ADD + + + INTERP0_ACCUM1_ADD + 0x00000000 + + + read-write + 0x00bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + INTERP0_BASE_1AND0 + 0x00000000 + + + read-write + 0x00c0 + Read/write access to accumulator 0 + INTERP1_ACCUM0 + 0x00000000 + + + read-write + 0x00c4 + Read/write access to accumulator 1 + INTERP1_ACCUM1 + 0x00000000 + + + read-write + 0x00c8 + Read/write access to BASE0 register. + INTERP1_BASE0 + 0x00000000 + + + read-write + 0x00cc + Read/write access to BASE1 register. + INTERP1_BASE1 + 0x00000000 + + + read-write + 0x00d0 + Read/write access to BASE2 register. + INTERP1_BASE2 + 0x00000000 + + + read-only + 0x00d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + INTERP1_POP_LANE0 + 0x00000000 + + + read-only + 0x00d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + INTERP1_POP_LANE1 + 0x00000000 + + + read-only + 0x00dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + INTERP1_POP_FULL + 0x00000000 + + + read-only + 0x00e0 + Read LANE0 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE0 + 0x00000000 + + + read-only + 0x00e4 + Read LANE1 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE1 + 0x00000000 + + + read-only + 0x00e8 + Read FULL result, without altering any internal state (PEEK). + INTERP1_PEEK_FULL + 0x00000000 + + + 0x00ec + Control register for lane 0 + + + read-only + [25:25] + Set if either OVERF0 or OVERF1 is set. + OVERF + + + read-only + [24:24] + Indicates if any masked-off MSBs in ACCUM1 are set. + OVERF1 + + + read-only + [23:23] + Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF0 + + + read-write + [22:22] + Only present on INTERP1 on each core. If CLAMP mode is enabled:\n + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n + BASE0 and an upper bound of BASE1.\n + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + CLAMP + + + read-write + [20:19] + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + FORCE_MSB + + + read-write + [18:18] + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + ADD_RAW + + + read-write + [17:17] + If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT + + + read-write + [16:16] + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + CROSS_INPUT + + + read-write + [15:15] + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + SIGNED + + + read-write + [14:10] + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB + + + read-write + [9:5] + The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB + + + read-write + [4:0] + Logical right-shift applied to accumulator before masking + SHIFT + + + INTERP1_CTRL_LANE0 + 0x00000000 + + + 0x00f0 + Control register for lane 1 + + + read-write + [20:19] + ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n + of pointers into flash or SRAM. + FORCE_MSB + + + read-write + [18:18] + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + ADD_RAW + + + read-write + [17:17] + If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT + + + read-write + [16:16] + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + CROSS_INPUT + + + read-write + [15:15] + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + SIGNED + + + read-write + [14:10] + The most-significant bit allowed to pass by the mask (inclusive)\n + Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB + + + read-write + [9:5] + The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB + + + read-write + [4:0] + Logical right-shift applied to accumulator before masking + SHIFT + + + INTERP1_CTRL_LANE1 + 0x00000000 + + + 0x00f4 + Values written here are atomically added to ACCUM0\n + Reading yields lane 0's raw shift and mask value (BASE0 not added). + + + read-write + [23:0] + INTERP1_ACCUM0_ADD + + + INTERP1_ACCUM0_ADD + 0x00000000 + + + 0x00f8 + Values written here are atomically added to ACCUM1\n + Reading yields lane 1's raw shift and mask value (BASE1 not added). + + + read-write + [23:0] + INTERP1_ACCUM1_ADD + + + INTERP1_ACCUM1_ADD + 0x00000000 + + + read-write + 0x00fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + INTERP1_BASE_1AND0 + 0x00000000 + + + read-only + 0x0100 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK0 + 0x00000000 + + + read-only + 0x0104 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK1 + 0x00000000 + + + read-only + 0x0108 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK2 + 0x00000000 + + + read-only + 0x010c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK3 + 0x00000000 + + + read-only + 0x0110 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK4 + 0x00000000 + + + read-only + 0x0114 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK5 + 0x00000000 + + + read-only + 0x0118 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK6 + 0x00000000 + + + read-only + 0x011c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK7 + 0x00000000 + + + read-only + 0x0120 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK8 + 0x00000000 + + + read-only + 0x0124 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK9 + 0x00000000 + + + read-only + 0x0128 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK10 + 0x00000000 + + + read-only + 0x012c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK11 + 0x00000000 + + + read-only + 0x0130 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK12 + 0x00000000 + + + read-only + 0x0134 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK13 + 0x00000000 + + + read-only + 0x0138 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK14 + 0x00000000 + + + read-only + 0x013c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK15 + 0x00000000 + + + read-only + 0x0140 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK16 + 0x00000000 + + + read-only + 0x0144 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK17 + 0x00000000 + + + read-only + 0x0148 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK18 + 0x00000000 + + + read-only + 0x014c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK19 + 0x00000000 + + + read-only + 0x0150 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK20 + 0x00000000 + + + read-only + 0x0154 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK21 + 0x00000000 + + + read-only + 0x0158 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK22 + 0x00000000 + + + read-only + 0x015c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK23 + 0x00000000 + + + read-only + 0x0160 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK24 + 0x00000000 + + + read-only + 0x0164 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK25 + 0x00000000 + + + read-only + 0x0168 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK26 + 0x00000000 + + + read-only + 0x016c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK27 + 0x00000000 + + + read-only + 0x0170 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK28 + 0x00000000 + + + read-only + 0x0174 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK29 + 0x00000000 + + + read-only + 0x0178 + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK30 + 0x00000000 + + + read-only + 0x017c + Reading from a spinlock address will:\n + - Return 0 if lock is already locked\n + - Otherwise return nonzero, and simultaneously claim the lock\n\n + Writing (any value) releases the lock.\n + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n + The value returned on success is 0x1 << lock number. + SPINLOCK31 + 0x00000000 + + + 32 + 1 + + + + 0 + 0x10000 + registers + + 0xe0000000 + PPB + + + 0xe010 + Use the SysTick Control and Status Register to enable the SysTick features. + + + read-only + [16:16] + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + COUNTFLAG + + + read-write + [2:2] + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n + Selects the SysTick timer clock source:\n + 0 = External reference clock.\n + 1 = Processor clock. + CLKSOURCE + + + read-write + [1:1] + Enables SysTick exception request:\n + 0 = Counting down to zero does not assert the SysTick exception request.\n + 1 = Counting down to zero to asserts the SysTick exception request. + TICKINT + + + read-write + [0:0] + Enable SysTick counter:\n + 0 = Counter disabled.\n + 1 = Counter enabled. + ENABLE + + + SYST_CSR + 0x00000000 + + + 0xe014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + + + read-write + [23:0] + Value to load into the SysTick Current Value Register when the counter reaches 0. + RELOAD + + + SYST_RVR + 0x00000000 + + + 0xe018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + + + read-write + [23:0] + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + CURRENT + + + SYST_CVR + 0x00000000 + + + 0xe01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + + + read-only + [31:31] + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + NOREF + + + read-only + [30:30] + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + SKEW + + + read-only + [23:0] + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + TENMS + + + SYST_CALIB + 0x00000000 + + + 0xe100 + Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n + If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. + + + read-write + [31:0] + Interrupt set-enable bits.\n + Write:\n + 0 = No effect.\n + 1 = Enable interrupt.\n + Read:\n + 0 = Interrupt disabled.\n + 1 = Interrupt enabled. + SETENA + + + NVIC_ISER + 0x00000000 + + + 0xe180 + Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. + + + read-write + [31:0] + Interrupt clear-enable bits.\n + Write:\n + 0 = No effect.\n + 1 = Disable interrupt.\n + Read:\n + 0 = Interrupt disabled.\n + 1 = Interrupt enabled. + CLRENA + + + NVIC_ICER + 0x00000000 + + + 0xe200 + The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. + + + read-write + [31:0] + Interrupt set-pending bits.\n + Write:\n + 0 = No effect.\n + 1 = Changes interrupt state to pending.\n + Read:\n + 0 = Interrupt is not pending.\n + 1 = Interrupt is pending.\n + Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n + An interrupt that is pending has no effect.\n + A disabled interrupt sets the state of that interrupt to pending. + SETPEND + + + NVIC_ISPR + 0x00000000 + + + 0xe280 + Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. + + + read-write + [31:0] + Interrupt clear-pending bits.\n + Write:\n + 0 = No effect.\n + 1 = Removes pending state and interrupt.\n + Read:\n + 0 = Interrupt is not pending.\n + 1 = Interrupt is pending. + CLRPEND + + + NVIC_ICPR + 0x00000000 + + + 0xe400 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n + Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n + These registers are only word-accessible + + + read-write + [31:30] + Priority of interrupt 3 + IP_3 + + + read-write + [23:22] + Priority of interrupt 2 + IP_2 + + + read-write + [15:14] + Priority of interrupt 1 + IP_1 + + + read-write + [7:6] + Priority of interrupt 0 + IP_0 + + + NVIC_IPR0 + 0x00000000 + + + 0xe404 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 7 + IP_7 + + + read-write + [23:22] + Priority of interrupt 6 + IP_6 + + + read-write + [15:14] + Priority of interrupt 5 + IP_5 + + + read-write + [7:6] + Priority of interrupt 4 + IP_4 + + + NVIC_IPR1 + 0x00000000 + + + 0xe408 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 11 + IP_11 + + + read-write + [23:22] + Priority of interrupt 10 + IP_10 + + + read-write + [15:14] + Priority of interrupt 9 + IP_9 + + + read-write + [7:6] + Priority of interrupt 8 + IP_8 + + + NVIC_IPR2 + 0x00000000 + + + 0xe40c + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 15 + IP_15 + + + read-write + [23:22] + Priority of interrupt 14 + IP_14 + + + read-write + [15:14] + Priority of interrupt 13 + IP_13 + + + read-write + [7:6] + Priority of interrupt 12 + IP_12 + + + NVIC_IPR3 + 0x00000000 + + + 0xe410 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 19 + IP_19 + + + read-write + [23:22] + Priority of interrupt 18 + IP_18 + + + read-write + [15:14] + Priority of interrupt 17 + IP_17 + + + read-write + [7:6] + Priority of interrupt 16 + IP_16 + + + NVIC_IPR4 + 0x00000000 + + + 0xe414 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 23 + IP_23 + + + read-write + [23:22] + Priority of interrupt 22 + IP_22 + + + read-write + [15:14] + Priority of interrupt 21 + IP_21 + + + read-write + [7:6] + Priority of interrupt 20 + IP_20 + + + NVIC_IPR5 + 0x00000000 + + + 0xe418 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 27 + IP_27 + + + read-write + [23:22] + Priority of interrupt 26 + IP_26 + + + read-write + [15:14] + Priority of interrupt 25 + IP_25 + + + read-write + [7:6] + Priority of interrupt 24 + IP_24 + + + NVIC_IPR6 + 0x00000000 + + + 0xe41c + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + + + read-write + [31:30] + Priority of interrupt 31 + IP_31 + + + read-write + [23:22] + Priority of interrupt 30 + IP_30 + + + read-write + [15:14] + Priority of interrupt 29 + IP_29 + + + read-write + [7:6] + Priority of interrupt 28 + IP_28 + + + NVIC_IPR7 + 0x00000000 + + + 0xed00 + Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. + + + read-only + [31:24] + Implementor code: 0x41 = ARM + IMPLEMENTER + + + read-only + [23:20] + Major revision number n in the rnpm revision status:\n + 0x0 = Revision 0. + VARIANT + + + read-only + [19:16] + Constant that defines the architecture of the processor:\n + 0xC = ARMv6-M architecture. + ARCHITECTURE + + + read-only + [15:4] + Number of processor within family: 0xC60 = Cortex-M0+ + PARTNO + + + read-only + [3:0] + Minor revision number m in the rnpm revision status:\n + 0x1 = Patch 1. + REVISION + + + CPUID + 0x410cc601 + + + 0xed04 + Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. + + + read-write + [31:31] + Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n + NMI set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes NMI exception state to pending.\n + Read:\n + 0 = NMI exception is not pending.\n + 1 = NMI exception is pending.\n + Because NMI is the highest-priority exception, normally the processor enters the NMI\n + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n + NMI signal is reasserted while the processor is executing that handler. + NMIPENDSET + + + read-write + [28:28] + PendSV set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes PendSV exception state to pending.\n + Read:\n + 0 = PendSV exception is not pending.\n + 1 = PendSV exception is pending.\n + Writing 1 to this bit is the only way to set the PendSV exception state to pending. + PENDSVSET + + + read-write + [27:27] + PendSV clear-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Removes the pending state from the PendSV exception. + PENDSVCLR + + + read-write + [26:26] + SysTick exception set-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Changes SysTick exception state to pending.\n + Read:\n + 0 = SysTick exception is not pending.\n + 1 = SysTick exception is pending. + PENDSTSET + + + read-write + [25:25] + SysTick exception clear-pending bit.\n + Write:\n + 0 = No effect.\n + 1 = Removes the pending state from the SysTick exception.\n + This bit is WO. On a register read its value is Unknown. + PENDSTCLR + + + read-only + [23:23] + The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. + ISRPREEMPT + + + read-only + [22:22] + External interrupt pending flag + ISRPENDING + + + read-only + [20:12] + Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. + VECTPENDING + + + read-only + [8:0] + Active exception number field. Reset clears the VECTACTIVE field. + VECTACTIVE + + + ICSR + 0x00000000 + + + 0xed08 + The VTOR holds the vector table offset address. + + + read-write + [31:8] + Bits [31:8] of the indicate the vector table offset address. + TBLOFF + + + VTOR + 0x00000000 + + + 0xed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + + + read-write + [31:16] + Register key:\n + Reads as Unknown\n + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + VECTKEY + + + read-only + [15:15] + Data endianness implemented:\n + 0 = Little-endian. + ENDIANESS + + + read-write + [2:2] + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + SYSRESETREQ + + + read-write + [1:1] + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + VECTCLRACTIVE + + + AIRCR + 0x00000000 + + + 0xed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + + + read-write + [4:4] + Send Event on Pending bit:\n + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n + processor is not waiting for an event, the event is registered and affects the next WFE.\n + The processor also wakes up on execution of an SEV instruction or an external event. + SEVONPEND + + + read-write + [2:2] + Controls whether the processor uses sleep or deep sleep as its low power mode:\n + 0 = Sleep.\n + 1 = Deep sleep. + SLEEPDEEP + + + read-write + [1:1] + Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n + 0 = Do not sleep when returning to Thread mode.\n + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + SLEEPONEXIT + + + SCR + 0x00000000 + + + 0xed14 + The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. + + + read-only + [9:9] + Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. + STKALIGN + + + read-only + [3:3] + Always reads as one, indicates that all unaligned accesses generate a HardFault. + UNALIGN_TRP + + + CCR + 0x00000000 + + + 0xed1c + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. + + + read-write + [31:30] + Priority of system handler 11, SVCall + PRI_11 + + + SHPR2 + 0x00000000 + + + 0xed20 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. + + + read-write + [31:30] + Priority of system handler 15, SysTick + PRI_15 + + + read-write + [23:22] + Priority of system handler 14, PendSV + PRI_14 + + + SHPR3 + 0x00000000 + + + 0xed24 + Use the System Handler Control and State Register to determine or clear the pending status of SVCall. + + + read-write + [15:15] + Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. + SVCALLPENDED + + + SHCSR + 0x00000000 + + + 0xed90 + Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. + + + read-only + [23:16] + Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. + IREGION + + + read-only + [15:8] + Number of regions supported by the MPU. + DREGION + + + read-only + [0:0] + Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. + SEPARATE + + + MPU_TYPE + 0x00000800 + + + 0xed94 + Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. + + + read-write + [2:2] + Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n + covered by any enabled region causes a fault.\n + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. + PRIVDEFENA + + + read-write + [1:1] + Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n + When the MPU is enabled:\n + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n + 1 = the MPU is enabled during HardFault and NMI handlers. + HFNMIENA + + + read-write + [0:0] + Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n + 0 = MPU disabled.\n + 1 = MPU enabled. + ENABLE + + + MPU_CTRL + 0x00000000 + + + 0xed98 + Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. + + + read-write + [3:0] + Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n + The MPU supports 8 memory regions, so the permitted values of this field are 0-7. + REGION + + + MPU_RNR + 0x00000000 + + + 0xed9c + Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. + + + read-write + [31:8] + Base address of the region. + ADDR + + + read-write + [4:4] + On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n + Write:\n + 0 = MPU_RNR not changed, and the processor:\n + Updates the base address for the region specified in the MPU_RNR.\n + Ignores the value of the REGION field.\n + 1 = The processor:\n + Updates the value of the MPU_RNR to the value of the REGION field.\n + Updates the base address for the region specified in the REGION field.\n + Always reads as zero. + VALID + + + read-write + [3:0] + On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. + REGION + + + MPU_RBAR + 0x00000000 + + + 0xeda0 + Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. + + + read-write + [31:16] + The MPU Region Attribute field. Use to define the region attribute control.\n + 28 = XN: Instruction access disable bit:\n + 0 = Instruction fetches enabled.\n + 1 = Instruction fetches disabled.\n + 26:24 = AP: Access permission field\n + 18 = S: Shareable bit\n + 17 = C: Cacheable bit\n + 16 = B: Bufferable bit + ATTRS + + + read-write + [15:8] + Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. + SRD + + + read-write + [5:1] + Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes + SIZE + + + read-write + [0:0] + Enables the region. + ENABLE + + + MPU_RASR + 0x00000000 + + + 32 + 1 + + + \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/CMakeLists.txt new file mode 100644 index 00000000000..9c39eef57e3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/CMakeLists.txt @@ -0,0 +1,3 @@ +add_library(hardware_structs INTERFACE) +target_include_directories(hardware_structs INTERFACE include) +target_link_libraries(hardware_structs INTERFACE hardware_regs) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h new file mode 100644 index 00000000000..559b5f17727 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +typedef struct { + io_rw_32 cs; + io_rw_32 result; + io_rw_32 fcs; + io_rw_32 fifo; + io_rw_32 div; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} adc_hw_t; + +check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); + +#define adc_hw ((adc_hw_t *const)ADC_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h new file mode 100644 index 00000000000..ce95a7c1984 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H +#define _HARDWARE_STRUCTS_BUS_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +enum bus_ctrl_perf_counter { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +}; + +typedef struct { + io_rw_32 priority; + io_ro_32 priority_ack; + struct { + io_rw_32 value; + io_rw_32 sel; + } counter[4]; +} bus_ctrl_hw_t; + +check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); + +#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h new file mode 100644 index 00000000000..489876d1698 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/clocks.h" + +/*! \brief Enumeration identifying a hardware clock + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +enum clock_index { + clk_gpout0 = 0, ///< GPIO Muxing 0 + clk_gpout1, ///< GPIO Muxing 1 + clk_gpout2, ///< GPIO Muxing 2 + clk_gpout3, ///< GPIO Muxing 3 + clk_ref, ///< Watchdog and timers reference clock + clk_sys, ///< Processors, bus fabric, memory, memory mapped registers + clk_peri, ///< Peripheral clock for UART and SPI + clk_usb, ///< USB clock + clk_adc, ///< ADC clock + clk_rtc, ///< Real time clock + CLK_COUNT +}; +/// \end::clkenum[] + +/// \tag::clock_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 div; + io_rw_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + io_rw_32 ref_khz; + io_rw_32 min_khz; + io_rw_32 max_khz; + io_rw_32 delay; + io_rw_32 interval; + io_rw_32 src; + io_ro_32 status; + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[CLK_COUNT]; + struct { + io_rw_32 ctrl; + io_rw_32 status; + } resus; + fc_hw_t fc0; + io_rw_32 wake_en0; + io_rw_32 wake_en1; + io_rw_32 sleep_en0; + io_rw_32 sleep_en1; + io_rw_32 enabled0; + io_rw_32 enabled1; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h new file mode 100644 index 00000000000..06cdf792750 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/dma.h" + +typedef struct { + io_rw_32 read_addr; + io_rw_32 write_addr; + io_rw_32 transfer_count; + io_rw_32 ctrl_trig; + io_rw_32 al1_ctrl; + io_rw_32 al1_read_addr; + io_rw_32 al1_write_addr; + io_rw_32 al1_transfer_count_trig; + io_rw_32 al2_ctrl; + io_rw_32 al2_transfer_count; + io_rw_32 al2_read_addr; + io_rw_32 al2_write_addr_trig; + io_rw_32 al3_ctrl; + io_rw_32 al3_write_addr; + io_rw_32 al3_transfer_count; + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; + uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + io_ro_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_rw_32 ints0; + uint32_t _pad1[1]; + io_rw_32 inte1; + io_rw_32 intf1; + io_rw_32 ints1; + io_rw_32 timer[4]; + io_wo_32 multi_channel_trigger; + io_rw_32 sniff_ctrl; + io_rw_32 sniff_data; + uint32_t _pad2[1]; + io_ro_32 fifo_levels; + io_wo_32 abort; +} dma_hw_t; + +typedef struct { + struct dma_debug_hw_channel { + io_ro_32 ctrdeq; + io_ro_32 tcr; + uint32_t pad[14]; + } ch[NUM_DMA_CHANNELS]; +} dma_debug_hw_t; + +#define dma_hw ((dma_hw_t *const)DMA_BASE) +#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h new file mode 100644 index 00000000000..4bc501f2886 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +typedef struct { + io_rw_32 con; + io_rw_32 tar; + io_rw_32 sar; + uint32_t _pad0; + io_rw_32 data_cmd; + io_rw_32 ss_scl_hcnt; + io_rw_32 ss_scl_lcnt; + io_rw_32 fs_scl_hcnt; + io_rw_32 fs_scl_lcnt; + uint32_t _pad1[2]; + io_rw_32 intr_stat; + io_rw_32 intr_mask; + io_rw_32 raw_intr_stat; + io_rw_32 rx_tl; + io_rw_32 tx_tl; + io_rw_32 clr_intr; + io_rw_32 clr_rx_under; + io_rw_32 clr_rx_over; + io_rw_32 clr_tx_over; + io_rw_32 clr_rd_req; + io_rw_32 clr_tx_abrt; + io_rw_32 clr_rx_done; + io_rw_32 clr_activity; + io_rw_32 clr_stop_det; + io_rw_32 clr_start_det; + io_rw_32 clr_gen_call; + io_rw_32 enable; + io_rw_32 status; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sda_hold; + io_rw_32 tx_abrt_source; + io_rw_32 slv_data_nack_only; + io_rw_32 dma_cr; + io_rw_32 dma_tdlr; + io_rw_32 dma_rdlr; + io_rw_32 sda_setup; + io_rw_32 ack_general_call; + io_rw_32 enable_status; + io_rw_32 fs_spklen; + uint32_t _pad2; + io_rw_32 clr_restart_det; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) + +// List of configuration constants for the Synopsys I2C hardware (you may see +// references to these in I2C register header; these are *fixed* values, +// set at hardware design time): + +// SLAVE_INTERFACE_TYPE .............. 0 +// REG_TIMEOUT_WIDTH ................. 4 +// REG_TIMEOUT_VALUE ................. 8 +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_SS_SCL_LOW_COUNT ............... 0x01d6 +// IC_HAS_DMA ........................ 0x1 +// IC_RX_FULL_GEN_NACK ............... 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x003c +// IC_HS_SCL_LOW_COUNT ............... 0x0010 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0xf +// IC_ADD_ENCODED_PARAMS ............. 0x1 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// SLVERR_RESP_EN .................... 0 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK ................... 0x1 +// HC_REG_TIMEOUT_VALUE .............. 0 +// IC_BUS_CLEAR_FEATURE .............. 0x1 +// IC_CAP_LOADING .................... 100 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_FS_SCL_LOW_COUNT ............... 0x0082 +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_TX_BUFFER_DEPTH ................ 32 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_CLK_TYPE ....................... 0x0 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x1 +// IC_STAT_FOR_CLK_STRETCH ........... 0x1 +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x1 +// IC_RX_BUFFER_DEPTH ................ 32 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 1 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_SMBUS_UDID_HC .................. 0x1 +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0190 + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h new file mode 100644 index 00000000000..683750733b6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/sio.h" + +typedef struct { + io_rw_32 accum[2]; + io_rw_32 base[3]; + io_ro_32 pop[3]; + io_ro_32 peek[3]; + io_rw_32 ctrl[2]; + io_rw_32 add_raw[2]; + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h new file mode 100644 index 00000000000..b19800fa7d3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOBANK0_H +#define _HARDWARE_STRUCTS_IOBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_bank0.h" + +typedef struct { + io_rw_32 inte[4]; + io_rw_32 intf[4]; + io_rw_32 ints[4]; +} io_irq_ctrl_hw_t; + +/// \tag::iobank0_hw[] +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[30]; + io_rw_32 intr[4]; + io_irq_ctrl_hw_t proc0_irq_ctrl; + io_irq_ctrl_hw_t proc1_irq_ctrl; + io_irq_ctrl_hw_t dormant_wake_irq_ctrl; +} iobank0_hw_t; +/// \end::iobank0_hw[] + +#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h new file mode 100644 index 00000000000..48d08a7c92b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOQSPI_H +#define _HARDWARE_STRUCTS_IOQSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_qspi.h" + +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[6]; +} ioqspi_hw_t; + +#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h new file mode 100644 index 00000000000..34e5c39e81f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_ro_32 type; + io_rw_32 ctrl; + io_rw_32 rnr; + io_rw_32 rbar; + io_rw_32 rasr; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h new file mode 100644 index 00000000000..451d7ebc383 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_qspi.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h new file mode 100644 index 00000000000..f56dc401150 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADSBANK0_H +#define _HARDWARE_STRUCTS_PADSBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_bank0.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[30]; +} padsbank0_hw_t; + +#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h new file mode 100644 index 00000000000..176863bb4d8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pio.h" + +typedef struct { + io_rw_32 ctrl; + io_ro_32 fstat; + io_rw_32 fdebug; + io_ro_32 flevel; + io_wo_32 txf[NUM_PIO_STATE_MACHINES]; + io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; + io_rw_32 irq; + io_wo_32 irq_force; + io_rw_32 input_sync_bypass; + io_rw_32 dbg_padout; + io_rw_32 dbg_padoe; + io_rw_32 dbg_cfginfo; + io_wo_32 instr_mem[32]; + struct pio_sm_hw { + io_rw_32 clkdiv; + io_rw_32 execctrl; + io_rw_32 shiftctrl; + io_ro_32 addr; + io_rw_32 instr; + io_rw_32 pinctrl; + } sm[NUM_PIO_STATE_MACHINES]; + io_rw_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_ro_32 ints0; + io_rw_32 inte1; + io_rw_32 intf1; + io_ro_32 ints1; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *const)PIO0_BASE) +#define pio1_hw ((pio_hw_t *const)PIO1_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h new file mode 100644 index 00000000000..4d5b5b78ccb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +/// \tag::pll_hw[] +typedef struct { + io_rw_32 cs; + io_rw_32 pwr; + io_rw_32 fbdiv_int; + io_rw_32 prim; +} pll_hw_t; + +#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) +/// \end::pll_hw[] + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h new file mode 100644 index 00000000000..cc9fb97e07d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/psm.h" + +typedef struct { + io_rw_32 frce_on; + io_rw_32 frce_off; + io_rw_32 wdsel; + io_rw_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *const)PSM_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h new file mode 100644 index 00000000000..54995610939 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pwm.h" + +typedef struct pwm_slice_hw { + io_rw_32 csr; + io_rw_32 div; + io_rw_32 ctr; + io_rw_32 cc; + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + pwm_slice_hw_t slice[NUM_PWM_SLICES]; + io_rw_32 en; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *const)PWM_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h new file mode 100644 index 00000000000..a96ddebd7c7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +/// \tag::resets_hw[] +typedef struct { + io_rw_32 reset; + io_rw_32 wdsel; + io_rw_32 reset_done; +} resets_hw_t; + +#define resets_hw ((resets_hw_t *const)RESETS_BASE) +/// \end::resets_hw[] + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h new file mode 100644 index 00000000000..10543937cf4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rosc.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 freqa; + io_rw_32 freqb; + io_rw_32 dormant; + io_rw_32 div; + io_rw_32 phase; + io_rw_32 status; + io_rw_32 randombit; + io_rw_32 count; + io_rw_32 dftx; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *const)ROSC_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h new file mode 100644 index 00000000000..276bd7a2428 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_RTC_H +#define _HARDWARE_STRUCTS_RTC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rtc.h" + +typedef struct { + io_rw_32 clkdiv_m1; + io_rw_32 setup_0; + io_rw_32 setup_1; + io_rw_32 ctrl; + io_rw_32 irq_setup_0; + io_rw_32 irq_setup_1; + io_rw_32 rtc_1; + io_rw_32 rtc_0; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} rtc_hw_t; + +#define rtc_hw ((rtc_hw_t *const)RTC_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h new file mode 100644 index 00000000000..b48a8725472 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// SCB == System Control Block +typedef struct { + io_ro_32 cpuid; + io_rw_32 icsr; + io_rw_32 vtor; + io_rw_32 aircr; + io_rw_32 scr; + // ... +} armv6m_scb_t; + +#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h new file mode 100644 index 00000000000..400083f81a9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +typedef struct { + io_ro_32 cpuid; + io_ro_32 gpio_in; + io_ro_32 gpio_hi_in; + uint32_t _pad; + + io_wo_32 gpio_out; + io_wo_32 gpio_set; + io_wo_32 gpio_clr; + io_wo_32 gpio_togl; + + io_wo_32 gpio_oe; + io_wo_32 gpio_oe_set; + io_wo_32 gpio_oe_clr; + io_wo_32 gpio_oe_togl; + + io_wo_32 gpio_hi_out; + io_wo_32 gpio_hi_set; + io_wo_32 gpio_hi_clr; + io_wo_32 gpio_hi_togl; + + io_wo_32 gpio_hi_oe; + io_wo_32 gpio_hi_oe_set; + io_wo_32 gpio_hi_oe_clr; + io_wo_32 gpio_hi_oe_togl; + + io_rw_32 fifo_st; + io_wo_32 fifo_wr; + io_ro_32 fifo_rd; + io_ro_32 spinlock_st; + + io_rw_32 div_udividend; + io_rw_32 div_udivisor; + io_rw_32 div_sdividend; + io_rw_32 div_sdivisor; + + io_rw_32 div_quotient; + io_rw_32 div_remainder; + io_rw_32 div_csr; + + uint32_t _pad2; + + interp_hw_t interp[2]; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h new file mode 100644 index 00000000000..5b3b2bab5d5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +typedef struct { + io_rw_32 cr0; + io_rw_32 cr1; + io_rw_32 dr; + io_rw_32 sr; + io_rw_32 cpsr; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *const)SPI0_BASE) +#define spi1_hw ((spi_hw_t *const)SPI1_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h new file mode 100644 index 00000000000..80779fe6ba2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SSI_H +#define _HARDWARE_STRUCTS_SSI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/ssi.h" + +typedef struct { + io_rw_32 ctrlr0; + io_rw_32 ctrlr1; + io_rw_32 ssienr; + io_rw_32 mwcr; + io_rw_32 ser; + io_rw_32 baudr; + io_rw_32 txftlr; + io_rw_32 rxftlr; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sr; + io_rw_32 imr; + io_rw_32 isr; + io_rw_32 risr; + io_rw_32 txoicr; + io_rw_32 rxoicr; + io_rw_32 rxuicr; + io_rw_32 msticr; + io_rw_32 icr; + io_rw_32 dmacr; + io_rw_32 dmatdlr; + io_rw_32 dmardlr; + io_rw_32 idr; + io_rw_32 ssi_version_id; + io_rw_32 dr0; + uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; + io_rw_32 rx_sample_dly; + io_rw_32 spi_ctrlr0; + io_rw_32 txd_drive_edge; +} ssi_hw_t; + +#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h new file mode 100644 index 00000000000..0bfc7293c10 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/syscfg.h" + +typedef struct { + io_rw_32 proc0_nmi_mask; + io_rw_32 proc1_nmi_mask; + io_rw_32 proc_config; + io_rw_32 proc_in_sync_bypass; + io_rw_32 proc_in_sync_bypass_hi; + io_rw_32 dbgforce; + io_rw_32 mempowerdown; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h new file mode 100644 index 00000000000..3c999715282 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_rw_32 csr; + io_rw_32 rvr; + io_ro_32 cvr; + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h new file mode 100644 index 00000000000..e051a06970c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/timer.h" + +#define NUM_TIMERS 4 + +typedef struct { + io_wo_32 timehw; + io_wo_32 timelw; + io_ro_32 timehr; + io_ro_32 timelr; + io_rw_32 alarm[NUM_TIMERS]; + io_rw_32 armed; + io_ro_32 timerawh; + io_ro_32 timerawl; + io_rw_32 dbgpause; + io_rw_32 pause; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_ro_32 ints; +} timer_hw_t; + +#define timer_hw ((timer_hw_t *const)TIMER_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h new file mode 100644 index 00000000000..42fe8e88bf9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +typedef struct { + io_rw_32 dr; + io_rw_32 rsr; + uint32_t _pad0[4]; + io_rw_32 fr; + uint32_t _pad1; + io_rw_32 ilpr; + io_rw_32 ibrd; + io_rw_32 fbrd; + io_rw_32 lcr_h; + io_rw_32 cr; + io_rw_32 ifls; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *const)UART0_BASE) +#define uart1_hw ((uart_hw_t *const)UART1_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h new file mode 100644 index 00000000000..5c3c4533995 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26 +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 + +#define USB_DPRAM_SIZE 4096 + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); + +typedef struct { + io_rw_32 dev_addr_ctrl; + io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + io_rw_32 main_ctrl; + io_rw_32 sof_rw; + io_ro_32 sof_rd; + io_rw_32 sie_ctrl; + io_rw_32 sie_status; + io_rw_32 int_ep_ctrl; + io_rw_32 buf_status; + io_rw_32 buf_cpu_should_handle; // for double buff + io_rw_32 abort; + io_rw_32 abort_done; + io_rw_32 ep_stall_arm; + io_rw_32 nak_poll; + io_rw_32 ep_nak_stall_status; + io_rw_32 muxing; + io_rw_32 pwr; + io_rw_32 phy_direct; + io_rw_32 phy_direct_override; + io_rw_32 phy_trim; + io_rw_32 linestate_tuning; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} usb_hw_t; + +check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h new file mode 100644 index 00000000000..9956d683152 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/vreg_and_chip_reset.h" + +typedef struct { + io_rw_32 vreg; + io_rw_32 bod; + io_rw_32 chip_reset; +} vreg_and_chip_reset_hw_t; + +#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h new file mode 100644 index 00000000000..2cf05f19d1e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/watchdog.h" + +typedef struct { + io_rw_32 ctrl; + io_wo_32 load; + io_ro_32 reason; + io_rw_32 scratch[8]; + io_rw_32 tick; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h new file mode 100644 index 00000000000..bfa5b1c0cb4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H +#define _HARDWARE_STRUCTS_XIP_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 flush; + io_rw_32 stat; + io_rw_32 ctr_hit; + io_rw_32 ctr_acc; + io_rw_32 stream_addr; + io_rw_32 stream_ctr; + io_rw_32 stream_fifo; +} xip_ctrl_hw_t; + +#define XIP_STAT_FIFO_FULL 0x4u +#define XIP_STAT_FIFO_EMPTY 0x2u +#define XIP_STAT_FLUSH_RDY 0x1u + +#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h new file mode 100644 index 00000000000..698e6a2ff2c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/xosc.h" + +/// \tag::xosc_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 status; + io_rw_32 dormant; + io_rw_32 startup; + io_rw_32 _reserved[3]; + io_rw_32 count; +} xosc_hw_t; + +#define xosc_hw ((xosc_hw_t *const)XOSC_BASE) +/// \end::xosc_hw[] + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake new file mode 100644 index 00000000000..76126602fea --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake @@ -0,0 +1,59 @@ +# include targets for all for PICO on device + +enable_language(ASM) + +function(pico_add_hex_output TARGET) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.hex) +endfunction() + +function(pico_add_bin_output TARGET) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.bin) +endfunction() + +function(pico_add_dis_output TARGET) + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJDUMP} -h ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >${TARGET}.dis + COMMAND ${CMAKE_OBJDUMP} -d ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >>${TARGET}.dis + ) +endfunction() + +function(pico_add_extra_outputs TARGET) + pico_add_hex_output(${TARGET}) + pico_add_bin_output(${TARGET}) + pico_add_dis_output(${TARGET}) + + # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't defined PICO_TARGET_NAME, type=bool, default=0, group=build + # PICO_BUILD_DEFINE: PICO_TARGET_NAME, The name of the build target being compiled (unless PICO_NO_TARGET_NAME set in build), type=string, default=target name, group=build + if (NOT PICO_NO_TARGET_NAME) + target_compile_definitions(${TARGET} PRIVATE + PICO_TARGET_NAME="${TARGET}" + ) + endif() + + if (PICO_SYMLINK_ELF_AS_FILENAME) + add_custom_target(${TARGET}_symlinked) + add_dependencies(${TARGET}_symlinked ${TARGET}) + + add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD + COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}" + COMMAND ln -s -r ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} "${PICO_SYMLINK_ELF_AS_FILENAME}" + COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}${CMAKE_EXECUTABLE_SUFFIX}" + ) + endif () + # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build + if (NOT PICO_NO_UF2) + pico_add_uf2_output(${TARGET}) + endif() +endfunction() + +add_subdirectory(common) +add_subdirectory(rp2_common) + +# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device, type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build +# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device, type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build +set(PICO_NO_HARDWARE "0" CACHE INTERNAL "") +# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device, type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build +# PICO_BUILD_DEFIN: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device, type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build +set(PICO_ON_DEVICE "1" CACHE INTERNAL "") + +set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt new file mode 100644 index 00000000000..ae0561fd7fe --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt @@ -0,0 +1,71 @@ +option(PICO_NO_FLASH "Default binaries to not not use flash") +option(PICO_COPY_TO_RAM "Default binaries to Copy code to RAM when booting from flash") + +set(CMAKE_EXECUTABLE_SUFFIX .elf) + +pico_add_subdirectory(hardware_base) +pico_add_subdirectory(hardware_claim) +# HAL items which expose a public (inline) functions/macro API above the raw hardware +pico_add_subdirectory(hardware_adc) +pico_add_subdirectory(hardware_clocks) +pico_add_subdirectory(hardware_dma) +pico_add_subdirectory(hardware_divider) +pico_add_subdirectory(hardware_flash) +pico_add_subdirectory(hardware_gpio) +pico_add_subdirectory(hardware_i2c) +pico_add_subdirectory(hardware_interp) +pico_add_subdirectory(hardware_irq) +pico_add_subdirectory(hardware_pio) +pico_add_subdirectory(hardware_pll) +pico_add_subdirectory(hardware_pwm) +pico_add_subdirectory(hardware_resets) +pico_add_subdirectory(hardware_rtc) +pico_add_subdirectory(hardware_spi) +pico_add_subdirectory(hardware_sync) +pico_add_subdirectory(hardware_timer) +pico_add_subdirectory(hardware_uart) +pico_add_subdirectory(hardware_vreg) +pico_add_subdirectory(hardware_watchdog) +pico_add_subdirectory(hardware_xosc) + +# Helper functions to connect to data/functions in the bootrom +pico_add_subdirectory(pico_bootrom) +pico_add_subdirectory(pico_platform) + +if (NOT PICO_BARE_METAL) + # NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS + pico_add_subdirectory(boot_stage2) + + pico_add_subdirectory(pico_multicore) + pico_add_subdirectory(pico_unique_id) + + pico_add_subdirectory(pico_bit_ops) + pico_add_subdirectory(pico_divider) + pico_add_subdirectory(pico_double) + pico_add_subdirectory(pico_int64_ops) + pico_add_subdirectory(pico_float) + pico_add_subdirectory(pico_mem_ops) + pico_add_subdirectory(pico_malloc) + pico_add_subdirectory(pico_printf) + + pico_add_subdirectory(pico_stdio) + pico_add_subdirectory(pico_stdio_semihosting) + pico_add_subdirectory(pico_stdio_uart) + + pico_add_subdirectory(tinyusb) + pico_add_subdirectory(pico_stdio_usb) + + pico_add_subdirectory(pico_stdlib) + + pico_add_subdirectory(pico_cxx_options) + pico_add_subdirectory(pico_standard_link) + + pico_add_subdirectory(pico_fix) + + pico_add_subdirectory(pico_runtime) + +endif() + +set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE) + +pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/README.md b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/README.md new file mode 100644 index 00000000000..b89380100dd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/README.md @@ -0,0 +1,8 @@ +This directory contains libraries specifically targeting the RP2040 or possible future related devices. It is selected when +`PICO_PLATFORM=rp2040` (the default) is specified for the build + +`hardware_` libraries exist for individual hardware components to provide a simple API +providing a thin abstraction hiding the details of accessing the hardware registers directly. + +`pico_` provides higher level functionality you might generally find in say an OS kernel, as well +as runtime support familiar to most C programmers. diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt new file mode 100644 index 00000000000..454e11cf83f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt @@ -0,0 +1,68 @@ +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default stage2 file to use unless overridden by pico_set_boot_stage2 on the TARGET, type=bool, default=.../boot2_w25q080.S, group=build +if (NOT PICO_DEFAULT_BOOT_STAGE2_FILE) + set(PICO_DEFAULT_BOOT_STAGE2_FILE "${CMAKE_CURRENT_LIST_DIR}/boot2_w25q080.S") +endif() + +set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot_stage2 source file" FORCE) + +if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE}) + message(FATAL_ERROR "Specified boot_stage2 source '${PICO_BOOT_STAGE2_FILE}' does not exist.") +endif() + +# needed by function below +set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") + +function(pico_define_boot_stage2 NAME SOURCES) + add_executable(${NAME} + ${SOURCES} + ) + + # todo bit of an abstraction failure - revisit for Clang support anyway + if (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${NAME} PRIVATE "-nostdlib") + else () + target_link_options(${NAME} PRIVATE "--specs=nosys.specs") + target_link_options(${NAME} PRIVATE "-nostartfiles") + endif () + + # boot2_helpers include dir + target_include_directories(${NAME} PRIVATE ${PICO_BOOT_STAGE2_DIR}/asminclude) + + target_link_libraries(${NAME} hardware_regs) + target_link_options(${NAME} PRIVATE "LINKER:--script=${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld") + set_target_properties(${NAME} PROPERTIES LINK_DEPENDS ${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld) + + pico_add_dis_output(${NAME}) + pico_add_map_output(${NAME}) + + set(ORIGINAL_BIN ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.bin) + set(PADDED_CHECKSUMMED_ASM ${CMAKE_CURRENT_BINARY_DIR}/${NAME}_padded_checksummed.S) + + find_package (Python3 REQUIRED COMPONENTS Interpreter) + + add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN}) + add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${ORIGINAL_BIN}) + + add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM}) + add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN} + COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM} + ) + + + add_library(${NAME}_library INTERFACE) + add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm) + # not strictly (or indeed actually) a link library, but this avoids dependency cycle + target_link_libraries(${NAME}_library INTERFACE ${PADDED_CHECKSUMMED_ASM}) +endfunction() + +macro(pico_set_boot_stage2 TARGET NAME) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BOOT_STAGE2 "${NAME}") + else() + message(FATAL_ERROR "boot stage2 implementation must be set on executable not library") + endif() +endmacro() + +pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE}) + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S new file mode 100644 index 00000000000..6f06fc1d78a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2 +#define _BOOT2_HELPER_EXIT_FROM_BOOT2 + +#include "hardware/regs/m0plus.h" + +// If entered from the bootrom, lr (which we earlier pushed) will be 0, +// and we vector through the table at the start of the main flash image. +// Any regular function call will have a nonzero value for lr. +check_return: + pop {r0} + cmp r0, #0 + beq vector_into_flash + bx r0 +vector_into_flash: + ldr r0, =(XIP_BASE + 0x100) + ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET) + str r0, [r1] + ldmia r0, {r0, r1} + msr msp, r0 + bx r1 + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S new file mode 100644 index 00000000000..83698ed601b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_READ_FLASH_SREG +#define _BOOT2_HELPER_READ_FLASH_SREG + +#include "boot2_helpers/wait_ssi_ready.S" + +// Pass status read cmd into r0. +// Returns status value in r0. +.global read_flash_sreg +.type read_flash_sreg,%function +.thumb_func +read_flash_sreg: + push {r1, lr} + str r0, [r3, #SSI_DR0_OFFSET] + // Dummy byte: + str r0, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + // Discard first byte and combine the next two + ldr r0, [r3, #SSI_DR0_OFFSET] + ldr r0, [r3, #SSI_DR0_OFFSET] + + pop {r1, pc} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S new file mode 100644 index 00000000000..2e49b6489d0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_WAIT_SSI_READY +#define _BOOT2_HELPER_WAIT_SSI_READY + +wait_ssi_ready: + push {r0, r1, lr} + + // Command is complete when there is nothing left to send + // (TX FIFO empty) and SSI is no longer busy (CSn deasserted) +1: + ldr r1, [r3, #SSI_SR_OFFSET] + movs r0, #SSI_SR_TFE_BITS + tst r1, r0 + beq 1b + movs r0, #SSI_SR_BUSY_BITS + tst r1, r0 + bne 1b + + pop {r0, r1, pc} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_generic_03h.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_generic_03h.S new file mode 100644 index 00000000000..a10e66abdfd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_generic_03h.S @@ -0,0 +1,103 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Anything which responds to 03h serial read command +// +// Details: * Configure SSI to translate each APB read into a 03h command +// * 8 command clocks, 24 address clocks and 32 data clocks +// * This enables you to boot from almost anything: you can pretty +// much solder a potato to your PCB, or a piece of cheese +// * The tradeoff is performance around 3x worse than QSPI XIP +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + +#define CMD_READ 0x03 + +// Value is number of address bits divided by 4 +#define ADDR_L 6 + +#define CTRLR0_XIP \ + (SSI_CTRLR0_SPI_FRF_VALUE_STD << SSI_CTRLR0_SPI_FRF_LSB) | /* Standard 1-bit SPI serial frames */ \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 clocks per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ << SSI_CTRLR0_TMOD_LSB) /* Send instr + addr, receive data */ + +#define SPI_CTRLR0_XIP \ + (CMD_READ << SSI_SPI_CTRLR0_XIP_CMD_LSB) | /* Value of instruction prefix */ \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (2 << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8 bit command prefix (field value is bits divided by 4) */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) /* command and address both in serial format */ + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.cpu cortex-m0 +.thumb + +.section .text + +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + + ldr r3, =XIP_SSI_BASE // Use as base address where possible + + // Disable SSI to allow further config + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + mov r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + + ldr r1, =(CTRLR0_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + // NDF=0 (single 32b read) + mov r1, #0x0 + str r1, [r3, #SSI_CTRLR1_OFFSET] + + // Re-enable SSI + mov r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + +// We are now in XIP mode. Any bus accesses to the XIP address window will be +// translated by the SSI into 03h read commands to the external flash (if cache is missed), +// and the data will be returned to the bus. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_is25lp080.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_is25lp080.S new file mode 100644 index 00000000000..80bf9d1100d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_is25lp080.S @@ -0,0 +1,262 @@ +// ---------------------------------------------------------------------------- +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: ISSI IS25LP080D +// Based on W25Q080 code: main difference is the QE bit being in +// SR1 instead of SR2. +// +// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register to determine if QSPI mode is enabled, +// and perform an SR programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Set VTOR = 0x10000100 (user vector table immediately after +// this boot2 image). +// * Read stack pointer (MSP) and reset vector from the flash +// vector table; set SP and jump, as though the processor had +// booted directly from flash. +// +// Building: * This code must be linked to run at 0x20027f00 +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0xa0 + +// The number of address + mode bits, divided by 4 (always 4, not function of +// interface width). +#define ADDR_L 8 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_WRITE_STATUS 0x01 +#define SREG_DATA 0x40 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.cpu cortex-m0 +.thumb + +.section .text + +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + + ldr r3, =XIP_SSI_BASE // Use as base address where possible + + // Disable SSI to allow further config + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + mov r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + mov r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating + ldr r0, =CMD_READ_STATUS + bl read_flash_sreg + ldr r2, =SREG_DATA + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + mov r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes + mov r1, #CMD_WRITE_STATUS + str r1, [r3, #SSI_DR0_OFFSET] + mov r0, #0 + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Poll status register for write completion +1: + ldr r0, =CMD_READ_STATUS + bl read_flash_sreg + mov r1, #1 + tst r0, r1 + bne 1b + +skip_sreg_programming: + + // Send a 0xA3 high-performance-mode instruction +// ldr r1, =0xa3 +// str r1, [r3, #SSI_DR0_OFFSET] +// bl wait_ssi_ready + + // Disable SSI again so that it can be reconfigured + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + + +// First we need to send the initial command to get us in to Fast Read Quad I/O +// mode. As this transaction requires a command, we can't send it in XIP mode. +// To enter Continuous Read mode as well we need to append 4'b0010 to the address +// bits and then add a further 4 don't care bits. We will construct this by +// specifying a 28-bit address, with the least significant bits being 4'b0010. +// This is just a dummy transaction so we'll perform a read from address zero +// and then discard what comes back. All we really care about is that at the +// end of the transaction, the flash device is in Continuous Read mode +// and from then on will only expect to receive addresses. +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + mov r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + mov r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + mov r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + mov r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// At this point CN# will be deasserted and the SPI clock will not be running. +// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and +// only expecting address bits after the next CN# assertion. So long as we +// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address +// then the Winbond device will remain in continuous read mode. This is the +// ideal mode for Execute-In-Place. +// (If we want to exit continuous read mode then we will need to switch back +// to APM mode and generate a 28-bit address phase with the extra nibble set +// to 4'b0000). + + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + mov r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// We are now in XIP mode, with all transactions using Dual I/O and only +// needing to send 24-bit addresses (plus mode bits) for each read transaction. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_usb_blinky.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_usb_blinky.S new file mode 100644 index 00000000000..74c47a3ec12 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_usb_blinky.S @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Stub second stage which calls into USB bootcode, with parameters. +// USB boot takes two parameters: +// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all +// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot +// The bootrom passes 0 for both of these parameters, but user code (or this +// second stage) can pass anything. + +#define USB_BOOT_MSD_AND_PICOBOOT 0x0 +#define USB_BOOT_MSD_ONLY 0x2 +#define USB_BOOT_PICOBOOT_ONLY 0x1 + +// Config +#define ACTIVITY_LED 0 +#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT + +.cpu cortex-m0 +.thumb + +.section .text + +.global _stage2_boot +.type _stage2_boot,%function + +.thumb_func +_stage2_boot: + mov r7, #0x14 // Pointer to _well_known pointer table in ROM + ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table + ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine + ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot + blx r7 + cmp r0, #0 + beq dead + + mov r7, r0 + ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use + mov r1, #BOOT_MODE + blx r7 + +dead: + wfi + b dead + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25q080.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25q080.S new file mode 100644 index 00000000000..ad3238e286a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25q080.S @@ -0,0 +1,287 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Winbond W25Q080 +// Also supports W25Q16JV (which has some different SR instructions) +// Also supports AT25SF081 +// Also supports S25FL132K0 +// +// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register 2 to determine if QSPI mode is enabled, +// and perform an SR2 programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Jump to exit pointer passed in via lr. Bootrom passes null, +// in which case this code uses a default 256 byte flash offset +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" +#include "hardware/regs/pads_qspi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif +#if PICO_FLASH_SPI_CLKDIV & 1 +#error PICO_FLASH_SPI_CLKDIV must be even +#endif + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0xa0 + +// The number of address + mode bits, divided by 4 (always 4, not function of +// interface width). +#define ADDR_L 8 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to +// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS2 0x35 +#define CMD_WRITE_STATUS 0x01 +#define SREG_DATA 0x02 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.syntax unified +.cpu cortex-m0plus +.thumb + +.section .text + +// The exit point is passed in lr. If entered from bootrom, this will be the +// flash address immediately following this second stage (0x10000100). +// Otherwise it will be a return address -- second stage being called as a +// function by user code, after copying out of XIP region. r3 holds SSI base, +// r0...2 used as temporaries. Other GPRs not used. +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + + // Set pad configuration: + // - SCLK 8mA drive, no slew limiting + // - SDx disable input Schmitt to reduce delay + + ldr r3, =PADS_QSPI_BASE + movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] + ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + bics r0, r1 + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] + + ldr r3, =XIP_SSI_BASE + + // Disable SSI to allow further config + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + + // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, + // if the flash launches data on SCLK posedge, we capture it at the time that + // the next SCLK posedge is launched. This is shortly before that posedge + // arrives at the flash, so data hold time should be ok. For + // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. + + movs r1, #1 + movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance + str r1, [r3, r2] + + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating + movs r0, #CMD_READ_STATUS2 + bl read_flash_sreg + movs r2, #SREG_DATA + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + movs r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes + movs r1, #CMD_WRITE_STATUS + str r1, [r3, #SSI_DR0_OFFSET] + movs r0, #0 + str r0, [r3, #SSI_DR0_OFFSET] + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Poll status register for write completion +1: + movs r0, #CMD_READ_STATUS + bl read_flash_sreg + movs r1, #1 + tst r0, r1 + bne 1b + +skip_sreg_programming: + + // Disable SSI again so that it can be reconfigured + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + +// Currently the flash expects an 8 bit serial command prefix on every +// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O +// command, with mode bits set such that the flash will not expect a serial +// command prefix on *subsequent* transfers. We don't care about the results +// of the read, the important part is the mode bits. + +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// The flash is in a state where we can blast addresses in parallel, and get +// parallel data back. Now configure the SSI to translate XIP bus accesses +// into QSPI transfers of this form. + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// Bus accesses to the XIP window will now be transparently serviced by the +// external flash on cache miss. We are ready to run code from flash. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25x10cl.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25x10cl.S new file mode 100644 index 00000000000..02628d4eb5d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_w25x10cl.S @@ -0,0 +1,196 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Winbond W25X10CL +// +// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode +// +// Details: * Disable SSI +// * Configure SSI to generate 8b command + 28b address + 2 wait, +// with address and data using dual SPI mode +// * Enable SSI +// * Generate dummy read with command = 0xBB, top 24b of address +// of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being +// generated by 2 wait cycles). This leaves the W25X10CL in +// continuous read mode +// * Disable SSI +// * Configure SSI to generate 0b command + 28b address + 2 wait, +// with the extra 4 bits of address LSB being 0x2 to keep the +// W25X10CL in continuous read mode forever +// * Enable SSI +// * Set VTOR = 0x10000100 +// * Read MSP reset vector from 0x10000100 and write to MSP (this +// will also enable XIP mode in the SSI wrapper) +// * Read PC reset vector from 0x10000104 and jump to it +// +// Building: * This code must be linked to run at 0x20000000 +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be an even number. +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + +// ---------------------------------------------------------------------------- +// The "System Control Block" is a set of internal Cortex-M0+ control registers +// that are memory mapped and accessed like any other H/W register. They have +// fixed addresses in the address map of every Cortex-M0+ system. +// ---------------------------------------------------------------------------- + +.equ SCB_VTOR, 0xE000ED08 // RW Vector Table Offset Register + +// ---------------------------------------------------------------------------- +// Winbond W25X10CL Supported Commands +// Taken from "w25x10cl_reg_021714.pdf" +// ---------------------------------------------------------------------------- + +.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb + +// ---------------------------------------------------------------------------- +// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Dual I/O" command sequence. +// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0] +// are don't care (we HiZ). Only M[5:4] are used, and they must be set +// to M[5:4] = 2'b10 to enable continuous read mode. +// ---------------------------------------------------------------------------- + +.equ W25X10CL_MODE_CONTINUOUS_READ, 0x20 + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.cpu cortex-m0 +.thumb + +.org 0 + +.section .text + +// This code will get copied to 0x20000000 and then executed + +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + ldr r3, =XIP_SSI_BASE // Use as base address where possible + +// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read + + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config + +// The Boot ROM sets a very conservative SPI clock frequency to be sure it can +// read the initial 256 bytes from any device. Here we can be more aggressive. + + mov r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock + +// First we need to send the initial command to get us in to Fast Read Dual I/O +// mode. As this transaction requires a command, we can't send it in XIP mode. +// To enter Continuous Read mode as well we need to append 4'b0010 to the address +// bits and then add a further 4 don't care bits. We will construct this by +// specifying a 28-bit address, with the least significant bits being 4'b0010. +// This is just a dummy transaction so we'll perform a read from address zero +// and then discard what comes back. All we really care about is that at the +// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode +// and from then on will only expect to receive addresses. + +#define CTRLR0_ENTER_XIP \ + (SSI_CTRLR0_SPI_FRF_VALUE_DUAL /* Dual I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + mov r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ + (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Dual I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + mov r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + mov r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + mov r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + +// Now we wait for the read transaction to complete by monitoring the SSI +// status register and checking for the "RX FIFO Not Empty" flag to assert. + + mov r1, #SSI_SR_RFNE_BITS +00: + ldr r0, [r3, #SSI_SR_OFFSET] // Read status register + tst r0, r1 // RFNE status flag set? + beq 00b // If not then wait + +// At this point CN# will be deasserted and the SPI clock will not be running. +// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and +// only expecting address bits after the next CN# assertion. So long as we +// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address +// then the Winbond device will remain in continuous read mode. This is the +// ideal mode for Execute-In-Place. +// (If we want to exit continuous read mode then we will need to switch back +// to APM mode and generate a 28-bit address phase with the extra nibble set +// to 4'b0000). + + mov r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD + +#define SPI_CTRLR0_XIP \ + (W25X10CL_MODE_CONTINUOUS_READ /* Mode bits to keep Winbond in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ + (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + mov r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// We are now in XIP mode, with all transactions using Dual I/O and only +// needing to send 24-bit addresses (plus mode bits) for each read transaction. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot_stage2.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot_stage2.ld new file mode 100644 index 00000000000..f8669ab64c0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot_stage2.ld @@ -0,0 +1,13 @@ +MEMORY { + /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom + stack. Note 4 bytes occupied by checksum. */ + SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252 +} + +SECTIONS { + . = ORIGIN(SRAM); + .text : { + *(.entry) + *(.text) + } >SRAM +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/doc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/doc.h new file mode 100644 index 00000000000..483dd682ffa --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup boot_stage2 boot_stage2 + * \brief Second stage boot loaders responsible for setting up external flash + */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/pad_checksum b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/pad_checksum new file mode 100755 index 00000000000..356227d589f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/pad_checksum @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 + +import argparse +import binascii +import struct +import sys + + +def any_int(x): + try: + return int(x, 0) + except: + raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x)) + + +def bitrev(x, width): + return int("{:0{w}b}".format(x, w=width)[::-1], 2) + + +parser = argparse.ArgumentParser() +parser.add_argument("ifile", help="Input file (binary)") +parser.add_argument("ofile", help="Output file (assembly)") +parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256", + type=any_int, default=256) +parser.add_argument("-s", "--seed", help="Checksum seed value, default 0", + type=any_int, default=0) +args = parser.parse_args() + +try: + idata = open(args.ifile, "rb").read() +except: + sys.exit("Could not open input file '{}'".format(args.ifile)) + +if len(idata) >= args.pad - 4: + sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad)) + +idata_padded = idata + bytes(args.pad - 4 - len(idata)) + +# Our bootrom CRC32 is slightly bass-ackward but it's best to work around for now (FIXME) +# 100% worth it to save two Thumb instructions +checksum = bitrev( + (binascii.crc32(bytes(bitrev(b, 8) for b in idata_padded), args.seed ^ 0xffffffff) ^ 0xffffffff) & 0xffffffff, 32) +odata = idata_padded + struct.pack("cs = ADC_CS_EN_BITS; + + // Internal staging completes in a few cycles, but poll to be sure + while (!(adc_hw->cs & ADC_CS_READY_BITS)) { + tight_loop_contents(); + } +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h new file mode 100644 index 00000000000..13d7c418f2b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_ADC_H_ +#define _HARDWARE_ADC_H_ + +#include "pico.h" +#include "hardware/structs/adc.h" +#include "hardware/gpio.h" + +/** \file hardware/adc.h + * \defgroup hardware_adc hardware_adc + * + * Analog to Digital Converter (ADC) API + * + * The RP2040 has an internal analogue-digital converter (ADC) with the following features: + * - SAR ADC + * - 500 kS/s (Using an independent 48MHz clock) + * - 12 bit (9.5 ENOB) + * - 5 input mux: + * - 4 inputs that are available on package pins shared with GPIO[29:26] + * - 1 input is dedicated to the internal temperature sensor + * - 4 element receive sample FIFO + * - Interrupt generation + * - DMA interface + * + * Although there is only one ADC you can specify the input to it using the adc_select_input() function. + * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read. + * + * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. + * + * Temperature sensor values can be approximated in centigrade as: + * + * T = 27 - (ADC_Voltage - 0.706)/0.001721 + * + * The FIFO, if used, can contain up to 4 entries. + * + * \subsection adc_example Example + * \addtogroup hardware_adc + * + * \include hello_adc.c + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADC, Enable/disable assertions in the ADC module, type=bool, default=0, group=hardware_adc +#ifndef PARAM_ASSERTIONS_ENABLED_ADC +#define PARAM_ASSERTIONS_ENABLED_ADC 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Initialise the ADC HW + * \ingroup hardware_adc + * + */ +void adc_init(void); + +/*! \brief Initialise the gpio for use as an ADC pin + * \ingroup hardware_adc + * + * Prepare a GPIO for use with ADC, by disabling all digital functions. + * + * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive. + */ +static inline void adc_gpio_init(uint gpio) { + invalid_params_if(ADC, gpio < 26 || gpio > 29); + // Select NULL function to make output driver hi-Z + gpio_set_function(gpio, GPIO_FUNC_NULL); + // Also disable digital pulls and digital receiver + gpio_disable_pulls(gpio); + gpio_set_input_enabled(gpio, false); +} + +/*! \brief ADC input select + * \ingroup hardware_adc + * + * Select an ADC input. 0...3 are GPIOs 26...29 respectively. + * Input 4 is the onboard temperature sensor. + * + * \param input Input to select. + */ +static inline void adc_select_input(uint input) { + invalid_params_if(ADC, input > 4); + hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS); +} + +/*! \brief Round Robin sampling selector + * \ingroup hardware_adc + * + * This function sets which inputs are to be run through in round robin mode. + * Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively) + * + * \param input_mask A bit pattern indicating which of the 5 inputs are to be sampled. Write a value of 0 to disable round robin sampling. + */ +static inline void adc_set_round_robin(uint input_mask) { + invalid_params_if(ADC, input_mask & ~ADC_CS_RROBIN_BITS); + hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS); +} + +/*! \brief Enable the onboard temperature sensor + * \ingroup hardware_adc + * + * \param enable Set true to power on the onboard temperature sensor, false to power off. + * + */ +static inline void adc_set_temp_sensor_enabled(bool enable) { + if (enable) + hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); + else + hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); +} + +/*! \brief Perform a single conversion + * \ingroup hardware_adc + * + * Performs an ADC conversion, waits for the result, and then returns it. + * + * \return Result of the conversion. + */ +static inline uint16_t adc_read(void) { + hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); + + while (!(adc_hw->cs & ADC_CS_READY_BITS)) + tight_loop_contents(); + + return adc_hw->result; +} + +/*! \brief Enable or disable free-running sampling mode + * \ingroup hardware_adc + * + * \param run false to disable, true to enable free running conversion mode. + */ +static inline void adc_run(bool run) { + if (run) + hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); + else + hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); +} + +/*! \brief Set the ADC Clock divisor + * \ingroup hardware_adc + * + * Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion, + * so any period less than that will be clamped to 96. + * + * \param clkdiv If non-zero, conversion will be started at intervals rather than back to back. + */ +static inline void adc_set_clkdiv(float clkdiv) { + invalid_params_if(ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1)); + adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB)); +} + +/*! \brief Setup the ADC FIFO + * \ingroup hardware_adc + * + * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped. + * + * \param en Enables write each conversion result to the FIFO + * \param dreq_en Enable DMA requests when FIFO contains data + * \param dreq_thresh Threshold for DMA requests/FIFO IRQ if enabled. + * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample + * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers. + */ +static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { + hw_write_masked(&adc_hw->fcs, + (!!en << ADC_FCS_EN_LSB) | + (!!dreq_en << ADC_FCS_DREQ_EN_LSB) | + (dreq_thresh << ADC_FCS_THRESH_LSB) | + (!!err_in_fifo << ADC_FCS_ERR_LSB) | + (!!byte_shift << ADC_FCS_SHIFT_LSB), + ADC_FCS_EN_BITS | + ADC_FCS_DREQ_EN_BITS | + ADC_FCS_THRESH_BITS | + ADC_FCS_ERR_BITS | + ADC_FCS_SHIFT_BITS + ); +} + +/*! \brief Check FIFO empty state + * \ingroup hardware_adc + * + * \return Returns true if the fifo is empty + */ +static inline bool adc_fifo_is_empty(void) { + return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS); +} + +/*! \brief Get number of entries in the ADC FIFO + * \ingroup hardware_adc + * + * The ADC FIFO is 4 entries long. This function will return how many samples are currently present. + */ +static inline uint8_t adc_fifo_get_level(void) { + return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB; +} + +/*! \brief Get ADC result from FIFO + * \ingroup hardware_adc + * + * Pops the latest result from the ADC FIFO. + */ +static inline uint16_t adc_fifo_get(void) { + return adc_hw->fifo; +} + +/*! \brief Wait for the ADC FIFO to have data. + * \ingroup hardware_adc + * + * Blocks until data is present in the FIFO + */ +static inline uint16_t adc_fifo_get_blocking(void) { + while (adc_fifo_is_empty()) + tight_loop_contents(); + return adc_hw->fifo; +} + +/*! \brief Drain the ADC FIFO + * \ingroup hardware_adc + * + * Will wait for any conversion to complete then drain the FIFO discarding any results. + */ +static inline void adc_fifo_drain(void) { + // Potentially there is still a conversion in progress -- wait for this to complete before draining + while (!(adc_hw->cs & ADC_CS_READY_BITS)) + tight_loop_contents(); + while (!adc_fifo_is_empty()) + (void) adc_fifo_get(); +} + +/*! \brief Enable/Disable ADC interrupts. + * \ingroup hardware_adc + * + * \param enabled Set to true to enable the ADC interrupts, false to disable + */ +static inline void adc_irq_set_enabled(bool enabled) { + adc_hw->inte = !!enabled; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/CMakeLists.txt new file mode 100644 index 00000000000..e045618fe26 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/CMakeLists.txt @@ -0,0 +1,3 @@ +add_library(hardware_base INTERFACE) +target_include_directories(hardware_base INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_link_libraries(hardware_base INTERFACE pico_base_headers) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h new file mode 100644 index 00000000000..6645fbdd0a1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_ADDRESS_MAPPED_H +#define _HARDWARE_ADDRESS_MAPPED_H + +#include "pico.h" +#include "hardware/regs/addressmap.h" + +/** \file address_mapped.h + * \defgroup hardware_base hardware_base + * + * Low-level types and (atomic) accessors for memory-mapped hardware registers + * + * `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included + * by default by all other hardware libraries. + * + * The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register. + * The register type names are formed by concatenating one from each of the 3 parts A, B, C + + * A | B | C | Meaning + * ------|---|---|-------- + * io_ | | | A Memory mapped IO register + *  |ro_| | read-only access + *  |rw_| | read-write access + *  |wo_| | write-only access (can't actually be enforced via C API) + *  | | 8| 8-bit wide access + *  | | 16| 16-bit wide access + *  | | 32| 32-bit wide access + * + * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write + * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`. + * + * RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within + * a hardware register so that concurrent access by two cores is always consistent with one atomic operation + * being performed first, followed by the second. + * + * See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register + * + * Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can + * get an alias to the entire structure such that writing any member (register) within the structure is equivalent + * to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()... + * + * For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller, + * leaving the other bits unchanged. + */ + +#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") +#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") + +typedef volatile uint32_t io_rw_32; +typedef const volatile uint32_t io_ro_32; +typedef volatile uint32_t io_wo_32; +typedef volatile uint16_t io_rw_16; +typedef const volatile uint16_t io_ro_16; +typedef volatile uint16_t io_wo_16; +typedef volatile uint8_t io_rw_8; +typedef const volatile uint8_t io_ro_8; +typedef volatile uint8_t io_wo_8; + +typedef volatile uint8_t *const ioptr; +typedef ioptr const const_ioptr; + +// Untyped conversion alias pointer generation macros +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr))) + +// Typed conversion alias pointer generation macros +#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) +#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) +#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) + +/*! \brief Atomically set the specified bits to 1 in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to set + */ +inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Atomically clear the specified bits to 0 in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to clear + */ +inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Atomically flip the specified bits in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to invert + */ +inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Set new values for a sub-set of the bits in a HW register + * \ingroup hardware_base + * + * Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set + * + * Note: this method allows safe concurrent modification of *different* bits of + * a register, but multiple concurrent access to the same bits is still unsafe. + * + * \param addr Address of writable register + * \param values Bits values + * \param write_mask Mask of bits to change + */ +inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { + hw_xor_bits(addr, (*addr ^ values) & write_mask); +} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt new file mode 100644 index 00000000000..33213fa2c1a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt @@ -0,0 +1,6 @@ +add_library(hardware_claim INTERFACE) +target_include_directories(hardware_claim INTERFACE include) +target_sources(hardware_claim INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/claim.c) + +target_link_libraries(hardware_claim INTERFACE hardware_sync) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c new file mode 100644 index 00000000000..2c5c8eda21c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/claim.h" + +uint32_t hw_claim_lock() { + return spin_lock_blocking(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM)); +} + +void hw_claim_unlock(uint32_t save) { + spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save); +} + +bool hw_is_claimed(uint8_t *bits, uint bit_index) { + bool rc; + uint32_t save = hw_claim_lock(); + if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) { + rc = false; + } else { + bits[bit_index >> 3u] |= (1u << (bit_index & 7u)); + rc = true; + } + hw_claim_unlock(save); + return rc; +} + +void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) { + uint32_t save = hw_claim_lock(); + if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) { + panic(message, bit_index); + } else { + bits[bit_index >> 3u] |= (1u << (bit_index & 7u)); + } + hw_claim_unlock(save); +} + +int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message) { + // don't bother check lsb / msb order as if wrong, then it'll fail anyway + uint32_t save = hw_claim_lock(); + int found_bit = -1; + for(uint bit=bit_lsb; bit <= bit_msb; bit++) { + if (!(bits[bit >> 3u] & (1u << (bit & 7u)))) { + bits[bit >> 3u] |= (1u << (bit & 7u)); + found_bit = bit; + break; + } + } + hw_claim_unlock(save); + if (found_bit < 0 && required) { + panic(message); + } + return found_bit; +} + +void hw_claim_clear(uint8_t *bits, uint bit_index) { + uint32_t save = hw_claim_lock(); + assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u))); + bits[bit_index >> 3u] &= ~(1u << (bit_index & 7u)); + hw_claim_unlock(save); +} + + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h new file mode 100644 index 00000000000..0c055135570 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_CLAIM_H +#define _HARDWARE_CLAIM_H + +#include "pico.h" +#include "hardware/sync.h" + +/** \file claim.h + * \defgroup hardware_claim hardware_claim + * + * Lightweight hardware resource management + * + * `hardware_claim` provides a simple API for management of hardware resources at runtime. + * + * This API is usually called by other hardware specific _claiming_ APIs and provides simple + * multi-core safe methods to manipulate compact bit-sets representing hardware resources. + * + * This API allows any other library to cooperatively participate in a scheme by which + * both compile time and runtime allocation of resources can co-exist, and conflicts + * can be avoided or detected (depending on the use case) without the libraries having + * any other knowledge of each other. + * + * Facilities are providing for: + * + * 1. Claiming resources (and asserting if they are already claimed) + * 2. Freeing (unclaiming) resources + * 3. Finding unused resources + */ + +/*! \brief Atomically claim a resource, panicking if it is already in use + * \ingroup hardware_claim + * + * The resource ownership is indicated by the bit_index bit in an array of bits. + * + * \param bits pointer to an array of bits (8 bits per byte) + * \param bit_index resource to claim (bit index into array of bits) + * \param message string to display if the bit cannot be claimed; note this may have a single printf format "%d" for the bit + */ +void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message); + +/*! \brief Atomically claim one resource out of a range of resources, optionally asserting if none are free + * \ingroup hardware_claim + * + * \param bits pointer to an array of bits (8 bits per byte) + * \param required true if this method should panic if the resource is not free + * \param bit_lsb the lower bound (inclusive) of the resource range to claim from + * \param bit_msb the upper bound (inclusive) of the resource range to claim from + * \param message string to display if the bit cannot be claimed + * \return the bit index representing the claimed or -1 if none are available in the range, and required = false + */ +int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message); + +/*! \brief Determine if a resource is claimed at the time of the call + * \ingroup hardware_claim + * + * The resource ownership is indicated by the bit_index bit in an array of bits. + * + * \param bits pointer to an array of bits (8 bits per byte) + * \param bit_index resource to unclaim (bit index into array of bits) + * \return true if the resource is claimed + */ +bool hw_is_claimed(uint8_t *bits, uint bit_index); + +/*! \brief Atomically unclaim a resource + * \ingroup hardware_claim + * + * The resource ownership is indicated by the bit_index bit in an array of bits. + * + * \param bits pointer to an array of bits (8 bits per byte) + * \param bit_index resource to unclaim (bit index into array of bits) + */ +void hw_claim_clear(uint8_t *bits, uint bit_index); + +/*! \brief Acquire the runtime mutual exclusion lock provided by the `hardware_claim` library + * \ingroup hardware_claim + * + * This method is called automatically by the other `hw_claim_` methods, however it is provided as a convenience + * to code that might want to protect other hardware initialization code from concurrent use. + * + * \note hw_claim_lock() uses a spin lock internally, so disables interrupts on the calling core, and will deadlock + * if the calling core already owns the lock. + * + * \return a token to pass to hw_claim_unlock() + */ +uint32_t hw_claim_lock(); + +/*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library + * \ingroup hardware_claim + * + * \note This method MUST be called from the same core that call hw_claim_lock() + * + * \param token the token returned by the corresponding call to hw_claim_lock() + */ +void hw_claim_unlock(uint32_t token); + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt new file mode 100644 index 00000000000..3718d833cc5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt @@ -0,0 +1,11 @@ +pico_simple_hardware_target(clocks) + +target_link_libraries(hardware_clocks INTERFACE + hardware_resets + hardware_watchdog + hardware_xosc + hardware_pll + # not currently used by clocks.c, but sensibly bundled here + # as changing frequencies may require upping voltage + hardware_vreg +) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c new file mode 100644 index 00000000000..6195dcd5756 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "hardware/regs/clocks.h" +#include "hardware/platform_defs.h" +#include "hardware/resets.h" +#include "hardware/clocks.h" +#include "hardware/watchdog.h" +#include "hardware/pll.h" +#include "hardware/xosc.h" +#include "hardware/irq.h" +#include "hardware/gpio.h" + +check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET); +check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET); +check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET); + +static uint32_t configured_freq[CLK_COUNT]; + +static resus_callback_t _resus_callback; + +// Clock muxing consists of two components: +// - A glitchless mux, which can be switched freely, but whose inputs must be +// free-running +// - An auxiliary (glitchy) mux, whose output glitches when switched, but has +// no constraints on its inputs +// Not all clocks have both types of mux. +static inline bool has_glitchless_mux(enum clock_index clk_index) { + return clk_index == clk_sys || clk_index == clk_ref; +} + +void clock_stop(enum clock_index clk_index) { + clock_hw_t *clock = &clocks_hw->clk[clk_index]; + hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); + configured_freq[clk_index] = 0; +} + +/// \tag::clock_configure[] +bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) { + uint32_t div; + + assert(src_freq >= freq); + + if (freq > src_freq) + return false; + + // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8) + div = (uint32_t) (((uint64_t) src_freq << 8) / freq); + + clock_hw_t *clock = &clocks_hw->clk[clk_index]; + + // If increasing divisor, set divisor before source. Otherwise set source + // before divisor. This avoids a momentary overspeed when e.g. switching + // to a faster source and increasing divisor to compensate. + if (div > clock->div) + clock->div = div; + + // If switching a glitchless slice (ref or sys) to an aux source, switch + // away from aux *first* to avoid passing glitches when changing aux mux. + // Assume (!!!) glitchless source 0 is no faster than the aux source. + if (has_glitchless_mux(clk_index) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) { + hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (!(clock->selected & 1u)) + tight_loop_contents(); + } + // If no glitchless mux, cleanly stop the clock to avoid glitches + // propagating when changing aux mux. Note it would be a really bad idea + // to do this on one of the glitchless clocks (clk_sys, clk_ref). + else { + hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + if (configured_freq[clk_index] > 0) { + // Delay for 3 cycles of the target clock, for ENABLE propagation. + // Note XOSC_COUNT is not helpful here because XOSC is not + // necessarily running, nor is timer... so, 3 cycles per loop: + uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1; + asm volatile ( + "1: \n\t" + "sub %0, #1 \n\t" + "bne 1b" + : "+r" (delay_cyc) + ); + } + } + + // Set aux mux first, and then glitchless mux if this clock has one + hw_write_masked(&clock->ctrl, + (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), + CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS + ); + + if (has_glitchless_mux(clk_index)) { + hw_write_masked(&clock->ctrl, + src << CLOCKS_CLK_REF_CTRL_SRC_LSB, + CLOCKS_CLK_REF_CTRL_SRC_BITS + ); + while (!(clock->selected & (1u << src))) + tight_loop_contents(); + } + + hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + + // Now that the source is configured, we can trust that the user-supplied + // divisor is a safe value. + clock->div = div; + + // Store the configured frequency + configured_freq[clk_index] = freq; + + return true; +} +/// \end::clock_configure[] + +void clocks_init(void) { + // Start tick in watchdog + watchdog_start_tick(XOSC_MHZ); + + // Everything is 48MHz on FPGA apart from RTC. Otherwise set to 0 and will be set in clock configure + if (running_on_fpga()) { + for (uint i = 0; i < CLK_COUNT; i++) { + configured_freq[i] = 48 * MHZ; + } + configured_freq[clk_rtc] = 46875; + return; + } + + // Disable resus that may be enabled from previous software + clocks_hw->resus.ctrl = 0; + + // Enable the xosc + xosc_init(); + + // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. + hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); + while (clocks_hw->clk[clk_sys].selected != 0x1) + tight_loop_contents(); + hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (clocks_hw->clk[clk_ref].selected != 0x1) + tight_loop_contents(); + + /// \tag::pll_settings[] + // Configure PLLs + // REF FBDIV VCO POSTDIV + // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz + // PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz + /// \end::pll_settings[] + + reset_block(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS); + unreset_block_wait(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS); + + /// \tag::pll_init[] + pll_init(pll_sys, 1, 1500 * MHZ, 6, 2); + pll_init(pll_usb, 1, 480 * MHZ, 5, 2); + /// \end::pll_init[] + + // Configure clocks + // CLK_REF = XOSC (12MHz) / 1 = 12MHz + clock_configure(clk_ref, + CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, + 0, // No aux mux + 12 * MHZ, + 12 * MHZ); + + /// \tag::configure_clk_sys[] + // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz + clock_configure(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, + 125 * MHZ, + 125 * MHZ); + /// \end::configure_clk_sys[] + + // CLK USB = PLL USB (48MHz) / 1 = 48MHz + clock_configure(clk_usb, + 0, // No GLMUX + CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 48 * MHZ); + + // CLK ADC = PLL USB (48MHZ) / 1 = 48MHz + clock_configure(clk_adc, + 0, // No GLMUX + CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 48 * MHZ); + + // CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz + clock_configure(clk_rtc, + 0, // No GLMUX + CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 46875); + + // CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable + // Normally choose clk_sys or clk_usb + clock_configure(clk_peri, + 0, + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, + 125 * MHZ, + 125 * MHZ); +} + +/// \tag::clock_get_hz[] +uint32_t clock_get_hz(enum clock_index clk_index) { + return configured_freq[clk_index]; +} +/// \end::clock_get_hz[] + +void clock_set_reported_hz(enum clock_index clk_index, uint hz) { + configured_freq[clk_index] = hz; +} + +/// \tag::frequency_count_khz[] +uint32_t frequency_count_khz(uint src) { + fc_hw_t *fc = &clocks_hw->fc0; + + // If frequency counter is running need to wait for it. It runs even if the source is NULL + while(fc->status & CLOCKS_FC0_STATUS_RUNNING_BITS) { + tight_loop_contents(); + } + + // Set reference freq + fc->ref_khz = clock_get_hz(clk_ref) / 1000; + + // FIXME: Don't pick random interval. Use best interval + fc->interval = 10; + + // No min or max + fc->min_khz = 0; + fc->max_khz = 0xffffffff; + + // Set SRC which automatically starts the measurement + fc->src = src; + + while(!(fc->status & CLOCKS_FC0_STATUS_DONE_BITS)) { + tight_loop_contents(); + } + + // Return the result + return fc->result >> CLOCKS_FC0_RESULT_KHZ_LSB; +} +/// \end::frequency_count_khz[] + +static void clocks_handle_resus(void) { + // Set clk_sys back to the ref clock rather than it being forced to clk_ref + // by resus. Call the user's resus callback if they have set one + + // CLK SYS = CLK_REF. Must be running for this code to be running + uint clk_ref_freq = clock_get_hz(clk_ref); + clock_configure(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, + 0, + clk_ref_freq, + clk_ref_freq); + + // Assert we have been resussed + assert(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS); + + // Now we have fixed clk_sys we can safely remove the resus + hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); + hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); + + // Now we should no longer be resussed + assert(!(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS)); + + // Call the user's callback to notify them of the resus event + if (_resus_callback) { + _resus_callback(); + } +} + +static void clocks_irq_handler(void) { + // Clocks interrupt handler. Only resus but handle irq + // defensively just in case. + uint32_t ints = clocks_hw->ints; + + if (ints & CLOCKS_INTE_CLK_SYS_RESUS_BITS) { + ints &= ~CLOCKS_INTE_CLK_SYS_RESUS_BITS; + clocks_handle_resus(); + } + +#ifndef NDEBUG + if (ints) { + panic("Unexpected clocks irq\n"); + } +#endif +} + +void clocks_enable_resus(resus_callback_t resus_callback) { + // Restart clk_sys if it is stopped by forcing it + // to the default source of clk_ref. If clk_ref stops running this will + // not work. + + // Store user's resus callback + _resus_callback = resus_callback; + + irq_set_exclusive_handler(CLOCKS_IRQ, clocks_irq_handler); + + // Enable the resus interrupt in clocks + clocks_hw->inte = CLOCKS_INTE_CLK_SYS_RESUS_BITS; + + // Enable the clocks irq + irq_set_enabled(CLOCKS_IRQ, true); + + // 2 * clk_ref freq / clk_sys_min_freq; + // assume clk_ref is 3MHz and we want clk_sys to be no lower than 1MHz + uint timeout = 2 * 3 * 1; + + // Enable resus with the maximum timeout + clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout; +} + +void clock_gpio_init(uint gpio, uint src, uint div) { + // Bit messy but it's as much code to loop through a lookup + // table. The sources for each gpout generators are the same + // so just call with the sources from GP0 + uint gpclk = 0; + if (gpio == 21) gpclk = clk_gpout0; + else if (gpio == 23) gpclk = clk_gpout1; + else if (gpio == 24) gpclk = clk_gpout2; + else if (gpio == 26) gpclk = clk_gpout3; + else { + invalid_params_if(CLOCKS, true); + } + + // Set up the gpclk generator + clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) | + CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS; + clocks_hw->clk[gpclk].div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB; + + // Set gpio pin to gpclock function + gpio_set_function(gpio, GPIO_FUNC_GPCK); +} + +static const uint8_t gpin0_src[CLK_COUNT] = { + CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT0 + CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT1 + CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT2 + CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT3 + CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_REF + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_SYS + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_PERI + CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_USB + CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_ADC + CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_RTC +}; + +// Assert GPIN1 is GPIN0 + 1 +static_assert(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); + +bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq) { + // Configure a clock to run from a GPIO input + uint gpin = 0; + if (gpio == 20) gpin = 0; + else if (gpio == 22) gpin = 1; + else { + invalid_params_if(CLOCKS, true); + } + + // Work out sources. GPIN is always an auxsrc + uint src = 0; + + // GPIN1 == GPIN0 + 1 + uint auxsrc = gpin0_src[clk_index] + gpin; + + if (has_glitchless_mux(clk_index)) { + // AUX src is always 1 + src = 1; + } + + // Set the GPIO function + gpio_set_function(gpio, GPIO_FUNC_GPCK); + + // Now we have the src, auxsrc, and configured the gpio input + // call clock configure to run the clock from a gpio + return clock_configure(clk_index, src, auxsrc, src_freq, freq); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h new file mode 100644 index 00000000000..35940eaaeeb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_CLOCKS_H_ +#define _HARDWARE_CLOCKS_H_ + +#include "pico.h" +#include "hardware/structs/clocks.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/clocks.h + * \defgroup hardware_clocks hardware_clocks + * + * Clock Management API + * + * This API provides a high level interface to the clock functions. + * + * The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock + * sources allowing the user to trade off performance against cost, board area and power consumption. From these sources + * it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and + * stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies + * + * Please refer to the datasheet for more details on the RP2040 clocks. + * + * The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If + * you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary + * clock source, then you will need to use one of the entries from the subsequent tables. + * + * **Main Clock Sources** + * + * Source | Reference Clock | System Clock + * -------|-----------------|--------- + * ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | | + * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX + * XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | | + * Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF + * + * **Auxiliary Clock Sources** + * + * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table + * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3. + * + * + * Aux Source | clk_gpout[x] | clk_ref | clk_sys + * -----------|------------|---------|-------- + * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + * GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + * GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 + * USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB + * ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC + * XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC + * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | | + * USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | | + * ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | | + * RTC Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC | | | + * Ref clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | | + * + * Aux Source | clk_peri | clk_usb | clk_adc + * -----------|-----------|---------|-------- + * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + * GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + * GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 + * USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB + * ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH + * XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC + * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | | | + * + * Aux Source | clk_rtc + * -----------|---------- + * System PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + * GPIO in 0 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + * GPIO in 1 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 + * USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB + * ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH + * XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC + + * + * \section clock_example Example + * \addtogroup hardware_clocks + * \include hello_48MHz.c + */ + +#define KHZ 1000 +#define MHZ 1000000 + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CLOCKS, Enable/disable assertions in the clocks module, type=bool, default=0, group=hardware_clocks +#ifndef PARAM_ASSERTIONS_ENABLED_CLOCKS +#define PARAM_ASSERTIONS_ENABLED_CLOCKS 0 +#endif + +/*! \brief Initialise the clock hardware + * \ingroup hardware_clocks + * + * Must be called before any other clock function. + */ +void clocks_init(); + +/*! \brief Configure the specified clock + * \ingroup hardware_clocks + * + * See the tables in the description for details on the possible values for clock sources. + * + * \param clk_index The clock to configure + * \param src The main clock source, can be 0. + * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 + * \param src_freq Frequency of the input clock source + * \param freq Requested frequency + */ +bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq); + +/*! \brief Stop the specified clock + * \ingroup hardware_clocks + * + * \param clk_index The clock to stop + */ +void clock_stop(enum clock_index clk_index); + +/*! \brief Get the current frequency of the specified clock + * \ingroup hardware_clocks + * + * \param clk_index Clock + * \return Clock frequency in Hz + */ +uint32_t clock_get_hz(enum clock_index clk_index); + +/*! \brief Measure a clocks frequency using the Frequency counter. + * \ingroup hardware_clocks + * + * Uses the inbuilt frequency counter to measure the specified clocks frequency. + * Currently, this function is accurate to +-1KHz. See the datasheet for more details. + */ +uint32_t frequency_count_khz(uint src); + +/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock + * \ingroup hardware_clocks + * + * \see clock_get_hz + */ +void clock_set_reported_hz(enum clock_index clk_index, uint hz); + +/// \tag::frequency_count_mhz[] +static inline float frequency_count_mhz(uint src) { + return ((float) (frequency_count_khz(src))) / KHZ; +} +/// \end::frequency_count_mhz[] + +/*! \brief Resus callback function type. + * \ingroup hardware_clocks + * + * User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them). + */ +typedef void (*resus_callback_t)(void); + +/*! \brief Enable the resus function. Restarts clk_sys if it is accidentally stopped. + * \ingroup hardware_clocks + * + * The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This + * could happen if the clock source the system clock is running from stops. For example if a PLL is stopped. + * + * \param resus_callback a function pointer provided by the user to call if a resus event happens. + */ +void clocks_enable_resus(resus_callback_t resus_callback); + +/*! \brief Output an optionally divided clock to the specified gpio pin. + * \ingroup hardware_clocks + * + * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 26. These GPIOs are connected to the GPOUT0-3 clock generators. + * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator. + * \param div The amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. + */ +void clock_gpio_init(uint gpio, uint src, uint div); + +/*! \brief Configure a clock to come from a gpio input + * \ingroup hardware_clocks + * + * \param clk_index The clock to configure + * \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22. + * \param src_freq Frequency of the input clock source + * \param freq Requested frequency + */ +bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py new file mode 100755 index 00000000000..4d901465d3c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/scripts/vcocalc.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description="PLL parameter calculator") +parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float) +parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float) +parser.add_argument("--vco-min", default=400, help="Override minimum VCO frequency. Default 400 MHz", type=float) +parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter") +parser.add_argument("output", help="Output frequency in MHz.", type=float) +args = parser.parse_args() + +# Fixed hardware parameters +fbdiv_range = range(16, 320 + 1) +postdiv_range = range(1, 7 + 1) + +best = (0, 0, 0, 0) +best_margin = args.output + +for fbdiv in (fbdiv_range if args.low_vco else reversed(fbdiv_range)): + vco = args.input * fbdiv + if vco < args.vco_min or vco > args.vco_max: + continue + # pd1 is inner loop so that we prefer higher ratios of pd1:pd2 + for pd2 in postdiv_range: + for pd1 in postdiv_range: + out = vco / pd1 / pd2 + margin = abs(out - args.output) + if margin < best_margin: + best = (out, fbdiv, pd1, pd2) + best_margin = margin + +print("Requested: {} MHz".format(args.output)) +print("Achieved: {} MHz".format(best[0])) +print("FBDIV: {} (VCO = {} MHz)".format(best[1], args.input * best[1])) +print("PD1: {}".format(best[2])) +print("PD2: {}".format(best[3])) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt new file mode 100644 index 00000000000..3bbdded5a11 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt @@ -0,0 +1,4 @@ +add_library(hardware_divider INTERFACE) +target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S) +target_include_directories(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_link_libraries(hardware_divider INTERFACE hardware_structs) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/divider.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/divider.S new file mode 100644 index 00000000000..b9389c514a7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/divider.S @@ -0,0 +1,76 @@ +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" + +.syntax unified +.cpu cortex-m0plus +.thumb + +// tag::hw_div_s32[] + +.macro __divider_delay + // delay 8 cycles + b 1f +1: b 1f +1: b 1f +1: b 1f +1: +.endm + +.align 2 + +regular_func_with_section hw_divider_divmod_s32 + ldr r3, =(SIO_BASE) + str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET] + str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET] + __divider_delay + // return 64 bit value so we can efficiently return both (note quotient must be read last) + ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] + ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET] + bx lr +// end::hw_div_s32[] + +.align 2 + +// tag::hw_div_u32[] +regular_func_with_section hw_divider_divmod_u32 + ldr r3, =(SIO_BASE) + str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET] + str r1, [r3, #SIO_DIV_UDIVISOR_OFFSET] + __divider_delay + // return 64 bit value so we can efficiently return both (note quotient must be read last) + ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] + ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET] + bx lr +// end::hw_div_u32[] + +#if SIO_DIV_CSR_READY_LSB == 0 +.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 +#else +#error need to change SHIFT above +#endif + +regular_func_with_section hw_divider_save_state + push {r4, r5, lr} + ldr r5, =SIO_BASE + ldr r4, [r5, #SIO_DIV_CSR_OFFSET] + # wait for results as we can't save signed-ness of operation +1: + lsrs r4, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY + bcc 1b + ldr r1, [r5, #SIO_DIV_UDIVIDEND_OFFSET] + ldr r2, [r5, #SIO_DIV_UDIVISOR_OFFSET] + ldr r3, [r5, #SIO_DIV_REMAINDER_OFFSET] + ldr r4, [r5, #SIO_DIV_QUOTIENT_OFFSET] + stmia r0!, {r1-r4} + pop {r4, r5, pc} + +regular_func_with_section hw_divider_restore_state + push {r4, r5, lr} + ldr r5, =SIO_BASE + ldmia r0!, {r1-r4} + str r1, [r5, #SIO_DIV_UDIVIDEND_OFFSET] + str r2, [r5, #SIO_DIV_UDIVISOR_OFFSET] + str r3, [r5, #SIO_DIV_REMAINDER_OFFSET] + str r4, [r5, #SIO_DIV_QUOTIENT_OFFSET] + pop {r4, r5, pc} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h new file mode 100644 index 00000000000..42a7b6dbb0e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_DIVIDER_H +#define _HARDWARE_DIVIDER_H + +#include "pico.h" +#include "hardware/structs/sio.h" + +/** \file hardware/divider.h + * \defgroup hardware_divider hardware_divider + * + * Low-level hardware-divider access + * + * The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend + * and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of + * this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers + * DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation to + * complete, or software can insert a fixed 8-cycle delay + * + * This header provides low level macros and inline functions for accessing the hardware dividers directly, + * and perhaps most usefully performing asynchronous divides. These functions however do not follow the regular + * SDK conventions for saving/restoring the divider state, so are not generally safe to call from interrupt handlers + * + * The pico_divider library provides a more user friendly set of APIs over the divider (and support for + * 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning + * you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider. + * + * @see pico_divider + * + * \subsection divider_example Example + * \addtogroup hardware_divider + * \include hello_divider.c + */ + +typedef uint64_t divmod_result_t; + +/*! \brief Start a signed asynchronous divide + * \ingroup hardware_divider + * + * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set + * (hw_divider_wait_ready()) prior to reading the results. + * + * \param a The dividend + * \param b The divisor + */ +static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { + check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET); + sio_hw->div_sdividend = a; + sio_hw->div_sdivisor = b; +} + +/*! \brief Start an unsigned asynchronous divide + * \ingroup hardware_divider + * + * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set + * (hw_divider_wait_ready()) prior to reading the results. + * + * \param a The dividend + * \param b The divisor + */ +static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { + check_hw_layout( + sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET); + sio_hw->div_udividend = a; + sio_hw->div_udivisor = b; +} + +/*! \brief Wait for a divide to complete + * \ingroup hardware_divider + * + * Wait for a divide to complete + */ +static inline void hw_divider_wait_ready() { + // this is #1 in lsr below + static_assert(SIO_DIV_CSR_READY_BITS == 1, ""); + + // we use one less register and instruction than gcc which uses a TST instruction + + uint32_t tmp; // allow compiler to pick scratch register + asm volatile ( + "hw_divider_result_loop_%=:" + "ldr %0, [%1, %2]\n\t" + "lsr %0, #1\n\t" + "bcc hw_divider_result_loop_%=\n\t" + : "=&l" (tmp) + : "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET) + : + ); +} + +/*! \brief Return result of HW divide, nowait + * \ingroup hardware_divider + * + * \note This is UNSAFE in that the calculation may not have been completed. + * + * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. + */ +static inline divmod_result_t hw_divider_result_nowait() { + // as ugly as this looks it is actually quite efficient + divmod_result_t rc = (((divmod_result_t) sio_hw->div_remainder) << 32u) | sio_hw->div_quotient; + return rc; +} + +/*! \brief Return result of last asynchronous HW divide + * \ingroup hardware_divider + * + * This function waits for the result to be ready by calling hw_divider_wait_ready(). + * + * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. + */ +static inline divmod_result_t hw_divider_result_wait() { + hw_divider_wait_ready(); + return hw_divider_result_nowait(); +} + +/*! \brief Return result of last asynchronous HW divide, unsigned quotient only + * \ingroup hardware_divider + * + * This function waits for the result to be ready by calling hw_divider_wait_ready(). + * + * \return Current unsigned quotient result. + */ +static inline uint32_t hw_divider_u32_quotient_wait() { + hw_divider_wait_ready(); + return sio_hw->div_quotient; +} + +/*! \brief Return result of last asynchronous HW divide, signed quotient only + * \ingroup hardware_divider + * + * This function waits for the result to be ready by calling hw_divider_wait_ready(). + * + * \return Current signed quotient result. + */ +static inline int32_t hw_divider_s32_quotient_wait() { + hw_divider_wait_ready(); + return sio_hw->div_quotient; +} + +/*! \brief Return result of last asynchronous HW divide, unsigned remainder only + * \ingroup hardware_divider + * + * This function waits for the result to be ready by calling hw_divider_wait_ready(). + * + * \return Current unsigned remainder result. + */ +static inline uint32_t hw_divider_u32_remainder_wait() { + hw_divider_wait_ready(); + int32_t rc = sio_hw->div_remainder; + sio_hw->div_quotient; // must read quotient to cooperate with other SDK code + return rc; +} + +/*! \brief Return result of last asynchronous HW divide, signed remainder only + * \ingroup hardware_divider + * + * This function waits for the result to be ready by calling hw_divider_wait_ready(). + * + * \return Current remainder results. + */ +static inline int32_t hw_divider_s32_remainder_wait() { + hw_divider_wait_ready(); + int32_t rc = sio_hw->div_remainder; + sio_hw->div_quotient; // must read quotient to cooperate with other SDK code + return rc; +} + +/*! \brief Do a signed HW divide and wait for result + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. + * + * \param a The dividend + * \param b The divisor + * \return Results of divide as a 32p32 fixed point value. + */ +divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b); + +/*! \brief Do an unsigned HW divide and wait for result + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. + * + * \param a The dividend + * \param b The divisor + * \return Results of divide as a 32p32 fixed point value. + */ +divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b); + +/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r 32p32 fixed point value. + * \return Unsigned quotient + */ +inline static uint32_t to_quotient_u32(divmod_result_t r) { + return (uint32_t) r; +} + +/*! \brief Efficient extraction of signed quotient from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r 32p32 fixed point value. + * \return Unsigned quotient + */ +inline static int32_t to_quotient_s32(divmod_result_t r) { + return (int32_t)(uint32_t)r; +} + +/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r 32p32 fixed point value. + * \return Unsigned remainder + * + * \note On Arm this is just a 32 bit register move or a nop + */ +inline static uint32_t to_remainder_u32(divmod_result_t r) { + return (uint32_t)(r >> 32u); +} + +/*! \brief Efficient extraction of signed remainder from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r 32p32 fixed point value. + * \return Signed remainder + * + * \note On arm this is just a 32 bit register move or a nop + */ +inline static int32_t to_remainder_s32(divmod_result_t r) { + return (int32_t)(r >> 32u); +} + +/*! \brief Do an unsigned HW divide, wait for result, return quotient + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return quotient. + * + * \param a The dividend + * \param b The divisor + * \return Quotient results of the divide + */ +static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { + return to_quotient_u32(hw_divider_divmod_u32(a, b)); +} + +/*! \brief Do an unsigned HW divide, wait for result, return remainder + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return remainder. + * + * \param a The dividend + * \param b The divisor + * \return Remainder results of the divide + */ +static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { + return to_remainder_u32(hw_divider_divmod_u32(a, b)); +} + +/*! \brief Do a signed HW divide, wait for result, return quotient + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return quotient. + * + * \param a The dividend + * \param b The divisor + * \return Quotient results of the divide + */ +static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) { + return to_quotient_s32(hw_divider_divmod_s32(a, b)); +} + +/*! \brief Do a signed HW divide, wait for result, return remainder + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return remainder. + * + * \param a The dividend + * \param b The divisor + * \return Remainder results of the divide + */ +static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) { + return to_remainder_s32(hw_divider_divmod_s32(a, b)); +} + +/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete + * \ingroup hardware_divider + */ +static inline void hw_divider_pause() { + asm volatile ( + "b _1_%=\n" + "_1_%=:\n" + "b _2_%=\n" + "_2_%=:\n" + "b _3_%=\n" + "_3_%=:\n" + "b _4_%=\n" + "_4_%=:\n" + :: : ); +} + +/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return quotient. + * + * \param a The dividend + * \param b The divisor + * \return Quotient result of the divide + */ +static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { + hw_divider_divmod_u32_start(a, b); + hw_divider_pause(); + return sio_hw->div_quotient; +} + +/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return remainder. + * + * \param a The dividend + * \param b The divisor + * \return Remainder result of the divide + */ +static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { + hw_divider_divmod_u32_start(a, b); + hw_divider_pause(); + int32_t rc = sio_hw->div_remainder; + sio_hw->div_quotient; // must read quotient to cooperate with other SDK code + return rc; +} + +/*! \brief Do a hardware signed HW divide, wait for result, return quotient + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return quotient. + * + * \param a The dividend + * \param b The divisor + * \return Quotient result of the divide + */ +static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { + hw_divider_divmod_s32_start(a, b); + hw_divider_pause(); + return sio_hw->div_quotient; +} + +/*! \brief Do a hardware signed HW divide, wait for result, return remainder + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return remainder. + * + * \param a The dividend + * \param b The divisor + * \return Remainder result of the divide + */ +static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { + hw_divider_divmod_s32_start(a, b); + hw_divider_pause(); + int32_t rc = sio_hw->div_remainder; + sio_hw->div_quotient; // must read quotient to cooperate with other SDK code + return rc; +} + +typedef struct { + uint32_t values[4]; +} hw_divider_state_t; + +/*! \brief Save the calling cores hardware divider state + * \ingroup hardware_divider + * + * Copy the current core's hardware divider state into the provided structure. This method + * waits for the divider results to be stable, then copies them to memory. + * They can be restored via hw_divider_restore_state() + * + * \param dest the location to store the divider state + */ +void hw_divider_save_state(hw_divider_state_t *dest); + +/*! \brief Load a saved hardware divider state into the current core's hardware divider + * \ingroup hardware_divider + * + * Copy the passed hardware divider state into the hardware divider. + * + * \param src the location to load the divider state from + */ + +void hw_divider_restore_state(hw_divider_state_t *src); + +#endif // _HARDWARE_DIVIDER_H diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/CMakeLists.txt new file mode 100644 index 00000000000..fe085417362 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/CMakeLists.txt @@ -0,0 +1,2 @@ +pico_simple_hardware_target(dma) +target_link_libraries(hardware_dma INTERFACE hardware_claim) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c new file mode 100644 index 00000000000..c912e7f0c59 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hardware/dma.h" +#include "hardware/claim.h" + +#define DMA_CHAN_STRIDE (DMA_CH1_CTRL_TRIG_OFFSET - DMA_CH0_CTRL_TRIG_OFFSET) +check_hw_size(dma_channel_hw_t, DMA_CHAN_STRIDE); +check_hw_layout(dma_hw_t, abort, DMA_CHAN_ABORT_OFFSET); + +// sanity check +static_assert(__builtin_offsetof(dma_hw_t, ch[0].ctrl_trig) == DMA_CH0_CTRL_TRIG_OFFSET, "hw mismatch"); +static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG_OFFSET, "hw mismatch"); + +static_assert(NUM_DMA_CHANNELS <= 16, ""); +static uint16_t _claimed; + +void dma_channel_claim(uint channel) { + check_dma_channel_param(channel); + hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed"); +} + +void dma_claim_mask(uint32_t mask) { + for(uint i = 0; mask; i++, mask >>= 1u) { + if (mask & 1u) dma_channel_claim(i); + } +} + +void dma_channel_unclaim(uint channel) { + check_dma_channel_param(channel); + hw_claim_clear((uint8_t *) &_claimed, channel); +} + +int dma_claim_unused_channel(bool required) { + return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available"); +} + +#ifndef NDEBUG + +void print_dma_ctrl(dma_channel_hw_t *channel) { + uint32_t ctrl = channel->ctrl_trig; + int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB; + printf("(%08x) ber %d rer %d wer %d busy %d trq %d cto %d rgsl %d rgsz %d inw %d inr %d sz %d hip %d en %d", + (uint) ctrl, + ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0, + ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0, + ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0, + ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0, + (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB), + (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB), + ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0, + rgsz ? (1 << rgsz) : 0, + ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0, + ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0, + 1 << ((ctrl & DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB), + ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0, + ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0); +} + +void check_dma_channel_param_impl(uint channel) { + valid_params_if(DMA, channel < NUM_DMA_CHANNELS); +} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h new file mode 100644 index 00000000000..bd30eaf4b3f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_DMA_H_ +#define _HARDWARE_DMA_H_ + +#include "pico.h" +#include "hardware/structs/dma.h" +#include "hardware/regs/dreq.h" +#include "pico/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/dma.h + * \defgroup hardware_dma hardware_dma + * + * DMA Controller API + * + * The RP2040 Direct Memory Access (DMA) master performs bulk data transfers on a processor’s + * behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The + * data throughput of the DMA is also significantly higher than one of RP2040’s processors. + * + * The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. + * There are 12 independent channels, which each supervise a sequence of bus transfers, usually in + * one of the following scenarios: + * + * * Memory to peripheral + * * Peripheral to memory + * * Memory to memory + */ + +// this is not defined in generated dreq.h +#define DREQ_FORCE 63 + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma +#ifndef PARAM_ASSERTIONS_ENABLED_DMA +#define PARAM_ASSERTIONS_ENABLED_DMA 0 +#endif + +static inline void check_dma_channel_param(uint channel) { +#if PARAM_ASSERTIONS_ENABLED(DMA) + // this method is used a lot by inline functions so avoid code bloat by deferring to function + extern void check_dma_channel_param_impl(uint channel); + check_dma_channel_param_impl(channel); +#endif +} + +inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) { + check_dma_channel_param(channel); + return &dma_hw->ch[channel]; +} + +/*! \brief Mark a dma channel as used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. Will cause a panic if the channel + * is already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param channel the dma channel + */ +void dma_channel_claim(uint channel); + +/*! \brief Mark multiple dma channels as used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. Will cause a panic if any of the channels + * are already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param channel_mask Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc) + */ +void dma_claim_mask(uint32_t channel_mask); + +/*! \brief Mark a dma channel as no longer used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. + * + * \param channel the dma channel to release + */ +void dma_channel_unclaim(uint channel); + +/*! \brief Claim a free dma channel + * \ingroup hardware_dma + * + * \param required if true the function will panic if none are available + * \return the dma channel number or -1 if required was false, and none were free + */ +int dma_claim_unused_channel(bool required); + +/** \brief DMA channel configuration + * \defgroup channel_config channel_config + * \ingroup hardware_dma + * + * A DMA channel needs to be configured, these functions provide handy helpers to set up configuration + * structures. See \ref dma_channel_config + * + */ + +/*! \brief Enumeration of available DMA channel transfer sizes. + * \ingroup hardware_dma + * + * Names indicate the number of bits. + */ +enum dma_channel_transfer_size { + DMA_SIZE_8 = 0, ///< Byte transfer (8 bits) + DMA_SIZE_16 = 1, ///< Half word transfer (16 bits) + DMA_SIZE_32 = 2 ///< Word transfer (32 bits) +}; + +typedef struct { + uint32_t ctrl; +} dma_channel_config; + +/*! \brief Set DMA channel read increment + * \ingroup channel_config + * + * \param c Pointer to channel configuration data + * \param incr True to enable read address increments, if false, each read will be from the same address + * Usually disabled for peripheral to memory transfers + */ +static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) { + c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS); +} + +/*! \brief Set DMA channel write increment + * \ingroup channel_config + * + * \param c Pointer to channel configuration data + * \param incr True to enable write address increments, if false, each write will be to the same address + * Usually disabled for memory to peripheral transfers + * Usually disabled for memory to peripheral transfers + */ +static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) { + c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS); +} + +/*! \brief Select a transfer request signal + * \ingroup channel_config + * + * The channel uses the transfer request signal to pace its data transfer rate. + * Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + * 0x0 to 0x3a -> select DREQ n as TREQ + * 0x3b -> Select Timer 0 as TREQ + * 0x3c -> Select Timer 1 as TREQ + * 0x3d -> Select Timer 2 as TREQ (Optional) + * 0x3e -> Select Timer 3 as TREQ (Optional) + * 0x3f -> Permanent request, for unpaced transfers. + * + * \param c Pointer to channel configuration data + * \param dreq Source (see description) + */ +static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) { + assert(dreq <= DREQ_FORCE); + c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); +} + +/*! \brief Set DMA channel completion channel + * \ingroup channel_config + * + * When this channel completes, it will trigger the channel indicated by chain_to. Disable by + * setting chain_to to itself (the same channel) + * + * \param c Pointer to channel configuration data + * \param chain_to Channel to trigger when this channel completes. + */ +static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) { + assert(chain_to <= NUM_DMA_CHANNELS); + c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB); +} + +/*! \brief Set the size of each DMA bus transfer + * \ingroup channel_config + * + * Set the size of each bus transfer (byte/halfword/word). The read and write addresses + * advance by the specific amount (1/2/4 bytes) with each transfer. + * + * \param c Pointer to channel configuration data + * \param size See enum for possible values. + */ +static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) { + assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32); + c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (size << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); +} + +/*! \brief Set address wrapping parameters + * \ingroup channel_config + * + * Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address + * will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned + * ring buffers. + * Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15) + * + * 0x0 -> No wrapping. + * + * \param c Pointer to channel configuration data + * \param write True to apply to write addresses, false to apply to read addresses + * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address. + * Effectively wraps the address on a (1 << size_bits) byte boundary. + */ +static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) { + assert(size_bits < 32); + c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | + (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) | + (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0); +} + +/*! \brief Set DMA byte swapping + * \ingroup channel_config + * + * No effect for byte data, for halfword data, the two bytes of each halfword are + * swapped. For word data, the four bytes of each word are swapped to reverse their order. + * + * \param c Pointer to channel configuration data + * \param bswap True to enable byte swapping + */ +static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) { + c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS); +} + +/*! \brief Set IRQ quiet mode + * \ingroup channel_config + * + * In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, + * an IRQ is raised when NULL is written to a trigger register, indicating the end of a control + * block chain. + * + * \param c Pointer to channel configuration data + * \param irq_quiet True to enable quiet mode, false to disable. + */ +static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) { + c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS); +} + +/*! + * \brief Enable/Disable the DMA channel + * \ingroup channel_config + * + * When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will + * remain high if already high) + * + * \param c Pointer to channel configuration data + * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data. + * + */ +static inline void channel_config_set_enable(dma_channel_config *c, bool enable) { + c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS); +} + +/*! \brief Enable access to channel by sniff hardware. + * \ingroup channel_config + * + * Sniff HW must be enabled and have this channel selected. + * + * \param c Pointer to channel configuration data + * \param sniff_enable True to enable the Sniff HW access to this DMA channel. + */ +static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) { + c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl & + ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); +} + +/*! \brief Get the default channel configuration for a given channel + * \ingroup channel_config + * + * Setting | Default + * --------|-------- + * Read Increment | true + * Write Increment | false + * DReq | DREQ_FORCE + * Chain to | self + * Data size | DMA_SIZE_32 + * Ring | write=false, size=0 (i.e. off) + * Byte Swap | false + * Quiet IRQs | false + * Channel Enable | true + * Sniff Enable | false + * + * \param channel DMA channel + * \return the default configuration which can then be modified. + */ +static inline dma_channel_config dma_channel_get_default_config(uint channel) { + dma_channel_config c = {0}; + channel_config_set_read_increment(&c, true); + channel_config_set_write_increment(&c, false); + channel_config_set_dreq(&c, DREQ_FORCE); + channel_config_set_chain_to(&c, channel); + channel_config_set_transfer_data_size(&c, DMA_SIZE_32); + channel_config_set_ring(&c, false, 0); + channel_config_set_bswap(&c, false); + channel_config_set_irq_quiet(&c, false); + channel_config_set_enable(&c, true); + channel_config_set_sniff_enable(&c, false); + return c; +} + +/*! \brief Get the current configuration for the specified channel. + * \ingroup channel_config + * + * \param channel DMA channel + * \return The current configuration as read from the HW register (not cached) + */ +static inline dma_channel_config dma_get_channel_config(uint channel) { + dma_channel_config c; + c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig; + return c; +} + +/*! \brief Get the raw configuration register from a channel configuration + * \ingroup channel_config + * + * \param config Pointer to a config structure. + * \return Register content + */ +static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) { + return config->ctrl; +} + +/*! \brief Set a channel configuration + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param config Pointer to a config structure with required configuration + * \param trigger True to trigger the transfer immediately + */ +static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) { + // Don't use CTRL_TRIG since we don't want to start a transfer + if (!trigger) { + dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config); + } else { + dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config); + } +} + +/*! \brief Set the DMA initial read address. + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param read_addr Initial read address of transfer. + * \param trigger True to start the transfer immediately + */ +static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) { + if (!trigger) { + dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr; + } else { + dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr; + } +} + +/*! \brief Set the DMA initial read address + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param write_addr Initial write address of transfer. + * \param trigger True to start the transfer immediately + */ +static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) { + if (!trigger) { + dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr; + } else { + dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr; + } +} + +/*! \brief Set the number of bus transfers the channel will do + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param trans_count The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size) + * \param trigger True to start the transfer immediately + */ +static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) { + if (!trigger) { + dma_channel_hw_addr(channel)->transfer_count = trans_count; + } else { + dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count; + } +} + +/*! \brief Configure all DMA parameters and optionally start transfer + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param config Pointer to DMA config structure + * \param write_addr Initial write address + * \param read_addr Initial read address + * \param transfer_count Number of transfers to perform + * \param trigger True to start the transfer immediately + */ +static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr, + const volatile void *read_addr, + uint transfer_count, bool trigger) { + dma_channel_set_read_addr(channel, read_addr, false); + dma_channel_set_write_addr(channel, write_addr, false); + dma_channel_set_trans_count(channel, transfer_count, false); + dma_channel_set_config(channel, config, trigger); +} + +/*! \brief Start a DMA transfer from a buffer immediately + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param read_addr Sets the initial read address + * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. + */ +inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, void *read_addr, + uint32_t transfer_count) { +// check_dma_channel_param(channel); + dma_channel_hw_t *hw = dma_channel_hw_addr(channel); + hw->read_addr = (uintptr_t) read_addr; + hw->al1_transfer_count_trig = transfer_count; +} + +/*! \brief Start a DMA transfer to a buffer immediately + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param write_addr Sets the initial write address + * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. + */ +inline static void dma_channel_transfer_to_buffer_now(uint channel, void *write_addr, uint32_t transfer_count) { + dma_channel_hw_t *hw = dma_channel_hw_addr(channel); + hw->write_addr = (uintptr_t) write_addr; + hw->al1_transfer_count_trig = transfer_count; +} + +/*! \brief Start one or more channels simultaneously + * \ingroup hardware_dma + * + * \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc. + */ +static inline void dma_start_channel_mask(uint32_t chan_mask) { + valid_params_if(DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS)); + dma_hw->multi_channel_trigger = chan_mask; +} + +/*! \brief Start a single DMA channel + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +static inline void dma_channel_start(uint channel) { + dma_start_channel_mask(1u << channel); +} + +/*! \brief Stop a DMA transfer + * \ingroup hardware_dma + * + * Function will only return once the DMA has stopped. + * + * \param channel DMA channel + */ +static inline void dma_channel_abort(uint channel) { + check_dma_channel_param(channel); + dma_hw->abort = 1u << channel; + // Bit will go 0 once channel has reached safe state + // (i.e. any in-flight transfers have retired) + while (dma_hw->abort & (1ul << channel)) tight_loop_contents(); +} + +/*! \brief Enable single DMA channel interrupt 0 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param enabled true to enable interrupt 0 on specified channel, false to disable. + */ +static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) { + check_dma_channel_param(channel); + check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET); + if (enabled) + hw_set_bits(&dma_hw->inte0, 1u << channel); + else + hw_clear_bits(&dma_hw->inte0, 1u << channel); +} + +/*! \brief Enable multiple DMA channels interrupt 0 + * \ingroup hardware_dma + * + * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. + */ +static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) { + if (enabled) { + hw_set_bits(&dma_hw->inte0, channel_mask); + } else { + hw_clear_bits(&dma_hw->inte0, channel_mask); + } +} + +/*! \brief Enable single DMA channel interrupt 1 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \param enabled true to enable interrupt 1 on specified channel, false to disable. + */ +static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) { + check_dma_channel_param(channel); + check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET); + if (enabled) + hw_set_bits(&dma_hw->inte1, 1u << channel); + else + hw_clear_bits(&dma_hw->inte1, 1u << channel); +} + +/*! \brief Enable multiple DMA channels interrupt 0 + * \ingroup hardware_dma + * + * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. + */ +static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) { + if (enabled) { + hw_set_bits(&dma_hw->inte1, channel_mask); + } else { + hw_clear_bits(&dma_hw->inte1, channel_mask); + } +} + +/*! \brief Check if DMA channel is busy + * \ingroup hardware_dma + * + * \param channel DMA channel + * \return true if the channel is currently busy + */ +inline static bool dma_channel_is_busy(uint channel) { + check_dma_channel_param(channel); + return !!(dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS); +} + +/*! \brief Wait for a DMA channel transfer to complete + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +inline static void dma_channel_wait_for_finish_blocking(uint channel) { + while (dma_channel_is_busy(channel)) tight_loop_contents(); +} + +/*! \brief Enable the DMA sniffing targeting the specified channel + * \ingroup hardware_dma + * + * The mode can be one of the following: + * + * Mode | Function + * -----|--------- + * 0x0 | Calculate a CRC-32 (IEEE802.3 polynomial) + * 0x1 | Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + * 0x2 | Calculate a CRC-16-CCITT + * 0x3 | Calculate a CRC-16-CCITT with bit reversed data + * 0xe | XOR reduction over all data. == 1 if the total 1 population count is odd. + * 0xf | Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + * + * \param channel DMA channel + * \param mode See description + * \param force_channel_enable Set true to also turn on sniffing in the channel configuration (this + * is usually what you want, but sometimes you might have a chain DMA with only certain segments + * of the chain sniffed, in which case you might pass false). + */ +inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) { + check_dma_channel_param(channel); + check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET); + if (force_channel_enable) { + hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); + } + dma_hw->sniff_ctrl = ((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) | + ((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) | + DMA_SNIFF_CTRL_EN_BITS; +} + +/*! \brief Enable the Sniffer byte swap function + * \ingroup hardware_dma + * + * Locally perform a byte reverse on the sniffed data, before feeding into checksum. + * + * Note that the sniff hardware is downstream of the DMA channel byteswap performed in the + * read master: if channel_config_set_bswap() and dma_sniffer_set_byte_swap_enabled() are both enabled, + * their effects cancel from the sniffer’s point of view. + * + * \param swap Set true to enable byte swapping + */ +inline static void dma_sniffer_set_byte_swap_enabled(bool swap) { + if (swap) + hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); + else + hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); +} + +/*! \brief Disable the DMA sniffer + * \ingroup hardware_dma + * + */ +inline static void dma_sniffer_disable() { + dma_hw->sniff_ctrl = 0; +} + +#ifndef NDEBUG +void print_dma_ctrl(dma_channel_hw_t *channel); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt new file mode 100644 index 00000000000..1ccab3351ff --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt @@ -0,0 +1,8 @@ +add_library(hardware_flash INTERFACE) + +target_sources(hardware_flash INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/flash.c + ) + +target_include_directories(hardware_flash INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_link_libraries(hardware_flash INTERFACE pico_base_headers pico_bootrom) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c new file mode 100644 index 00000000000..8657ba50233 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/flash.h" +#include "pico/bootrom.h" + +#include "hardware/structs/ssi.h" +#include "hardware/structs/ioqspi.h" + +#define FLASH_BLOCK_ERASE_CMD 0xd8 + +// Standard RUID instruction: 4Bh command prefix, 32 dummy bits, 64 data bits. +#define FLASH_RUID_CMD 0x4b +#define FLASH_RUID_DUMMY_BYTES 4 +#define FLASH_RUID_DATA_BYTES 8 +#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES) + +#define __compiler_barrier() asm volatile("" ::: "memory") + +//----------------------------------------------------------------------------- +// Infrastructure for reentering XIP mode after exiting for programming (take +// a copy of boot2 before XIP exit). Calling boot2 as a function works because +// it accepts a return vector in LR (and doesn't trash r4-r7). Bootrom passes +// NULL in LR, instructing boot2 to enter flash vector table's reset handler. + +#if !PICO_NO_FLASH + +#define BOOT2_SIZE_WORDS 64 + +static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; +static bool boot2_copyout_valid = false; + +static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() { + if (boot2_copyout_valid) + return; + for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) + boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i]; + __compiler_barrier(); + boot2_copyout_valid = true; +} + +static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() { + ((void (*)(void))boot2_copyout+1)(); +} + +#else + +static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() {} + +static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() { + // Set up XIP for 03h read on bus access (slow but generic) + void (*flash_enter_cmd_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('C', 'X')); + assert(flash_enter_cmd_xip); + flash_enter_cmd_xip(); +} + +#endif + +//----------------------------------------------------------------------------- +// Actual flash programming shims (work whether or not PICO_NO_FLASH==1) + +void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_t count) { +#ifdef PICO_FLASH_SIZE_BYTES + hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); +#endif + invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1)); + invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1)); + void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); + void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); + void (*flash_range_erase)(uint32_t, size_t, uint32_t, uint8_t) = + (void(*)(uint32_t, size_t, uint32_t, uint8_t))rom_func_lookup(rom_table_code('R', 'E')); + void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); + assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache); + flash_init_boot2_copyout(); + + // No flash accesses after this point + __compiler_barrier(); + + connect_internal_flash(); + flash_exit_xip(); + flash_range_erase(flash_offs, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD); + flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing + flash_enable_xip_via_boot2(); +} + +void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) { +#ifdef PICO_FLASH_SIZE_BYTES + hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); +#endif + invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1)); + invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1)); + void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); + void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); + void (*flash_range_program)(uint32_t, const uint8_t*, size_t) = + (void(*)(uint32_t, const uint8_t*, size_t))rom_func_lookup(rom_table_code('R', 'P')); + void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); + assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache); + flash_init_boot2_copyout(); + + __compiler_barrier(); + + connect_internal_flash(); + flash_exit_xip(); + flash_range_program(flash_offs, data, count); + flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing + flash_enable_xip_via_boot2(); +} + +//----------------------------------------------------------------------------- +// Lower-level flash access functions + +#if !PICO_NO_FLASH +// Bitbanging the chip select using IO overrides, in case RAM-resident IRQs +// are still running, and the FIFO bottoms out. (the bootrom does the same) +static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) { + uint32_t field_val = high ? + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; + hw_write_masked(&ioqspi_hw->io[1].ctrl, + field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS + ); +} + +// May want to expose this at some point but this is unlikely to be the right +// interface to do so. Keep it static +static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { + void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); + void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); + void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); + assert(connect_internal_flash && flash_exit_xip && flash_flush_cache); + flash_init_boot2_copyout(); + __compiler_barrier(); + connect_internal_flash(); + flash_exit_xip(); + + flash_cs_force(0); + size_t tx_remaining = count; + size_t rx_remaining = count; + // We may be interrupted -- don't want FIFO to overflow if we're distracted. + const size_t max_in_flight = 16 - 2; + while (tx_remaining || rx_remaining) { + uint32_t flags = ssi_hw->sr; + bool can_put = !!(flags & SSI_SR_TFNF_BITS); + bool can_get = !!(flags & SSI_SR_RFNE_BITS); + if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) { + ssi_hw->dr0 = *txbuf++; + --tx_remaining; + } + if (can_get && rx_remaining) { + *rxbuf++ = ssi_hw->dr0; + --rx_remaining; + } + } + flash_cs_force(1); + + flash_flush_cache(); + flash_enable_xip_via_boot2(); +} +#endif + +// Use standard RUID command to get a unique identifier for the flash (and +// hence the board) + +static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, ""); + +void flash_get_unique_id(uint8_t *id_out) { +#if PICO_NO_FLASH + panic_unsupported(); +#else + uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0}; + uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0}; + txbuf[0] = FLASH_RUID_CMD; + flash_do_cmd(txbuf, rxbuf, FLASH_RUID_TOTAL_BYTES); + for (int i = 0; i < FLASH_RUID_DATA_BYTES; i++) + id_out[i] = rxbuf[i + 1 + FLASH_RUID_DUMMY_BYTES]; +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h new file mode 100644 index 00000000000..40e2949d6e6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_FLASH_H +#define _HARDWARE_FLASH_H + +#include "pico.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash +#ifndef PARAM_ASSERTIONS_ENABLED_FLASH +#define PARAM_ASSERTIONS_ENABLED_FLASH 0 +#endif + +#define FLASH_PAGE_SIZE (1u << 8) +#define FLASH_SECTOR_SIZE (1u << 12) +#define FLASH_BLOCK_SIZE (1u << 16) + +#define FLASH_UNIQUE_ID_SIZE_BYTES 8 + +/** \file flash.h + * \defgroup hardware_flash hardware_flash + * + * Low level flash programming and erase API + * + * Note these functions are *unsafe* if you have two cores concurrently + * executing from flash. In this case you must perform your own + * synchronisation to make sure no XIP accesses take place during flash + * programming. + * + * Likewise they are *unsafe* if you have interrupt handlers or an interrupt + * vector table in flash, so you must disable interrupts before calling in + * this case. + * + * If PICO_NO_FLASH=1 is not defined (i.e. if the program is built to run from + * flash) then these functions will make a static copy of the second stage + * bootloader in SRAM, and use this to reenter execute-in-place mode after + * programming or erasing flash, so that they can safely be called from + * flash-resident code. + * + * \subsection flash_example Example + * \include flash_program.c + */ + + +/*! \brief Erase areas of flash + * \ingroup hardware_flash + * + * \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector. + * \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector). + */ +void flash_range_erase(uint32_t flash_offs, size_t count); + +/*! \brief Program flash + * \ingroup hardware_flash + * + * \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page. + * \param data Pointer to the data to program into flash + * \param count Number of bytes to program. Must be a multiple of 256 bytes (one page). + */ + +void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count); + +/*! \brief Get flash unique 64 bit identifier + * \ingroup hardware_flash + * + * Use a standard 4Bh RUID instruction to retrieve the 64 bit unique + * identifier from a flash device attached to the QSPI interface. Since there + * is a 1:1 association between the MCU and this flash, this also serves as a + * unique identifier for the board. + * + * \param id_out Pointer to an 8-byte buffer to which the ID will be written + */ +void flash_get_unique_id(uint8_t *id_out); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/CMakeLists.txt new file mode 100644 index 00000000000..1bfb078f37f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(gpio) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c new file mode 100644 index 00000000000..7051de309ab --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/gpio.h" +#include "hardware/sync.h" + +#include "hardware/structs/iobank0.h" +#include "hardware/irq.h" + +#include "pico/binary_info.h" + +static gpio_irq_callback_t _callbacks[NUM_CORES]; + +// Get the raw value from the pin, bypassing any muxing or overrides. +int gpio_get_pad(uint gpio) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); + return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS) + >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB; +} + +/// \tag::gpio_set_function[] +// Select function for this GPIO, and ensure input/output are enabled at the pad. +// This also clears the input/output/irq override bits. +void gpio_set_function(uint gpio, enum gpio_function fn) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + invalid_params_if(GPIO, fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); + // Set input enable on, output disable off + hw_write_masked(&padsbank0_hw->io[gpio], + PADS_BANK0_GPIO0_IE_BITS, + PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS + ); + // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it. + // This doesn't affect e.g. pullup/pulldown, as these are in pad controls. + iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; +} +/// \end::gpio_set_function[] + +enum gpio_function gpio_get_function(uint gpio) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB); +} + +// Note that, on RP2040, setting both pulls enables a "bus keep" function, +// i.e. weak pull to whatever is current high/low state of GPIO. +void gpio_set_pulls(uint gpio, bool up, bool down) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked( + &padsbank0_hw->io[gpio], + (!!up << PADS_BANK0_GPIO0_PUE_LSB) | (!!down << PADS_BANK0_GPIO0_PDE_LSB), + PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS + ); +} + +// Direct overrides for pad controls +void gpio_set_inover(uint gpio, uint value) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&iobank0_hw->io[gpio].ctrl, + value << IO_BANK0_GPIO0_CTRL_INOVER_LSB, + IO_BANK0_GPIO0_CTRL_INOVER_BITS + ); +} + +void gpio_set_outover(uint gpio, uint value) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&iobank0_hw->io[gpio].ctrl, + value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB, + IO_BANK0_GPIO0_CTRL_OUTOVER_BITS + ); +} + +void gpio_set_oeover(uint gpio, uint value) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&iobank0_hw->io[gpio].ctrl, + value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB, + IO_BANK0_GPIO0_CTRL_OEOVER_BITS + ); +} + +static void gpio_irq_handler(void) { + io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? + &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; + for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) { + io_rw_32 *status_reg = &irq_ctrl_base->ints[gpio / 8]; + uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf; + if (events) { + // TODO: If both cores care about this event then the second core won't get the irq? + gpio_acknowledge_irq(gpio, events); + gpio_irq_callback_t callback = _callbacks[get_core_num()]; + if (callback) { + callback(gpio, events); + } + } + } +} + +static void _gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_irq_ctrl_hw_t *irq_ctrl_base) { + // Clear stale events which might cause immediate spurious handler entry + gpio_acknowledge_irq(gpio, events); + + io_rw_32 *en_reg = &irq_ctrl_base->inte[gpio / 8]; + events <<= 4 * (gpio % 8); + + if (enabled) + hw_set_bits(en_reg, events); + else + hw_clear_bits(en_reg, events); +} + +void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) { + // Separate mask/force/status per-core, so check which core called, and + // set the relevant IRQ controls. + io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? + &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; + _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); +} + +void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback) { + gpio_set_irq_enabled(gpio, events, enabled); + + // TODO: Do we want to support a callback per GPIO pin? + // Install IRQ handler + _callbacks[get_core_num()] = callback; + irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler); + irq_set_enabled(IO_IRQ_BANK0, true); +} + +void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) { + io_irq_ctrl_hw_t *irq_ctrl_base = &iobank0_hw->dormant_wake_irq_ctrl; + _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); +} + +void gpio_acknowledge_irq(uint gpio, uint32_t events) { + iobank0_hw->intr[gpio / 8] = events << 4 * (gpio % 8); +} + +#define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE) +void gpio_debug_pins_init() { + gpio_init_mask(DEBUG_PIN_MASK); + gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK); + bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug")); +} + +void gpio_set_input_enabled(uint gpio, bool enabled) { + if (enabled) + hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); + else + hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); +} + +void _gpio_init(uint gpio) { + sio_hw->gpio_oe_clr = 1ul << gpio; + sio_hw->gpio_clr = 1ul << gpio; + gpio_set_function(gpio, GPIO_FUNC_SIO); +} + +void gpio_init_mask(uint gpio_mask) { + for(uint i=0;i<32;i++) { + if (gpio_mask & 1) { + _gpio_init(i); + } + gpio_mask >>= 1; + } +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h new file mode 100644 index 00000000000..563c6a0137e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_GPIO_H_ +#define _HARDWARE_GPIO_H_ + +#include "pico.h" +#include "hardware/structs/sio.h" +#include "hardware/structs/padsbank0.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_GPIO, Enable/disable assertions in the GPIO module, type=bool, default=0, group=hardware_gpio +#ifndef PARAM_ASSERTIONS_ENABLED_GPIO +#define PARAM_ASSERTIONS_ENABLED_GPIO 0 +#endif + +/** \file gpio.h + * \defgroup hardware_gpio hardware_gpio + * + * General Purpose Input/Output (GPIO) API + * + * RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use case, + * the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an external + * flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital input and + * output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC). Each GPIO + * can be controlled directly by software running on the processors, or by a number of other functional blocks. + * + * The function allocated to each GPIO is selected by calling the \ref gpio_set_function function. \note Not all functions + * are available on all pins. + * + * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be selected on + * one _GPIO_ at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical OR of these + * GPIO inputs. Please refer to the datasheet for more information on GPIO function select. + * + * ### Function Select Table + * + * GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 + * -------|----------|-----------|----------|--------|-----|------|------|---------------|---- + * 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET + * 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN + * 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET + * 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN + * 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET + * 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN + * 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET + * 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN + * 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET + * 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN + * 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET + * 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN + * 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET + * 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN + * 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET + * 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET + * 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN + * 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET + * 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET + * 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN + * 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET + * 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET + * 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN + + */ + +/*! \brief GPIO function definitions for use with function select + * \ingroup hardware_gpio + * \brief GPIO function selectors + * + * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be + * selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical + * OR of these GPIO inputs. + * + * Please refer to the datsheet for more information on GPIO function selection. + */ +enum gpio_function { + GPIO_FUNC_XIP = 0, + GPIO_FUNC_SPI = 1, + GPIO_FUNC_UART = 2, + GPIO_FUNC_I2C = 3, + GPIO_FUNC_PWM = 4, + GPIO_FUNC_SIO = 5, + GPIO_FUNC_PIO0 = 6, + GPIO_FUNC_PIO1 = 7, + GPIO_FUNC_GPCK = 8, + GPIO_FUNC_USB = 9, + GPIO_FUNC_NULL = 0xf, +}; + +#define GPIO_OUT 1 +#define GPIO_IN 0 + +/*! \brief GPIO Interrupt level definitions + * \ingroup hardware_gpio + * \brief GPIO Interrupt levels + * + * An interrupt can be generated for every GPIO pin in 4 scenarios: + * + * * Level High: the GPIO pin is a logical 1 + * * Level Low: the GPIO pin is a logical 0 + * * Edge High: the GPIO has transitioned from a logical 0 to a logical 1 + * * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0 + * + * The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will + * become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be + * cleared by writing to the INTR register. + */ +enum gpio_irq_level { + GPIO_IRQ_LEVEL_LOW = 0x1u, + GPIO_IRQ_LEVEL_HIGH = 0x2u, + GPIO_IRQ_EDGE_FALL = 0x4u, + GPIO_IRQ_EDGE_RISE = 0x8u, +}; + +typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events); + +enum gpio_override { + GPIO_OVERRIDE_NORMAL = 0, ///< peripheral signal selected via \ref gpio_set_function + GPIO_OVERRIDE_INVERT = 1, ///< invert peripheral signal selected via \ref gpio_set_function + GPIO_OVERRIDE_LOW = 2, ///< drive low/disable output + GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output +}; + +// ---------------------------------------------------------------------------- +// Pad Controls + IO Muxing +// ---------------------------------------------------------------------------- +// Declarations for gpio.c + +/*! \brief Select GPIO function + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param fn Which GPIO function select to use from list \ref gpio_function + */ +void gpio_set_function(uint gpio, enum gpio_function fn); + +enum gpio_function gpio_get_function(uint gpio); + +/*! \brief Select up and down pulls on specific GPIO + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param up If true set a pull up on the GPIO + * \param down If true set a pull down on the GPIO + * + * \note On the RP2040, setting both pulls enables a "bus keep" function, + * i.e. a weak pull to whatever is current high/low state of GPIO. + */ +void gpio_set_pulls(uint gpio, bool up, bool down); + +/*! \brief Set specified GPIO to be pulled up. + * \ingroup hardware_gpio + * + * \param gpio GPIO number + */ +static inline void gpio_pull_up(uint gpio) { + gpio_set_pulls(gpio, true, false); +} + +/*! \brief Determine if the specified GPIO is pulled up. + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return true if the GPIO is pulled up + */ +static inline bool gpio_is_pulled_up(uint gpio) { + return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0; +} + +/*! \brief Set specified GPIO to be pulled down. + * \ingroup hardware_gpio + * + * \param gpio GPIO number + */ +static inline void gpio_pull_down(uint gpio) { + gpio_set_pulls(gpio, false, true); +} + +/*! \brief Determine if the specified GPIO is pulled down. + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return true if the GPIO is pulled down + */ +static inline bool gpio_is_pulled_down(uint gpio) { + return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0; +} + +/*! \brief Disable pulls on specified GPIO + * \ingroup hardware_gpio + * + * \param gpio GPIO number + */ +static inline void gpio_disable_pulls(uint gpio) { + gpio_set_pulls(gpio, false, false); +} + +/*! \brief Set GPIO output override + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param value See \ref gpio_override + */ +void gpio_set_outover(uint gpio, uint value); + +/*! \brief Select GPIO input override + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param value See \ref gpio_override + */ +void gpio_set_inover(uint gpio, uint value); + +/*! \brief Select GPIO output enable override + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param value See \ref gpio_override + */ +void gpio_set_oeover(uint gpio, uint value); + +/*! \brief Enable GPIO input + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param enabled true to enable input on specified GPIO + */ +void gpio_set_input_enabled(uint gpio, bool enabled); + +/*! \brief Enable or disable interrupts for specified GPIO + * \ingroup hardware_gpio + * + * \note The IO IRQs are independent per-processor. This configures IRQs for + * the processor that calls the function. + * + * \param gpio GPIO number + * \param events Which events will cause an interrupt + * \param enabled Enable or disable flag + * + * Events is a bitmask of the following: + * + * bit | interrupt + * ----|---------- + * 0 | Low level + * 1 | High level + * 2 | Edge low + * 3 | Edge high + */ +void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled); + +/*! \brief Enable interrupts for specified GPIO + * \ingroup hardware_gpio + * + * \note The IO IRQs are independent per-processor. This configures IRQs for + * the processor that calls the function. + * + * \param gpio GPIO number + * \param events Which events will cause an interrupt See \ref gpio_set_irq_enabled for details. + * \param enabled Enable or disable flag + * \param callback user function to call on GPIO irq. Note only one of these can be set per processor. + * + * \note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin. + * + */ +void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback); + +/*! \brief Enable dormant wake up interrupt for specified GPIO + * \ingroup hardware_gpio + * + * This configures IRQs to restart the XOSC or ROSC when they are + * disabled in dormant mode + * + * \param gpio GPIO number + * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details. + * \param enabled Enable/disable flag + */ +void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled); + +/*! \brief Acknowledge a GPIO interrupt + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param events Bitmask of events to clear. See \ref gpio_set_irq_enabled for details. + * + */ +void gpio_acknowledge_irq(uint gpio, uint32_t events); + +/*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) + * \ingroup hardware_gpio + * + * Clear the output enable (i.e. set to input) + * Clear any output value. + * + * \param gpio GPIO number + */ +void _gpio_init(uint gpio); + +/*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) + * \ingroup hardware_gpio + * + * Clear the output enable (i.e. set to input) + * Clear any output value. + * + * \param gpio_mask Mask with 1 bit per GPIO number to initialize + */ +void gpio_init_mask(uint gpio_mask); +// ---------------------------------------------------------------------------- +// Input +// ---------------------------------------------------------------------------- + +/*! \brief Get state of a single specified GPIO + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return Current state of the GPIO. 0 for low, non-zero for high + */ +static inline bool gpio_get(uint gpio) { + return !!((1ul << gpio) & sio_hw->gpio_in); +} + +/*! \brief Get raw value of all GPIOs + * \ingroup hardware_gpio + * + * \return Bitmask of raw GPIO values, as bits 0-29 + */ +static inline uint32_t gpio_get_all() { + return sio_hw->gpio_in; +} + +// ---------------------------------------------------------------------------- +// Output +// ---------------------------------------------------------------------------- + +/*! \brief Drive high every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to set, as bits 0-29 + */ +static inline void gpio_set_mask(uint32_t mask) { + sio_hw->gpio_set = mask; +} + +/*! \brief Drive low every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to clear, as bits 0-29 + */ +static inline void gpio_clr_mask(uint32_t mask) { + sio_hw->gpio_clr = mask; +} + +/*! \brief Toggle every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to toggle, as bits 0-29 + */ +static inline void gpio_xor_mask(uint32_t mask) { + sio_hw->gpio_togl = mask; +} + +/*! \brief Drive GPIO high/low depending on parameters + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to change, as bits 0-29 + * \param value Value to set + * + * For each 1 bit in \p mask, drive that pin to the value given by + * corresponding bit in \p value, leaving other pins unchanged. + * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ + * bashing different pins from the same core. + */ +static inline void gpio_put_masked(uint32_t mask, uint32_t value) { + sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask; +} + +/*! \brief Drive all pins simultaneously + * \ingroup hardware_gpio + * + * \param value Bitmask of GPIO values to change, as bits 0-29 + */ +static inline void gpio_put_all(uint32_t value) { + sio_hw->gpio_out = value; +} + +/*! \brief Drive a single GPIO high/low + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param value If false clear the GPIO, otherwise set it. + */ +static inline void gpio_put(uint gpio, bool value) { + uint32_t mask = 1ul << gpio; + if (value) + gpio_set_mask(mask); + else + gpio_clr_mask(mask); +} + +// ---------------------------------------------------------------------------- +// Direction +// ---------------------------------------------------------------------------- + +/*! \brief Set a number of GPIOs to output + * \ingroup hardware_gpio + * + * Switch all GPIOs in "mask" to output + * + * \param mask Bitmask of GPIO to set to output, as bits 0-29 + */ +static inline void gpio_set_dir_out_masked(uint32_t mask) { + sio_hw->gpio_oe_set = mask; +} + +/*! \brief Set a number of GPIOs to input + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO to set to input, as bits 0-29 + */ +static inline void gpio_set_dir_in_masked(uint32_t mask) { + sio_hw->gpio_oe_clr = mask; +} + +/*! \brief Set multiple GPIO directions + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO to set to input, as bits 0-29 + * \param value Values to set + * + * For each 1 bit in "mask", switch that pin to the direction given by + * corresponding bit in "value", leaving other pins unchanged. + * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, + * simultaneously. + */ +static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) { + sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask; +} + +/*! \brief Set direction of all pins simultaneously. + * \ingroup hardware_gpio + * + * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in + */ +static inline void gpio_set_dir_all_bits(uint32_t values) { + sio_hw->gpio_oe = values; +} + +/*! \brief Set a single GPIO direction + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \param out true for out, false for in + */ +static inline void gpio_set_dir(uint gpio, bool out) { + uint32_t mask = 1ul << gpio; + if (out) + gpio_set_dir_out_masked(mask); + else + gpio_set_dir_in_masked(mask); +} + +/*! \brief Check if a specific GPIO direction is OUT + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return true if the direction for the pin is OUT + */ +static inline bool gpio_is_dir_out(uint gpio) { + return !!(sio_hw->gpio_oe & (1u << (gpio))); +} + +/*! \brief Get a specific GPIO direction + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return 1 for out, 0 for in + */ +static inline uint gpio_get_dir(uint gpio) { + return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway +} + +extern void gpio_debug_pins_init(); + +#ifdef __cplusplus +} +#endif + + +// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio +#ifndef PICO_DEBUG_PIN_BASE +#define PICO_DEBUG_PIN_BASE 19u +#endif + +// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio +#ifndef PICO_DEBUG_PIN_COUNT +#define PICO_DEBUG_PIN_COUNT 3u +#endif + +#ifndef __cplusplus +// note these two macros may only be used once per and only apply per compilation unit (hence the CU_) +#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins; +#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x); +#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p)) +#else +#define CU_REGISTER_DEBUG_PINS(p...) \ + enum DEBUG_PIN_TYPE { _none = 0, p }; \ + template class __debug_pin_settings { \ + public: \ + static inline bool enabled() { return false; } \ + }; +#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings::enabled() { return true; }; +#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings

::enabled()) +#endif +#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<restart_on_next = false; + + i2c->hw->enable = 0; + + // Configure as a fast-mode master with RepStart support, 7-bit addresses + i2c->hw->con = + I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB | + I2C_IC_CON_MASTER_MODE_BITS | + I2C_IC_CON_IC_SLAVE_DISABLE_BITS | + I2C_IC_CON_IC_RESTART_EN_BITS; + + // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0. + i2c->hw->tx_tl = 0; + i2c->hw->rx_tl = 0; + + // Always enable the DREQ signalling -- harmless if DMA isn't listening + i2c->hw->dma_cr = I2C_IC_DMA_CR_TDMAE_BITS | I2C_IC_DMA_CR_RDMAE_BITS; + + // Re-sets i2c->hw->enable upon returning: + return i2c_set_baudrate(i2c, baudrate); +} + +void i2c_deinit(i2c_inst_t *i2c) { + i2c_reset(i2c); +} + +uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { + invalid_params_if(I2C, baudrate == 0); + // I2C is synchronous design that runs from clk_sys + uint freq_in = clock_get_hz(clk_sys); + + // TODO there are some subtleties to I2C timing which we are completely ignoring here + uint period = (freq_in + baudrate / 2) / baudrate; + uint hcnt = period * 3 / 5; // oof this one hurts + uint lcnt = period - hcnt; + // Check for out-of-range divisors: + invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS); + invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS); + invalid_params_if(I2C, hcnt < 8); + invalid_params_if(I2C, lcnt < 8); + + i2c->hw->enable = 0; + // Always use "fast" mode (<= 400 kHz, works fine for standard mode too) + hw_write_masked(&i2c->hw->con, + I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB, + I2C_IC_CON_SPEED_BITS + ); + i2c->hw->fs_scl_hcnt = hcnt; + i2c->hw->fs_scl_lcnt = lcnt; + i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16; + + i2c->hw->enable = 1; + return freq_in / period; +} + +void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) { + invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(I2C, i2c_reserved_addr(addr)); + i2c->hw->enable = 0; + if (slave) { + hw_clear_bits(&i2c->hw->con, + I2C_IC_CON_MASTER_MODE_BITS | + I2C_IC_CON_IC_SLAVE_DISABLE_BITS + ); + i2c->hw->sar = addr; + } else { + hw_set_bits(&i2c->hw->con, + I2C_IC_CON_MASTER_MODE_BITS | + I2C_IC_CON_IC_SLAVE_DISABLE_BITS + ); + } + i2c->hw->enable = 1; +} + +static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, + check_timeout_fn timeout_check, struct timeout_state *ts) { + invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(I2C, i2c_reserved_addr(addr)); + // Synopsys hw accepts start/stop flags alongside data items in the same + // FIFO word, so no 0 byte transfers. + invalid_params_if(I2C, len == 0); + + i2c->hw->enable = 0; + i2c->hw->tar = addr; + i2c->hw->enable = 1; + + bool abort = false; + bool timeout = false; + + uint32_t abort_reason; + size_t byte_ctr; + + for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) { + bool first = byte_ctr == 0; + bool last = byte_ctr == len - 1; + + i2c->hw->data_cmd = + !!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | + !!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | + *src++; + + do { + // Note clearing the abort flag also clears the reason, and this + // instance of flag is clear-on-read! + abort_reason = i2c->hw->tx_abrt_source; + abort = (bool) i2c->hw->clr_tx_abrt; + if (timeout_check) { + timeout = timeout_check(ts); + abort |= timeout; + } + tight_loop_contents(); + } while (!abort && !(i2c->hw->status & I2C_IC_STATUS_TFE_BITS)); + + // Note the hardware issues a STOP automatically on an abort condition. + // Note also the hardware clears RX FIFO as well as TX on abort, + // because we set hwparam IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0. + if (abort) + break; + } + + int rval; + + // A lot of things could have just happened due to the ingenious and + // creative design of I2C. Try to figure things out. + if (abort) { + if (timeout) + rval = PICO_ERROR_TIMEOUT; + else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) { + // No reported errors - seems to happen if there is nothing connected to the bus. + // Address byte not acknowledged + rval = PICO_ERROR_GENERIC; + } else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS) { + // Address acknowledged, some data not acknowledged + rval = byte_ctr; + } else { + //panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason); + rval = PICO_ERROR_GENERIC; + } + } else { + rval = byte_ctr; + } + + // nostop means we are now at the end of a *message* but not the end of a *transfer* + i2c->restart_on_next = nostop; + return rval; +} + +int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop) { + return i2c_write_blocking_internal(i2c, addr, src, len, nostop, NULL, NULL); +} + +int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, + absolute_time_t until) { + timeout_state_t ts; + return i2c_write_blocking_internal(i2c, addr, src, len, nostop, init_single_timeout_until(&ts, until), &ts); +} + +int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, + uint timeout_per_char_us) { + timeout_state_t ts; + return i2c_write_blocking_internal(i2c, addr, src, len, nostop, + init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts); +} + +static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, + check_timeout_fn timeout_check, timeout_state_t *ts) { + invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(I2C, i2c_reserved_addr(addr)); + invalid_params_if(I2C, len == 0); + + i2c->hw->enable = 0; + i2c->hw->tar = addr; + i2c->hw->enable = 1; + + bool abort = false; + bool timeout = false; + uint32_t abort_reason; + size_t byte_ctr; + + for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) { + bool first = byte_ctr == 0; + bool last = byte_ctr == len - 1; + while (!i2c_get_write_available(i2c)) + tight_loop_contents(); + + i2c->hw->data_cmd = + !!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | + !!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | + I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read + + do { + abort_reason = i2c->hw->tx_abrt_source; + abort = (bool) i2c->hw->clr_tx_abrt; + if (timeout_check) { + timeout = timeout_check(ts); + abort |= timeout; + } + } while (!abort && !i2c_get_read_available(i2c)); + + if (abort) + break; + + *dst++ = i2c->hw->data_cmd; + } + + int rval; + + if (abort) { + if (timeout) + rval = PICO_ERROR_TIMEOUT; + else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) { + // No reported errors - seems to happen if there is nothing connected to the bus. + // Address byte not acknowledged + rval = PICO_ERROR_GENERIC; + } else { +// panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason); + rval = PICO_ERROR_GENERIC; + } + } else { + rval = byte_ctr; + } + + i2c->restart_on_next = nostop; + return rval; +} + +int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop) { + return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, NULL, NULL); +} + +int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until) { + timeout_state_t ts; + return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, init_single_timeout_until(&ts, until), &ts); +} + +int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, + uint timeout_per_char_us) { + timeout_state_t ts; + return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, + init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h new file mode 100644 index 00000000000..dda598c3e0c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_I2C_H +#define _HARDWARE_I2C_H + +#include "pico.h" +#include "pico/time.h" +#include "hardware/structs/i2c.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c +#ifndef PARAM_ASSERTIONS_ENABLED_I2C +#define PARAM_ASSERTIONS_ENABLED_I2C 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/i2c.h + * \defgroup hardware_i2c hardware_i2c + * + * I2C Controller API + * + * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry + * information between the devices connected to the bus. Each device is recognized by a unique address and can operate as + * either a “transmitter†or “receiverâ€, depending on the function of the device. Devices can also be considered as masters or + * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the + * clock signals to permit that transfer. At that time, any device addressed is considered a slave. + * + * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function. + * + * The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in the datasheet. The muxing options + * give some IO flexibility, but each controller external pin should be connected to only one GPIO. + * + * Note that the controller does NOT support High speed mode or Ultra-fast speed mode, the fastest operation being fast mode plus + * at up to 1000Kb/s. + * + * See the datasheet for more information on the I2C controller and its usage. + * + * \subsection i2c_example Example + * \addtogroup hardware_i2c + * \include bus_scan.c + */ + +typedef struct i2c_inst i2c_inst_t; + +/** The I2C identifiers for use in I2C functions. + * + * e.g. i2c_init(i2c0, 48000) + * + * \ingroup hardware_i2c + * @{ + */ +extern i2c_inst_t i2c0_inst; +extern i2c_inst_t i2c1_inst; + +#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0 +#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1 + +/** @} */ + +// ---------------------------------------------------------------------------- +// Setup + +/*! \brief Initialise the I2C HW block + * \ingroup hardware_i2c + * + * Put the I2C hardware into a known state, and enable it. Must be called + * before other functions. By default, the I2C is configured to operate as a + * master. + * + * The I2C bus frequency is set as close as possible to requested, and + * the return actual rate set is returned + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) + * \return Actual set baudrate + */ +uint i2c_init(i2c_inst_t *i2c, uint baudrate); + +/*! \brief Disable the I2C HW block + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * + * Disable the I2C again if it is no longer used. Must be reinitialised before + * being used again. + */ +void i2c_deinit(i2c_inst_t *i2c); + +/*! \brief Set I2C baudrate + * \ingroup hardware_i2c + * + * Set I2C bus frequency as close as possible to requested, and return actual + * rate set. + * Baudrate may not be as exactly requested due to clocking limitations. + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) + * \return Actual set baudrate + */ +uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate); + +/*! \brief Set I2C port to slave mode + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param slave true to use slave mode, false to use master mode + * \param addr If \p slave is true, set the slave address to this value + */ +void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr); + +// ---------------------------------------------------------------------------- +// Generic input/output + +struct i2c_inst { + i2c_hw_t *hw; + bool restart_on_next; +}; + +/*! \brief Convert I2c instance to hardware instance number + * \ingroup hardware_i2c + * + * \param i2c I2C instance + * \return Number of UART, 0 or 1. + */ +static inline uint i2c_hw_index(i2c_inst_t *i2c) { + invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); + return i2c == i2c1 ? 1 : 0; +} + +static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) { + i2c_hw_index(i2c); // check it is a hw i2c + return i2c->hw; +} + +/*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached. + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to write to + * \param src Pointer to data to send + * \param len Length of data in bytes to send + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \param until The absolute time that the block will wait until the entire transaction is complete. Note, an individual timeout of + * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent + * bytes fails to transfer within that sub timeout, the function will return with an error. + * + * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. + */ +int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, absolute_time_t until); + +/*! \brief Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached. + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to read from + * \param dst Pointer to buffer to receive data + * \param len Length of data in bytes to receive + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \param until The absolute time that the block will wait until the entire transaction is complete. + * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. + */ +int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until); + +/*! \brief Attempt to write specified number of bytes to address, with timeout + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to write to + * \param src Pointer to data to send + * \param len Length of data in bytes to send + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \param timeout_us The time that the function will wait for the entire transaction to complete. Note, an individual timeout of + * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent + * bytes fails to transfer within that sub timeout, the function will return with an error. + * + * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. + */ +static inline int i2c_write_timeout_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_us) { + absolute_time_t t = make_timeout_time_us(timeout_us); + return i2c_write_blocking_until(i2c, addr, src, len, nostop, t); +} + +int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_per_char_us); + +/*! \brief Attempt to read specified number of bytes from address, with timeout + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to read from + * \param dst Pointer to buffer to receive data + * \param len Length of data in bytes to receive + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \param timeout_us The time that the function will wait for the entire transaction to complete + * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred. + */ +static inline int i2c_read_timeout_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_us) { + absolute_time_t t = make_timeout_time_us(timeout_us); + return i2c_read_blocking_until(i2c, addr, dst, len, nostop, t); +} + +int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_per_char_us); + +/*! \brief Attempt to write specified number of bytes to address, blocking + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to write to + * \param src Pointer to data to send + * \param len Length of data in bytes to send + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present. + */ +int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop); + +/*! \brief Attempt to read specified number of bytes from address, blocking + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param addr Address of device to read from + * \param dst Pointer to buffer to receive data + * \param len Length of data in bytes to receive + * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), + * and the next transfer will begin with a Restart rather than a Start. + * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present. + */ +int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop); + + +/*! \brief Determine non-blocking write space available + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \return 0 if no space is available in the I2C to write more data. If return is nonzero, at + * least that many bytes can be written without blocking. + */ +static inline size_t i2c_get_write_available(i2c_inst_t *i2c) { + const size_t IC_TX_BUFFER_DEPTH = 32; + return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr; +} + +/*! \brief Determine number of bytes received + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \return 0 if no data available, if return is nonzero at + * least that many bytes can be read without blocking. + */ +static inline size_t i2c_get_read_available(i2c_inst_t *i2c) { + return i2c_get_hw(i2c)->rxflr; +} + +/*! \brief Write direct to TX FIFO + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param src Data to send + * \param len Number of bytes to send + * + * Writes directly to the to I2C TX FIFO which us mainly useful for + * slave-mode operation. + */ +static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) { + for (size_t i = 0; i < len; ++i) { + // TODO NACK or STOP on end? + while (!i2c_get_write_available(i2c)) + tight_loop_contents(); + i2c_get_hw(i2c)->data_cmd = *src++; + } +} + +/*! \brief Write direct to TX FIFO + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param dst Buffer to accept data + * \param len Number of bytes to send + * + * Reads directly from the I2C RX FIFO which us mainly useful for + * slave-mode operation. + */ +static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { + for (size_t i = 0; i < len; ++i) { + while (!i2c_get_read_available(i2c)) + tight_loop_contents(); + *dst++ = i2c_get_hw(i2c)->data_cmd; + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/CMakeLists.txt new file mode 100644 index 00000000000..d6d693fcde5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(interp) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h new file mode 100644 index 00000000000..18cefc53eca --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_INTERP_H +#define _HARDWARE_INTERP_H + +#include "pico.h" +#include "hardware/structs/interp.h" +#include "hardware/regs/sio.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_INTERP, Enable/disable assertions in the interpolation module, type=bool, default=0, group=hardware_interp +#ifndef PARAM_ASSERTIONS_ENABLED_INTERP +#define PARAM_ASSERTIONS_ENABLED_INTERP 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/interp.h + * \defgroup hardware_interp hardware_interp + * + * Hardware Interpolator API + * + * Each core is equipped with two interpolators (INTERP0 and INTERP1) which can be used to accelerate + * tasks by combining certain pre-configured simple operations into a single processor cycle. Intended + * for cases where the pre-configured operation is repeated a large number of times, this results in + * code which uses both fewer CPU cycles and fewer CPU registers in the time critical sections of the + * code. + * + * The interpolators are used heavily to accelerate audio operations within the SDK, but their + * flexible configuration make it possible to optimise many other tasks such as quantization and + * dithering, table lookup address generation, affine texture mapping, decompression and linear feedback. + * + * Please refer to the RP2040 datasheet for more information on the HW interpolators and how they work. + */ + +#define interp0 interp0_hw +#define interp1 interp1_hw + +/** \brief Interpolator configuration + * \defgroup interp_config interp_config + * \ingroup hardware_interp + * + * Each interpolator needs to be configured, these functions provide handy helpers to set up configuration + * structures. + * + */ + +typedef struct { + uint32_t ctrl; +} interp_config; + +static inline uint interp_index(interp_hw_t *interp) { + assert(interp == interp0 || interp == interp1); + return interp == interp1 ? 1 : 0; +} + +/*! \brief Claim the interpolator lane specified + * \ingroup hardware_interp + * + * Use this function to claim exclusive access to the specified interpolator lane. + * + * This function will panic if the lane is already claimed. + * + * \param interp Interpolator on which to claim a lane. interp0 or interp1 + * \param lane The lane number, 0 or 1. + */ +void interp_claim_lane(interp_hw_t *interp, uint lane); + +/*! \brief Claim the interpolator lanes specified in the mask + * \ingroup hardware_interp + * + * \param interp Interpolator on which to claim lanes. interp0 or interp1 + * \param lane_mask Bit pattern of lanes to claim (only bits 0 and 1 are valid) + */ +void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask); + +/*! \brief Release a previously claimed interpolator lane + * \ingroup hardware_interp + * + * \param interp Interpolator on which to release a lane. interp0 or interp1 + * \param lane The lane number, 0 or 1 + */ +void interp_unclaim_lane(interp_hw_t *interp, uint lane); + +/*! \brief Set the interpolator shift value + * \ingroup interp_config + * + * Sets the number of bits the accumulator is shifted before masking, on each iteration. + * + * \param c Pointer to an interpolator config + * \param shift Number of bits + */ +static inline void interp_config_set_shift(interp_config *c, uint shift) { + valid_params_if(INTERP, shift < 32); + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | + ((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS); +} + +/*! \brief Set the interpolator mask range + * \ingroup interp_config + * + * Sets the range of bits (least to most) that are allowed to pass through the interpolator + * + * \param c Pointer to interpolation config + * \param mask_lsb The least significant bit allowed to pass + * \param mask_msb The most significant bit allowed to pass + */ +static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) { + valid_params_if(INTERP, mask_msb < 32); + valid_params_if(INTERP, mask_lsb <= mask_msb); + c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) | + ((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) | + ((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS); +} + +/*! \brief Enable cross input + * \ingroup interp_config + * + * Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware. + * This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the + * shift+mask bypass + * + * \param c Pointer to interpolation config + * \param cross_input If true, enable the cross input. + */ +static inline void interp_config_set_cross_input(interp_config *c, bool cross_input) { + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) | + (cross_input ? SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS : 0); +} + +/*! \brief Enable cross results + * \ingroup interp_config + * + * Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation. + * + * \param c Pointer to interpolation config + * \param cross_result If true, enables the cross result + */ +static inline void interp_config_set_cross_result(interp_config *c, bool cross_result) { + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) | + (cross_result ? SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS : 0); +} + +/*! \brief Set sign extension + * \ingroup interp_config + * + * Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits + * before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor. + * + * \param c Pointer to interpolation config + * \param _signed If true, enables sign extension + */ +static inline void interp_config_set_signed(interp_config *c, bool _signed) { + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) | + (_signed ? SIO_INTERP0_CTRL_LANE0_SIGNED_BITS : 0); +} + +/*! \brief Set raw add option + * \ingroup interp_config + * + * When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result. + * + * \param c Pointer to interpolation config + * \param add_raw If true, enable raw add option. + */ +static inline void interp_config_set_add_raw(interp_config *c, bool add_raw) { + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) | + (add_raw ? SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS : 0); +} + +/*! \brief Set blend mode + * \ingroup interp_config + * + * If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + * by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) + * + * LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + * + * FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + * + * LANE1 SIGNED flag controls whether the interpolation is signed or unsig + * + * \param c Pointer to interpolation config + * \param blend Set true to enable blend mode. +*/ +static inline void interp_config_set_blend(interp_config *c, bool blend) { + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) | + (blend ? SIO_INTERP0_CTRL_LANE0_BLEND_BITS : 0); +} + +/*! \brief Set interpolator clamp mode (Interpolator 1 only) + * \ingroup interp_config + * + * Only present on INTERP1 on each core. If CLAMP mode is enabled: + * - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. + * - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + * + * \param c Pointer to interpolation config + * \param clamp Set true to enable clamp mode + */ +static inline void interp_config_set_clamp(interp_config *c, bool clamp) { + c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) | + (clamp ? SIO_INTERP1_CTRL_LANE0_CLAMP_BITS : 0); +} + +/*! \brief Set interpolator Force bits + * \ingroup interp_config + * + * ORed into bits 29:28 of the lane result presented to the processor on the bus. + * + * No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + * of pointers into flash or SRAM + * + * \param c Pointer to interpolation config + * \param bits Sets the force bits to that specified. Range 0-3 (two bits) + */ +static inline void interp_config_set_force_bits(interp_config *c, uint bits) { + invalid_params_if(INTERP, bits > 3); + // note cannot use hw_set_bits on SIO + c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | + (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB); +} + +/*! \brief Get a default configuration + * \ingroup interp_config + * + * \return A default interpolation configuration + */ +static inline interp_config interp_default_config() { + interp_config c = {0}; + // Just pass through everything + interp_config_set_mask(&c, 0, 31); + return c; +} + +/*! \brief Send configuration to a lane + * \ingroup interp_config + * + * If an invalid configuration is specified (ie a lane specific item is set on wrong lane), + * depending on setup this function can panic. + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane to set + * \param config Pointer to interpolation config + */ + +static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) { + invalid_params_if(INTERP, lane > 1); + invalid_params_if(INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS && + (!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit + invalid_params_if(INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS && + (interp_index(interp) || lane)); // only interp0 lane 0 has blend bit + interp->ctrl[lane] = config->ctrl; +} + +/*! \brief Directly set the force bits on a specified lane + * \ingroup hardware_interp + * + * These bits are ORed into bits 29:28 of the lane result presented to the processor on the bus. + * There is no effect on the internal 32-bit datapath. + * + * Useful for using a lane to generate sequence of pointers into flash or SRAM, saving a subsequent + * OR or add operation. + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane to set + * \param bits The bits to set (bits 0 and 1, value range 0-3) + */ +static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) { + // note cannot use hw_set_bits on SIO + interp->ctrl[lane] |= (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB); +} + +typedef struct { + io_rw_32 accum[2]; + io_rw_32 base[3]; + io_rw_32 ctrl[2]; +} interp_hw_save_t; + +/*! \brief Save the specified interpolator state + * \ingroup hardware_interp + * + * Can be used to save state if you need an interpolator for another purpose, state + * can then be recovered afterwards and continue from that point + * + * \param interp Interpolator instance, interp0 or interp1. + * \param saver Pointer to the save structure to fill in + */ +void interp_save(interp_hw_t *interp, interp_hw_save_t *saver); + +/*! \brief Restore an interpolator state + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param saver Pointer to save structure to reapply to the specified interpolator + */ +void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver); + +/*! \brief Sets the interpolator base register by lane + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 or 2 + * \param val The value to apply to the register + */ +static inline void interp_set_base(interp_hw_t *interp, uint lane, uint32_t val) { + interp->base[lane] = val; +} + +/*! \brief Gets the content of interpolator base register by lane + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 or 2 + * \return The current content of the lane base register + */ +static inline uint32_t interp_get_base(interp_hw_t *interp, uint lane) { + return interp->base[lane]; +} + +/*! \brief Sets the interpolator base registers simultaneously + * \ingroup hardware_interp + * + * The lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + * Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set. + * + * \param interp Interpolator instance, interp0 or interp1. + * \param val The value to apply to the register + */ +static inline void interp_set_base_both(interp_hw_t *interp, uint32_t val) { + interp->base01 = val; +} + + +/*! \brief Sets the interpolator accumulator register by lane + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \param val The value to apply to the register + */ +static inline void interp_set_accumulator(interp_hw_t *interp, uint lane, uint32_t val) { + interp->accum[lane] = val; +} + +/*! \brief Gets the content of the interpolator accumulator register by lane + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \return The current content of the register + */ +static inline uint32_t interp_get_accumulator(interp_hw_t *interp, uint lane) { + return interp->accum[lane]; +} + +/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \return The content of the lane result register + */ +static inline uint32_t interp_pop_lane_result(interp_hw_t *interp, uint lane) { + return interp->pop[lane]; +} + +/*! \brief Read lane result + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \return The content of the lane result register + */ +static inline uint32_t interp_peek_lane_result(interp_hw_t *interp, uint lane) { + return interp->peek[lane]; +} + +/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \return The content of the FULL register + */ +static inline uint32_t interp_pop_full_result(interp_hw_t *interp) { + return interp->pop[2]; +} + +/*! \brief Read lane result + * \ingroup hardware_interp + * + * \param interp Interpolator instance, interp0 or interp1. + * \return The content of the FULL register + */ +static inline uint32_t interp_peek_full_result(interp_hw_t *interp) { + return interp->peek[2]; +} + +/*! \brief Add to accumulator + * \ingroup hardware_interp + * + * Atomically add the specified value to the accumulator on the specified lane + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \param val Value to add + * \return The content of the FULL register + */ +static inline void interp_add_accumulater(interp_hw_t *interp, uint lane, uint32_t val) { + interp->add_raw[lane] = val; +} + +/*! \brief Get raw lane value + * \ingroup hardware_interp + * + * Returns the raw shift and mask value from the specified lane, BASE0 is NOT added + * + * \param interp Interpolator instance, interp0 or interp1. + * \param lane The lane number, 0 or 1 + * \return The raw shift/mask value + */ +static inline uint32_t interp_get_raw(interp_hw_t *interp, uint lane) { + return interp->add_raw[lane]; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c new file mode 100644 index 00000000000..5fdad93c191 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/interp.h" +#include "hardware/structs/sio.h" +#include "hardware/claim.h" + +check_hw_size(interp_hw_t, SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET); + +check_hw_layout(sio_hw_t, interp, SIO_INTERP0_ACCUM0_OFFSET); + +static_assert(NUM_DMA_CHANNELS <= 16, ""); + +static uint8_t _claimed; + +void interp_claim_lane(interp_hw_t *interp, uint lane) { + valid_params_if(INTERP, lane < 2); + uint bit = (interp_index(interp) << 1u) | lane; + hw_claim_or_assert((uint8_t *) &_claimed, bit, "Lane is already claimed"); +} + +void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) { + valid_params_if(INTERP, lane_mask && lane_mask <= 0x3); + if (lane_mask & 1u) interp_claim_lane(interp, 0); + if (lane_mask & 2u) interp_claim_lane(interp, 1); +} + +void interp_unclaim_lane(interp_hw_t *interp, uint lane) { + valid_params_if(INTERP, lane < 2); + uint bit = (interp_index(interp) << 1u) | lane; + hw_claim_clear((uint8_t *) &_claimed, bit); +} + +void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) { + saver->accum[0] = interp->accum[0]; + saver->accum[1] = interp->accum[1]; + saver->base[0] = interp->base[0]; + saver->base[1] = interp->base[1]; + saver->base[2] = interp->base[2]; + saver->ctrl[0] = interp->ctrl[0]; + saver->ctrl[1] = interp->ctrl[1]; +} + +void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver) { + interp->accum[0] = saver->accum[0]; + interp->accum[1] = saver->accum[1]; + interp->base[0] = saver->base[0]; + interp->base[1] = saver->base[1]; + interp->base[2] = saver->base[2]; + interp->ctrl[0] = saver->ctrl[0]; + interp->ctrl[1] = saver->ctrl[1]; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/CMakeLists.txt new file mode 100644 index 00000000000..c2182319d1c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/CMakeLists.txt @@ -0,0 +1,6 @@ +pico_simple_hardware_target(irq) + +# additional sources/libraries + +target_sources(hardware_irq INTERFACE ${CMAKE_CURRENT_LIST_DIR}/irq_handler_chain.S) +target_link_libraries(hardware_irq INTERFACE pico_sync) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h new file mode 100644 index 00000000000..6075118f273 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_IRQ_H_ +#define _HARDWARE_IRQ_H_ + +// These two config items are also used by assembler, so keeping separate +// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum Number of shared IRQ handers, default=4, advanced=true, group=hardware_irq +#ifndef PICO_MAX_SHARED_IRQ_HANDLERS +#define PICO_MAX_SHARED_IRQ_HANDLERS 4u +#endif + +// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handers, type=bool, default=0, group=hardware_irq +#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS +#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 +#endif + +#ifndef __ASSEMBLER__ + +#include "pico.h" +#include "hardware/regs/intctrl.h" +#include "hardware/regs/m0plus.h" + +/** \file irq.h + * \defgroup hardware_irq hardware_irq + * + * Hardware interrupt handling + * + * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC). + * + * Interrupts are identified by a number from 0 to 31. + * + * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). + * + * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts + * where there is one IO interrupt per bank, per core. These are completely independent, so for example, processor 0 can be + * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. + * + * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). + * + * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions + * or starvation of one of the cores. Additionally don't forget that disabling interrupts on one core does not disable interrupts + * on the other core. + * + * There are three different ways to set handlers for an IRQ: + * - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source + * - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core + * - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and + * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). + * + * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will + * be in r0. + * + * \section interrupt_nums Interrupt Numbers + * + * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly. + * + * IRQ | Interrupt Source + * ----|----------------- + * 0 | TIMER_IRQ_0 + * 1 | TIMER_IRQ_1 + * 2 | TIMER_IRQ_2 + * 3 | TIMER_IRQ_3 + * 4 | PWM_IRQ_WRAP + * 5 | USBCTRL_IRQ + * 6 | XIP_IRQ + * 7 | PIO0_IRQ_0 + * 8 | PIO0_IRQ_1 + * 9 | PIO1_IRQ_0 + * 10 | PIO1_IRQ_1 + * 11 | DMA_IRQ_0 + * 12 | DMA_IRQ_1 + * 13 | IO_IRQ_BANK0 + * 14 | IO_IRQ_QSPI + * 15 | SIO_IRQ_PROC0 + * 16 | SIO_IRQ_PROC1 + * 17 | CLOCKS_IRQ + * 18 | SPI0_IRQ + * 19 | SPI1_IRQ + * 20 | UART0_IRQ + * 21 | UART1_IRQ + * 22 | ADC0_IRQ_FIFO + * 23 | I2C0_IRQ + * 24 | I2C1_IRQ + * 25 | RTC_IRQ + * + */ + +// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq +#ifndef PICO_DEFAULT_IRQ_PRIORITY +#define PICO_DEFAULT_IRQ_PRIORITY 0x80 +#endif + +#define PICO_LOWEST_IRQ_PRIORITY 0x01 +#define PICO_HIGHEST_IRQ_PRIORITY 0xff + +// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq +#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY +#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80 +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_IRQ, Enable/disable assertions in the IRQ module, type=bool, default=0, group=hardware_irq +#ifndef PARAM_ASSERTIONS_ENABLED_IRQ +#define PARAM_ASSERTIONS_ENABLED_IRQ 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Interrupt handler function type + * \ingroup hardware_irq + * + * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions + */ +typedef void (*irq_handler_t)(); + +/*! \brief Set specified interrupts priority + * \ingroup hardware_irq + * + * \param num Interrupt number + * \param hardware_priority Priority to set. Hardware priorities range from 0 (lowest) to 255 (highest) though only + * the top 2 bits are significant on ARM Cortex M0+. To make it easier to specify higher or lower priorities + * than the default, all IRQ priorities are initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + */ +void irq_set_priority(uint num, uint8_t hardware_priority); + +/*! \brief Enable or disable a specific interrupt on the executing core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \param enabled true to enable the interrupt, false to disable + */ +void irq_set_enabled(uint num, bool enabled); + +/*! \brief Determine if a specific interrupt is enabled on the executing core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \return true if the interrupt is enabled + */ +bool irq_is_enabled(uint num); + +/*! \brief Enable/disable multiple interrupts on the executing core + * \ingroup hardware_irq + * + * \param mask 32-bit mask with one bits set for the interrupts to enable/disable + * \param enabled true to enable the interrupts, false to disable them. + */ +void irq_set_mask_enabled(uint32_t mask, bool enabled); + +/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core. + * \ingroup hardware_irq + * + * Use this method to set a handler for single IRQ source interrupts, or when + * your code, use case or performance requirements dictate that there should + * no other handlers for the interrupt. + * + * This method will assert if there is already any sort of interrupt handler installed + * for the specified irq number. + * + * \param num Interrupt number \ref interrupt_nums + * \param handler The handler to set. See \ref irq_handler_t + * \see irq_add_shared_handler + */ +void irq_set_exclusive_handler(uint num, irq_handler_t handler); + +/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core. + * \ingroup hardware_irq + * + * This method will return an exclusive IRQ handler set on this core + * by irq_set_exclusive_handler if there is one. + * + * \param num Interrupt number \ref interrupt_nums + * \see irq_set_exclusive_handler + * \return handler The handler if an exclusive handler is set for the IRQ, + * NULL if no handler is set or shared/shareable handlers are installed + */ +irq_handler_t irq_get_exclusive_handler(uint num); + +/*! \brief Add a shared interrupt handler for an interrupt on the executing core + * \ingroup hardware_irq + * + * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs). + * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The + * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt. + * + * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if + * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers + * would be exceeded. + * + * \param num Interrupt number + * \param handler The handler to set. See \ref irq_handler_t + * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called. + * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based + * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good + * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of + * the priority range by default. + * + * \see irq_set_exclusive_handler + */ +void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); + +/*! \brief Remove a specific interrupt handler for the given irq number on the executing core + * \ingroup hardware_irq + * + * This method may be used to remove an irq set via either irq_set_exclusive_handler() or + * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given + * IRQ number + * + * \note This method may *only* be called from user (non IRQ code) or from within the handler + * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call + * from another IRQ will cause an assertion. + * + * \param num Interrupt number \ref interrupt_nums + * \param handler The handler to removed. + * \see irq_set_exclusive_handler + * \see irq_add_shared_handler + */ +void irq_remove_handler(uint num, irq_handler_t handler); + +/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR) + * of the execution core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \return the address stored in the VTABLE for the given irq number + */ +irq_handler_t irq_get_vtable_handler(uint num); + +/*! \brief Clear a specific interrupt on the executing core + * \ingroup hardware_irq + * + * \param int_num Interrupt number \ref interrupt_nums + */ +static inline void irq_clear(uint int_num) { + *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F))); +} + +/*! \brief Force an interrupt to pending on the executing core + * \ingroup hardware_irq + * + * This should generally not be used for IRQs connected to hardware. + * + * \param num Interrupt number \ref interrupt_nums + */ +void irq_set_pending(uint num); + + +/*! \brief Perform IRQ priority intiialization for the current core + * + * \note This is an internal method and user should generally not call it. + */ +void irq_init_priorities(); +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c new file mode 100644 index 00000000000..255c00df808 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/irq.h" +#include "hardware/regs/m0plus.h" +#include "hardware/platform_defs.h" +#include "hardware/structs/scb.h" + +#include "pico/mutex.h" +#include "pico/assert.h" + +extern void __unhandled_user_irq(); +extern uint __get_current_exception(); + +static inline irq_handler_t *get_vtable() { + return (irq_handler_t *) scb_hw->vtor; +} + +static inline void *add_thumb_bit(void *addr) { + return (void *) (((uintptr_t) addr) | 0x1); +} + +static inline void *remove_thumb_bit(void *addr) { + return (void *) (((uintptr_t) addr) & ~0x1); +} + +static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) { + // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness) + get_vtable()[16 + num] = handler; + __dmb(); + spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save); +} + +static inline void check_irq_param(uint num) { + invalid_params_if(IRQ, num >= NUM_IRQS); +} + +void irq_set_enabled(uint num, bool enabled) { + check_irq_param(num); + irq_set_mask_enabled(1u << num, enabled); +} + +bool irq_is_enabled(uint num) { + check_irq_param(num); + return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); +} + +void irq_set_mask_enabled(uint32_t mask, bool enabled) { + if (enabled) { + // Clear pending before enable + // (if IRQ is actually asserted, it will immediately re-pend) + *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask; + *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask; + } else { + *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask; + } +} + +void irq_set_pending(uint num) { + check_irq_param(num); + *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; +} + +#if PICO_MAX_SHARED_IRQ_HANDLERS +// limited by 8 bit relative links (and reality) +static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, ""); + +// note these are not real functions, they are code fragments (i.e. don't call them) +extern void irq_handler_chain_first_slot(); +extern void irq_handler_chain_remove_tail(); + +extern struct irq_handler_chain_slot { + // first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next + // in chain (or end of chain handler) + uint16_t inst1; + uint16_t inst2; + uint16_t inst3; + union { + // when a handler is removed while executing, it needs an extra instruction, which overwrites + // the link and the priority; this is ok because no one else is modifying the chain, as + // the chain is effectively core local, and the user code which might still need this link + // disable the IRQ in question before updating, which means we aren't executing! + struct { + int8_t link; + uint8_t priority; + }; + uint16_t inst4; + }; + irq_handler_t handler; +} irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS]; + +static int8_t irq_hander_chain_free_slot_head; +#endif + +static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) { + return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots); +} + +irq_handler_t irq_get_vtable_handler(uint num) { + check_irq_param(num); + return get_vtable()[16 + num]; +} + +void irq_set_exclusive_handler(uint num, irq_handler_t handler) { + check_irq_param(num); +#if !PICO_NO_RAM_VECTOR_TABLE + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); + uint32_t save = spin_lock_blocking(lock); + __unused irq_handler_t current = irq_get_vtable_handler(num); + hard_assert(current == __unhandled_user_irq || current == handler); + set_raw_irq_handler_and_unlock(num, handler, save); +#else + panic_unsupported(); +#endif +} + +irq_handler_t irq_get_exclusive_handler(uint num) { + check_irq_param(num); +#if !PICO_NO_RAM_VECTOR_TABLE + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); + uint32_t save = spin_lock_blocking(lock); + irq_handler_t current = irq_get_vtable_handler(num); + spin_unlock(lock, save); + if (current == __unhandled_user_irq || is_shared_irq_raw_handler(current)) { + return NULL; + } + return current; +#else + panic_unsupported(); +#endif +} + + +static uint16_t make_branch(uint16_t *from, void *to) { + uint32_t ui_from = (uint32_t)from; + uint32_t ui_to = (uint32_t)to; + uint32_t delta = (ui_to - ui_from - 4) / 2; + assert(!(delta >> 11u)); + return 0xe000 | (delta & 0x7ff); +} + +static void insert_branch_and_link(uint16_t *from, void *to) { + uint32_t ui_from = (uint32_t)from; + uint32_t ui_to = (uint32_t)to; + uint32_t delta = (ui_to - ui_from - 4) / 2; + assert(!(delta >> 11u)); + from[0] = 0xf000 | ((delta >> 11u) & 0x7ffu); + from[1] = 0xf800 | (delta & 0x7ffu); +} + +static inline void *resolve_branch(uint16_t *inst) { + assert(0x1c == (*inst)>>11u); + int32_t i_addr = (*inst) << 21u; + i_addr /= (int32_t)(1u<<21u); + return inst + 2 + i_addr; +} + +// GCC produces horrible code for subtraction of pointers here, and it was bugging me +static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) { + static_assert(sizeof(struct irq_handler_chain_slot) == 12, ""); + int32_t result; + // return (to - from); + // note this implementation has limited range, but is fine for plenty more than -128->127 result + asm (".syntax unified\n" + "subs %1, %2\n" + "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding) + "ldr %0, =0xaaaa\n" + "muls %0, %1\n" + "lsrs %0, 20\n" + : "=l" (result), "+l" (to) + : "l" (from) + : + ); + return result; +} + +void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) { + check_irq_param(num); +#if PICO_DISABLE_SHARED_IRQ_HANDLERS + +#endif +#if PICO_NO_RAM_VECTOR_TABLE || !PICO_MAX_SHARED_IRQ_HANDLERS + panic_unsupported() +#else + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); + uint32_t save = spin_lock_blocking(lock); + hard_assert(irq_hander_chain_free_slot_head >= 0); + struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head]; + int slot_index = irq_hander_chain_free_slot_head; + irq_hander_chain_free_slot_head = slot->link; + irq_handler_t vtable_handler = get_vtable()[16 + num]; + if (!is_shared_irq_raw_handler(vtable_handler)) { + // start new chain + hard_assert(vtable_handler == __unhandled_user_irq); + struct irq_handler_chain_slot slot_data = { + .inst1 = 0xa100, // add r1, pc, #0 + .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot + .inst3 = 0xbd00, // pop {pc} + .link = -1, + .priority = order_priority, + .handler = handler + }; + *slot = slot_data; + vtable_handler = (irq_handler_t)add_thumb_bit(slot); + } else { + assert(!((((uintptr_t)vtable_handler) - ((uintptr_t)irq_handler_chain_slots) - 1)%sizeof(struct irq_handler_chain_slot))); + struct irq_handler_chain_slot *prev_slot = NULL; + struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler); + struct irq_handler_chain_slot *cur_slot = existing_vtable_slot; + while (cur_slot->priority > order_priority) { + prev_slot = cur_slot; + if (cur_slot->link < 0) break; + cur_slot = &irq_handler_chain_slots[cur_slot->link]; + } + if (prev_slot) { + // insert into chain + struct irq_handler_chain_slot slot_data = { + .inst1 = 0x4801, // ldr r0, [pc, #4] + .inst2 = 0x4780, // blx r0 + .inst3 = prev_slot->link >= 0 ? + make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot + 0xbd00, // pop {pc} + .link = prev_slot->link, + .priority = order_priority, + .handler = handler + }; + // update code and data links + prev_slot->inst3 = make_branch(&prev_slot->inst3, slot), + prev_slot->link = slot_index; + *slot = slot_data; + } else { + // update with new chain head + struct irq_handler_chain_slot slot_data = { + .inst1 = 0xa100, // add r1, pc, #0 + .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot + .inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot + .link = slot_diff(existing_vtable_slot, irq_handler_chain_slots), + .priority = order_priority, + .handler = handler + }; + *slot = slot_data; + // fixup previous head slot + existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4] + existing_vtable_slot->inst2 = 0x4780; // blx r0 + vtable_handler = (irq_handler_t)add_thumb_bit(slot); + } + } + set_raw_irq_handler_and_unlock(num, vtable_handler, save); +#endif +} + +void irq_remove_handler(uint num, irq_handler_t handler) { +#if !PICO_NO_RAM_VECTOR_TABLE + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); + uint32_t save = spin_lock_blocking(lock); + irq_handler_t vtable_handler = get_vtable()[16 + num]; + if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) { +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS + if (is_shared_irq_raw_handler(vtable_handler)) { + // This is a bit tricky, as an executing IRQ handler doesn't take a lock. + + // First thing to do is to disable the IRQ in question; that takes care of calls from user code. + // Note that a irq handler chain is local to our own core, so we don't need to worry about the other core + bool was_enabled = irq_is_enabled(num); + irq_set_enabled(num, false); + __dmb(); + + // It is possible we are being called while an IRQ for this chain is already in progress. + // The issue we have here is that we must not free a slot that is currently being executed, because + // inst3 is still to be executed, and inst3 might get overwritten if the slot is re-used. + + // By disallowing other exceptions from removing an IRQ handler (which seems fair) + // we now only have to worry about removing a slot from a chain that is currently executing. + + // Note we expect that the slot we are deleting is the one that is executing. + // In particular, bad things happen if the caller were to delete the handler in the chain + // before it. This is not an allowed use case though, and I can't imagine anyone wanting to in practice. + // Sadly this is not something we can detect. + + uint exception = __get_current_exception(); + hard_assert(!exception || exception == num + 16); + + struct irq_handler_chain_slot *prev_slot = NULL; + struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler); + struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot; + int to_free_slot_index = to_free_slot - irq_handler_chain_slots; + while (to_free_slot->handler != handler) { + prev_slot = to_free_slot; + if (to_free_slot->link < 0) break; + to_free_slot = &irq_handler_chain_slots[to_free_slot->link]; + } + if (to_free_slot->handler == handler) { + int next_slot_index = to_free_slot->link; + if (next_slot_index >= 0) { + // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid + // Note this only matters in the exception case anyway, and it that case, we will skip the next handler, + // however in that case it's IRQ cause should immediately cause re-entry of the IRQ and the only side + // effect will be that there was potentially brief out of priority order execution of the handlers + struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index]; + to_free_slot->handler = next_slot->handler; + to_free_slot->priority = next_slot->priority; + to_free_slot->link = next_slot->link; + to_free_slot->inst3 = next_slot->link >= 0 ? + make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot + 0xbd00; // pop {pc} + + // add old next slot back to free list + next_slot->link = irq_hander_chain_free_slot_head; + irq_hander_chain_free_slot_head = next_slot_index; + } else { + // Slot being removed is at the end of the chain + if (!exception) { + // case when we're not in exception, we physically unlink now + if (prev_slot) { + // chain is not empty + prev_slot->link = -1; + prev_slot->inst3 = 0xbd00; // pop {pc} + } else { + // chain is not empty + vtable_handler = __unhandled_user_irq; + } + // add slot back to free list + to_free_slot->link = irq_hander_chain_free_slot_head; + irq_hander_chain_free_slot_head = to_free_slot_index; + } else { + // since we are the last slot we know that our inst3 hasn't executed yet, so we change + // it to bl to irq_handler_chain_remove_tail which will remove the slot. + // NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION + // BUT THEY ARE NOT NEEDED NOW + insert_branch_and_link(&to_free_slot->inst3, irq_handler_chain_remove_tail); + } + } + } else { + assert(false); // not found + } + irq_set_enabled(num, was_enabled); + } +#else + assert(false); // not found +#endif + } else { + vtable_handler = __unhandled_user_irq; + } + set_raw_irq_handler_and_unlock(num, vtable_handler, save); +#else + panic_unsupported(); +#endif +} + +void irq_set_priority(uint num, uint8_t hardware_priority) { + check_irq_param(num); + + // note that only 32 bit writes are supported + io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); + *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); +} + +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS +// used by irq_handler_chain.S to remove the last link in a handler chain after it executes +// note this must be called only with the last slot in a chain (and during the exception) +void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) { + irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot); + assert(is_shared_irq_raw_handler(slot_handler)); + + int exception = __get_current_exception(); + assert(exception); + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); + uint32_t save = spin_lock_blocking(lock); + int slot_index = slot - irq_handler_chain_slots; + if (slot_handler == get_vtable()[exception]) { + get_vtable()[exception] = __unhandled_user_irq; + } else { + bool __unused found = false; + // need to find who points at the slot and update it + for(uint i=0;ilink = irq_hander_chain_free_slot_head; + irq_hander_chain_free_slot_head = slot_index; + spin_unlock(lock, save); +} +#endif + +void irq_init_priorities() { +#if PICO_DEFAULT_IRQ_PRIORITY != 0 + for (uint irq = 0; irq < NUM_IRQS; irq++) { + irq_set_priority(irq, PICO_DEFAULT_IRQ_PRIORITY); + } +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S new file mode 100644 index 00000000000..6a8a4b688f3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/platform_defs.h" +#include "hardware/irq.h" + +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS +.syntax unified +.cpu cortex-m0plus +.thumb + +.data +.align 2 + +.global irq_handler_chain_slots + +.global irq_handler_chain_first_slot +.global irq_handler_chain_remove_tail + +// +// These Slots make up the code and structure of the handler chains; the only external information are the VTABLE entries +// (obviously one set per core) and a free list head. Each individual handler chain starts with the VTABLE entry I +// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executble. +// +// The execution jumps (via branch instruction) from one slot to the other, then jumps to the end of chain handler. +// The entirety of the state needed to traverse the chain is contained within the slots of the chain, which is why +// a VTABLE entry is all that is needed per chain (rather than requiring a separarte set of head pointers) +// + +irq_handler_chain_slots: +.set next_slot_number, 1 +.rept PICO_MAX_SHARED_IRQ_HANDLERS + // a slot is executable and is always 3 instructions long. + .hword 0 // inst1 (either: ldr r0, [pc, #4] or for the FIRST slot : add r1, pc, #0 ) + .hword 0 // inst2 ( blx r0 b irq_handler_chain_first_slot ) + + .hword 0 // inst3 (either: b next_slot or for the LAST pop {pc} ) + + // next is a single byte index of next slot in chain (or -1 to end) +.if next_slot_number == PICO_MAX_SHARED_IRQ_HANDLERS + .byte 0xff +.else + .byte next_slot_number +.endif + // next is the 8 bit unsigned priority + .byte 0x00 +1: + // and finally the handler function pointer + .word 0x00000000 + .set next_slot_number, next_slot_number + 1 +.endr + +irq_handler_chain_first_slot: + push {lr} + ldr r0, [r1, #4] + adds r1, #1 + mov lr, r1 + bx r0 +irq_handler_chain_remove_tail: + mov r0, lr + subs r0, #9 + ldr r1, =irq_add_tail_to_free_list + blx r1 + pop {pc} + + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/CMakeLists.txt new file mode 100644 index 00000000000..ad018690bca --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/CMakeLists.txt @@ -0,0 +1,4 @@ +pico_simple_hardware_target(pio) + +# additional libraries +target_link_libraries(hardware_pio INTERFACE hardware_gpio hardware_claim) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h new file mode 100644 index 00000000000..68975a9777f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h @@ -0,0 +1,1021 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PIO_H_ +#define _HARDWARE_PIO_H_ + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/structs/pio.h" +#include "hardware/gpio.h" +#include "hardware/regs/dreq.h" +#include "hardware/pio_instructions.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO, Enable/disable assertions in the PIO module, type=bool, default=0, group=hardware_pio +#ifndef PARAM_ASSERTIONS_ENABLED_PIO +#define PARAM_ASSERTIONS_ENABLED_PIO 0 +#endif + +/** \file hardware/pio.h + * \defgroup hardware_pio hardware_pio + * + * Programmable I/O (PIO) API + * + * A programmable input/output block (PIO) is a versatile hardware interface which + * can support a number of different IO standards. There are two PIO blocks in the RP2040 + * + * Each PIO is programmable in the same sense as a processor: the four state machines independently + * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general + * purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism, + * precise timing, and close integration with fixed-function hardware. Each state machine is equipped + * with: + * * Two 32-bit shift registers – either direction, any shift count + * * Two 32-bit scratch registers + * * 4×32 bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction + * * Fractional clock divider (16 integer, 8 fractional bits) + * * Flexible GPIO mapping + * * DMA interface, sustained throughput up to 1 word per clock from system DMA + * * IRQ flag set/clear/status + * + * Full details of the PIO can be found in the RP2040 datasheet. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, ""); + +/** \brief FIFO join states + * \ingroup hardware_pio + */ +enum pio_fifo_join { + PIO_FIFO_JOIN_NONE = 0, + PIO_FIFO_JOIN_TX = 1, + PIO_FIFO_JOIN_RX = 2, +}; + +enum pio_mov_status_type { + STATUS_TX_LESSTHAN = 0, + STATUS_RX_LESSTHAN = 1 +}; + +typedef pio_hw_t *PIO; + +/** Identifier for the first (PIO 0) hardware PIO instance (for use in PIO functions). + * + * e.g. pio_gpio_init(pio0, 5) + * + * \ingroup hardware_pio + * @{ + */ +#define pio0 pio0_hw +/** @} */ + +/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions). + * + * e.g. pio_gpio_init(pio1, 5) + * + * \ingroup hardware_pio + * @{ + */ +#define pio1 pio1_hw +/** @} */ + +/** \brief PIO state machine configuration + * \defgroup sm_config sm_config + * \ingroup hardware_pio + * + * A PIO block needs to be configured, these functions provide helpers to set up configuration + * structures. See \ref pio_sm_set_config + * + */ + +/** \brief PIO Configuration structure + * \ingroup sm_config + */ +typedef struct { + uint32_t clkdiv; + uint32_t execctrl; + uint32_t shiftctrl; + uint32_t pinctrl; +} pio_sm_config; + +static inline void check_sm_param(uint sm) { + valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES); +} + +/*! \brief Set the 'out' pins in a state machine configuration + * \ingroup sm_config + * + * Can overlap with the 'in', 'set' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param out_base 0-31 First pin to set as output + * \param out_count 0-32 Number of pins to set. + */ +static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) { + assert(out_base < 32); + assert(out_count <= 32); + c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | + (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | + (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); +} + +/*! \brief Set the 'set' pins in a state machine configuration + * \ingroup sm_config + * + * Can overlap with the 'in', 'out' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param set_base 0-31 First pin to set as + * \param set_count 0-5 Number of pins to set. + */ +static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) { + assert(set_base < 32); + assert(set_count <= 5); + c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | + (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | + (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); +} + +/*! \brief Set the 'in' pins in a state machine configuration + * \ingroup sm_config + * + * Can overlap with the 'out', ''set' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param in_base 0-31 First pin to set as input + */ +static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { + assert(in_base < 32); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | + (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); +} + +/*! \brief Set the 'sideset' pins in a state machine configuration + * \ingroup sm_config + * + * Can overlap with the 'in', 'out' and 'set' pins + * + * \param c Pointer to the configuration structure to modify + * \param sideset_base base pin for 'side set' + */ +static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) { + assert(sideset_base < 32); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | + (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); +} + +/*! \brief Set the 'sideset' options in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param bit_count Number of bits to steal from delay field in the instruction for use of side set + * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction + * \param pindirs True if the side set affects pin directions rather than values + */ +static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) { + assert(bit_count <= 32); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | + (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); + + c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | + (!!optional << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | + (!!pindirs << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); +} + +/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration + * \ingroup sm_config + * + * The clock divider acts on the system clock to provide a clock for the state machine. + * See the datasheet for more details. + * + * \param c Pointer to the configuration structure to modify + * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n + * will cause the state machine to run 1 cycle in every n. + * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable + * although it will depend on the use case. + */ +static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { + uint16_t div_int = (uint16_t) div; + uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); + c->clkdiv = + (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | + (div_int << PIO_SM0_CLKDIV_INT_LSB); +} + +/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration + * \ingroup sm_config + * + * The clock divider acts on the system clock to provide a clock for the state machine. + * See the datasheet for more details. + * + * \param c Pointer to the configuration structure to modify + * \param div_int Integer part of the divisor + * \param div_frac Fractional part in 1/256ths + * \sa sm_config_set_clkdiv + */ +static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { + c->clkdiv = + (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | + (div_int << PIO_SM0_CLKDIV_INT_LSB); +} + +/*! \brief Set the wrap addresses in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param wrap_target the instruction memory address to wrap to + * \param wrap the instruction memory address after which to set the program counter to wrap_target + * if the instruction does not itself update the program_counter + */ +static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) { + assert(wrap < PIO_INSTRUCTION_COUNT); + assert(wrap_target < PIO_INSTRUCTION_COUNT); + c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | + (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | + (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); +} + +/*! \brief Set the 'jmp' pin in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction + */ +static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { + assert(pin < 32); + c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) | + (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); +} + +/*! \brief Setup 'in' shifting parameters in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param shift_right true to shift ISR to right, false to shift ISR to left + * \param autopush whether autopush is enabled + * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR + */ +static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) { + valid_params_if(PIO, push_threshold <= 32); + c->shiftctrl = (c->shiftctrl & + ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | + PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | + PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | + (!!shift_right << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | + (!!autopush << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | + ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); +} + +/*! \brief Setup 'out' shifting parameters in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param shift_right true to shift OSR to right, false to shift OSR to left + * \param autopull whether autopull is enabled + * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR + */ +static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) { + valid_params_if(PIO, pull_threshold <= 32); + c->shiftctrl = (c->shiftctrl & + ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | + PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | + PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | + (!!shift_right << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | + (!!autopull << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | + ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); +} + +/*! \brief Setup the FIFO joining in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param join Specifies the join type. \see enum pio_fifo_join + */ +static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) { + assert(join >= 0 && join <= 2); + c->shiftctrl = (c->shiftctrl & ~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | + (join << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); +} + +/*! \brief Set special 'out' operations in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles) + * \param has_enable_pin true to enable auxiliary OUT enable pin + * \param enable_pin_index pin index for auxiliary OUT enable + */ +static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, int enable_pin_index) { + c->execctrl = (c->execctrl & + ~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | + PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | + (!!sticky << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | + (!!has_enable_pin << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | + ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); +} + +/*! \brief Set source for 'mov status' in a state machine configuration + * \ingroup sm_config + * + * \param c Pointer to the configuration structure to modify + * \param status_sel the status operation selector + * \param status_n parameter for the mov status operation (currently a bit count) + */ +static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) { + c->execctrl = (c->execctrl + & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) + | ((status_sel << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) + | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS); +} + + +/*! \brief Get the default state machine configuration + * \ingroup sm_config + * + * Setting | Default + * --------|-------- + * Out Pins | 32 starting at 0 + * Set Pins | 0 starting at 0 + * In Pins (base) | 0 + * Side Set Pins (base) | 0 + * Side Set | disabled + * Wrap | wrap=31, wrap_to=0 + * In Shift | shift_direction=right, autopush=false, push_thrshold=32 + * Out Shift | shift_direction=right, autopull=false, pull_thrshold=32 + * Jmp Pin | 0 + * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 + * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0 + * + * \return the default state machine configuration which can then be modified. + */ +static inline pio_sm_config pio_get_default_sm_config() { + pio_sm_config c = {0, 0, 0}; + sm_config_set_clkdiv_int_frac(&c, 1, 0); + sm_config_set_wrap(&c, 0, 31); + sm_config_set_in_shift(&c, true, false, 32); + sm_config_set_out_shift(&c, true, false, 32); + return c; +} + +/*! \brief Apply a state machine configuration to a state machine + * \ingroup hardware_pio + * + * \param pio Handle to PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param config the configuration to apply +*/ +static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { + check_sm_param(sm); + pio->sm[sm].clkdiv = config->clkdiv; + pio->sm[sm].execctrl = config->execctrl; + pio->sm[sm].shiftctrl = config->shiftctrl; + pio->sm[sm].pinctrl = config->pinctrl; +} + +/*! \brief Return the instance number of a PIO instance + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \return the PIO instance number (either 0 or 1) + */ +static inline uint pio_get_index(PIO pio) { + assert(pio == pio0 || pio == pio1); + return pio == pio1 ? 1 : 0; +} + +/*! \brief Setup the function select for a GPIO to use output from the given PIO instance + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pin the GPIO pin whose function select to set + */ +static inline void pio_gpio_init(PIO pio, uint pin) { + assert(pio == pio0 || pio == pio1); + gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1); +} + +/*! \brief Return the DREQ to use for pacing transfers to a particular state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param is_tx true for sending data to the state machine, false for received data from the state machine + */ +static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) { + assert(pio == pio0 || pio == pio1); + check_sm_param(sm); + return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0); +} + +typedef struct pio_program { + const uint16_t *instructions; + uint8_t length; + int8_t origin; // required instruction memory origin or -1 +} __packed pio_program_t; + +/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param program the program definition + * \return true if the program can be loaded; false if there is not suitable space in the instruction memory + */ +bool pio_can_add_program(PIO pio, const pio_program_t *program); + +/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param program the program definition + * \param offset the instruction memory offset wanted for the start of the program + * \return true if the program can be loaded at that location; false if there is not space in the instruction memory + */ +bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); + +/*! \brief Attempt to load the program, panicking if not possible + * \ingroup hardware_pio + * + * \see pico_can_add_program if you need to check whether the program can be loaded + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param program the program definition + * \return the instruction memory offset the program is loaded at + */ +uint pio_add_program(PIO pio, const pio_program_t *program); + +/*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible + * \ingroup hardware_pio + * + * \see pico_can_add_program_at_offset if you need to check whether the program can be loaded + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param program the program definition + * \param offset the instruction memory offset wanted for the start of the program + */ +void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); + +/*! \brief Remove a program from a PIO instance's instruction memory + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param program the program definition + * \param loaded_offset the loaded offset returned when the program was added + */ +void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset); + +/*! \brief Clears all of a PIO instance's instruction memory + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + */ +void pio_clear_instruction_memory(PIO pio); + +/*! \brief Resets the state machine to a consistent state, and configures it + * \ingroup hardware_pio + * + * This method: + * - disables the state machine (if running) + * - clears the FIFOs + * - applies the configuration + * - resets any internal state + * - jumps to the initial program location + * + * The state machine is disabled on return from this call + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param initial_pc the initial program memory offset to run from + * \param config the configuration to apply (or NULL to apply defaults) + */ +void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config); + +/*! \brief Enable or disable a PIO state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param enabled true to enable the state machine; false to disable + */ +static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { + pio->ctrl = (pio->ctrl & ~(1u << sm)) | (!!enabled << sm); +} + +/*! \brief Enable or disable multiple PIO state machines + * \ingroup hardware_pio + * + * Note that this method just sets the enabled state of the state machine; + * if now enabled they continue exactly from where they left off. + * + * \see pio_enable_sm_mask_in_sync if you wish to enable multiple state machines + * and ensure their clock dividers are in sync. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param mask bit mask of state machine indexes to modify the enabled state of + * \param enabled true to enable the state machines; false to disable + */ +static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) { + pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); +} + +/*! \brief Restart a state machine with a known state + * \ingroup hardware_pio + * + * This method clears the ISR, shift counters, clock divider counter + * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +static inline void pio_sm_restart(PIO pio, uint sm) { + pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm); +} + +/*! \brief Restart multiple state machine with a known state + * \ingroup hardware_pio + * + * This method clears the ISR, shift counters, clock divider counter + * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param mask bit mask of state machine indexes to modify the enabled state of + */ +static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { + pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS; +} + +/*! \brief Restart a state machine's clock divider (resetting the fractional count) + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { + pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm); +} + +/*! \brief Restart multiple state machines' clock dividers (resetting the fractional count) + * \ingroup hardware_pio + * + * This method can be used to guarantee that multiple state machines with fractional clock dividers + * are exactly in sync + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param mask bit mask of state machine indexes to modify the enabled state of + */ +static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { + pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS; +} + +/*! \brief Enable multiple PIO state machines synchronizing their clock dividers + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param mask bit mask of state machine indexes to modify the enabled state of + */ +static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { + pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | + ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS); +} + +/*! \brief Return the current program counter for a state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return the program counter + */ +static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { + check_sm_param(sm); + return (uint8_t) pio->sm[sm].addr; +} + +/*! \brief Immediately execute an instruction on a state machine + * \ingroup hardware_pio + * + * This instruction is executed instead of the next instruction in the normal control flow on the state machine. + * Subsequent calls to this method replace the previous executed + * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * is still running (i.e. it is stalled on some condition) + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param instr the encoded PIO instruction + */ +inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { + check_sm_param(sm); + pio->sm[sm].instr = instr; +} + +/*! \brief Determine if an instruction set by pio_sm_exec() is stalled executing + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if the executed instruction is still running (stalled) + */ +static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { + check_sm_param(sm); + return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS); +} + +/*! \brief Immediately execute an instruction on a state machine and wait for it to complete + * \ingroup hardware_pio + * + * This instruction is executed instead of the next instruction in the normal control flow on the state machine. + * Subsequent calls to this method replace the previous executed + * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * is still running (i.e. it is stalled on some condition) + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param instr the encoded PIO instruction + */ +static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { + pio_sm_exec(pio, sm, instr); + while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents(); +} + +/*! \brief Set the current wrap configuration for a state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param wrap_target the instruction memory address to wrap to + * \param wrap the instruction memory address after which to set the program counter to wrap_target + * if the instruction does not itself update the program_counter + */ +static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) { + check_sm_param(sm); + pio->sm[sm].execctrl = + (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | + (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | + (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); +} + +/*! \brief Set the current 'out' pins for a state machine + * \ingroup sm_config + * + * Can overlap with the 'in', 'set' and 'sideset' pins + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param out_base 0-31 First pin to set as output + * \param out_count 0-32 Number of pins to set. + */ +static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) { + check_sm_param(sm); + assert(out_base < 32); + assert(out_count <= 32); + pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | + (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | + (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); +} + + +/*! \brief Set the current 'set' pins for a state machine + * \ingroup sm_config + * + * Can overlap with the 'in', 'out' and 'sideset' pins + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param set_base 0-31 First pin to set as + * \param set_count 0-5 Number of pins to set. + */ +static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) { + check_sm_param(sm); + assert(set_base < 32); + assert(set_count <= 5); + pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | + (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | + (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); +} + +/*! \brief Set the current 'in' pins for a state machine + * \ingroup sm_config + * + * Can overlap with the 'out', ''set' and 'sideset' pins + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param in_base 0-31 First pin to set as input + */ +static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { + check_sm_param(sm); + assert(in_base < 32); + pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | + (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); +} + +/*! \brief Set the current 'sideset' pins for a state machine + * \ingroup sm_config + * + * Can overlap with the 'in', 'out' and 'set' pins + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param sideset_base base pin for 'side set' + */ +static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) { + check_sm_param(sm); + assert(sideset_base < 32); + pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | + (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); +} + +/*! \brief Write a word of data to a state machine's TX FIFO + * \ingroup hardware_pio + * + * If the FIFO is full, the most recent value will be overwritten + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param data the 32 bit data value + */ +static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { + check_sm_param(sm); + pio->txf[sm] = data; +} + +/*! \brief Read a word of data from a state machine's RX FIFO + * \ingroup hardware_pio + * + * If the FIFO is empty, the return value is zero. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +static inline uint32_t pio_sm_get(PIO pio, uint sm) { + check_sm_param(sm); + return pio->rxf[sm]; +} + +/*! \brief Determine if a state machine's RX FIFO is full + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if the RX FIFO is full + */ +static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { + check_sm_param(sm); + return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0; +} + +/*! \brief Determine if a state machine's RX FIFO is empty + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if the RX FIFO is empty + */ +static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { + check_sm_param(sm); + return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0; +} + +/*! \brief Return the number of elements currently in a state machine's RX FIFO + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return the number of elements in the RX FIFO + */ +static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { + check_sm_param(sm); + int bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); + const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB; + return (pio->flevel >> bitoffs) & mask; +} + +/*! \brief Determine if a state machine's TX FIFO is full + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if the TX FIFO is full + */ +static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { + check_sm_param(sm); + return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0; +} + +/*! \brief Determine if a state machine's TX FIFO is empty + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if the TX FIFO is empty + */ +static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { + check_sm_param(sm); + return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0; +} + +/*! \brief Return the number of elements currently in a state machine's TX FIFO + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return the number of elements in the TX FIFO + */ +static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { + check_sm_param(sm); + unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB); + const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB; + return (pio->flevel >> bitoffs) & mask; +} + +/*! \brief Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param data the 32 bit data value + */ +static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { + check_sm_param(sm); + while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents(); + pio_sm_put(pio, sm, data); +} + +/*! \brief Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { + check_sm_param(sm); + while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents(); + return pio_sm_get(pio, sm); +} + +/*! \brief Empty out a state machine's TX FIFO + * \ingroup hardware_pio + * + * This method executes `pull` instructions on the state machine until the TX FIFO is empty + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +void pio_sm_drain_tx_fifo(PIO pio, uint sm); + +/*! \brief set the current clock divider for a state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param div the floating point clock divider + */ +static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { + check_sm_param(sm); + uint16_t div_int = (uint16_t) div; + uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); + pio->sm[sm].clkdiv = + (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | + (div_int << PIO_SM0_CLKDIV_INT_LSB); +} + +/*! \brief set the current clock divider for a state machine using a 16:8 fraction + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param div_int the integer part of the clock divider + * \param div_frac the fractional part of the clock divider in 1/256s + */ +static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { + check_sm_param(sm); + pio->sm[sm].clkdiv = + (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | + (div_int << PIO_SM0_CLKDIV_INT_LSB); +} + +/*! \brief Clear a state machine's TX and RX FIFOFs + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +static inline void pio_sm_clear_fifos(PIO pio, uint sm) { + // changing the FIFO join state clears the fifo + check_sm_param(sm); + hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); + hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); +} + +/*! \brief Use a state machine to set a value on all pins for the PIO instance + * \ingroup hardware_pio + * + * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on all 32 pins, + * before restoring the state machine's pin configuration to what it was. + * + * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) to use + * \param pin_values the pin values to set + */ +void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values); + +/*! \brief Use a state machine to set a value on multiple pins for the PIO instance + * \ingroup hardware_pio + * + * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on up to 32 pins, + * before restoring the state machine's pin configuration to what it was. + * + * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) to use + * \param pin_values the pin values to set (if the corresponding bit in pin_mask is set) + * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. + */ +void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask); + +/*! \brief Use a state machine to set the pin directions for multiple pins for the PIO instance + * \ingroup hardware_pio + * + * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set pin directions on up to 32 pins, + * before restoring the state machine's pin configuration to what it was. + * + * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) to use + * \param pin_dirs the pin directions to set - 1 = out, 0 = in (if the corresponding bit in pin_mask is set) + * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. + */ +void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask); + +/*! \brief Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance + * \ingroup hardware_pio + * + * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set the pin direction on consecutive pins, + * before restoring the state machine's pin configuration to what it was. + * + * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) to use + * \param pin_base the first pin to set a direction for + * \param pin_count the count of consecutive pins to set the direction for + * \param is_out the direction to set; true = out, false = in + */ +void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out); + +/*! \brief Mark a state machine as used + * \ingroup hardware_pio + * + * Method for cooperative claiming of hardware. Will cause a panic if the state machine + * is already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +void pio_sm_claim(PIO pio, uint sm); + +/*! \brief Mark multiple state machines as used + * \ingroup hardware_pio + * + * Method for cooperative claiming of hardware. Will cause a panic if any of the state machines + * are already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm_mask Mask of state machine indexes + */ +void pio_claim_sm_mask(PIO pio, uint sm_mask); + +/*! \brief Mark a state machine as no longer used + * \ingroup hardware_pio + * + * Method for cooperative claiming of hardware. + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + */ +void pio_sm_unclaim(PIO pio, uint sm); + +/*! \brief Claim a free state machine on a PIO instance + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param required if true the function will panic if none are available + * \return the state machine index or -1 if required was false, and none were free + */ +int pio_claim_unused_sm(PIO pio, bool required); + +#ifdef __cplusplus +} +#endif + +#endif // _PIO_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h new file mode 100644 index 00000000000..757411d5e2d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PIO_INSTRUCTIONS_H_ +#define _HARDWARE_PIO_INSTRUCTIONS_H_ + +#include "pico.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=hardware_pio +#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS +#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +enum pio_instr_bits { + pio_instr_bits_jmp = 0x0000, + pio_instr_bits_wait = 0x2000, + pio_instr_bits_in = 0x4000, + pio_instr_bits_out = 0x6000, + pio_instr_bits_push = 0x8000, + pio_instr_bits_pull = 0x8080, + pio_instr_bits_mov = 0xa000, + pio_instr_bits_irq = 0xc000, + pio_instr_bits_set = 0xe000, +}; + +#ifndef NDEBUG +#define _PIO_INVALID_IN_SRC 0x08u +#define _PIO_INVALID_OUT_DEST 0x10u +#define _PIO_INVALID_SET_DEST 0x20u +#define _PIO_INVALID_MOV_SRC 0x40u +#define _PIO_INVALID_MOV_DEST 0x80u +#else +#define _PIO_INVALID_IN_SRC 0u +#define _PIO_INVALID_OUT_DEST 0u +#define _PIO_INVALID_SET_DEST 0u +#define _PIO_INVALID_MOV_SRC 0u +#define _PIO_INVALID_MOV_DEST 0u +#endif + +enum pio_src_dest { + pio_pins = 0u, + pio_x = 1u, + pio_y = 2u, + pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, + pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, + pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, + pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_isr = 6u | _PIO_INVALID_SET_DEST, + pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST, + pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, +}; + +inline static uint _pio_major_instr_bits(uint instr) { + return instr & 0xe000u; +} + +inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { + valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7); +#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS) + uint32_t major = _pio_major_instr_bits(instr_bits); + if (major == pio_instr_bits_in || major == pio_instr_bits_out) { + assert(arg2 && arg2 <= 32); + } else { + assert(arg2 <= 31); + } +#endif + return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); +} + +inline static uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { + return _pio_encode_instr_and_args(instr_bits, dest & 7u, value); +} + +inline static uint pio_encode_delay(uint cycles) { + valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f); + return cycles << 8u; +} + +inline static uint pio_encode_sideset(uint sideset_bit_count, uint value) { + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5); + valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); + return value << (13u - sideset_bit_count); +} + +inline static uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 2 && sideset_bit_count <= 5); + valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); + return 0x1000u | value << (12u - sideset_bit_count); +} + +inline static uint pio_encode_jmp(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr); +} + +inline static uint _pio_encode_irq(bool relative, uint irq) { + valid_params_if(PIO_INSTRUCTIONS, irq <= 7); + return (relative ? 0x10u : 0x0u) | irq; +} + +inline static uint pio_encode_wait_gpio(bool polarity, uint pin) { + return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), pin); +} + +inline static uint pio_encode_wait_pin(bool polarity, uint pin) { + return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin); +} + +inline static uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { + valid_params_if(PIO_INSTRUCTIONS, irq <= 7); + return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq)); +} + +inline static uint pio_encode_in(enum pio_src_dest src, uint value) { + valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, value); +} + +inline static uint pio_encode_out(enum pio_src_dest dest, uint value) { + valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, value); +} + +inline static uint pio_encode_push(bool if_full, bool block) { + return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); +} + +inline static uint pio_encode_pull(bool if_empty, bool block) { + return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); +} + +inline static uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { + valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); + valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u); +} + +inline static uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { + valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); + valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u)); +} + +inline static uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { + valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); + valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u)); +} + +inline static uint pio_encode_irq_set(bool relative, uint irq) { + return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq)); +} + +inline static uint pio_encode_irq_clear(bool relative, uint irq) { + return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq)); +} + +inline static uint pio_encode_set(enum pio_src_dest dest, uint value) { + valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value); +} + +inline static uint pio_encode_nop() { + return pio_encode_mov(pio_y, pio_y); +} + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c new file mode 100644 index 00000000000..8221225196b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/claim.h" +#include "hardware/pio.h" +#include "hardware/pio_instructions.h" + +// sanity check +check_hw_layout(pio_hw_t, sm[0].clkdiv, PIO_SM0_CLKDIV_OFFSET); +check_hw_layout(pio_hw_t, sm[1].clkdiv, PIO_SM1_CLKDIV_OFFSET); +check_hw_layout(pio_hw_t, instr_mem[0], PIO_INSTR_MEM0_OFFSET); +check_hw_layout(pio_hw_t, inte0, PIO_IRQ0_INTE_OFFSET); +check_hw_layout(pio_hw_t, txf[1], PIO_TXF1_OFFSET); +check_hw_layout(pio_hw_t, rxf[3], PIO_RXF3_OFFSET); +check_hw_layout(pio_hw_t, ints1, PIO_IRQ1_INTS_OFFSET); + +static_assert(NUM_PIO_STATE_MACHINES * NUM_PIOS <= 8, ""); +static uint8_t claimed; + +void pio_sm_claim(PIO pio, uint sm) { + check_sm_param(sm); + uint which = pio_get_index(pio); + if (which) { + hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM %d already claimed"); + } else { + hw_claim_or_assert(&claimed, sm, "PIO 0 SM %d already claimed"); + } +} + +void pio_claim_sm_mask(PIO pio, uint sm_mask) { + for(uint i = 0; sm_mask; i++, sm_mask >>= 1u) { + if (sm_mask & 1u) pio_sm_claim(pio, i); + } +} +void pio_sm_unclaim(PIO pio, uint sm) { + check_sm_param(sm); + uint which = pio_get_index(pio); + hw_claim_clear(&claimed, which * NUM_PIO_STATE_MACHINES + sm); +} + +int pio_claim_unused_sm(PIO pio, bool required) { + uint which = pio_get_index(pio); + uint base = which * NUM_PIO_STATE_MACHINES; + int index = hw_claim_unused_from_range((uint8_t*)&claimed, required, base, + base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available"); + return index >= base ? index - base : -1; +} + +void pio_load_program(PIO pio, const uint16_t *prog, uint8_t prog_len, uint8_t load_offset) { + // instructions are only 16 bits, but instruction memory locations are spaced 32 bits apart + // Adjust the addresses of any jump instructions to respect load offset + assert(load_offset + prog_len <= PIO_INSTRUCTION_COUNT); + +} + +static_assert(PIO_INSTRUCTION_COUNT <= 32, ""); +static uint32_t _used_instruction_space[2]; + +static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) { + assert(program->length < PIO_INSTRUCTION_COUNT); + uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; + uint32_t program_mask = (1u << program->length) - 1; + if (program->origin >= 0) { + if (program->origin > 32 - program->length) return -1; + return used_mask & (program_mask << program->origin) ? -1 : program->origin; + } else { + // work down from the top always + for (int i = 32 - program->length; i >= 0; i--) { + if (!(used_mask & (program_mask << (uint) i))) { + return i; + } + } + return -1; + } +} + +bool pio_can_add_program(PIO pio, const pio_program_t *program) { + uint32_t save = hw_claim_lock(); + bool rc = -1 != _pio_find_offset_for_program(pio, program); + hw_claim_unlock(save); + return rc; +} + +static bool _pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { + assert(offset < PIO_INSTRUCTION_COUNT); + assert(offset + program->length <= PIO_INSTRUCTION_COUNT); + if (program->origin >= 0 && program->origin != offset) return false; + uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; + uint32_t program_mask = (1u << program->length) - 1; + return !(used_mask & (program_mask << offset)); +} + +bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { + uint32_t save = hw_claim_lock(); + bool rc = _pio_can_add_program_at_offset(pio, program, offset); + hw_claim_unlock(save); + return rc; +} + +static void _pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { + if (!_pio_can_add_program_at_offset(pio, program, offset)) { + panic("No program space"); + } + for (uint i = 0; i < program->length; ++i) { + uint16_t instr = program->instructions[i]; + pio->instr_mem[offset + i] = pio_instr_bits_jmp != _pio_major_instr_bits(instr) ? instr : instr + offset; + } + uint32_t program_mask = (1u << program->length) - 1; + _used_instruction_space[pio_get_index(pio)] |= program_mask << offset; +} + +// these assert if unable +uint pio_add_program(PIO pio, const pio_program_t *program) { + uint32_t save = hw_claim_lock(); + int offset = _pio_find_offset_for_program(pio, program); + if (offset < 0) { + panic("No program space"); + } + _pio_add_program_at_offset(pio, program, offset); + hw_claim_unlock(save); + return offset; +} + +void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { + uint32_t save = hw_claim_lock(); + _pio_add_program_at_offset(pio, program, offset); + hw_claim_unlock(save); +} + +void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) { + uint32_t program_mask = (1u << program->length) - 1; + program_mask <<= loaded_offset; + uint32_t save = hw_claim_lock(); + assert(program_mask == (_used_instruction_space[pio_get_index(pio)] & program_mask)); + _used_instruction_space[pio_get_index(pio)] &= ~program_mask; + hw_claim_unlock(save); +} + +void pio_clear_instruction_memory(PIO pio) { + uint32_t save = hw_claim_lock(); + _used_instruction_space[pio_get_index(pio)] = 0; + for(uint i=0;iinstr_mem[i] = pio_encode_jmp(i); + } + hw_claim_unlock(save); +} + +// Set the value of all PIO pins. This is done by forcibly executing +// instructions on a "victim" state machine, sm. Ideally you should choose one +// which is not currently running a program. This is intended for one-time +// setup of initial pin states. +void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) { + uint32_t pinctrl_saved = pio->sm[sm].pinctrl; + uint remaining = 32; + uint base = 0; + while (remaining) { + uint decrement = remaining > 5 ? 5 : remaining; + pio->sm[sm].pinctrl = + (decrement << PIO_SM0_PINCTRL_SET_COUNT_LSB) | + (base << PIO_SM0_PINCTRL_SET_BASE_LSB); + pio_sm_exec(pio, sm, pio_encode_set(pio_pins, pins & 0x1fu)); + remaining -= decrement; + base += decrement; + pins >>= 5; + } + pio->sm[sm].pinctrl = pinctrl_saved; +} + +void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_mask) { + uint32_t pinctrl_saved = pio->sm[sm].pinctrl; + while (pin_mask) { + uint base = __builtin_ctz(pin_mask); + pio->sm[sm].pinctrl = + (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | + (base << PIO_SM0_PINCTRL_SET_BASE_LSB); + pio_sm_exec(pio, sm, pio_encode_set(pio_pins, (pinvals >> base) & 0x1u)); + pin_mask &= pin_mask - 1; + } + pio->sm[sm].pinctrl = pinctrl_saved; +} + +void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t pin_mask) { + uint32_t pinctrl_saved = pio->sm[sm].pinctrl; + while (pin_mask) { + uint base = __builtin_ctz(pin_mask); + pio->sm[sm].pinctrl = + (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | + (base << PIO_SM0_PINCTRL_SET_BASE_LSB); + pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, (pindirs >> base) & 0x1u)); + pin_mask &= pin_mask - 1; + } + pio->sm[sm].pinctrl = pinctrl_saved; +} + +void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) { + assert(pin < 32u); + uint32_t pinctrl_saved = pio->sm[sm].pinctrl; + uint pindir_val = is_out ? 0x1f : 0; + while (count > 5) { + pio->sm[sm].pinctrl = (5u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB); + pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val)); + count -= 5; + pin = (pin + 5) & 0x1f; + } + pio->sm[sm].pinctrl = (count << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB); + pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val)); + pio->sm[sm].pinctrl = pinctrl_saved; +} + +void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) { + // Halt the machine, set some sensible defaults + pio_sm_set_enabled(pio, sm, false); + + if (config) { + pio_sm_set_config(pio, sm, config); + } else { + pio_sm_config c = pio_get_default_sm_config(); + pio_sm_set_config(pio, sm, &c); + } + + pio_sm_clear_fifos(pio, sm); + + // Clear FIFO debug flags + const uint32_t fdebug_sm_mask = + (1u << PIO_FDEBUG_TXOVER_LSB) | + (1u << PIO_FDEBUG_RXUNDER_LSB) | + (1u << PIO_FDEBUG_TXSTALL_LSB) | + (1u << PIO_FDEBUG_RXSTALL_LSB); + pio->fdebug = fdebug_sm_mask << sm; + + // Finally, clear some internal SM state + pio_sm_restart(pio, sm); + pio_sm_clkdiv_restart(pio, sm); + pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc)); +} + +void pio_sm_drain_tx_fifo(PIO pio, uint sm) { + uint instr = (pio->sm[sm].shiftctrl & PIO_SM0_SHIFTCTRL_AUTOPULL_BITS) ? pio_encode_out(pio_null, 32) : + pio_encode_pull(false, false); + while (!pio_sm_is_tx_fifo_empty(pio, sm)) { + pio_sm_exec(pio, sm, instr); + } +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/CMakeLists.txt new file mode 100644 index 00000000000..37ff759639a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(pll) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h new file mode 100644 index 00000000000..023e340339e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLL_H_ +#define _HARDWARE_PLL_H_ + +#include "pico.h" +#include "hardware/structs/pll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/pll.h + * \defgroup hardware_pll hardware_pll + * + * Phase Locked Loop control APIs + * + * There are two PLLs in RP2040. They are: + * - pll_sys - Used to generate up to a 133MHz system clock + * - pll_usb - Used to generate a 48MHz USB reference clock + * + * For details on how the PLL's are calculated, please refer to the RP2040 datasheet. + */ + +typedef pll_hw_t *PLL; + +#define pll_sys pll_sys_hw +#define pll_usb pll_usb_hw + +/*! \brief Initialise specified PLL. + * \ingroup hardware_pll + * \param pll pll_sys or pll_usb + * \param ref_div Input clock divider. + * \param vco_freq Requested output from the VCO (voltage controlled oscillator) + * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2 + * \param post_div2 Post Divider 2 - range 1-7 + */ +void pll_init(PLL pll, uint32_t ref_div, uint32_t vco_freq, uint32_t post_div1, uint8_t post_div2); + +/*! \brief Release/uninitialise specified PLL. + * \ingroup hardware_pll + * + * This will turn off the power to the specified PLL. Note this function does not currently check if + * the PLL is in use before powering it off so should be used with care. + * + * \param pll pll_sys or pll_usb + */ +void pll_deinit(PLL pll); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c new file mode 100644 index 00000000000..a55ed5ca88f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// For MHZ definitions etc +#include "hardware/clocks.h" +#include "hardware/pll.h" + +/// \tag::pll_init_calculations[] +void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, uint8_t post_div2) { + // Turn off PLL in case it is already running + pll->pwr = 0xffffffff; + pll->fbdiv_int = 0; + + uint32_t ref_mhz = XOSC_MHZ / refdiv; + pll->cs = refdiv; + + // What are we multiplying the reference clock by to get the vco freq + // (The regs are called div, because you divide the vco output and compare it to the refclk) + uint32_t fbdiv = vco_freq / (ref_mhz * MHZ); +/// \end::pll_init_calculations[] + + // fbdiv + assert(fbdiv >= 16 && fbdiv <= 320); + + // Check divider ranges + assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7)); + + // post_div1 should be >= post_div2 + // from appnote page 11 + // postdiv1 is designed to operate with a higher input frequency + // than postdiv2 + assert(post_div2 <= post_div1); + +/// \tag::pll_init_finish[] + // Check that reference frequency is no greater than vco / 16 + assert(ref_mhz <= (vco_freq / 16)); + + // Put calculated value into feedback divider + pll->fbdiv_int = fbdiv; + + // Turn on PLL + uint32_t power = PLL_PWR_PD_BITS | // Main power + PLL_PWR_VCOPD_BITS; // VCO Power + + hw_clear_bits(&pll->pwr, power); + + // Wait for PLL to lock + while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents(); + + // Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 + uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | + (post_div2 << PLL_PRIM_POSTDIV2_LSB); + pll->prim = pdiv; + + // Turn on post divider + hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS); +/// \end::pll_init_finish[] +} + +void pll_deinit(PLL pll) { + // todo: Make sure there are no sources running from this pll? + pll->pwr = PLL_PWR_BITS; +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/CMakeLists.txt new file mode 100644 index 00000000000..c8d34014c95 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_headers_only_target(pwm) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h new file mode 100644 index 00000000000..4b572f7711d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PWM_H +#define _HARDWARE_PWM_H + +#include "pico.h" +#include "hardware/structs/pwm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hadrware_pwm +#ifndef PARAM_ASSERTIONS_ENABLED_PWM +#define PARAM_ASSERTIONS_ENABLED_PWM 0 +#endif + +/** \file hardware/pwm.h + * \defgroup hardware_pwm hardware_pwm + * + * Hardware Pulse Width Modulation (PWM) API + * + * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or + * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable + * PWM outputs. All 30 GPIOs can be driven by the PWM block + * + * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a + * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of + * time spent at the high signal level is known as the duty cycle of the signal. + * + * The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then + * immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after + * reaching TOP, until it reaches 0 again. + * + * \subsection pwm_example Example + * \addtogroup hardware_pwm + * \include hello_pwm.c + */ + +/** \brief PWM Divider mode settings + * \ingroup hardware_pwm + * + */ +enum pwm_clkdiv_mode +{ + PWM_DIV_FREE_RUNNING, ///< Free-running counting at rate dictated by fractional divider + PWM_DIV_B_HIGH, ///< Fractional divider is gated by the PWM B pin + PWM_DIV_B_RISING, ///< Fractional divider advances with each rising edge of the PWM B pin + PWM_DIV_B_FALLING ///< Fractional divider advances with each falling edge of the PWM B pin +}; + +enum pwm_chan +{ + PWM_CHAN_A = 0, + PWM_CHAN_B = 1 +}; + +typedef struct { + uint32_t csr; + uint32_t div; + uint32_t top; +} pwm_config; + +/** \brief Determine the PWM slice that is attached to the specified GPIO + * \ingroup hardware_pwm + * + * \return The PWM slice number that controls the specified GPIO. + */ +static inline uint pwm_gpio_to_slice_num(uint gpio) { + valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); + return (gpio >> 1u) & 7u; +} + +/** \brief Determine the PWM channel that is attached to the specified GPIO. + * \ingroup hardware_pwm + * + * Each slice 0 to 7 has two channels, A and B. + * + * \return The PWM channel that controls the specified GPIO. + */ +static inline uint pwm_gpio_to_channel(uint gpio) { + valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); + return gpio & 1u; +} + +/** \brief Set phase correction in a PWM configuration + * \ingroup hardware_pwm + * + * \param c PWM configuration struct to modify + * \param phase_correct true to set phase correct modulation, false to set trailing edge + * + * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached, + * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. + */ +static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) { + c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS) + | (!!phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB); +} + +/** \brief Set clock divider in a PWM configuration + * \ingroup hardware_pwm + * + * \param c PWM configuration struct to modify + * \param div Value to divide counting rate by. Must be greater than or equal to 1. + * + * If the divide mode is free-running, the PWM counter runs at clk_sys / div. + * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) + * before passing them on to the PWM counter. + */ +static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { + c->div = (uint32_t)(div * (float)(1u << PWM_CH1_DIV_INT_LSB)); +} + +/** \brief Set PWM clock divider in a PWM configuration + * \ingroup hardware_pwm + * + * \param c PWM configuration struct to modify + * \param div integer value to reduce counting rate by. Must be greater than or equal to 1. + * + * If the divide mode is free-running, the PWM counter runs at clk_sys / div. + * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) + * before passing them on to the PWM counter. + */ +static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { + c->div = div << PWM_CH1_DIV_INT_LSB; +} + +/** \brief Set PWM counting mode in a PWM configuration + * \ingroup hardware_pwm + * + * \param c PWM configuration struct to modify + * \param mode PWM divide/count mode + * + * Configure which event gates the operation of the fractional divider. + * The default is always-on (free-running PWM). Can also be configured to count on + * high level, rising edge or falling edge of the B pin input. + */ +static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) { + valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); + c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS) + | (mode << PWM_CH0_CSR_DIVMODE_LSB); +} + +/** \brief Set output polarity in a PWM configuration + * \ingroup hardware_pwm + * + * \param c PWM configuration struct to modify + * \param a true to invert output A + * \param b true to invert output B + */ +static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) { + c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS)) + | ((!!a << PWM_CH0_CSR_A_INV_LSB) | (!!b << PWM_CH0_CSR_B_INV_LSB)); +} + +/** \brief Set PWM counter wrap value in a PWM configuration + * \ingroup hardware_pwm + * + * Set the highest value the counter will reach before returning to 0. Also known as TOP. + * + * \param c PWM configuration struct to modify + * \param wrap Value to set wrap to + */ +static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { + c->top = wrap; +} + +/** \brief Initialise a PWM with settings from a configuration object + * \ingroup hardware_pwm + * + * Use the \ref pwm_get_default_config() function to initialise a config structure, make changes as + * needed using the pwm_config_* functions, then call this function to set up the PWM. + * + * \param slice_num PWM slice number + * \param c The configuration to use + * \param start If true the PWM will be started running once configured. If false you will need to start + * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled() + */ +static inline void pwm_init(uint slice_num, pwm_config *c, bool start) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + pwm_hw->slice[slice_num].csr = 0; + + pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET; + pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET; + pwm_hw->slice[slice_num].top = c->top; + pwm_hw->slice[slice_num].div = c->div; + pwm_hw->slice[slice_num].csr = c->csr | (!!start << PWM_CH0_CSR_EN_LSB); +} + +/** \brief Get a set of default values for PWM configuration + * \ingroup hardware_pwm + * + * PWM config is free running at system clock speed, no phase correction, wrapping at 0xffff, + * with standard polarities for channels A and B. + * + * \return Set of default values. + */ +static inline pwm_config pwm_get_default_config() { + pwm_config c = {0, 0, 0}; + pwm_config_set_phase_correct(&c, false); + pwm_config_set_clkdiv_int(&c, 1); + pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING); + pwm_config_set_output_polarity(&c, false, false); + pwm_config_set_wrap(&c, 0xffffu); + return c; +} + +/** \brief Set the current PWM counter wrap value + * \ingroup hardware_pwm + * + * Set the highest value the counter will reach before returning to 0. Also known as TOP. + * + * \param slice_num PWM slice number + * \param wrap Value to set wrap to + */ +static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + pwm_hw->slice[slice_num].top = wrap; +} + +/** \brief Set the current PWM counter compare value for one channel + * \ingroup hardware_pwm + * + * Set the value of the PWM counter compare value, for either channel A or channel B + * + * \param slice_num PWM slice number + * \param chan Which channel to update. 0 for A, 1 for B. + * \param level new level for the selected output + */ +static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_write_masked( + &pwm_hw->slice[slice_num].cc, + level << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), + chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS + ); +} + +/** \brief Set PWM counter compare values + * \ingroup hardware_pwm + * + * Set the value of the PWM counter compare values, A and B + * + * \param slice_num PWM slice number + * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted + * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted + */ +static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + pwm_hw->slice[slice_num].cc = (level_b << PWM_CH0_CC_B_LSB) | (level_a << PWM_CH0_CC_A_LSB); +} + +/** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO. + * \ingroup hardware_pwm + * + * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding + * counter-compare field. + * + * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs + * mapping to the same slice and channel (if GPIOs have a difference of 16). + * + * \param gpio GPIO to set level of + * \param level PWM level for this GPIO + */ +static inline void pwm_set_gpio_level(uint gpio, uint16_t level) { + valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); + pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level); +} + +/** \brief Get PWM counter + * \ingroup hardware_pwm + * + * Get current value of PWM counter + * + * \param slice_num PWM slice number + * \return Current value of PWM counter + */ +static inline int16_t pwm_get_counter(uint slice_num) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + return (pwm_hw->slice[slice_num].ctr); +} + +/** \brief Set PWM counter + * \ingroup hardware_pwm + * + * Set the value of the PWM counter + * + * \param slice_num PWM slice number + * \param c Value to set the PWM counter to + * + */ +static inline void pwm_set_counter(uint slice_num, uint16_t c) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + pwm_hw->slice[slice_num].ctr = c; +} + +/** \brief Advance PWM count + * \ingroup hardware_pwm + * + * Advance the phase of a running the counter by 1 count. + * + * This function will return once the increment is complete. + * + * \param slice_num PWM slice number + */ +static inline void pwm_advance_count(uint slice_num) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); + while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) { + tight_loop_contents(); + } +} + +/** \brief Retard PWM count + * \ingroup hardware_pwm + * + * Retard the phase of a running counter by 1 count + * + * This function will return once the retardation is complete. + * + * \param slice_num PWM slice number + */ +static inline void pwm_retard_count(uint slice_num) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); + while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) { + tight_loop_contents(); + } +} + +/** \brief Set PWM clock divider using an 8:4 fractional value + * \ingroup hardware_pwm + * + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * + * \param slice_num PWM slice number + * \param integer 8 bit integer part of the clock divider + * \param fract 4 bit fractional part of the clock divider + */ +static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + valid_params_if(PWM, fract >= 0 && slice_num <= 16); + pwm_hw->slice[slice_num].div = (integer << PWM_CH0_DIV_INT_LSB) | (fract << PWM_CH0_DIV_FRAC_LSB); +} + +/** \brief Set PWM clock divider + * \ingroup hardware_pwm + * + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * + * \param slice_num PWM slice number + * \param divider Floating point clock divider, 1.f <= value < 256.f + */ +static inline void pwm_set_clkdiv(uint slice_num, float divider) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + valid_params_if(PWM, divider >= 1.f && divider < 256.f); + uint8_t i = (uint8_t)divider; + uint8_t f = (uint8_t)((divider - i) * (0x01 << 4)); + pwm_set_clkdiv_int_frac(slice_num, i, f); +} + +/** \brief Set PWM output polarity + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + * \param a true to invert output A + * \param b true to invert output B + */ +static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_write_masked(&pwm_hw->slice[slice_num].csr, !!a << PWM_CH0_CSR_A_INV_LSB | !!b << PWM_CH0_CSR_B_INV_LSB, + PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS); +} + + +/** \brief Set PWM divider mode + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + * \param mode Required divider mode + */ +static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); + hw_write_masked(&pwm_hw->slice[slice_num].csr, mode << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); +} + +/** \brief Set PWM phase correct on/off + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + * \param phase_correct true to set phase correct modulation, false to set trailing edge + * + * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached, + * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. + */ +static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_write_masked(&pwm_hw->slice[slice_num].csr, phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); +} + +/** \brief Enable/Disable PWM + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + * \param enabled true to enable the specified PWM, false to disable + */ +static inline void pwm_set_enabled(uint slice_num, bool enabled) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + hw_write_masked(&pwm_hw->slice[slice_num].csr, !!enabled << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); +} + +/** \brief Enable/Disable multiple PWM slices simultaneously + * \ingroup hardware_pwm + * + * \param mask Bitmap of PWMs to enable/disable. Bits 0 to 7 enable slices 0-7 respectively + */ +static inline void pwm_set_mask_enabled(uint32_t mask) { + pwm_hw->en = mask; +} + +/*! \brief Enable PWM instance interrupt + * \ingroup hardware_pwm + * + * Used to enable a single PWM instance interrupt + * + * \param slice_num PWM block to enable/disable + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) { + valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + if (enabled) { + hw_set_bits(&pwm_hw->inte, 1u << slice_num); + } else { + hw_clear_bits(&pwm_hw->inte, 1u << slice_num); + } +} + +/*! \brief Enable multiple PWM instance interrupts + * \ingroup hardware_pwm + * + * Use this to enable multiple PWM interrupts at once. + * + * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) { + valid_params_if(PWM, slice_mask < 256); + if (enabled) { + hw_set_bits(&pwm_hw->inte, slice_mask); + } else { + hw_clear_bits(&pwm_hw->inte, slice_mask); + } +} + +/*! \brief Clear single PWM channel interrupt + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline void pwm_clear_irq(uint slice_num) { + pwm_hw->intr = 1u << slice_num; +} + +/*! \brief Get PWM interrupt status, raw + * \ingroup hardware_pwm + * + * \return Bitmask of all PWM interrupts currently set + */ +static inline int32_t pwm_get_irq_status_mask() { + return pwm_hw->ints; +} + +/*! \brief Force PWM interrupt + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline void pwm_force_irq(uint slice_num) { + pwm_hw->intf = 1u << slice_num; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt new file mode 100644 index 00000000000..0b314573e60 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(hardware_resets INTERFACE) +target_include_directories(hardware_resets INTERFACE include) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h new file mode 100644 index 00000000000..fab604bdaeb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_RESETS_H +#define _HARDWARE_RESETS_H + +#include "pico.h" +#include "hardware/structs/resets.h" + +/** \file hardware/resets.h + * \defgroup hardware_resets hardware_resets + * + * Hardware Reset API + * + * The reset controller allows software control of the resets to all of the peripherals that are not + * critical to boot the processor in the RP2040. + * + * \subsubsection reset_bitmask + * \addtogroup hardware_resets + * + * Multiple blocks are referred to using a bitmask as follows: + * + * Block to reset | Bit + * ---------------|---- + * USB | 24 + * UART 1 | 23 + * UART 0 | 22 + * Timer | 21 + * TB Manager | 20 + * SysInfo | 19 + * System Config | 18 + * SPI 1 | 17 + * SPI 0 | 16 + * RTC | 15 + * PWM | 14 + * PLL USB | 13 + * PLL System | 12 + * PIO 1 | 11 + * PIO 0 | 10 + * Pads - QSPI | 9 + * Pads - bank 0 | 8 + * JTAG | 7 + * IO Bank 1 | 6 + * IO Bank 0 | 5 + * I2C 1 | 4 + * I2C 0 | 3 + * DMA | 2 + * Bus Control | 1 + * ADC 0 | 0 + * + * \subsection reset_example Example + * \addtogroup hardware_resets + * \include hello_reset.c + */ + +/// \tag::reset_funcs[] + +/*! \brief Reset the specified HW blocks + * \ingroup hardware_resets + * + * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask + */ +static inline void reset_block(uint32_t bits) { + hw_set_bits(&resets_hw->reset, bits); +} + +/*! \brief bring specified HW blocks out of reset + * \ingroup hardware_resets + * + * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask + */ +static inline void unreset_block(uint32_t bits) { + hw_clear_bits(&resets_hw->reset, bits); +} + +/*! \brief Bring specified HW blocks out of reset and wait for completion + * \ingroup hardware_resets + * + * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask + */ +static inline void unreset_block_wait(uint32_t bits) { + hw_clear_bits(&resets_hw->reset, bits); + while (~resets_hw->reset_done & bits) + tight_loop_contents(); +} +/// \end::reset_funcs[] + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/CMakeLists.txt new file mode 100644 index 00000000000..dce6effb6d2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(rtc) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h new file mode 100644 index 00000000000..83d5bdf288c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_RTC_H +#define _HARDWARE_RTC_H + +#include "pico.h" +#include "hardware/structs/rtc.h" + +/** \file hardware/rtc.h + * \defgroup hardware_rtc hardware_rtc + * + * Hardware Real Time Clock API + * + * The RTC keeps track of time in human readable format and generates events when the time is equal + * to a preset value. Think of a digital clock, not epoch time used by most computers. There are seven + * fields, one each for year (12 bit), month (4 bit), day (5 bit), day of the week (3 bit), hour (5 bit) + * minute (6 bit) and second (6 bit), storing the data in binary format. + * + * \sa datetime_t + * + * \subsection rtc_example Example + * \addtogroup hardware_rtc + * + * \include hello_rtc.c + */ + + +typedef void (*rtc_callback_t)(void); + +/*! \brief Initialise the RTC system + * \ingroup hardware_rtc + */ +void rtc_init(void); + +/*! \brief Set the RTC to the specified time + * \ingroup hardware_rtc + * + * \param t Pointer to a \ref datetime_t structure contains time to set + * \return true if set, false if the passed in datetime was invalid. + */ +bool rtc_set_datetime(datetime_t *t); + +/*! \brief Get the current time from the RTC + * \ingroup hardware_rtc + * + * \param t Pointer to a \ref datetime_t structure to receive the current RTC time + * \return true if datetime is valid, false if the RTC is not running. + */ +bool rtc_get_datetime(datetime_t *t); + +/*! \brief Is the RTC running? + * \ingroup hardware_rtc + * + */ +bool rtc_running(void); + +/*! \brief Set a time in the future for the RTC to call a user provided callback + * \ingroup hardware_rtc + * + * \param t Pointer to a \ref datetime_t structure containing a time in the future to fire the alarm. Any values set to -1 will not be matched on. + * \param user_callback pointer to a \ref rtc_callback_t to call when the alarm fires + */ +void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback); + +/*! \brief Disable the RTC alarm (if active) + * \ingroup hardware_rtc + */ +void rtc_disable_alarm(void); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c new file mode 100644 index 00000000000..91bd1994c1d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" + +#include "hardware/irq.h" +#include "hardware/rtc.h" +#include "hardware/resets.h" +#include "hardware/clocks.h" + +// Set this when setting an alarm +static rtc_callback_t _callback = NULL; +static bool _alarm_repeats = false; + +bool rtc_running(void) { + return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); +} + +void rtc_init(void) { + // Get clk_rtc freq and make sure it is running + uint rtc_freq = clock_get_hz(clk_rtc); + assert(rtc_freq != 0); + + // Take rtc out of reset now that we know clk_rtc is running + reset_block(RESETS_RESET_RTC_BITS); + unreset_block_wait(RESETS_RESET_RTC_BITS); + + // Set up the 1 second divider. + // If rtc_freq is 400 then clkdiv_m1 should be 399 + rtc_freq -= 1; + + // Check the freq is not too big to divide + assert(rtc_freq <= RTC_CLKDIV_M1_BITS); + + // Write divide value + rtc_hw->clkdiv_m1 = rtc_freq; +} + +static bool valid_datetime(datetime_t *t) { + // Valid ranges taken from RTC doc. Note when setting an RTC alarm + // these values are allowed to be -1 to say "don't match this value" + if (!(t->year >= 0 && t->year <= 4095)) return false; + if (!(t->month >= 1 && t->month <= 12)) return false; + if (!(t->day >= 1 && t->day <= 31)) return false; + if (!(t->dotw >= 0 && t->dotw <= 6)) return false; + if (!(t->hour >= 0 && t->hour <= 23)) return false; + if (!(t->min >= 0 && t->min <= 59)) return false; + if (!(t->sec >= 0 && t->sec <= 59)) return false; + return true; +} + +bool rtc_set_datetime(datetime_t *t) { + if (!valid_datetime(t)) { + return false; + } + + // Disable RTC + rtc_hw->ctrl = 0; + // Wait while it is still active + while (rtc_running()) { + tight_loop_contents(); + } + + // Write to setup registers + rtc_hw->setup_0 = (t->year << RTC_SETUP_0_YEAR_LSB ) | + (t->month << RTC_SETUP_0_MONTH_LSB) | + (t->day << RTC_SETUP_0_DAY_LSB); + rtc_hw->setup_1 = (t->dotw << RTC_SETUP_1_DOTW_LSB) | + (t->hour << RTC_SETUP_1_HOUR_LSB) | + (t->min << RTC_SETUP_1_MIN_LSB) | + (t->sec << RTC_SETUP_1_SEC_LSB); + + // Load setup values into rtc clock domain + rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; + + // Enable RTC and wait for it to be running + rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS; + while (!rtc_running()) { + tight_loop_contents(); + } + + return true; +} + +bool rtc_get_datetime(datetime_t *t) { + // Make sure RTC is running + if (!rtc_running()) { + return false; + } + + // Note: RTC_0 should be read before RTC_1 + t->dotw = (rtc_hw->rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB; + t->hour = (rtc_hw->rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB; + t->min = (rtc_hw->rtc_0 & RTC_RTC_0_MIN_BITS ) >> RTC_RTC_0_MIN_LSB; + t->sec = (rtc_hw->rtc_0 & RTC_RTC_0_SEC_BITS ) >> RTC_RTC_0_SEC_LSB; + t->year = (rtc_hw->rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB; + t->month = (rtc_hw->rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB; + t->day = (rtc_hw->rtc_1 & RTC_RTC_1_DAY_BITS ) >> RTC_RTC_1_DAY_LSB; + + return true; +} + +static void rtc_enable_alarm(void) { + // Set matching and wait for it to be enabled + hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); + while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)) { + tight_loop_contents(); + } +} + +static void rtc_irq_handler(void) { + // Always disable the alarm to clear the current IRQ. + // Even if it is a repeatable alarm, we don't want it to keep firing. + // If it matches on a second it can keep firing for that second. + rtc_disable_alarm(); + + if (_alarm_repeats) { + // If it is a repeatable alarm, re enable the alarm. + rtc_enable_alarm(); + } + + // Call user callback function + if (_callback) { + _callback(); + } +} + +static bool rtc_alarm_repeats(datetime_t *t) { + // If any value is set to -1 then we don't match on that value + // hence the alarm will eventually repeat + if (t->year == -1) return true; + if (t->month == -1) return true; + if (t->day == -1) return true; + if (t->dotw == -1) return true; + if (t->hour == -1) return true; + if (t->min == -1) return true; + if (t->sec == -1) return true; + return false; +} + +void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback) { + rtc_disable_alarm(); + + // Only add to setup if it isn't -1 + rtc_hw->irq_setup_0 = ((t->year == -1) ? 0 : (t->year << RTC_IRQ_SETUP_0_YEAR_LSB )) | + ((t->month == -1) ? 0 : (t->month << RTC_IRQ_SETUP_0_MONTH_LSB)) | + ((t->day == -1) ? 0 : (t->day << RTC_IRQ_SETUP_0_DAY_LSB )); + rtc_hw->irq_setup_1 = ((t->dotw == -1) ? 0 : (t->dotw << RTC_IRQ_SETUP_1_DOTW_LSB)) | + ((t->hour == -1) ? 0 : (t->hour << RTC_IRQ_SETUP_1_HOUR_LSB)) | + ((t->min == -1) ? 0 : (t->min << RTC_IRQ_SETUP_1_MIN_LSB )) | + ((t->sec == -1) ? 0 : (t->sec << RTC_IRQ_SETUP_1_SEC_LSB )); + + // Set the match enable bits for things we care about + if (t->year != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); + if (t->month != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); + if (t->day != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); + if (t->dotw != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); + if (t->hour != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); + if (t->min != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); + if (t->sec != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); + + // Does it repeat? I.e. do we not match on any of the bits + _alarm_repeats = rtc_alarm_repeats(t); + + // Store function pointer we can call later + _callback = user_callback; + + irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler); + + // Enable the IRQ at the peri + rtc_hw->inte = RTC_INTE_RTC_BITS; + + // Enable the IRQ at the proc + irq_set_enabled(RTC_IRQ, true); + + rtc_enable_alarm(); +} + +void rtc_disable_alarm(void) { + // Disable matching and wait for it to stop being active + hw_clear_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); + while(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS) { + tight_loop_contents(); + } +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/CMakeLists.txt new file mode 100644 index 00000000000..03e7f1f290c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(spi) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h new file mode 100644 index 00000000000..3ee8736e0c5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_SPI_H +#define _HARDWARE_SPI_H + +#include "pico.h" +#include "pico/time.h" +#include "hardware/structs/spi.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi +#ifndef PARAM_ASSERTIONS_ENABLED_SPI +#define PARAM_ASSERTIONS_ENABLED_SPI 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/spi.h + * \defgroup hardware_spi hardware_spi + * + * Hardware SPI API + * + * RP2040 has 2 identical instances of the Serial Peripheral Interface (SPI) controller. + * + * The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have + * Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces. + * + * Controller can be defined as master or slave using the \ref spi_set_slave function. + * + * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information. + */ + +/** + * Opaque type representing an SPI instance. + */ +typedef struct spi_inst spi_inst_t; + +/** Identifier for the first (SPI 0) hardware SPI instance (for use in SPI functions). + * + * e.g. spi_init(spi0, 48000) + * + * \ingroup hardware_spi + */ +#define spi0 ((spi_inst_t * const)spi0_hw) + +/** Identifier for the second (SPI 1) hardware SPI instance (for use in SPI functions). + * + * e.g. spi_init(spi1, 48000) + * + * \ingroup hardware_spi + */ +#define spi1 ((spi_inst_t * const)spi1_hw) + +typedef enum { + SPI_CPHA_0 = 0, + SPI_CPHA_1 = 1 +} spi_cpha_t; + +typedef enum { + SPI_CPOL_0 = 0, + SPI_CPOL_1 = 1 +} spi_cpol_t; + +typedef enum { + SPI_LSB_FIRST = 0, + SPI_MSB_FIRST = 1 +} spi_order_t; + +// ---------------------------------------------------------------------------- +// Setup + +/*! \brief Initialise SPI instances + * \ingroup hardware_spi + * Puts the SPI into a known state, and enable it. Must be called before other + * functions. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param baudrate Baudrate required in Hz + * + * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen, + * and this function does not return any indication of this. You can use the \ref spi_set_baudrate function + * which will return the actual baudrate selected if this is important. + */ +void spi_init(spi_inst_t *spi, uint baudrate); + +/*! \brief Deinitialise SPI instances + * \ingroup hardware_spi + * Puts the SPI into a disabled state. Init will need to be called to reenable the device + * functions. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + */ +void spi_deinit(spi_inst_t *spi); + +/*! \brief Set SPI baudrate + * \ingroup hardware_spi + * + * Set SPI frequency as close as possible to baudrate, and return the actual + * achieved rate. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param baudrate Baudrate required in Hz, should be capable of a bitrate of at least 2Mbps, or higher, depending on system clock settings. + * \return The actual baudrate set + */ +uint spi_set_baudrate(spi_inst_t *spi, uint baudrate); + +/*! \brief Convert I2c instance to hardware instance number + * \ingroup hardware_spi + * + * \param spi SPI instance + * \return Number of SPI, 0 or 1. + */ +static inline uint spi_get_index(spi_inst_t *spi) { + invalid_params_if(SPI, spi != spi0 && spi != spi1); + return spi == spi1 ? 1 : 0; +} + +static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { + spi_get_index(spi); // check it is a hw spi + return (spi_hw_t *)spi; +} + +/*! \brief Configure SPI + * \ingroup hardware_spi + * + * Configure how the SPI serialises and deserialises data on the wire + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param data_bits Number of data bits per transfer. Valid values 4..16. + * \param cpol SSPCLKOUT polarity, applicable to Motorola SPI frame format only. + * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only + * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022 + */ +static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, spi_order_t order) { + invalid_params_if(SPI, data_bits < 4 || data_bits > 16); + // LSB-first not supported on PL022: + invalid_params_if(SPI, order != SPI_MSB_FIRST); + invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); + invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); + hw_write_masked(&spi_get_hw(spi)->cr0, + (data_bits - 1) << SPI_SSPCR0_DSS_LSB | + cpol << SPI_SSPCR0_SPO_LSB | + cpha << SPI_SSPCR0_SPH_LSB, + SPI_SSPCR0_DSS_BITS | + SPI_SSPCR0_SPO_BITS | + SPI_SSPCR0_SPH_BITS); +} + +/*! \brief Set SPI master/slave + * \ingroup hardware_spi + * + * Configure the SPI for master- or slave-mode operation. By default, + * spi_init() sets master-mode. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param slave true to set SPI device as a slave device, false for master. + */ +static inline void spi_set_slave(spi_inst_t *spi, bool slave) { + if (slave) + hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); + else + hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); +} + +// ---------------------------------------------------------------------------- +// Generic input/output + +/*! \brief Check whether a write can be done on SPI device + * \ingroup hardware_spi + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return 0 if no space is available to write. Non-zero if a write is possible + * + * \note Although the controllers each have a 8 deep TX FIFO, the current HW implementation can only return 0 or 1 + * rather than the space available. + */ +static inline size_t spi_is_writable(spi_inst_t *spi) { + // PL022 doesn't expose levels directly, so return values are only 0 or 1 + return (spi_get_hw(spi)->sr & SPI_SSPSR_TNF_BITS) >> SPI_SSPSR_TNF_LSB; +} + +/*! \brief Check whether a read can be done on SPI device + * \ingroup hardware_spi + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return Non-zero if a read is possible i.e. data is present + * + * \note Although the controllers each have a 8 deep RX FIFO, the current HW implementation can only return 0 or 1 + * rather than the data available. + */ +static inline size_t spi_is_readable(spi_inst_t *spi) { + return (spi_get_hw(spi)->sr & SPI_SSPSR_RNE_BITS) >> SPI_SSPSR_RNE_LSB; +} + +/*! \brief Write/Read to/from an SPI device + * \ingroup hardware_spi + * + * Write \p len bytes from \p src to SPI. Simultaneously read \p len bytes from SPI to \p dst. + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param src Buffer of data to write + * \param dst Buffer for read data + * \param len Length of BOTH buffers + * \return Number of bytes written/read +*/ +int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len); + +/*! \brief Write to an SPI device, blocking + * \ingroup hardware_spi + * + * Write \p len bytes from \p src to SPI, and discard any data received back + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param src Buffer of data to write + * \param len Length of \p src + * \return Number of bytes written/read + */ +int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len); + +/*! \brief Read from an SPI device + * \ingroup hardware_spi + * + * Read \p len bytes from SPI to \p dst. + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * \p repeated_tx_data is output repeatedly on TX as data is read in from RX. + * Generally this can be 0, but some devices require a specific value here, + * e.g. SD cards expect 0xff + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param repeated_tx_data Buffer of data to write + * \param dst Buffer for read data + * \param len Length of buffer \p dst + * \return Number of bytes written/read + */ +int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len); + +// ---------------------------------------------------------------------------- +// SPI-specific operations and aliases + +// FIXME need some instance-private data for select() and deselect() if we are going that route + +/*! \brief Write/Read half words to/from an SPI device + * \ingroup hardware_spi + * + * Write \p len halfwords from \p src to SPI. Simultaneously read \p len halfwords from SPI to \p dst. + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * + * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read/write 8 data_bits. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param src Buffer of data to write + * \param dst Buffer for read data + * \param len Length of BOTH buffers in halfwords + * \return Number of bytes written/read +*/ +int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len); + +/*! \brief Write to an SPI device + * \ingroup hardware_spi + * + * Write \p len halfwords from \p src to SPI. Discard any data received back. + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * + * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only write 8 data_bits. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param src Buffer of data to write + * \param len Length of buffers + * \return Number of bytes written/read +*/ +int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); + +/*! \brief Read from an SPI device + * \ingroup hardware_spi + * + * Read \p len halfwords from SPI to \p dst. + * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate. + * \p repeated_tx_data is output repeatedly on TX as data is read in from RX. + * Generally this can be 0, but some devices require a specific value here, + * e.g. SD cards expect 0xff + * + * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read 8 data_bits. + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param repeated_tx_data Buffer of data to write + * \param dst Buffer for read data + * \param len Length of buffer \p dst in halfwords + * \return Number of bytes written/read + */ +int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c new file mode 100644 index 00000000000..b0cad30755c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/resets.h" +#include "hardware/clocks.h" +#include "hardware/spi.h" + +static inline void spi_reset(spi_inst_t *spi) { + invalid_params_if(SPI, spi != spi0 && spi != spi1); + reset_block(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); +} + +static inline void spi_unreset(spi_inst_t *spi) { + invalid_params_if(SPI, spi != spi0 && spi != spi1); + unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); +} + +void spi_init(spi_inst_t *spi, uint baudrate) { + spi_reset(spi); + spi_unreset(spi); + + (void) spi_set_baudrate(spi, baudrate); + spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); + // Always enable DREQ signals -- harmless if DMA is not listening + hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); + spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); + + // Finally enable the SPI + hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); +} + +void spi_deinit(spi_inst_t *spi) { + hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); + hw_clear_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); + spi_reset(spi); +} + +uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) { + uint freq_in = clock_get_hz(clk_peri); + uint prescale, postdiv; + invalid_params_if(SPI, baudrate > freq_in); + + // Find smallest prescale value which puts output frequency in range of + // post-divide. Prescale is an even number from 2 to 254 inclusive. + for (prescale = 2; prescale <= 254; prescale += 2) { + if (freq_in < (prescale + 2) * 256 * (uint64_t) baudrate) + break; + } + invalid_params_if(SPI, prescale > 254); // Frequency too low + + // Find largest post-divide which makes output <= baudrate. Post-divide is + // an integer in the range 1 to 256 inclusive. + for (postdiv = 256; postdiv > 1; --postdiv) { + if (freq_in / (prescale * (postdiv - 1)) > baudrate) + break; + } + + spi_get_hw(spi)->cpsr = prescale; + hw_write_masked(&spi_get_hw(spi)->cr0, (postdiv - 1) << SPI_SSPCR0_SCR_LSB, SPI_SSPCR0_SCR_BITS); + + // Return the frequency we were able to achieve + return freq_in / (prescale * postdiv); +} + +// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst. +// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit) +int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) { + // Never have more transfers in flight than will fit into the RX FIFO, + // else FIFO will overflow if this code is heavily interrupted. + const size_t fifo_depth = 8; + size_t rx_remaining = len, tx_remaining = len; + + while (rx_remaining || tx_remaining) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + spi_get_hw(spi)->dr = (uint32_t) *src++; + --tx_remaining; + } + if (rx_remaining && spi_is_readable(spi)) { + *dst++ = (uint8_t) spi_get_hw(spi)->dr; + --rx_remaining; + } + } + + return len; +} + +// Write len bytes directly from src to the SPI, and discard any data received back +int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) { + // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX + // is full, PL022 inhibits RX pushes, and sets a sticky flag on + // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set. + for (size_t i = 0; i < len; ++i) { + while (!spi_is_writable(spi)) + tight_loop_contents(); + spi_get_hw(spi)->dr = (uint32_t)src[i]; + } + // Drain RX FIFO, then wait for shifting to finish (which may be *after* + // TX FIFO drains), then drain RX FIFO again + while (spi_is_readable(spi)) + (void)spi_get_hw(spi)->dr; + while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS) + tight_loop_contents(); + while (spi_is_readable(spi)) + (void)spi_get_hw(spi)->dr; + + // Don't leave overrun flag set + spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; + + return len; +} + +// Read len bytes directly from the SPI to dst. +// repeated_tx_data is output repeatedly on SO as data is read in from SI. +// Generally this can be 0, but some devices require a specific value here, +// e.g. SD cards expect 0xff +int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) { + const size_t fifo_depth = 8; + size_t rx_remaining = len, tx_remaining = len; + + while (rx_remaining || tx_remaining) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; + --tx_remaining; + } + if (rx_remaining && spi_is_readable(spi)) { + *dst++ = (uint8_t) spi_get_hw(spi)->dr; + --rx_remaining; + } + } + + return len; +} + +// Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst. +int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) { + // Never have more transfers in flight than will fit into the RX FIFO, + // else FIFO will overflow if this code is heavily interrupted. + const size_t fifo_depth = 8; + size_t rx_remaining = len, tx_remaining = len; + + while (rx_remaining || tx_remaining) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + spi_get_hw(spi)->dr = (uint32_t) *src++; + --tx_remaining; + } + if (rx_remaining && spi_is_readable(spi)) { + *dst++ = (uint16_t) spi_get_hw(spi)->dr; + --rx_remaining; + } + } + + return len; +} + +// Write len bytes directly from src to the SPI, and discard any data received back +int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) { + // Deliberately overflow FIFO, then clean up afterward, to minimise amount + // of APB polling required per halfword + for (size_t i = 0; i < len; ++i) { + while (!spi_is_writable(spi)) + tight_loop_contents(); + spi_get_hw(spi)->dr = (uint32_t)src[i]; + } + + while (spi_is_readable(spi)) + (void)spi_get_hw(spi)->dr; + while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS) + tight_loop_contents(); + while (spi_is_readable(spi)) + (void)spi_get_hw(spi)->dr; + + // Don't leave overrun flag set + spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; + + return len; +} + +// Read len halfwords directly from the SPI to dst. +// repeated_tx_data is output repeatedly on SO as data is read in from SI. +int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) { + const size_t fifo_depth = 8; + size_t rx_remaining = len, tx_remaining = len; + + while (rx_remaining || tx_remaining) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; + --tx_remaining; + } + if (rx_remaining && spi_is_readable(spi)) { + *dst++ = (uint16_t) spi_get_hw(spi)->dr; + --rx_remaining; + } + } + + return len; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/CMakeLists.txt new file mode 100644 index 00000000000..1c64ed61a49 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(sync) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h new file mode 100644 index 00000000000..f375ff8bdad --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_SYNC_H +#define _HARDWARE_SYNC_H + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** \file hardware/sync.h + * \defgroup hardware_sync hardware_sync + * + * Low level hardware spin-lock, barrier and processor event API + * + * Functions for synchronisation between core's, HW, etc + * + * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software + * resources. + * + * \note spin locks 0-15 are currently reserved for fixed uses by the SDK - i.e. if you use them other + * functionality may break or not function optimally + */ + +/** \brief A spin lock identifier + * \ingroup hardware_sync + */ +typedef volatile uint32_t spin_lock_t; + +// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_IRQ +#define PICO_SPINLOCK_ID_IRQ 9 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_TIMER +#define PICO_SPINLOCK_ID_TIMER 10 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM +#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Spinlock ID for striped first, min=16, max=31, default=16, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST +#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Spinlock ID for striped last, min=16, max=31, default=23, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_STRIPED_LAST +#define PICO_SPINLOCK_ID_STRIPED_LAST 23 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Spinlock ID for claim free first, min=16, max=31, default=24, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST +#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_END, Spinlock ID for claim free end, min=16, max=31, default=31, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_END +#define PICO_SPINLOCK_ID_CLAIM_FREE_END 31 +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync +#ifndef PARAM_ASSERTIONS_ENABLED_SYNC +#define PARAM_ASSERTIONS_ENABLED_SYNC 0 +#endif + + +/*! \brief Insert a SEV instruction in to the code path. + * \ingroup hardware_sync + + * The SEV (send event) instruction sends an event to both cores. + */ +inline static void __sev() { + __asm volatile ("sev"); +} + +/*! \brief Insert a WFE instruction in to the code path. + * \ingroup hardware_sync + * + * The WFE (wait for event) instruction waits until one of a number of + * events occurs, including events signalled by the SEV instruction on either core. + */ +inline static void __wfe() { + __asm volatile ("wfe"); +} + +/*! \brief Insert a WFI instruction in to the code path. + * \ingroup hardware_sync +* + * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core. + */ +inline static void __wfi() { + __asm volatile ("wfi"); +} + +/*! \brief Insert a DMB instruction in to the code path. + * \ingroup hardware_sync + * + * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this + * instruction will be observed before any explicit access after the instruction. + */ +inline static void __dmb() { + __asm volatile ("dmb"); +} + +/*! \brief Insert a ISB instruction in to the code path. + * \ingroup hardware_sync + * + * ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, + * so that all instructions following the ISB are fetched from cache or memory again, after + * the ISB instruction has been completed. + */ +inline static void __isb() { + __asm volatile ("isb"); +} + +/*! \brief Acquire a memory fence + * \ingroup hardware_sync + */ +inline static void __mem_fence_acquire() { + // the original code below makes it hard for us to be included from C++ via a header + // which itself is in an extern "C", so just use __dmb instead, which is what + // is required on Cortex M0+ + __dmb(); +//#ifndef __cplusplus +// atomic_thread_fence(memory_order_acquire); +//#else +// std::atomic_thread_fence(std::memory_order_acquire); +//#endif +} + +/*! \brief Release a memory fence + * \ingroup hardware_sync + * + */ +inline static void __mem_fence_release() { + // the original code below makes it hard for us to be included from C++ via a header + // which itself is in an extern "C", so just use __dmb instead, which is what + // is required on Cortex M0+ + __dmb(); +//#ifndef __cplusplus +// atomic_thread_fence(memory_order_release); +//#else +// std::atomic_thread_fence(std::memory_order_release); +//#endif +} + +/*! \brief Save and disable interrupts + * \ingroup hardware_sync + * + * \return The prior interrupt enable status for restoration later via restore_interrupts() + */ +inline static uint32_t save_and_disable_interrupts() { + uint32_t status; + __asm volatile ("mrs %0, PRIMASK" : "=r" (status)::); + __asm volatile ("cpsid i"); + return status; +} + +/*! \brief Restore interrupts to a specified state + * \ingroup hardware_sync + * + * \param status Previous interrupt status from save_and_disable_interrupts() + */ +inline static void restore_interrupts(uint32_t status) { + __asm volatile ("msr PRIMASK,%0"::"r" (status) : ); +} + +/*! \brief Get HW Spinlock instance from number + * \ingroup hardware_sync + * + * \param lock_num Spinlock ID + * \return The spinlock instance + */ +inline static spin_lock_t *spin_lock_instance(uint lock_num) { + return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); +} + +/*! \brief Get HW Spinlock number from instance + * \ingroup hardware_sync + * + * \param lock The Spinlock instance + * \return The Spinlock ID + */ +inline static uint spin_lock_get_num(spin_lock_t *lock) { + return lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET); +} + +/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { + // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run + // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core + // anyway which should be finished soon + while (__builtin_expect(!*lock, 0)); + __mem_fence_acquire(); +} + +/*! \brief Release a spin lock without re-enabling interrupts + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +inline static void spin_unlock_unsafe(spin_lock_t *lock) { + __mem_fence_release(); + *lock = 0; +} + +/*! \brief Acquire a spin lock safely + * \ingroup hardware_sync + * + * This function will disable interrupts prior to acquiring the spinlock + * + * \param lock Spinlock instance + * \return interrupt status to be used when unlocking, to restore to original state + */ +inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { + uint32_t save = save_and_disable_interrupts(); + spin_lock_unsafe_blocking(lock); + return save; +} + +/*! \brief Check to see if a spinlock is currently acquired elsewhere. + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +inline static bool is_spin_locked(const spin_lock_t *lock) { + check_hw_size(spin_lock_t, 4); + uint32_t lock_num = lock - spin_lock_instance(0); + return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); +} + +/*! \brief Release a spin lock safely + * \ingroup hardware_sync + * + * This function will re-enable interrupts according to the parameters. + * + * \param lock Spinlock instance + * \param saved_irq Return value from the \ref spin_lock_blocking() function. + * \return interrupt status to be used when unlocking, to restore to original state + * + * \sa spin_lock_blocking() + */ +inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { + spin_unlock_unsafe(lock); + restore_interrupts(saved_irq); +} + +/*! \brief Get the current core number + * \ingroup hardware_sync + * + * \return The core number the call was made from + */ +static inline uint get_core_num() { + return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); +} + +/*! \brief Initialise a spin lock + * \ingroup hardware_sync + * + * The spin lock is initially unlocked + * + * \param lock_num The spin lock number + * \return The spin lock instance + */ +spin_lock_t *spin_lock_init(uint lock_num); + +/*! \brief Release all spin locks + * \ingroup hardware_sync + */ +void spin_locks_reset(void); + +// this number is not claimed +uint next_striped_spin_lock_num(); + +/*! \brief Mark a spin lock as used + * \ingroup hardware_sync + * + * Method for cooperative claiming of hardware. Will cause a panic if the spin lock + * is already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param lock_num the spin lock number + */ +void spin_lock_claim(uint lock_num); + +/*! \brief Mark multiple spin locks as used + * \ingroup hardware_sync + * + * Method for cooperative claiming of hardware. Will cause a panic if any of the spin locks + * are already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param lock_num_mask Bitfield of all required spin locks to claim (bit 0 == spin lock 0, bit 1 == spin lock 1 etc) + */ +void spin_lock_claim_mask(uint32_t lock_num_mask); + +/*! \brief Mark a spin lock as no longer used + * \ingroup hardware_sync + * + * Method for cooperative claiming of hardware. + * + * \param lock_num the spin lock number to release + */ +void spin_lock_unclaim(uint lock_num); + +/*! \brief Claim a free spin lock + * \ingroup hardware_sync + * + * \param required if true the function will panic if none are available + * \return the spin lock number or -1 if required was false, and none were free + */ +int spin_lock_claim_unused(bool required); + +#define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); }) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c new file mode 100644 index 00000000000..dba040a1772 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/sync.h" +#include "hardware/claim.h" + +static_assert(PICO_SPINLOCK_ID_STRIPED_LAST >= PICO_SPINLOCK_ID_STRIPED_FIRST, ""); +static uint8_t striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; +static uint32_t claimed; + +static void check_lock_num(uint __unused lock_num) { + invalid_params_if(SYNC, lock_num >= 32); +} + +void spin_locks_reset(void) { + for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { + spin_unlock_unsafe(spin_lock_instance(i)); + } +} + +spin_lock_t *spin_lock_init(uint lock_num) { + assert(lock_num >= 0 && lock_num < NUM_SPIN_LOCKS); + spin_lock_t *lock = spin_lock_instance(lock_num); + spin_unlock_unsafe(lock); + return lock; +} + +uint next_striped_spin_lock_num() { + uint rc = striped_spin_lock_num++; + if (striped_spin_lock_num > PICO_SPINLOCK_ID_STRIPED_LAST) { + striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; + } + return rc; +} + +void spin_lock_claim(uint lock_num) { + check_lock_num(lock_num); + hw_claim_or_assert((uint8_t *) &claimed, lock_num, "Spinlock %d is already claimed"); +} + +void spin_lock_claim_mask(uint32_t mask) { + for(uint i = 0; mask; i++, mask >>= 1u) { + if (mask & 1u) spin_lock_claim(i); + } +} + +void spin_lock_unclaim(uint lock_num) { + check_lock_num(lock_num); + hw_claim_clear((uint8_t *) &claimed, lock_num); +} + +int spin_lock_claim_unused(bool required) { + return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_END, "No spinlocks are available"); +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/CMakeLists.txt new file mode 100644 index 00000000000..358f74c50f3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/CMakeLists.txt @@ -0,0 +1,2 @@ +pico_simple_hardware_target(timer) +target_link_libraries(hardware_timer INTERFACE hardware_claim) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h new file mode 100644 index 00000000000..1815a2780eb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_TIMER_H +#define _HARDWARE_TIMER_H + +#include "pico.h" +#include "hardware/structs/timer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/timer.h + * \defgroup hardware_timer hardware_timer + * + * Low-level hardware timer API + * + * This API provides medium level access to the timer HW. + * See also \ref pico_time which provides higher levels functionality using the hardware timer. + * + * The timer peripheral on RP2040 supports the following features: + * - single 64-bit counter, incrementing once per microsecond + * - Latching two-stage read of counter, for race-free read over 32 bit bus + * - Four alarms: match on the lower 32 bits of counter, IRQ on match. + * + * By default the timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.8.2) which is derived + * from the clk_ref. + * + * The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of the 64 + * bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent to: + * - 2^32 ÷ 10^6: ~4295 seconds + * - 4295 ÷ 60: ~72 minutes + * + * The timer is expected to be used for short sleeps, if you want a longer alarm see the \ref hardware_rtc functions. + * + * \subsection timer_example Example + * \addtogroup hardware_timer + * + * \include hello_timer.c + * + * \see pico_time + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIMER, Enable/disable assertions in the timer module, type=bool, default=0, group=hardware_timer +#ifndef PARAM_ASSERTIONS_ENABLED_TIMER +#define PARAM_ASSERTIONS_ENABLED_TIMER 0 +#endif + +static inline void check_hardware_alarm_num_param(uint alarm_num) { + invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); +} + +/*! \brief Return a 32 bit timestamp value in microseconds +* \ingroup hardware_timer +* +* Returns the low 32 bits of the hardware timer. +* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds. +* +* \return the 32 bit timestamp +*/ +static inline uint32_t time_us_32() { + return timer_hw->timerawl; +} + +/*! \brief Return the current 64 bit timestamp value in microseconds +* \ingroup hardware_timer +* +* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this +* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps +* (we apologize for introducing a potential year 5851444 bug). +* +* \return the 64 bit timestamp +*/ +uint64_t time_us_64(); + +/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds + * \ingroup hardware_timer + * + * \param delay_us delay amount + */ +void busy_wait_us_32(uint32_t delay_us); + +/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds + * \ingroup hardware_timer + * + * \param delay_us delay amount + */ +void busy_wait_us(uint64_t delay_us); + +/*! \brief Busy wait wasting cycles until after the specified timestamp + * \ingroup hardware_timer + * + * \param t Absolute time to wait until + */ +void busy_wait_until(absolute_time_t t); + +/*! \brief Check if the specified timestamp has been reached + * \ingroup hardware_timer + * + * \param t Absolute time to compare against current time + * \return true if it is now after the specified timestamp + */ +static inline bool time_reached(absolute_time_t t) { + uint64_t target = to_us_since_boot(t); + uint32_t hi_target = target >> 32u; + uint32_t hi = timer_hw->timerawh; + return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target)); +} + +/*! Callback function type for hardware alarms + * \ingroup hardware_timer + * + * \param alarm_num the hardware alarm number + * \sa hardware_alarm_set_callback + */ +typedef void (*hardware_alarm_callback_t)(uint alarm_num); + +/*! \brief cooperatively claim the use of this hardware alarm_num + * \ingroup hardware_timer + * + * This method hard asserts if the hardware alarm is currently claimed. + * + * \param alarm_num the hardware alarm to claim + * \sa hardware_claiming + */ +void hardware_alarm_claim(uint alarm_num); + +/*! \brief cooperatively release the claim on use of this hardware alarm_num + * \ingroup hardware_timer + * + * \param alarm_num the hardware alarm to unclaim + * \sa hardware_claiming + */ +void hardware_alarm_unclaim(uint alarm_num); + +/*! \brief Enable/Disable a callback for a hardware timer on this core + * \ingroup hardware_timer + * + * This method enables/disables the alarm IRQ for the specified hardware alarm on the + * calling core, and set the specified callback to be associated with that alarm. + * + * This callback will be used for the timeout set via hardware_alarm_set_target + * + * \note This will install the handler on the current core if the IRQ handler isn't already set. + * Therefore the user has the opportunity to call this up from the core of their choice + * + * \param alarm_num the hardware alarm number + * \param callback the callback to install, or NULL to unset + * + * \sa hardware_alarm_set_target + */ +void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); + +/** + * \brief Set the current target for the specified hardware alarm + * + * This will replace any existing target + * + * @param alarm_num the hardware alarm number + * @param t the target timestamp + * @return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set + */ +bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); + +/** + * \brief Cancel an existing target (if any) for a given hardware_alarm + * + * @param alarm_num + */ + +void hardware_alarm_cancel(uint alarm_num); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c new file mode 100644 index 00000000000..76d5f9038ac --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/timer.h" +#include "hardware/irq.h" +#include "hardware/sync.h" +#include "hardware/claim.h" + +check_hw_layout(timer_hw_t, ints, TIMER_INTS_OFFSET); + +static hardware_alarm_callback_t alarm_callbacks[NUM_TIMERS]; +static uint32_t target_hi[NUM_TIMERS]; +static uint8_t timer_callbacks_pending; + +static_assert(NUM_TIMERS <= 4, ""); +static uint8_t claimed; + +void hardware_alarm_claim(uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + hw_claim_or_assert(&claimed, alarm_num, "Hardware alarm %d already claimed"); +} + +void hardware_alarm_unclaim(uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + hw_claim_clear(&claimed, alarm_num); +} + +/// tag::time_us_64[] +uint64_t time_us_64() { + // Need to make sure that the upper 32 bits of the timer + // don't change, so read that first + uint32_t hi = timer_hw->timerawh; + uint32_t lo; + do { + // Read the lower 32 bits + lo = timer_hw->timerawl; + // Now read the upper 32 bits again and + // check that it hasn't incremented. If it has loop around + // and read the lower 32 bits again to get an accurate value + uint32_t next_hi = timer_hw->timerawh; + if (hi == next_hi) break; + hi = next_hi; + } while (true); + return ((uint64_t) hi << 32u) | lo; +} +/// end::time_us_64[] + +/// \tag::busy_wait[] +void busy_wait_us_32(uint32_t delay_us) { + if (0 <= (int32_t)delay_us) { + // we only allow 31 bits, otherwise we could have a race in the loop below with + // values very close to 2^32 + uint32_t start = timer_hw->timerawl; + while (timer_hw->timerawl - start < delay_us) { + tight_loop_contents(); + } + } else { + busy_wait_us(delay_us); + } +} + +void busy_wait_us(uint64_t delay_us) { + uint64_t base = time_us_64(); + uint64_t target = base + delay_us; + if (target < base) { + target = (uint64_t)-1; + } + absolute_time_t t; + update_us_since_boot(&t, target); + busy_wait_until(t); +} + +void busy_wait_until(absolute_time_t t) { + uint64_t target = to_us_since_boot(t); + uint32_t hi_target = target >> 32u; + uint32_t hi = timer_hw->timerawh; + while (hi < hi_target) { + hi = timer_hw->timerawh; + tight_loop_contents(); + } + while (hi == hi_target && timer_hw->timerawl < (uint32_t) target) { + hi = timer_hw->timerawh; + tight_loop_contents(); + } +} +/// \end::busy_wait[] + +static inline uint harware_alarm_irq_number(uint alarm_num) { + return TIMER_IRQ_0 + alarm_num; +} + +static void hardware_alarm_irq_handler() { + // Determine which timer this IRQ is for + uint32_t ipsr; + __asm volatile ("mrs %0, ipsr" : "=r" (ipsr)::); + uint alarm_num = (ipsr & 0x3fu) - 16 - TIMER_IRQ_0; + check_hardware_alarm_num_param(alarm_num); + + hardware_alarm_callback_t callback = NULL; + + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); + uint32_t save = spin_lock_blocking(lock); + // Clear the timer IRQ (inside lock, because we check whether we have handled the IRQ yet in alarm_set by looking at the interrupt status + timer_hw->intr = 1u << alarm_num; + + // make sure the IRQ is still valid + if (timer_callbacks_pending & (1u << alarm_num)) { + // Now check whether we have a timer event to handle that isn't already obsolete (this could happen if we + // were already in the IRQ handler before someone else changed the timer setup + if (timer_hw->timerawh >= target_hi[alarm_num]) { + // we have reached the right high word as well as low word value + callback = alarm_callbacks[alarm_num]; + timer_callbacks_pending &= ~(1u << alarm_num); + } else { + // try again in 2^32 us + timer_hw->alarm[alarm_num] = timer_hw->alarm[alarm_num]; // re-arm the timer + } + } + + spin_unlock(lock, save); + + if (callback) { + callback(alarm_num); + } +} + +void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) { + // todo check current core owner + // note this should probably be subsumed by irq_set_exclusive_handler anyway, since that + // should disallow IRQ handlers on both cores + check_hardware_alarm_num_param(alarm_num); + uint irq_num = harware_alarm_irq_number(alarm_num); + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); + uint32_t save = spin_lock_blocking(lock); + if (callback) { + if (hardware_alarm_irq_handler != irq_get_vtable_handler(irq_num)) { + // note that set_exclusive will silently allow you to set the handler to the same thing + // since it is idempotent, which means we don't need to worry about locking ourselves + irq_set_exclusive_handler(irq_num, hardware_alarm_irq_handler); + irq_set_enabled(irq_num, true); + // Enable interrupt in block and at processor + hw_set_bits(&timer_hw->inte, 1u << alarm_num); + } + alarm_callbacks[alarm_num] = callback; + } else { + alarm_callbacks[alarm_num] = NULL; + timer_callbacks_pending &= ~(1u << alarm_num); + irq_remove_handler(irq_num, hardware_alarm_irq_handler); + irq_set_enabled(irq_num, false); + } + spin_unlock(lock, save); +} + +bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) { + bool missed; + uint64_t now = time_us_64(); + uint64_t t = to_us_since_boot(target); + if (now >= t) { + missed = true; + } else { + missed = false; + + // 1) actually set the hardware timer + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); + uint32_t save = spin_lock_blocking(lock); + timer_hw->intr = 1u << alarm_num; + timer_callbacks_pending |= 1u << alarm_num; + timer_hw->alarm[alarm_num] = (uint32_t) t; + // Set the alarm. Writing time should arm it + target_hi[alarm_num] = t >> 32u; + + // 2) check for races + if (!(timer_hw->armed & 1u << alarm_num)) { + // not armed, so has already fired .. IRQ must be pending (we are still under lock) + assert(timer_hw->ints & 1u << alarm_num); + } else { + if (time_us_64() >= t) { + // ok well it is time now; the irq isn't being handled yet because of the spin lock + // however the other core might be in the IRQ handler itself about to do a callback + // we do the firing ourselves (and indicate to the IRQ handler if any that it shouldn't + missed = true; + // disarm the timer + timer_hw->armed = 1u << alarm_num; + timer_hw->intr = 1u << alarm_num; // clear the IRQ too + // and set flag in case we're already in the IRQ handler waiting on the spinlock (on the other core) + timer_callbacks_pending &= ~(1u << alarm_num); + } + } + spin_unlock(lock, save); + } + return missed; +} + +void hardware_alarm_cancel(uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); + uint32_t save = spin_lock_blocking(lock); + timer_hw->armed = 1u << alarm_num; + timer_callbacks_pending &= ~(1u << alarm_num); + spin_unlock(lock, save); +} + + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/CMakeLists.txt new file mode 100644 index 00000000000..9fe65d54226 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(uart) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h new file mode 100644 index 00000000000..c957a335284 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_UART_H +#define _HARDWARE_UART_H + +#include "pico.h" +#include "hardware/structs/uart.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart +#ifndef PARAM_ASSERTIONS_ENABLED_UART +#define PARAM_ASSERTIONS_ENABLED_UART 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PICO_UART_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF translation support, type=bool, default=1, group=hardware_uart +#ifndef PICO_UART_ENABLE_CRLF_SUPPORT +#define PICO_UART_ENABLE_CRLF_SUPPORT 1 +#endif + +// PICO_CONFIG: PICO_UART_DEFAULT_CRLF, Enable/disable CR/LF translation on UART, type=bool, default=0, depends=PICO_UART_ENABLE_CRLF_SUPPORT, group=hardware_uart +#ifndef PICO_UART_DEFAULT_CRLF +#define PICO_UART_DEFAULT_CRLF 0 +#endif + +// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, default=0, group=hardware_uart +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 ///< Default UART instance +#endif + +// PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart +#ifndef PICO_DEFAULT_UART_BAUD_RATE +#define PICO_DEFAULT_UART_BAUD_RATE 115200 ///< Default baud rate +#endif + +// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, default=0, group=hardware_uart +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 ///< Default TX pin +#endif + +// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, default=1, group=hardware_uart +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 ///< Default RX pin +#endif + +/** \file hardware/uart.h + * \defgroup hardware_uart hardware_uart + * + * Hardware UART API + * + * RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number + * of GPIO pins as defined in the GPIO muxing. + * + * Only the TX, RX, RTS, and CTS signals are + * connected, meaning that the modem mode and IrDA mode of the PL011 are not supported. + * + * \subsection uart_example Example + * \addtogroup hardware_uart + * + * \code + * int main() { + * + * // Initialise UART 0 + * uart_init(uart0, 115200); + * + * // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX + * gpio_set_function(0, GPIO_FUNC_UART); + * gpio_set_function(1, GPIO_FUNC_UART); + * + * uart_puts(uart0, "Hello world!"); + * } + * \endcode + */ + +// Currently always a pointer to hw but it might not be in the future +typedef struct uart_inst uart_inst_t; + +/** The UART identifiers for use in UART functions. + * + * e.g. uart_init(uart1, 48000) + * + * \ingroup hardware_uart + * @{ + */ +#define uart0 ((uart_inst_t * const)uart0_hw) ///< Identifier for UART instance 0 +#define uart1 ((uart_inst_t * const)uart1_hw) ///< Identifier for UART instance 1 + +/** @} */ + +#ifndef PICO_DEFAULT_UART_INSTANCE +#define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART)) +#endif + +#define uart_default PICO_DEFAULT_UART_INSTANCE + +/*! \brief Convert UART instance to hardware instance number + * \ingroup hardware_uart + * + * \param uart UART instance + * \return Number of UART, 0 or 1. + */ +static inline uint uart_get_index(uart_inst_t *uart) { + invalid_params_if(UART, uart != uart0 && uart != uart1); + return uart == uart1 ? 1 : 0; +} + +static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) { + uart_get_index(uart); // check it is a hw uart + return (uart_hw_t *)uart; +} + +/** \brief UART Parity enumeration + * \ingroup hardware_uart + */ +typedef enum { + UART_PARITY_NONE, + UART_PARITY_EVEN, + UART_PARITY_ODD +} uart_parity_t; + +// ---------------------------------------------------------------------------- +// Setup + +/*! \brief Initialise a UART + * \ingroup hardware_uart + * + * Put the UART into a known state, and enable it. Must be called before other + * functions. + * + * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen, + * and this function will return the configured baud rate. + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param baudrate Baudrate of UART in Hz + * \return Actual set baudrate + */ +uint uart_init(uart_inst_t *uart, uint baudrate); + +/*! \brief DeInitialise a UART + * \ingroup hardware_uart + * + * Disable the UART if it is no longer used. Must be reinitialised before + * being used again. + * + * \param uart UART instance. \ref uart0 or \ref uart1 + */ +void uart_deinit(uart_inst_t *uart); + +/*! \brief Set UART baud rate + * \ingroup hardware_uart + * + * Set baud rate as close as possible to requested, and return actual rate selected. + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param baudrate Baudrate in Hz + * \return Actual set baudrate + */ +uint uart_set_baudrate(uart_inst_t *uart, uint baudrate); + +/*! \brief Set UART flow control CTS/RTS + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param cts If true enable flow control of TX by clear-to-send input + * \param rts If true enable assertion of request-to-send output by RX flow control + */ +static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) { + hw_write_masked(&uart_get_hw(uart)->cr, + (!!cts << UART_UARTCR_CTSEN_LSB) | (!!rts << UART_UARTCR_RTSEN_LSB), + UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS); +} + +/*! \brief Set UART data format + * \ingroup hardware_uart + * + * Configure the data format (bits etc() for the UART + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param data_bits Number of bits of data. 5..8 + * \param stop_bits Number of stop bits 1..2 + * \param parity Parity option. + */ +static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) { + invalid_params_if(UART, data_bits < 5 || data_bits > 8); + invalid_params_if(UART, stop_bits != 1 && stop_bits != 2); + invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); + hw_write_masked(&uart_get_hw(uart)->lcr_h, + ((data_bits - 5) << UART_UARTLCR_H_WLEN_LSB) | + ((stop_bits - 1) << UART_UARTLCR_H_STP2_LSB) | + ((parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | + ((parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), + UART_UARTLCR_H_WLEN_BITS | + UART_UARTLCR_H_STP2_BITS | + UART_UARTLCR_H_PEN_BITS | + UART_UARTLCR_H_EPS_BITS); +} + +/*! \brief Setup UART interrupts + * \ingroup hardware_uart + * + * Enable the UART's interrupt output. An interrupt handler will need to be installed prior to calling + * this function. + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param rx_has_data If true an interrupt will be fired when the RX FIFO contain data. + * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data. + */ +static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { + uart_get_hw(uart)->imsc = (!!tx_needs_data << UART_UARTIMSC_TXIM_LSB) | + (!!rx_has_data << UART_UARTIMSC_RXIM_LSB); + if (rx_has_data) { + // Set minimum threshold + hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB, + UART_UARTIFLS_RXIFLSEL_BITS); + } + if (tx_needs_data) { + // Set maximum threshold + hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_TXIFLSEL_LSB, + UART_UARTIFLS_TXIFLSEL_BITS); + } +} + +/*! \brief Test if specific UART is enabled + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \return true if the UART is enabled + */ +static inline bool uart_is_enabled(uart_inst_t *uart) { + return !!(uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS); +} + +/*! \brief Enable/Disable the FIFOs on specified UART + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param enabled true to enable FIFO (default), false to disable + */ +static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { + hw_write_masked(&uart_get_hw(uart)->lcr_h, + (!!enabled << UART_UARTLCR_H_FEN_LSB), + UART_UARTLCR_H_FEN_BITS); +} + + +// ---------------------------------------------------------------------------- +// Generic input/output + +/*! \brief Determine if space is available in the TX FIFO + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \return false if no space available, true otherwise + */ +static inline bool uart_is_writable(uart_inst_t *uart) { + return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS); +} + +/*! \brief Wait for the UART TX fifo to be drained + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + */ +static inline void uart_tx_wait_blocking(uart_inst_t *uart) { + while (uart_get_hw(uart)->fr & UART_UARTFR_BUSY_BITS) tight_loop_contents(); +} + +/*! \brief Determine whether data is waiting in the RX FIFO + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \return 0 if no data available, otherwise the number of bytes, at least, that can be read + * + * \note HW limitations mean this function will return either 0 or 1. + */ +static inline bool uart_is_readable(uart_inst_t *uart) { + // PL011 doesn't expose levels directly, so return values are only 0 or 1 + return !(uart_get_hw(uart)->fr & UART_UARTFR_RXFE_BITS); +} + +/*! \brief Write to the UART for transmission. + * \ingroup hardware_uart + * + * This function will block until all the data has been sent to the UART + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param src The bytes to send + * \param len The number of bytes to send + */ +static inline void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) { + for (size_t i = 0; i < len; ++i) { + while (!uart_is_writable(uart)) + tight_loop_contents(); + uart_get_hw(uart)->dr = *src++; + } +} + +/*! \brief Read from the UART + * \ingroup hardware_uart + * + * This function will block until all the data has been received from the UART + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param dst Buffer to accept received bytes + * \param len The number of bytes to receive. + */ +static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) { + for (size_t i = 0; i < len; ++i) { + while (!uart_is_readable(uart)) + tight_loop_contents(); + *dst++ = uart_get_hw(uart)->dr; + } +} + +// ---------------------------------------------------------------------------- +// UART-specific operations and aliases + +/*! \brief Write single character to UART for transmission. + * \ingroup hardware_uart + * + * This function will block until all the character has been sent + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param c The character to send + */ +static inline void uart_putc_raw(uart_inst_t *uart, char c) { + uart_write_blocking(uart, (const uint8_t *) &c, 1); +} + +/*! \brief Write single character to UART for transmission, with optional CR/LF conversions + * \ingroup hardware_uart + * + * This function will block until the character has been sent + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param c The character to send + */ +static inline void uart_putc(uart_inst_t *uart, char c) { +#if PICO_UART_ENABLE_CRLF_SUPPORT + extern short uart_char_to_line_feed[NUM_UARTS]; + if (uart_char_to_line_feed[uart_get_index(uart)] == c) + uart_putc_raw(uart, '\r'); +#endif + uart_putc_raw(uart, c); +} + +/*! \brief Write string to UART for transmission, doing any CR/LF conversions + * \ingroup hardware_uart + * + * This function will block until the entire string has been sent + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param s The null terminated string to send + */ +static inline void uart_puts(uart_inst_t *uart, const char *s) { +#if PICO_UART_ENABLE_CRLF_SUPPORT + bool last_was_cr = false; + while (*s) { + // Don't add extra carriage returns if one is present + if (last_was_cr) + uart_putc_raw(uart, *s); + else + uart_putc(uart, *s); + last_was_cr = *s++ == '\r'; + } +#else + while (*s) + uart_putc(uart, *s++); +#endif +} + +/*! \brief Read a single character to UART + * \ingroup hardware_uart + * + * This function will block until the character has been read + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \return The character read. + */ +static inline char uart_getc(uart_inst_t *uart) { + char c; + uart_read_blocking(uart, (uint8_t *) &c, 1); + return c; +} + +/*! \brief Assert a break condition on the UART transmission. + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param en Assert break condition (TX held low) if true. Clear break condition if false. + */ +static inline void uart_set_break(uart_inst_t *uart, bool en) { + if (en) + hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS); + else + hw_clear_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS); +} + +/*! \brief Set CR/LF conversion on UART + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param translate If true, convert line feeds to carriage return on transmissions + */ +void uart_set_translate_crlf(uart_inst_t *uart, bool translate); + +/*! \brief Wait for the default UART'S TX fifo to be drained + * \ingroup hardware_uart + */ +static inline void uart_default_tx_wait_blocking() { + uart_tx_wait_blocking(uart_default); +} + +/*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param us the number of microseconds to wait at most (may be 0 for an instantaneous check) + * \return true if the RX FIFO became non empty before the timeout, false otherwise + */ +bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c new file mode 100644 index 00000000000..51d8d74b223 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/uart.h" + +#include "hardware/structs/uart.h" +#include "hardware/resets.h" +#include "hardware/clocks.h" +#include "hardware/timer.h" + +#include "pico/assert.h" +#include "pico.h" + +check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET); +check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET); + +#if PICO_UART_ENABLE_CRLF_SUPPORT +short uart_char_to_line_feed[NUM_UARTS]; +#endif + +/// \tag::uart_reset[] +static inline void uart_reset(uart_inst_t *uart) { + invalid_params_if(UART, uart != uart0 && uart != uart1); + reset_block(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); +} + +static inline void uart_unreset(uart_inst_t *uart) { + invalid_params_if(UART, uart != uart0 && uart != uart1); + unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); +} +/// \end::uart_reset[] + +/// \tag::uart_init[] +uint uart_init(uart_inst_t *uart, uint baudrate) { + invalid_params_if(UART, uart != uart0 && uart != uart1); + + if (clock_get_hz(clk_peri) == 0) + return 0; + + uart_reset(uart); + uart_unreset(uart); + +#if PICO_UART_ENABLE_CRLF_SUPPORT + uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF); +#endif + + // Any LCR writes need to take place before enabling the UART + uint baud = uart_set_baudrate(uart, baudrate); + uart_set_format(uart, 8, 1, UART_PARITY_NONE); + + // Enable the UART, both TX and RX + uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS; + // Enable FIFOs + hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS); + // Always enable DREQ signals -- no harm in this if DMA is not listening + uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS; + + return baud; +} +/// \end::uart_init[] + +void uart_deinit(uart_inst_t *uart) { + invalid_params_if(UART, uart != uart0 && uart != uart1); + uart_reset(uart); +} + +/// \tag::uart_set_baudrate[] +uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { + invalid_params_if(UART, baudrate == 0); + uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate); + uint32_t baud_ibrd = baud_rate_div >> 7; + uint32_t baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; + + if (baud_ibrd == 0) { + baud_ibrd = 1; + baud_fbrd = 0; + } else if (baud_ibrd >= 65535) { + baud_ibrd = 65535; + baud_fbrd = 0; + } + + // Load PL011's baud divisor registers + uart_get_hw(uart)->ibrd = baud_ibrd; + uart_get_hw(uart)->fbrd = baud_fbrd; + + // PL011 needs a (dummy) line control register write to latch in the + // divisors. We don't want to actually change LCR contents here. + hw_set_bits(&uart_get_hw(uart)->lcr_h, 0); + + // See datasheet + return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd); +} +/// \end::uart_set_baudrate[] + +void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) { +#if PICO_UART_ENABLE_CRLF_SUPPORT + uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100; +#else + panic_unsupported(); +#endif +} + +bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) { + uint32_t t = time_us_32(); + do { + if (uart_is_readable(uart)) return true; + } while ((time_us_32() - t) <= us); + return false; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/CMakeLists.txt new file mode 100644 index 00000000000..9a5b1507e6f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(vreg) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h new file mode 100644 index 00000000000..7b4e2598655 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/include/hardware/vreg.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_VREG_H_ +#define _HARDWARE_VREG_H_ + +#include "pico.h" +#include "hardware/structs/vreg_and_chip_reset.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file vreg.h + * \defgroup hardware_vreg hardware_vreg + * + * Voltage Regulation API + * + */ + +/** Possible voltage values that can be applied to the regulator + */ +enum vreg_voltage { + VREG_VOLTAGE_0_85 = 0b0110, ///< 0.85v + VREG_VOLTAGE_0_90 = 0b0111, ///< 0.90v + VREG_VOLTAGE_0_95 = 0b1000, ///< 0.95v + VREG_VOLTAGE_1_00 = 0b1001, ///< 1.00v + VREG_VOLTAGE_1_05 = 0b1010, ///< 1.05v + VREG_VOLTAGE_1_10 = 0b1011, ///< 1.10v + VREG_VOLTAGE_1_15 = 0b1100, ///< 1.15v + VREG_VOLTAGE_1_20 = 0b1101, ///< 1.20v + VREG_VOLTAGE_1_25 = 0b1110, ///< 1.25v + VREG_VOLTAGE_1_30 = 0b1111, ///< 1.30v + + VREG_VOLTAGE_MIN = VREG_VOLTAGE_0_85, ///< Always the minimum possible voltage + VREG_VOLTAGE_DEFAULT = VREG_VOLTAGE_1_10, ///< Default voltage on power up. + VREG_VOLTAGE_MAX = VREG_VOLTAGE_1_30, ///< Always the maximum possible voltage +}; + + +/*! \brief Set voltage + * \ingroup hardware_vreg + * + * \param voltage The voltage (from enumeration \ref vreg_voltage) to apply to the voltage regulator + **/ +void vreg_set_voltage(enum vreg_voltage voltage); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c new file mode 100644 index 00000000000..654ab5af3d3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "hardware/vreg.h" + +void vreg_set_voltage(enum vreg_voltage voltage) { + hw_write_masked(&vreg_and_chip_reset_hw->vreg, voltage << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/CMakeLists.txt new file mode 100644 index 00000000000..43a401b11f0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(watchdog) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h new file mode 100644 index 00000000000..ae5ccdc8639 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_WATCHDOG_H +#define _HARDWARE_WATCHDOG_H + +#include "pico.h" + +/** \file hardware/watchdog.h + * \defgroup hardware_watchdog hardware_watchdog + * + * Hardware Watchdog Timer API + * + * Supporting functions for the Pico hardware watchdog timer. + * + * The RP2040 has a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero. + * For example, this can be used to restart the processor if the software running on it gets stuck in an infinite loop + * or similar. The programmer has to periodically write a value to the watchdog to stop it reaching zero. + * + * \subsection watchdog_example Example + * \addtogroup hardware_watchdog + * \include hello_watchdog.c + */ + +/*! \brief Define actions to perform at watchdog timeout + * \ingroup hardware_watchdog + * + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * parameter will not be in microseconds. See the datasheet for more details. + * + * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. + * + * \param pc If Zero, a standard boot will be performed, if non-zero this is the program counter to jump to on reset. + * \param sp If \p pc is non-zero, this will be the stack pointer used. + * \param delay_ms Initial load value. Maximum value 0x7fffff, approximately 8.3s. + */ +void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms); + +/*! \brief Start the watchdog tick + * \ingroup hardware_watchdog + * + * \param cycles This needs to be a divider that when applied to the XOSC input, produces a 1MHz clock. So if the XOSC is + * 12MHz, this will need to be 12. + */ +void watchdog_start_tick(uint cycles); + +/*! \brief Reload the watchdog counter with the amount of time set in watchdog_enable + * \ingroup hardware_watchdog + * + */ +void watchdog_update(void); + +/** + * \brief Enable the watchdog + * \ingroup hardware_watchdog + * + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * parameter will not be in microseconds. See the datasheet for more details. + * + * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. + * + * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds + * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code + */ +void watchdog_enable(uint32_t delay_ms, bool pause_on_debug); + +/** + * \brief Did the watchdog cause the last reboot? + * \ingroup hardware_watchdog + * + * @return true if the watchdog timer or a watchdog force caused the last reboot + * @return false there has been no watchdog reboot since run has been + */ +bool watchdog_caused_reboot(void); + +/** + * @brief Returns the number of microseconds before the watchdog will reboot the chip. + * \ingroup hardware_watchdog + * + * @return The number of microseconds before the watchdog will reboot the chip. + */ +uint32_t watchdog_get_count(void); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c new file mode 100644 index 00000000000..36031aaffca --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "hardware/watchdog.h" +#include "hardware/structs/watchdog.h" +#include "hardware/structs/psm.h" + +/// \tag::watchdog_start_tick[] +void watchdog_start_tick(uint cycles) { + // Important: This function also provides a tick reference to the timer + watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS; +} +/// \end::watchdog_start_tick[] + +// Value to load when updating the watchdog + +// tag::watchdog_update[] +static uint32_t load_value; + +void watchdog_update(void) { + watchdog_hw->load = load_value; +} +// end::watchdog_update[] + +uint32_t watchdog_get_count(void) { + return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ; +} + +// tag::watchdog_enable[] +// Helper function used by both watchdog_enable and watchdog_reboot +void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { + hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); + + // Reset everything apart from ROSC and XOSC + hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS)); + + uint32_t dbg_bits = WATCHDOG_CTRL_PAUSE_DBG0_BITS | + WATCHDOG_CTRL_PAUSE_DBG1_BITS | + WATCHDOG_CTRL_PAUSE_JTAG_BITS; + + if (pause_on_debug) { + hw_set_bits(&watchdog_hw->ctrl, dbg_bits); + } else { + hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); + } + + if (!delay_ms) delay_ms = 50; + + // Note, we have x2 here as the watchdog HW currently decrements twice per tick + load_value = delay_ms * 1000 * 2; + + if (load_value > 0xffffffu) + load_value = 0xffffffu; + + + watchdog_update(); + + hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); +} +// end::watchdog_enable[] + +void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { + // This watchdog enable doesn't reboot so clear scratch register + // with magic word to jump into code + watchdog_hw->scratch[4] = 0; + _watchdog_enable(delay_ms, pause_on_debug); +} + +void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { + check_hw_layout(watchdog_hw_t, scratch[7], WATCHDOG_SCRATCH7_OFFSET); + + // Clear enable before setting up scratch registers + hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); + + if (pc) { + pc |= 1u; // thumb mode + watchdog_hw->scratch[4] = 0xb007c0d3; + watchdog_hw->scratch[5] = pc ^ -0xb007c0d3; + watchdog_hw->scratch[6] = sp; + watchdog_hw->scratch[7] = pc; +// printf("rebooting %08x/%08x in %dms...\n", (uint) pc, (uint) sp, (uint) delay_ms); + } else { + watchdog_hw->scratch[4] = 0; +// printf("rebooting (regular)) in %dms...\n", (uint) delay_ms); + } + + // Don't pause watchdog for debug + _watchdog_enable(delay_ms, 0); +} + +bool watchdog_caused_reboot(void) { + // If any reason bits are set this is true + return watchdog_hw->reason; +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/CMakeLists.txt new file mode 100644 index 00000000000..50e86c23398 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(xosc) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h new file mode 100644 index 00000000000..0aa0842dbcb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_XOSC_H_ +#define _HARDWARE_XOSC_H_ + +#include "pico.h" +#include "hardware/structs/xosc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/xosc.h + * \defgroup hardware_xosc hardware_xosc + * + * Crystal Oscillator (XOSC) API + */ + +/*! \brief Initialise the crystal oscillator system + * \ingroup hardware_xosc + * + * This function will block until the crystal oscillator has stabilised. + **/ +void xosc_init(void); + +/*! \brief Disable the Crystal oscillator + * \ingroup hardware_xosc + * + * Turns off the crystal oscillator source, and waits for it to become unstable + **/ +void xosc_disable(void); + +/*! \brief Set the crystal oscillator system to dormant + * \ingroup hardware_xosc + * + * Turns off the crystal oscillator until it is woken by an interrupt. This will block and hence + * the entire system will stop, until an interrupt wakes it up. This function will + * continue to block until the oscillator becomes stable after its wakeup. + **/ +void xosc_dormant(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c new file mode 100644 index 00000000000..977f0bdc007 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" + +// For MHZ definitions etc +#include "hardware/clocks.h" + +#include "hardware/platform_defs.h" +#include "hardware/regs/xosc.h" +#include "hardware/structs/xosc.h" + +void xosc_init(void) { + // Assumes 1-15 MHz input + assert(XOSC_MHZ <= 15); + xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; + + // Set xosc startup delay + uint32_t startup_delay = (((12 * MHZ) / 1000) + 128) / 256; + xosc_hw->startup = startup_delay; + + // Set the enable bit now that we have set freq range and startup delay + hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); + + // Wait for XOSC to be stable + while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)); +} + +void xosc_disable(void) { + uint32_t tmp = xosc_hw->ctrl; + tmp &= (~XOSC_CTRL_ENABLE_BITS); + tmp |= (XOSC_CTRL_ENABLE_VALUE_DISABLE << XOSC_CTRL_ENABLE_LSB); + xosc_hw->ctrl = tmp; + // Wait for stable to go away + while(xosc_hw->status & XOSC_STATUS_STABLE_BITS); +} + +void xosc_dormant(void) { + // WARNING: This stops the xosc until woken up by an irq + xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT; + // Wait for it to become stable once woken up + while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt new file mode 100644 index 00000000000..7e5f2b97c73 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt @@ -0,0 +1,57 @@ +if (NOT TARGET pico_bit_ops) + #shims for ROM functions for -lgcc functions (listed below) + add_library(pico_bit_ops INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_bit_ops_compiler INTERFACE) + # PICO_BUILD_DEFINE: PICO_BIT_OPS_COMPILER, whether compiler provided bit_ops bit functions support is being used, type=bool, default=0, but dependent on CMake options, group=pico_bit_ops + target_compile_definitions(pico_bit_ops_compiler INTERFACE + PICO_BIT_OPS_COMPILER=1 + ) + + # add alias "default" which is just pico. + add_library(pico_bit_ops_default INTERFACE) + target_link_libraries(pico_bit_ops_default INTERFACE pico_bit_ops_pico) + + set(PICO_DEFAULT_BIT_OPS_IMPL pico_bit_ops_default) + + add_library(pico_bit_ops_pico INTERFACE) + target_link_libraries(pico_bit_ops INTERFACE + $>,$,${PICO_DEFAULT_BIT_OPS_IMPL}>) + + # PICO_BUILD_DEFINE: PICO_BIT_OPS_PICO, whether optimized pico/bootrom provided bit_ops bit functions support is being used, type=bool, default=1, but dependent on CMake options, group=pico_bit_ops + target_compile_definitions(pico_bit_ops_pico INTERFACE + PICO_BIT_OPS_PICO=1 + ) + + target_sources(pico_bit_ops_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/bit_ops_aeabi.S + ) + + target_link_libraries(pico_bit_ops_pico INTERFACE pico_bootrom pico_bit_ops_headers) + + # gcc + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzdi2) + pico_wrap_function(pico_bit_ops_pico __ctzsi2) + pico_wrap_function(pico_bit_ops_pico __ctzdi2) + pico_wrap_function(pico_bit_ops_pico __popcountsi2) + pico_wrap_function(pico_bit_ops_pico __popcountdi2) + + # armclang + pico_wrap_function(pico_bit_ops_pico __clz) + pico_wrap_function(pico_bit_ops_pico __clzl) + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzll) + + macro(pico_set_bit_ops_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BIT_OPS_IMPL "pico_bit_ops_${IMPL}") + else() + message(FATAL_ERROR "bit_ops implementation must be set on executable not library") + endif() + endmacro() + +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S new file mode 100644 index 00000000000..7c0b42cc672 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.syntax unified +.cpu cortex-m0plus +.thumb + +#include "pico/asm_helper.S" +__pre_init __aeabi_bits_init, 00010 + +.macro bits_section name +#if PICO_BITS_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.section .data.aeabi_bits_funcs +.global aeabi_bits_funcs, aeabi_bits_funcs_end +.equ BITS_FUNC_COUNT, 4 +.align 4 +aeabi_bits_funcs: + .word rom_table_code('P','3') // popcount32 + .word rom_table_code('L','3') // clz32 + .word rom_table_code('T','3') // ctz32 + .word rom_table_code('R','3') // reverse32 +aeabi_bits_funcs_end: + +.section .text +.thumb_func +__aeabi_bits_init: + ldr r0, =aeabi_bits_funcs + movs r1, #BITS_FUNC_COUNT + ldr r3, =rom_funcs_lookup + bx r3 + +.equ POPCOUNT32, 0 +.equ CLZ32, 4 +.equ CTZ32, 8 +.equ REVERSE32, 12 + +bits_section clzsi +wrapper_func __clz +wrapper_func __clzl +wrapper_func __clzsi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #CLZ32] + bx r3 + +bits_section ctzsi +wrapper_func __ctzsi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #CTZ32] + bx r3 + +bits_section popcountsi +wrapper_func __popcountsi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #POPCOUNT32] + bx r3 + +bits_section clzdi +wrapper_func __clzll +wrapper_func __clzdi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #CLZ32] + cmp r1, #0 + bne 1f + push {lr} + blx r3 + adds r0, #32 + pop {pc} +1: + mov r0, r1 + bx r3 + +bits_section ctzdi +wrapper_func __ctzdi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #CTZ32] + cmp r0, #0 + bne 1f + bx r3 +1: + push {lr} + mov r0, r1 + blx r3 + adds r0, #32 + pop {pc} + +bits_section popcountdi +wrapper_func __popcountdi2 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #POPCOUNT32] + push {r1, r3, lr} + blx r3 + mov ip, r0 + pop {r0, r3} + blx r3 + mov r1, ip + add r0, r1 + pop {pc} + +bits_section reverse32 +regular_func reverse32 + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #REVERSE32] + bx r3 + +bits_section __rev +regular_func __rev +regular_func __revl + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #REVERSE32] + bx r3 + +bits_section __revll +regular_func __revll + push {lr} + ldr r3, =aeabi_bits_funcs + ldr r3, [r3, #REVERSE32] + push {r1, r3} + blx r3 + mov ip, r0 // reverse32 preserves ip + pop {r0, r3} + blx r3 + mov r1, ip + pop {pc} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/CMakeLists.txt new file mode 100644 index 00000000000..58ea575cd0b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/CMakeLists.txt @@ -0,0 +1,8 @@ +add_library(pico_bootrom INTERFACE) + +target_sources(pico_bootrom INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/bootrom.c + ) + +target_include_directories(pico_bootrom INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_link_libraries(pico_bootrom INTERFACE pico_base_headers) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c new file mode 100644 index 00000000000..08cdb33738e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/bootrom.h" + +/// \tag::table_lookup[] + +// Bootrom function: rom_table_lookup +// Returns the 32 bit pointer into the ROM if found or NULL otherwise. +typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); + +// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer +#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address) + +void *rom_func_lookup(uint32_t code) { + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); + uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); + return rom_table_lookup(func_table, code); +} + +void *rom_data_lookup(uint32_t code) { + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); + uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(0x16); + return rom_table_lookup(data_table, code); +} +/// \end::table_lookup[] + +bool rom_funcs_lookup(uint32_t *table, unsigned int count) { + bool ok = true; + for (unsigned int i = 0; i < count; i++) { + table[i] = (uintptr_t) rom_func_lookup(table[i]); + if (!table[i]) ok = false; + } + return ok; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h new file mode 100644 index 00000000000..1aa12973ef9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PLATFORM_BOOTROM_H +#define _PLATFORM_BOOTROM_H + +#include "pico.h" + +/** \file bootrom.h + * \defgroup pico_bootrom pico_bootrom + * Access to functions and data in the RP2040 bootrom + */ + + +/*! \brief Return a bootrom lookup code based on two ASCII characters + * \ingroup pico_bootrom + * + * These codes are uses to lookup data or function addresses in the bootrom + * + * \param c1 the first character + * \param c2 the second character + * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() + */ +static inline uint32_t rom_table_code(char c1, char c2) { + return (c2 << 8u) | c1; +} + +/*! + * \brief Lookup a bootrom function by code + * \ingroup pico_bootrom + * \param code the code + * \return a pointer to the function, or NULL if the code does not match any bootrom function + */ +void *rom_func_lookup(uint32_t code); + +/*! + * \brief Lookup a bootrom address by code + * \ingroup pico_bootrom + * \param code the code + * \return a pointer to the data, or NULL if the code does not match any bootrom function + */ +void *rom_data_lookup(uint32_t code); + +/*! + * \brief Helper function to lookup the addresses of multiple bootrom functions + * \ingroup pico_bootrom + * + * This method looks up the 'codes' in the table, and convert each table entry to the looked up + * function pointer, if there is a function for that code in the bootrom. + * + * \param table an IN/OUT array, elements are codes on input, function pointers on success. + * \param count the number of elements in the table + * \return true if all the codes were found, and converted to function pointers, false otherwise + */ +bool rom_funcs_lookup(uint32_t *table, unsigned int count); + +typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t); + +/*! + * \brief Reboot the device into BOOTSEL mode + * \ingroup pico_bootrom + * + * This function reboots the device into the BOOTSEL mode ('usb boot"). + * + * Facilities are provided to enable an "activity light" via GPIO attached LED for the USB Mass Storage Device, + * and to limit the USB interfaces exposed. + * + * \param usb_activity_gpio_pin_mask 0 No pins are used as per a cold boot. Otherwise a single bit set indicating which + * GPIO pin should be set to output and raised whenever there is mass storage activity + * from the host. + * \param disable_interface_mask value to control exposed interfaces + * - 0 To enable both interfaces (as per a cold boot) + * - 1 To disable the USB Mass Storage Interface + * - 2 To disable the USB PICOBOOT Interface + */ +static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, + uint32_t disable_interface_mask) { + reset_usb_boot_fn func = (reset_usb_boot_fn) rom_func_lookup(rom_table_code('U', 'B')); + func(usb_activity_gpio_pin_mask, disable_interface_mask); +} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h new file mode 100644 index 00000000000..4eb4b1c8903 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_SF_TABLE_H +#define _PICO_SF_TABLE_H + +// NOTE THESE FUNCTION IMPLEMENTATIONS MATCH THE BEHAVIOR DESCRIBED IN THE BOOTROM SECTION OF THE RP2040 DATASHEET + +#define SF_TABLE_FADD 0x00 +#define SF_TABLE_FSUB 0x04 +#define SF_TABLE_FMUL 0x08 +#define SF_TABLE_FDIV 0x0c +#define SF_TABLE_FCMP_FAST 0x10 +#define SF_TABLE_FCMP_FAST_FLAGS 0x14 +#define SF_TABLE_FSQRT 0x18 +#define SF_TABLE_FLOAT2INT 0x1c +#define SF_TABLE_FLOAT2FIX 0x20 +#define SF_TABLE_FLOAT2UINT 0x24 +#define SF_TABLE_FLOAT2UFIX 0x28 +#define SF_TABLE_INT2FLOAT 0x2c +#define SF_TABLE_FIX2FLOAT 0x30 +#define SF_TABLE_UINT2FLOAT 0x34 +#define SF_TABLE_UFIX2FLOAT 0x38 +#define SF_TABLE_FCOS 0x3c +#define SF_TABLE_FSIN 0x40 +#define SF_TABLE_FTAN 0x44 +#define SF_TABLE_V3_FSINCOS 0x48 +#define SF_TABLE_FEXP 0x4c +#define SF_TABLE_FLN 0x50 + +#define SF_TABLE_V1_SIZE 0x54 + +#define SF_TABLE_FCMP_BASIC 0x54 +#define SF_TABLE_FATAN2 0x58 +#define SF_TABLE_INT642FLOAT 0x5c +#define SF_TABLE_FIX642FLOAT 0x60 +#define SF_TABLE_UINT642FLOAT 0x64 +#define SF_TABLE_UFIX642FLOAT 0x68 +#define SF_TABLE_FLOAT2INT64 0x6c +#define SF_TABLE_FLOAT2FIX64 0x70 +#define SF_TABLE_FLOAT2UINT64 0x74 +#define SF_TABLE_FLOAT2UFIX64 0x78 +#define SF_TABLE_FLOAT2DOUBLE 0x7c + +#define SF_TABLE_V2_SIZE 0x80 + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/CMakeLists.txt new file mode 100644 index 00000000000..4b20e3ab2c3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/CMakeLists.txt @@ -0,0 +1,23 @@ +if (NOT TARGET pico_cxx_options) + add_library(pico_cxx_options INTERFACE) + + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enabled CXX exception handling, type=bool, default=0, group=pico_cxx_options + # PICO_BUILD_DEFINE: PICO_CXX_ENABLE_EXCEPTIONS, value of CMake var PICO_CXX_ENABLE_EXCEPTIONS, type=string, default=0, group=pico_cxx_options + if (NOT PICO_CXX_ENABLE_EXCEPTIONS) + target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=0) + target_compile_options( pico_cxx_options INTERFACE $<$:-fno-exceptions>) + target_compile_options( pico_cxx_options INTERFACE $<$:-fno-unwind-tables>) + else() + target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=1) + endif() + + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_RTTI, Enabled CXX rtti, type=bool, default=0, group=pico_cxx_options + if (NOT PICO_CXX_ENABLE_RTTI) + target_compile_options( pico_cxx_options INTERFACE $<$:-fno-rtti>) + endif() + + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enabled cxa-atexit, type=bool, default=0, group=pico_cxx_options + if (NOT PICO_CXX_ENABLE_CXA_ATEXIT) + target_compile_options( pico_cxx_options INTERFACE $<$:-fno-use-cxa-atexit>) + endif() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/doc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/doc.h new file mode 100644 index 00000000000..5d84e22549f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_cxx_options/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup pico_cxx_options pico_cxx_options + * \brief non-code library controlling C++ related compile options + */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt new file mode 100644 index 00000000000..9eda2355633 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt @@ -0,0 +1,52 @@ +if (NOT TARGET pico_divider) + # library to be depended on - we make this depend on particular implementations using per target generator expressions + add_library(pico_divider INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_divider_compiler INTERFACE) + target_compile_definitions(pico_divider_compiler INTERFACE + PICO_DIVIDER_COMPILER=1 + ) + + # add alias "default" which is just hardware. + add_library(pico_divider_default INTERFACE) + target_link_libraries(pico_divider_default INTERFACE pico_divider_hardware) + + set(PICO_DEFAULT_DIVIDER_IMPL pico_divider_default) + + target_link_libraries(pico_divider INTERFACE + $>,$,${PICO_DEFAULT_DIVIDER_IMPL}>) + + add_library(pico_divider_hardware_explicit INTERFACE) + target_sources(pico_divider_hardware_explicit INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/divider.S + ) + + target_link_libraries(pico_divider_hardware_explicit INTERFACE + pico_divider_headers + hardware_regs + ) + + add_library(pico_divider_hardware INTERFACE) + target_compile_definitions(pico_divider_hardware INTERFACE + PICO_DIVIDER_HARDWARE=1 + ) + + target_link_libraries(pico_divider_hardware INTERFACE pico_divider_hardware_explicit) + + pico_wrap_function(pico_divider_hardware __aeabi_idiv) + pico_wrap_function(pico_divider_hardware __aeabi_idivmod) + pico_wrap_function(pico_divider_hardware __aeabi_ldivmod) + pico_wrap_function(pico_divider_hardware __aeabi_uidiv) + pico_wrap_function(pico_divider_hardware __aeabi_uidivmod) + pico_wrap_function(pico_divider_hardware __aeabi_uldivmod) + + macro(pico_set_divider_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_DIVIDER_IMPL "pico_divider_${IMPL}") + else() + message(FATAL_ERROR "divider implementation must be set on executable not library") + endif() + endmacro() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S new file mode 100644 index 00000000000..12eae389959 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/regs/sio.h" +#include "hardware/regs/addressmap.h" + +.syntax unified +.cpu cortex-m0plus +.thumb + +#include "pico/asm_helper.S" + +#ifndef PICO_DIVIDER_CALL_IDIV0 +#define PICO_DIVIDER_CALL_IDIV0 1 +#endif + +#ifndef PICO_DIVIDER_CALL_LDIV0 +#define PICO_DIVIDER_CALL_LDIV0 1 +#endif + +.macro div_section name +#if PICO_DIVIDER_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +#if SIO_DIV_CSR_READY_LSB == 0 +.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 +#else +need to change SHIFT above +#endif +#if SIO_DIV_CSR_DIRTY_LSB == 1 +.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2 +#else +need to change SHIFT above +#endif + +@ wait 8-n cycles for the hardware divider +.macro wait_div n +.rept (8-\n) / 2 + b 9f +9: +.endr +.if (8-\n) % 2 + nop +.endif +.endm + + +#if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4) +#error register layout has changed - we rely on this order to make sure we save/restore in the right order +#endif + +# SIO_BASE ptr in r2 +.macro save_div_state_and_lr + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + # wait for results as we can't save signed-ness of operation +1: + lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY + bcc 1b + push {r4, r5, r6, r7, lr} + // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! + ldr r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] + ldr r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] + ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] + ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] +.endm + +.macro restore_div_state_and_return + // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order + // + // it is worth considering what happens if we are interrupted + // + // after writing r4: we are DIRTY and !READY + // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be + // saved/restored correctly and we'll restore the rest ourselves + // after writing r4, r5: we are DIRTY and !READY + // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor + // at least will be saved/restored correctly and and we'll restore the rest ourselves + // after writing r4, r5, r6: we are DIRTY and READY + // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), + // and we'll restore the remainder after the fact + + // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space + // and so 4 reads is cheaper (and we don't have to adjust r2) + str r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] + str r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] + str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] + str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] + pop {r4, r5, r6, r7, pc} +.endm + +.macro save_div_state_and_lr_64 + push {r4, r5, r6, r7, lr} + ldr r6, =SIO_BASE +1: + ldr r5, [r6, #SIO_DIV_CSR_OFFSET] + # wait for results as we can't save signed-ness of operation + lsrs r5, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY + bcc 1b + // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! + ldr r4, [r6, #SIO_DIV_UDIVIDEND_OFFSET] + ldr r5, [r6, #SIO_DIV_UDIVISOR_OFFSET] + ldr r7, [r6, #SIO_DIV_REMAINDER_OFFSET] + ldr r6, [r6, #SIO_DIV_QUOTIENT_OFFSET] +.endm + +.macro restore_div_state_and_return_64 + // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order + // + // it is worth considering what happens if we are interrupted + // + // after writing r4: we are DIRTY and !READY + // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be + // saved/restored correctly and we'll restore the rest ourselves + // after writing r4, r5: we are DIRTY and !READY + // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor + // at least will be saved/restored correctly and and we'll restore the rest ourselves + // after writing r4, r5, r6: we are DIRTY and READY + // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), + // and we'll restore the remainder after the fact + + mov ip, r2 + ldr r2, =SIO_BASE + // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space + // and so 4 reads is cheaper (and we don't have to adjust r2) + str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] + str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] + str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] + str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] + mov r2, ip + pop {r4, r5, r6, r7, pc} +.endm + + +// since idiv and idivmod only differ by a cycle, we'll make them the same! +div_section WRAPPER_FUNC_NAME(__aeabi_idiv) +.align 2 +wrapper_func __aeabi_idiv +wrapper_func __aeabi_idivmod +regular_func div_s32s32 +regular_func divmod_s32s32 + ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs divmod_s32s32_savestate +regular_func divmod_s32s32_unsafe + str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET] + str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET] + cmp r1, #0 + beq 1f + wait_div 2 + // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) + ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] + ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] + bx lr +1: + push {r2, lr} + movs r1, #0x80 + lsls r1, #24 + asrs r2, r0, #31 + eors r1, r2 + cmp r0, #0 + beq 1f + mvns r0, r1 +1: +#if PICO_DIVIDER_CALL_IDIV0 + bl __aeabi_idiv0 +#endif + movs r1, #0 // remainder 0 + // need to restore saved r2 as it hold SIO ptr + pop {r2, pc} +.align 2 +regular_func divmod_s32s32_savestate + save_div_state_and_lr + bl divmod_s32s32_unsafe + restore_div_state_and_return + +// since uidiv and uidivmod only differ by a cycle, we'll make them the same! +div_section WRAPPER_FUNC_NAME(__aeabi_uidiv) +regular_func div_u32u32 +regular_func divmod_u32u32 +wrapper_func __aeabi_uidiv +wrapper_func __aeabi_uidivmod + ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs divmod_u32u32_savestate +regular_func divmod_u32u32_unsafe + str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET] + str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET] + cmp r1, #0 + beq 1f + wait_div 2 + // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) + ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] + ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] + bx lr +1: + push {r2, lr} + cmp r0, #0 + beq 1f + movs r0, #0 + mvns r0, r0 +1: +#if PICO_DIVIDER_CALL_IDIV0 + bl __aeabi_idiv0 +#endif + movs r1, #0 // remainder 0 + // need to restore saved r2 as it hold SIO ptr + pop {r2, pc} +.align 2 +regular_func divmod_u32u32_savestate + save_div_state_and_lr + bl divmod_u32u32_unsafe + restore_div_state_and_return + +div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) + +.align 2 +wrapper_func __aeabi_ldivmod +regular_func div_s64s64 +regular_func divmod_s64s64 + mov ip, r2 + ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore + ldr r2, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + mov r2, ip + bcs divmod_s64s64_savestate + b divmod_s64s64_unsafe +.align 2 +divmod_s64s64_savestate: + save_div_state_and_lr_64 + bl divmod_s64s64_unsafe + restore_div_state_and_return_64 + +.align 2 +wrapper_func __aeabi_uldivmod +regular_func div_u64u64 +regular_func divmod_u64u64 + mov ip, r2 + ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore + ldr r2, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + mov r2, ip + bcs divmod_u64u64_savestate + b divmod_u64u64_unsafe +.align 2 +regular_func divmod_u64u64_savestate + save_div_state_and_lr_64 + bl divmod_u64u64_unsafe + restore_div_state_and_return_64 +.macro dneg lo,hi + mvns \hi,\hi + rsbs \lo,#0 + bne l\@_1 + adds \hi,#1 +l\@_1: +.endm + +.align 2 +regular_func divmod_s64s64_unsafe + cmp r3,#0 + blt 1f +@ here x +ve + beq 2f @ could x be zero? +3: + cmp r1,#0 + bge divmod_u64u64_unsafe @ both positive +@ y -ve, x +ve + push {r14} + dneg r0,r1 + bl divmod_u64u64_unsafe + dneg r0,r1 + dneg r2,r3 + pop {r15} + +2: + cmp r2,#0 + bne 3b @ back if x not zero + + cmp r0,#0 @ y==0? + bne 4f + cmp r1,#0 + beq 5f @ then pass 0 to __aeabi_ldiv0 +4: + movs r0,#0 + lsrs r1,#31 + lsls r1,#31 @ get sign bit + bne 5f @ y -ve? pass -2^63 to __aeabi_ldiv0 + mvns r0,r0 + lsrs r1,r0,#1 @ y +ve: pass 2^63-1 to __aeabi_ldiv0 +5: + push {r14} +#if PICO_DIVIDER_CALL_LDIV0 + bl __aeabi_ldiv0 +#endif + movs r2,#0 @ and return 0 for the remainder + movs r3,#0 + pop {r15} + +1: +@ here x -ve + push {r14} + cmp r1,#0 + blt 1f +@ y +ve, x -ve + dneg r2,r3 + bl divmod_u64u64_unsafe + dneg r0,r1 + pop {r15} + +1: +@ y -ve, x -ve + dneg r0,r1 + dneg r2,r3 + bl divmod_u64u64_unsafe + dneg r2,r3 + pop {r15} + +regular_func divmod_u64u64_unsafe + cmp r1,#0 + bne y64 @ y fits in 32 bits? + cmp r3,#0 @ yes; and x? + bne 1f + cmp r2,#0 + beq 2f @ x==0? + mov r12,r7 + ldr r7,=#SIO_BASE + str r0,[r7,#SIO_DIV_UDIVIDEND_OFFSET] + str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] + movs r1,#0 + movs r3,#0 + wait_div 2 + ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET] + ldr r0,[r7,#SIO_DIV_QUOTIENT_OFFSET] + mov r7,r12 + bx r14 + +2: @ divide by 0 with y<2^32 + cmp r0,#0 @ y==0? + beq 3f @ then pass 0 to __aeabi_ldiv0 +udiv0: + ldr r0,=#0xffffffff + movs r1,r0 @ pass 2^64-1 to __aeabi_ldiv0 +3: + push {r14} +#if PICO_DIVIDER_CALL_LDIV0 + bl __aeabi_ldiv0 +#endif + movs r2,#0 @ and return 0 for the remainder + movs r3,#0 + pop {r15} + +1: + movs r2,r0 @ x>y, so result is 0 remainder y + movs r3,r1 + movs r0,#0 + movs r1,#0 + bx r14 + +.ltorg + +@ here y occupies more than 32 bits +@ split into cases acccording to the size of x +y64: + cmp r3,#0 + beq 1f + b y64_x48 @ if x does not fit in 32 bits, go to 48- and 64-bit cases +1: + lsrs r3,r2,#16 + bne y64_x32 @ jump if x is 17..32 bits + +@ here x is at most 16 bits + + cmp r2,#0 + beq udiv0 @ x==0? exit as with y!=0 case above + push {r7} + ldr r7,=#SIO_BASE + str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET] + str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] + wait_div 4 + push {r4, r5} + lsrs r4,r0,#16 + ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r0=y0-q0*x; 0<=r0>16); + wait_div 1 + uxth r4,r0 + ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1>16); + wait_div 3 + movs r3,#0 + lsls r4,r5,#16 @ quotient=(q0<<32)+(q1<<16)+q2 + lsrs r5,#16 + ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r2=y2-q2*x; 0<=r2>15)+1; 2^16>48)*r)>>16; + lsls r7,r6,#13 + mov r14,r7 @ quh=q0<<13 + + muls r3,r6 @ x0l*q + lsrs r7,r3,#15 + lsls r3,#17 @ r3:r7 is (x0l*q)<<17 + subs r0,r3 + sbcs r1,r7 @ y-=(x0l*q)<<17 + + lsrs r3,r2,#16 @ x0h + muls r3,r6 @ q*x0h + adds r3,r3 + subs r1,r3 @ y-=(x0h*q)<<17 + + lsrs r6,r1,#3 + muls r6,r4 + lsrs r6,#16 @ q=((ui32)(y>>35)*r)>>16; + add r14,r6 @ quh+=q1 + + uxth r3,r2 @ x0l + muls r3,r6 @ x0l*q + lsrs r7,r3,#28 + lsls r3,#4 @ r3:r7 is (x0l*q)<<4 + subs r0,r3 + sbcs r1,r7 @ y-=(x0l*q)<<4 + + lsrs r3,r2,#16 @ x0h + muls r3,r6 @ x0h*q + lsrs r7,r3,#12 + lsls r3,#20 @ r3:r7 is (x0h*q)<<4 + subs r0,r3 + sbcs r1,r7 @ y-=(x0h*q)<<4 + + lsrs r6,r0,#22 + lsls r7,r1,#10 + orrs r6,r7 @ y>>22 + muls r6,r4 + lsrs r6,#16 @ q=((ui32)(y>>22)*r)>>16; + + cmp r5,#9 + blt last0 @ if(xsh<9) goto last0; + +@ on this path xsh>=9, which means x<2^23 + lsrs r2,#9 @ x0>>9: this shift loses no bits +@ the remainder y-x0*q is guaranteed less than a very small multiple of the remaining quotient +@ bits (at most 6 bits) times x, and so fits in one word + muls r2,r6 @ x0*q + subs r0,r2 @ y-x0*q + lsls r7,r6,#13 @ qul=q<<13 +1: + lsrs r6,r0,#9 + muls r6,r4 + lsrs r6,#16 @ q=((ui32)(y>>9)*r)>>16; + +@ here +@ r0 y +@ r2 x0>>9 +@ r5 xsh +@ r6 q +@ r7 qul +@ r12 x +@ r14 quh + + movs r3,#22 + subs r3,r5 @ 22-xsh + lsrs r6,r3 @ q>>=22-xsh + lsrs r7,r3 @ qul>>=22-xsh + adds r7,r6 @ qul+=q + mov r4,r12 + muls r6,r4 @ x*q + subs r2,r0,r6 @ y-=x*q + mov r0,r14 @ quh + adds r5,#4 @ xsh+4 + adds r3,#6 @ 28-xsh + movs r1,r0 + lsrs r1,r3 + lsls r0,r5 @ r0:r1 is quh<<(4+xsh) + adds r0,r7 + bcc 1f +2: + adds r1,#1 +1: @ qu=((ui64)quh<<(4+xsh))+qul + cmp r2,r4 + bhs 3f + movs r3,#0 + pop {r4-r7,r15} + +.ltorg + +3: + subs r2,r4 + adds r0,#1 + bcc 1b + b 2b @ while(y>=x) y-=x,qu++; + +@ here: +@ r0:r1 y +@ r2 x0 +@ r4 r +@ r5 xsh; xsh<9 +@ r6 q + +last0: + movs r7,#9 + subs r7,r5 @ 9-xsh + lsrs r6,r7 + mov r4,r12 @ x + uxth r2,r4 + muls r2,r6 @ q*xlo + subs r0,r2 + bcs 1f + subs r1,#1 @ y-=q*xlo +1: + lsrs r2,r4,#16 @ xhi + muls r2,r6 @ q*xhi + lsrs r3,r2,#16 + lsls r2,#16 + subs r2,r0,r2 + sbcs r1,r3 @ y-q*xhi + movs r3,r1 @ y now in r2:r3 + mov r0,r14 @ quh + adds r5,#4 @ xsh+4 + adds r7,#19 @ 28-xsh + movs r1,r0 + lsrs r1,r7 + lsls r0,r5 @ r0:r1 is quh<<(4+xsh) + adds r0,r6 + bcc 1f + adds r1,#1 @ quh<<(xsh+4))+q +1: + cmp r3,#0 @ y>=2^32? + bne 3f + cmp r2,r4 @ y>=x? + bhs 4f + pop {r4-r7,r15} + +3: + adds r0,#1 @ qu++ + bcc 2f + adds r1,#1 +2: + subs r2,r4 @ y-=x + bcs 3b + subs r3,#1 + bne 3b + +1: + cmp r2,r4 + bhs 4f + pop {r4-r7,r15} + +4: + adds r0,#1 @ qu++ + bcc 2f + adds r1,#1 +2: + subs r2,r4 @ y-=x + b 1b + +y64_x48: +@ here x is 33..64 bits + push {r4-r7,r14} @ save a copy of x + lsrs r4,r3,#16 + beq 1f + b y64_x64 @ jump if x is 49..64 bits +1: + push {r2-r3} @ save a copy of x +@ here x is 33..48 bits + movs r5,#0 @ xsh=0 + lsrs r4,r3,#8 + bne 1f + lsls r3,#8 + lsrs r6,r2,#24 + orrs r3,r6 + lsls r2,#8 @ if(x0<1U<<40) x0<<=8,xsh =8; + adds r5,#8 +1: + lsrs r4,r3,#12 + bne 1f + lsls r3,#4 + lsrs r6,r2,#28 + orrs r3,r6 + lsls r2,#4 @ if(x0<1U<<44) x0<<=4,xsh+=4; + adds r5,#4 +1: + lsrs r4,r3,#14 + bne 1f + lsls r3,#2 + lsrs r6,r2,#30 + orrs r3,r6 + lsls r2,#2 @ if(x0<1U<<46) x0<<=2,xsh+=2; + adds r5,#2 +1: + lsrs r4,r3,#15 + bne 1f + adds r2,r2 + adcs r3,r3 @ if(x0<1U<<47) x0<<=1,xsh+=1; + adds r5,#1 +1: +@ now 2^47<=x0<2^48, 0<=xsh<16 (amount x is shifted in x0); number of quotient bits to be calculated qb=xsh+17 17<=qb<33 + movs r4,r3 + adds r7,r2,r2 + adcs r4,r4 + adds r4,#1 @ x1=(ui32)(x0>>31)+1; // 2^16>48)*r)>>16; + lsls r7,r6,#13 + mov r14,r7 @ save q<<13 + uxth r7,r2 @ x0l + muls r7,r6 + subs r0,r7 + bcs 1f + subs r1,#1 +1: + subs r0,r7 + bcs 1f + subs r1,#1 +1: + uxth r7,r3 @ x0h + muls r7,r6 + subs r1,r7 + subs r1,r7 + lsrs r7,r2,#16 @ x0m + muls r7,r6 + lsls r6,r7,#17 + lsrs r7,#15 + subs r0,r6 + sbcs r1,r7 @ y-=((ui64)q*x0)<<1; + + lsrs r6,r1,#3 @ y>>35 + muls r6,r4 + lsrs r6,#16 @ q=((ui32)(y>>35)*r)>>16; + + cmp r5,#12 + blt last1 @ if(xsh<12) goto last1; + + add r14,r6 @ qu<<13+q + lsrs r2,#12 + lsls r7,r3,#20 + orrs r2,r7 + lsrs r3,#12 @ x0>>12 + + uxth r7,r2 @ x0l + muls r7,r6 + subs r0,r7 + bcs 1f + subs r1,#1 +1: + uxth r7,r3 @ x0h + muls r7,r6 + subs r1,r7 + lsrs r7,r2,#16 @ x0m + muls r7,r6 + lsls r6,r7,#16 + lsrs r7,#16 + subs r0,r6 + sbcs r1,r7 @ y-=((ui64)q*x0)>>12 + + lsrs r6,r0,#22 + lsls r7,r1,#10 + orrs r6,r7 @ y>>22 + muls r6,r4 + movs r7,#41 + subs r7,r5 + lsrs r6,r7 @ q=((ui32)(y>>22)*r)>>(16+25-xsh) + + subs r5,#12 + mov r7,r14 + lsls r7,r5 +2: + adds r7,r6 @ qu=(qu<<(xsh-12))+q + pop {r4,r5} @ recall x + +@ here +@ r0:r1 y +@ r4:r5 x +@ r6 q +@ r7 qu + + uxth r2,r4 + uxth r3,r5 + muls r2,r6 @ xlo*q + muls r3,r6 @ xhi*q + subs r0,r2 + sbcs r1,r3 + lsrs r2,r4,#16 + muls r2,r6 + lsrs r3,r2,#16 + lsls r2,#16 @ xm*q + subs r0,r2 + sbcs r1,r3 @ y-=(ui64)q*x + +1: + movs r2,r0 + movs r3,r1 + adds r7,#1 + subs r0,r4 + sbcs r1,r5 @ while(y>=x) y-=x,qu++; + bhs 1b + subs r0,r7,#1 @ correction to qu + movs r1,#0 + pop {r4-r7,r15} + +last1: +@ r0:r1 y +@ r2:r3 x0 +@ r5 xsh +@ r6 q + + movs r7,#12 + subs r7,r5 + lsrs r6,r7 @ q>>=12-xsh + mov r7,r14 + lsrs r7,#13 + lsls r7,r5 + adds r7,r7 @ qu<<(xsh+1) + b 2b + +y64_x64: +@ here x is 49..64 bits + movs r4,#0 @ q=0 if x>>32==0xffffffff + adds r5,r3,#1 + beq 1f + + ldr r7,=#SIO_BASE + str r5,[r7,#SIO_DIV_UDIVISOR_OFFSET] + str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET] + wait_div 0 + ldr r4,[r7,#SIO_DIV_QUOTIENT_OFFSET] @ q=(ui32)(y>>32)/((x>>32)+1) +1: + uxth r5,r2 + uxth r6,r3 + muls r5,r4 + muls r6,r4 + subs r0,r5 + sbcs r1,r6 + lsrs r5,r2,#16 + lsrs r6,r3,#16 + muls r5,r4 + muls r6,r4 + lsls r6,#16 + lsrs r7,r5,#16 + orrs r6,r7 + lsls r5,#16 + subs r0,r5 + sbcs r1,r6 @ y-=(ui64)q*x + + cmp r1,r3 @ while(y>=x) y-=x,q++ + bhs 1f +3: + movs r2,r0 + movs r3,r1 + movs r0,r4 + movs r1,#0 + pop {r4-r7,r15} + +1: + bne 2f + cmp r0,r2 + blo 3b +2: + subs r0,r2 + sbcs r1,r3 + adds r4,#1 + cmp r1,r3 + blo 3b + b 1b + +div_section divmod_s64s64_rem +regular_func divmod_s64s64_rem + push {r4, lr} + bl divmod_s64s64 + ldr r4, [sp, #8] + stmia r4!, {r2,r3} + pop {r4, pc} + +div_section divmod_u64u64_rem +regular_func divmod_u64u64_rem + push {r4, lr} + bl divmod_u64u64 + ldr r4, [sp, #8] + stmia r4!, {r2,r3} + pop {r4, pc} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt new file mode 100644 index 00000000000..a707385aa48 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt @@ -0,0 +1,127 @@ +if (NOT TARGET pico_double) + # library to be depended on - we make this depend on particular implementations using per target generator expressions + add_library(pico_double INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_double_compiler INTERFACE) + # PICO_BUILD_DEFINE: PICO_DOUBLE_COMPILER, whether compiler provided double support is being used, type=bool, default=0, but dependent on CMake options, group=pico_double + target_compile_definitions(pico_double_compiler INTERFACE + PICO_DOUBLE_COMPILER=1 + ) + + add_library(pico_double_headers INTERFACE) + target_include_directories(pico_double_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + # add alias "default" which is just pico. + add_library(pico_double_default INTERFACE) + target_link_libraries(pico_double_default INTERFACE pico_double_pico) + + set(PICO_DEFAULT_DOUBLE_IMPL pico_double_default) + + target_link_libraries(pico_double INTERFACE + $>,$,${PICO_DEFAULT_DOUBLE_IMPL}>) + + add_library(pico_double_pico INTERFACE) + target_sources(pico_double_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/double_aeabi.S + ${CMAKE_CURRENT_LIST_DIR}/double_init_rom.c + ${CMAKE_CURRENT_LIST_DIR}/double_math.c + ${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim.S + ) + # PICO_BUILD_DEFINE: PICO_DOUBLE_PICO, whether optimized pico/bootrom provided double support is being used, type=bool, default=1, but dependent on CMake options, group=pico_double + target_compile_definitions(pico_double_pico INTERFACE + PICO_DOUBLE_PICO=1 + ) + + target_link_libraries(pico_double_pico INTERFACE pico_bootrom pico_double_headers) + + add_library(pico_double_none INTERFACE) + target_sources(pico_double_none INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/double_none.S + ) + + target_link_libraries(pico_double_none INTERFACE pico_double_headers) + + # PICO_BUILD_DEFINE: PICO_DOUBLE_NONE, whether double support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_double + target_compile_definitions(pico_double_none INTERFACE + PICO_DOUBLE_NONE=1 + PICO_PRINTF_SUPPORT_FLOAT=0 # printing floats/doubles won't work, so we can save space by removing it + ) + + function(wrap_double_functions TARGET) + pico_wrap_function(${TARGET} __aeabi_dadd) + pico_wrap_function(${TARGET} __aeabi_ddiv) + pico_wrap_function(${TARGET} __aeabi_dmul) + pico_wrap_function(${TARGET} __aeabi_drsub) + pico_wrap_function(${TARGET} __aeabi_dsub) + pico_wrap_function(${TARGET} __aeabi_cdcmpeq) + pico_wrap_function(${TARGET} __aeabi_cdrcmple) + pico_wrap_function(${TARGET} __aeabi_cdcmple) + pico_wrap_function(${TARGET} __aeabi_dcmpeq) + pico_wrap_function(${TARGET} __aeabi_dcmplt) + pico_wrap_function(${TARGET} __aeabi_dcmple) + pico_wrap_function(${TARGET} __aeabi_dcmpge) + pico_wrap_function(${TARGET} __aeabi_dcmpgt) + pico_wrap_function(${TARGET} __aeabi_dcmpun) + pico_wrap_function(${TARGET} __aeabi_i2d) + pico_wrap_function(${TARGET} __aeabi_l2d) + pico_wrap_function(${TARGET} __aeabi_ui2d) + pico_wrap_function(${TARGET} __aeabi_ul2d) + pico_wrap_function(${TARGET} __aeabi_d2iz) + pico_wrap_function(${TARGET} __aeabi_d2lz) + pico_wrap_function(${TARGET} __aeabi_d2uiz) + pico_wrap_function(${TARGET} __aeabi_d2ulz) + pico_wrap_function(${TARGET} __aeabi_d2f) + pico_wrap_function(${TARGET} sqrt) + pico_wrap_function(${TARGET} cos) + pico_wrap_function(${TARGET} sin) + pico_wrap_function(${TARGET} tan) + pico_wrap_function(${TARGET} atan2) + pico_wrap_function(${TARGET} exp) + pico_wrap_function(${TARGET} log) + + pico_wrap_function(${TARGET} ldexp) + pico_wrap_function(${TARGET} copysign) + pico_wrap_function(${TARGET} trunc) + pico_wrap_function(${TARGET} floor) + pico_wrap_function(${TARGET} ceil) + pico_wrap_function(${TARGET} round) + pico_wrap_function(${TARGET} sincos) # gnu + pico_wrap_function(${TARGET} asin) + pico_wrap_function(${TARGET} acos) + pico_wrap_function(${TARGET} atan) + pico_wrap_function(${TARGET} sinh) + pico_wrap_function(${TARGET} cosh) + pico_wrap_function(${TARGET} tanh) + pico_wrap_function(${TARGET} asinh) + pico_wrap_function(${TARGET} acosh) + pico_wrap_function(${TARGET} atanh) + pico_wrap_function(${TARGET} exp2) + pico_wrap_function(${TARGET} log2) + pico_wrap_function(${TARGET} exp10) + pico_wrap_function(${TARGET} log10) + pico_wrap_function(${TARGET} pow) + pico_wrap_function(${TARGET} powint) #gnu + pico_wrap_function(${TARGET} hypot) + pico_wrap_function(${TARGET} cbrt) + pico_wrap_function(${TARGET} fmod) + pico_wrap_function(${TARGET} drem) + pico_wrap_function(${TARGET} remainder) + pico_wrap_function(${TARGET} remquo) + pico_wrap_function(${TARGET} expm1) + pico_wrap_function(${TARGET} log1p) + pico_wrap_function(${TARGET} fma) + endfunction() + + wrap_double_functions(pico_double_pico) + wrap_double_functions(pico_double_none) + + macro(pico_set_double_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_DOUBLE_IMPL "pico_double_${IMPL}") + else() + message(FATAL_ERROR "double implementation must be set on executable not library") + endif() + endmacro() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S new file mode 100644 index 00000000000..4ef7748e9a8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S @@ -0,0 +1,801 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "pico/bootrom/sf_table.h" + +__pre_init __aeabi_double_init, 00020 + +.syntax unified +.cpu cortex-m0plus +.thumb + +.macro double_section name +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro _double_wrapper_func x + wrapper_func \x +.endm + +.macro wrapper_func_d1 x + _double_wrapper_func \x +#if PICO_DOUBLE_PROPAGATE_NANS + mov ip, lr + bl __check_nan_d1 + mov lr, ip +#endif +.endm + +.macro wrapper_func_d2 x + _double_wrapper_func \x +#if PICO_DOUBLE_PROPAGATE_NANS + mov ip, lr + bl __check_nan_d2 + mov lr, ip +#endif +.endm + +.section .text + +#if PICO_DOUBLE_PROPAGATE_NANS +.thumb_func +__check_nan_d1: + movs r3, #1 + lsls r3, #21 + lsls r2, r1, #1 + adds r2, r3 + bhi 1f + bx lr +1: + bx ip + +.thumb_func +__check_nan_d2: + push {r0, r2} + movs r2, #1 + lsls r2, #21 + lsls r0, r1, #1 + adds r0, r2 + bhi 1f + lsls r0, r3, #1 + adds r0, r2 + bhi 2f + pop {r0, r2} + bx lr +2: + pop {r0, r2} + mov r0, r2 + mov r1, r3 + bx ip +1: + pop {r0, r2} + bx ip +#endif + +.macro table_tail_call SF_TABLE_OFFSET + push {r3, r4} +#if PICO_DOUBLE_SUPPORT_ROM_V1 +#ifndef NDEBUG + movs r3, #0 + mov ip, r3 +#endif +#endif + ldr r3, =sd_table + ldr r3, [r3, #\SF_TABLE_OFFSET] + str r3, [sp, #4] + pop {r3, pc} +.endm + +.macro shimmable_table_tail_call SF_TABLE_OFFSET shim + push {r3, r4} + ldr r3, =sd_table + ldr r3, [r3, #\SF_TABLE_OFFSET] +#if PICO_DOUBLE_SUPPORT_ROM_V1 + mov ip, pc +#endif + str r3, [sp, #4] + pop {r3, pc} +#if PICO_DOUBLE_SUPPORT_ROM_V1 +.byte \SF_TABLE_OFFSET, 0xdf +.word \shim +#endif +.endm + +.macro double_wrapper_section func +double_section WRAPPER_FUNC_NAME(\func) +.endm + +double_section push_r8_r11 +regular_func push_r8_r11 + mov r4,r8 + mov r5,r9 + mov r6,r10 + mov r7,r11 + push {r4-r7} + bx r14 + +double_section pop_r8_r11 +regular_func pop_r8_r11 + pop {r4-r7} + mov r8,r4 + mov r9,r5 + mov r10,r6 + mov r11,r7 + bx r14 + +# note generally each function is in a separate section unless there is fall thru or branching between them +# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool + +# note functions are word aligned except where they are an odd number of linear instructions + +// double FUNC_NAME(__aeabi_dadd)(double, double) double-precision addition +double_wrapper_section __aeabi_darithmetic +// double FUNC_NAME(__aeabi_drsub)(double x, double y) double-precision reverse subtraction, y - x + +# frsub first because it is the only one that needs alignment +.align 2 +wrapper_func __aeabi_drsub + eors r0, r1 + eors r1, r0 + eors r0, r1 + // fall thru + +// double FUNC_NAME(__aeabi_dsub)(double x, double y) double-precision subtraction, x - y +wrapper_func_d2 __aeabi_dsub +#if PICO_DOUBLE_PROPAGATE_NANS + // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost + mov ip, r0 + mov r0, r1 + eors r0, r3 + bmi 1f // different signs + mov r0, ip + push {r0-r3, lr} + bl 2f + b ddiv_dsub_nan_helper +1: + mov r0, ip +2: +#endif + shimmable_table_tail_call SF_TABLE_FSUB dsub_shim + +wrapper_func_d2 __aeabi_dadd + shimmable_table_tail_call SF_TABLE_FADD dadd_shim + +// double FUNC_NAME(__aeabi_ddiv)(double n, double d) double-precision division, n / d +wrapper_func_d2 __aeabi_ddiv +#if PICO_DOUBLE_PROPAGATE_NANS + push {r0-r3, lr} + bl 1f + b ddiv_dsub_nan_helper +1: +#endif + shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim + +ddiv_dsub_nan_helper: +#if PICO_DOUBLE_PROPAGATE_NANS + // check for infinite op infinite (or rather check for infinite result with both + // operands being infinite) + lsls r2, r1, #1 + asrs r2, r2, #21 + adds r2, #1 + beq 2f + add sp, #16 + pop {pc} +2: + ldr r2, [sp, #4] + ldr r3, [sp, #12] + lsls r2, #1 + asrs r2, r2, #21 + lsls r3, #1 + asrs r3, r3, #24 + ands r2, r3 + adds r2, #1 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 +3: + add sp, #16 + pop {pc} +#endif + +// double FUNC_NAME(__aeabi_dmul)(double, double) double-precision multiplication +wrapper_func_d2 __aeabi_dmul +#if PICO_DOUBLE_PROPAGATE_NANS + push {r0-r3, lr} + bl 1f + + // check for multiplication of infinite by zero (or rather check for infinite result with either + // operand 0) + lsls r3, r1, #1 + asrs r3, r3, #21 + adds r3, #1 + beq 2f + add sp, #16 + pop {pc} +2: + ldr r2, [sp, #4] + ldr r3, [sp, #12] + ands r2, r3 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 +3: + add sp, #16 + pop {pc} +1: +#endif + shimmable_table_tail_call SF_TABLE_FMUL dmul_shim + +// void FUNC_NAME(__aeabi_cdrcmple)(double, double) reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags +double_wrapper_section __aeabi_cdcmple + +wrapper_func __aeabi_cdrcmple + push {r0-r7,r14} + eors r0, r2 + eors r2, r0 + eors r0, r2 + eors r1, r3 + eors r3, r1 + eors r1, r3 + b __aeabi_dfcmple_guts + +// NOTE these share an implementation as we have no excepting NaNs. +// void FUNC_NAME(__aeabi_cdcmple)(double, double) 3-way (<, =, ?>) compare [1], result in PSR ZC flags +// void FUNC_NAME(__aeabi_cdcmpeq)(double, double) non-excepting equality comparison [1], result in PSR ZC flags +@ compare r0:r1 against r2:r3, returning -1/0/1 for <, =, > +@ also set flags accordingly +.align 2 +wrapper_func __aeabi_cdcmple +wrapper_func __aeabi_cdcmpeq + push {r0-r7,r14} +__aeabi_dfcmple_guts: + ldr r7,=#0x7ff @ flush NaNs and denormals + lsls r4,r1,#1 + lsrs r4,#21 + beq 1f + cmp r4,r7 + bne 2f + lsls r4, r1, #12 + bhi 7f +1: + movs r0,#0 + lsrs r1,#20 + lsls r1,#20 +2: + lsls r4,r3,#1 + lsrs r4,#21 + beq 1f + cmp r4,r7 + bne 2f + lsls r4, r3, #12 + bhi 7f +1: + movs r2,#0 + lsrs r3,#20 + lsls r3,#20 +2: + movs r6,#1 + eors r3,r1 + bmi 4f @ opposite signs? then can proceed on basis of sign of x + eors r3,r1 @ restore r3 + bpl 2f + cmp r3,r1 + bne 7f +1: + cmp r2,r0 +7: + pop {r0-r7,r15} +2: + cmp r1,r3 + bne 7b +1: + cmp r0,r2 + pop {r0-r7,r15} +4: + orrs r3,r1 @ make -0==+0 + adds r3,r3 + orrs r3,r0 + orrs r3,r2 + beq 7b + mvns r1, r1 @ carry inverse of r1 sign + adds r1, r1 + pop {r0-r7,r15} + + +// int FUNC_NAME(__aeabi_dcmpeq)(double, double) result (1, 0) denotes (=, ?<>) [2], use for C == and != +double_wrapper_section __aeabi_dcmpeq +.align 2 +wrapper_func __aeabi_dcmpeq + push {lr} + bl __aeabi_cdcmpeq + beq 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_dcmplt)(double, double) result (1, 0) denotes (<, ?>=) [2], use for C < +double_wrapper_section __aeabi_dcmplt +.align 2 +wrapper_func __aeabi_dcmplt + push {lr} + bl __aeabi_cdcmple + sbcs r0, r0 + pop {pc} + +// int FUNC_NAME(__aeabi_dcmple)(double, double) result (1, 0) denotes (<=, ?>) [2], use for C <= +double_wrapper_section __aeabi_dcmple +.align 2 +wrapper_func __aeabi_dcmple + push {lr} + bl __aeabi_cdcmple + bls 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_dcmpge)(double, double) result (1, 0) denotes (>=, ?<) [2], use for C >= +double_wrapper_section __aeabi_dcmpge +.align 2 +wrapper_func __aeabi_dcmpge + push {lr} + // because of NaNs it is better to reverse the args than the result + bl __aeabi_cdrcmple + bls 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_dcmpgt)(double, double) result (1, 0) denotes (>, ?<=) [2], use for C > +double_wrapper_section __aeabi_dcmpgt +wrapper_func __aeabi_dcmpgt + push {lr} + // because of NaNs it is better to reverse the args than the result + bl __aeabi_cdrcmple + sbcs r0, r0 + pop {pc} + +// int FUNC_NAME(__aeabi_dcmpun)(double, double) result (1, 0) denotes (?, <=>) [2], use for C99 isunordered() +double_wrapper_section __aeabi_dcmpun +wrapper_func __aeabi_dcmpun + movs r0, #1 + lsls r0, #21 + lsls r2, r1, #1 + adds r2, r0 + bhi 1f + lsls r2, r3, #1 + adds r2, r0 + bhi 1f + movs r0, #0 + bx lr +1: + movs r0, #1 + bx lr + + movs r0, #0 + bx lr + +// double FUNC_NAME(__aeabi_ui2d)(unsigned) unsigned to double (double precision) conversion +double_wrapper_section __aeabi_ui2d + shimmable_table_tail_call SF_TABLE_UINT2FLOAT uint2double_shim + +double_wrapper_section __aeabi_i2d + +wrapper_func __aeabi_ui2d + movs r1, #0 + cmp r0, #0 + bne 2f +1: + bx lr +// double FUNC_NAME(__aeabi_i2d)(int) integer to double (double precision) conversion +wrapper_func __aeabi_i2d + asrs r1, r0, #31 + eors r0, r1 + subs r0, r1 + beq 1b + lsls r1, #31 +2: + push {r0, r1, r4, lr} + ldr r3, =sf_clz_func + ldr r3, [r3] + blx r3 + pop {r2, r3} + adds r4, r0, #1 + lsls r2, r4 + lsls r0, r2, #20 + lsrs r2, #12 + ldr r1,=#1055 + subs r1, r4 + lsls r1, #20 + orrs r1, r3 + orrs r1, r2 + pop {r4, pc} + +// int FUNC_NAME(__aeabi_d2iz)(double) double (double precision) to integer C-style conversion [3] +double_wrapper_section __aeabi_d2iz +wrapper_func __aeabi_d2iz +regular_func double2int_z + push {r4, lr} + lsls r4, r1, #1 + lsrs r2, r4, #21 + movs r3, #0x80 + adds r2, r3 + lsls r3, #3 + subs r2, r3 + lsls r3, #21 + cmp r2, #126 + ble 1f + subs r2, #158 + bge 2f + asrs r4, r1, #31 + lsls r1, #12 + lsrs r1, #1 + orrs r1, r3 + negs r2, r2 + lsrs r1, r2 + lsls r4, #1 + adds r4, #1 + adds r2, #21 + cmp r2, #32 + bge 3f + lsrs r0, r2 + orrs r0, r1 + muls r0, r4 + pop {r4, pc} +1: + movs r0, #0 + pop {r4, pc} +3: + mov r0, r1 + muls r0, r4 + pop {r4, pc} +2: + // overflow + lsrs r0, r1, #31 + adds r0, r3 + subs r0, #1 + pop {r4, pc} + +double_section double2int +regular_func double2int + shimmable_table_tail_call SF_TABLE_FLOAT2INT double2int_shim + +// unsigned FUNC_NAME(__aeabi_d2uiz)(double) double (double precision) to unsigned C-style conversion [3] +double_wrapper_section __aeabi_d2uiz +wrapper_func __aeabi_d2uiz +regular_func double2uint + shimmable_table_tail_call SF_TABLE_FLOAT2UINT double2uint_shim + +double_section fix2double +regular_func fix2double + shimmable_table_tail_call SF_TABLE_FIX2FLOAT fix2double_shim + +double_section ufix2double +regular_func ufix2double + shimmable_table_tail_call SF_TABLE_UFIX2FLOAT ufix2double_shim + +double_section fix642double +regular_func fix642double + shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642double_shim + +double_section ufix2double +regular_func ufix642double + shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642double_shim + +// double FUNC_NAME(__aeabi_l2d)(long long) long long to double (double precision) conversion +double_wrapper_section __aeabi_l2d +wrapper_func __aeabi_l2d + shimmable_table_tail_call SF_TABLE_INT642FLOAT int642double_shim + +// double FUNC_NAME(__aeabi_l2f)(long long) long long to double (double precision) conversion +double_wrapper_section __aeabi_ul2d +wrapper_func __aeabi_ul2d + shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642double_shim + +// long long FUNC_NAME(__aeabi_d2lz)(double) double (double precision) to long long C-style conversion [3] +double_wrapper_section __aeabi_d2lz +wrapper_func __aeabi_d2lz +regular_func double2int64_z + cmn r1, r1 + bcc double2int64 + push {lr} + lsls r1, #1 + lsrs r1, #1 + movs r2, #0 + bl double2ufix64 + cmp r1, #0 + bmi 1f + movs r2, #0 + rsbs r0, #0 + sbcs r2, r1 + mov r1, r2 + pop {pc} +1: + movs r1, #128 + lsls r1, #24 + movs r0, #0 + pop {pc} + +double_section double2int64 +regular_func double2int64 + shimmable_table_tail_call SF_TABLE_FLOAT2INT64 double2int64_shim + +// unsigned long long FUNC_NAME(__aeabi_d2ulz)(double) double to unsigned long long C-style conversion [3] +double_wrapper_section __aeabi_d2ulz +wrapper_func __aeabi_d2ulz + shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 double2uint64_shim + +double_section double2fix64 +regular_func double2fix64 + shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 double2fix64_shim + +double_section double2ufix64 +regular_func double2ufix64 + shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 double2ufix64_shim + +double_section double2fix +regular_func double2fix + shimmable_table_tail_call SF_TABLE_FLOAT2FIX double2fix_shim + +double_section double2ufix +regular_func double2ufix + shimmable_table_tail_call SF_TABLE_FLOAT2UFIX double2ufix_shim + +double_wrapper_section __aeabi_d2f +1: +#if PICO_DOUBLE_PROPAGATE_NANS + // copy sign bit and 23 NAN id bits into sign bit and significant id bits, also set high id bit + + lsrs r0, #30 + lsls r2, r1, #12 + lsrs r2, #9 + asrs r1, #22 + lsls r1, #22 + orrs r0, r1 + orrs r0, r2 + bx lr +#endif +wrapper_func __aeabi_d2f +#if PICO_DOUBLE_PROPAGATE_NANS + movs r3, #1 + lsls r3, #21 + lsls r2, r1, #1 + adds r2, r3 + bhi 1b +#endif + // note double->float in double table at same index as float->double in double table + shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE double2float_shim + +double_wrapper_section srqt +wrapper_func_d1 sqrt + shimmable_table_tail_call SF_TABLE_FSQRT dsqrt_shim + +double_wrapper_section sincostan_remainder +regular_func sincostan_remainder + ldr r2, =0x54442D18 // 2 * M_PI + ldr r3, =0x401921FB + push {lr} + bl remainder + pop {pc} + +double_wrapper_section cos +#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 +wrapper_func cos + // rom version only works for -1024 < angle < 1024 + lsls r2, r1, #2 + bcc 1f + lsrs r2, #22 + cmp r2, #9 + bge 2f +1: + shimmable_table_tail_call SF_TABLE_FCOS dcos_shim +2: +#if PICO_DOUBLE_PROPAGATE_NANS + lsls r2, r1, #1 + asrs r2, #21 + adds r2, #1 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 + bx lr +3: +#endif + push {lr} + bl sincostan_remainder + pop {r2} + mov lr, r2 + b 1b + +double_wrapper_section sin +#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 +wrapper_func sin + // rom version only works for -1024 < angle < 1024 + lsls r2, r1, #2 + bcc 1f + lsrs r2, #22 + cmp r2, #9 + bge 2f +1: + shimmable_table_tail_call SF_TABLE_FSIN dsin_shim +2: +#if PICO_DOUBLE_PROPAGATE_NANS + lsls r2, r1, #1 + asrs r2, #21 + adds r2, #1 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 + bx lr +3: +#endif + push {lr} + bl sincostan_remainder + pop {r2} + mov lr, r2 + b 1b + +double_wrapper_section sincos + // out of line remainder code for abs(angle)>=1024 +2: +#if PICO_DOUBLE_PROPAGATE_NANS + lsls r2, r1, #1 + asrs r2, #21 + adds r2, #1 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 + pop {r4-r5} + stmia r4!, {r0, r1} + stmia r5!, {r0, r1} + pop {r4, r5, pc} +3: +#endif + push {lr} + bl sincostan_remainder + pop {r2} + mov lr, r2 + b 1f + +wrapper_func sincos + push {r2-r5, lr} + // rom version only works for -1024 < angle < 1024 + lsls r2, r1, #2 + bcc 1f + lsrs r2, #22 + cmp r2, #9 + bge 2b +1: + + bl 2f + pop {r4-r5} + stmia r4!, {r0, r1} + stmia r5!, {r2, r3} + pop {r4, r5, pc} + +2: + shimmable_table_tail_call SF_TABLE_V3_FSINCOS sincos_shim_bootstrap +#if PICO_DOUBLE_PROPAGATE_NANS +.align 2 +1: + pop {r2, r3} + stmia r2!, {r0, r1} + mov lr, r3 + pop {r3} + stmia r3!, {r0, r1} + bx lr +#endif +.thumb_func +sincos_shim_bootstrap: + push {r2, r3, r4} + movs r3, #0x13 + ldrb r3, [r3] +#if PICO_DOUBLE_SUPPORT_ROM_V1 + cmp r3, #1 + bne 1f + ldr r3, =dsincos_shim + b 2f +#endif +1: + ldr r3, =dsincos_shim_v2 +2: + ldr r2, =sd_table + str r3, [r2, #SF_TABLE_V3_FSINCOS] + str r3, [sp, #8] + pop {r2, r3, pc} +.thumb_func +dsincos_shim_v2: + push {r4-r7,r14} + bl push_r8_r11 + bl v2_rom_dsincos_internal + mov r12,r0 @ save ε + bl v2_rom_dcos_finish + push {r0,r1} + mov r0,r12 + bl v2_rom_dsin_finish + pop {r2,r3} + bl pop_r8_r11 + pop {r4-r7,r15} +.thumb_func +v2_rom_dsincos_internal: + push {r0, lr} + ldr r0, =0x3855 + str r0, [sp, #4] + pop {r0, pc} +.thumb_func +v2_rom_dcos_finish: + push {r0, r1} + ldr r0, =0x389d + str r0, [sp, #4] + pop {r0, pc} +.thumb_func +v2_rom_dsin_finish: + push {r0, r1} + ldr r0, =0x38d9 + str r0, [sp, #4] + pop {r0, pc} + +double_wrapper_section tan +#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024 +wrapper_func tan + // rom version only works for -1024 < angle < 1024 + lsls r2, r1, #2 + bcc 1f + lsrs r2, #22 + cmp r2, #9 + bge 2f +1: + shimmable_table_tail_call SF_TABLE_FTAN dtan_shim +2: +#if PICO_DOUBLE_PROPAGATE_NANS + lsls r2, r1, #1 + asrs r2, #21 + adds r2, #1 + bne 3f + // infinite to nan + movs r2, #1 + lsls r2, #19 + orrs r1, r2 + bx lr +3: +#endif + push {lr} + bl sincostan_remainder + pop {r2} + mov lr, r2 + b 1b + +double_wrapper_section atan2 +wrapper_func_d2 atan2 + shimmable_table_tail_call SF_TABLE_FATAN2 datan2_shim + +double_wrapper_section exp +wrapper_func_d1 exp + shimmable_table_tail_call SF_TABLE_FEXP dexp_shim + +double_wrapper_section log +wrapper_func_d1 log + shimmable_table_tail_call SF_TABLE_FLN dln_shim + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c new file mode 100644 index 00000000000..82950b41500 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "pico/bootrom.h" +#include "pico/bootrom/sf_table.h" + +// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE... +// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE +uint32_t sd_table[SF_TABLE_V2_SIZE / 2]; + +#if !PICO_DOUBLE_SUPPORT_ROM_V1 +static __attribute__((noreturn)) void missing_double_func_shim() { + panic("missing double function"); +} +#endif +extern void double_table_shim_on_use_helper(); + +void __aeabi_double_init() { + int rom_version = rp2040_rom_version(); +#if PICO_DOUBLE_SUPPORT_ROM_V1 + if (rom_version == 1) { + + // this is a little tricky.. we only want to pull in a shim if the corresponding function + // is called. to that end we include a SVC instruction with the table offset as the call number + // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper + // function is garbage collected, so is the shim function. + // + // double_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address + // pointed to by IP and patches the double_table entry with the real shim the first time the function is called. + for(uint i=0; i= 2) { + void *rom_table = rom_data_lookup(rom_table_code('S', 'D')); + assert(*((uint8_t *)(((void *)rom_data_lookup(rom_table_code('S', 'F')))-2)) * 4 >= SF_TABLE_V2_SIZE); + memcpy(&sd_table, rom_table, SF_TABLE_V2_SIZE); + if (rom_version == 2) { +#ifndef NDEBUG + if (*(uint16_t *)0x3854 != 0xb500 || // this is dsincos(_internal) + + *(uint16_t *)0x38d8 != 0x4649 || // this is dsin_finish + *(uint16_t *)0x389c != 0x4659 // this is dcos_finish + ) { + panic(NULL); + } +#endif + } + } + if (rom_version < 3) { + // we use the unused entry for SINCOS + sd_table[SF_TABLE_V3_FSINCOS / 4] = (uintptr_t) double_table_shim_on_use_helper; + } +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c new file mode 100644 index 00000000000..41d4380e7c8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "pico/types.h" +#include "pico/double.h" +#include "pico/platform.h" + +typedef uint64_t ui64; +typedef uint32_t ui32; +typedef int64_t i64; + +#define PINF ( HUGE_VAL) +#define MINF (-HUGE_VAL) +#define PZERO (+0.0) +#define MZERO (-0.0) + + +#define PI 3.14159265358979323846 +#define LOG2 0.69314718055994530941 +// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers +#define LOG10 2.30258509299404568401 +#define LOG2E 1.44269504088896340737 +#define LOG10E 0.43429448190325182765 +#define ONETHIRD 0.33333333333333333333 + +#define PIf 3.14159265358979323846f +#define LOG2f 0.69314718055994530941f +#define LOG2Ef 1.44269504088896340737f +#define LOG10Ef 0.43429448190325182765f +#define ONETHIRDf 0.33333333333333333333f + +#define DUNPACK(x,e,m) e=((x)>>52)&0x7ff,m=((x)&0x000fffffffffffffULL)|0x0010000000000000ULL +#define DUNPACKS(x,s,e,m) s=((x)>>63),DUNPACK((x),(e),(m)) + +_Pragma("GCC diagnostic push") +_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"") + +static inline bool disnan(double x) { + ui64 ix=*(i64*)&x; + // checks the top bit of the low 32 bit of the NAN, but it I think that is ok + return ((uint32_t)(ix >> 31)) > 0xffe00000u; +} + +#if PICO_DOUBLE_PROPAGATE_NANS +#define check_nan_d1(x) if (disnan((x))) return (x) +#define check_nan_d2(x,y) if (disnan((x))) return (x); else if (disnan((y))) return (y); +#else +#define check_nan_d1(x) ((void)0) +#define check_nan_d2(x,y) ((void)0) +#endif + +static inline int dgetsignexp(double x) { + ui64 ix=*(ui64*)&x; + return (ix>>52)&0xfff; +} + +static inline int dgetexp(double x) { + ui64 ix=*(ui64*)&x; + return (ix>>52)&0x7ff; +} + +static inline double dldexp(double x,int de) { + ui64 ix=*(ui64*)&x,iy; + int e; + e=dgetexp(x); + if(e==0||e==0x7ff) return x; + e+=de; + if(e<=0) iy=ix&0x8000000000000000ULL; // signed zero for underflow + else if(e>=0x7ff) iy=(ix&0x8000000000000000ULL)|0x7ff0000000000000ULL; // signed infinity on overflow + else iy=ix+((ui64)de<<52); + return *(double*)&iy; +} + +double WRAPPER_FUNC(ldexp)(double x, int de) { + check_nan_d1(x); + return dldexp(x, de); +} + + +static inline double dcopysign(double x,double y) { + ui64 ix=*(ui64*)&x,iy=*(ui64*)&y; + ix=((ix&0x7fffffffffffffffULL)|(iy&0x8000000000000000ULL)); + return *(double*)&ix; +} + +double WRAPPER_FUNC(copysign)(double x, double y) { + check_nan_d2(x,y); + return dcopysign(x, y); +} +static inline int diszero(double x) { return dgetexp (x)==0; } +static inline int dispzero(double x) { return dgetsignexp(x)==0; } +static inline int dismzero(double x) { return dgetsignexp(x)==0x800; } +static inline int disinf(double x) { return dgetexp (x)==0x7ff; } +static inline int dispinf(double x) { return dgetsignexp(x)==0x7ff; } +static inline int disminf(double x) { return dgetsignexp(x)==0xfff; } + +static inline int disint(double x) { + ui64 ix=*(ui64*)&x,m; + int e=dgetexp(x); + if(e==0) return 1; // 0 is an integer + e-=0x3ff; // remove exponent bias + if(e<0) return 0; // |x|<1 + e=52-e; // bit position in mantissa with significance 1 + if(e<=0) return 1; // |x| large, so must be an integer + m=(1ULL<>e)&1; +} + +static inline int disstrictneg(double x) { + ui64 ix=*(ui64*)&x; + if(diszero(x)) return 0; + return ix>>63; +} + +static inline int disneg(double x) { + ui64 ix=*(ui64*)&x; + return ix>>63; +} + +static inline double dneg(double x) { + ui64 ix=*(ui64*)&x; + ix^=0x8000000000000000ULL; + return *(double*)&ix; +} + +static inline int dispo2(double x) { + ui64 ix=*(ui64*)&x; + if(diszero(x)) return 0; + if(disinf(x)) return 0; + ix&=0x000fffffffffffffULL; + return ix==0; +} + +static inline double dnan_or(double x) { +#if PICO_DOUBLE_PROPAGATE_NANS + return NAN; +#else + return x; +#endif +} + +double WRAPPER_FUNC(trunc)(double x) { + check_nan_d1(x); + ui64 ix=*(ui64*)&x,m; + int e=dgetexp(x); + e-=0x3ff; // remove exponent bias + if(e<0) { // |x|<1 + ix&=0x8000000000000000ULL; + return *(double*)&ix; + } + e=52-e; // bit position in mantissa with significance 1 + if(e<=0) return x; // |x| large, so must be an integer + m=(1ULL<=5+0x3ff) { // |x|>=32? + if(!disneg(x)) return 1; // 1 << exp 2x; avoid generating infinities later + else return -1; // 1 >> exp 2x + } + u=exp(dldexp(x,1)); + return (u-1)/(u+1); +} + +double WRAPPER_FUNC(asinh)(double x) { + check_nan_d1(x); + int e; + e=dgetexp(x); + if(e>=32+0x3ff) { // |x|>=2^32? + if(!disneg(x)) return log( x )+LOG2; // 1/x^2 << 1 + else return dneg(log(dneg(x))+LOG2); // 1/x^2 << 1 + } + if(x>0) return log(sqrt(x*x+1)+x); + else return dneg(log(sqrt(x*x+1)-x)); +} + +double WRAPPER_FUNC(acosh)(double x) { + check_nan_d1(x); + int e; + if(disneg(x)) x=dneg(x); + e=dgetexp(x); + if(e>=32+0x3ff) return log(x)+LOG2; // |x|>=2^32? + return log(sqrt((x-1)*(x+1))+x); +} + +double WRAPPER_FUNC(atanh)(double x) { + check_nan_d1(x); + return dldexp(log((1+x)/(1-x)),-1); +} + +double WRAPPER_FUNC(exp2)(double x) { + check_nan_d1(x); + int e; + // extra check for disminf as this catches -Nan, and x<=-4096 doesn't. + if (disminf(x) || x<=-4096) return 0; // easily underflows + else if (x>=4096) return PINF; // easily overflows + e=(int)round(x); + x-=e; + return dldexp(exp(x*LOG2),e); +} +double WRAPPER_FUNC(log2)(double x) { check_nan_d1(x); return log(x)*LOG2E; } +double WRAPPER_FUNC(exp10)(double x) { check_nan_d1(x); return pow(10,x); } +double WRAPPER_FUNC(log10)(double x) { check_nan_d1(x); return log(x)*LOG10E; } + +// todo these are marked as lofi +double WRAPPER_FUNC(expm1(double x) { check_nan_d1(x); return exp)(x)-1; } +double WRAPPER_FUNC(log1p(double x) { check_nan_d1(x); return log)(1+x); } +double WRAPPER_FUNC(fma)(double x,double y,double z) { check_nan_d1(x); return x*y+z; } + +// general power, x>0, finite +static double dpow_1(double x,double y) { + int a,b,c; + double t,rt,u,v,v0,v1,w,ry; + a=dgetexp(x)-0x3ff; + u=log2(dldexp(x,-a)); // now log_2 x = a+u + if(u>0.5) u-=1,a++; // |u|<=~0.5 + if(a==0) return exp2(u*y); + // here |log_2 x| >~0.5 + if(y>= 4096) { // then easily over/underflows + if(a<0) return 0; + return PINF; + } + if(y<=-4096) { // then easily over/underflows + if(a<0) return PINF; + return 0; + } + ry=round(y); + v=y-ry; + v0=dldexp(round(ldexp(v,26)),-26); + v1=v-v0; + b=(int)ry; // guaranteed to fit in an int; y=b+v0+v1 + // now the result is exp2( (a+u) * (b+v0+v1) ) + c=a*b; // integer + t=a*v0; + rt=round(t); + c+=(int)rt; + w=t-rt; + t=a*v1; + w+=t; + t=u*b; + rt=round(t); + c+=(int)rt; + w+=t-rt; + w+=u*v; + return dldexp(exp2(w),c); +} + +static double dpow_int2(double x,int y) { + double u; + if(y==1) return x; + u=dpow_int2(x,y/2); + u*=u; + if(y&1) u*=x; + return u; +} + +// for the case where x not zero or infinity, y small and not zero +static inline double dpowint_1(double x,int y) { + if(y<0) x=1/x,y=-y; + return dpow_int2(x,y); +} + +// for the case where x not zero or infinity +static double dpowint_0(double x,int y) { + int e; + if(disneg(x)) { + if(disoddint(y)) return dneg(dpowint_0(dneg(x),y)); + else return dpowint_0(dneg(x),y); + } + if(dispo2(x)) { + e=dgetexp(x)-0x3ff; + if(y>=2048) y= 2047; // avoid overflow + if(y<-2048) y=-2048; + y*=e; + return dldexp(1,y); + } + if(y==0) return 1; + if(y>=-32&&y<=32) return dpowint_1(x,y); + return dpow_1(x,y); +} + +double WRAPPER_FUNC(powint)(double x,int y) { + _Pragma("GCC diagnostic push") + _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") + if(x==1.0||y==0) return 1; + _Pragma("GCC diagnostic pop") + check_nan_d1(x); + if(diszero(x)) { + if(y>0) { + if(y&1) return x; + else return 0; + } + if((y&1)) return dcopysign(PINF,x); + return PINF; + } + if(dispinf(x)) { + if(y<0) return 0; + else return PINF; + } + if(disminf(x)) { + if(y>0) { + if((y&1)) return MINF; + else return PINF; + } + if((y&1)) return MZERO; + else return PZERO; + } + return dpowint_0(x,y); +} + +// for the case where y is guaranteed a finite integer, x not zero or infinity +static double dpow_0(double x,double y) { + int e,p; + if(disneg(x)) { + if(disoddint(y)) return dneg(dpow_0(dneg(x),y)); + else return dpow_0(dneg(x),y); + } + p=(int)y; + if(dispo2(x)) { + e=dgetexp(x)-0x3ff; + if(p>=2048) p= 2047; // avoid overflow + if(p<-2048) p=-2048; + p*=e; + return dldexp(1,p); + } + if(p==0) return 1; + if(p>=-32&&p<=32) return dpowint_1(x,p); + return dpow_1(x,y); +} + +double WRAPPER_FUNC(pow)(double x,double y) { + _Pragma("GCC diagnostic push") + _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") + + if(x==1.0||diszero(y)) return 1; + check_nan_d2(x, y); + if(x==-1.0&&disinf(y)) return 1; + _Pragma("GCC diagnostic pop") + + if(diszero(x)) { + if(!disneg(y)) { + if(disoddint(y)) return x; + else return 0; + } + if(disoddint(y)) return dcopysign(PINF,x); + return PINF; + } + if(dispinf(x)) { + if(disneg(y)) return 0; + else return PINF; + } + if(disminf(x)) { + if(!disneg(y)) { + if(disoddint(y)) return MINF; + else return PINF; + } + if(disoddint(y)) return MZERO; + else return PZERO; + } + if(dispinf(y)) { + if(dgetexp(x)<0x3ff) return PZERO; + else return PINF; + } + if(disminf(y)) { + if(dgetexp(x)<0x3ff) return PINF; + else return PZERO; + } + if(disint(y)) return dpow_0(x,y); + if(disneg(x)) return PINF; + return dpow_1(x,y); +} + +double WRAPPER_FUNC(hypot)(double x,double y) { + check_nan_d2(x, y); + int ex,ey; + ex=dgetexp(x); ey=dgetexp(y); + if(ex>=0x3ff+400||ey>=0x3ff+400) { // overflow, or nearly so + x=dldexp(x,-600),y=dldexp(y,-600); + return dldexp(sqrt(x*x+y*y), 600); + } + else if(ex<=0x3ff-400&&ey<=0x3ff-400) { // underflow, or nearly so + x=dldexp(x, 600),y=dldexp(y, 600); + return dldexp(sqrt(x*x+y*y),-600); + } + return sqrt(x*x+y*y); +} + +double WRAPPER_FUNC(cbrt)(double x) { + check_nan_d1(x); + int e; + if(disneg(x)) return dneg(cbrt(dneg(x))); + if(diszero(x)) return dcopysign(PZERO,x); + e=dgetexp(x)-0x3ff; + e=(e*0x5555+0x8000)>>16; // ~e/3, rounded + x=dldexp(x,-e*3); + x=exp(log(x)*ONETHIRD); + return dldexp(x,e); +} + +// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo +// 2^52<=|mx|,my<2^53, e>=0; 0<=result0) { + r=0xffffffffU/(ui32)(my>>36); // reciprocal estimate Q16 + } + while(e>0) { + s=e; if(s>12) s=12; // gain up to 12 bits on each iteration + q=(mx>>38)*r; // Q30 + q=((q>>(29-s))+1)>>1; // Q(s), rounded + mx=(mx<=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my + if(mx>=my) mx-=my,quo++; + if(mx<0) mx+=my,quo--; + if(mx<0) mx+=my,quo--; + if(pquo) *pquo=quo; + return mx; +} + +double WRAPPER_FUNC(fmod)(double x,double y) { + check_nan_d2(x, y); + ui64 ix=*(ui64*)&x,iy=*(ui64*)&y; + int sx,ex,ey; + i64 mx,my; + DUNPACKS(ix,sx,ex,mx); + DUNPACK(iy,ey,my); + if(ex==0x7ff) return dnan_or(PINF); + if(ey==0) return PINF; + if(ex==0) { + if(!disneg(x)) return PZERO; + return MZERO; + } + if(ex|y|/2 + mx-=my+my; + ey--; + q=1; + } else { // x<-|y|/2 + mx=my+my-mx; + ey--; + q=-1; + } + } + else { + if(sx) mx=-mx; + mx=drem_0(mx,my,ex-ey,&q); + if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient? + mx-=my; + q++; + } + } + if(sy) q=-q; + if(quo) *quo=q; + return fix642double(mx,0x3ff-ey+52); +} + +double WRAPPER_FUNC(drem)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); } + +double WRAPPER_FUNC(remainder)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); } + +_Pragma("GCC diagnostic pop") // strict-aliasing \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_none.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_none.S new file mode 100644 index 00000000000..feded31cb6b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_none.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "pico/bootrom/sf_table.h" + +.syntax unified +.cpu cortex-m0plus +.thumb + + wrapper_func __aeabi_dadd + wrapper_func __aeabi_ddiv + wrapper_func __aeabi_dmul + wrapper_func __aeabi_drsub + wrapper_func __aeabi_dsub + wrapper_func __aeabi_cdcmpeq + wrapper_func __aeabi_cdrcmple + wrapper_func __aeabi_cdcmple + wrapper_func __aeabi_dcmpeq + wrapper_func __aeabi_dcmplt + wrapper_func __aeabi_dcmple + wrapper_func __aeabi_dcmpge + wrapper_func __aeabi_dcmpgt + wrapper_func __aeabi_dcmpun + wrapper_func __aeabi_i2d + wrapper_func __aeabi_l2d + wrapper_func __aeabi_ui2d + wrapper_func __aeabi_ul2d + wrapper_func __aeabi_d2iz + wrapper_func __aeabi_d2lz + wrapper_func __aeabi_d2uiz + wrapper_func __aeabi_d2ulz + wrapper_func __aeabi_d2f + wrapper_func sqrt + wrapper_func cos + wrapper_func sin + wrapper_func tan + wrapper_func atan2 + wrapper_func exp + wrapper_func log + + wrapper_func ldexp + wrapper_func copysign + wrapper_func trunc + wrapper_func floor + wrapper_func ceil + wrapper_func round + wrapper_func sincos + wrapper_func asin + wrapper_func acos + wrapper_func atan + wrapper_func sinh + wrapper_func cosh + wrapper_func tanh + wrapper_func asinh + wrapper_func acosh + wrapper_func atanh + wrapper_func exp2 + wrapper_func log2 + wrapper_func exp10 + wrapper_func log10 + wrapper_func pow + wrapper_func powint + wrapper_func hypot + wrapper_func cbrt + wrapper_func fmod + wrapper_func drem + wrapper_func remainder + wrapper_func remquo + wrapper_func expm1 + wrapper_func log1p + wrapper_func fma + + push {lr} // keep stack trace sane + ldr r0, =str + bl panic + +str: + .asciz "double support is disabled" \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_v1_rom_shim.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_v1_rom_shim.S new file mode 100644 index 00000000000..63e7be32dc8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_v1_rom_shim.S @@ -0,0 +1,2184 @@ +/** + * Copyright (c) 2020 Mark Owen https://www.quinapalus.com . + * + * Raspberry Pi (Trading) Ltd (Licensor) hereby grants to you a non-exclusive license to use the software solely on a + * Raspberry Pi Pico device. No other use is permitted under the terms of this license. + * + * This software is also available from the copyright owner under GPLv2 licence. + * + * THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "pico/asm_helper.S" + +.syntax unified +.cpu cortex-m0plus +.thumb + +.macro double_section name +// todo separate flag for shims? +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +double_section double_table_shim_on_use_helper +regular_func double_table_shim_on_use_helper + push {r0-r2, lr} + mov r0, ip +#ifndef NDEBUG + // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro + cmp r0, #0 + bne 1f + bkpt #0 +#endif +1: + ldrh r1, [r0] + lsrs r2, r1, #8 + adds r0, #2 + cmp r2, #0xdf + bne 1b + uxtb r1, r1 // r1 holds table offset + lsrs r2, r0, #2 + bcc 1f + // unaligned + ldrh r2, [r0, #0] + ldrh r0, [r0, #2] + lsls r0, #16 + orrs r0, r2 + b 2f +1: + ldr r0, [r0] +2: + ldr r2, =sd_table + str r0, [r2, r1] + str r0, [sp, #12] + pop {r0-r2, pc} + +#if PICO_DOUBLE_SUPPORT_ROM_V1 +// Note that the V1 ROM has no double support, so this is basically the identical +// library, and shim inter-function calls do not bother to redirect back thru the +// wrapper functions + +.equ use_hw_div,1 +.equ IOPORT ,0xd0000000 +.equ DIV_UDIVIDEND,0x00000060 +.equ DIV_UDIVISOR ,0x00000064 +.equ DIV_QUOTIENT ,0x00000070 +.equ DIV_CSR ,0x00000078 + +@ Notation: +@ rx:ry means the concatenation of rx and ry with rx having the less significant bits + +.equ debug,0 +.macro mdump k +.if debug + push {r0-r3} + push {r14} + push {r0-r3} + bl osp + movs r0,#\k + bl o1ch + pop {r0-r3} + bl dump + bl osp + bl osp + ldr r0,[r13] + bl o8hex @ r14 + bl onl + pop {r0} + mov r14,r0 + pop {r0-r3} +.endif +.endm + + +@ IEEE double in ra:rb -> +@ mantissa in ra:rb 12Q52 (53 significant bits) with implied 1 set +@ exponent in re +@ sign in rs +@ trashes rt +.macro mdunpack ra,rb,re,rs,rt + lsrs \re,\rb,#20 @ extract sign and exponent + subs \rs,\re,#1 + lsls \rs,#20 + subs \rb,\rs @ clear sign and exponent in mantissa; insert implied 1 + lsrs \rs,\re,#11 @ sign + lsls \re,#21 + lsrs \re,#21 @ exponent + beq l\@_1 @ zero exponent? + adds \rt,\re,#1 + lsrs \rt,#11 + beq l\@_2 @ exponent != 0x7ff? then done +l\@_1: + movs \ra,#0 + movs \rb,#1 + lsls \rb,#20 + subs \re,#128 + lsls \re,#12 +l\@_2: +.endm + +@ IEEE double in ra:rb -> +@ signed mantissa in ra:rb 12Q52 (53 significant bits) with implied 1 +@ exponent in re +@ trashes rt0 and rt1 +@ +zero, +denormal -> exponent=-0x80000 +@ -zero, -denormal -> exponent=-0x80000 +@ +Inf, +NaN -> exponent=+0x77f000 +@ -Inf, -NaN -> exponent=+0x77e000 +.macro mdunpacks ra,rb,re,rt0,rt1 + lsrs \re,\rb,#20 @ extract sign and exponent + lsrs \rt1,\rb,#31 @ sign only + subs \rt0,\re,#1 + lsls \rt0,#20 + subs \rb,\rt0 @ clear sign and exponent in mantissa; insert implied 1 + lsls \re,#21 + bcc l\@_1 @ skip on positive + mvns \rb,\rb @ negate mantissa + rsbs \ra,#0 + bcc l\@_1 + adds \rb,#1 +l\@_1: + lsrs \re,#21 + beq l\@_2 @ zero exponent? + adds \rt0,\re,#1 + lsrs \rt0,#11 + beq l\@_3 @ exponent != 0x7ff? then done + subs \re,\rt1 +l\@_2: + movs \ra,#0 + lsls \rt1,#1 @ +ve: 0 -ve: 2 + adds \rb,\rt1,#1 @ +ve: 1 -ve: 3 + lsls \rb,#30 @ create +/-1 mantissa + asrs \rb,#10 + subs \re,#128 + lsls \re,#12 +l\@_3: +.endm + +double_section WRAPPER_FUNC_NAME(__aeabi_dsub) + +# frsub first because it is the only one that needs alignment +regular_func drsub_shim + push {r0-r3} + pop {r0-r1} + pop {r2-r3} + // fall thru + +regular_func dsub_shim + push {r4-r7,r14} + movs r4,#1 + lsls r4,#31 + eors r3,r4 @ flip sign on second argument + b da_entry @ continue in dadd + +.align 2 +double_section dadd_shim +regular_func dadd_shim + push {r4-r7,r14} +da_entry: + mdunpacks r0,r1,r4,r6,r7 + mdunpacks r2,r3,r5,r6,r7 + subs r7,r5,r4 @ ye-xe + subs r6,r4,r5 @ xe-ye + bmi da_ygtx +@ here xe>=ye: need to shift y down r6 places + mov r12,r4 @ save exponent + cmp r6,#32 + bge da_xrgty @ xe rather greater than ye? + adds r7,#32 + movs r4,r2 + lsls r4,r4,r7 @ rounding bit + sticky bits +da_xgty0: + movs r5,r3 + lsls r5,r5,r7 + lsrs r2,r6 + asrs r3,r6 + orrs r2,r5 +da_add: + adds r0,r2 + adcs r1,r3 +da_pack: +@ here unnormalised signed result (possibly 0) is in r0:r1 with exponent r12, rounding + sticky bits in r4 +@ Note that if a large normalisation shift is required then the arguments were close in magnitude and so we +@ cannot have not gone via the xrgty/yrgtx paths. There will therefore always be enough high bits in r4 +@ to provide a correct continuation of the exact result. +@ now pack result back up + lsrs r3,r1,#31 @ get sign bit + beq 1f @ skip on positive + mvns r1,r1 @ negate mantissa + mvns r0,r0 + movs r2,#0 + rsbs r4,#0 + adcs r0,r2 + adcs r1,r2 +1: + mov r2,r12 @ get exponent + lsrs r5,r1,#21 + bne da_0 @ shift down required? + lsrs r5,r1,#20 + bne da_1 @ normalised? + cmp r0,#0 + beq da_5 @ could mantissa be zero? +da_2: + adds r4,r4 + adcs r0,r0 + adcs r1,r1 + subs r2,#1 @ adjust exponent + lsrs r5,r1,#20 + beq da_2 +da_1: + lsls r4,#1 @ check rounding bit + bcc da_3 +da_4: + adds r0,#1 @ round up + bcc 2f + adds r1,#1 +2: + cmp r4,#0 @ sticky bits zero? + bne da_3 + lsrs r0,#1 @ round to even + lsls r0,#1 +da_3: + subs r2,#1 + bmi da_6 + adds r4,r2,#2 @ check if exponent is overflowing + lsrs r4,#11 + bne da_7 + lsls r2,#20 @ pack exponent and sign + add r1,r2 + lsls r3,#31 + add r1,r3 + pop {r4-r7,r15} + +da_7: +@ here exponent overflow: return signed infinity + lsls r1,r3,#31 + ldr r3,=#0x7ff00000 + orrs r1,r3 + b 1f +da_6: +@ here exponent underflow: return signed zero + lsls r1,r3,#31 +1: + movs r0,#0 + pop {r4-r7,r15} + +da_5: +@ here mantissa could be zero + cmp r1,#0 + bne da_2 + cmp r4,#0 + bne da_2 +@ inputs must have been of identical magnitude and opposite sign, so return +0 + pop {r4-r7,r15} + +da_0: +@ here a shift down by one place is required for normalisation + adds r2,#1 @ adjust exponent + lsls r6,r0,#31 @ save rounding bit + lsrs r0,#1 + lsls r5,r1,#31 + orrs r0,r5 + lsrs r1,#1 + cmp r6,#0 + beq da_3 + b da_4 + +da_xrgty: @ xe>ye and shift>=32 places + cmp r6,#60 + bge da_xmgty @ xe much greater than ye? + subs r6,#32 + adds r7,#64 + + movs r4,r2 + lsls r4,r4,r7 @ these would be shifted off the bottom of the sticky bits + beq 1f + movs r4,#1 +1: + lsrs r2,r2,r6 + orrs r4,r2 + movs r2,r3 + lsls r3,r3,r7 + orrs r4,r3 + asrs r3,r2,#31 @ propagate sign bit + b da_xgty0 + +da_ygtx: +@ here ye>xe: need to shift x down r7 places + mov r12,r5 @ save exponent + cmp r7,#32 + bge da_yrgtx @ ye rather greater than xe? + adds r6,#32 + movs r4,r0 + lsls r4,r4,r6 @ rounding bit + sticky bits +da_ygtx0: + movs r5,r1 + lsls r5,r5,r6 + lsrs r0,r7 + asrs r1,r7 + orrs r0,r5 + b da_add + +da_yrgtx: + cmp r7,#60 + bge da_ymgtx @ ye much greater than xe? + subs r7,#32 + adds r6,#64 + + movs r4,r0 + lsls r4,r4,r6 @ these would be shifted off the bottom of the sticky bits + beq 1f + movs r4,#1 +1: + lsrs r0,r0,r7 + orrs r4,r0 + movs r0,r1 + lsls r1,r1,r6 + orrs r4,r1 + asrs r1,r0,#31 @ propagate sign bit + b da_ygtx0 + +da_ymgtx: @ result is just y + movs r0,r2 + movs r1,r3 +da_xmgty: @ result is just x + movs r4,#0 @ clear sticky bits + b da_pack + +.ltorg + +@ equivalent of UMULL +@ needs five temporary registers +@ can have rt3==rx, in which case rx trashed +@ can have rt4==ry, in which case ry trashed +@ can have rzl==rx +@ can have rzh==ry +@ can have rzl,rzh==rt3,rt4 +.macro mul32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 + @ t0 t1 t2 t3 t4 + @ (x) (y) + uxth \rt0,\rx @ xl + uxth \rt1,\ry @ yl + muls \rt0,\rt1 @ xlyl=L + lsrs \rt2,\rx,#16 @ xh + muls \rt1,\rt2 @ xhyl=M0 + lsrs \rt4,\ry,#16 @ yh + muls \rt2,\rt4 @ xhyh=H + uxth \rt3,\rx @ xl + muls \rt3,\rt4 @ xlyh=M1 + adds \rt1,\rt3 @ M0+M1=M + bcc l\@_1 @ addition of the two cross terms can overflow, so add carry into H + movs \rt3,#1 @ 1 + lsls \rt3,#16 @ 0x10000 + adds \rt2,\rt3 @ H' +l\@_1: + @ t0 t1 t2 t3 t4 + @ (zl) (zh) + lsls \rzl,\rt1,#16 @ ML + lsrs \rzh,\rt1,#16 @ MH + adds \rzl,\rt0 @ ZL + adcs \rzh,\rt2 @ ZH +.endm + +@ SUMULL: x signed, y unsigned +@ in table below ¯ means signed variable +@ needs five temporary registers +@ can have rt3==rx, in which case rx trashed +@ can have rt4==ry, in which case ry trashed +@ can have rzl==rx +@ can have rzh==ry +@ can have rzl,rzh==rt3,rt4 +.macro muls32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 + @ t0 t1 t2 t3 t4 + @ ¯(x) (y) + uxth \rt0,\rx @ xl + uxth \rt1,\ry @ yl + muls \rt0,\rt1 @ xlyl=L + asrs \rt2,\rx,#16 @ ¯xh + muls \rt1,\rt2 @ ¯xhyl=M0 + lsrs \rt4,\ry,#16 @ yh + muls \rt2,\rt4 @ ¯xhyh=H + uxth \rt3,\rx @ xl + muls \rt3,\rt4 @ xlyh=M1 + asrs \rt4,\rt1,#31 @ M0sx (M1 sign extension is zero) + adds \rt1,\rt3 @ M0+M1=M + movs \rt3,#0 @ 0 + adcs \rt4,\rt3 @ ¯Msx + lsls \rt4,#16 @ ¯Msx<<16 + adds \rt2,\rt4 @ H' + + @ t0 t1 t2 t3 t4 + @ (zl) (zh) + lsls \rzl,\rt1,#16 @ M~ + lsrs \rzh,\rt1,#16 @ M~ + adds \rzl,\rt0 @ ZL + adcs \rzh,\rt2 @ ¯ZH +.endm + +@ SSMULL: x signed, y signed +@ in table below ¯ means signed variable +@ needs five temporary registers +@ can have rt3==rx, in which case rx trashed +@ can have rt4==ry, in which case ry trashed +@ can have rzl==rx +@ can have rzh==ry +@ can have rzl,rzh==rt3,rt4 +.macro muls32_s32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4 + @ t0 t1 t2 t3 t4 + @ ¯(x) (y) + uxth \rt0,\rx @ xl + uxth \rt1,\ry @ yl + muls \rt0,\rt1 @ xlyl=L + asrs \rt2,\rx,#16 @ ¯xh + muls \rt1,\rt2 @ ¯xhyl=M0 + asrs \rt4,\ry,#16 @ ¯yh + muls \rt2,\rt4 @ ¯xhyh=H + uxth \rt3,\rx @ xl + muls \rt3,\rt4 @ ¯xlyh=M1 + adds \rt1,\rt3 @ ¯M0+M1=M + asrs \rt3,\rt1,#31 @ Msx + bvc l\@_1 @ + mvns \rt3,\rt3 @ ¯Msx flip sign extension bits if overflow +l\@_1: + lsls \rt3,#16 @ ¯Msx<<16 + adds \rt2,\rt3 @ H' + + @ t0 t1 t2 t3 t4 + @ (zl) (zh) + lsls \rzl,\rt1,#16 @ M~ + lsrs \rzh,\rt1,#16 @ M~ + adds \rzl,\rt0 @ ZL + adcs \rzh,\rt2 @ ¯ZH +.endm + +@ can have rt2==rx, in which case rx trashed +@ can have rzl==rx +@ can have rzh==rt1 +.macro square32_64 rx,rzl,rzh,rt0,rt1,rt2 + @ t0 t1 t2 zl zh + uxth \rt0,\rx @ xl + muls \rt0,\rt0 @ xlxl=L + uxth \rt1,\rx @ xl + lsrs \rt2,\rx,#16 @ xh + muls \rt1,\rt2 @ xlxh=M + muls \rt2,\rt2 @ xhxh=H + lsls \rzl,\rt1,#17 @ ML + lsrs \rzh,\rt1,#15 @ MH + adds \rzl,\rt0 @ ZL + adcs \rzh,\rt2 @ ZH +.endm + +double_section dmul_shim + regular_func dmul_shim + push {r4-r7,r14} + mdunpack r0,r1,r4,r6,r5 + mov r12,r4 + mdunpack r2,r3,r4,r7,r5 + eors r7,r6 @ sign of result + add r4,r12 @ exponent of result + push {r0-r2,r4,r7} + +@ accumulate full product in r12:r5:r6:r7 + mul32_32_64 r0,r2, r0,r5, r4,r6,r7,r0,r5 @ XL*YL + mov r12,r0 @ save LL bits + + mul32_32_64 r1,r3, r6,r7, r0,r2,r4,r6,r7 @ XH*YH + + pop {r0} @ XL + mul32_32_64 r0,r3, r0,r3, r1,r2,r4,r0,r3 @ XL*YH + adds r5,r0 + adcs r6,r3 + movs r0,#0 + adcs r7,r0 + + pop {r1,r2} @ XH,YL + mul32_32_64 r1,r2, r1,r2, r0,r3,r4, r1,r2 @ XH*YL + adds r5,r1 + adcs r6,r2 + movs r0,#0 + adcs r7,r0 + +@ here r5:r6:r7 holds the product [1..4) in Q(104-32)=Q72, with extra LSBs in r12 + pop {r3,r4} @ exponent in r3, sign in r4 + lsls r1,r7,#11 + lsrs r2,r6,#21 + orrs r1,r2 + lsls r0,r6,#11 + lsrs r2,r5,#21 + orrs r0,r2 + lsls r5,#11 @ now r5:r0:r1 Q83=Q(51+32), extra LSBs in r12 + lsrs r2,r1,#20 + bne 1f @ skip if in range [2..4) + adds r5,r5 @ shift up so always [2..4) Q83, i.e. [1..2) Q84=Q(52+32) + adcs r0,r0 + adcs r1,r1 + subs r3,#1 @ correct exponent +1: + ldr r6,=#0x3ff + subs r3,r6 @ correct for exponent bias + lsls r6,#1 @ 0x7fe + cmp r3,r6 + bhs dm_0 @ exponent over- or underflow + lsls r5,#1 @ rounding bit to carry + bcc 1f @ result is correctly rounded + adds r0,#1 + movs r6,#0 + adcs r1,r6 @ round up + mov r6,r12 @ remaining sticky bits + orrs r5,r6 + bne 1f @ some sticky bits set? + lsrs r0,#1 + lsls r0,#1 @ round to even +1: + lsls r3,#20 + adds r1,r3 +dm_2: + lsls r4,#31 + add r1,r4 + pop {r4-r7,r15} + +@ here for exponent over- or underflow +dm_0: + bge dm_1 @ overflow? + adds r3,#1 @ would-be zero exponent? + bne 1f + adds r0,#1 + bne 1f @ all-ones mantissa? + adds r1,#1 + lsrs r7,r1,#21 + beq 1f + lsrs r1,#1 + b dm_2 +1: + lsls r1,r4,#31 + movs r0,#0 + pop {r4-r7,r15} + +@ here for exponent overflow +dm_1: + adds r6,#1 @ 0x7ff + lsls r1,r6,#20 + movs r0,#0 + b dm_2 + +.ltorg + +@ Approach to division y/x is as follows. +@ +@ First generate u1, an approximation to 1/x to about 29 bits. Multiply this by the top +@ 32 bits of y to generate a0, a first approximation to the result (good to 28 bits or so). +@ Calculate the exact remainder r0=y-a0*x, which will be about 0. Calculate a correction +@ d0=r0*u1, and then write a1=a0+d0. If near a rounding boundary, compute the exact +@ remainder r1=y-a1*x (which can be done using r0 as a basis) to determine whether to +@ round up or down. +@ +@ The calculation of 1/x is as given in dreciptest.c. That code verifies exhaustively +@ that | u1*x-1 | < 10*2^-32. +@ +@ More precisely: +@ +@ x0=(q16)x; +@ x1=(q30)x; +@ y0=(q31)y; +@ u0=(q15~)"(0xffffffffU/(unsigned int)roundq(x/x_ulp))/powq(2,16)"(x0); // q15 approximation to 1/x; "~" denotes rounding rather than truncation +@ v=(q30)(u0*x1-1); +@ u1=(q30)u0-(q30~)(u0*v); +@ +@ a0=(q30)(u1*y0); +@ r0=(q82)y-a0*x; +@ r0x=(q57)r0; +@ d0=r0x*u1; +@ a1=d0+a0; +@ +@ Error analysis +@ +@ Use Greek letters to represent the errors introduced by rounding and truncation. +@ +@ râ‚€ = y - aâ‚€x +@ = y - [ uâ‚ ( y - α ) - β ] x where 0 ≤ α < 2^-31, 0 ≤ β < 2^-30 +@ = y ( 1 - uâ‚x ) + ( uâ‚α + β ) x +@ +@ Hence +@ +@ | râ‚€ / x | < 2 * 10*2^-32 + 2^-31 + 2^-30 +@ = 26*2^-32 +@ +@ râ‚ = y - aâ‚x +@ = y - aâ‚€x - dâ‚€x +@ = râ‚€ - dâ‚€x +@ = râ‚€ - uâ‚ ( râ‚€ - γ ) x where 0 ≤ γ < 2^-57 +@ = râ‚€ ( 1 - uâ‚x ) + uâ‚γx +@ +@ Hence +@ +@ | râ‚ / x | < 26*2^-32 * 10*2^-32 + 2^-57 +@ = (260+128)*2^-64 +@ < 2^-55 +@ +@ Empirically it seems to be nearly twice as good as this. +@ +@ To determine correctly whether the exact remainder calculation can be skipped we need a result +@ accurate to < 0.25ulp. In the case where x>y the quotient will be shifted up one place for normalisation +@ and so 1ulp is 2^-53 and so the calculation above suffices. + +double_section ddiv_shim + regular_func ddiv_shim + push {r4-r7,r14} +ddiv0: @ entry point from dtan + mdunpack r2,r3,r4,r7,r6 @ unpack divisor + +.if use_hw_div + + movs r5,#IOPORT>>24 + lsls r5,#24 + movs r6,#0 + mvns r6,r6 + str r6,[r5,#DIV_UDIVIDEND] + lsrs r6,r3,#4 @ x0=(q16)x + str r6,[r5,#DIV_UDIVISOR] +@ if there are not enough cycles from now to the read of the quotient for +@ the divider to do its stuff we need a busy-wait here + +.endif + +@ unpack dividend by hand to save on register use + lsrs r6,r1,#31 + adds r6,r7 + mov r12,r6 @ result sign in r12b0; r12b1 trashed + lsls r1,#1 + lsrs r7,r1,#21 @ exponent + beq 1f @ zero exponent? + adds r6,r7,#1 + lsrs r6,#11 + beq 2f @ exponent != 0x7ff? then done +1: + movs r0,#0 + movs r1,#0 + subs r7,#64 @ less drastic fiddling of exponents to get 0/0, Inf/Inf correct + lsls r7,#12 +2: + subs r6,r7,r4 + lsls r6,#2 + add r12,r12,r6 @ (signed) exponent in r12[31..8] + subs r7,#1 @ implied 1 + lsls r7,#21 + subs r1,r7 + lsrs r1,#1 + +.if use_hw_div + + ldr r6,[r5,#DIV_QUOTIENT] + adds r6,#1 + lsrs r6,#1 + +.else + +@ this is not beautiful; could be replaced by better code that uses knowledge of divisor range + push {r0-r3} + movs r0,#0 + mvns r0,r0 + lsrs r1,r3,#4 @ x0=(q16)x + bl __aeabi_uidiv @ !!! this could (but apparently does not) trash R12 + adds r6,r0,#1 + lsrs r6,#1 + pop {r0-r3} + +.endif + +@ here +@ r0:r1 y mantissa +@ r2:r3 x mantissa +@ r6 u0, first approximation to 1/x Q15 +@ r12: result sign, exponent + + lsls r4,r3,#10 + lsrs r5,r2,#22 + orrs r5,r4 @ x1=(q30)x + muls r5,r6 @ u0*x1 Q45 + asrs r5,#15 @ v=u0*x1-1 Q30 + muls r5,r6 @ u0*v Q45 + asrs r5,#14 + adds r5,#1 + asrs r5,#1 @ round u0*v to Q30 + lsls r6,#15 + subs r6,r5 @ u1 Q30 + +@ here +@ r0:r1 y mantissa +@ r2:r3 x mantissa +@ r6 u1, second approximation to 1/x Q30 +@ r12: result sign, exponent + + push {r2,r3} + lsls r4,r1,#11 + lsrs r5,r0,#21 + orrs r4,r5 @ y0=(q31)y + mul32_32_64 r4,r6, r4,r5, r2,r3,r7,r4,r5 @ y0*u1 Q61 + adds r4,r4 + adcs r5,r5 @ a0=(q30)(y0*u1) + +@ here +@ r0:r1 y mantissa +@ r5 a0, first approximation to y/x Q30 +@ r6 u1, second approximation to 1/x Q30 +@ r12 result sign, exponent + + ldr r2,[r13,#0] @ xL + mul32_32_64 r2,r5, r2,r3, r1,r4,r7,r2,r3 @ xL*a0 + ldr r4,[r13,#4] @ xH + muls r4,r5 @ xH*a0 + adds r3,r4 @ r2:r3 now x*a0 Q82 + lsrs r2,#25 + lsls r1,r3,#7 + orrs r2,r1 @ r2 now x*a0 Q57; r7:r2 is x*a0 Q89 + lsls r4,r0,#5 @ y Q57 + subs r0,r4,r2 @ r0x=y-x*a0 Q57 (signed) + +@ here +@ r0 r0x Q57 +@ r5 a0, first approximation to y/x Q30 +@ r4 yL Q57 +@ r6 u1 Q30 +@ r12 result sign, exponent + + muls32_32_64 r0,r6, r7,r6, r1,r2,r3, r7,r6 @ r7:r6 r0x*u1 Q87 + asrs r3,r6,#25 + adds r5,r3 + lsls r3,r6,#7 @ r3:r5 a1 Q62 (but bottom 7 bits are zero so 55 bits of precision after binary point) +@ here we could recover another 7 bits of precision (but not accuracy) from the top of r7 +@ but these bits are thrown away in the rounding and conversion to Q52 below + +@ here +@ r3:r5 a1 Q62 candidate quotient [0.5,2) or so +@ r4 yL Q57 +@ r12 result sign, exponent + + movs r6,#0 + adds r3,#128 @ for initial rounding to Q53 + adcs r5,r5,r6 + lsrs r1,r5,#30 + bne dd_0 +@ here candidate quotient a1 is in range [0.5,1) +@ so 30 significant bits in r5 + + lsls r4,#1 @ y now Q58 + lsrs r1,r5,#9 @ to Q52 + lsls r0,r5,#23 + lsrs r3,#9 @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result + orrs r0,r3 + bcs dd_1 + b dd_2 +dd_0: +@ here candidate quotient a1 is in range [1,2) +@ so 31 significant bits in r5 + + movs r2,#4 + add r12,r12,r2 @ fix exponent; r3:r5 now effectively Q61 + adds r3,#128 @ complete rounding to Q53 + adcs r5,r5,r6 + lsrs r1,r5,#10 + lsls r0,r5,#22 + lsrs r3,#10 @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result + orrs r0,r3 + bcc dd_2 +dd_1: + +@ here +@ r0:r1 rounded result Q53 [0.5,1) or Q52 [1,2), but may not be correctly rounded-to-nearest +@ r4 yL Q58 or Q57 +@ r12 result sign, exponent +@ carry set + + adcs r0,r0,r0 + adcs r1,r1,r1 @ z Q53 with 1 in LSB + lsls r4,#16 @ Q105-32=Q73 + ldr r2,[r13,#0] @ xL Q52 + ldr r3,[r13,#4] @ xH Q20 + + movs r5,r1 @ zH Q21 + muls r5,r2 @ zH*xL Q73 + subs r4,r5 + muls r3,r0 @ zL*xH Q73 + subs r4,r3 + mul32_32_64 r2,r0, r2,r3, r5,r6,r7,r2,r3 @ xL*zL + rsbs r2,#0 @ borrow from low half? + sbcs r4,r3 @ y-xz Q73 (remainder bits 52..73) + + cmp r4,#0 + + bmi 1f + movs r2,#0 @ round up + adds r0,#1 + adcs r1,r2 +1: + lsrs r0,#1 @ shift back down to Q52 + lsls r2,r1,#31 + orrs r0,r2 + lsrs r1,#1 +dd_2: + add r13,#8 + mov r2,r12 + lsls r7,r2,#31 @ result sign + asrs r2,#2 @ result exponent + ldr r3,=#0x3fd + adds r2,r3 + ldr r3,=#0x7fe + cmp r2,r3 + bhs dd_3 @ over- or underflow? + lsls r2,#20 + adds r1,r2 @ pack exponent +dd_5: + adds r1,r7 @ pack sign + pop {r4-r7,r15} + +dd_3: + movs r0,#0 + cmp r2,#0 + bgt dd_4 @ overflow? + movs r1,r7 + pop {r4-r7,r15} + +dd_4: + adds r3,#1 @ 0x7ff + lsls r1,r3,#20 + b dd_5 + +.section SECTION_NAME(dsqrt_shim) +/* +Approach to square root x=sqrt(y) is as follows. + +First generate a3, an approximation to 1/sqrt(y) to about 30 bits. Multiply this by y +to give a4~sqrt(y) to about 28 bits and a remainder r4=y-a4^2. Then, because +d sqrt(y) / dy = 1 / (2 sqrt(y)) let d4=r4*a3/2 and then the value a5=a4+d4 is +a better approximation to sqrt(y). If this is near a rounding boundary we +compute an exact remainder y-a5*a5 to decide whether to round up or down. + +The calculation of a3 and a4 is as given in dsqrttest.c. That code verifies exhaustively +that | 1 - a3a4 | < 10*2^-32, | r4 | < 40*2^-32 and | r4/y | < 20*2^-32. + +More precisely, with "y" representing y truncated to 30 binary places: + +u=(q3)y; // 24-entry table +a0=(q8~)"1/sqrtq(x+x_ulp/2)"(u); // first approximation from table +p0=(q16)(a0*a0) * (q16)y; +r0=(q20)(p0-1); +dy0=(q15)(r0*a0); // Newton-Raphson correction term +a1=(q16)a0-dy0/2; // good to ~9 bits + +p1=(q19)(a1*a1)*(q19)y; +r1=(q23)(p1-1); +dy1=(q15~)(r1*a1); // second Newton-Raphson correction +a2x=(q16)a1-dy1/2; // good to ~16 bits +a2=a2x-a2x/1t16; // prevent overflow of a2*a2 in 32 bits + +p2=(a2*a2)*(q30)y; // Q62 +r2=(q36)(p2-1+1t-31); +dy2=(q30)(r2*a2); // Q52->Q30 +a3=(q31)a2-dy2/2; // good to about 30 bits +a4=(q30)(a3*(q30)y+1t-31); // good to about 28 bits + +Error analysis + + râ‚„ = y - a₄² + dâ‚„ = 1/2 a₃râ‚„ + aâ‚… = aâ‚„ + dâ‚„ + râ‚… = y - a₅² + = y - ( aâ‚„ + dâ‚„ )² + = y - a₄² - a₃aâ‚„râ‚„ - 1/4 a₃²r₄² + = râ‚„ - a₃aâ‚„râ‚„ - 1/4 a₃²r₄² + + | râ‚… | < | râ‚„ | | 1 - a₃aâ‚„ | + 1/4 r₄² + + aâ‚… = √y √( 1 - râ‚…/y ) + = √y ( 1 - 1/2 râ‚…/y + ... ) + +So to first order (second order being very tiny) + + √y - aâ‚… = 1/2 râ‚…/y + +and + + | √y - aâ‚… | < 1/2 ( | râ‚„/y | | 1 - a₃aâ‚„ | + 1/4 r₄²/y ) + +From dsqrttest.c (conservatively): + + < 1/2 ( 20*2^-32 * 10*2^-32 + 1/4 * 40*2^-32*20*2^-32 ) + = 1/2 ( 200 + 200 ) * 2^-64 + < 2^-56 + +Empirically we see about 1ulp worst-case error including rounding at Q57. + +To determine correctly whether the exact remainder calculation can be skipped we need a result +accurate to < 0.25ulp at Q52, or 2^-54. +*/ + +dq_2: + bge dq_3 @ +Inf? + movs r1,#0 + b dq_4 + +dq_0: + lsrs r1,#31 + lsls r1,#31 @ preserve sign bit + lsrs r2,#21 @ extract exponent + beq dq_4 @ -0? return it + asrs r1,#11 @ make -Inf + b dq_4 + +dq_3: + ldr r1,=#0x7ff + lsls r1,#20 @ return +Inf +dq_4: + movs r0,#0 +dq_1: + bx r14 + +.align 2 +regular_func dsqrt_shim + lsls r2,r1,#1 + bcs dq_0 @ negative? + lsrs r2,#21 @ extract exponent + subs r2,#1 + ldr r3,=#0x7fe + cmp r2,r3 + bhs dq_2 @ catches 0 and +Inf + push {r4-r7,r14} + lsls r4,r2,#20 + subs r1,r4 @ insert implied 1 + lsrs r2,#1 + bcc 1f @ even exponent? skip + adds r0,r0,r0 @ odd exponent: shift up mantissa + adcs r1,r1,r1 +1: + lsrs r3,#2 + adds r2,r3 + lsls r2,#20 + mov r12,r2 @ save result exponent + +@ here +@ r0:r1 y mantissa Q52 [1,4) +@ r12 result exponent + + adr r4,drsqrtapp-8 @ first eight table entries are never accessed because of the mantissa's leading 1 + lsrs r2,r1,#17 @ y Q3 + ldrb r2,[r4,r2] @ initial approximation to reciprocal square root a0 Q8 + lsrs r3,r1,#4 @ first Newton-Raphson iteration + muls r3,r2 + muls r3,r2 @ i32 p0=a0*a0*(y>>14); // Q32 + asrs r3,r3,#12 @ i32 r0=p0>>12; // Q20 + muls r3,r2 + asrs r3,#13 @ i32 dy0=(r0*a0)>>13; // Q15 + lsls r2,#8 + subs r2,r3 @ i32 a1=(a0<<8)-dy0; // Q16 + + movs r3,r2 + muls r3,r3 + lsrs r3,#13 + lsrs r4,r1,#1 + muls r3,r4 @ i32 p1=((a1*a1)>>11)*(y>>11); // Q19*Q19=Q38 + asrs r3,#15 @ i32 r1=p1>>15; // Q23 + muls r3,r2 + asrs r3,#23 + adds r3,#1 + asrs r3,#1 @ i32 dy1=(r1*a1+(1<<23))>>24; // Q23*Q16=Q39; Q15 + subs r2,r3 @ i32 a2=a1-dy1; // Q16 + lsrs r3,r2,#16 + subs r2,r3 @ if(a2>=0x10000) a2=0xffff; to prevent overflow of a2*a2 + +@ here +@ r0:r1 y mantissa +@ r2 a2 ~ 1/sqrt(y) Q16 +@ r12 result exponent + + movs r3,r2 + muls r3,r3 + lsls r1,#10 + lsrs r4,r0,#22 + orrs r1,r4 @ y Q30 + mul32_32_64 r1,r3, r4,r3, r5,r6,r7,r4,r3 @ i64 p2=(ui64)(a2*a2)*(ui64)y; // Q62 r4:r3 + lsls r5,r3,#6 + lsrs r4,#26 + orrs r4,r5 + adds r4,#0x20 @ i32 r2=(p2>>26)+0x20; // Q36 r4 + uxth r5,r4 + muls r5,r2 + asrs r4,#16 + muls r4,r2 + lsrs r5,#16 + adds r4,r5 + asrs r4,#6 @ i32 dy2=((i64)r2*(i64)a2)>>22; // Q36*Q16=Q52; Q30 + lsls r2,#15 + subs r2,r4 + +@ here +@ r0 y low bits +@ r1 y Q30 +@ r2 a3 ~ 1/sqrt(y) Q31 +@ r12 result exponent + + mul32_32_64 r2,r1, r3,r4, r5,r6,r7,r3,r4 + adds r3,r3,r3 + adcs r4,r4,r4 + adds r3,r3,r3 + movs r3,#0 + adcs r3,r4 @ ui32 a4=((ui64)a3*(ui64)y+(1U<<31))>>31; // Q30 + +@ here +@ r0 y low bits +@ r1 y Q30 +@ r2 a3 Q31 ~ 1/sqrt(y) +@ r3 a4 Q30 ~ sqrt(y) +@ r12 result exponent + + square32_64 r3, r4,r5, r6,r5,r7 + lsls r6,r0,#8 + lsrs r7,r1,#2 + subs r6,r4 + sbcs r7,r5 @ r4=(q60)y-a4*a4 + +@ by exhaustive testing, r4 = fffffffc0e134fdc .. 00000003c2bf539c Q60 + + lsls r5,r7,#29 + lsrs r6,#3 + adcs r6,r5 @ r4 Q57 with rounding + muls32_32_64 r6,r2, r6,r2, r4,r5,r7,r6,r2 @ d4=a3*r4/2 Q89 +@ r4+d4 is correct to 1ULP at Q57, tested on ~9bn cases including all extreme values of r4 for each possible y Q30 + + adds r2,#8 + asrs r2,#5 @ d4 Q52, rounded to Q53 with spare bit in carry + +@ here +@ r0 y low bits +@ r1 y Q30 +@ r2 d4 Q52, rounded to Q53 +@ C flag contains d4_b53 +@ r3 a4 Q30 + + bcs dq_5 + + lsrs r5,r3,#10 @ a4 Q52 + lsls r4,r3,#22 + + asrs r1,r2,#31 + adds r0,r2,r4 + adcs r1,r5 @ a4+d4 + + add r1,r12 @ pack exponent + pop {r4-r7,r15} + +.ltorg + + +@ round(sqrt(2^22./[68:8:252])) +drsqrtapp: +.byte 0xf8,0xeb,0xdf,0xd6,0xcd,0xc5,0xbe,0xb8 +.byte 0xb2,0xad,0xa8,0xa4,0xa0,0x9c,0x99,0x95 +.byte 0x92,0x8f,0x8d,0x8a,0x88,0x85,0x83,0x81 + +dq_5: +@ here we are near a rounding boundary, C is set + adcs r2,r2,r2 @ d4 Q53+1ulp + lsrs r5,r3,#9 + lsls r4,r3,#23 @ r4:r5 a4 Q53 + asrs r1,r2,#31 + adds r4,r2,r4 + adcs r5,r1 @ r4:r5 a5=a4+d4 Q53+1ulp + movs r3,r5 + muls r3,r4 + square32_64 r4,r1,r2,r6,r2,r7 + adds r2,r3 + adds r2,r3 @ r1:r2 a5^2 Q106 + lsls r0,#22 @ y Q84 + + rsbs r1,#0 + sbcs r0,r2 @ remainder y-a5^2 + bmi 1f @ y=0 +@ ω+=dω +@ x+=y>>i, y-=x>>i + adds r0,r3 + adcs r1,r4 + + mov r3,r11 + asrs r3,r7 + mov r4,r11 + lsls r4,r6 + mov r2,r10 + lsrs r2,r7 + orrs r2,r4 @ r2:r3 y>>i, rounding in carry + mov r4,r8 + mov r5,r9 @ r4:r5 x + adcs r2,r4 + adcs r3,r5 @ r2:r3 x+(y>>i) + mov r8,r2 + mov r9,r3 + + mov r3,r5 + lsls r3,r6 + asrs r5,r7 + lsrs r4,r7 + orrs r4,r3 @ r4:r5 x>>i, rounding in carry + mov r2,r10 + mov r3,r11 + sbcs r2,r4 + sbcs r3,r5 @ r2:r3 y-(x>>i) + mov r10,r2 + mov r11,r3 + bx r14 + + +@ ω>0 / y<0 +@ ω-=dω +@ x-=y>>i, y+=x>>i +1: + subs r0,r3 + sbcs r1,r4 + + mov r3,r9 + asrs r3,r7 + mov r4,r9 + lsls r4,r6 + mov r2,r8 + lsrs r2,r7 + orrs r2,r4 @ r2:r3 x>>i, rounding in carry + mov r4,r10 + mov r5,r11 @ r4:r5 y + adcs r2,r4 + adcs r3,r5 @ r2:r3 y+(x>>i) + mov r10,r2 + mov r11,r3 + + mov r3,r5 + lsls r3,r6 + asrs r5,r7 + lsrs r4,r7 + orrs r4,r3 @ r4:r5 y>>i, rounding in carry + mov r2,r8 + mov r3,r9 + sbcs r2,r4 + sbcs r3,r5 @ r2:r3 x-(y>>i) + mov r8,r2 + mov r9,r3 + bx r14 + +ret_dzero: + movs r0,#0 + movs r1,#0 + bx r14 + +@ convert packed double in r0:r1 to signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point], with rounding towards -Inf +@ fixed-point versions only work with reasonable values in r2 because of the way dunpacks works + +double_section double2int_shim + regular_func double2int_shim + movs r2,#0 @ and fall through +regular_func double2fix_shim + push {r14} + adds r2,#32 + bl double2fix64_shim + movs r0,r1 + pop {r15} + +double_section double2uint_shim + regular_func double2uint_shim + movs r2,#0 @ and fall through +regular_func double2ufix_shim + push {r14} + adds r2,#32 + bl double2ufix64_shim + movs r0,r1 + pop {r15} + +double_section double2int64_shim + regular_func double2int64_shim + movs r2,#0 @ and fall through +regular_func double2fix64_shim + push {r14} + bl d2fix + + asrs r2,r1,#31 + cmp r2,r3 + bne 1f @ sign extension bits fail to match sign of result? + pop {r15} +1: + mvns r0,r3 + movs r1,#1 + lsls r1,#31 + eors r1,r1,r0 @ generate extreme fixed-point values + pop {r15} + +double_section double2uint64_shim + regular_func double2uint64_shim + movs r2,#0 @ and fall through +regular_func double2ufix64_shim + asrs r3,r1,#20 @ negative? return 0 + bmi ret_dzero +@ and fall through + +@ convert double in r0:r1 to signed fixed point in r0:r1:r3, r2 places after point, rounding towards -Inf +@ result clamped so that r3 can only be 0 or -1 +@ trashes r12 +.thumb_func +d2fix: + push {r4,r14} + mov r12,r2 + bl dunpacks + asrs r4,r2,#16 + adds r4,#1 + bge 1f + movs r1,#0 @ -0 -> +0 +1: + asrs r3,r1,#31 + ldr r4, =d2fix_a + bx r4 + +.weak d2fix_a // weak because it exists in float code too +regular_func d2fix_a +@ here +@ r0:r1 two's complement mantissa +@ r2 unbaised exponent +@ r3 mantissa sign extension bits + add r2,r12 @ exponent plus offset for required binary point position + subs r2,#52 @ required shift + bmi 1f @ shift down? +@ here a shift up by r2 places + cmp r2,#12 @ will clamp? + bge 2f + movs r4,r0 + lsls r1,r2 + lsls r0,r2 + rsbs r2,#0 + adds r2,#32 @ complementary shift + lsrs r4,r2 + orrs r1,r4 + pop {r4,r15} +2: + mvns r0,r3 + mvns r1,r3 @ overflow: clamp to extreme fixed-point values + pop {r4,r15} +1: +@ here a shift down by -r2 places + adds r2,#32 + bmi 1f @ long shift? + mov r4,r1 + lsls r4,r2 + rsbs r2,#0 + adds r2,#32 @ complementary shift + asrs r1,r2 + lsrs r0,r2 + orrs r0,r4 + pop {r4,r15} +1: +@ here a long shift down + movs r0,r1 + asrs r1,#31 @ shift down 32 places + adds r2,#32 + bmi 1f @ very long shift? + rsbs r2,#0 + adds r2,#32 + asrs r0,r2 + pop {r4,r15} +1: + movs r0,r3 @ result very near zero: use sign extension bits + movs r1,r3 + pop {r4,r15} + +double_section double2float_shim + regular_func double2float_shim + lsls r2,r1,#1 + lsrs r2,#21 @ exponent + ldr r3,=#0x3ff-0x7f + subs r2,r3 @ fix exponent bias + ble 1f @ underflow or zero + cmp r2,#0xff + bge 2f @ overflow or infinity + lsls r2,#23 @ position exponent of result + lsrs r3,r1,#31 + lsls r3,#31 + orrs r2,r3 @ insert sign + lsls r3,r0,#3 @ rounding bits + lsrs r0,#29 + lsls r1,#12 + lsrs r1,#9 + orrs r0,r1 @ assemble mantissa + orrs r0,r2 @ insert exponent and sign + lsls r3,#1 + bcc 3f @ no rounding + beq 4f @ all sticky bits 0? +5: + adds r0,#1 +3: + bx r14 +4: + lsrs r3,r0,#1 @ odd? then round up + bcs 5b + bx r14 +1: + beq 6f @ check case where value is just less than smallest normal +7: + lsrs r0,r1,#31 + lsls r0,#31 + bx r14 +6: + lsls r2,r1,#12 @ 20 1:s at top of mantissa? + asrs r2,#12 + adds r2,#1 + bne 7b + lsrs r2,r0,#29 @ and 3 more 1:s? + cmp r2,#7 + bne 7b + movs r2,#1 @ return smallest normal with correct sign + b 8f +2: + movs r2,#0xff +8: + lsrs r0,r1,#31 @ return signed infinity + lsls r0,#8 + adds r0,r2 + lsls r0,#23 + bx r14 + +double_section x2double_shims +@ convert signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point] to packed double in r0:r1, with rounding + +.align 2 +regular_func uint2double_shim + movs r1,#0 @ and fall through +regular_func ufix2double_shim + movs r2,r1 + movs r1,#0 + b ufix642double_shim + +.align 2 +regular_func int2double_shim + movs r1,#0 @ and fall through +regular_func fix2double_shim + movs r2,r1 + asrs r1,r0,#31 @ sign extend + b fix642double_shim + +.align 2 +regular_func uint642double_shim + movs r2,#0 @ and fall through +regular_func ufix642double_shim + movs r3,#0 + b uf2d + +.align 2 +regular_func int642double_shim + movs r2,#0 @ and fall through +regular_func fix642double_shim + asrs r3,r1,#31 @ sign bit across all bits + eors r0,r3 + eors r1,r3 + subs r0,r3 + sbcs r1,r3 +uf2d: + push {r4,r5,r14} + ldr r4,=#0x432 + subs r2,r4,r2 @ form biased exponent +@ here +@ r0:r1 unnormalised mantissa +@ r2 -Q (will become exponent) +@ r3 sign across all bits + cmp r1,#0 + bne 1f @ short normalising shift? + movs r1,r0 + beq 2f @ zero? return it + movs r0,#0 + subs r2,#32 @ fix exponent +1: + asrs r4,r1,#21 + bne 3f @ will need shift down (and rounding?) + bcs 4f @ normalised already? +5: + subs r2,#1 + adds r0,r0 @ shift up + adcs r1,r1 + lsrs r4,r1,#21 + bcc 5b +4: + ldr r4,=#0x7fe + cmp r2,r4 + bhs 6f @ over/underflow? return signed zero/infinity +7: + lsls r2,#20 @ pack and return + adds r1,r2 + lsls r3,#31 + adds r1,r3 +2: + pop {r4,r5,r15} +6: @ return signed zero/infinity according to unclamped exponent in r2 + mvns r2,r2 + lsrs r2,#21 + movs r0,#0 + movs r1,#0 + b 7b + +3: +@ here we need to shift down to normalise and possibly round + bmi 1f @ already normalised to Q63? +2: + subs r2,#1 + adds r0,r0 @ shift up + adcs r1,r1 + bpl 2b +1: +@ here we have a 1 in b63 of r0:r1 + adds r2,#11 @ correct exponent for subsequent shift down + lsls r4,r0,#21 @ save bits for rounding + lsrs r0,#11 + lsls r5,r1,#21 + orrs r0,r5 + lsrs r1,#11 + lsls r4,#1 + beq 1f @ sticky bits are zero? +8: + movs r4,#0 + adcs r0,r4 + adcs r1,r4 + b 4b +1: + bcc 4b @ sticky bits are zero but not on rounding boundary + lsrs r4,r0,#1 @ increment if odd (force round to even) + b 8b + + +.ltorg + +double_section dunpacks + regular_func dunpacks + mdunpacks r0,r1,r2,r3,r4 + ldr r3,=#0x3ff + subs r2,r3 @ exponent without offset + bx r14 + +@ r0:r1 signed mantissa Q52 +@ r2 unbiased exponent < 10 (i.e., |x|<2^10) +@ r4 pointer to: +@ - divisor reciprocal approximation r=1/d Q15 +@ - divisor d Q62 0..20 +@ - divisor d Q62 21..41 +@ - divisor d Q62 42..62 +@ returns: +@ r0:r1 reduced result y Q62, -0.6 d < y < 0.6 d (better in practice) +@ r2 quotient q (number of reductions) +@ if exponent >=10, returns r0:r1=0, r2=1024*mantissa sign +@ designed to work for 0.5=0: in quadrant 0 + cmp r1,r3 + ble 2f @ y<~x so 0≤θ<~Ï€/4: skip + adds r6,#1 + eors r1,r5 @ negate x + b 3f @ and exchange x and y = rotate by -Ï€/2 +1: + cmp r3,r7 + bge 2f @ -y<~x so -Ï€/4<~θ≤0: skip + subs r6,#1 + eors r3,r5 @ negate y and ... +3: + movs r7,r0 @ exchange x and y + movs r0,r2 + movs r2,r7 + movs r7,r1 + movs r1,r3 + movs r3,r7 +2: +@ here -Ï€/4<~θ<~Ï€/4 +@ r6 has quadrant offset + push {r6} + cmp r2,#0 + bne 1f + cmp r3,#0 + beq 10f @ x==0 going into division? + lsls r4,r3,#1 + asrs r4,#21 + adds r4,#1 + bne 1f @ x==Inf going into division? + lsls r4,r1,#1 + asrs r4,#21 + adds r4,#1 @ y also ±Inf? + bne 10f + subs r1,#1 @ make them both just finite + subs r3,#1 + b 1f + +10: + movs r0,#0 + movs r1,#0 + b 12f + +1: + bl ddiv_shim + movs r2,#62 + bl double2fix64_shim +@ r0:r1 y/x + mov r10,r0 + mov r11,r1 + movs r0,#0 @ ω=0 + movs r1,#0 + mov r8,r0 + movs r2,#1 + lsls r2,#30 + mov r9,r2 @ x=1 + + adr r4,dtab_cc + mov r12,r4 + movs r7,#1 + movs r6,#31 +1: + bl dcordic_vec_step + adds r7,#1 + subs r6,#1 + cmp r7,#33 + bne 1b +@ r0:r1 atan(y/x) Q62 +@ r8:r9 x residual Q62 +@ r10:r11 y residual Q62 + mov r2,r9 + mov r3,r10 + subs r2,#12 @ this makes atan(0)==0 +@ the following is basically a division residual y/x ~ atan(residual y/x) + movs r4,#1 + lsls r4,#29 + movs r7,#0 +2: + lsrs r2,#1 + movs r3,r3 @ preserve carry + bmi 1f + sbcs r3,r2 + adds r0,r4 + adcs r1,r7 + lsrs r4,#1 + bne 2b + b 3f +1: + adcs r3,r2 + subs r0,r4 + sbcs r1,r7 + lsrs r4,#1 + bne 2b +3: + lsls r6,r1,#31 + asrs r1,#1 + lsrs r0,#1 + orrs r0,r6 @ Q61 + +12: + pop {r6} + + cmp r6,#0 + beq 1f + ldr r4,=#0x885A308D @ Ï€/2 Q61 + ldr r5,=#0x3243F6A8 + bpl 2f + mvns r4,r4 @ negative quadrant offset + mvns r5,r5 +2: + lsls r6,#31 + bne 2f @ skip if quadrant offset is ±1 + adds r0,r4 + adcs r1,r5 +2: + adds r0,r4 + adcs r1,r5 +1: + movs r2,#61 + bl fix642double_shim + + bl pop_r8_r11 + pop {r4-r7,r15} + +.ltorg + +dtab_cc: +.word 0x61bb4f69, 0x1dac6705 @ atan 2^-1 Q62 +.word 0x96406eb1, 0x0fadbafc @ atan 2^-2 Q62 +.word 0xab0bdb72, 0x07f56ea6 @ atan 2^-3 Q62 +.word 0xe59fbd39, 0x03feab76 @ atan 2^-4 Q62 +.word 0xba97624b, 0x01ffd55b @ atan 2^-5 Q62 +.word 0xdddb94d6, 0x00fffaaa @ atan 2^-6 Q62 +.word 0x56eeea5d, 0x007fff55 @ atan 2^-7 Q62 +.word 0xaab7776e, 0x003fffea @ atan 2^-8 Q62 +.word 0x5555bbbc, 0x001ffffd @ atan 2^-9 Q62 +.word 0xaaaaadde, 0x000fffff @ atan 2^-10 Q62 +.word 0xf555556f, 0x0007ffff @ atan 2^-11 Q62 +.word 0xfeaaaaab, 0x0003ffff @ atan 2^-12 Q62 +.word 0xffd55555, 0x0001ffff @ atan 2^-13 Q62 +.word 0xfffaaaab, 0x0000ffff @ atan 2^-14 Q62 +.word 0xffff5555, 0x00007fff @ atan 2^-15 Q62 +.word 0xffffeaab, 0x00003fff @ atan 2^-16 Q62 +.word 0xfffffd55, 0x00001fff @ atan 2^-17 Q62 +.word 0xffffffab, 0x00000fff @ atan 2^-18 Q62 +.word 0xfffffff5, 0x000007ff @ atan 2^-19 Q62 +.word 0xffffffff, 0x000003ff @ atan 2^-20 Q62 +.word 0x00000000, 0x00000200 @ atan 2^-21 Q62 @ consider optimising these +.word 0x00000000, 0x00000100 @ atan 2^-22 Q62 +.word 0x00000000, 0x00000080 @ atan 2^-23 Q62 +.word 0x00000000, 0x00000040 @ atan 2^-24 Q62 +.word 0x00000000, 0x00000020 @ atan 2^-25 Q62 +.word 0x00000000, 0x00000010 @ atan 2^-26 Q62 +.word 0x00000000, 0x00000008 @ atan 2^-27 Q62 +.word 0x00000000, 0x00000004 @ atan 2^-28 Q62 +.word 0x00000000, 0x00000002 @ atan 2^-29 Q62 +.word 0x00000000, 0x00000001 @ atan 2^-30 Q62 +.word 0x80000000, 0x00000000 @ atan 2^-31 Q62 +.word 0x40000000, 0x00000000 @ atan 2^-32 Q62 + +double_section dexp_guts +regular_func dexp_shim + push {r4-r7,r14} + bl dunpacks + adr r4,dreddata1 + bl dreduce + cmp r1,#0 + bge 1f + ldr r4,=#0xF473DE6B + ldr r5,=#0x2C5C85FD @ ln2 Q62 + adds r0,r4 + adcs r1,r5 + subs r2,#1 +1: + push {r2} + movs r7,#1 @ shift + adr r6,dtab_exp + movs r2,#0 + movs r3,#1 + lsls r3,#30 @ x=1 Q62 + +3: + ldmia r6!,{r4,r5} + mov r12,r6 + subs r0,r4 + sbcs r1,r5 + bmi 1f + + rsbs r6,r7,#0 + adds r6,#32 @ complementary shift + movs r5,r3 + asrs r5,r7 + movs r4,r3 + lsls r4,r6 + movs r6,r2 + lsrs r6,r7 @ rounding bit in carry + orrs r4,r6 + adcs r2,r4 + adcs r3,r5 @ x+=x>>i + b 2f + +1: + adds r0,r4 @ restore argument + adcs r1,r5 +2: + mov r6,r12 + adds r7,#1 + cmp r7,#33 + bne 3b + +@ here +@ r0:r1 ε (residual x, where x=a+ε) Q62, |ε|≤2^-32 (so fits in r0) +@ r2:r3 exp a Q62 +@ and we wish to calculate exp x=exp a exp ε~(exp a)(1+ε) + muls32_32_64 r0,r3, r4,r1, r5,r6,r7,r4,r1 +@ r4:r1 ε exp a Q(62+62-32)=Q92 + lsrs r4,#30 + lsls r0,r1,#2 + orrs r0,r4 + asrs r1,#30 + adds r0,r2 + adcs r1,r3 + + pop {r2} + rsbs r2,#0 + adds r2,#62 + bl fix642double_shim @ in principle we can pack faster than this because we know the exponent + pop {r4-r7,r15} + +.ltorg + +.align 2 +regular_func dln_shim + push {r4-r7,r14} + lsls r7,r1,#1 + bcs 5f @ <0 ... + asrs r7,#21 + beq 5f @ ... or =0? return -Inf + adds r7,#1 + beq 6f @ Inf/NaN? return +Inf + bl dunpacks + push {r2} + lsls r1,#9 + lsrs r2,r0,#23 + orrs r1,r2 + lsls r0,#9 +@ r0:r1 m Q61 = m/2 Q62 0.5≤m/2<1 + + movs r7,#1 @ shift + adr r6,dtab_exp + mov r12,r6 + movs r2,#0 + movs r3,#0 @ y=0 Q62 + +3: + rsbs r6,r7,#0 + adds r6,#32 @ complementary shift + movs r5,r1 + asrs r5,r7 + movs r4,r1 + lsls r4,r6 + movs r6,r0 + lsrs r6,r7 + orrs r4,r6 @ x>>i, rounding bit in carry + adcs r4,r0 + adcs r5,r1 @ x+(x>>i) + + lsrs r6,r5,#30 + bne 1f @ x+(x>>i)>1? + movs r0,r4 + movs r1,r5 @ x+=x>>i + mov r6,r12 + ldmia r6!,{r4,r5} + subs r2,r4 + sbcs r3,r5 + +1: + movs r4,#8 + add r12,r4 + adds r7,#1 + cmp r7,#33 + bne 3b +@ here: +@ r0:r1 residual x, nearly 1 Q62 +@ r2:r3 y ~ ln m/2 = ln m - ln2 Q62 +@ result is y + ln2 + ln x ~ y + ln2 + (x-1) + lsls r1,#2 + asrs r1,#2 @ x-1 + adds r2,r0 + adcs r3,r1 + + pop {r7} +@ here: +@ r2:r3 ln m/2 = ln m - ln2 Q62 +@ r7 unbiased exponent + + adr r4,dreddata1+4 + ldmia r4,{r0,r1,r4} + adds r7,#1 + muls r0,r7 @ Q62 + muls r1,r7 @ Q41 + muls r4,r7 @ Q20 + lsls r7,r1,#21 + asrs r1,#11 + asrs r5,r1,#31 + adds r0,r7 + adcs r1,r5 + lsls r7,r4,#10 + asrs r4,#22 + asrs r5,r1,#31 + adds r1,r7 + adcs r4,r5 +@ r0:r1:r4 exponent*ln2 Q62 + asrs r5,r3,#31 + adds r0,r2 + adcs r1,r3 + adcs r4,r5 +@ r0:r1:r4 result Q62 + movs r2,#62 +1: + asrs r5,r1,#31 + cmp r4,r5 + beq 2f @ r4 a sign extension of r1? + lsrs r0,#4 @ no: shift down 4 places and try again + lsls r6,r1,#28 + orrs r0,r6 + lsrs r1,#4 + lsls r6,r4,#28 + orrs r1,r6 + asrs r4,#4 + subs r2,#4 + b 1b +2: + bl fix642double_shim + pop {r4-r7,r15} + +5: + ldr r1,=#0xfff00000 + movs r0,#0 + pop {r4-r7,r15} + +6: + ldr r1,=#0x7ff00000 + movs r0,#0 + pop {r4-r7,r15} + +.ltorg + +.align 2 +dreddata1: +.word 0x0000B8AA @ 1/ln2 Q15 +.word 0x0013DE6B @ ln2 Q62 Q62=2C5C85FDF473DE6B split into 21-bit pieces +.word 0x000FEFA3 +.word 0x000B1721 + +dtab_exp: +.word 0xbf984bf3, 0x19f323ec @ log 1+2^-1 Q62 +.word 0xcd4d10d6, 0x0e47fbe3 @ log 1+2^-2 Q62 +.word 0x8abcb97a, 0x0789c1db @ log 1+2^-3 Q62 +.word 0x022c54cc, 0x03e14618 @ log 1+2^-4 Q62 +.word 0xe7833005, 0x01f829b0 @ log 1+2^-5 Q62 +.word 0x87e01f1e, 0x00fe0545 @ log 1+2^-6 Q62 +.word 0xac419e24, 0x007f80a9 @ log 1+2^-7 Q62 +.word 0x45621781, 0x003fe015 @ log 1+2^-8 Q62 +.word 0xa9ab10e6, 0x001ff802 @ log 1+2^-9 Q62 +.word 0x55455888, 0x000ffe00 @ log 1+2^-10 Q62 +.word 0x0aa9aac4, 0x0007ff80 @ log 1+2^-11 Q62 +.word 0x01554556, 0x0003ffe0 @ log 1+2^-12 Q62 +.word 0x002aa9ab, 0x0001fff8 @ log 1+2^-13 Q62 +.word 0x00055545, 0x0000fffe @ log 1+2^-14 Q62 +.word 0x8000aaaa, 0x00007fff @ log 1+2^-15 Q62 +.word 0xe0001555, 0x00003fff @ log 1+2^-16 Q62 +.word 0xf80002ab, 0x00001fff @ log 1+2^-17 Q62 +.word 0xfe000055, 0x00000fff @ log 1+2^-18 Q62 +.word 0xff80000b, 0x000007ff @ log 1+2^-19 Q62 +.word 0xffe00001, 0x000003ff @ log 1+2^-20 Q62 +.word 0xfff80000, 0x000001ff @ log 1+2^-21 Q62 +.word 0xfffe0000, 0x000000ff @ log 1+2^-22 Q62 +.word 0xffff8000, 0x0000007f @ log 1+2^-23 Q62 +.word 0xffffe000, 0x0000003f @ log 1+2^-24 Q62 +.word 0xfffff800, 0x0000001f @ log 1+2^-25 Q62 +.word 0xfffffe00, 0x0000000f @ log 1+2^-26 Q62 +.word 0xffffff80, 0x00000007 @ log 1+2^-27 Q62 +.word 0xffffffe0, 0x00000003 @ log 1+2^-28 Q62 +.word 0xfffffff8, 0x00000001 @ log 1+2^-29 Q62 +.word 0xfffffffe, 0x00000000 @ log 1+2^-30 Q62 +.word 0x80000000, 0x00000000 @ log 1+2^-31 Q62 +.word 0x40000000, 0x00000000 @ log 1+2^-32 Q62 + + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/include/pico/double.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/include/pico/double.h new file mode 100644 index 00000000000..0893233feef --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/include/pico/double.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_DOUBLE_H +#define _PICO_DOUBLE_H + +#include +#include "pico/types.h" +#include "pico/bootrom/sf_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file double.h +* \defgroup pico_double pico_double +* +* Optimized double-precision floating point functions +* +* (Replacement) optimized implementations are provided of the following compiler built-ins +* and math library functions: +* +* - __aeabi_dadd, __aeabi_ddiv, __aeabi_dmul, __aeabi_drsub, __aeabi_dsub, __aeabi_cdcmpeq, __aeabi_cdrcmple, __aeabi_cdcmple, __aeabi_dcmpeq, __aeabi_dcmplt, __aeabi_dcmple, __aeabi_dcmpge, __aeabi_dcmpgt, __aeabi_dcmpun, __aeabi_i2d, __aeabi_l2d, __aeabi_ui2d, __aeabi_ul2d, __aeabi_d2iz, __aeabi_d2lz, __aeabi_d2uiz, __aeabi_d2ulz, __aeabi_d2f +* - sqrt, cos, sin, tan, atan2, exp, log, ldexp, copysign, trunc, floor, ceil, round, asin, acos, atan, sinh, cosh, tanh, asinh, acosh, atanh, exp2, log2, exp10, log10, pow,, hypot, cbrt, fmod, drem, remainder, remquo, expm1, log1p, fma +* - powint, sincos (GNU extensions) +* +* The following additional optimized functions are also provided: +* +* - fix2double, ufix2double, fix642double, ufix642double, double2fix, double2ufix, double2fix64, double2ufix64, double2int, double2int64, double2int_z, double2int64_z +*/ + +double fix2double(int32_t m, int e); +double ufix2double(uint32_t m, int e); +double fix642double(int64_t m, int e); +double ufix642double(uint64_t m, int e); + +// These methods round towards -Infinity. +int32_t double2fix(double f, int e); +uint32_t double2ufix(double f, int e); +int64_t double2fix64(double f, int e); +uint64_t double2ufix64(double f, int e); +int32_t double2int(double f); +int64_t double2int64(double f); + +// These methods round towards 0. +int32_t double2int_z(double f); +int64_t double2int64_z(double f); + +double exp10(double x); +void sincos(double x, double *sinx, double *cosx); +double powint(double x, int y); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/CMakeLists.txt new file mode 100644 index 00000000000..81a9eaafb98 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/CMakeLists.txt @@ -0,0 +1 @@ +pico_add_subdirectory(rp2040_usb_device_enumeration) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt new file mode 100644 index 00000000000..0d682ab4eca --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt @@ -0,0 +1,9 @@ +add_library(pico_fix_rp2040_usb_device_enumeration INTERFACE) + +target_sources(pico_fix_rp2040_usb_device_enumeration INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/rp2040_usb_device_enumeration.c + ) + +target_include_directories(pico_fix_rp2040_usb_device_enumeration INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +target_link_libraries(pico_fix_rp2040_usb_device_enumeration INTERFACE hardware_structs pico_time) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h new file mode 100644 index 00000000000..49f115e907e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H +#define _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H + +/*! \brief Perform a brute force workaround for USB device enumeration issue + * \ingroup pico_fix + * + * This method should be called during the IRQ handler for a bus reset + */ +void rp2040_usb_device_enumeration_fix(void); + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c new file mode 100644 index 00000000000..8319e36cb71 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "pico/time.h" +#include "hardware/structs/usb.h" +#include "hardware/gpio.h" +#include "pico/fix/rp2040_usb_device_enumeration.h" + +#define LS_SE0 0b00 +#define LS_J 0b01 +#define LS_K 0b10 +#define LS_SE1 0b11 + +static void hw_enumeration_fix_wait_se0(void); +static void hw_enumeration_fix_force_ls_j(void); +static void hw_enumeration_fix_finish(void); + +void rp2040_usb_device_enumeration_fix(void) { + // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time + // before it will move to the connected state. However on a hub that broadcasts packets + // for other devices this isn't the case. The plan here is to wait for the end of the bus + // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately + // this requires us to use GPIO15 as there is no other way to force the input path. + // We only need to force DP as DM can be left at zero. It will be gated off by GPIO + // logic if it isn't func selected. + + // Wait SE0 phase will call force ls_j phase which will call finish phase + hw_enumeration_fix_wait_se0(); +} + +static inline uint8_t hw_line_state(void) { + return (usb_hw->sie_status & USB_SIE_STATUS_LINE_STATE_BITS) >> USB_SIE_STATUS_LINE_STATE_LSB; +} + +int64_t hw_enumeration_fix_wait_se0_callback(alarm_id_t id, void *user_data) { + if (hw_line_state() == LS_SE0) { + // Come back in 1ms and check again + return 1000; + } else { + // Now force LS_J (next stage of fix) + hw_enumeration_fix_force_ls_j(); + // No more repeats + return 0; + } +} + +static inline void hw_enumeration_fix_busy_wait_se0(void) { + while (hw_line_state() == LS_SE0) tight_loop_contents(); + // Now force LS_J (next stage of fix) + hw_enumeration_fix_force_ls_j(); +} + +static void hw_enumeration_fix_wait_se0(void) { + // Wait for SE0 to end (i.e. the host to stop resetting). This reset can last quite long. + // 10-15ms so we are going to set a timer callback. + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + if (add_alarm_in_ms(1, hw_enumeration_fix_wait_se0_callback, NULL, true) >= 0) { + // hw_enumeration_fix_wait_se0_callback will be called in 1ms to check if se0 has finished + // (and will poll every 1ms from there) + return; + } +#endif + // if timer pool disabled, or no timer available, have to busy wait. + hw_enumeration_fix_busy_wait_se0(); +} + +int64_t hw_enumeration_fix_force_ls_j_done(alarm_id_t id, void *user_data) { + hw_enumeration_fix_finish(); + return 0; +} + +static void hw_enumeration_fix_force_ls_j(void) { + // Force LS_J + const uint dp = 15; + //const uint dm = 16; + gpio_set_function(dp, 8); + // TODO: assert dm is not funcseld to usb + + // J state is a differential 1 for a full speed device so + // DP = 1 and DM = 0. Don't actually need to set DM low as it + // is already gated assuming it isn't funcseld. + gpio_set_inover(dp, GPIO_OVERRIDE_HIGH); + + // TODO: What to do about existing DP state here? + + // Force PHY pull up to stay before switching away from the phy + hw_set_alias(usb_hw)->phy_direct = USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS; + hw_set_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS; + + // Switch to GPIO phy with LS_J forced + usb_hw->muxing = USB_USB_MUXING_TO_DIGITAL_PAD_BITS | USB_USB_MUXING_SOFTCON_BITS; + + // LS_J is now forced but while loop here just to check + hard_assert(hw_line_state() == LS_J); // "LS_J not forced!" + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + if (add_alarm_in_ms(1, hw_enumeration_fix_force_ls_j_done, NULL, true) >= 0) { + // hw_enumeration_fix_force_ls_j_done will be called in 1ms + return; + } +#endif + // if timer pool disabled, or no timer available, have to busy wait. + busy_wait_us(1000); + hw_enumeration_fix_finish(); +} + +static void hw_enumeration_fix_finish(void) { + // Should think we are connected now + while (!(usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS)) tight_loop_contents(); + + // Switch back to USB phy + usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; + + // Get rid of DP pullup override + hw_clear_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/CMakeLists.txt new file mode 100644 index 00000000000..a6e78957040 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/CMakeLists.txt @@ -0,0 +1,126 @@ +if (NOT TARGET pico_float) + # library to be depended on - we make this depend on particular implementations using per target generator expressions + add_library(pico_float INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_float_compiler INTERFACE) + # PICO_BUILD_DEFINE: PICO_FLOAT_COMPILER, whether compiler provided float support is being used, type=bool, default=0, but dependent on CMake options, group=pico_float + target_compile_definitions(pico_float_compiler INTERFACE + PICO_FLOAT_COMPILER=1 + ) + + add_library(pico_float_headers INTERFACE) + target_include_directories(pico_float_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + # add alias "default" which is just rom. + add_library(pico_float_default INTERFACE) + target_link_libraries(pico_float_default INTERFACE pico_float_pico) + + set(PICO_DEFAULT_FLOAT_IMPL pico_float_default) + + target_link_libraries(pico_float INTERFACE + $>,$,${PICO_DEFAULT_FLOAT_IMPL}>) + + add_library(pico_float_pico INTERFACE) + target_sources(pico_float_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_aeabi.S + ${CMAKE_CURRENT_LIST_DIR}/float_init_rom.c + ${CMAKE_CURRENT_LIST_DIR}/float_math.c + ${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim.S + ) + # PICO_BUILD_DEFINE: PICO_FLOAT_PICO, whether optimized pico/bootrom provided float support is being used, type=bool, default=1, but dependent on CMake options, group=pico_float + target_compile_definitions(pico_float_pico INTERFACE + PICO_FLOAT_PICO=1 + ) + + target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers) + + add_library(pico_float_none INTERFACE) + target_sources(pico_float_none INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_none.S + ) + + target_link_libraries(pico_float_none INTERFACE pico_float_headers) + + # PICO_BUILD_DEFINE: PICO_FLOAT_NONE, whether float support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_float + target_compile_definitions(pico_float_none INTERFACE + PICO_FLOAT_NONE=1 + ) + + function(wrap_float_functions TARGET) + pico_wrap_function(${TARGET} __aeabi_fadd) + pico_wrap_function(${TARGET} __aeabi_fdiv) + pico_wrap_function(${TARGET} __aeabi_fmul) + pico_wrap_function(${TARGET} __aeabi_frsub) + pico_wrap_function(${TARGET} __aeabi_fsub) + pico_wrap_function(${TARGET} __aeabi_cfcmpeq) + pico_wrap_function(${TARGET} __aeabi_cfrcmple) + pico_wrap_function(${TARGET} __aeabi_cfcmple) + pico_wrap_function(${TARGET} __aeabi_fcmpeq) + pico_wrap_function(${TARGET} __aeabi_fcmplt) + pico_wrap_function(${TARGET} __aeabi_fcmple) + pico_wrap_function(${TARGET} __aeabi_fcmpge) + pico_wrap_function(${TARGET} __aeabi_fcmpgt) + pico_wrap_function(${TARGET} __aeabi_fcmpun) + pico_wrap_function(${TARGET} __aeabi_i2f) + pico_wrap_function(${TARGET} __aeabi_l2f) + pico_wrap_function(${TARGET} __aeabi_ui2f) + pico_wrap_function(${TARGET} __aeabi_ul2f) + pico_wrap_function(${TARGET} __aeabi_f2iz) + pico_wrap_function(${TARGET} __aeabi_f2lz) + pico_wrap_function(${TARGET} __aeabi_f2uiz) + pico_wrap_function(${TARGET} __aeabi_f2ulz) + pico_wrap_function(${TARGET} __aeabi_f2d) + pico_wrap_function(${TARGET} sqrtf) + pico_wrap_function(${TARGET} cosf) + pico_wrap_function(${TARGET} sinf) + pico_wrap_function(${TARGET} tanf) + pico_wrap_function(${TARGET} atan2f) + pico_wrap_function(${TARGET} expf) + pico_wrap_function(${TARGET} logf) + + pico_wrap_function(${TARGET} ldexpf) + pico_wrap_function(${TARGET} copysignf) + pico_wrap_function(${TARGET} truncf) + pico_wrap_function(${TARGET} floorf) + pico_wrap_function(${TARGET} ceilf) + pico_wrap_function(${TARGET} roundf) + pico_wrap_function(${TARGET} sincosf) # gnu + pico_wrap_function(${TARGET} asinf) + pico_wrap_function(${TARGET} acosf) + pico_wrap_function(${TARGET} atanf) + pico_wrap_function(${TARGET} sinhf) + pico_wrap_function(${TARGET} coshf) + pico_wrap_function(${TARGET} tanhf) + pico_wrap_function(${TARGET} asinhf) + pico_wrap_function(${TARGET} acoshf) + pico_wrap_function(${TARGET} atanhf) + pico_wrap_function(${TARGET} exp2f) + pico_wrap_function(${TARGET} log2f) + pico_wrap_function(${TARGET} exp10f) + pico_wrap_function(${TARGET} log10f) + pico_wrap_function(${TARGET} powf) + pico_wrap_function(${TARGET} powintf) #gnu + pico_wrap_function(${TARGET} hypotf) + pico_wrap_function(${TARGET} cbrtf) + pico_wrap_function(${TARGET} fmodf) + pico_wrap_function(${TARGET} dremf) + pico_wrap_function(${TARGET} remainderf) + pico_wrap_function(${TARGET} remquof) + pico_wrap_function(${TARGET} expm1f) + pico_wrap_function(${TARGET} log1pf) + pico_wrap_function(${TARGET} fmaf) + endfunction() + + wrap_float_functions(pico_float_pico) + wrap_float_functions(pico_float_none) + + macro(pico_set_float_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_FLOAT_IMPL "pico_float_${IMPL}") + else() + message(FATAL_ERROR "float implementation must be set on executable not library") + endif() + endmacro() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S new file mode 100644 index 00000000000..2aee5f250ad --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S @@ -0,0 +1,724 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "pico/bootrom/sf_table.h" + +__pre_init __aeabi_float_init, 00020 + +.syntax unified +.cpu cortex-m0plus +.thumb + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro float_wrapper_section func +float_section WRAPPER_FUNC_NAME(\func) +.endm + +.macro _float_wrapper_func x + wrapper_func \x +.endm + +.macro wrapper_func_f1 x + _float_wrapper_func \x +#if PICO_FLOAT_PROPAGATE_NANS + mov ip, lr + bl __check_nan_f1 + mov lr, ip +#endif +.endm + +.macro wrapper_func_f2 x + _float_wrapper_func \x +#if PICO_FLOAT_PROPAGATE_NANS + mov ip, lr + bl __check_nan_f2 + mov lr, ip +#endif +.endm + +.section .text + +#if PICO_FLOAT_PROPAGATE_NANS +.thumb_func +__check_nan_f1: + movs r3, #1 + lsls r3, #24 + lsls r2, r0, #1 + adds r2, r3 + bhi 1f + bx lr +1: + bx ip + +.thumb_func +__check_nan_f2: + movs r3, #1 + lsls r3, #24 + lsls r2, r0, #1 + adds r2, r3 + bhi 1f + lsls r2, r1, #1 + adds r2, r3 + bhi 2f + bx lr +2: + mov r0, r1 +1: + bx ip +#endif + +.macro table_tail_call SF_TABLE_OFFSET +#if PICO_FLOAT_SUPPORT_ROM_V1 +#ifndef NDEBUG + movs r3, #0 + mov ip, r3 +#endif +#endif + ldr r3, =sf_table + ldr r3, [r3, #\SF_TABLE_OFFSET] + bx r3 +.endm + +.macro shimmable_table_tail_call SF_TABLE_OFFSET shim + ldr r3, =sf_table + ldr r3, [r3, #\SF_TABLE_OFFSET] +#if PICO_FLOAT_SUPPORT_ROM_V1 + mov ip, pc +#endif + bx r3 +#if PICO_FLOAT_SUPPORT_ROM_V1 +.byte \SF_TABLE_OFFSET, 0xdf +.word \shim +#endif +.endm + + +# note generally each function is in a separate section unless there is fall thru or branching between them +# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool + +# note functions are word aligned except where they are an odd number of linear instructions + +// float FUNC_NAME(__aeabi_fadd)(float, float) single-precision addition +float_wrapper_section __aeabi_farithmetic +// float FUNC_NAME(__aeabi_frsub)(float x, float y) single-precision reverse subtraction, y - x + +# frsub first because it is the only one that needs alignment +.align 2 +wrapper_func __aeabi_frsub + eors r0, r1 + eors r1, r0 + eors r0, r1 + // fall thru + +// float FUNC_NAME(__aeabi_fsub)(float x, float y) single-precision subtraction, x - y +wrapper_func_f2 __aeabi_fsub +#if PICO_FLOAT_PROPAGATE_NANS + // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost + mov r2, r0 + eors r2, r1 + bmi 1f // different signs + push {r0, r1, lr} + bl 1f + b fdiv_fsub_nan_helper +1: +#endif + table_tail_call SF_TABLE_FSUB + +wrapper_func_f2 __aeabi_fadd + table_tail_call SF_TABLE_FADD + +// float FUNC_NAME(__aeabi_fdiv)(float n, float d) single-precision division, n / d +wrapper_func_f2 __aeabi_fdiv +#if PICO_FLOAT_PROPAGATE_NANS + push {r0, r1, lr} + bl 1f + b fdiv_fsub_nan_helper +1: +#endif + table_tail_call SF_TABLE_FDIV + +fdiv_fsub_nan_helper: +#if PICO_FLOAT_PROPAGATE_NANS + pop {r1, r2} + + // check for infinite op infinite (or rather check for infinite result with both + // operands being infinite) + lsls r3, r0, #1 + asrs r3, r3, #24 + adds r3, #1 + beq 2f + pop {pc} +2: + lsls r1, #1 + asrs r1, r1, #24 + lsls r2, #1 + asrs r2, r2, #24 + ands r1, r2 + adds r1, #1 + bne 3f + // infinite to nan + movs r1, #1 + lsls r1, #22 + orrs r0, r1 +3: + pop {pc} +#endif + +// float FUNC_NAME(__aeabi_fmul)(float, float) single-precision multiplication +wrapper_func_f2 __aeabi_fmul +#if PICO_FLOAT_PROPAGATE_NANS + push {r0, r1, lr} + bl 1f + pop {r1, r2} + + // check for multiplication of infinite by zero (or rather check for infinite result with either + // operand 0) + lsls r3, r0, #1 + asrs r3, r3, #24 + adds r3, #1 + beq 2f + pop {pc} +2: + ands r1, r2 + bne 3f + // infinite to nan + movs r1, #1 + lsls r1, #22 + orrs r0, r1 +3: + pop {pc} +1: +#endif + table_tail_call SF_TABLE_FMUL + +// void FUNC_NAME(__aeabi_cfrcmple)(float, float) reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags +float_wrapper_section __aeabi_cfcmple +.align 2 +wrapper_func __aeabi_cfrcmple + push {r0-r2, lr} + eors r0, r1 + eors r1, r0 + eors r0, r1 + b __aeabi_cfcmple_guts + +// NOTE these share an implementation as we have no excepting NaNs. +// void FUNC_NAME(__aeabi_cfcmple)(float, float) 3-way (<, =, ?>) compare [1], result in PSR ZC flags +// void FUNC_NAME(__aeabi_cfcmpeq)(float, float) non-excepting equality comparison [1], result in PSR ZC flags +.align 2 +wrapper_func __aeabi_cfcmple +wrapper_func __aeabi_cfcmpeq + push {r0-r2, lr} + +__aeabi_cfcmple_guts: + lsls r2,r0,#1 + lsrs r2,#24 + beq 1f + cmp r2,#0xff + bne 2f + lsls r2, r0, #9 + bhi 3f +1: + lsrs r0,#23 @ clear mantissa if denormal or infinite + lsls r0,#23 +2: + lsls r2,r1,#1 + lsrs r2,#24 + beq 1f + cmp r2,#0xff + bne 2f + lsls r2, r1, #9 + bhi 3f +1: + lsrs r1,#23 @ clear mantissa if denormal or infinite + lsls r1,#23 +2: + movs r2,#1 @ initialise result + eors r1,r0 + bmi 2f @ opposite signs? then can proceed on basis of sign of x + eors r1,r0 @ restore y + bpl 1f + cmp r1,r0 + pop {r0-r2, pc} +1: + cmp r0,r1 + pop {r0-r2, pc} +2: + orrs r1, r0 @ handle 0/-0 + adds r1, r1 @ note this always sets C + beq 3f + mvns r0, r0 @ carry inverse of r0 sign + adds r0, r0 +3: + pop {r0-r2, pc} + + +// int FUNC_NAME(__aeabi_fcmpeq)(float, float) result (1, 0) denotes (=, ?<>) [2], use for C == and != +float_wrapper_section __aeabi_fcmpeq +.align 2 +wrapper_func __aeabi_fcmpeq + push {lr} + bl __aeabi_cfcmpeq + beq 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_fcmplt)(float, float) result (1, 0) denotes (<, ?>=) [2], use for C < +float_wrapper_section __aeabi_fcmplt +.align 2 +wrapper_func __aeabi_fcmplt + push {lr} + bl __aeabi_cfcmple + sbcs r0, r0 + pop {pc} + +// int FUNC_NAME(__aeabi_fcmple)(float, float) result (1, 0) denotes (<=, ?>) [2], use for C <= +float_wrapper_section __aeabi_fcmple +.align 2 +wrapper_func __aeabi_fcmple + push {lr} + bl __aeabi_cfcmple + bls 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_fcmpge)(float, float) result (1, 0) denotes (>=, ?<) [2], use for C >= +float_wrapper_section __aeabi_fcmpge +.align 2 +wrapper_func __aeabi_fcmpge + push {lr} + // because of NaNs it is better to reverse the args than the result + bl __aeabi_cfrcmple + bls 1f + movs r0, #0 + pop {pc} +1: + movs r0, #1 + pop {pc} + +// int FUNC_NAME(__aeabi_fcmpgt)(float, float) result (1, 0) denotes (>, ?<=) [2], use for C > +float_wrapper_section __aeabi_fcmpgt +wrapper_func __aeabi_fcmpgt + push {lr} + // because of NaNs it is better to reverse the args than the result + bl __aeabi_cfrcmple + sbcs r0, r0 + pop {pc} + +// int FUNC_NAME(__aeabi_fcmpun)(float, float) result (1, 0) denotes (?, <=>) [2], use for C99 isunordered() +float_wrapper_section __aeabi_fcmpun +wrapper_func __aeabi_fcmpun + movs r3, #1 + lsls r3, #24 + lsls r2, r0, #1 + adds r2, r3 + bhi 1f + lsls r2, r1, #1 + adds r2, r3 + bhi 1f + movs r0, #0 + bx lr +1: + movs r0, #1 + bx lr + + +// float FUNC_NAME(__aeabi_ui2f)(unsigned) unsigned to float (single precision) conversion +float_wrapper_section __aeabi_ui2f +wrapper_func __aeabi_ui2f + subs r1, r1 + cmp r0, #0 + bne __aeabi_i2f_main + mov r0, r1 + bx lr + +float_wrapper_section __aeabi_i2f +// float FUNC_NAME(__aeabi_i2f)(int) integer to float (single precision) conversion +wrapper_func __aeabi_i2f + lsrs r1, r0, #31 + lsls r1, #31 + bpl 1f + rsbs r0, #0 +1: + cmp r0, #0 + beq 7f +__aeabi_i2f_main: + + mov ip, lr + push {r0, r1} + ldr r3, =sf_clz_func + ldr r3, [r3] + blx r3 + pop {r1, r2} + lsls r1, r0 + subs r0, #158 + rsbs r0, #0 + + adds r1,#0x80 @ rounding + bcs 5f @ tripped carry? then have leading 1 in C as required (and result is even so can ignore sticky bits) + + lsls r3,r1,#24 @ check bottom 8 bits of r1 + beq 6f @ in rounding-tie case? + lsls r1,#1 @ remove leading 1 +3: + lsrs r1,#9 @ align mantissa + lsls r0,#23 @ align exponent + orrs r0,r2 @ assemble exponent and mantissa +4: + orrs r0,r1 @ apply sign +1: + bx ip +5: + adds r0,#1 @ correct exponent offset + b 3b +6: + lsrs r1,#9 @ ensure even result + lsls r1,#10 + b 3b +7: + bx lr + + +// int FUNC_NAME(__aeabi_f2iz)(float) float (single precision) to integer C-style conversion [3] +float_wrapper_section __aeabi_f2iz +wrapper_func __aeabi_f2iz +regular_func float2int_z + lsls r1, r0, #1 + lsrs r2, r1, #24 + movs r3, #0x80 + lsls r3, #24 + cmp r2, #126 + ble 1f + subs r2, #158 + bge 2f + asrs r1, r0, #31 + lsls r0, #9 + lsrs r0, #1 + orrs r0, r3 + negs r2, r2 + lsrs r0, r2 + lsls r1, #1 + adds r1, #1 + muls r0, r1 + bx lr +1: + movs r0, #0 + bx lr +2: + lsrs r0, #31 + adds r0, r3 + subs r0, #1 + bx lr + + cmn r0, r0 + bcc float2int + push {lr} + lsls r0, #1 + lsrs r0, #1 + movs r1, #0 + bl __aeabi_f2uiz + cmp r0, #0 + bmi 1f + rsbs r0, #0 + pop {pc} +1: + movs r0, #128 + lsls r0, #24 + pop {pc} + +float_section float2int +regular_func float2int + shimmable_table_tail_call SF_TABLE_FLOAT2INT float2int_shim + +float_section float2fix +regular_func float2fix + shimmable_table_tail_call SF_TABLE_FLOAT2FIX float2fix_shim + +float_section float2ufix +regular_func float2ufix + table_tail_call SF_TABLE_FLOAT2UFIX + +// unsigned FUNC_NAME(__aeabi_f2uiz)(float) float (single precision) to unsigned C-style conversion [3] +float_wrapper_section __aeabi_f2uiz +wrapper_func __aeabi_f2uiz + table_tail_call SF_TABLE_FLOAT2UINT + +float_section fix2float +regular_func fix2float + table_tail_call SF_TABLE_FIX2FLOAT + +float_section ufix2float +regular_func ufix2float + table_tail_call SF_TABLE_UFIX2FLOAT + +float_section fix642float +regular_func fix642float + shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642float_shim + +float_section ufix642float +regular_func ufix642float + shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642float_shim + +// float FUNC_NAME(__aeabi_l2f)(long long) long long to float (single precision) conversion +float_wrapper_section __aeabi_l2f +1: + ldr r2, =__aeabi_i2f + bx r2 +wrapper_func __aeabi_l2f + asrs r2, r0, #31 + cmp r1, r2 + beq 1b + shimmable_table_tail_call SF_TABLE_INT642FLOAT int642float_shim + +// float FUNC_NAME(__aeabi_l2f)(long long) long long to float (single precision) conversion +float_wrapper_section __aeabi_ul2f +1: + ldr r2, =__aeabi_ui2f + bx r2 +wrapper_func __aeabi_ul2f + cmp r1, #0 + beq 1b + shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642float_shim + +// long long FUNC_NAME(__aeabi_f2lz)(float) float (single precision) to long long C-style conversion [3] +float_wrapper_section __aeabi_f2lz +wrapper_func __aeabi_f2lz +regular_func float2int64_z + cmn r0, r0 + bcc float2int64 + push {lr} + lsls r0, #1 + lsrs r0, #1 + movs r1, #0 + bl float2ufix64 + cmp r1, #0 + bmi 1f + movs r2, #0 + rsbs r0, #0 + sbcs r2, r1 + mov r1, r2 + pop {pc} +1: + movs r1, #128 + lsls r1, #24 + movs r0, #0 + pop {pc} + +float_section float2int64 +regular_func float2int64 + shimmable_table_tail_call SF_TABLE_FLOAT2INT64 float2int64_shim + +float_section float2fix64 +regular_func float2fix64 + shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 float2fix64_shim + +// unsigned long long FUNC_NAME(__aeabi_f2ulz)(float) float to unsigned long long C-style conversion [3] +float_wrapper_section __aeabi_f2ulz +wrapper_func __aeabi_f2ulz + shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 float2uint64_shim + +float_section float2ufix64 +regular_func float2ufix64 + shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 float2ufix64_shim + +float_wrapper_section __aeabi_f2d +1: +#if PICO_FLOAT_PROPAGATE_NANS + // copy sign bit and 25 NAN id bits into sign bit and significant ID bits, also setting the high id bit + asrs r1, r0, #3 + movs r2, #0xf + lsls r2, #27 + orrs r1, r2 + lsls r0, #25 + bx lr +#endif +wrapper_func __aeabi_f2d +#if PICO_FLOAT_PROPAGATE_NANS + movs r3, #1 + lsls r3, #24 + lsls r2, r0, #1 + adds r2, r3 + bhi 1b +#endif + shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE float2double_shim + +float_wrapper_section srqtf +wrapper_func_f1 sqrtf +#if PICO_FLOAT_SUPPORT_ROM_V1 + // check for negative + asrs r1, r0, #23 + bmi 1f +#endif + table_tail_call SF_TABLE_FSQRT +#if PICO_FLOAT_SUPPORT_ROM_V1 +1: + mvns r0, r1 + cmp r0, #255 + bne 2f + // -0 or -Denormal return -0 (0x80000000) + lsls r0, #31 + bx lr +2: + // return -Inf (0xff800000) + asrs r0, r1, #31 + lsls r0, #23 + bx lr +#endif + +float_wrapper_section cosf +// note we don't use _f1 since we do an infinity/nan check for outside of range +wrapper_func cosf + // rom version only works for -128 < angle < 128 + lsls r1, r0, #1 + lsrs r1, #24 + cmp r1, #127 + 7 + bge 1f +2: + table_tail_call SF_TABLE_FCOS +1: +#if PICO_FLOAT_PROPAGATE_NANS + // also check for infinites + cmp r1, #255 + bne 3f + // infinite to nan + movs r1, #1 + lsls r1, #22 + orrs r0, r1 + bx lr +3: +#endif + ldr r1, =0x40c90fdb // 2 * M_PI + push {lr} + bl remainderf + pop {r1} + mov lr, r1 + b 2b + +float_wrapper_section sinf +// note we don't use _f1 since we do an infinity/nan check for outside of range +wrapper_func sinf + // rom version only works for -128 < angle < 128 + lsls r1, r0, #1 + lsrs r1, #24 + cmp r1, #127 + 7 + bge 1f +2: + table_tail_call SF_TABLE_FSIN +1: +#if PICO_FLOAT_PROPAGATE_NANS + // also check for infinites + cmp r1, #255 + bne 3f + // infinite to nan + movs r1, #1 + lsls r1, #22 + orrs r0, r1 + bx lr +3: +#endif + ldr r1, =0x40c90fdb // 2 * M_PI + push {lr} + bl remainderf + pop {r1} + mov lr, r1 + b 2b + +float_wrapper_section sincosf +// note we don't use _f1 since we do an infinity/nan check for outside of range +wrapper_func sincosf + push {r1, r2, lr} + // rom version only works for -128 < angle < 128 + lsls r3, r0, #1 + lsrs r3, #24 + cmp r3, #127 + 7 + bge 3f +2: + ldr r3, =sf_table + ldr r3, [r3, #SF_TABLE_FSIN] + blx r3 + pop {r2, r3} + str r0, [r2] + str r1, [r3] + pop {pc} +#if PICO_FLOAT_PROPAGATE_NANS +.align 2 + pop {pc} +#endif +3: +#if PICO_FLOAT_PROPAGATE_NANS + // also check for infinites + cmp r3, #255 + bne 4f + // infinite to nan + movs r3, #1 + lsls r3, #22 + orrs r0, r3 + str r0, [r1] + str r0, [r2] + add sp, #12 + bx lr +4: +#endif + ldr r1, =0x40c90fdb // 2 * M_PI + push {lr} + bl remainderf + pop {r1} + mov lr, r1 + b 2b + +float_wrapper_section tanf +// note we don't use _f1 since we do an infinity/nan check for outside of range +wrapper_func tanf + // rom version only works for -128 < angle < 128 + lsls r1, r0, #1 + lsrs r1, #24 + cmp r1, #127 + 7 + bge 1f +2: + table_tail_call SF_TABLE_FTAN +1: +#if PICO_FLOAT_PROPAGATE_NANS + // also check for infinites + cmp r1, #255 + bne 3f + // infinite to nan + movs r1, #1 + lsls r1, #22 + orrs r0, r1 + bx lr +3: +#endif + ldr r1, =0x40c90fdb // 2 * M_PI + push {lr} + bl remainderf + pop {r1} + mov lr, r1 + b 2b + +float_wrapper_section atan2f +wrapper_func_f2 atan2f + shimmable_table_tail_call SF_TABLE_FATAN2 fatan2_shim + +float_wrapper_section expf +wrapper_func_f1 expf + table_tail_call SF_TABLE_FEXP + +float_wrapper_section logf +wrapper_func_f1 logf + table_tail_call SF_TABLE_FLN diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c new file mode 100644 index 00000000000..3dbefa67465 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "pico/bootrom.h" +#include "pico/bootrom/sf_table.h" + +// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE... +// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE +uint32_t sf_table[SF_TABLE_V2_SIZE / 2]; +void *sf_clz_func; + +#if !PICO_FLOAT_SUPPORT_ROM_V1 +static __attribute__((noreturn)) void missing_float_func_shim() { + panic(""); +} +#endif + +void __aeabi_float_init() { + int rom_version = rp2040_rom_version(); + void *rom_table = rom_data_lookup(rom_table_code('S', 'F')); +#if PICO_FLOAT_SUPPORT_ROM_V1 + if (rom_version == 1) { + memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE); + extern void float_table_shim_on_use_helper(); + // todo replace NDEBUG with a more exclusive assertion guard +#ifndef NDEBUG + if (*(uint16_t *)0x29ee != 0x0fc4 || // this is packx + *(uint16_t *)0x29c0 != 0x0dc2 || // this is upackx + *(uint16_t *)0x2b96 != 0xb5c0 || // this is cordic_vec + *(uint16_t *)0x2b18 != 0x2500 || // this is packretns + *(uint16_t *)0x2acc != 0xb510 || // this is float2fix + *(uint32_t *)0x2cfc != 0x6487ed51 // pi_q29 + ) { + panic(""); + } +#endif + + // this is a little tricky.. we only want to pull in a shim if the corresponding function + // is called. to that end we include a SVC instruction with the table offset as the call number + // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper + // function is garbage collected, so is the shim function. + // + // float_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address + // pointed to by IP and patches the float_table entry with the real shim the first time the function is called. + + for(uint i=SF_TABLE_V1_SIZE/4; i= 2) { + assert(*((uint8_t *)(rom_table-2)) * 4 >= SF_TABLE_V2_SIZE); + memcpy(&sf_table, rom_table, SF_TABLE_V2_SIZE); + } + sf_clz_func = rom_func_lookup(rom_table_code('L', '3')); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c new file mode 100644 index 00000000000..e54c8688039 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c @@ -0,0 +1,565 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/types.h" +#include "pico/float.h" +#include "pico/platform.h" + +typedef uint32_t ui32; +typedef int32_t i32; + +#define PINF ( HUGE_VAL) +#define MINF (-HUGE_VAL) +#define NANF ((float)NAN) +#define PZERO (+0.0) +#define MZERO (-0.0) + +#define PI 3.14159265358979323846 +#define LOG2 0.69314718055994530941 +// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers +#define LOG10 2.30258509299404568401 +#define LOG2E 1.44269504088896340737 +#define LOG10E 0.43429448190325182765 +#define ONETHIRD 0.33333333333333333333 + +#define PIf 3.14159265358979323846f +#define LOG2f 0.69314718055994530941f +#define LOG2Ef 1.44269504088896340737f +#define LOG10Ef 0.43429448190325182765f +#define ONETHIRDf 0.33333333333333333333f + +#define FUNPACK(x,e,m) e=((x)>>23)&0xff,m=((x)&0x007fffff)|0x00800000 +#define FUNPACKS(x,s,e,m) s=((x)>>31),FUNPACK((x),(e),(m)) + +_Pragma("GCC diagnostic push") +_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"") + +static inline bool fisnan(float x) { + ui32 ix=*(i32*)&x; + return ix * 2 > 0xff000000u; +} + +#if PICO_FLOAT_PROPAGATE_NANS +#define check_nan_f1(x) if (fisnan((x))) return (x) +#define check_nan_f2(x,y) if (fisnan((x))) return (x); else if (fisnan((y))) return (y); +#else +#define check_nan_f1(x) ((void)0) +#define check_nan_f2(x,y) ((void)0) +#endif + +static inline int fgetsignexp(float x) { + ui32 ix=*(ui32*)&x; + return (ix>>23)&0x1ff; +} + +static inline int fgetexp(float x) { + ui32 ix=*(ui32*)&x; + return (ix>>23)&0xff; +} + +static inline float fldexp(float x,int de) { + ui32 ix=*(ui32*)&x,iy; + int e; + e=fgetexp(x); + if(e==0||e==0xff) return x; + e+=de; + if(e<=0) iy=ix&0x80000000; // signed zero for underflow + else if(e>=0xff) iy=(ix&0x80000000)|0x7f800000ULL; // signed infinity on overflow + else iy=ix+((ui32)de<<23); + return *(float*)&iy; +} + +float WRAPPER_FUNC(ldexpf)(float x, int de) { + check_nan_f1(x); + return fldexp(x, de); +} + +static inline float fcopysign(float x,float y) { + ui32 ix=*(ui32*)&x,iy=*(ui32*)&y; + ix=((ix&0x7fffffff)|(iy&0x80000000)); + return *(float*)&ix; +} + +float WRAPPER_FUNC(copysignf)(float x, float y) { + check_nan_f2(x,y); + return fcopysign(x, y); +} + +static inline int fiszero(float x) { return fgetexp (x)==0; } +static inline int fispzero(float x) { return fgetsignexp(x)==0; } +static inline int fismzero(float x) { return fgetsignexp(x)==0x100; } +static inline int fisinf(float x) { return fgetexp (x)==0xff; } +static inline int fispinf(float x) { return fgetsignexp(x)==0xff; } +static inline int fisminf(float x) { return fgetsignexp(x)==0x1ff; } + +static inline int fisint(float x) { + ui32 ix=*(ui32*)&x,m; + int e=fgetexp(x); + if(e==0) return 1; // 0 is an integer + e-=0x7f; // remove exponent bias + if(e<0) return 0; // |x|<1 + e=23-e; // bit position in mantissa with significance 1 + if(e<=0) return 1; // |x| large, so must be an integer + m=(1<>e)&1; +} + +static inline int fisstrictneg(float x) { + ui32 ix=*(ui32*)&x; + if(fiszero(x)) return 0; + return ix>>31; +} + +static inline int fisneg(float x) { + ui32 ix=*(ui32*)&x; + return ix>>31; +} + +static inline float fneg(float x) { + ui32 ix=*(ui32*)&x; + ix^=0x80000000; + return *(float*)&ix; +} + +static inline int fispo2(float x) { + ui32 ix=*(ui32*)&x; + if(fiszero(x)) return 0; + if(fisinf(x)) return 0; + ix&=0x007fffff; + return ix==0; +} + +static inline float fnan_or(float x) { +#if PICO_FLOAT_PROPAGATE_NANS + return NANF; +#else + return x; +#endif +} + +float WRAPPER_FUNC(truncf)(float x) { + check_nan_f1(x); + ui32 ix=*(ui32*)&x,m; + int e=fgetexp(x); + e-=0x7f; // remove exponent bias + if(e<0) { // |x|<1 + ix&=0x80000000; + return *(float*)&ix; + } + e=23-e; // bit position in mantissa with significance 1 + if(e<=0) return x; // |x| large, so must be an integer + m=(1<=4+0x7f) { // |x|>=16? + if(!fisneg(x)) return 1; // 1 << exp 2x; avoid generating infinities later + else return -1; // 1 >> exp 2x + } + u=expf(fldexp(x,1)); + return (u-1.0f)/(u+1.0f); +} + +float WRAPPER_FUNC(asinhf)(float x) { + check_nan_f1(x); + int e; + e=fgetexp(x); + if(e>=16+0x7f) { // |x|>=2^16? + if(!fisneg(x)) return logf( x )+LOG2f; // 1/x^2 << 1 + else return fneg(logf(fneg(x))+LOG2f); // 1/x^2 << 1 + } + if(x>0) return (float)log(sqrt((double)x*(double)x+1.0)+(double)x); + else return fneg((float)log(sqrt((double)x*(double)x+1.0)-(double)x)); +} + +float WRAPPER_FUNC(acoshf)(float x) { + check_nan_f1(x); + int e; + if(fisneg(x)) x=fneg(x); + e=fgetexp(x); + if(e>=16+0x7f) return logf(x)+LOG2f; // |x|>=2^16? + return (float)log(sqrt(((double)x+1.0)*((double)x-1.0))+(double)x); +} + +float WRAPPER_FUNC(atanhf)(float x) { + check_nan_f1(x); + return fldexp(logf((1.0f+x)/(1.0f-x)),-1); +} + +float WRAPPER_FUNC(exp2f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG2); } +float WRAPPER_FUNC(log2f)(float x) { check_nan_f1(x); return logf(x)*LOG2Ef; } +float WRAPPER_FUNC(exp10f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG10); } +float WRAPPER_FUNC(log10f)(float x) { check_nan_f1(x); return logf(x)*LOG10Ef; } + +float WRAPPER_FUNC(expm1f)(float x) { check_nan_f1(x); return (float)(exp((double)x)-1); } +float WRAPPER_FUNC(log1pf)(float x) { check_nan_f1(x); return (float)(log(1+(double)x)); } +float WRAPPER_FUNC(fmaf)(float x,float y,float z) { + check_nan_f2(x,y); + check_nan_f1(z); + return (float)((double)x*(double)y+(double)z); +} // has double rounding so not exact + +// general power, x>0 +static inline float fpow_1(float x,float y) { + return (float)exp(log((double)x)*(double)y); // using double-precision intermediates for better accuracy +} + +static float fpow_int2(float x,int y) { + float u; + if(y==1) return x; + u=fpow_int2(x,y/2); + u*=u; + if(y&1) u*=x; + return u; +} + +// for the case where x not zero or infinity, y small and not zero +static inline float fpowint_1(float x,int y) { + if(y<0) x=1.0f/x,y=-y; + return fpow_int2(x,y); +} + +// for the case where x not zero or infinity +static float fpowint_0(float x,int y) { + int e; + if(fisneg(x)) { + if(fisoddint(y)) return fneg(fpowint_0(fneg(x),y)); + else return fpowint_0(fneg(x),y); + } + if(fispo2(x)) { + e=fgetexp(x)-0x7f; + if(y>=256) y= 255; // avoid overflow + if(y<-256) y=-256; + y*=e; + return fldexp(1,y); + } + if(y==0) return 1; + if(y>=-32&&y<=32) return fpowint_1(x,y); + return fpow_1(x,y); +} + +float WRAPPER_FUNC(powintf)(float x,int y) { + _Pragma("GCC diagnostic push") + _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") + if(x==1.0f||y==0) return 1; + if(x==0.0f) { + if(y>0) { + if(y&1) return x; + else return 0; + } + if((y&1)) return fcopysign(PINF,x); + return PINF; + } + _Pragma("GCC diagnostic pop") + check_nan_f1(x); + if(fispinf(x)) { + if(y<0) return 0; + else return PINF; + } + if(fisminf(x)) { + if(y>0) { + if((y&1)) return MINF; + else return PINF; + } + if((y&1)) return MZERO; + else return PZERO; + } + return fpowint_0(x,y); +} + +// for the case where y is guaranteed a finite integer, x not zero or infinity +static float fpow_0(float x,float y) { + int e,p; + if(fisneg(x)) { + if(fisoddint(y)) return fneg(fpow_0(fneg(x),y)); + else return fpow_0(fneg(x),y); + } + p=(int)y; + if(fispo2(x)) { + e=fgetexp(x)-0x7f; + if(p>=256) p= 255; // avoid overflow + if(p<-256) p=-256; + p*=e; + return fldexp(1,p); + } + if(p==0) return 1; + if(p>=-32&&p<=32) return fpowint_1(x,p); + return fpow_1(x,y); +} + +float WRAPPER_FUNC(powf)(float x,float y) { + _Pragma("GCC diagnostic push") + _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"") + if(x==1.0f||fiszero(y)) return 1; + check_nan_f2(x,y); + if(x==-1.0f&&fisinf(y)) return 1; + _Pragma("GCC diagnostic pop") + if(fiszero(x)) { + if(!fisneg(y)) { + if(fisoddint(y)) return x; + else return 0; + } + if(fisoddint(y)) return fcopysign(PINF,x); + return PINF; + } + if(fispinf(x)) { + if(fisneg(y)) return 0; + else return PINF; + } + if(fisminf(x)) { + if(!fisneg(y)) { + if(fisoddint(y)) return MINF; + else return PINF; + } + if(fisoddint(y)) return MZERO; + else return PZERO; + } + if(fispinf(y)) { + if(fgetexp(x)<0x7f) return PZERO; + else return PINF; + } + if(fisminf(y)) { + if(fgetexp(x)<0x7f) return PINF; + else return PZERO; + } + if(fisint(y)) return fpow_0(x,y); + if(fisneg(x)) return PINF; + return fpow_1(x,y); +} + +float WRAPPER_FUNC(hypotf)(float x,float y) { + check_nan_f2(x,y); + int ex,ey; + ex=fgetexp(x); ey=fgetexp(y); + if(ex>=0x7f+50||ey>=0x7f+50) { // overflow, or nearly so + x=fldexp(x,-70),y=fldexp(y,-70); + return fldexp(sqrtf(x*x+y*y), 70); + } + else if(ex<=0x7f-50&&ey<=0x7f-50) { // underflow, or nearly so + x=fldexp(x, 70),y=fldexp(y, 70); + return fldexp(sqrtf(x*x+y*y),-70); + } + return sqrtf(x*x+y*y); +} + +float WRAPPER_FUNC(cbrtf)(float x) { + check_nan_f1(x); + int e; + if(fisneg(x)) return fneg(cbrtf(fneg(x))); + if(fiszero(x)) return fcopysign(PZERO,x); + e=fgetexp(x)-0x7f; + e=(e*0x5555+0x8000)>>16; // ~e/3, rounded + x=fldexp(x,-e*3); + x=expf(logf(x)*ONETHIRDf); + return fldexp(x,e); +} + +// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo +// 2^23<=|mx|,my<2^24, e>=0; 0<=result0) { + r=0xffffffffU/(ui32)(my>>7); // reciprocal estimate Q16 + } + while(e>0) { + s=e; if(s>12) s=12; // gain up to 12 bits on each iteration + q=(mx>>9)*r; // Q30 + q=((q>>(29-s))+1)>>1; // Q(s), rounded + mx=(mx<=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my + if(mx>=my) mx-=my,quo++; + if(mx<0) mx+=my,quo--; + if(mx<0) mx+=my,quo--; + if(pquo) *pquo=quo; + return mx; +} + +float WRAPPER_FUNC(fmodf)(float x,float y) { + check_nan_f2(x,y); + ui32 ix=*(ui32*)&x,iy=*(ui32*)&y; + int sx,ex,ey; + i32 mx,my; + FUNPACKS(ix,sx,ex,mx); + FUNPACK(iy,ey,my); + if(ex==0xff) { + return fnan_or(PINF); + } + if(ey==0) return PINF; + if(ex==0) { + if(!fisneg(x)) return PZERO; + return MZERO; + } + if(ex|y|/2 + mx-=my+my; + ey--; + q=1; + } else { // x<-|y|/2 + mx=my+my-mx; + ey--; + q=-1; + } + } + else { + if(sx) mx=-mx; + mx=frem_0(mx,my,ex-ey,&q); + if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient? + mx-=my; + q++; + } + } + if(sy) q=-q; + if(quo) *quo=q; + return fix2float(mx,0x7f-ey+23); +} + +float WRAPPER_FUNC(dremf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); } + +float WRAPPER_FUNC(remainderf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); } + +_Pragma("GCC diagnostic pop") // strict-aliasing diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_none.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_none.S new file mode 100644 index 00000000000..743a75e3908 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_none.S @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "pico/bootrom/sf_table.h" + +.syntax unified +.cpu cortex-m0plus +.thumb + +wrapper_func __aeabi_fadd +wrapper_func __aeabi_fdiv +wrapper_func __aeabi_fmul +wrapper_func __aeabi_frsub +wrapper_func __aeabi_fsub +wrapper_func __aeabi_cfcmpeq +wrapper_func __aeabi_cfrcmple +wrapper_func __aeabi_cfcmple +wrapper_func __aeabi_fcmpeq +wrapper_func __aeabi_fcmplt +wrapper_func __aeabi_fcmple +wrapper_func __aeabi_fcmpge +wrapper_func __aeabi_fcmpgt +wrapper_func __aeabi_fcmpun +wrapper_func __aeabi_i2f +wrapper_func __aeabi_l2f +wrapper_func __aeabi_ui2f +wrapper_func __aeabi_ul2f +wrapper_func __aeabi_i2f +wrapper_func __aeabi_f2iz +wrapper_func __aeabi_f2lz +wrapper_func __aeabi_f2uiz +wrapper_func __aeabi_f2ulz +wrapper_func sqrtf +wrapper_func cosf +wrapper_func sinf +wrapper_func tanf +wrapper_func atan2f +wrapper_func expf +wrapper_func logf +wrapper_func ldexpf +wrapper_func copysignf +wrapper_func truncf +wrapper_func floorf +wrapper_func ceilf +wrapper_func roundf +wrapper_func sincosf +wrapper_func asinf +wrapper_func acosf +wrapper_func atanf +wrapper_func sinhf +wrapper_func coshf +wrapper_func tanhf +wrapper_func asinhf +wrapper_func acoshf +wrapper_func atanhf +wrapper_func exp2f +wrapper_func log2f +wrapper_func exp10f +wrapper_func log10f +wrapper_func powf +wrapper_func powintf +wrapper_func hypotf +wrapper_func cbrtf +wrapper_func fmodf +wrapper_func dremf +wrapper_func remainderf +wrapper_func remquof +wrapper_func expm1f +wrapper_func log1pf +wrapper_func fmaf + push {lr} // keep stack trace sane + ldr r0, =str + bl panic + +str: + .asciz "float support is disabled" \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_v1_rom_shim.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_v1_rom_shim.S new file mode 100644 index 00000000000..a29925ed376 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_v1_rom_shim.S @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" + +#if PICO_FLOAT_SUPPORT_ROM_V1 +.syntax unified +.cpu cortex-m0plus +.thumb + +#ifndef PICO_FLOAT_IN_RAM +#define PICO_FLOAT_IN_RAM 0 +#endif + +.macro float_section name +// todo separate flag for shims? +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +float_section float_table_shim_on_use_helper +regular_func float_table_shim_on_use_helper + push {r0-r2, lr} + mov r0, ip +#ifndef NDEBUG + // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro + cmp r0, #0 + bne 1f + bkpt #0 +#endif +1: + ldrh r1, [r0] + lsrs r2, r1, #8 + adds r0, #2 + cmp r2, #0xdf + bne 1b + uxtb r1, r1 // r1 holds table offset + lsrs r2, r0, #2 + bcc 1f + // unaligned + ldrh r2, [r0, #0] + ldrh r0, [r0, #2] + lsls r0, #16 + orrs r0, r2 + b 2f +1: + ldr r0, [r0] +2: + ldr r2, =sf_table + str r0, [r2, r1] + str r0, [sp, #12] + pop {r0-r2, pc} + +float_section 642float_shims + +@ convert uint64 to float, rounding +regular_func uint642float_shim + movs r2,#0 @ fall through + +@ convert unsigned 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 +regular_func ufix642float_shim + push {r4,r5,r14} + cmp r1,#0 + bpl 3f @ positive? we can use signed code + lsls r5,r1,#31 @ contribution to sticky bits + orrs r5,r0 + lsrs r0,r1,#1 + subs r2,#1 + b 4f + +@ convert int64 to float, rounding +regular_func int642float_shim + movs r2,#0 @ fall through + +@ convert signed 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 +regular_func fix642float_shim + push {r4,r5,r14} +3: + movs r5,r0 + orrs r5,r1 + beq ret_pop45 @ zero? return +0 + asrs r5,r1,#31 @ sign bits +2: + asrs r4,r1,#24 @ try shifting 7 bits at a time + cmp r4,r5 + bne 1f @ next shift will overflow? + lsls r1,#7 + lsrs r4,r0,#25 + orrs r1,r4 + lsls r0,#7 + adds r2,#7 + b 2b +1: + movs r5,r0 + movs r0,r1 +4: + rsbs r2,#0 + adds r2,#32+29 + + // bl packx + ldr r1, =0x29ef // packx + blx r1 +ret_pop45: + pop {r4,r5,r15} + +float_section fatan2_shim +regular_func fatan2_shim + push {r4,r5,r14} + + ldr r4, =0x29c1 // unpackx + mov ip, r4 +@ unpack arguments and shift one down to have common exponent + blx ip + mov r4,r0 + mov r0,r1 + mov r1,r4 + mov r4,r2 + mov r2,r3 + mov r3,r4 + blx ip + lsls r0,r0,#5 @ Q28 + lsls r1,r1,#5 @ Q28 + adds r4,r2,r3 @ this is -760 if both arguments are 0 and at least -380-126=-506 otherwise + asrs r4,#9 + adds r4,#1 + bmi 2f @ force y to 0 proper, so result will be zero + subs r4,r2,r3 @ calculate shift + bge 1f @ ex>=ey? + rsbs r4,#0 @ make shift positive + asrs r0,r4 + cmp r4,#28 + blo 3f + asrs r0,#31 + b 3f +1: + asrs r1,r4 + cmp r4,#28 + blo 3f +2: +@ here |x|>>|y| or both x and y are ±0 + cmp r0,#0 + bge 4f @ x positive, return signed 0 + ldr r3, =0x2cfc @ &pi_q29, circular coefficients + ldr r0,[r3] @ x negative, return +/- pi + asrs r1,#31 + eors r0,r1 + b 7f +4: + asrs r0,r1,#31 + b 7f +3: + movs r2,#0 @ initial angle + ldr r3, =0x2cfc @ &pi_q29, circular coefficients + cmp r0,#0 @ x negative + bge 5f + rsbs r0,#0 @ rotate to 1st/4th quadrants + rsbs r1,#0 + ldr r2,[r3] @ pi Q29 +5: + movs r4,#1 @ m=1 + ldr r5, =0x2b97 @ cordic_vec + blx r5 @ also produces magnitude (with scaling factor 1.646760119), which is discarded + mov r0,r2 @ result here is -pi/2..3pi/2 Q29 +@ asrs r2,#29 +@ subs r0,r2 + ldr r3, =0x2cfc @ &pi_q29, circular coefficients + ldr r2,[r3] @ pi Q29 + adds r4,r0,r2 @ attempt to fix -3pi/2..-pi case + bcs 6f @ -pi/2..0? leave result as is + subs r4,r0,r2 @ pi: take off 2pi +6: + subs r0,#1 @ fiddle factor so atan2(0,1)==0 +7: + movs r2,#0 @ exponent for pack + ldr r3, =0x2b19 + bx r3 + +float_section float232_shims + +regular_func float2int_shim + movs r1,#0 @ fall through +regular_func float2fix_shim + // check for -0 or -denormal upfront + asrs r2, r0, #23 + adds r2, #128 + adds r2, #128 + beq 1f + // call original + ldr r2, =0x2acd + bx r2 + 1: + movs r0, #0 + bx lr + +float_section float264_shims + +regular_func float2int64_shim + movs r1,#0 @ and fall through +regular_func float2fix64_shim + push {r14} + bl f2fix + b d2f64_a + +regular_func float2uint64_shim + movs r1,#0 @ and fall through +regular_func float2ufix64_shim + asrs r3,r0,#23 @ negative? return 0 + bmi ret_dzero +@ and fall through + +@ convert float in r0 to signed fixed point in r0:r1:r3, r1 places after point, rounding towards -Inf +@ result clamped so that r3 can only be 0 or -1 +@ trashes r12 +.thumb_func +f2fix: + push {r4,r14} + mov r12,r1 + asrs r3,r0,#31 + lsls r0,#1 + lsrs r2,r0,#24 + beq 1f @ zero? + cmp r2,#0xff @ Inf? + beq 2f + subs r1,r2,#1 + subs r2,#0x7f @ remove exponent bias + lsls r1,#24 + subs r0,r1 @ insert implied 1 + eors r0,r3 + subs r0,r3 @ top two's complement + asrs r1,r0,#4 @ convert to double format + lsls r0,#28 + ldr r4, =d2fix_a + bx r4 +1: + movs r0,#0 + movs r1,r0 + movs r3,r0 + pop {r4,r15} +2: + mvns r0,r3 @ return max/min value + mvns r1,r3 + pop {r4,r15} + +ret_dzero: + movs r0,#0 + movs r1,#0 + bx r14 + +float_section d2fix_a_float + +.weak d2fix_a // weak because it exists in float shims too +.thumb_func +d2fix_a: +@ here +@ r0:r1 two's complement mantissa +@ r2 unbaised exponent +@ r3 mantissa sign extension bits + add r2,r12 @ exponent plus offset for required binary point position + subs r2,#52 @ required shift + bmi 1f @ shift down? +@ here a shift up by r2 places + cmp r2,#12 @ will clamp? + bge 2f + movs r4,r0 + lsls r1,r2 + lsls r0,r2 + rsbs r2,#0 + adds r2,#32 @ complementary shift + lsrs r4,r2 + orrs r1,r4 + pop {r4,r15} +2: + mvns r0,r3 + mvns r1,r3 @ overflow: clamp to extreme fixed-point values + pop {r4,r15} +1: +@ here a shift down by -r2 places + adds r2,#32 + bmi 1f @ long shift? + mov r4,r1 + lsls r4,r2 + rsbs r2,#0 + adds r2,#32 @ complementary shift + asrs r1,r2 + lsrs r0,r2 + orrs r0,r4 + pop {r4,r15} +1: +@ here a long shift down + movs r0,r1 + asrs r1,#31 @ shift down 32 places + adds r2,#32 + bmi 1f @ very long shift? + rsbs r2,#0 + adds r2,#32 + asrs r0,r2 + pop {r4,r15} +1: + movs r0,r3 @ result very near zero: use sign extension bits + movs r1,r3 + pop {r4,r15} +d2f64_a: + asrs r2,r1,#31 + cmp r2,r3 + bne 1f @ sign extension bits fail to match sign of result? + pop {r15} +1: + mvns r0,r3 + movs r1,#1 + lsls r1,#31 + eors r1,r1,r0 @ generate extreme fixed-point values + pop {r15} + +float_section float2double_shim +regular_func float2double_shim + lsrs r3,r0,#31 @ sign bit + lsls r3,#31 + lsls r1,r0,#1 + lsrs r2,r1,#24 @ exponent + beq 1f @ zero? + cmp r2,#0xff @ Inf? + beq 2f + lsrs r1,#4 @ exponent and top 20 bits of mantissa + ldr r2,=#(0x3ff-0x7f)<<20 @ difference in exponent offsets + adds r1,r2 + orrs r1,r3 + lsls r0,#29 @ bottom 3 bits of mantissa + bx r14 +1: + movs r1,r3 @ return signed zero +3: + movs r0,#0 + bx r14 +2: + ldr r1,=#0x7ff00000 @ return signed infinity + adds r1,r3 + b 3b + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/pico/float.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/pico/float.h new file mode 100644 index 00000000000..8b06ea8c025 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/pico/float.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_FLOAT_H +#define _PICO_FLOAT_H + +#include +#include +#include "pico/types.h" +#include "pico/bootrom/sf_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file float.h +* \defgroup pico_float pico_float +* +* Optimized single-precision floating point functions +* +* (Replacement) optimized implementations are provided of the following compiler built-ins +* and math library functions: +* +* - __aeabi_fadd, __aeabi_fdiv, __aeabi_fmul, __aeabi_frsub, __aeabi_fsub, __aeabi_cfcmpeq, __aeabi_cfrcmple, __aeabi_cfcmple, __aeabi_fcmpeq, __aeabi_fcmplt, __aeabi_fcmple, __aeabi_fcmpge, __aeabi_fcmpgt, __aeabi_fcmpun, __aeabi_i2f, __aeabi_l2f, __aeabi_ui2f, __aeabi_ul2f, __aeabi_f2iz, __aeabi_f2lz, __aeabi_f2uiz, __aeabi_f2ulz, __aeabi_f2d, sqrtf, cosf, sinf, tanf, atan2f, expf, logf +* - ldexpf, copysignf, truncf, floorf, ceilf, roundf, asinf, acosf, atanf, sinhf, coshf, tanhf, asinhf, acoshf, atanhf, exp2f, log2f, exp10f, log10f, powf, hypotf, cbrtf, fmodf, dremf, remainderf, remquof, expm1f, log1pf, fmaf +* - powintf, sincosf (GNU extensions) +* +* The following additional optimized functions are also provided: +* +* - fix2float, ufix2float, fix642float, ufix642float, float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2int64, float2int_z, float2int64_z +*/ + +float fix2float(int32_t m, int e); +float ufix2float(uint32_t m, int e); +float fix642float(int64_t m, int e); +float ufix642float(uint64_t m, int e); + +// These methods round towards -Infinity. +int32_t float2fix(float f, int e); +uint32_t float2ufix(float f, int e); +int64_t float2fix64(float f, int e); +uint64_t float2ufix64(float f, int e); +int32_t float2int(float f); +int64_t float2int64(float f); + +// These methods round towards 0. +int32_t float2int_z(float f); +int64_t float2int64_z(float f); + +float exp10f(float x); +void sincosf(float x, float *sinx, float *cosx); +float powintf(float x, int y); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/CMakeLists.txt new file mode 100644 index 00000000000..b589bed22a6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/CMakeLists.txt @@ -0,0 +1,44 @@ +if (NOT TARGET pico_int64_ops) + + #shims for ROM functions for -lgcc functions (listed below) + add_library(pico_int64_ops INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_int64_ops_compiler INTERFACE) + # PICO_BUILD_DEFINE: PICO_INT64_OPS_COMPILER, whether compiler provided int64_ops multiplication support is being used, type=bool, default=0, but dependent on CMake options, group=pico_int64_ops + target_compile_definitions(pico_int64_ops_compiler INTERFACE + PICO_INT64_OPS_COMPILER=1 + ) + + # add alias "default" which is just pico. + add_library(pico_int64_ops_default INTERFACE) + target_link_libraries(pico_int64_ops_default INTERFACE pico_int64_ops_pico) + + set(PICO_DEFAULT_INT64_OPS_IMPL pico_int64_ops_default) + + target_link_libraries(pico_int64_ops INTERFACE + $>,$,${PICO_DEFAULT_INT64_OPS_IMPL}>) + + add_library(pico_int64_ops_pico INTERFACE) + target_include_directories(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_sources(pico_int64_ops_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/pico_int64_ops_aeabi.S + ) + + # PICO_BUILD_DEFINE: PICO_INT64_OPS_PICO, whether optimized pico/bootrom provided int64_ops multiplication support is being used, type=bool, default=1, but dependent on CMake options, group=pico_int64_ops + target_compile_definitions(pico_int64_ops_pico INTERFACE + PICO_INT64_OPS_PICO=1 + ) + + pico_wrap_function(pico_int64_ops_pico __aeabi_lmul) + + macro(pico_set_int64_ops_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_INT64_OPS_IMPL "pico_int64_ops_${IMPL}") + else() + message(FATAL_ERROR "int64_ops implementation must be set on executable not library") + endif() + endmacro() +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h new file mode 100644 index 00000000000..db3213ef92b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/include/pico/int64_ops.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_INT64_H +#define _PICO_INT64_H + +#include "pico/types.h" + +/** \file int64_ops.h + * \defgroup pico_int64_ops pico_int64_ops + * + * Optimized replacement implementations of the compiler built-in 64 bit multiplication + * + * This library does not provide any additional functions +*/ + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S new file mode 100644 index 00000000000..903820bff33 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.syntax unified +.cpu cortex-m0plus +.thumb + +#include "pico/asm_helper.S" + +.section SECTION_NAME(__aeabi_lmul) +wrapper_func __aeabi_lmul + muls r1, r2 + muls r3, r0 + adds r1, r3 + mov r12, r1 + lsrs r1, r2, #16 + uxth r3, r0 + muls r3, r1 + push {r4} + lsrs r4, r0, #16 + muls r1, r4 + uxth r2, r2 + uxth r0, r0 + muls r0, r2 + muls r2, r4 + lsls r4, r3, #16 + lsrs r3, #16 + adds r0, r4 + pop {r4} + adcs r1, r3 + lsls r3, r2, #16 + lsrs r2, #16 + adds r0, r3 + adcs r1, r2 + add r1, r12 + bx lr + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt new file mode 100644 index 00000000000..fddacc90c7a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt @@ -0,0 +1,14 @@ +if (NOT TARGET pico_malloc) + #shims for ROM functions for -lgcc functions (listed below) + add_library(pico_malloc INTERFACE) + + target_sources(pico_malloc INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/pico_malloc.c + ) + + pico_wrap_function(pico_malloc malloc) + pico_wrap_function(pico_malloc calloc) + pico_wrap_function(pico_malloc free) + + target_link_libraries(pico_malloc INTERFACE pico_sync) +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h new file mode 100644 index 00000000000..e84dd4d16cf --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_MALLOC_H +#define _PICO_MALLOC_H + +/** \file malloc.h +* \defgroup pico_malloc pico_malloc +* +* Multi-core safety for malloc, calloc and free +* +* This library does not provide any additional functions +*/ + +// PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc +#if PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX) +#define PICO_USE_MALLOC_MUTEX 1 +#endif + +// PICO_CONFIG: PICO_MALLOC_PANIC, Enable/disable panic when an allocation failure occurs, type=bool, default=1, group=pico_malloc +#ifndef PICO_MALLOC_PANIC +#define PICO_MALLOC_PANIC 1 +#endif + +// PICO_CONFIG: PICO_DEBUG_MALLOC, Enable/disable debug printf from malloc, type=bool, default=0, group=pico_malloc +#ifndef PICO_DEBUG_MALLOC +#define PICO_DEBUG_MALLOC 0 +#endif + +// PICO_CONFIG: PICO_DEBUG_MALLOC_LOW_WATER, Define the lower bound for allocation addresses to be printed by PICO_DEBUG_MALLOC, min=0, default=0, group=pico_malloc +#ifndef PICO_DEBUG_MALLOC_LOW_WATER +#define PICO_DEBUG_MALLOC_LOW_WATER 0 +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c new file mode 100644 index 00000000000..548a48b9e08 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "pico.h" + +#if PICO_USE_MALLOC_MUTEX +#include "pico/mutex.h" +auto_init_mutex(malloc_mutex); +#endif + +extern void *__real_malloc(size_t size); +extern void *__real_calloc(size_t count, size_t size); +extern void __real_free(void *mem); + +extern char __StackLimit; /* Set by linker. */ + +static inline void check_alloc(void *mem, uint8_t size) { +#if PICO_MALLOC_PANIC + if (!mem || (((char *)mem) + size) > &__StackLimit) { + panic("Out of memory"); + } +#endif +} + +void *__wrap_malloc(size_t size) { +#if PICO_USE_MALLOC_MUTEX + mutex_enter_blocking(&malloc_mutex); +#endif + void *rc = __real_malloc(size); +#if PICO_USE_MALLOC_MUTEX + mutex_exit(&malloc_mutex); +#endif +#ifdef PICO_DEBUG_MALLOC + if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { + printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size); + } +#endif + check_alloc(rc, size); + return rc; +} + +void *__wrap_calloc(size_t count, size_t size) { +#if PICO_USE_MALLOC_MUTEX + mutex_enter_blocking(&malloc_mutex); +#endif + void *rc = __real_calloc(count, size); +#if PICO_USE_MALLOC_MUTEX + mutex_exit(&malloc_mutex); +#endif +#ifdef PICO_DEBUG_MALLOC + if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { + printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size); + } +#endif + check_alloc(rc, size); + return rc; +} + +void __wrap_free(void *mem) { +#if PICO_USE_MALLOC_MUTEX + mutex_enter_blocking(&malloc_mutex); +#endif + __real_free(mem); +#if PICO_USE_MALLOC_MUTEX + mutex_exit(&malloc_mutex); +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt new file mode 100644 index 00000000000..20d410a361f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt @@ -0,0 +1,52 @@ +if (NOT TARGET pico_mem_ops) + #shims for ROM functions for -lgcc functions (listed below) + add_library(pico_mem_ops INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_mem_ops_compiler INTERFACE) + # PICO_BUILD_DEFINE: PICO_MEM_OPS_COMPILER, whether compiler provided mem_ops memcpy etc. support is being used, type=bool, default=0, but dependent on CMake options, group=pico_mem_ops + target_compile_definitions(pico_mem_ops_compiler INTERFACE + PICO_MEM_OPS_COMPILER=1 + ) + + # add alias "default" which is just pico. + add_library(pico_mem_ops_default INTERFACE) + target_link_libraries(pico_mem_ops_default INTERFACE pico_mem_ops_pico) + + set(PICO_DEFAULT_MEM_OPS_IMPL pico_mem_ops_default) + + add_library(pico_mem_ops_pico INTERFACE) + target_link_libraries(pico_mem_ops INTERFACE + $>,$,${PICO_DEFAULT_MEM_OPS_IMPL}>) + + # PICO_BUILD_DEFINE: PICO_MEM_OPS_PICO, whether optimized pico/bootrom provided mem_ops memcpy etc. support is being used, type=bool, default=1, but dependent on CMake options, group=pico_mem_ops + target_compile_definitions(pico_mem_ops_pico INTERFACE + PICO_MEM_OPS_PICO=1 + ) + + + target_sources(pico_mem_ops_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/mem_ops_aeabi.S + ) + + + target_link_libraries(pico_mem_ops INTERFACE pico_bootrom) + + pico_wrap_function(pico_mem_ops_pico memcpy) + pico_wrap_function(pico_mem_ops_pico memset) + pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy) + pico_wrap_function(pico_mem_ops_pico __aeabi_memset) + pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy4) + pico_wrap_function(pico_mem_ops_pico __aeabi_memset4) + pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy8) + pico_wrap_function(pico_mem_ops_pico __aeabi_memset8) + + macro(pico_set_mem_ops_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_MEM_OPS_IMPL "pico_mem_ops_${IMPL}") + else() + message(FATAL_ERROR "mem_ops implementation must be set on executable not library") + endif() + endmacro() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h new file mode 100644 index 00000000000..0c224fb7f70 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/include/pico/mem_ops.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_MEMORY_H +#define _PICO_MEMORY_H + +#include "pico/types.h" + +/** \file mem_ops.h + * \defgroup pico_mem_ops pico_mem_ops + * + * Provides optimized replacement implementations of the compiler built-in memcpy, memset and related functions: + * + * - memset, memcpy + * - __aeabi_memset, __aeabi_memset4, __aeabi_memset8, __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8 + * + * This library does not provide any additional functions + */ +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c new file mode 100644 index 00000000000..4047d231bcd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops.c @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/mem_ops.h" diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S new file mode 100644 index 00000000000..e07a9feeec7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.syntax unified +.cpu cortex-m0plus +.thumb + +#include "pico/asm_helper.S" + +__pre_init __aeabi_mem_init, 00001 + +.macro mem_section name +#if PICO_MEM_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.equ MEMSET, 0 +.equ MEMCPY, 4 +.equ MEMSET4, 8 +.equ MEMCPY4, 12 +.equ MEM_FUNC_COUNT, 4 + +# NOTE: All code sections are placed in RAM (at the expense of some veneer cost for calls from flash) because +# otherwise code using basic c division operators will require XIP flash access. + +.section .data.aeabi_mem_funcs +.global aeabi_mem_funcs, aeabi_mem_funcs_end + +.align 2 +aeabi_mem_funcs: + .word rom_table_code('M','S') + .word rom_table_code('M','C') + .word rom_table_code('S','4') + .word rom_table_code('C','4') +aeabi_mem_funcs_end: + +.section .text +regular_func __aeabi_mem_init + ldr r0, =aeabi_mem_funcs + movs r1, #MEM_FUNC_COUNT + ldr r3, =rom_funcs_lookup + bx r3 + +# lump them both together because likely both to be used, in which case doing so saves 1 word +# and it only costs 1 word if not + +// Note from Run-time ABI for the ARM architecture 4.3.4: +// If there is an attached device with efficient memory copying or clearing operations +// (such as a DMA engine), its device supplement specifies whether it may be used in +// implementations of these functions and what effect such use has on the device’s state. + +mem_section aeabi_memset_memcpy + +wrapper_func __aeabi_memset + // args are backwards + eors r0, r1 + eors r1, r0 + eors r0, r1 + ldr r3, =aeabi_mem_funcs + ldr r3, [r3, #MEMSET] + bx r3 + +wrapper_func __aeabi_memset4 +wrapper_func __aeabi_memset8 + // args are backwards + eors r0, r1 + eors r1, r0 + eors r0, r1 + ldr r3, =aeabi_mem_funcs + ldr r3, [r3, #MEMSET4] + bx r3 + +wrapper_func __aeabi_memcpy4 +wrapper_func __aeabi_memcpy8 + ldr r3, =aeabi_mem_funcs + ldr r3, [r3, #MEMCPY4] + bx r3 + +mem_section memset + +wrapper_func memset + ldr r3, =aeabi_mem_funcs + ldr r3, [r3, #MEMSET] + bx r3 + +mem_section memcpy +wrapper_func __aeabi_memcpy +wrapper_func memcpy + ldr r3, =aeabi_mem_funcs + ldr r3, [r3, #MEMCPY] + bx r3 + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt new file mode 100644 index 00000000000..06f378230cd --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt @@ -0,0 +1,17 @@ +if (NOT TARGET pico_multicore) + add_library(pico_multicore INTERFACE) + + target_sources(pico_multicore INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/multicore.c) + + target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_compile_definitions(pico_multicore INTERFACE + PICO_MULTICORE=1 + ) + + target_link_libraries(pico_multicore INTERFACE pico_sync) +endif() + + + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h new file mode 100644 index 00000000000..bc0c64d21f7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_MULTICORE_H +#define _PICO_MULTICORE_H + +#include "pico/types.h" +#include "pico/sync.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file multicore.h + * \defgroup pico_multicore pico_multicore + * Adds support for running code on the second processor core (core1) + * + * \subsection multicore_example Example + * \addtogroup pico_multicore + * \include multicore.c +*/ + +// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE/0x800, group=pico_multicore +#ifndef PICO_CORE1_STACK_SIZE +#ifdef PICO_STACK_SIZE +#define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE +#else +#define PICO_CORE1_STACK_SIZE 0x800 +#endif +#endif + +/*! \brief Reset Core 1 + * \ingroup pico_multicore + * + */ +void multicore_reset_core1(); + +/*! \brief Run code on core 1 + * \ingroup pico_multicore + * + * Reset core1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack) + * + * \param entry Function entry point, this function should not return. + */ +void multicore_launch_core1(void (*entry)(void)); + +/*! \brief Launch code on core 1 with stack + * \ingroup pico_multicore + * + * Reset core1 and enter the given function on core 1 using the passed stack for core 1 + */ +void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); + +/*! \brief Send core 1 to sleep. + * \ingroup pico_multicore + * + */ +void multicore_sleep_core1(); + +/*! \brief Launch code on core 1 with no stack protection + * \ingroup pico_multicore + * + * Reset core1 and enter the given function using the passed sp as the initial stack pointer. + * This is a bare bones functions that does not provide a stack guard even if USE_STACK_GUARDS is defined + * + */ +void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); + +/*! + * \defgroup multicore_fifo fifo + * \ingroup pico_multicore + * \brief Functions for inter-core FIFO + * + * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits + * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written + * by core 1, and read by core 0. + */ + + +/*! \brief Check the read FIFO to see if there is data waiting + * \ingroup multicore_fifo + * + * \return true if the FIFO has data in it, false otherwise + */ +static inline bool multicore_fifo_rvalid() { + return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); +} + +/*! \brief Check the FIFO to see if the write FIFO is full + * \ingroup multicore_fifo + * + * @return true if the FIFO is full, false otherwise + */ +static inline bool multicore_fifo_wready() { + return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); +} + +/*! \brief Push data on to the FIFO. + * \ingroup multicore_fifo + * + * This function will block until there is space for the data to be sent. + * Use multicore_fifo_wready() to check if it is possible to write to the + * FIFO if you don't want to block. + * + * \param data A 32 bit value to push on to the FIFO + */ +void multicore_fifo_push_blocking(uint32_t data); + +bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); + +/*! \brief Pop data from the FIFO. + * \ingroup multicore_fifo + * + * This function will block until there is data ready to be read + * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't + * want to block. + * + * \return 32 bit unsigned data from the FIFO. + */ +uint32_t multicore_fifo_pop_blocking(); + +bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); + +/*! \brief Flush any data in the outgoing FIFO + * \ingroup multicore_fifo + * + */ +static inline void multicore_fifo_drain() { + while (multicore_fifo_rvalid()) + (void) sio_hw->fifo_rd; +} + +/*! \brief Clear FIFO interrupt + * \ingroup multicore_fifo +*/ +static inline void multicore_fifo_clear_irq() { + // Write any value to clear any interrupts + sio_hw->fifo_st = 0xff; +} + +/*! \brief Get FIFO status + * \ingroup multicore_fifo + * + * \return The status as a bitfield + * + * Bit | Description + * ----|------------ + * 3 | Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + * 2 | Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid) +*/ +static inline int32_t multicore_fifo_get_status() { + return sio_hw->fifo_st; +} + +// call this from the lockout victim thread +void multicore_lockout_victim_init(); + +// start locking out the other core (it will be +bool multicore_lockout_start_timeout_us(uint64_t timeout_us); +void multicore_lockout_start_blocking(); + +bool multicore_lockout_end_timeout_us(uint64_t timeout_us); +void multicore_lockout_end_blocking(); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c new file mode 100644 index 00000000000..0ceea4def89 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/stdlib.h" +#include "pico/multicore.h" +#include "hardware/sync.h" +#include "hardware/irq.h" +#include "hardware/structs/scb.h" +#include "hardware/structs/sio.h" +#include "hardware/regs/psm.h" +#include "hardware/claim.h" +#if PICO_USE_STACK_GUARDS +#include "pico/runtime.h" +#endif + +static inline void multicore_fifo_push_blocking_inline(uint32_t data) { + // We wait for the fifo to have some space + while (!multicore_fifo_wready()) + tight_loop_contents(); + + sio_hw->fifo_wr = data; + + // Fire off an event to the other core + __sev(); +} + +void multicore_fifo_push_blocking(uint32_t data) { + multicore_fifo_push_blocking_inline(data); +} + +bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) { + absolute_time_t end_time = make_timeout_time_us(timeout_us); + // We wait for the fifo to have some space + while (!multicore_fifo_wready()) { + tight_loop_contents(); + if (time_reached(end_time)) return false; + } + + sio_hw->fifo_wr = data; + + // Fire off an event to the other core + __sev(); + return true; +} + +static inline uint32_t multicore_fifo_pop_blocking_inline() { + // If nothing there yet, we wait for an event first, + // to try and avoid too much busy waiting + while (!multicore_fifo_rvalid()) + __wfe(); + + return sio_hw->fifo_rd; +} + +uint32_t multicore_fifo_pop_blocking() { + return multicore_fifo_pop_blocking_inline(); +} + +bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) { + absolute_time_t end_time = make_timeout_time_us(timeout_us); + // If nothing there yet, we wait for an event first, + // to try and avoid too much busy waiting + while (!multicore_fifo_rvalid()) { + __wfe(); + if (time_reached(end_time)) return false; + } + + *out = sio_hw->fifo_rd; + return true; +} + +// Default stack for core1 ... if multicore_launch_core1 is not included then .stack1 section will be garbage collected +static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)]; + +static void __attribute__ ((naked)) core1_trampoline() { + __asm("pop {r0, r1, pc}"); +} + +int core1_wrapper(int (*entry)(void), void *stack_base) { +#if PICO_USE_STACK_GUARDS + // install core1 stack guard + runtime_install_stack_guard(stack_base); +#endif + irq_init_priorities(); + return (*entry)(); +} + +void multicore_reset_core1() { + // Use atomic aliases just in case core 1 is also manipulating some posm state + io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET); + io_rw_32 *power_off_set = hw_set_alias(power_off); + io_rw_32 *power_off_clr = hw_clear_alias(power_off); + + // Hard-reset core 1. + // Reading back confirms the core 1 reset is in the correct state, but also + // forces APB IO bridges to fence on any internal store buffering + *power_off_set = PSM_FRCE_OFF_PROC1_BITS; + while (!(*power_off & PSM_FRCE_OFF_PROC1_BITS)) tight_loop_contents(); + + // Bring core 1 back out of reset. It will drain its own mailbox FIFO, then push + // a 0 to our mailbox to tell us it has done this. + *power_off_clr = PSM_FRCE_OFF_PROC1_BITS; +} + +void multicore_sleep_core1() { + multicore_reset_core1(); + // note we give core1 an invalid stack pointer, as it should not be used + // note also if we ge simply passed a function that returned immediately, we'd end up in core1_hang anyway + // however that would waste 2 bytes for that function (the horror!) + extern void core1_hang(); // in crt0.S + multicore_launch_core1_raw(core1_hang, (uint32_t *) -1, scb_hw->vtor); +} + +void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) { + assert(!(stack_size_bytes & 3u)); + uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t); + // push 2 values onto top of stack for core1_trampoline + stack_ptr -= 3; + stack_ptr[0] = (uintptr_t) entry; + stack_ptr[1] = (uintptr_t) stack_bottom; + stack_ptr[2] = (uintptr_t) core1_wrapper; + multicore_launch_core1_raw(core1_trampoline, stack_ptr, scb_hw->vtor); +} + +void multicore_launch_core1(void (*entry)(void)) { + extern char __StackOneBottom; + uint32_t *stack_limit = (uint32_t *) &__StackOneBottom; + // hack to reference core1_stack although that pointer is wrong.... core1_stack should always be <= stack_limit, if not boom! + uint32_t *stack = core1_stack <= stack_limit ? stack_limit : (uint32_t *) -1; + multicore_launch_core1_with_stack(entry, stack, sizeof(core1_stack)); +} + +void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) { + uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry}; + + uint seq = 0; + do { + uint cmd = cmd_sequence[seq]; + // we drain before sending a 0 + if (!cmd) { + multicore_fifo_drain(); + __sev(); // core 1 may be waiting for fifo space + } + multicore_fifo_push_blocking(cmd); + uint32_t response = multicore_fifo_pop_blocking(); + // move to next state on correct response otherwise start over + seq = cmd == response ? seq + 1 : 0; + } while (seq < count_of(cmd_sequence)); +} + +#define LOCKOUT_MAGIC_START 0x73a8831e +#define LOCKOUT_MAGIC_END (LOCKOUT_MAGIC_START ^ -1) + +static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, ""); + +static mutex_t lockout_mutex; +static bool lockout_in_progress; + +// note this method is in RAM because lockout is used when writing to flash +// it only makes inline calls +static void __isr __not_in_flash_func(multicore_lockout_handler)() { + multicore_fifo_clear_irq(); + while (multicore_fifo_rvalid()) { + if (sio_hw->fifo_rd == LOCKOUT_MAGIC_START) { + uint32_t save = save_and_disable_interrupts(); + multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_START); + while (multicore_fifo_pop_blocking_inline() != LOCKOUT_MAGIC_END) { + tight_loop_contents(); // not tight but endless potentially + } + restore_interrupts(save); + multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_END); + } + } +} + +static void check_lockout_mutex_init() { + // use known available lock - we only need it briefly + uint32_t save = hw_claim_lock(); + if (!mutex_is_initialzed(&lockout_mutex)) { + mutex_init(&lockout_mutex); + } + hw_claim_unlock(save); +} + +void multicore_lockout_victim_init() { + check_lockout_mutex_init(); + uint core_num = get_core_num(); + irq_set_exclusive_handler(SIO_IRQ_PROC0 + core_num, multicore_lockout_handler); + irq_set_enabled(SIO_IRQ_PROC0 + core_num, true); +} + +static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) { + uint irq_num = SIO_IRQ_PROC0 + get_core_num(); + bool enabled = irq_is_enabled(irq_num); + if (enabled) irq_set_enabled(irq_num, false); + bool rc = false; + do { + int64_t next_timeout_us = absolute_time_diff_us(get_absolute_time(), until); + if (next_timeout_us < 0) { + break; + } + multicore_fifo_push_timeout_us(magic, next_timeout_us); + next_timeout_us = absolute_time_diff_us(get_absolute_time(), until); + if (next_timeout_us < 0) { + break; + } + uint32_t word = 0; + if (!multicore_fifo_pop_timeout_us(next_timeout_us, &word)) { + break; + } + if (word == magic) { + rc = true; + } + } while (!rc); + if (enabled) irq_set_enabled(irq_num, true); + return rc; +} + +static bool multicore_lockout_start_block_until(absolute_time_t until) { + check_lockout_mutex_init(); + if (!mutex_enter_block_until(&lockout_mutex, until)) { + return false; + } + hard_assert(!lockout_in_progress); + bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_START, until); + lockout_in_progress = rc; + mutex_exit(&lockout_mutex); + return rc; +} + +bool multicore_lockout_start_timeout_us(uint64_t timeout_us) { + return multicore_lockout_start_block_until(make_timeout_time_us(timeout_us)); +} + +void multicore_lockout_start_blocking() { + multicore_lockout_start_block_until(at_the_end_of_time); +} + +static bool multicore_lockout_end_block_until(absolute_time_t until) { + assert(mutex_is_initialzed(&lockout_mutex)); + if (!mutex_enter_block_until(&lockout_mutex, until)) { + return false; + } + assert(lockout_in_progress); + bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_END, until); + if (rc) { + lockout_in_progress = false; + } + mutex_exit(&lockout_mutex); + return rc; +} + +bool multicore_lockout_end_timeout_us(uint64_t timeout_us) { + return multicore_lockout_end_block_until(make_timeout_time_us(timeout_us)); +} + +void multicore_lockout_end_blocking() { + multicore_lockout_end_block_until(at_the_end_of_time); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt new file mode 100644 index 00000000000..00000f38cf0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt @@ -0,0 +1,25 @@ +if (NOT TARGET pico_platform_headers) + add_library(pico_platform_headers INTERFACE) + + target_compile_definitions(pico_platform_headers INTERFACE + PICO_NO_HARDWARE=0 + PICO_ON_DEVICE=1 + PICO_BUILD=1 + ) + + target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_link_libraries(pico_platform_headers INTERFACE hardware_regs) +endif() + +if (NOT TARGET pico_platform) + add_library(pico_platform INTERFACE) + target_sources(pico_platform INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/platform.c) + + target_link_libraries(pico_platform INTERFACE pico_platform_headers) +endif() + +function(pico_add_platform_library TARGET) + target_link_libraries(pico_platform INTERFACE ${TARGET}) +endfunction() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S new file mode 100644 index 00000000000..050e6a5fb51 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/platform_defs.h" +#include "pico/config.h" + +#define WRAPPER_FUNC_NAME(x) __wrap_##x +#define SECTION_NAME(x) .text.##x +#define RAM_SECTION_NAME(x) .time_critical.##x +#define rom_table_code(c1, c2) ((c1) | ((c2) << 8)) + +// do not put align in here as it is used mid function sometimes +.macro regular_func x +.global \x +.type \x,%function +.thumb_func +\x: +.endm + +.macro regular_func_with_section x +.section .text.\x +regular_func \x +.endm + +// do not put align in here as it is used mid function sometimes +.macro wrapper_func x +regular_func WRAPPER_FUNC_NAME(\x) +.endm + +.macro __pre_init func, priority_string +.section .preinit_array.\priority_string +.align 2 +.word \func +.endm + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h new file mode 100644 index 00000000000..718a5ecab28 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_H_ +#define _PICO_PLATFORM_H_ + +#include +#include "pico/types.h" +#include "hardware/platform_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file platform.h +* \defgroup pico_platform pico_platform +* Compiler definitions for the selected PICO_PLATFORM +*/ + +#define __isr + +#define __not_in_flash(group) __attribute__((section(".time_critical." group))) +#define __not_in_flash_func(x) __not_in_flash(__STRING(x)) x +#define __no_inline_not_in_flash_func(x) __attribute__((noinline)) __not_in_flash_func(x) + +// For use with PICO_COPY_TO_RAM: +#define __in_flash(group) __attribute__((section(".flashdata" group))) + +#define __scratch_x(group) __attribute__((section(".scratch_x." group))) +#define __scratch_y(group) __attribute__((section(".scratch_y." group))) + +#define __time_critical_func(x) __not_in_flash_func(x) +#define __after_data(group) __attribute__((section(".after_data." group))) +#define __packed_aligned __packed __aligned(4) + +#ifndef count_of +#define count_of(a) (sizeof(a)/sizeof((a)[0])) +#endif + +#ifndef MAX +#define MAX(a, b) ((a)>(b)?(a):(b)) +#endif + +#ifndef MIN +#define MIN(a, b) ((b)>(a)?(a):(b)) +#endif + +#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group + +inline static void __breakpoint() { + __asm__("bkpt #0"); +} + +// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values +// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore +// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode +#define host_safe_hw_ptr(x) ((uintptr_t)(x)) + +void __attribute__((noreturn)) panic_unsupported(); + +void __attribute__((noreturn)) panic(const char *fmt, ...); + +bool running_on_fpga(); +uint8_t rp2040_chip_version(); + +static inline uint8_t rp2040_rom_version() { + return *(uint8_t*)0x13; +} + +// called by any tight hardware polling loop... nominally empty, but can be modified for debugging +static inline void tight_loop_contents() {} + +// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values +// which of course does not work if we're running the code natively on a 64 bit platform for testing. +// Therefore we provide this function which allows the host runtime to provide a mapping +#define native_safe_hw_ptr(x) ((uintptr_t)(x)) + +// multiplies a by b using multiply instruction using the ARM mul instruction regardless of values +inline static int32_t __mul_instruction(int32_t a, int32_t b) { +asm ("mul %0, %1" : "+l" (a) : "l" (b) : ); +return a; +} + +#define WRAPPER_FUNC(x) __wrap_ ## x +#define REAL_FUNC(x) __real_ ## x + +// macro to multiply value a by possibly constant value b +// if b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default +#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ +(__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ +(a)*(b)) + +#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c new file mode 100644 index 00000000000..86167ab2dff --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" +#include "hardware/regs/sysinfo.h" + +bool running_on_fpga() { + return !!((*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS); +} + +#define MANUFACTURER_RPI 0x927 +#define PART_RP2 0x2 + +uint8_t rp2040_chip_version() { + // First register of sysinfo is chip id + uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET)); + uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS; + uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB; + assert(manufacturer == MANUFACTURER_RPI); + assert(part == PART_RP2); + // Version 1 == B0/B1 + int version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; + return version; +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt new file mode 100644 index 00000000000..cf2082e81b8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt @@ -0,0 +1,63 @@ +if (NOT TARGET pico_printf) + # library to be depended on - we make this depend on particular implementations using per target generator expressions + add_library(pico_printf INTERFACE) + + # no custom implementation; falls thru to compiler + add_library(pico_printf_compiler INTERFACE) + target_compile_definitions(pico_printf_compiler INTERFACE + PICO_PRINTF_COMPILER=1 + ) + + add_library(pico_printf_headers INTERFACE) + target_include_directories(pico_printf_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + # add alias "default" which is just pico. + add_library(pico_printf_default INTERFACE) + target_link_libraries(pico_printf_default INTERFACE pico_printf_pico) + + set(PICO_DEFAULT_PRINTF_IMPL pico_printf_default) + + target_link_libraries(pico_printf INTERFACE + $>,$,${PICO_DEFAULT_PRINTF_IMPL}>) + + add_library(pico_printf_pico INTERFACE) + target_sources(pico_printf_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/printf.c + ) + + target_compile_definitions(pico_printf_pico INTERFACE + PICO_PRINTF_PICO=1 + ) + + target_link_libraries(pico_printf_pico INTERFACE pico_printf_headers) + + add_library(pico_printf_none INTERFACE) + target_sources(pico_printf_none INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/printf_none.S + ) + + target_link_libraries(pico_printf_none INTERFACE pico_printf_headers) + + target_compile_definitions(pico_printf_none INTERFACE + PICO_PRINTF_NONE=1 + ) + + function(wrap_printf_functions TARGET) + # note that printf and vprintf are in pico_stdio so we can provide thread safety + pico_wrap_function(${TARGET} sprintf) + pico_wrap_function(${TARGET} snprintf) + pico_wrap_function(${TARGET} vsnprintf) + endfunction() + + wrap_printf_functions(pico_printf_pico) + wrap_printf_functions(pico_printf_none) + + macro(pico_set_printf_implementation TARGET IMPL) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_PRINTF_IMPL "pico_printf_${IMPL}") + else() + message(FATAL_ERROR "printf implementation must be set on executable not library") + endif() + endmacro() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h new file mode 100644 index 00000000000..6a82b8db4a0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h @@ -0,0 +1,93 @@ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on +// embedded systems with a very limited resources. +// Use this instead of bloated standard/newlib printf. +// These routines are thread safe and reentrant. +// +/////////////////////////////////////////////////////////////////////////////// + +#ifndef PICO_PRINTF_H_ +#define PICO_PRINTF_H_ + +/** \file printf.h + * \defgroup pico_printf pico_printf + * + * Compact replacement for printf by Marco Paland (info@paland.com) + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pico.h" +#include +#include + +// PICO_CONFIG: PICO_PRINTF_ALWAYS_INCLUDED, Whether to always include printf code even if only called weakly (by panic), type=bool, default=1 in debug build 0 otherwise, group=pico_printf +#ifndef PICO_PRINTF_ALWAYS_INCLUDED +#ifndef NDEBUG +#define PICO_PRINTF_ALWAYS_INCLUDED 1 +#else +#define PICO_PRINTF_ALWAYS_INCLUDED 0 +#endif +#endif + +#if PICO_PRINTF_PICO +// weak raw printf may be a puts if printf has not been called, +// so that we can support gc of printf when it isn't called +// +// it is called raw to distinguish it from the regular printf which +// is in stdio.c and does mutex protection +#if !PICO_PRINTF_ALWAYS_INCLUDED +bool __printflike(1, 0) weak_raw_printf(const char *fmt, ...); +bool weak_raw_vprintf(const char *fmt, va_list args); +#else +#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;}) +#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;}) +#endif + +/** + * printf with output function + * You may use this as dynamic alternative to printf() with its fixed _putchar() output + * \param out An output function which takes one character and an argument pointer + * \param arg An argument pointer for user data passed to output function + * \param format A string that specifies the format of the output + * \return The number of characters that are sent to the output function, not counting the terminating null character + */ +int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va); + +#else + +#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;}) +#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;}) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _PRINTF_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c new file mode 100644 index 00000000000..833bd7fcf1c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c @@ -0,0 +1,937 @@ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on +// embedded systems with a very limited resources. These routines are thread +// safe and reentrant! +// Use this instead of the bloated standard/newlib printf cause these use +// malloc for printf (and may not be thread safe). +// +/////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include + +#include "pico/platform.h" +#include "pico/printf.h" + +// PICO_CONFIG: PICO_PRINTF_NTOA_BUFFER_SIZE, Define printf ntoa buffer size, min=0, max=128, default=32, group=pico_printf +// 'ntoa' conversion buffer size, this must be big enough to hold one converted +// numeric number including padded zeros (dynamically created on stack) +#ifndef PICO_PRINTF_NTOA_BUFFER_SIZE +#define PICO_PRINTF_NTOA_BUFFER_SIZE 32U +#endif + +// PICO_CONFIG: PICO_PRINTF_FTOA_BUFFER_SIZE, Define printf ftoa buffer size, min=0, max=128, default=32, group=pico_printf +// 'ftoa' conversion buffer size, this must be big enough to hold one converted +// float number including padded zeros (dynamically created on stack) +#ifndef PICO_PRINTF_FTOA_BUFFER_SIZE +#define PICO_PRINTF_FTOA_BUFFER_SIZE 32U +#endif + +// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, default=1, group=pico_printf +// support for the floating point type (%f) +#ifndef PICO_PRINTF_SUPPORT_FLOAT +#define PICO_PRINTF_SUPPORT_FLOAT 1 +#endif + +// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, default=1, group=pico_printf +// support for exponential floating point notation (%e/%g) +#ifndef PICO_PRINTF_SUPPORT_EXPONENTIAL +#define PICO_PRINTF_SUPPORT_EXPONENTIAL 1 +#endif + +// PICO_CONFIG: PICO_PRINTF_DEFAULT_FLOAT_PRECISION, Define default floating point precision, min=1, max=16, default=6, group=pico_printf +#ifndef PICO_PRINTF_DEFAULT_FLOAT_PRECISION +#define PICO_PRINTF_DEFAULT_FLOAT_PRECISION 6U +#endif + +// PICO_CONFIG: PICO_PRINTF_MAX_FLOAT, Define the largest float suitable to print with %f, min=1, max=1e9, default=1e9, group=pico_printf +#ifndef PICO_PRINTF_MAX_FLOAT +#define PICO_PRINTF_MAX_FLOAT 1e9 +#endif + +// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), default=1, group=pico_printf +#ifndef PICO_PRINTF_SUPPORT_LONG_LONG +#define PICO_PRINTF_SUPPORT_LONG_LONG 1 +#endif + +// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), default=1, group=pico_printf +// ptrdiff_t is normally defined in as long or long long type +#ifndef PICO_PRINTF_SUPPORT_PTRDIFF_T +#define PICO_PRINTF_SUPPORT_PTRDIFF_T 1 +#endif + +/////////////////////////////////////////////////////////////////////////////// + +// internal flag definitions +#define FLAGS_ZEROPAD (1U << 0U) +#define FLAGS_LEFT (1U << 1U) +#define FLAGS_PLUS (1U << 2U) +#define FLAGS_SPACE (1U << 3U) +#define FLAGS_HASH (1U << 4U) +#define FLAGS_UPPERCASE (1U << 5U) +#define FLAGS_CHAR (1U << 6U) +#define FLAGS_SHORT (1U << 7U) +#define FLAGS_LONG (1U << 8U) +#define FLAGS_LONG_LONG (1U << 9U) +#define FLAGS_PRECISION (1U << 10U) +#define FLAGS_ADAPT_EXP (1U << 11U) + +// import float.h for DBL_MAX +#if PICO_PRINTF_SUPPORT_FLOAT + +#include + +#endif + +/** + * Output a character to a custom device like UART, used by the printf() function + * This function is declared here only. You have to write your custom implementation somewhere + * \param character Character to output + */ +static void _putchar(char character) { + putchar(character); +} + +// output function type +typedef void (*out_fct_type)(char character, void *buffer, size_t idx, size_t maxlen); + +#if !PICO_PRINTF_ALWAYS_INCLUDED +// we don't have a way to specify a truly weak symbol reference (the linker will always include targets in a single link step, +// so we make a function pointer that is initialized on the first printf called... if printf is not included in the binary +// (or has never been called - we can't tell) then this will be null. the assumption is that if you are using printf +// you are likely to have printed something. +static int (*lazy_vsnprintf)(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va); +#endif + +// wrapper (used as buffer) for output function type +typedef struct { + void (*fct)(char character, void *arg); + void *arg; +} out_fct_wrap_type; + +// internal buffer output +static inline void _out_buffer(char character, void *buffer, size_t idx, size_t maxlen) { + if (idx < maxlen) { + ((char *) buffer)[idx] = character; + } +} + +// internal null output +static inline void _out_null(char character, void *buffer, size_t idx, size_t maxlen) { + (void) character; + (void) buffer; + (void) idx; + (void) maxlen; +} + +// internal _putchar wrapper +static inline void _out_char(char character, void *buffer, size_t idx, size_t maxlen) { + (void) buffer; + (void) idx; + (void) maxlen; + if (character) { + _putchar(character); + } +} + + +// internal output function wrapper +static inline void _out_fct(char character, void *buffer, size_t idx, size_t maxlen) { + (void) idx; + (void) maxlen; + if (character) { + // buffer is the output fct pointer + ((out_fct_wrap_type *) buffer)->fct(character, ((out_fct_wrap_type *) buffer)->arg); + } +} + + +// internal secure strlen +// \return The length of the string (excluding the terminating 0) limited by 'maxsize' +static inline unsigned int _strnlen_s(const char *str, size_t maxsize) { + const char *s; + for (s = str; *s && maxsize--; ++s); + return (unsigned int) (s - str); +} + + +// internal test if char is a digit (0-9) +// \return true if char is a digit +static inline bool _is_digit(char ch) { + return (ch >= '0') && (ch <= '9'); +} + + +// internal ASCII string to unsigned int conversion +static unsigned int _atoi(const char **str) { + unsigned int i = 0U; + while (_is_digit(**str)) { + i = i * 10U + (unsigned int) (*((*str)++) - '0'); + } + return i; +} + + +// output the specified string in reverse, taking care of any zero-padding +static size_t _out_rev(out_fct_type out, char *buffer, size_t idx, size_t maxlen, const char *buf, size_t len, + unsigned int width, unsigned int flags) { + const size_t start_idx = idx; + + // pad spaces up to given width + if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { + for (size_t i = len; i < width; i++) { + out(' ', buffer, idx++, maxlen); + } + } + + // reverse string + while (len) { + out(buf[--len], buffer, idx++, maxlen); + } + + // append pad spaces up to given width + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) { + out(' ', buffer, idx++, maxlen); + } + } + + return idx; +} + + +// internal itoa format +static size_t _ntoa_format(out_fct_type out, char *buffer, size_t idx, size_t maxlen, char *buf, size_t len, + bool negative, unsigned int base, unsigned int prec, unsigned int width, + unsigned int flags) { + // pad leading zeros + if (!(flags & FLAGS_LEFT)) { + if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < prec) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + // handle hash + if (flags & FLAGS_HASH) { + if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { + len--; + if (len && (base == 16U)) { + len--; + } + } + if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'x'; + } else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'X'; + } else if ((base == 2U) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'b'; + } + if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) { + buf[len++] = '0'; + } + } + + if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +// internal itoa for 'long' type +static size_t _ntoa_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, + unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) { + char buf[PICO_PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char) (value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags); +} + + +// internal itoa for 'long long' type +#if PICO_PRINTF_SUPPORT_LONG_LONG + +static size_t _ntoa_long_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long long value, + bool negative, unsigned long long base, unsigned int prec, unsigned int width, + unsigned int flags) { + char buf[PICO_PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char) (value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags); +} + +#endif // PICO_PRINTF_SUPPORT_LONG_LONG + + +#if PICO_PRINTF_SUPPORT_FLOAT + +#if PICO_PRINTF_SUPPORT_EXPONENTIAL +// forward declaration so that _ftoa can switch to exp notation for values > PICO_PRINTF_MAX_FLOAT +static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, + unsigned int width, unsigned int flags); +#endif + +#define is_nan __builtin_isnan + +// internal ftoa for fixed decimal floating point +static size_t _ftoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, + unsigned int width, unsigned int flags) { + char buf[PICO_PRINTF_FTOA_BUFFER_SIZE]; + size_t len = 0U; + double diff = 0.0; + + // powers of 10 + static const double pow10[] = {1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000}; + + // test for special values + if (is_nan(value)) + return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + if (value < -DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + if (value > DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, + width, flags); + + // test for very large values + // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad + if ((value > PICO_PRINTF_MAX_FLOAT) || (value < -PICO_PRINTF_MAX_FLOAT)) { +#if PICO_PRINTF_SUPPORT_EXPONENTIAL + return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); +#else + return 0U; +#endif + } + + // test for negative + bool negative = false; + if (value < 0) { + negative = true; + value = 0 - value; + } + + // set default precision, if not set explicitly + if (!(flags & FLAGS_PRECISION)) { + prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION; + } + // limit precision to 9, cause a prec >= 10 can lead to overflow errors + while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { + buf[len++] = '0'; + prec--; + } + + int whole = (int) value; + double tmp = (value - whole) * pow10[prec]; + unsigned long frac = (unsigned long) tmp; + diff = tmp - frac; + + if (diff > 0.5) { + ++frac; + // handle rollover, e.g. case 0.99 with prec 1 is 1.0 + if (frac >= pow10[prec]) { + frac = 0; + ++whole; + } + } else if (diff < 0.5) { + } else if ((frac == 0U) || (frac & 1U)) { + // if halfway, round up if odd OR if last digit is 0 + ++frac; + } + + if (prec == 0U) { + diff = value - (double) whole; + if (!((diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + // exactly 0.5 and ODD, then round up + // 1.5 -> 2, but 2.5 -> 2 + ++whole; + } + } else { + unsigned int count = prec; + // now do fractional part, as an unsigned number + while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { + --count; + buf[len++] = (char) (48U + (frac % 10U)); + if (!(frac /= 10U)) { + break; + } + } + // add extra 0s + while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { + buf[len++] = '0'; + } + if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { + // add decimal + buf[len++] = '.'; + } + } + + // do whole part, number is reversed + while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { + buf[len++] = (char) (48 + (whole % 10)); + if (!(whole /= 10)) { + break; + } + } + + // pad leading zeros + if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { + if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < width) && (len < PICO_PRINTF_FTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +#if PICO_PRINTF_SUPPORT_EXPONENTIAL + +// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse +static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, + unsigned int width, unsigned int flags) { + // check for NaN and special values + if (is_nan(value) || (value > DBL_MAX) || (value < -DBL_MAX)) { + return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); + } + + // determine the sign + const bool negative = value < 0; + if (negative) { + value = -value; + } + + // default precision + if (!(flags & FLAGS_PRECISION)) { + prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION; + } + + // determine the decimal exponent + // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) + union { + uint64_t U; + double F; + } conv; + + conv.F = value; + int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 + conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) + // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 + int expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); + // now we want to compute 10^expval but we want to be sure it won't overflow + exp2 = (int) (expval * 3.321928094887362 + 0.5); + const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; + const double z2 = z * z; + conv.U = (uint64_t) (exp2 + 1023) << 52U; + // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex + conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); + // correct for rounding errors + if (value < conv.F) { + expval--; + conv.F /= 10; + } + + // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters + unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; + + // in "%g" mode, "prec" is the number of *significant figures* not decimals + if (flags & FLAGS_ADAPT_EXP) { + // do we want to fall-back to "%f" mode? + if ((value >= 1e-4) && (value < 1e6)) { + if ((int) prec > expval) { + prec = (unsigned) ((int) prec - expval - 1); + } else { + prec = 0; + } + flags |= FLAGS_PRECISION; // make sure _ftoa respects precision + // no characters in exponent + minwidth = 0U; + expval = 0; + } else { + // we use one sigfig for the whole part + if ((prec > 0) && (flags & FLAGS_PRECISION)) { + --prec; + } + } + } + + // will everything fit? + unsigned int fwidth = width; + if (width > minwidth) { + // we didn't fall-back so subtract the characters required for the exponent + fwidth -= minwidth; + } else { + // not enough characters, so go back to default sizing + fwidth = 0U; + } + if ((flags & FLAGS_LEFT) && minwidth) { + // if we're padding on the right, DON'T pad the floating part + fwidth = 0U; + } + + // rescale the float value + if (expval) { + value /= conv.F; + } + + // output the floating part + const size_t start_idx = idx; + idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); + + // output the exponent part + if (minwidth) { + // output the exponential symbol + out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); + // output the exponent value + idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth - 1, + FLAGS_ZEROPAD | FLAGS_PLUS); + // might need to right-pad spaces + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + } + } + return idx; +} + +#endif // PICO_PRINTF_SUPPORT_EXPONENTIAL +#endif // PICO_PRINTF_SUPPORT_FLOAT + +// internal vsnprintf +static int _vsnprintf(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va) { +#if !PICO_PRINTF_ALWAYS_INCLUDED + lazy_vsnprintf = _vsnprintf; +#endif + unsigned int flags, width, precision, n; + size_t idx = 0U; + + if (!buffer) { + // use null output function + out = _out_null; + } + + while (*format) { + // format specifier? %[flags][width][.precision][length] + if (*format != '%') { + // no + out(*format, buffer, idx++, maxlen); + format++; + continue; + } else { + // yes, evaluate it + format++; + } + + // evaluate flags + flags = 0U; + do { + switch (*format) { + case '0': + flags |= FLAGS_ZEROPAD; + format++; + n = 1U; + break; + case '-': + flags |= FLAGS_LEFT; + format++; + n = 1U; + break; + case '+': + flags |= FLAGS_PLUS; + format++; + n = 1U; + break; + case ' ': + flags |= FLAGS_SPACE; + format++; + n = 1U; + break; + case '#': + flags |= FLAGS_HASH; + format++; + n = 1U; + break; + default : + n = 0U; + break; + } + } while (n); + + // evaluate width field + width = 0U; + if (_is_digit(*format)) { + width = _atoi(&format); + } else if (*format == '*') { + const int w = va_arg(va, int); + if (w < 0) { + flags |= FLAGS_LEFT; // reverse padding + width = (unsigned int) -w; + } else { + width = (unsigned int) w; + } + format++; + } + + // evaluate precision field + precision = 0U; + if (*format == '.') { + flags |= FLAGS_PRECISION; + format++; + if (_is_digit(*format)) { + precision = _atoi(&format); + } else if (*format == '*') { + const int prec = (int) va_arg(va, int); + precision = prec > 0 ? (unsigned int) prec : 0U; + format++; + } + } + + // evaluate length field + switch (*format) { + case 'l' : + flags |= FLAGS_LONG; + format++; + if (*format == 'l') { + flags |= FLAGS_LONG_LONG; + format++; + } + break; + case 'h' : + flags |= FLAGS_SHORT; + format++; + if (*format == 'h') { + flags |= FLAGS_CHAR; + format++; + } + break; +#if PICO_PRINTF_SUPPORT_PTRDIFF_T + case 't' : + flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; +#endif + case 'j' : + flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + case 'z' : + flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + default : + break; + } + + // evaluate specifier + switch (*format) { + case 'd' : + case 'i' : + case 'u' : + case 'x' : + case 'X' : + case 'o' : + case 'b' : { + // set the base + unsigned int base; + if (*format == 'x' || *format == 'X') { + base = 16U; + } else if (*format == 'o') { + base = 8U; + } else if (*format == 'b') { + base = 2U; + } else { + base = 10U; + flags &= ~FLAGS_HASH; // no hash for dec format + } + // uppercase + if (*format == 'X') { + flags |= FLAGS_UPPERCASE; + } + + // no plus or space flag for u, x, X, o, b + if ((*format != 'i') && (*format != 'd')) { + flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + } + + // ignore '0' flag when precision is given + if (flags & FLAGS_PRECISION) { + flags &= ~FLAGS_ZEROPAD; + } + + // convert the integer + if ((*format == 'i') || (*format == 'd')) { + // signed + if (flags & FLAGS_LONG_LONG) { +#if PICO_PRINTF_SUPPORT_LONG_LONG + const long long value = va_arg(va, long long); + idx = _ntoa_long_long(out, buffer, idx, maxlen, + (unsigned long long) (value > 0 ? value : 0 - value), value < 0, base, + precision, width, flags); +#endif + } else if (flags & FLAGS_LONG) { + const long value = va_arg(va, long); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) (value > 0 ? value : 0 - value), + value < 0, base, precision, width, flags); + } else { + const int value = (flags & FLAGS_CHAR) ? (char) va_arg(va, int) : (flags & FLAGS_SHORT) + ? (short int) va_arg(va, int) + : va_arg(va, int); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int) (value > 0 ? value : 0 - value), + value < 0, base, precision, width, flags); + } + } else { + // unsigned + if (flags & FLAGS_LONG_LONG) { +#if PICO_PRINTF_SUPPORT_LONG_LONG + idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, + precision, width, flags); +#endif + } else if (flags & FLAGS_LONG) { + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, + width, flags); + } else { + const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char) va_arg(va, unsigned int) + : (flags & FLAGS_SHORT) + ? (unsigned short int) va_arg(va, + unsigned int) + : va_arg(va, unsigned int); + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + } + } + format++; + break; + } + case 'f' : + case 'F' : +#if PICO_PRINTF_SUPPORT_FLOAT + if (*format == 'F') flags |= FLAGS_UPPERCASE; + idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); +#else + for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen); + va_arg(va, double); +#endif + format++; + break; + case 'e': + case 'E': + case 'g': + case 'G': +#if PICO_PRINTF_SUPPORT_FLOAT && PICO_PRINTF_SUPPORT_EXPONENTIAL + if ((*format == 'g') || (*format == 'G')) flags |= FLAGS_ADAPT_EXP; + if ((*format == 'E') || (*format == 'G')) flags |= FLAGS_UPPERCASE; + idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); +#else + for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen); + va_arg(va, double); +#endif + format++; + break; + case 'c' : { + unsigned int l = 1U; + // pre padding + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // char output + out((char) va_arg(va, int), buffer, idx++, maxlen); + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 's' : { + const char *p = va_arg(va, char*); + unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1); + // pre padding + if (flags & FLAGS_PRECISION) { + l = (l < precision ? l : precision); + } + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // string output + while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { + out(*(p++), buffer, idx++, maxlen); + } + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 'p' : { + width = sizeof(void *) * 2U; + flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; +#if PICO_PRINTF_SUPPORT_LONG_LONG + const bool is_ll = sizeof(uintptr_t) == sizeof(long long); + if (is_ll) { + idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t) va_arg(va, void*), false, 16U, + precision, width, flags); + } else { +#endif + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) ((uintptr_t) va_arg(va, void*)), false, + 16U, precision, width, flags); +#if PICO_PRINTF_SUPPORT_LONG_LONG + } +#endif + format++; + break; + } + + case '%' : + out('%', buffer, idx++, maxlen); + format++; + break; + + default : + out(*format, buffer, idx++, maxlen); + format++; + break; + } + } + + // termination + out((char) 0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); + + // return written chars without terminating \0 + return (int) idx; +} + + +/////////////////////////////////////////////////////////////////////////////// + +int WRAPPER_FUNC(sprintf)(char *buffer, const char *format, ...) { + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, (size_t) -1, format, va); + va_end(va); + return ret; +} + +int WRAPPER_FUNC(snprintf)(char *buffer, size_t count, const char *format, ...) { + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); + va_end(va); + return ret; +} + +int WRAPPER_FUNC(vsnprintf)(char *buffer, size_t count, const char *format, va_list va) { + return _vsnprintf(_out_buffer, buffer, count, format, va); +} + +int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va) { + const out_fct_wrap_type out_fct_wrap = {out, arg}; + return _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va); +} + +#if PICO_PRINTF_PICO +#if !PICO_PRINTF_ALWAYS_INCLUDED +bool weak_raw_printf(const char *fmt, ...) { + va_list va; + va_start(va, fmt); + bool rc = weak_raw_vprintf(fmt, va); + va_end(va); + return rc; +} + +bool weak_raw_vprintf(const char *fmt, va_list args) { + if (lazy_vsnprintf) { + char buffer[1]; + lazy_vsnprintf(_out_char, buffer, (size_t) -1, fmt, args); + return true; + } else { + puts(fmt); + return false; + } +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf_none.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf_none.S new file mode 100644 index 00000000000..adc00ee54aa --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf_none.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "pico/bootrom/sf_table.h" + +.syntax unified +.cpu cortex-m0plus +.thumb + +wrapper_func sprintf +wrapper_func snprintf +wrapper_func vsnprintf +regular_func printf_none_assert + push {lr} // keep stack trace sane + ldr r0, =str + bl panic + +str: + .asciz "printf support is disabled" \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt new file mode 100644 index 00000000000..83c08f61e04 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt @@ -0,0 +1,44 @@ +add_library(pico_runtime INTERFACE) + +target_sources(pico_runtime INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/runtime.c +) + +target_include_directories(pico_runtime INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +target_link_libraries(pico_runtime INTERFACE + hardware_uart + hardware_clocks + hardware_irq + pico_printf + pico_sync + ) + +if (TARGET pico_bit_ops) + target_link_libraries(pico_runtime INTERFACE pico_bit_ops) +endif() +if (TARGET pico_divider) + target_link_libraries(pico_runtime INTERFACE pico_divider) +endif() +if (TARGET pico_double) + target_link_libraries(pico_runtime INTERFACE pico_double) +endif() +if (TARGET pico_int64_ops) + target_link_libraries(pico_runtime INTERFACE pico_int64_ops) +endif() +if (TARGET pico_float) + target_link_libraries(pico_runtime INTERFACE pico_float) +endif() +if (TARGET pico_malloc) + target_link_libraries(pico_runtime INTERFACE pico_malloc) +endif() +if (TARGET pico_mem_ops) + target_link_libraries(pico_runtime INTERFACE pico_mem_ops) +endif() +if (TARGET pico_standard_link) + target_link_libraries(pico_runtime INTERFACE pico_standard_link) +endif() + +# todo is this correct/needed? +target_link_options(pico_runtime INTERFACE "--specs=nosys.specs") + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h new file mode 100644 index 00000000000..752ec6cdefc --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/include/pico/runtime.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_RUNTIME_H +#define _PICO_RUNTIME_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file runtime.h +* \defgroup pico_runtime pico_runtime +* Aggregate runtime support including @ref pico_bit_ops, @ref pico_divider, @ref pico_double, @ref pico_int64_ops, @ref pico_float, @ref pico_malloc, @ref pico_mem_ops and @ref pico_standard_link +*/ + + +void runtime_install_stack_guard(void *stack_bottom); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c new file mode 100644 index 00000000000..bd11d8f80b2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "pico.h" + +#include "hardware/regs/m0plus.h" +#include "hardware/regs/resets.h" +#include "hardware/structs/mpu.h" +#include "hardware/structs/scb.h" +#include "hardware/structs/padsbank0.h" + +#include "hardware/clocks.h" +#include "hardware/irq.h" +#include "hardware/resets.h" + +#include "pico/mutex.h" +#include "pico/time.h" +// Use mbed printf +//#include "pico/printf.h" + +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" +#endif + +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +extern char __StackLimit; /* Set by linker. */ + +uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48]; + +// this is called for each thread since they have their own MPU +void runtime_install_stack_guard(void *stack_bottom) { + // this is called b4 runtime_init is complete, so beware printf or assert + + // make sure no one is using the MPU yet + if (mpu_hw->ctrl) { + // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea + __breakpoint(); + } + + uintptr_t addr = (uintptr_t) stack_bottom; + // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will + // just shorten the valid stack range a tad + addr = (addr + 31u) & ~31u; + + // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want + uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u)); + mpu_hw->ctrl = 5; // enable mpu with background default map + mpu_hw->rbar = (addr & ~0xff) | 0x8 | 0; + mpu_hw->rasr = 1 // enable region + | (0x7 << 1) // size 2^(7 + 1) = 256 + | (subregion_select << 8) + | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions +} + +void runtime_init(void) { + // Reset all peripherals to put system into a known state, + // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash + // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot + reset_block(~( + RESETS_RESET_IO_QSPI_BITS | + RESETS_RESET_PADS_QSPI_BITS | + RESETS_RESET_PLL_USB_BITS | + RESETS_RESET_PLL_SYS_BITS + )); + + // Remove reset from peripherals which are clocked only by clk_sys and + // clk_ref. Other peripherals stay in reset until we've configured clocks. + unreset_block_wait(RESETS_RESET_BITS & ~( + RESETS_RESET_ADC_BITS | + RESETS_RESET_RTC_BITS | + RESETS_RESET_SPI0_BITS | + RESETS_RESET_SPI1_BITS | + RESETS_RESET_UART0_BITS | + RESETS_RESET_UART1_BITS | + RESETS_RESET_USBCTRL_BITS + )); + + // pre-init runs really early since we need it even for memcpy and divide! + // (basically anything in aeabi that uses bootrom) + + // Start and end points of the constructor list, + // defined by the linker script. + extern void (*__preinit_array_start)(); + extern void (*__preinit_array_end)(); + + // Call each function in the list. + // We have to take the address of the symbols, as __preinit_array_start *is* + // the first function pointer, not the address of it. + for (void (**p)() = &__preinit_array_start; p < &__preinit_array_end; ++p) { + (*p)(); + } + + // After calling preinit we have enough runtime to do the exciting maths + // in clocks_init + clocks_init(); + + // Peripheral clocks should now all be running + unreset_block_wait(RESETS_RESET_BITS); + +#if !PICO_IE_26_29_UNCHANGED_ON_RESET + // after resetting BANK0 we should disable IE on 26-29 + hw_clear_alias(padsbank0_hw)->io[26] = hw_clear_alias(padsbank0_hw)->io[27] = + hw_clear_alias(padsbank0_hw)->io[28] = hw_clear_alias(padsbank0_hw)->io[29] = PADS_BANK0_GPIO0_IE_BITS; +#endif + + extern mutex_t __mutex_array_start; + extern mutex_t __mutex_array_end; + + // the first function pointer, not the address of it. + for (mutex_t *m = &__mutex_array_start; m < &__mutex_array_end; m++) { + mutex_init(m); + } + +#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH) + __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table)); + scb_hw->vtor = (intptr_t) ram_vector_table; +#endif + +#ifndef NDEBUG + uint32_t xpsr; + __asm volatile ("mrs %0, XPSR" : "=r" (xpsr)::); + if (xpsr & 0xffu) { + // crap; started in exception handler + __asm ("bkpt #0"); + } +#endif + +#if PICO_USE_STACK_GUARDS + // install core0 stack guard + extern char __StackBottom; + runtime_install_stack_guard(&__StackBottom); +#endif + + spin_locks_reset(); + irq_init_priorities(); + alarm_pool_init_default(); + + // Start and end points of the constructor list, + // defined by the linker script. + extern void (*__init_array_start)(); + extern void (*__init_array_end)(); + + // Call each function in the list. + // We have to take the address of the symbols, as __init_array_start *is* + // the first function pointer, not the address of it. + for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) { + (*p)(); + } + +} + +void __exit(int status) { +#if PICO_ENTER_USB_BOOT_ON_EXIT + reset_usb_boot(0,0); +#else + while (1) { + __breakpoint(); + } +#endif +} + +void *__sbrk(int incr) { + extern char end; /* Set by linker. */ + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + char *next_heap_end = heap_end + incr; + + if (__builtin_expect(next_heap_end >= (&__StackLimit), false)) { +#if PICO_USE_OPTIMISTIC_SBRK + if (next_heap_end == &__StackLimit) { +// errno = ENOMEM; + return (char *) -1; + } + next_heap_end = &__StackLimit; +#else + return (char *) -1; +#endif + } + + heap_end = next_heap_end; + return (void *) prev_heap_end; +} + +// exit is not useful... no desire to pull in __call_exitprocs +void exit(int status) { + __exit(status); +} + +// incorrect warning from GCC 6 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsuggest-attribute=format" +void __assert_func(const char *file, int line, const char *func, const char *failedexpr) { + printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", + failedexpr, file, line, func ? ", function: " : "", + func ? func : ""); + + exit(1); +} + +#pragma GCC diagnostic pop + +void __attribute__((noreturn)) panic_unsupported() { + panic("not supported"); +} + +// todo consider making this try harder to output if we panic early +// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC") +// more importantly there may be no stdout/UART initialized yet +// todo we may want to think about where we print panic messages to; writing to USB appears to work +// though it doesn't seem like we can expect it to... fine for now +// +void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { + puts("\n*** PANIC ***\n"); + if (fmt) { +#if PICO_PRINTF_NONE + puts(fmt); +#else + va_list args; + va_start(args, fmt); +#if PICO_PRINTF_ALWAYS_INCLUDED + vprintf(fmt, args); +#else + vprintf(fmt, args); +#endif + va_end(args); + puts("\n"); +#endif + } + + exit(1); +} + +void hard_assertion_failure(void) { + panic("Hard assert"); +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt new file mode 100644 index 00000000000..8dc8ab8c3a4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt @@ -0,0 +1,93 @@ +if (NOT TARGET pico_standard_link) + add_library(pico_standard_link INTERFACE) + + target_sources(pico_standard_link INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/crt0.S + ${CMAKE_CURRENT_LIST_DIR}/new_delete.cpp + ${CMAKE_CURRENT_LIST_DIR}/binary_info.c + ) + + pico_add_map_output(pico_standard_link) + + # todo revisit when we do Clang + if (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(pico_standard_link INTERFACE "LINKER:-nostdlib") + endif () + + target_link_libraries(pico_standard_link INTERFACE hardware_regs pico_bootrom pico_binary_info pico_cxx_options) + + function(pico_add_link_depend TARGET dependency) + get_target_property(target_type ${TARGET} TYPE) + if (${target_type} STREQUAL "INTERFACE_LIBRARY") + set(PROP "INTERFACE_LINK_DEPENDS") + else() + set(PROP "LINK_DEPENDS") + endif() + get_target_property(_LINK_DEPENDS ${TARGET} ${PROP}) + if (NOT _LINK_DEPENDS) + set(_LINK_DEPENDS ${dependency}) + else() + list(APPEND _LINK_DEPENDS ${dependency}) + endif() + set_target_properties(${TARGET} PROPERTIES ${PROP} "${_LINK_DEPENDS}") + endfunction() + + # need this because cmake does not appear to have a way to override an INTERFACE variable + function(pico_set_linker_script TARGET LDSCRIPT) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_LINKER_SCRIPT ${LDSCRIPT}) + pico_add_link_depend(${TARGET} ${LDSCRIPT}) + endfunction() + + function(pico_set_binary_type TARGET TYPE) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BINARY_TYPE ${TYPE}) + endfunction() + + if (PICO_NO_FLASH) + set(PICO_DEFAULT_BINARY_TYPE no_flash) + elseif (PICO_USE_BLOCKED_RAM) + set(PICO_DEFAULT_BINARY_TYPE blocked_ram) + elseif (PICO_COPY_TO_RAM) + set(PICO_DEFAULT_BINARY_TYPE copy_to_ram) + else() + set(PICO_DEFAULT_BINARY_TYPE default) + endif() + + # LINKER script will be PICO_TARGET_LINKER_SCRIPT if set on target, or ${CMAKE_CURRENT_LIST_DIR}/memmap_foo.ld + # if PICO_TARGET_BINARY_TYPE is set to foo on the target, otherwise ${CMAKE_CURRENT_LIST_DIR}/memmap_${PICO_DEFAULT_BINARY_TYPE).ld + target_link_options(pico_standard_link INTERFACE + "LINKER:--script=$>,$,${CMAKE_CURRENT_LIST_DIR}/memmap_$,>,${PICO_DEFAULT_BINARY_TYPE},$>.ld>" + ) + + # PICO_NO_FLASH will be set based on PICO_TARGET_BUILD_TYPE target property being equal to no_flash if set, otherwise to the value of the PICO_NO_FLASH cmake variable unless PICO_TARGET_TYPE is set to something else + # PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link + target_compile_definitions(pico_standard_link INTERFACE PICO_NO_FLASH=$,no_flash>,1,$,$>>>) + # PICO_USE_BLOCKED_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to use_blocked_ram if set, otherwise to the value of the PICO_USE_BLOCKED_RAM cmake variable unless PICO_TARGET_TYPE is set to something else + # PICO_BUILD_DEFINE: PICO_USE_BLOCKS_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link + target_compile_definitions(pico_standard_link INTERFACE PICO_USE_BLOCKED_RAM=$,use_blocked_ram>,1,$,$>>>) + # PICO_COPY_TO_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to copy_to_ram if set, otherwise to the value of the PICO_COPY_TO_RAM cmake variable unless PICO_TARGET_TYPE is set to something else + # PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link + target_compile_definitions(pico_standard_link INTERFACE PICO_COPY_TO_RAM=$,copy_to_ram>,1,$,$>>>) + + target_compile_definitions(pico_standard_link INTERFACE PICO_CMAKE_BUILD_TYPE="${CMAKE_BUILD_TYPE}") + if (PICO_DEOPTIMIZED_DEBUG AND "${CMAKE_BUILD_TYPE}" STREQUAL "Debug") + target_compile_definitions(pico_standard_link INTERFACE PICO_DEOPTIMIZED_DEBUG=1) + endif() + + # todo revisit/recall reasoning for why not -nostartfiles always? + # -nostartfiles will be added if PICO_NO_FLASH would be defined to 1 + target_link_options(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>:-nostartfiles>) + # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0 + target_link_libraries(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>>:$>,$,bs2_default>_library>) + + # done in compiler now + #target_link_options(pico_standard_link INTERFACE "LINKER:--build-id=none") + + # this line occasionally useful for debugging ... todo maybe make a PICO_ var +# target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only + + # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections, and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link + if (NOT PICO_NO_GC_SECTIONS) + target_compile_options(pico_standard_link INTERFACE -ffunction-sections -fdata-sections) + target_link_options(pico_standard_link INTERFACE "LINKER:--gc-sections") + endif() +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c new file mode 100644 index 00000000000..9a879c7bff7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_NO_BINARY_INFO && !PICO_NO_PROGRAM_INFO +#include "pico/binary_info.h" + +// Note we put at most 4 pieces of binary info in the reset section because that's how much spare space we had +// (picked the most common ones)... if there is a link failure because of .reset section overflow then move +// more out. +#define reset_section_attr __attribute__((section(".reset"))) + +#if !PICO_NO_FLASH +#ifndef PICO_NO_BI_BINARY_SIZE +extern char __flash_binary_end; +bi_decl_with_attr(bi_binary_end((uintptr_t)&__flash_binary_end), reset_section_attr) +#endif +#endif + +#if !PICO_NO_BI_PROGRAM_BUILD_DATE +#ifndef PICO_PROGRAM_BUILD_DATE +#define PICO_PROGRAM_BUILD_DATE __DATE__ +#endif +bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), reset_section_attr); +#endif + +#if !PICO_NO_BI_PROGRAM_NAME +#if !defined(PICO_PROGRAM_NAME) && defined(PICO_TARGET_NAME) +#define PICO_PROGRAM_NAME PICO_TARGET_NAME +#endif +#ifdef PICO_PROGRAM_NAME +bi_decl_with_attr(bi_program_name(PICO_PROGRAM_NAME), reset_section_attr) +#endif +#endif + +#if !PICO_NO_BI_PICO_BOARD +#ifdef PICO_BOARD +bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PICO_BOARD, PICO_BOARD)) +#endif +#endif + +#if !PICO_NO_BI_SDK_VERSION +#ifdef PICO_SDK_VERSION_STRING +bi_decl_with_attr(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_SDK_VERSION, PICO_SDK_VERSION_STRING),reset_section_attr) +#endif +#endif + +#if !PICO_NO_BI_PROGRAM_VERSION_STRING +#ifdef PICO_PROGRAM_VERSION_STRING +bi_decl(bi_program_version_string(PICO_PROGRAM_VERSION_STRING)) +#endif +#endif + + +#if !PICO_NO_BI_PROGRAM_DESCRIPTION +#ifdef PICO_PROGRAM_DESCRIPTION +bi_decl(bi_program_description(PICO_PROGRAM_DESCRIPTION)) +#endif +#endif + +#if !PICO_NO_BI_PROGRAM_URL +#ifdef PICO_PROGRAM_URL +bi_decl(bi_program_url(PICO_PROGRAM_URL)) +#endif +#endif + +#if !PICO_NO_BUILD_TYPE_FEATURE +#ifdef PICO_CMAKE_BUILD_TYPE +bi_decl(bi_program_build_attribute(PICO_CMAKE_BUILD_TYPE)) +#else +#ifndef NDEBUG +bi_decl(bi_program_build_attribute("Debug")) +#else +bi_decl(bi_program_build_attribute("Release")) +#endif +#endif + +#if PICO_DEOPTIMIZED_DEBUG +bi_decl(bi_program_build_attribute("All optimization disabled")) +#endif +#endif + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S new file mode 100644 index 00000000000..38de6086342 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/regs/m0plus.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" +#include "pico/binary_info/defs.h" + +#ifdef NDEBUG +#ifndef COLLAPSE_IRQS +#define COLLAPSE_IRQS +#endif +#endif + +.syntax unified +.cpu cortex-m0plus +.thumb + +.section .vectors, "ax" +.align 2 + +.global __vectors +__vectors: +.word __StackTop +.word _reset_handler +.word isr_nmi +.word HardFault_Handler +.word MemManage_Handler +.word BusFault_Handler +.word UsageFault_Handler +.word isr_invalid // Reserved, should never fire +.word isr_invalid // Reserved, should never fire +.word isr_invalid // Reserved, should never fire +.word isr_invalid // Reserved, should never fire +.word SVC_Handler +.word isr_invalid // Reserved, should never fire +.word isr_invalid // Reserved, should never fire +.word PendSV_Handler +.word SysTick_Handler +.word isr_irq0 +.word isr_irq1 +.word isr_irq2 +.word isr_irq3 +.word isr_irq4 +.word isr_irq5 +.word isr_irq6 +.word isr_irq7 +.word isr_irq8 +.word isr_irq9 +.word isr_irq10 +.word isr_irq11 +.word isr_irq12 +.word isr_irq13 +.word isr_irq14 +.word isr_irq15 +.word isr_irq16 +.word isr_irq17 +.word isr_irq18 +.word isr_irq19 +.word isr_irq20 +.word isr_irq21 +.word isr_irq22 +.word isr_irq23 +.word isr_irq24 +.word isr_irq25 +.word isr_irq26 +.word isr_irq27 +.word isr_irq28 +.word isr_irq29 +.word isr_irq30 +.word isr_irq31 + +// Declare a weak symbol for each ISR. +// By default, they will fall through to the undefined IRQ handler below (breakpoint), +// but can be overridden by C functions with correct name. + +.macro decl_isr_bkpt name +.weak \name +.type \name,%function +.thumb_func +\name: + bkpt #0 +.endm + +// these are separated out for clarity +decl_isr_bkpt isr_invalid +decl_isr_bkpt isr_nmi +decl_isr_bkpt isr_hardfault +decl_isr_bkpt isr_svcall +decl_isr_bkpt isr_pendsv +decl_isr_bkpt isr_systick + +.macro decl_isr name +.weak \name +.type \name,%function +.thumb_func +\name: +.endm + +decl_isr isr_irq0 +decl_isr isr_irq1 +decl_isr isr_irq2 +decl_isr isr_irq3 +decl_isr isr_irq4 +decl_isr isr_irq5 +decl_isr isr_irq6 +decl_isr isr_irq7 +decl_isr isr_irq8 +decl_isr isr_irq9 +decl_isr isr_irq10 +decl_isr isr_irq11 +decl_isr isr_irq12 +decl_isr isr_irq13 +decl_isr isr_irq14 +decl_isr isr_irq15 +decl_isr isr_irq16 +decl_isr isr_irq17 +decl_isr isr_irq18 +decl_isr isr_irq19 +decl_isr isr_irq20 +decl_isr isr_irq21 +decl_isr isr_irq22 +decl_isr isr_irq23 +decl_isr isr_irq24 +decl_isr isr_irq25 +decl_isr isr_irq26 +decl_isr isr_irq27 +decl_isr isr_irq28 +decl_isr isr_irq29 +decl_isr isr_irq30 +decl_isr isr_irq31 + +// All unhandled USER IRQs fall through to here +.global __unhandled_user_irq +.thumb_func +__unhandled_user_irq: + bl __get_current_exception + subs r0, #16 +.global unhandled_user_irq_num_in_r0 +unhandled_user_irq_num_in_r0: + bkpt #0 + +// ---------------------------------------------------------------------------- + +.section .binary_info_header, "a" + +// Header must be in first 256 bytes of main image (i.e. excluding flash boot2). +// For flash builds we put it immediately after vector table; for NO_FLASH the +// vectors are at a +0x100 offset because the bootrom enters RAM images directly +// at their lowest address, so we put the header in the VTOR alignment hole. + +#if !PICO_NO_BINARY_INFO +binary_info_header: +.word BINARY_INFO_MARKER_START +.word __binary_info_start +.word __binary_info_end +.word data_cpy_table // we may need to decode pointers that are in RAM at runtime. +.word BINARY_INFO_MARKER_END +#endif + +// ---------------------------------------------------------------------------- + +.section .reset, "ax" + +// On flash builds, the vector table comes first in the image (conventional). +// On NO_FLASH builds, the reset handler section comes first, as the entry +// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned. +// Image is entered in various ways: +// +// - NO_FLASH builds are entered from beginning by UF2 bootloader +// +// - Flash builds vector through the table into _reset_handler from boot2 +// +// - Either type can be entered via _entry_point by the debugger, and flash builds +// must then be sent back round the boot sequence to properly initialise flash + +// ELF entry point: +.type _entry_point,%function +.thumb_func +.global _entry_point +_entry_point: + +#if PICO_NO_FLASH + // Vector through our own table (SP, VTOR will not have been set up at + // this point). Same path for debugger entry and bootloader entry. + ldr r0, =__vectors +#else + // Debugger tried to run code after loading, so SSI is in 03h-only mode. + // Go back through bootrom + boot2 to properly initialise flash. + movs r0, #0 +#endif + ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET) + str r0, [r1] + ldmia r0!, {r1, r2} + msr msp, r1 + bx r2 + +// Reset handler: +// - initialises .data +// - clears .bss +// - calls runtime_init +// - calls main +// - calls exit (which should eventually hang the processor via _exit) + +.type _reset_handler,%function +.thumb_func +_reset_handler: + // Only core 0 should run the C runtime startup code; core 1 is normally + // sleeping in the bootrom at this point but check to be sure + ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET) + ldr r0, [r0] + cmp r0, #0 + bne hold_non_core0_in_bootrom + + adr r4, data_cpy_table + + // assume there is at least one entry +1: + ldmia r4!, {r1-r3} + cmp r1, #0 + beq 2f + bl data_cpy + b 1b +2: + + // Zero out the BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + movs r0, #0 + b bss_fill_test +bss_fill_loop: + stm r1!, {r0} +bss_fill_test: + cmp r1, r2 + bne bss_fill_loop + +platform_entry: // symbol for stack traces + // Use 32-bit jumps, in case these symbols are moved out of branch range + // (e.g. if main is in SRAM and crt0 in flash) + //ldr r1, =runtime_init + //blx r1 + ldr r1, =_start + blx r1 + ldr r1, =exit + blx r1 + // exit should not return. If it does, hang the core. + // (fall thru into our hang _exit impl +.weak _exit +.type _exit,%function +.thumb_func +_exit: +1: // separate label because _exit can be moved out of branch range + bkpt #0 + b 1b + +data_cpy_loop: + ldm r1!, {r0} + stm r2!, {r0} +data_cpy: + cmp r2, r3 + blo data_cpy_loop + bx lr + +.align 2 +data_cpy_table: +#if PICO_COPY_TO_RAM +.word __ram_text_source__ +.word __ram_text_start__ +.word __ram_text_end__ +#endif +.word __etext +.word __data_start__ +.word __data_end__ + +.word __scratch_x_source__ +.word __scratch_x_start__ +.word __scratch_x_end__ + +.word __scratch_y_source__ +.word __scratch_y_start__ +.word __scratch_y_end__ + +.word 0 // null terminator + +// ---------------------------------------------------------------------------- +// Provide safe defaults for _exit and runtime_init +// Full implementations usually provided by platform.c + +.weak runtime_init +.type runtime_init,%function +.thumb_func +runtime_init: + bx lr + +// ---------------------------------------------------------------------------- +// If core 1 somehow gets into crt0 due to a spectacular VTOR mishap, we need to +// catch it and send back to the sleep-and-launch code in the bootrom. Shouldn't +// happen (it should sleep in the ROM until given an entry point via the +// cross-core FIFOs) but it's good to be defensive. + +hold_non_core0_in_bootrom: + ldr r0, = 'W' | ('V' << 8) + bl rom_func_lookup + bx r0 + +.global __get_current_exception +.thumb_func +__get_current_exception: + mrs r0, ipsr + uxtb r0, r0 + bx lr + +// ---------------------------------------------------------------------------- +// Stack/heap dummies to set size + +.section .stack +// align to allow for memory protection (although this alignment is pretty much ignored by linker script) +.align 5 + .equ StackSize, PICO_STACK_SIZE +.space StackSize + +.section .heap +.align 2 + .equ HeapSize, PICO_HEAP_SIZE +.space HeapSize diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/doc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/doc.h new file mode 100644 index 00000000000..d8ce3d49007 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/doc.h @@ -0,0 +1,10 @@ +/** + * \defgroup pico_standard_link pico_standard_link + * \brief Standard link step providing the basics for creating a runnable binary + * + * This includes + * - C runtime initialization + * - Linker scripts for 'default', 'no_flash', 'blocked_ram' and 'copy_to_ram' binaries + * - 'Binary Information' support + * - Linker option control + */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_blocked_ram.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_blocked_ram.ld new file mode 100644 index 00000000000..5b0afe65bd9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_blocked_ram.ld @@ -0,0 +1,252 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + RAM(rwx) : ORIGIN = 0x21000000, LENGTH = 256k + SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes big + and checksummed. It is usually built by the boot_stage2 target + in the Raspberry Pi Pico SDK + */ + + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ == 256, + "ERROR: Pico second stage bootloader must be 256 bytes in size") + + /* The second stage will always enter the image at the start of .text. + The debugger will use the ELF entry point, which is the _entry_point + symbol if present, otherwise defaults to start of .text. + This can be used to transfer control back to the bootrom on debugger + launches only, to perform proper flash setup. + */ + + .text : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.reset)) + /* TODO revisit this now memset/memcpy/float in ROM */ + /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from + * FLASH ... we will include any thing excluded here in .data below by default */ + *(.init) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + .rodata : { + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + /* End of .text-like segments */ + __etext = .; + + .ram_vector_table (COPY): { + *(.ram_vector_table) + } > RAM + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT> FLASH + + .uninitialized_data (COPY): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .bss : { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (COPY): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (COPY): + { + *(.stack*) + } > SCRATCH_Y + + .flash_end : { + __flash_binary_end = .; + } > FLASH + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") + /* todo assert on extra code */ +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_copy_to_ram.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_copy_to_ram.ld new file mode 100644 index 00000000000..90975b593f6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_copy_to_ram.ld @@ -0,0 +1,253 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k + SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes big + and checksummed. It is usually built by the boot_stage2 target + in the Raspberry Pi Pico SDK + */ + + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ == 256, + "ERROR: Pico second stage bootloader must be 256 bytes in size") + + /* The second stage will always enter the image at the start of .text. + The debugger will use the ELF entry point, which is the _entry_point + symbol if present, otherwise defaults to start of .text. + This can be used to transfer control back to the bootrom on debugger + launches only, to perform proper flash setup. + */ + + .flashtext : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.reset)) + } + + .rodata : { + /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */ + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + /* Vector table goes first in RAM, to avoid large alignment hole */ + .ram_vector_table (COPY): { + *(.ram_vector_table) + } > RAM + + .text : { + __ram_text_start__ = .; + *(.init) + *(.text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + . = ALIGN(4); + __ram_text_end__ = .; + } > RAM AT> FLASH + __ram_text_source__ = LOADADDR(.text); + + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT> FLASH + /* __etext is the name of the .data init source pointer (...) */ + __etext = LOADADDR(.data); + + .uninitialized_data (COPY): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .bss : { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (COPY): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (COPY): + { + *(.stack*) + } > SCRATCH_Y + + .flash_end : { + __flash_binary_end = .; + } > FLASH + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") + /* todo assert on extra code */ +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_default.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_default.ld new file mode 100644 index 00000000000..07d5812db1f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_default.ld @@ -0,0 +1,252 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k + SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes big + and checksummed. It is usually built by the boot_stage2 target + in the Raspberry Pi Pico SDK + */ + + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ == 256, + "ERROR: Pico second stage bootloader must be 256 bytes in size") + + /* The second stage will always enter the image at the start of .text. + The debugger will use the ELF entry point, which is the _entry_point + symbol if present, otherwise defaults to start of .text. + This can be used to transfer control back to the bootrom on debugger + launches only, to perform proper flash setup. + */ + + .text : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.reset)) + /* TODO revisit this now memset/memcpy/float in ROM */ + /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from + * FLASH ... we will include any thing excluded here in .data below by default */ + *(.init) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + .rodata : { + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + /* End of .text-like segments */ + __etext = .; + + .ram_vector_table (COPY): { + *(.ram_vector_table) + } > RAM + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT> FLASH + + .uninitialized_data (COPY): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .bss : { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (COPY): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (COPY): + { + *(.stack*) + } > SCRATCH_Y + + .flash_end : { + __flash_binary_end = .; + } > FLASH + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") + /* todo assert on extra code */ +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_no_flash.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_no_flash.ld new file mode 100644 index 00000000000..7a5977fa552 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/memmap_no_flash.ld @@ -0,0 +1,217 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k + SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Note in NO_FLASH builds the entry point for both the bootrom, and debugger + entry (ELF entry point), are *first* in the image, and the vector table + follows immediately afterward. This is because the bootrom enters RAM + binaries directly at their lowest address (preferring main RAM over XIP + cache-as-SRAM if both are used). + */ + + .text : { + __logical_binary_start = .; + __reset_start = .; + KEEP (*(.reset)) + __reset_end = .; + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + . = ALIGN(256); + KEEP (*(.vectors)) + *(.time_critical*) + *(.text*) + . = ALIGN(4); + *(.init) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + } > RAM + + .rodata : { + *(.rodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > RAM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > RAM + __binary_info_end = .; + . = ALIGN(4); + + .data : { + /* End of .text-like segments */ + __etext = .; + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + *(.after_data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM + + .uninitialized_data (COPY): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y + __scratch_y_source__ = LOADADDR(.scratch_y); + + .bss : { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (COPY): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (COPY): + { + *(.stack*) + } > SCRATCH_Y + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") + /* todo assert on extra code */ +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp new file mode 100644 index 00000000000..ecb04b4e6c0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_CXX_ENABLE_EXCEPTIONS +// Override the standard allocators to use regular malloc/free + +#include + +void *operator new(std::size_t n) { + return std::malloc(n); +} + +void *operator new[](std::size_t n) { + return std::malloc(n); +} + +void operator delete(void *p, std::size_t n) noexcept { std::free(p); } + +void operator delete(void *p) { std::free(p); } + +void operator delete[](void *p) noexcept { std::free(p); } + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt new file mode 100644 index 00000000000..15ca07ba4ab --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt @@ -0,0 +1,18 @@ +if (NOT TARGET pico_stdio) + add_library(pico_stdio INTERFACE) + + target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_sources(pico_stdio INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/stdio.c + ) + + pico_wrap_function(pico_stdio printf) + pico_wrap_function(pico_stdio vprintf) + pico_wrap_function(pico_stdio puts) + pico_wrap_function(pico_stdio putchar) + + if (TARGET pico_printf) + target_link_libraries(pico_stdio INTERFACE pico_printf) + endif() +endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/LICENSE b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/LICENSE new file mode 100644 index 00000000000..8f7ebd0b98d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/LICENSE @@ -0,0 +1,22 @@ +The MIT License (MIT) + +Copyright (c) 2014 Marco Paland + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h new file mode 100644 index 00000000000..aec49dfb353 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_STDIO_H +#define _PICO_STDIO_H + +/** \file stdio.h +* \defgroup pico_stdio pico_stdio +* Customized stdio support allowing for input and output from UART, USB, semi-hosting etc. +* +* Note the API for adding additional input output devices is not yet considered stable +*/ + +#include "pico.h" + +// PICO_CONFIG: PICO_STDOUT_MUTEX, Enable/disable mutex around stdout, type=bool, default=1, group=pico_stdio +#ifndef PICO_STDOUT_MUTEX +#define PICO_STDOUT_MUTEX 1 +#endif + +// PICO_CONFIG: PICO_STDIO_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF output conversion support, type=bool, default=1, group=pico_stdio +#ifndef PICO_STDIO_ENABLE_CRLF_SUPPORT +#define PICO_STDIO_ENABLE_CRLF_SUPPORT 1 +#endif + +// PICO_CONFIG: PICO_STDIO_DEFAULT_CRLF, Default for CR/LF conversion enabled on all stdio outputs, type=bool, default=1, depends=PICO_STDIO_ENABLE_CRLF_SUPPORT, group=pico_stdio +#ifndef PICO_STDIO_DEFAULT_CRLF +#define PICO_STDIO_DEFAULT_CRLF 1 +#endif + +// PICO_CONFIG: PICO_STDIO_STACK_BUFFER_SIZE, Define printf buffer size (on stack)... this is just a working buffer not a max output size, min=0, max=512, default=128, group=pico_stdio +#ifndef PICO_STDIO_STACK_BUFFER_SIZE +#define PICO_STDIO_STACK_BUFFER_SIZE 128 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct stdio_driver stdio_driver_t; + +/*! \brief Initialize all of the present standard stdio types that are linked into the binary. + * \ingroup pico_stdio + * + * Call this method once you have set up your clocks to enable the stdio support for UART, USB + * and semihosting based on the presence of the respective librariess in the binary. + * + * \see stdio_uart, stdio_usb, stdio_semihosting + */ +void stdio_init_all(); + +/*! \brief Initialize all of the present standard stdio types that are linked into the binary. + * \ingroup pico_stdio + * + * Call this method once you have set up your clocks to enable the stdio support for UART, USB + * and semihosting based on the presence of the respective librariess in the binary. + * + * \see stdio_uart, stdio_usb, stdio_semihosting + */ +void stdio_flush(); + +/*! \brief Return a character from stdin if there is one available within a timeout + * \ingroup pico_stdio + * + * \param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available. + * \return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs + */ +int getchar_timeout_us(uint32_t timeout_us); + +/*! \brief Adds or removes a driver from the list of active drivers used for input/output + * \ingroup pico_stdio + * + * \note this method should always be called on an initialized driver + * \param driver the driver + * \param enabled true to add, false to remove + */ +void stdio_set_driver_enabled(stdio_driver_t *driver, bool enabled); + +/*! \brief Control limiting of output to a single driver + * \ingroup pico_stdio + * + * \note this method should always be called on an initialized driver + * + * \param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers). + * if NULL then all enabled drivers will be used + */ +void stdio_filter_driver(stdio_driver_t *driver); + +/*! \brief control conversion of line feeds to carriage return on transmissions + * \ingroup pico_stdio + * + * \note this method should always be called on an initialized driver + * + * \param driver the driver + * \param translate If true, convert line feeds to carriage return on transmissions + */ +void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h new file mode 100644 index 00000000000..017206d3cd2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_STDIO_DRIVER_H +#define _PICO_STDIO_DRIVER_H + +#include "pico/stdio.h" +#include "pico/platform.h" + +struct stdio_driver { + void (*out_chars)(const char *buf, int len); + void (*out_flush)(); + int (*in_chars)(char *buf, int len); + stdio_driver_t *next; +#if PICO_STDIO_ENABLE_CRLF_SUPPORT + bool last_ended_with_cr; + bool crlf_enabled; +#endif +}; + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c new file mode 100644 index 00000000000..aecc488891e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "pico.h" +#include "pico/mutex.h" +#include "pico/printf.h" +#include "pico/stdio.h" +#include "pico/stdio/driver.h" +#include "pico/time.h" + +#if PICO_STDIO_UART +#include "pico/stdio_uart.h" +#endif + +#if PICO_STDIO_USB +#include "pico/stdio_usb.h" +#endif + +#if PICO_STDIO_SEMIHOSTING +#include "pico/stdio_semihosting.h" +#endif + +static stdio_driver_t *drivers; +static stdio_driver_t *filter; + +#if PICO_STDOUT_MUTEX +auto_init_mutex(print_mutex); + +bool stdout_serialize_begin() { + int core_num = get_core_num(); + uint32_t owner; + if (!mutex_try_enter(&print_mutex, &owner)) { + if (owner == core_num) { + return false; + } + // other core owns the mutex, so lets wait + mutex_enter_blocking(&print_mutex); + } + return true; +} + +void stdout_serialize_end() { + mutex_exit(&print_mutex); +} + +#else +static bool print_serialize_begin() { + return true; +} +static void print_serialize_end() { +} +#endif + +static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) { +#if PICO_STDIO_ENABLE_CRLF_SUPPORT + if (!driver->crlf_enabled) { + driver->out_chars(s, len); + return; + } + int first_of_chunk = 0; + static const char crlf_str[] = {'\r', '\n'}; + for (int i = 0; i < len; i++) { + bool prev_char_was_cr = i > 0 ? s[i - 1] == '\r' : driver->last_ended_with_cr; + if (s[i] == '\n' && !prev_char_was_cr) { + if (i > first_of_chunk) { + driver->out_chars(&s[first_of_chunk], i - first_of_chunk); + } + driver->out_chars(crlf_str, 2); + first_of_chunk = i + 1; + } + } + if (first_of_chunk < len) { + driver->out_chars(&s[first_of_chunk], len - first_of_chunk); + } + if (len > 0) { + driver->last_ended_with_cr = s[len - 1] == '\r'; + } +#else + driver->out_chars(s, len); +#endif +} + +static bool stdio_put_string(const char *s, int len, bool newline) { + bool serialzed = stdout_serialize_begin(); + if (!serialzed) { +#if PICO_STDIO_IGNORE_NESTED_STDOUT + return false; +#endif + } + if (len == -1) len = strlen(s); + for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { + if (!driver->out_chars) continue; + if (filter && filter != driver) continue; + stdio_out_chars_crlf(driver, s, len); + if (newline) { + const char c = '\n'; + stdio_out_chars_crlf(driver, &c, 1); + } + } + if (serialzed) { + stdout_serialize_end(); + } + return len; +} + +static int stdio_get_until(char *buf, int len, absolute_time_t until) { + do { + // todo round robin might be nice on each call, but then again hopefully + // no source will starve the others + for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { + if (filter && filter != driver) continue; + if (driver->in_chars) { + int read = driver->in_chars(buf, len); + if (read > 0) { + return read; + } + } + } + // todo maybe a little sleep here? + } while (!time_reached(until)); + return PICO_ERROR_TIMEOUT; +} + +int WRAPPER_FUNC(putchar)(int c) { + char cc = c; + stdio_put_string(&cc, 1, false); + return c; +} + +int WRAPPER_FUNC(puts)(const char *s) { + int len = strlen(s); + stdio_put_string(s, len, true); + stdio_flush(); + return len; +} + +int _read(int handle, char *buffer, int length) { + if (handle == 0) { + return stdio_get_until(buffer, length, at_the_end_of_time); + } + return -1; +} + +int _write(int handle, char *buffer, int length) { + if (handle == 1) { + stdio_put_string(buffer, length, false); + return length; + } + return -1; +} + +void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) { + stdio_driver_t *prev = drivers; + for (stdio_driver_t *d = drivers; d; d = d->next) { + if (d == driver) { + if (!enable) { + prev->next = d->next; + driver->next = NULL; + } + return; + } + prev = d; + } + if (enable) { + if (prev) prev->next = driver; + else drivers = driver; + } +} + +void stdio_flush() { + for (stdio_driver_t *d = drivers; d; d = d->next) { + if (d->out_flush) d->out_flush(); + } +} + +typedef struct stdio_stack_buffer { + uint used; + char buf[PICO_STDIO_STACK_BUFFER_SIZE]; +} stdio_stack_buffer_t; + +static void stdio_stack_buffer_flush(stdio_stack_buffer_t *buffer) { + if (buffer->used) { + for (stdio_driver_t *d = drivers; d; d = d->next) { + if (!d->out_chars) continue; + if (filter && filter != d) continue; + stdio_out_chars_crlf(d, buffer->buf, buffer->used); + } + buffer->used = 0; + } +} + +static void stdio_buffered_printer(char c, void *arg) { + stdio_stack_buffer_t *buffer = (stdio_stack_buffer_t *)arg; + if (buffer->used == PICO_STDIO_STACK_BUFFER_SIZE) { + stdio_stack_buffer_flush(buffer); + } + buffer->buf[buffer->used++] = c; +} + +int WRAPPER_FUNC(vprintf)(const char *format, va_list va) { + bool serialzed = stdout_serialize_begin(); + if (!serialzed) { +#if PICO_STDIO_IGNORE_NESTED_STDOUT + return 0; +#endif + } + int ret; +#if PICO_PRINTF_PICO + struct stdio_stack_buffer buffer = {.used = 0}; + ret = vfctprintf(stdio_buffered_printer, &buffer, format, va); + stdio_stack_buffer_flush(&buffer); + stdio_flush(); +#elif PICO_PRINTF_NONE + extern void printf_none_assert(); + printf_none_assert(); +#else + extern int REAL_FUNC(vprintf)(const char *format, va_list va); + ret = REAL_FUNC(vprintf)(format, va); +#endif + if (serialzed) { + stdout_serialize_end(); + } + return ret; +} + +int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...) +{ + va_list va; + va_start(va, format); + int ret = vprintf(format, va); + va_end(va); + return ret; +} + +void stdio_init_all() { + // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway + // These are well known ones +#if PICO_STDIO_UART + stdio_uart_init(); +#endif + +#if PICO_STDIO_SEMIHOSTING + stdio_semihosting_init(); +#endif + +#if PICO_STDIO_USB + stdio_usb_init(); +#endif +} + +int WRAPPER_FUNC(getchar)() { + char buf[1]; + if (0 == stdio_get_until(buf, sizeof(buf), at_the_end_of_time)) { + return PICO_ERROR_TIMEOUT; + } + return (uint8_t)buf[0]; +} + +int getchar_timeout_us(uint32_t timeout_us) { + char buf[1]; + int rc = stdio_get_until(buf, sizeof(buf), make_timeout_time_us(timeout_us)); + if (rc < 0) return rc; + assert(rc); + return (uint8_t)buf[0]; +} + +void stdio_filter_driver(stdio_driver_t *driver) { + filter = driver; +} + +void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) { +#if PICO_STDIO_ENABLE_CRLF_SUPPORT + if (enabled && !driver->crlf_enabled) { + driver->last_ended_with_cr = false; + } + driver->crlf_enabled = enabled; +#else + panic_unsupported(); +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt new file mode 100644 index 00000000000..c65aa91d55a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt @@ -0,0 +1,13 @@ +add_library(pico_stdio_semihosting INTERFACE) + +target_sources(pico_stdio_semihosting INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/stdio_semihosting.c +) + +target_include_directories(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +target_compile_definitions(pico_stdio_semihosting INTERFACE + PICO_STDIO_SEMIHOSTING=1 +) + +target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h new file mode 100644 index 00000000000..0c2f00639b8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_STDIO_SEMIHOSTING_H +#define _PICO_STDIO_SEMIHOSTING_H + +#include "pico/stdio.h" + +/** \brief Experimental support for stdout using RAM semihosting + * \defgroup pico_stdio_semihosting pico_stdio_semihosting + * \ingroup pico_stdio + * + * Linking this library or calling `pico_enable_stdio_semihosting(TARGET)` in the CMake (which + * achieves the same thing) will add semihosting to the drivers used for standard output + */ + +// PICO_CONFIG: PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF, Default state of CR/LF translation for semihosting output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_semihosting +#ifndef PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF +#define PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF +#endif + +extern stdio_driver_t stdio_semihosting; + +/*! \brief Explicitly initialize stdout over semihosting and add it to the current set of stdout targets + * \ingroup pico_stdio_semihosting + * + * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_semihosting` is included in the build + */ +void stdio_semihosting_init(); + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c new file mode 100644 index 00000000000..89367702e4f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/stdio/driver.h" +#include "pico/stdio_semihosting.h" +#include "pico/binary_info.h" + +//static void __attribute__((naked)) semihosting_puts(const char *s) { +// __asm ( +// +// "mov r1, r0\n" +// "mov r0, #4\n" +// "bkpt 0xab\n" +// "bx lr\n" +// ); +//} + +static void __attribute__((naked)) semihosting_putc(char c) { + __asm ( + + "mov r1, r0\n" + "mov r0, #3\n" + "bkpt 0xab\n" + "bx lr\n" + ); +} + + +static void stdio_semihosting_out_chars(const char *buf, int length) { + for (uint i = 0; i RTC_IRQ, ""); // note RTC_IRQ is currently the last one +static mutex_t stdio_usb_mutex; + +static void low_priority_worker_irq() { + // if the mutex is already owned, then we are in user code + // in this file which will do a tud_task itself, so we'll just do nothing + // until the next tick; we won't starve + if (mutex_try_enter(&stdio_usb_mutex, NULL)) { + tud_task(); + mutex_exit(&stdio_usb_mutex); + } +} + +static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) { + irq_set_pending(PICO_STDIO_USB_LOW_PRIORITY_IRQ); + return PICO_STDIO_USB_TASK_INTERVAL_US; +} + +static void stdio_usb_out_chars(const char *buf, int length) { + static uint64_t last_avail_time; + uint32_t owner; + if (!mutex_try_enter(&stdio_usb_mutex, &owner)) { + if (owner == get_core_num()) return; // would deadlock otherwise + mutex_enter_blocking(&stdio_usb_mutex); + } + if (tud_cdc_connected()) { + for (int i = 0; i < length;) { + int n = length - i; + int avail = tud_cdc_write_available(); + if (n > avail) n = avail; + if (n) { + int n2 = tud_cdc_write(buf + i, n); + tud_task(); + tud_cdc_write_flush(); + i += n2; + last_avail_time = time_us_64(); + } else { + tud_task(); + tud_cdc_write_flush(); + if (!tud_cdc_connected() || + (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) { + break; + } + } + } + } else { + // reset our timeout + last_avail_time = 0; + } + mutex_exit(&stdio_usb_mutex); +} + +int stdio_usb_in_chars(char *buf, int length) { + uint32_t owner; + if (!mutex_try_enter(&stdio_usb_mutex, &owner)) { + if (owner == get_core_num()) return PICO_ERROR_NO_DATA; // would deadlock otherwise + mutex_enter_blocking(&stdio_usb_mutex); + } + int rc = PICO_ERROR_NO_DATA; + if (tud_cdc_connected() && tud_cdc_available()) { + int count = tud_cdc_read(buf, length); + rc = count ? count : PICO_ERROR_NO_DATA; + } + mutex_exit(&stdio_usb_mutex); + return rc; +} + +stdio_driver_t stdio_usb = { + .out_chars = stdio_usb_out_chars, + .in_chars = stdio_usb_in_chars, +#if PICO_STDIO_ENABLE_CRLF_SUPPORT + .crlf_enabled = PICO_STDIO_USB_DEFAULT_CRLF +#endif +}; + +bool stdio_usb_init(void) { +#if !PICO_NO_BI_STDIO_USB + bi_decl_if_func_used(bi_program_feature("USB stdin / stdout")); +#endif + + // initialize TinyUSB + tusb_init(); + + irq_set_exclusive_handler(PICO_STDIO_USB_LOW_PRIORITY_IRQ, low_priority_worker_irq); + irq_set_enabled(PICO_STDIO_USB_LOW_PRIORITY_IRQ, true); + + mutex_init(&stdio_usb_mutex); + bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true); + if (rc) { + stdio_set_driver_enabled(&stdio_usb, true); + } + return rc; +} +#else +#include "pico/stdio_usb.h" +#warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked +bool stdio_usb_init(void) { + return false; +} +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c new file mode 100644 index 00000000000..3199886e88a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c @@ -0,0 +1,121 @@ +/* + * This file is based on a file originally part of the + * MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(TINYUSB_HOST_LINKED) && !defined(TINYUSB_DEVICE_LINKED) + +#include "tusb.h" + +#define USBD_VID (0x2E8A) // Raspberry Pi +#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC + +#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) +#define USBD_MAX_POWER_MA (250) + +#define USBD_ITF_CDC (0) // needs 2 interfaces +#define USBD_ITF_MAX (2) + +#define USBD_CDC_EP_CMD (0x81) +#define USBD_CDC_EP_OUT (0x02) +#define USBD_CDC_EP_IN (0x82) +#define USBD_CDC_CMD_MAX_SIZE (8) +#define USBD_CDC_IN_OUT_MAX_SIZE (64) + +#define USBD_STR_0 (0x00) +#define USBD_STR_MANUF (0x01) +#define USBD_STR_PRODUCT (0x02) +#define USBD_STR_SERIAL (0x03) +#define USBD_STR_CDC (0x04) + +// Note: descriptors returned from callbacks must exist long enough for transfer to complete + +static const tusb_desc_device_t usbd_desc_device = { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100, + .iManufacturer = USBD_STR_MANUF, + .iProduct = USBD_STR_PRODUCT, + .iSerialNumber = USBD_STR_SERIAL, + .bNumConfigurations = 1, +}; + +static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = { + TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_MAX, USBD_STR_0, USBD_DESC_LEN, + TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, USBD_MAX_POWER_MA), + + TUD_CDC_DESCRIPTOR(USBD_ITF_CDC, USBD_STR_CDC, USBD_CDC_EP_CMD, + USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE), +}; + +static const char *const usbd_desc_str[] = { + [USBD_STR_MANUF] = "Raspberry Pi", + [USBD_STR_PRODUCT] = "Pico", + [USBD_STR_SERIAL] = "000000000000", // TODO + [USBD_STR_CDC] = "Board CDC", +}; + +const uint8_t *tud_descriptor_device_cb(void) { + return (const uint8_t *)&usbd_desc_device; +} + +const uint8_t *tud_descriptor_configuration_cb(uint8_t index) { + (void)index; + return usbd_desc_cfg; +} + +const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + #define DESC_STR_MAX (20) + static uint16_t desc_str[DESC_STR_MAX]; + + uint8_t len; + if (index == 0) { + desc_str[1] = 0x0409; // supported language is English + len = 1; + } else { + if (index >= sizeof(usbd_desc_str) / sizeof(usbd_desc_str[0])) { + return NULL; + } + const char *str = usbd_desc_str[index]; + for (len = 0; len < DESC_STR_MAX - 1 && str[len]; ++len) { + desc_str[1 + len] = str[len]; + } + } + + // first byte is length (including header), second byte is string type + desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * len + 2); + + return desc_str; +} + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt new file mode 100644 index 00000000000..900ae09fe70 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt @@ -0,0 +1,45 @@ +# PICO_CMAKE_CONFIG: PICO_STDIO_UART, OPTION: Globally enable stdio UART, default=1, group=pico_stdlib +option(PICO_STDIO_UART "Globablly enable stdio UART" 1) +# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTION: Globally enable stdio USB, default=0, group=pico_stdlib +option(PICO_STDIO_USB "Globablly enable stdio USB" 0) +# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTIONS: Globally enable stdio semihosting, default=0, group=pico_stdlib +option(PICO_STDIO_USB "Globablly enable stdio semihosting " 0) + +if (NOT TARGET pico_stdlib) + add_library(pico_stdlib INTERFACE) + target_sources(pico_stdlib INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/stdlib.c + ) + target_link_libraries(pico_stdlib INTERFACE + pico_stdlib_headers + pico_platform + pico_runtime + pico_stdio + pico_time + ) + + function(pico_enable_stdio_uart TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_UART ${ENABLED}) + endfunction() + + function(pico_enable_stdio_usb TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_USB ${ENABLED}) + endfunction() + + function(pico_enable_stdio_semihosting TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_SEMIHOSTING ${ENABLED}) + endfunction() + + if (TARGET pico_stdio_uart) + target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_UART},$>>,pico_stdio_uart,>) + endif() + + if (TARGET pico_stdio_usb) + target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_USB},$>>,pico_stdio_usb,>) + endif() + + if (TARGET pico_stdio_semihosting) + target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_SEMIHOSTING},$>>,pico_stdio_semihosting,>) + endif() + +endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c new file mode 100644 index 00000000000..28d5d386af1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/stdlib.h" +#include "hardware/pll.h" +#include "hardware/clocks.h" +#if PICO_STDIO_UART +#include "pico/stdio_uart.h" +#else +#include "pico/binary_info.h" +#endif + +// everything running off the USB oscillator +void set_sys_clock_48mhz() { + if (!running_on_fpga()) { + // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB + // which has a source frequency of 48MHz + clock_configure(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 48 * MHZ); + + // Turn off PLL sys for good measure + pll_deinit(pll_sys); + + // CLK peri is clocked from clk_sys so need to change clk_peri's freq + clock_configure(clk_peri, + 0, + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, + 48 * MHZ, + 48 * MHZ); + } +} + +void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) { + if (!running_on_fpga()) { + clock_configure(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 48 * MHZ); + + pll_init(pll_sys, 1, vco_freq, post_div1, post_div2); + uint32_t freq = vco_freq / (post_div1 * post_div2); + + // Configure clocks + // CLK_REF = XOSC (12MHz) / 1 = 12MHz + clock_configure(clk_ref, + CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, + 0, // No aux mux + 12 * MHZ, + 12 * MHZ); + + // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz + clock_configure(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, + freq, freq); + + clock_configure(clk_peri, + 0, // Only AUX mux on ADC + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + 48 * MHZ, + 48 * MHZ); + } +} + +bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv_out) { + uint crystal_freq_khz = clock_get_hz(clk_ref) / 1000; + for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { + uint vco = fbdiv * crystal_freq_khz; + if (vco < 400000 || vco > 1600000) continue; + for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { + for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { + uint out = vco / (postdiv1 * postdiv2); + if (out == freq_khz && !(vco % (postdiv1 * postdiv2))) { + *vco_out = vco * 1000; + *postdiv1_out = postdiv1; + *postdiv_out = postdiv2; + return true; + } + } + } + } + return false; +} + +void setup_default_uart() { +#if PICO_STDIO_UART + stdio_uart_init(); +#elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) + // this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present + uart_init(uart_default, PICO_DEFAULT_UART_BAUD_RATE); + if (PICO_DEFAULT_UART_TX_PIN >= 0) + gpio_set_function(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART); + if (PICO_DEFAULT_UART_RX_PIN >= 0) + gpio_set_function(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART); + bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); +#endif +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt new file mode 100644 index 00000000000..4c367d79ba6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt @@ -0,0 +1,9 @@ +add_library(pico_unique_id INTERFACE) + +target_sources(pico_unique_id INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/unique_id.c +) + +target_include_directories(pico_unique_id INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +target_link_libraries(pico_unique_id INTERFACE hardware_flash) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h new file mode 100644 index 00000000000..be956cae619 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_UNIQUE_ID_H_ +#define _PICO_UNIQUE_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file pico/unique_id.h + * \defgroup pico_unique_id pico_unique_id + * + * Unique device ID access API + * + * RP2040 does not have an on-board unique identifier (all instances of RP2040 + * silicon are identical and have no persistent state). However, RP2040 boots + * from serial NOR flash devices which have a 64-bit unique ID as a standard + * feature, and there is a 1:1 association between RP2040 and flash, so this + * is suitable for use as a unique identifier for an RP2040-based board. + * + * This library injects a call to the flash_get_unique_id function from the + * hardware_flash library, to run before main, and stores the result in a + * static location which can safely be accessed at any time via + * pico_get_unique_id(). + * + * This avoids some pitfalls of the hardware_flash API, which requires any + * flash-resident interrupt routines to be disabled when called into. + */ + +#define PICO_UNIQUE_BOARD_ID_SIZE_BYTES 8 + +/** + * \brief Unique board identifier + * \ingroup pico_unique_id + * + * This struct is suitable for holding the unique identifier of a NOR flash + * device on an RP2040-based board. It contains an array of + * PICO_UNIQUE_BOARD_ID_SIZE_BYTES identifier bytes. + */ +typedef struct { + uint8_t id[PICO_UNIQUE_BOARD_ID_SIZE_BYTES]; +} pico_unique_board_id_t; + +/*! \brief Get unique ID + * \ingroup pico_unique_id + * + * Get the unique 64-bit device identifier which was retrieved from the + * external NOR flash device at boot. + * + * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE. + * + * \param id_out a pointer to a pico_unique_board_id_t struct, to which the identifier will be written + */ +void pico_get_unique_board_id(pico_unique_board_id_t *id_out); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c new file mode 100644 index 00000000000..dd2f96ddc67 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/flash.h" +#include "pico/unique_id.h" + +static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Board ID size must match flash ID size"); + +static pico_unique_board_id_t retrieved_id; + +static void __attribute__((constructor)) _retrieve_unique_id_on_boot() { +#if PICO_NO_FLASH + // The hardware_flash call will panic() if called directly on a NO_FLASH + // build. Since this constructor is pre-main it would be annoying to + // debug, so just produce something well-defined and obviously wrong. + for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) + retrieved_id.id[i] = 0xee; +#else + flash_get_unique_id(retrieved_id.id); +#endif +} + +void pico_get_unique_board_id(pico_unique_board_id_t *id_out) { + *id_out = retrieved_id; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt new file mode 100644 index 00000000000..a48c65475aa --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt @@ -0,0 +1,111 @@ +if (DEFINED ENV{PICO_TINYUSB_PATH} AND (NOT PICO_TINYUSB_PATH)) + set(PICO_TINYUSB_PATH $ENV{PICO_TINYUSB_PATH}) + message("Using PICO_TINYUSB_PATH from environment ('${PICO_TINYUSB_PATH}')") +endif () + +set(TINYUSB_TEST_PATH "src/portable/raspberrypi/rp2040") +if (NOT PICO_TINYUSB_PATH) + set(PICO_TINYUSB_PATH ${PROJECT_SOURCE_DIR}/lib/tinyusb) + if (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) + message(WARNING "TinyUSB submodule has not been initialized; USB support will be unavailable + hint: try 'git submodule update --init'.") + endif() +elseif (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) + message(WARNING "PICO_TINYUSB_PATH specified but content not present.") +endif() + +if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) + message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; adding USB support.") + + add_library(tinyusb_common INTERFACE) + target_link_libraries(tinyusb_common INTERFACE + hardware_structs + hardware_irq + hardware_resets + pico_sync + ) + + target_sources(tinyusb_common INTERFACE + ${PICO_TINYUSB_PATH}/src/tusb.c + ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c + ) + + set(TINYUSB_DEBUG_LEVEL 0) + if (CMAKE_BUILD_TYPE STREQUAL "Debug") + message("Compiling TinyUSB with CFG_TUSB_DEBUG=1") + set(TINYUSB_DEBUG_LEVEL 1) + endif () + + target_compile_definitions(tinyusb_common INTERFACE + CFG_TUSB_MCU=OPT_MCU_RP2040 + CFG_TUSB_OS=OPT_OS_PICO #seems examples are hard coded to OPT_OS_NONE + CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL} + ) + + target_include_directories(tinyusb_common INTERFACE + ${PICO_TINYUSB_PATH}/src + ${PICO_TINYUSB_PATH}/src/common + ${PICO_TINYUSB_PATH}/hw + ) + + add_library(tinyusb_device_unmarked INTERFACE) + target_sources(tinyusb_device_unmarked INTERFACE + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/dcd_rp2040.c + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c + ${PICO_TINYUSB_PATH}/src/device/usbd.c + ${PICO_TINYUSB_PATH}/src/device/usbd_control.c + ${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c + ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c + ${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c + ${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c + ${PICO_TINYUSB_PATH}/src/class/msc/msc_device.c + ${PICO_TINYUSB_PATH}/src/class/net/net_device.c + ${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c + ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_device.c + ) + + target_compile_definitions(tinyusb_device_unmarked INTERFACE + # off by default note TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX defaults from PICO_RP2040_USB_DEVICE_ENUMERATION_FIX +# TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1 + ) + + # unmarked version used by stdio USB + target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration) + + add_library(tinyusb_device INTERFACE) + target_link_libraries(tinyusb_device INTERFACE tinyusb_device_unmarked) + target_compile_definitions(tinyusb_device INTERFACE + RP2040_USB_DEVICE_MODE=1 + TINYUSB_DEVICE_LINKED=1 + ) + + add_library(tinyusb_host INTERFACE) + target_sources(tinyusb_host INTERFACE + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c + ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c + ${PICO_TINYUSB_PATH}/src/host/usbh.c + ${PICO_TINYUSB_PATH}/src/host/usbh_control.c + ${PICO_TINYUSB_PATH}/src/host/hub.c + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c + ${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c + ${PICO_TINYUSB_PATH}/src/class/msc/msc_host.c + ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_host.c + ) + + # Sometimes have to do host specific actions in mostly + # common functions + target_compile_definitions(tinyusb_host INTERFACE + RP2040_USB_HOST_MODE=1 + TINYUSB_HOST_LINKED=1 + ) + + target_link_libraries(tinyusb_host INTERFACE tinyusb_common) + + add_library(tinyusb_board INTERFACE) + target_sources(tinyusb_board INTERFACE + ${PICO_TINYUSB_PATH}/hw/bsp/raspberry_pi_pico/board_raspberry_pi_pico.c + ) + +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/doc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/doc.h new file mode 100644 index 00000000000..6c361e0002a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/doc.h @@ -0,0 +1,7 @@ +/** + * \defgroup tinyusb_device tinyusb_device + * \brief TinyUSB Device-mode support for the RP2040 + * + * \defgroup tinyusb_host tinyusb_host + * \brief TinyUSB Host-mode support for the RP2040 + */ From d513993457a61cf37cf53aaf02a53c769f132484 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 10:56:43 +0200 Subject: [PATCH 016/227] RP2040: add NANO_RP2040_CONNECT target --- targets/CMakeLists.txt | 1 + targets/TARGET_RASPBERRYPI/CMakeLists.txt | 11 + .../TARGET_RP2040/.mbedignore | 20 ++ .../TARGET_RP2040/CMakeLists.txt | 12 + .../TARGET_RP2040/PeripheralNames.h | 102 +++++++ .../TARGET_RP2040/PortNames.h | 31 +++ .../TARGET_NANO_RP2040_CONNECT/PinNames.h | 64 +++++ .../TARGET_NANO_RP2040_CONNECT/board.c | 3 + .../bs2_default_padded_checksummed.S | 23 ++ .../TOOLCHAIN_GCC_ARM/memmap_default.ld | 252 ++++++++++++++++++ .../TARGET_RASPBERRYPI/TARGET_RP2040/cmsis.h | 60 +++++ .../TARGET_RP2040/cmsis_nvic.h | 36 +++ .../TARGET_RASPBERRYPI/TARGET_RP2040/device.h | 37 +++ .../TARGET_RP2040/gpio_api.c | 37 +++ .../TARGET_RP2040/mbed_overrides.c | 11 + .../TARGET_RP2040/objects.h | 111 ++++++++ targets/TARGET_RASPBERRYPI/mbed_rtx.h | 27 ++ targets/targets.json | 29 ++ 18 files changed, 867 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/PortNames.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis_nvic.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/device.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/mbed_overrides.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h create mode 100644 targets/TARGET_RASPBERRYPI/mbed_rtx.h diff --git a/targets/CMakeLists.txt b/targets/CMakeLists.txt index 36c9454e67e..a54c44804bd 100644 --- a/targets/CMakeLists.txt +++ b/targets/CMakeLists.txt @@ -15,6 +15,7 @@ if(${CMAKE_CROSSCOMPILING}) add_subdirectory(TARGET_NORDIC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NUVOTON EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NXP EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_RASPBERRYPI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_RENESAS EXCLUDE_FROM_ALL) add_subdirectory(TARGET_Samsung EXCLUDE_FROM_ALL) add_subdirectory(TARGET_Silicon_Labs EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_RASPBERRYPI/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/CMakeLists.txt new file mode 100644 index 00000000000..3ba15e7d898 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("RPI2010" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_RPI2040) +endif() + +target_include_directories(mbed-core + INTERFACE + . +) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore new file mode 100644 index 00000000000..2b44582cfcf --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -0,0 +1,20 @@ +pico-sdk/common/pico_stdlib/include/pico/* +pico-sdk/common/pico_time/include/pico/* +pico-sdk/rp2_common/pico_stdio* +pico-sdk/rp2_common/pico_printf* +pico-sdk/boards/include/boards/* +pico-sdk/common/pico_base/include/pico/* +pico-sdk/rp2_common/boot_stage2/* +pico-sdk/rp2_common/pico_multicore/* +pico-sdk/rp2_common/pico_malloc/* +pico-sdk/rp2_common/pico_stdlib/ +pico-sdk/rp2_common/pico_mem_ops/* +pico-sdk/rp2_common/pico_double/double_aeabi.S +pico-sdk/rp2_common/pico_double/double_none.S +pico-sdk/rp2_common/pico_float/float_aeabi.S +pico-sdk/rp2_common/pico_float/float_none.S +pico-sdk/rp2_common/pico_standard_link/new_delete.cpp +pico-sdk/rp2_common/pico_standard_link/*.ld +pico-sdk/rp2_common/pico_unique_id/* +pico-sdk/rp2_common/hardware_divider/* +pico-sdk/host/* \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt new file mode 100644 index 00000000000..9dc92970487 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("NANO_RP2040_CONNECT" IN_LIST MBED_TARGET_LABELS) + target_include_directories(mbed-core + INTERFACE + TARGET_NANO_RP2040_CONNECT + ) +endif() + +add_subdirectory(rp2_common) +add_subdirectory(rp2040) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h new file mode 100644 index 00000000000..220d4a831ef --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +typedef enum { + UART_0 = 0, + UART_1, +} UARTName; + +typedef enum { + ADC0_0 = 26, + ADC0_1, + ADC0_2, + ADC0_3 +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1 +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1 +} I2CName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6 +} PWMName; + +/* Defines to be used by application */ +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrainPullUp = 3, + OpenDrainNoPull = 4, + OpenDrainPullDown = 5, + PushPullNoPull = PullNone, + PushPullPullUp = PullUp, + PushPullPullDown = PullDown, + OpenDrain = OpenDrainPullUp, + PullDefault = PullNone +} PinMode; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART uart0 + +// Default peripherals +#define MBED_SPI0 p5, p6, p7, p8 +#define MBED_SPI1 p11, p12, p13, p14 + +#define MBED_UART0 p9, p10 +#define MBED_UART1 p13, p14 +#define MBED_UART2 p28, p27 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 p28, p27 +#define MBED_I2C1 p9, p10 + +#define MBED_ANALOGIN0 p15 +#define MBED_ANALOGIN1 p16 +#define MBED_ANALOGIN2 p17 +#define MBED_ANALOGIN3 p18 + +#define MBED_PWMOUT0 p26 +#define MBED_PWMOUT1 p25 +#define MBED_PWMOUT2 p24 +#define MBED_PWMOUT3 p23 +#define MBED_PWMOUT4 p22 +#define MBED_PWMOUT5 p21 + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PortNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PortNames.h new file mode 100644 index 00000000000..e657d7c65e5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PortNames.h @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h new file mode 100644 index 00000000000..1590820a31f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h @@ -0,0 +1,64 @@ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "PeripheralNames.h" +#include "boards/pico.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + + A0 = 26, + A1 = 27, + A2 = 28, + A3 = 29, + + USBTX = p0, + USBRX = p1, + + LED1 = p25, + LED2 = p25, + LED3 = p25, + LED4 = p25, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c new file mode 100644 index 00000000000..1f775638f9b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c @@ -0,0 +1,3 @@ +#include "PinNames.h" + +uint32_t SystemCoreClock = 120000000; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S new file mode 100644 index 00000000000..e9be188191a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S @@ -0,0 +1,23 @@ +// Padded and checksummed version of: /ssd/rp2040/pico-examples/build/pico-sdk/src/rp2_common/boot_stage2/bs2_default.bin + +.cpu cortex-m0plus +.thumb + +.section .boot2, "ax" + +.byte 0x00, 0xb5, 0x31, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60 +.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2d, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61 +.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2a, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20 +.byte 0x00, 0xf0, 0x42, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x12, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0 +.byte 0x32, 0xf8, 0x19, 0x6e, 0x31, 0x21, 0x19, 0x66, 0x1a, 0x66, 0x00, 0xf0, 0x2c, 0xf8, 0x19, 0x6e +.byte 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21, 0x08, 0x42, 0xf9, 0xd1 +.byte 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60, 0x1a, 0x49, 0x1b, 0x48 +.byte 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0x20, 0x21, 0x19, 0x66, 0x00, 0xf0 +.byte 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60 +.byte 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49, 0x08, 0x60, 0x03, 0xc8 +.byte 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20, 0x01, 0x42, 0xfb, 0xd0 +.byte 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66, 0x18, 0x66, 0xff, 0xf7 +.byte 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x00, 0x18 +.byte 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x18 +.byte 0x22, 0x20, 0x00, 0x20, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00 +.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb3, 0x64, 0x01, 0x1a diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld new file mode 100644 index 00000000000..07d5812db1f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld @@ -0,0 +1,252 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k + SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes big + and checksummed. It is usually built by the boot_stage2 target + in the Raspberry Pi Pico SDK + */ + + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ == 256, + "ERROR: Pico second stage bootloader must be 256 bytes in size") + + /* The second stage will always enter the image at the start of .text. + The debugger will use the ELF entry point, which is the _entry_point + symbol if present, otherwise defaults to start of .text. + This can be used to transfer control back to the bootrom on debugger + launches only, to perform proper flash setup. + */ + + .text : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.reset)) + /* TODO revisit this now memset/memcpy/float in ROM */ + /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from + * FLASH ... we will include any thing excluded here in .data below by default */ + *(.init) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + .rodata : { + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + /* End of .text-like segments */ + __etext = .; + + .ram_vector_table (COPY): { + *(.ram_vector_table) + } > RAM + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT> FLASH + + .uninitialized_data (COPY): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .bss : { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (COPY): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (COPY): + { + *(.stack*) + } > SCRATCH_Y + + .flash_end : { + __flash_binary_end = .; + } > FLASH + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary") + /* todo assert on extra code */ +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis.h new file mode 100644 index 00000000000..0920ce23594 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis.h @@ -0,0 +1,60 @@ +#ifndef __RP2040_H__ +#define __RP2040_H__ + +typedef enum IRQn +{ + /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /* ---------------------- RP2040 Specific Interrupt Numbers ------------------ */ + TIMER_IRQ_0n = 0, /*!< */ + TIMER_IRQ_1n = 1, /*!< */ + TIMER_IRQ_2n = 2, /*!< */ + TIMER_IRQ_3n = 3, /*!< */ + PWM_IRQ_WRAPn = 4, /*!< */ + USBCTRL_IRQn = 5, /*!< */ + XIP_IRQn = 6, /*!< */ + PIO0_IRQ_0n = 7, /*!< */ + PIO0_IRQ_1n = 8, /*!< */ + PIO1_IRQ_0n = 9, /*!< */ + PIO1_IRQ_1n = 10, /*!< */ + DMA_IRQ_0n = 11, /*!< */ + DMA_IRQ_1n = 12, /*!< */ + IO_IRQ_BANK0n = 13, /*!< */ + IO_IRQ_QSPIn = 14, /*!< */ + SIO_IRQ_PROC0n = 15, /*!< */ + SIO_IRQ_PROC1n = 16, /*!< */ + CLOCKS_IRQn = 17, /*!< */ + SPI0_IRQn = 18, /*!< */ + SPI1_IRQn = 19, /*!< */ + UART0_IRQn = 20, /*!< */ + UART1_IRQn = 21, /*!< */ + ADC_IRQ_FIFOn = 22, /*!< */ + I2C0_IRQn = 23, /*!< */ + I2C1_IRQn = 24, /*!< */ + RTC_IRQn = 25, /*!< */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */ +#define __MPU_PRESENT 0 /* MPU present or not */ +#define __VTOR_PRESENT 1 /* VTOR present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0plus.h" +#include "cmsis_nvic.h" + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis_nvic.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis_nvic.h new file mode 100644 index 00000000000..fc07aa7f004 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/cmsis_nvic.h @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x10000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x0 // 0 B +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x0 // 0 B +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/device.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/device.h new file mode 100644 index 00000000000..8c01d7bae12 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/device.h @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c new file mode 100644 index 00000000000..bdc1ab925d2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c @@ -0,0 +1,37 @@ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +void gpio_write(gpio_t *obj, int value) +{ + gpio_put(obj->pin, value); +} + +int gpio_read(gpio_t *obj) +{ + return gpio_get(obj->pin); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + _gpio_init(obj->pin); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + gpio_set_pulls(obj->pin, mode == PullUp, mode == PullDown); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + obj->direction = direction; + if (direction == PIN_OUTPUT) { + gpio_set_dir(obj->pin, GPIO_OUT); + } + if (direction == PIN_INPUT) { + gpio_set_dir(obj->pin, GPIO_IN); + } +} + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/mbed_overrides.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/mbed_overrides.c new file mode 100644 index 00000000000..323d734cd5e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/mbed_overrides.c @@ -0,0 +1,11 @@ +#include "cmsis.h" +#include "objects.h" +#include "platform/mbed_error.h" + +int mbed_sdk_inited = 0; + +void mbed_sdk_init() +{ + runtime_init(); + mbed_sdk_inited = 1; +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h new file mode 100644 index 00000000000..ad3cca07b07 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wtype-limits" +#pragma GCC diagnostic ignored "-Wignored-qualifiers" + +#ifdef __cplusplus +#include +#include +extern "C" { +#endif +#include "pico.h" +#include "pico/platform.h" +#include "pico/types.h" +#include "pico/assert.h" +#include "pico/time.h" +#include "pico/types.h" +#include "hardware/pwm.h" +#include "hardware/adc.h" +#include "hardware/resets.h" +#include "hardware/timer.h" +#include "hardware/uart.h" +#include "hardware/spi.h" +#include "hardware/i2c.h" +#include "hardware/gpio.h" +#include "hardware/regs/addressmap.h" +#ifdef __cplusplus +} +#endif + +#pragma GCC diagnostic pop + +#include "cmsis.h" + +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct gpio_s gpio_t; + +struct gpio_s { + PinName pin; + PinDirection direction; +}; + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +/* common objects */ +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct serial_s { + uart_inst_t * const uart; + int index; +}; + +struct i2c_s { + i2c_inst_t * const *i2c; +}; + +struct spi_s { + spi_inst_t * const *spi; +}; + +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/mbed_rtx.h b/targets/TARGET_RASPBERRYPI/mbed_rtx.h new file mode 100644 index 00000000000..f43fa2e32d7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/mbed_rtx.h @@ -0,0 +1,27 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_RPI2040) + +/* TODO */ + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index c035a6ed521..239260df44d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9404,6 +9404,35 @@ "inherits": ["AMA3B1KK"], "components_add": ["lis2dh12", "hm01b0"] }, + "RP2040": { + "inherits": ["Target"], + "core": "Cortex-M0+", + "supported_toolchains": ["GCC_ARM"], + "extra_labels": [ + "RASPBERRYPI", + "memmap_default" + ], + "release_versions": [ + "5" + ], + "overrides": { + "xip-enable": true + }, + "device_has": [ + "ANALOGIN", + "PORT_IN", + "PORT_OUT" + ] + }, + "NANO_RP2040_CONNECT": { + "inherits": ["RP2040"], + "macros_add": [ + "PICO_NO_BINARY_INFO=1", + "MBED_MPU_CUSTOM", + "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", + "PICO_ON_DEVICE=1" + ] + }, "__build_tools_metadata__": { "version": "1", "public": false From 37d5a054bb8687e0057d2a20175b1bf7130b23be Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 12 Feb 2021 13:29:58 +0100 Subject: [PATCH 017/227] RP2040: add placeholder files for includes like pico/*.h --- .../TARGET_RP2040/pico-sdk/boards/include/placeholder.h | 0 .../pico-sdk/common/pico_stdlib/include/placeholder.h | 0 .../TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h | 0 3 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d From 7e800b025ab9f48b006f96888406a46ca0867227 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 12 Feb 2021 15:49:55 +0100 Subject: [PATCH 018/227] RP2040: implement serial api --- .../TARGET_RP2040/PeripheralPins.c | 85 +++++++ .../TARGET_RP2040/PeripheralPins.h | 72 ++++++ .../TARGET_NANO_RP2040_CONNECT/PinNames.h | 4 + .../TARGET_RP2040/gpio_api.c | 2 +- .../TARGET_RP2040/objects.h | 18 +- .../TARGET_RP2040/serial_api.c | 214 ++++++++++++++++++ targets/targets.json | 6 +- 7 files changed, 392 insertions(+), 9 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c new file mode 100644 index 00000000000..97a2acd2618 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c @@ -0,0 +1,85 @@ +#include "pinmap.h" +#include "objects.h" +#include "PeripheralPins.h" + +const PinMap PinMap_FULL[] = { + {p0, 0, 0}, + {p1, 0, 0}, + {p2, 0, 0}, + {p3, 0, 0}, + {p4, 0, 0}, + {p5, 0, 0}, + {p6, 0, 0}, + {p7, 0, 0}, + {p8, 0, 0}, + {p9, 0, 0}, + {p10, 0, 0}, + {p11, 0, 0}, + {p12, 0, 0}, + {p13, 0, 0}, + {p14, 0, 0}, + {p15, 0, 0}, + {p16, 0, 0}, + {p17, 0, 0}, + {p18, 0, 0}, + {p19, 0, 0}, + {p20, 0, 0}, + {p21, 0, 0}, + {p22, 0, 0}, + {p23, 0, 0}, + {p24, 0, 0}, + {p25, 0, 0}, + {p26, 0, 0}, + {p27, 0, 0}, + {p28, 0, 0}, + {p29, 0, 0}, + {NC, NC, 0} +}; + + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {p0, UART_0, (uint32_t) uart0}, + {p4, UART_1, (uint32_t) uart1}, + {p8, UART_1, (uint32_t) uart1}, + {p12, UART_0, (uint32_t) uart0}, + {p16, UART_0, (uint32_t) uart0}, + {p20, UART_1, (uint32_t) uart1}, + {p24, UART_1, (uint32_t) uart1}, + {p28, UART_0, (uint32_t) uart0}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {p1, UART_0, (uint32_t) uart0}, + {p5, UART_1, (uint32_t) uart1}, + {p9, UART_1, (uint32_t) uart1}, + {p13, UART_0, (uint32_t) uart0}, + {p17, UART_0, (uint32_t) uart0}, + {p21, UART_1, (uint32_t) uart1}, + {p25, UART_1, (uint32_t) uart1}, + {p29, UART_0, (uint32_t) uart0}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {p2, UART_0, (uint32_t) uart0}, + {p6, UART_1, (uint32_t) uart1}, + {p10, UART_1, (uint32_t) uart1}, + {p14, UART_0, (uint32_t) uart0}, + {p18, UART_0, (uint32_t) uart0}, + {p22, UART_1, (uint32_t) uart1}, + {p26, UART_1, (uint32_t) uart1}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {p3, UART_0, (uint32_t) uart0}, + {p7, UART_1, (uint32_t) uart1}, + {p11, UART_1, (uint32_t) uart1}, + {p15, UART_0, (uint32_t) uart0}, + {p19, UART_0, (uint32_t) uart0}, + {p23, UART_1, (uint32_t) uart1}, + {p27, UART_1, (uint32_t) uart1}, + {NC, NC, 0} +}; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h new file mode 100644 index 00000000000..abeaed1d82a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h @@ -0,0 +1,72 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2018-2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// SPDX-License-Identifier: Apache-2.0 +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "PeripheralNames.h" + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM_OUT[]; +#endif + +//*** SERIAL *** +#if DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif + +//*** SPI *** +#if DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** ADC *** +#if DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#if DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** QSPI *** +#if DEVICE_QSPI +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; +extern const PinMap PinMap_QSPI_DATA0[]; +extern const PinMap PinMap_QSPI_DATA1[]; +extern const PinMap PinMap_QSPI_DATA2[]; +extern const PinMap PinMap_QSPI_DATA3[]; +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h index 1590820a31f..e84e89440c5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h @@ -35,6 +35,10 @@ typedef enum { p23 = 23, p24 = 24, p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, // ADC internal channels ADC_TEMP = 0xF0, diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c index bdc1ab925d2..7f6131c9727 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c @@ -1,5 +1,5 @@ #include "mbed_assert.h" -#include "gpio_api.h" +#include "hal/gpio_api.h" #include "pinmap.h" #include "mbed_error.h" diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index ad3cca07b07..7272492f2f7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -40,6 +40,7 @@ extern "C" { #include "hardware/spi.h" #include "hardware/i2c.h" #include "hardware/gpio.h" +#include "hardware/irq.h" #include "hardware/regs/addressmap.h" #ifdef __cplusplus } @@ -57,8 +58,6 @@ extern "C" { extern "C" { #endif -typedef struct gpio_s gpio_t; - struct gpio_s { PinName pin; PinDirection direction; @@ -87,16 +86,20 @@ struct analogin_s { }; struct serial_s { - uart_inst_t * const uart; - int index; + uart_inst_t * dev; + PinName pin_rx; + PinName pin_tx; + PinName pin_rts; + PinName pin_cts; + uint32_t baud; }; struct i2c_s { - i2c_inst_t * const *i2c; + i2c_inst_t * dev; }; struct spi_s { - spi_inst_t * const *spi; + spi_inst_t * dev; }; struct flash_s { @@ -104,6 +107,9 @@ struct flash_s { uint32_t dummy; }; +typedef struct gpio_s gpio_t; +typedef struct serial_s serial_t; + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c new file mode 100644 index 00000000000..6a90e64323f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c @@ -0,0 +1,214 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/serial_api.h" +#include "mbed_error.h" +#include "PinNames.h" +#include "PeripheralPins.h" +#include + +#if DEVICE_SERIAL + +#ifdef __cplusplus +extern "C" { +#endif + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + if (tx == STDIO_UART_TX && stdio_uart_inited != 0) { + memmove(obj, &stdio_uart, sizeof(serial_t)); + return; + } + memset(obj, 0, sizeof(serial_t)); + struct serial_s *ser = obj; + ser->pin_tx = tx; + ser->pin_rx = rx; + ser->pin_rts = NC; + ser->pin_cts = NC; + + UARTName dev_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName dev_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + if (dev_tx != dev_rx) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "Invalid serial pins"); + } + if (dev_tx == UART_0) { + obj->dev = uart0; + } else { + obj->dev = uart1; + } + + uart_init(obj->dev, MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE); + gpio_set_function(tx, GPIO_FUNC_UART); + gpio_set_function(rx, GPIO_FUNC_UART); + + //uart_set_translate_crlf(obj->dev, false); + uart_set_fifo_enabled(obj->dev, false); + + if (tx == STDIO_UART_TX) { + memmove(&stdio_uart, obj, sizeof(serial_t)); + stdio_uart_inited = 1; + } +} + +void serial_free(serial_t *obj) +{ + uart_deinit(obj->dev); +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->baud = (uint32_t)baudrate; + uart_set_baudrate(obj->dev, obj->baud); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uart_parity_t hal_parity; + switch (parity) { + case ParityNone: + hal_parity = UART_PARITY_NONE; + break; + case ParityOdd: + hal_parity = UART_PARITY_ODD; + break; + case ParityEven: + hal_parity = UART_PARITY_EVEN; + break; + default: + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "Unsupported parity"); + } + uart_set_format(obj->dev, data_bits, stop_bits, hal_parity); +} + +static volatile uart_irq_handler irq_handler; +static volatile uint32_t serial_irq_ids[2] = {0}; + +static inline void uart0_irq(void) +{ + irq_handler(serial_irq_ids[0], RxIrq); +} + +static inline void uart1_irq(void) +{ + irq_handler(serial_irq_ids[1], RxIrq); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + int UART_IRQ = obj->dev == uart0 ? UART0_IRQ : UART1_IRQ; + if (obj->dev == uart0) { + serial_irq_ids[0] = id; + } else { + serial_irq_ids[1] = id; + } + irq_handler = handler; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + int UART_IRQ = obj->dev == uart0 ? UART0_IRQ : UART1_IRQ; + + irq_set_exclusive_handler(UART_IRQ, obj->dev == uart0 ? uart0_irq : uart1_irq); + irq_set_enabled(UART_IRQ, enable); + + uart_set_irq_enables(obj->dev, irq == RxIrq, irq == TxIrq); +} + +int serial_getc(serial_t *obj) +{ + return uart_getc(obj->dev); +} + +void serial_putc(serial_t *obj, int c) +{ + uart_putc_raw(obj->dev, c); +} + +int serial_readable(serial_t *obj) +{ + return uart_is_readable(obj->dev); +} + +int serial_writable(serial_t *obj) +{ + return uart_is_writable(obj->dev); +} + +void serial_clear(serial_t *obj) +{ + MBED_WARNING(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "serial_clear"); +} + +void serial_break_set(serial_t *obj) +{ + uart_set_break(obj->dev, true); +} + +void serial_break_clear(serial_t *obj) +{ + uart_set_break(obj->dev, false); +} + +void serial_pinout_tx(PinName tx) +{ + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "serial_pinout_tx"); +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + obj->pin_rts = rxflow; + obj->pin_cts = txflow; + + if (obj->pin_rts != NC) { + gpio_set_function(obj->pin_rts, GPIO_FUNC_UART); + } + if (obj->pin_cts != NC) { + gpio_set_function(obj->pin_cts, GPIO_FUNC_UART); + } + + if (type == FlowControlRTSCTS) { + uart_set_hw_flow(obj->dev, true, true); + } else { + uart_set_hw_flow(obj->dev, type == FlowControlCTS, type == FlowControlRTS); + } +} + +const PinMap *serial_tx_pinmap(void) +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap(void) +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap(void) +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap(void) +{ + return PinMap_UART_RTS; +} + +#endif \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index 239260df44d..6bf4c4af106 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9421,7 +9421,8 @@ "device_has": [ "ANALOGIN", "PORT_IN", - "PORT_OUT" + "PORT_OUT", + "SERIAL" ] }, "NANO_RP2040_CONNECT": { @@ -9430,7 +9431,8 @@ "PICO_NO_BINARY_INFO=1", "MBED_MPU_CUSTOM", "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", - "PICO_ON_DEVICE=1" + "PICO_ON_DEVICE=1", + "PICO_UART_ENABLE_CRLF_SUPPORT=0" ] }, "__build_tools_metadata__": { From ba63f1ff4ef571e72ee250445680758ce8f2fe26 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 12 Feb 2021 17:03:32 +0100 Subject: [PATCH 019/227] RP2040: add pinmap for i2c, spi, pwm --- .../TARGET_RP2040/PeripheralNames.h | 6 +- .../TARGET_RP2040/PeripheralPins.c | 121 ++++++++++++++++++ .../TARGET_RP2040/PeripheralPins.h | 4 +- 3 files changed, 127 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h index 220d4a831ef..3d512ba87f5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h @@ -43,12 +43,14 @@ typedef enum { } I2CName; typedef enum { - PWM_1 = 0, + PWM_0 = 0, + PWM_1, PWM_2, PWM_3, PWM_4, PWM_5, - PWM_6 + PWM_6, + PWM_7 } PWMName; /* Defines to be used by application */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c index 97a2acd2618..67329993d41 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c @@ -82,4 +82,125 @@ const PinMap PinMap_UART_RTS[] = { {p23, UART_1, (uint32_t) uart1}, {p27, UART_1, (uint32_t) uart1}, {NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM_OUT[] = { + {p0, PWM_0, 0}, + {p1, PWM_0, 0}, + {p2, PWM_1, 0}, + {p3, PWM_1, 0}, + {p4, PWM_2, 0}, + {p5, PWM_2, 0}, + {p6, PWM_3, 0}, + {p7, PWM_3, 0}, + {p8, PWM_4, 0}, + {p9, PWM_4, 0}, + {p10, PWM_5, 0}, + {p11, PWM_5, 0}, + {p12, PWM_6, 0}, + {p13, PWM_6, 0}, + {p14, PWM_7, 0}, + {p15, PWM_7, 0}, + {p16, PWM_0, 0}, + {p17, PWM_0, 0}, + {p18, PWM_1, 0}, + {p19, PWM_1, 0}, + {p20, PWM_2, 0}, + {p21, PWM_2, 0}, + {p22, PWM_3, 0}, + {p23, PWM_3, 0}, + {p24, PWM_4, 0}, + {p25, PWM_4, 0}, + {p26, PWM_5, 0}, + {p27, PWM_5, 0}, + {p28, PWM_6, 0}, + {p29, PWM_6, 0}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_MISO[] = { + {p0, SPI_0, (uint32_t) spi0}, + {p4, SPI_0, (uint32_t) spi0}, + {p8, SPI_1, (uint32_t) spi0}, + {p12, SPI_1, (uint32_t) spi0}, + {p16, SPI_0, (uint32_t) spi0}, + {p20, SPI_0, (uint32_t) spi0}, + {p24, SPI_1, (uint32_t) spi0}, + {p28, SPI_1, (uint32_t) spi0}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {p1, SPI_0, (uint32_t) spi0}, + {p5, SPI_0, (uint32_t) spi0}, + {p9, SPI_1, (uint32_t) spi0}, + {p13, SPI_1, (uint32_t) spi0}, + {p17, SPI_0, (uint32_t) spi0}, + {p21, SPI_0, (uint32_t) spi0}, + {p25, SPI_1, (uint32_t) spi0}, + {p29, SPI_1, (uint32_t) spi0}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {p2, SPI_0, (uint32_t) spi0}, + {p6, SPI_0, (uint32_t) spi0}, + {p10, SPI_1, (uint32_t) spi1}, + {p14, SPI_1, (uint32_t) spi1}, + {p18, SPI_0, (uint32_t) spi0}, + {p22, SPI_0, (uint32_t) spi0}, + {p26, SPI_1, (uint32_t) spi1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {p3, SPI_0, (uint32_t) spi0}, + {p7, SPI_0, (uint32_t) spi0}, + {p11, SPI_1, (uint32_t) spi1}, + {p15, SPI_1, (uint32_t) spi1}, + {p19, SPI_0, (uint32_t) spi0}, + {p23, SPI_0, (uint32_t) spi0}, + {p27, SPI_1, (uint32_t) spi1}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {p0, I2C_0, (uint32_t) i2c0}, + {p2, I2C_1, (uint32_t) i2c1}, + {p4, I2C_0, (uint32_t) i2c0}, + {p6, I2C_1, (uint32_t) i2c1}, + {p8, I2C_0, (uint32_t) i2c0}, + {p10, I2C_1, (uint32_t) i2c1}, + {p12, I2C_0, (uint32_t) i2c0}, + {p14, I2C_1, (uint32_t) i2c1}, + {p16, I2C_0, (uint32_t) i2c0}, + {p18, I2C_1, (uint32_t) i2c1}, + {p20, I2C_0, (uint32_t) i2c0}, + {p22, I2C_1, (uint32_t) i2c1}, + {p24, I2C_0, (uint32_t) i2c0}, + {p26, I2C_1, (uint32_t) i2c1}, + {p28, I2C_0, (uint32_t) i2c0}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {p1, I2C_0, (uint32_t) i2c0}, + {p3, I2C_1, (uint32_t) i2c1}, + {p5, I2C_0, (uint32_t) i2c0}, + {p7, I2C_1, (uint32_t) i2c1}, + {p9, I2C_0, (uint32_t) i2c0}, + {p11, I2C_1, (uint32_t) i2c1}, + {p13, I2C_0, (uint32_t) i2c0}, + {p15, I2C_1, (uint32_t) i2c1}, + {p17, I2C_0, (uint32_t) i2c0}, + {p19, I2C_1, (uint32_t) i2c1}, + {p21, I2C_0, (uint32_t) i2c0}, + {p23, I2C_1, (uint32_t) i2c1}, + {p25, I2C_0, (uint32_t) i2c0}, + {p27, I2C_1, (uint32_t) i2c1}, + {p29, I2C_0, (uint32_t) i2c0}, + {NC, NC, 0} }; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h index abeaed1d82a..482f8f499cb 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.h @@ -43,10 +43,10 @@ extern const PinMap PinMap_UART_CTS[]; //*** SPI *** #if DEVICE_SPI -extern const PinMap PinMap_SPI_MOSI[]; extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; extern const PinMap PinMap_SPI_SSEL[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; #endif //*** ADC *** From 893e1e8250d399a91e810c107bdecaef3a50f11a Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Feb 2021 12:24:50 +0100 Subject: [PATCH 020/227] RP2040: Mark .init section as KEEP --- .../TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld index 07d5812db1f..fb2ff6d18aa 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld @@ -67,7 +67,7 @@ SECTIONS /* TODO revisit this now memset/memcpy/float in ROM */ /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from * FLASH ... we will include any thing excluded here in .data below by default */ - *(.init) + KEEP (*(.init)) *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) *(.fini) /* Pull all c'tors into .text */ From 0fa87a1cc7f755216ecdd36fd37f6dfe6e06695d Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Mon, 15 Feb 2021 13:52:41 +0100 Subject: [PATCH 021/227] RP2040: implement mbed api analogin. --- .../TARGET_RP2040/PeripheralNames.h | 5 +- .../TARGET_RP2040/PeripheralPins.c | 16 +++++- .../TARGET_RP2040/analogin_api.c | 57 +++++++++++++++++++ .../TARGET_RP2040/objects.h | 2 - 4 files changed, 73 insertions(+), 7 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h index 3d512ba87f5..67353ffe81d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h @@ -26,10 +26,7 @@ typedef enum { } UARTName; typedef enum { - ADC0_0 = 26, - ADC0_1, - ADC0_2, - ADC0_3 + ADC0 = 0, } ADCName; typedef enum { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c index 67329993d41..6364d42a5c3 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c @@ -203,4 +203,18 @@ const PinMap PinMap_I2C_SCL[] = { {p27, I2C_1, (uint32_t) i2c1}, {p29, I2C_0, (uint32_t) i2c0}, {NC, NC, 0} -}; \ No newline at end of file +}; + +/************ADC***************/ +/* ADC inputs 0-3 are GPIOs 26-29, ADC input 4 + * is the onboard temperature sensor. + */ +const PinMap PinMap_ADC[] = { + { A0, ADC0, 0}, + { A1, ADC0, 1}, + { A2, ADC0, 2}, + { A3, ADC0, 3}, + { ADC_TEMP, ADC0, 4}, + { NC, NC, 0} +}; + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c new file mode 100644 index 00000000000..4e95f4551f4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c @@ -0,0 +1,57 @@ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "adc.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +static float const ADC_VREF_VOLTAGE = 3.3f; /* 3.3V */ +static uint16_t const ADC_RESOLUTION_BITS = 12; +static float const ADC_CONVERSION_FACTOR = ADC_VREF_VOLTAGE / (1 << ADC_RESOLUTION_BITS); + +void analogin_init(analogin_t *obj, PinName pin) +{ + /* Make sure pin is an analog pin we can use for ADC */ + MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC); + + static bool is_adc_initialized = false; + /* Initialize the ADC the first time it is being used, + * but don't reinitialize it again afterwards. + */ + if (!is_adc_initialized) + { + adc_init(); + is_adc_initialized = true; + } + + /* Lookup the corresponding ADC channel for a given pin. */ + obj->channel = pinmap_find_function(pin, PinMap_ADC); + /* Make sure GPIO is high-impedance, no pullups etc. */ + adc_gpio_init(pin); + /* Check if the ADC channel we just configured belongs to the + * temperature sensor. If that's the case, enable the temperature + * sensor. + */ + if (pin == ADC_TEMP) + adc_set_temp_sensor_enabled(true); +} + +float analogin_read(analogin_t *obj) +{ + /* Read the raw 12-Bit value from the ADC. */ + uint16_t const analog_in_raw = analogin_read_u16(obj); + /* Convert it to a voltage value. */ + return (analog_in_raw * ADC_CONVERSION_FACTOR); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + /* Select the desired ADC input channel. */ + adc_select_input(obj->channel); + /* Read the 16-Bit ADC value. */ + return adc_read(); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index 7272492f2f7..16dab0daaf8 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -80,8 +80,6 @@ struct port_s { /* common objects */ struct analogin_s { - ADCName adc; - PinName pin; uint8_t channel; }; From e4afab4cad35622e4640ed1058fc5e4ab2afbd9e Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Mon, 15 Feb 2021 15:51:03 +0100 Subject: [PATCH 022/227] RP2040: add SPI support --- .../TARGET_RP2040/PeripheralPins.c | 16 +-- .../hardware_spi/include/hardware/spi.h | 2 +- .../pico-sdk/rp2_common/hardware_spi/spi.c | 2 +- .../TARGET_RP2040/spi_api.c | 111 ++++++++++++++++++ targets/targets.json | 3 +- 5 files changed, 123 insertions(+), 11 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c index 6364d42a5c3..6ba32555659 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralPins.c @@ -123,24 +123,24 @@ const PinMap PinMap_PWM_OUT[] = { const PinMap PinMap_SPI_MISO[] = { {p0, SPI_0, (uint32_t) spi0}, {p4, SPI_0, (uint32_t) spi0}, - {p8, SPI_1, (uint32_t) spi0}, - {p12, SPI_1, (uint32_t) spi0}, + {p8, SPI_1, (uint32_t) spi1}, + {p12, SPI_1, (uint32_t) spi1}, {p16, SPI_0, (uint32_t) spi0}, {p20, SPI_0, (uint32_t) spi0}, - {p24, SPI_1, (uint32_t) spi0}, - {p28, SPI_1, (uint32_t) spi0}, + {p24, SPI_1, (uint32_t) spi1}, + {p28, SPI_1, (uint32_t) spi1}, {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { {p1, SPI_0, (uint32_t) spi0}, {p5, SPI_0, (uint32_t) spi0}, - {p9, SPI_1, (uint32_t) spi0}, - {p13, SPI_1, (uint32_t) spi0}, + {p9, SPI_1, (uint32_t) spi1}, + {p13, SPI_1, (uint32_t) spi1}, {p17, SPI_0, (uint32_t) spi0}, {p21, SPI_0, (uint32_t) spi0}, - {p25, SPI_1, (uint32_t) spi0}, - {p29, SPI_1, (uint32_t) spi0}, + {p25, SPI_1, (uint32_t) spi1}, + {p29, SPI_1, (uint32_t) spi1}, {NC, NC, 0} }; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h index 3ee8736e0c5..789efc6f0d4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h @@ -86,7 +86,7 @@ typedef enum { * and this function does not return any indication of this. You can use the \ref spi_set_baudrate function * which will return the actual baudrate selected if this is important. */ -void spi_init(spi_inst_t *spi, uint baudrate); +void _spi_init(spi_inst_t *spi, uint baudrate); /*! \brief Deinitialise SPI instances * \ingroup hardware_spi diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c index b0cad30755c..1de19764e3c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c @@ -18,7 +18,7 @@ static inline void spi_unreset(spi_inst_t *spi) { unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); } -void spi_init(spi_inst_t *spi, uint baudrate) { +void _spi_init(spi_inst_t *spi, uint baudrate) { spi_reset(spi); spi_unreset(spi); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c new file mode 100644 index 00000000000..1cc6bfa0fb8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c @@ -0,0 +1,111 @@ +/****************************************************************************** + * INCLUDE + ******************************************************************************/ + +#include "mbed_assert.h" +#include "mbed_critical.h" +#include "spi_api.h" +#include "PeripheralPins.h" +#include "PeripheralNames.h" + +/****************************************************************************** + * CONSTANT + ******************************************************************************/ + +static unsigned int const SPI_MASTER_DEFAULT_BITRATE = 1000 * 1000; /* 1 MHz */ + +/****************************************************************************** + * FUNCTION DEFINITION + ******************************************************************************/ + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + /* Check if all pins do in fact belong to the same SPI module. */ + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + MBED_ASSERT(spi_mosi == spi_miso); + MBED_ASSERT(spi_miso == spi_sclk); + MBED_ASSERT(spi_sclk == spi_ssel); + MBED_ASSERT(spi_ssel != (SPIName)NC); + + /* Obtain pointer to the SPI module. */ + obj->dev = (spi_inst_t *)pinmap_function(mosi, PinMap_SPI_MOSI); + + /* Configure GPIOs for SPI usage. */ + gpio_set_function(mosi, GPIO_FUNC_SPI); + gpio_set_function(sclk, GPIO_FUNC_SPI); + gpio_set_function(miso, GPIO_FUNC_SPI); + + /* Initialize SPI at 1 MHz bitrate */ + _spi_init(obj->dev, SPI_MASTER_DEFAULT_BITRATE); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + /* Doing some parameter sanity checks. */ + MBED_ASSERT((bits >= 4) && (bits <= 16)); + MBED_ASSERT((mode >= 0) && (mode <= 3)); + + /* Determine parameters for CPOL, CPHA */ + typedef struct + { + spi_cpol_t cpol; + spi_cpha_t cpha; + } spi_mode_t; + spi_mode_t const SPI_MODE[4] = + { + {SPI_CPOL_0, SPI_CPHA_0}, /* MODE 0 */ + {SPI_CPOL_0, SPI_CPHA_1}, /* MODE 1 */ + {SPI_CPOL_1, SPI_CPHA_0}, /* MODE 2 */ + {SPI_CPOL_1, SPI_CPHA_1} /* MODE 3 */ + }; + + /* Configure the SPI. */ + spi_set_format(obj->dev, bits, SPI_MODE[mode].cpol, SPI_MODE[mode].cpha, SPI_MSB_FIRST); + /* Set's the SPI up as slave if the value of slave is different from 0, e.g. a value of 1 or -1 set's this SPI up as a slave. */ + spi_set_slave(obj->dev, slave != 0); +} + +void spi_frequency(spi_t *obj, int hz) +{ + spi_set_baudrate(obj->dev, hz); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint8_t rx; + uint8_t const tx = (uint8_t)value; + spi_write_read_blocking(obj->dev, &tx, &rx, sizeof(rx)); + return rx; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + /* The pico-sdk API does not support different length SPI buffers. */ + MBED_ASSERT(tx_length == rx_length); + /* Perform the SPI transfer. */ + return spi_write_read_blocking(obj->dev, (const uint8_t *)tx_buffer, (uint8_t *)rx_buffer, (size_t)tx_length); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} diff --git a/targets/targets.json b/targets/targets.json index 6bf4c4af106..ec39112970c 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9422,7 +9422,8 @@ "ANALOGIN", "PORT_IN", "PORT_OUT", - "SERIAL" + "SERIAL", + "SPI" ] }, "NANO_RP2040_CONNECT": { From d6fea51098dae1c0922183e7844c76bc83afd6e5 Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Tue, 16 Feb 2021 06:30:59 +0100 Subject: [PATCH 023/227] RP2040: prefix pico-sdk's i2c_init function with a '_' to avoid name clashes with mbed I2C API. --- .../TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c | 2 +- .../pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c index cc4212ae9af..dc2810187ea 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c @@ -31,7 +31,7 @@ static inline bool i2c_reserved_addr(uint8_t addr) { return (addr & 0x78) == 0 || (addr & 0x78) == 0x78; } -uint i2c_init(i2c_inst_t *i2c, uint baudrate) { +uint _i2c_init(i2c_inst_t *i2c, uint baudrate) { i2c_reset(i2c); i2c_unreset(i2c); i2c->restart_on_next = false; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index dda598c3e0c..ead7bf1b1bb 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -80,7 +80,7 @@ extern i2c_inst_t i2c1_inst; * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) * \return Actual set baudrate */ -uint i2c_init(i2c_inst_t *i2c, uint baudrate); +uint _i2c_init(i2c_inst_t *i2c, uint baudrate); /*! \brief Disable the I2C HW block * \ingroup hardware_i2c From e3f2b9e35f7c557ecea0cd92b763aac2f63bed59 Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Tue, 16 Feb 2021 06:29:59 +0100 Subject: [PATCH 024/227] RP2040: add I2C peripheral support --- .../TARGET_RP2040/i2c_api.c | 88 +++++++++++++++++++ .../TARGET_RP2040/objects.h | 1 + targets/targets.json | 1 + 3 files changed, 90 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c new file mode 100644 index 00000000000..210279b3b01 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c @@ -0,0 +1,88 @@ +/****************************************************************************** + * INCLUDE + ******************************************************************************/ + +#include "mbed_assert.h" +#include "i2c_api.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +/****************************************************************************** + * CONST + ******************************************************************************/ + +static unsigned int const DEFAULT_I2C_BAUDRATE = 100 * 1000; /* 100 kHz */ + +/****************************************************************************** + * FUNCTION DEFINITION + ******************************************************************************/ + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + /* Verify if both pins belong to the same I2C peripheral. */ + I2CName const i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName const i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + MBED_ASSERT(i2c_sda == i2c_scl); + + /* Obtain the pointer to the I2C hardware instance. */ + obj->dev = (i2c_inst_t *)pinmap_function(sda, PinMap_I2C_SDA); + obj->baudrate = DEFAULT_I2C_BAUDRATE; + + /* Initialize the I2C module. */ + _i2c_init(obj->dev, obj->baudrate); + + /* Configure GPIO for I2C as alternate function. */ + gpio_set_function(sda, GPIO_FUNC_I2C); + gpio_set_function(scl, GPIO_FUNC_I2C); + + /* Enable pull-ups for I2C pins. */ + gpio_pull_up(sda); + gpio_pull_up(scl); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + obj->baudrate = i2c_set_baudrate(obj->dev, hz); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int const bytes_read = i2c_read_blocking(obj->dev, + (uint8_t)address, + (uint8_t *)data, + (size_t)length, + /* nostop = */(stop == 0)); + if (bytes_read < 0) + return I2C_ERROR_NO_SLAVE; + else + return bytes_read; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int const bytes_written = i2c_write_blocking(obj->dev, + address, + (const uint8_t *)data, + (size_t)length, + /* nostop = */(stop == 0)); + if (bytes_written < 0) + return I2C_ERROR_NO_SLAVE; + else + return bytes_written; +} + +void i2c_reset(i2c_t *obj) +{ + i2c_deinit(obj->dev); + _i2c_init(obj->dev, obj->baudrate); +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index 16dab0daaf8..061cee5908a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -94,6 +94,7 @@ struct serial_s { struct i2c_s { i2c_inst_t * dev; + unsigned int baudrate; }; struct spi_s { diff --git a/targets/targets.json b/targets/targets.json index ec39112970c..a383c71b276 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9420,6 +9420,7 @@ }, "device_has": [ "ANALOGIN", + "I2C", "PORT_IN", "PORT_OUT", "SERIAL", From 8e1cdfb6560a0c090631dc20cbc32d8926890e12 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 10:41:45 +0100 Subject: [PATCH 025/227] RP2040: implement USBDevice Code by @ghollingworth --- .../TARGET_RP2040/USBPhyHw.h | 77 +++ .../TARGET_RP2040/USBPhy_RP2040.cpp | 511 ++++++++++++++++++ targets/targets.json | 4 +- 3 files changed, 591 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhyHw.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhyHw.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhyHw.h new file mode 100644 index 00000000000..d0f938851fa --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhyHw.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2018-2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USBPHYHW_H +#define USBPHYHW_H + +#include "mbed.h" +#include "USBPhy.h" +#include "hardware/structs/usb.h" + +typedef struct endpoint_info_ { + uint8_t *data; // pointer to user memory to store data to + uint8_t next_pid; // Next DATA0/DATA1 PID to use on this endpoint + uint8_t *dpram; // Pointer into the dpram for endpoint data +} endpoint_info_t; + +class USBPhyHw : public USBPhy { +public: + USBPhyHw(); + virtual ~USBPhyHw(); + virtual void init(USBPhyEvents *events); + virtual void deinit(); + virtual bool powered(); + virtual void connect(); + virtual void disconnect(); + virtual void configure(); + virtual void unconfigure(); + virtual void sof_enable(); + virtual void sof_disable(); + virtual void set_address(uint8_t address); + virtual void remote_wakeup(); + virtual const usb_ep_table_t *endpoint_table(); + + virtual uint32_t ep0_set_max_packet(uint32_t max_packet); + virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size); + virtual void ep0_read(uint8_t *data, uint32_t size); + virtual uint32_t ep0_read_result(); + virtual void ep0_write(uint8_t *buffer, uint32_t size); + virtual void ep0_stall(); + + virtual bool endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type); + virtual void endpoint_remove(usb_ep_t endpoint); + virtual void endpoint_stall(usb_ep_t endpoint); + virtual void endpoint_unstall(usb_ep_t endpoint); + + virtual bool endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual uint32_t endpoint_read_result(usb_ep_t endpoint); + virtual bool endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual void endpoint_abort(usb_ep_t endpoint); + + virtual void process(); + +private: + USBPhyEvents *events; + int new_addr; // Indicates a new device address has been chosen + uint32_t dpram_buffer_free_ptr; + endpoint_info_t ep_info_in [USB_NUM_ENDPOINTS]; + endpoint_info_t ep_info_out[USB_NUM_ENDPOINTS]; + + static void _usbisr(void); +}; + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp new file mode 100644 index 00000000000..2ef354035d6 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2018-2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "USBPhyHw.h" +// USB register definitions from pico-sdk +#include "hardware/regs/usb.h" +// USB hardware struct definitions from pico-sdk +#include "hardware/structs/usb.h" +// For interrupt enable and numbers +#include "hardware/irq.h" +// For resetting the USB controller +#include "hardware/resets.h" + +#ifdef PICO_RP2040_USB_DEVICE_ENUMERATION_FIX +#include "rp2040_usb_device_enumeration.h" +#endif + +// These accessor functions are used to implement bit clear / bit sets through +// an atomic alias (this handles the state where both cores can access a register +// and cause a bit loss through a read-modify-write access) +#define usb_hw_set hw_set_alias(usb_hw) +#define usb_hw_clear hw_clear_alias(usb_hw) + +static USBPhyHw *instance; + +USBPhy *get_usb_phy() +{ + static USBPhyHw usbphy; + return &usbphy; +} + +USBPhyHw::USBPhyHw(): events(NULL) +{ + +} + +USBPhyHw::~USBPhyHw() +{ + +} + +void USBPhyHw::init(USBPhyEvents *events) +{ + this->events = events; + this->new_addr = 0; + instance = this; + + // Disable IRQ + NVIC_DisableIRQ(USBCTRL_IRQn); + + // Reset usb controller + reset_block(RESETS_RESET_USBCTRL_BITS); + unreset_block_wait(RESETS_RESET_USBCTRL_BITS); + + // Clear any previous state in dpram just in case + memset(usb_dpram, 0, sizeof(*usb_dpram)); + + // Mux the controller to the onboard usb phy + usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS; + + // Force VBUS detect so the device thinks it is plugged into a host + usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS; + + // Enable the USB controller in device mode. + usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS; + + // Enable IRQ + NVIC_SetVector(USBCTRL_IRQn, (uint32_t)&_usbisr); + NVIC_EnableIRQ(USBCTRL_IRQn); +} + +void USBPhyHw::deinit() +{ + // Disconnect and disable interrupt + disconnect(); + NVIC_DisableIRQ(USBCTRL_IRQn); +} + +bool USBPhyHw::powered() +{ + return true; +} + +void USBPhyHw::connect() +{ + // Enable interrupts for when a buffer is done, when the bus is reset, + // and when a setup packet is received + usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | + USB_INTS_BUS_RESET_BITS | + USB_INTS_SETUP_REQ_BITS; + + // Present full speed device by enabling pull up on DP + usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; + + // Enable interrupts on EP0, single buffered + usb_hw_set->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS; +} + +void USBPhyHw::disconnect() +{ + // Clear all endpoint interrupts and disable interrupts + memset(&usb_dpram->ep_ctrl[0], 0, sizeof(*usb_dpram) - sizeof(usb_dpram->setup_packet)); + + // TODO - Disable pullup on D+ + usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; +} + +void USBPhyHw::configure() +{ + // Nothing to be done +} + +void USBPhyHw::unconfigure() +{ + // Also nothing to do here +} + +void USBPhyHw::sof_enable() +{ + usb_hw_set->inte = USB_INTE_DEV_SOF_BITS; +} + +void USBPhyHw::sof_disable() +{ + usb_hw_clear->inte = USB_INTE_DEV_SOF_BITS; +} + +void USBPhyHw::set_address(uint8_t address) +{ + // We can't set the device address here, because we're only half way + // through the control transfer (the OUT bit), we need to wait until the + // IN bit is completed (the status phase) before setting it... + this->new_addr = address; +} + +void USBPhyHw::remote_wakeup() +{ + // Send remote wakeup over USB lines + // TODO - confirm that the resume doesn't require resetting + usb_hw_set->sie_ctrl = USB_SIE_CTRL_RESUME_BITS; +} + +const usb_ep_table_t *USBPhyHw::endpoint_table() +{ + static const usb_ep_table_t template_table = { + sizeof(usb_dpram->epx_data), + { + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0}, + } + }; + return &template_table; +} + +uint32_t USBPhyHw::ep0_set_max_packet(uint32_t max_packet) +{ + // Our max packet size is 64 bytes + return 64; +} + +// read setup packet +void USBPhyHw::ep0_setup_read_result(uint8_t *buffer, uint32_t size) +{ + memcpy(buffer, (void *) usb_dpram->setup_packet, size < 8 ? size : 8); +} + +void USBPhyHw::ep0_read(uint8_t *data, uint32_t size) +{ + endpoint_info_t * ep = &this->ep_info_out[0]; + + ep->data = data; + + usb_dpram->ep_buf_ctrl[0].out = (size & USB_BUF_CTRL_LEN_MASK) | + USB_BUF_CTRL_AVAIL | + (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : 0); + + ep->next_pid = !ep->next_pid; +} + +uint32_t USBPhyHw::ep0_read_result() +{ + endpoint_info_t * ep = &this->ep_info_out[0]; + int buf_ctrl = usb_dpram->ep_buf_ctrl[0].out; + int sz = buf_ctrl & USB_BUF_CTRL_LEN_MASK; + + if(buf_ctrl & USB_BUF_CTRL_FULL) + { + if(ep->data != NULL) + { + memcpy(ep->data, ep->dpram, sz); + } + } + else + sz = 0; + + return sz; +} + +void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size) +{ + endpoint_info_t * ep = &this->ep_info_in[0]; + + if(buffer != NULL) + memcpy((void *) ep->dpram, buffer, size); + + __asm volatile ( + "b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1:\n" + : : : "memory"); + + usb_dpram->ep_buf_ctrl[0].in = size | + USB_BUF_CTRL_FULL | + USB_BUF_CTRL_AVAIL | + (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : 0) ; + ep->next_pid = !ep->next_pid; +} + +void USBPhyHw::ep0_stall() +{ + usb_hw->ep_stall_arm = 3; + usb_dpram->ep_buf_ctrl[0].in = USB_BUF_CTRL_STALL; + usb_dpram->ep_buf_ctrl[0].out = USB_BUF_CTRL_STALL; +} + +bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type) +{ + int ep_num = endpoint & 0x7f; + int in = endpoint >> 7; + io_rw_32 * ep_ctrl = in ? &usb_dpram->ep_ctrl[ep_num - 1].in : + &usb_dpram->ep_ctrl[ep_num - 1].out; + if(this->dpram_buffer_free_ptr + max_packet < sizeof(usb_dpram->epx_data) ) + { + endpoint_info_t * ep = in ? &this->ep_info_in[ep_num] : &this->ep_info_out[ep_num]; + ep->next_pid = 0; + ep->dpram = &usb_dpram->epx_data[this->dpram_buffer_free_ptr]; + + *ep_ctrl = + EP_CTRL_ENABLE_BITS | + EP_CTRL_INTERRUPT_PER_BUFFER | + type << EP_CTRL_BUFFER_TYPE_LSB | + EP_CTRL_INTERRUPT_ON_STALL | + (this->dpram_buffer_free_ptr + 0x180); + + this->dpram_buffer_free_ptr += (max_packet + 63) & ~63; + } + else + { + return false; + } + + return true; +} + +void USBPhyHw::endpoint_remove(usb_ep_t endpoint) +{ + // Halt here, unhandled + volatile int going = true; + while(going); +} + +void USBPhyHw::endpoint_stall(usb_ep_t endpoint) +{ + // Halt here, unhandled + volatile int going = true; + while(going); +} + +void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) +{ + // Halt here, unhandled + volatile int going = true; + while(going); +} + +bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + int ep_num = endpoint & 0x7f; + + endpoint_info_t * ep = &this->ep_info_out[ep_num]; + + ep->data = data; + + usb_dpram->ep_buf_ctrl[ep_num].out = + (size & USB_BUF_CTRL_LEN_MASK) | + USB_BUF_CTRL_AVAIL | + (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : 0); + + ep->next_pid = !ep->next_pid; + + return true; +} + +uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint) +{ + int ep_num = endpoint & 0x7f; + endpoint_info_t * ep = &this->ep_info_out[ep_num]; + + int buf_ctrl = usb_dpram->ep_buf_ctrl[ep_num].out; + int sz = buf_ctrl & USB_BUF_CTRL_LEN_MASK; + + if(buf_ctrl & USB_BUF_CTRL_FULL) + { + if(ep->data != NULL) + { + memcpy(ep->data, ep->dpram, sz); + } + } + else + sz = 0; + + return sz; +} + +bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + int ep_num = endpoint & 0x7f; + + endpoint_info_t * ep = &this->ep_info_in[ep_num]; + + if(data != NULL) + memcpy(ep->dpram, data, size); + + __asm volatile ( + "b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1: b 1f\n" + "1:\n" + : : : "memory"); + + + usb_dpram->ep_buf_ctrl[ep_num].in = size | + USB_BUF_CTRL_FULL | + USB_BUF_CTRL_AVAIL | + (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : 0); + + ep->next_pid = !ep->next_pid; + + return true; +} + +void USBPhyHw::endpoint_abort(usb_ep_t endpoint) +{ + // Unhandled, halt here + volatile int going = true; + while(going); +} + +void USBPhyHw::process() +{ + // reset interrupt + if (usb_hw->ints & USB_INTS_BUS_RESET_BITS) { + // Clear the device address + usb_hw->dev_addr_ctrl = 0; + // Reset all endpoint buffers and controls (leave SETUP packet) + memset(&usb_dpram->ep_ctrl[0], 0, sizeof(*usb_dpram) - sizeof(usb_dpram->setup_packet)); + this->dpram_buffer_free_ptr = 0; + // Clear the bus reset + usb_hw->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; + + // This is required, but having trouble working out how to link in +#ifdef PICO_RP2040_USB_DEVICE_ENUMERATION_FIX + rp2040_usb_device_enumeration_fix(); +#endif + + // reset bus for USBDevice layer + events->reset(); + + // Re-enable interrupt + NVIC_ClearPendingIRQ(USBCTRL_IRQn); + NVIC_EnableIRQ(USBCTRL_IRQn); + return; + } + + // Received SETUP packet + if(usb_hw->ints & USB_INTS_SETUP_REQ_BITS) + { + this->ep_info_in [0].next_pid = 1; + this->ep_info_in [0].dpram = usb_dpram->ep0_buf_a; + this->ep_info_out[0].next_pid = 1; + this->ep_info_out[0].dpram = usb_dpram->ep0_buf_a; + events->ep0_setup(); + // Clear interrupt + usb_hw->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; + } + + // BUFF_STATUS bits have changed + if(usb_hw->ints & USB_INTS_BUFF_STATUS_BITS) + { + uint32_t buff_status = usb_hw->buf_status; + int i; + + // EP0 IN + if(buff_status & 1) + { + // Clear this bit + usb_hw->buf_status = 1; + events->ep0_in(); + + // If we got a new address in the (OUT) DATA stage of a control + // transfer, then set it here after having received the (IN) STATUS + // stage + if(this->new_addr != 0) + { + usb_hw->dev_addr_ctrl = this->new_addr; + this->new_addr = 0; + } + } + + // EP0 OUT + if(buff_status & 2) + { + // Clear this bit + usb_hw->buf_status = 2; + events->ep0_out(); + } + + // Go through the rest of the bits + for(i = 2; i < 32; i++) + { + if(buff_status & (1 << i)) + { + // Clear the bit + usb_hw->buf_status = 1 << i; + if(i & 1) + { + events->out(i / 2); + } + else + { + events->in(0x80 | (i / 2)); + } + } + } + } + + // sof interrupt + if (usb_hw->ints & USB_INTR_DEV_SOF_BITS) { + // SOF event, read frame number + events->sof(usb_hw->sof_rd); + } + + // Suspend / Resume not tested, not found a way of triggering suspend + if(usb_hw->ints & USB_INTS_DEV_RESUME_FROM_HOST_BITS) + { + // Will clear the interrupt + usb_hw_set->sie_ctrl = USB_SIE_CTRL_RESUME_BITS; + events->suspend(false); + } + + if(usb_hw->ints & USB_INTS_DEV_SUSPEND_BITS) + { + usb_hw->sie_status = USB_SIE_STATUS_SUSPENDED_BITS; + events->suspend(true); + } + + // If any interrupts are still set (except BUFSTATUS), then hang for analysis + // This is only for debug while developing the driver + if(usb_hw->ints & ~16) + { + volatile int ints = usb_hw->ints; + volatile int going = 1; + while(ints && going); + } + + + // Re-enable interrupt + NVIC_ClearPendingIRQ(USBCTRL_IRQn); + NVIC_EnableIRQ(USBCTRL_IRQn); +} + +void USBPhyHw::_usbisr(void) +{ + NVIC_DisableIRQ(USBCTRL_IRQn); + instance->events->start_process(); +} diff --git a/targets/targets.json b/targets/targets.json index a383c71b276..93ff9bb0830 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9424,12 +9424,14 @@ "PORT_IN", "PORT_OUT", "SERIAL", - "SPI" + "SPI", + "USBDEVICE" ] }, "NANO_RP2040_CONNECT": { "inherits": ["RP2040"], "macros_add": [ + "PICO_HEAP_SIZE=0x30000", "PICO_NO_BINARY_INFO=1", "MBED_MPU_CUSTOM", "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", From 9aedeae665bf291e739a8d2fb3aee162f62b457c Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 16:46:39 +0100 Subject: [PATCH 026/227] RP2040: avoid float.h first level inclusion --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore | 1 + .../pico-sdk/rp2_common/pico_float/include/placeholder.h | 0 2 files changed, 1 insertion(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore index 2b44582cfcf..f0ee61c1603 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -13,6 +13,7 @@ pico-sdk/rp2_common/pico_double/double_aeabi.S pico-sdk/rp2_common/pico_double/double_none.S pico-sdk/rp2_common/pico_float/float_aeabi.S pico-sdk/rp2_common/pico_float/float_none.S +pico-sdk/rp2_common/pico_float/include/pico/* pico-sdk/rp2_common/pico_standard_link/new_delete.cpp pico-sdk/rp2_common/pico_standard_link/*.ld pico-sdk/rp2_common/pico_unique_id/* diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d From 0e81f0e842ceb11f61d99b541dc87e46517a8032 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 16:47:27 +0100 Subject: [PATCH 027/227] RP2040: don't initalize contructors during runtime_init() --- .../pico-sdk/rp2_common/pico_runtime/runtime.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c index bd11d8f80b2..22ff5208e62 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c @@ -142,19 +142,6 @@ void runtime_init(void) { spin_locks_reset(); irq_init_priorities(); alarm_pool_init_default(); - - // Start and end points of the constructor list, - // defined by the linker script. - extern void (*__init_array_start)(); - extern void (*__init_array_end)(); - - // Call each function in the list. - // We have to take the address of the symbols, as __init_array_start *is* - // the first function pointer, not the address of it. - for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) { - (*p)(); - } - } void __exit(int status) { From ac48559b2e03d5c3cc756da189b6bfd0d93ee5ab Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 16:48:23 +0100 Subject: [PATCH 028/227] RP2040: add pwm driver --- .../TARGET_RP2040/objects.h | 9 + .../TARGET_RP2040/pwmout_api.c | 198 ++++++++++++++++++ targets/targets.json | 1 + 3 files changed, 208 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index 061cee5908a..5e5f2f0d6a4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -101,6 +101,15 @@ struct spi_s { spi_inst_t * dev; }; +struct pwmout_s { + PinName pin; + uint8_t slice; + uint8_t channel; + uint16_t period; + float percent; + pwm_config cfg; +}; + struct flash_s { /* nothing to be stored for now */ uint32_t dummy; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c new file mode 100644 index 00000000000..5f5d8479959 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if DEVICE_PWMOUT + +#include "hal/pwmout_api.h" +#include "PeripheralPins.h" +#include "pinmap.h" +#include "hardware/pwm.h" +#include "hardware/clocks.h" + +const uint count_top = 1000; + +/** Initialize the pwm out peripheral and configure the pin + * + * Parameter obj The pwmout object to initialize + * Parameter pin The pwmout pin to initialize + */ +void pwmout_init(pwmout_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + /* Populate PWM object with default values. */ + obj->slice = pwm_gpio_to_slice_num(pin); + obj->channel = pwm_gpio_to_channel(pin); + obj->pin = pin; + obj->period = 0; + obj->percent = 0.5f; + + obj->cfg = pwm_get_default_config(); + pwm_config_set_wrap(&(obj->cfg), count_top); + + pwm_init(obj->slice, &(obj->cfg), false); + gpio_set_function(pin, GPIO_FUNC_PWM); +} + +/** Deinitialize the pwmout object + * + * Parameter obj The pwmout object + */ +void pwmout_free(pwmout_t *obj) +{ + MBED_ASSERT(obj); + pwm_set_enabled(obj->slice, false); +} + +/** Set the output duty-cycle in range <0.0f, 1.0f> + * + * pulse 0.0f represents 0 percentage, 1.0f represents 100 percent. + * Parameter obj The pwmout object + * Parameter percent The floating-point percentage number + */ +void pwmout_write(pwmout_t *obj, float percent) +{ + obj->percent = percent; + pwm_set_gpio_level(obj->pin, percent * (count_top + 1)); +} + +/** Read the current float-point output duty-cycle + * + * Parameter obj The pwmout object + * Return A floating-point output duty-cycle + */ +float pwmout_read(pwmout_t *obj) +{ + /* Return percentage stored in object instead of calculating the value. + * This prevents floating point rounding errors. + */ + return obj->percent; +} + +/** Set the PWM period specified in seconds, keeping the duty cycle the same + * + * Periods smaller than microseconds (the lowest resolution) are set to zero. + * Parameter obj The pwmout object + * Parameter seconds The floating-point seconds period + */ +void pwmout_period(pwmout_t *obj, float period) +{ + /* Set new period. */ + pwmout_period_us(obj, period * 1000000); +} + +/** Set the PWM period specified in miliseconds, keeping the duty cycle the same + * + * Parameter obj The pwmout object + * Parameter ms The milisecond period + */ +void pwmout_period_ms(pwmout_t *obj, int period) +{ + /* Set new period. */ + pwmout_period_us(obj, period * 1000); +} + +/** Set the PWM period specified in microseconds, keeping the duty cycle the same + * + * Parameter obj The pwmout object + * Parameter us The microsecond period + */ +void pwmout_period_us(pwmout_t *obj, int period) +{ + obj->period = period; + + // min_period should be 8us + uint32_t min_period = 1000000 * count_top / clock_get_hz(clk_sys); + + pwm_config_set_clkdiv(&(obj->cfg), (float)period / (float)min_period); + pwm_init(obj->slice, &(obj->cfg), false); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->period; +} + +/** Set the PWM pulsewidth specified in seconds, keeping the period the same. + * + * Parameter obj The pwmout object + * Parameter seconds The floating-point pulsewidth in seconds + */ +void pwmout_pulsewidth(pwmout_t *obj, float pulse) +{ + pwmout_pulsewidth_us(obj, pulse * 1000000); +} + +/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same. + * + * Parameter obj The pwmout object + * Parameter ms The floating-point pulsewidth in miliseconds + */ +void pwmout_pulsewidth_ms(pwmout_t *obj, int pulse) +{ + pwmout_pulsewidth_us(obj, pulse * 1000); +} + +/** Set the PWM pulsewidth specified in microseconds, keeping the period the same. + * + * Parameter obj The pwmout object + * Parameter us The floating-point pulsewidth in microseconds + */ +void pwmout_pulsewidth_us(pwmout_t *obj, int pulse) +{ + /* Cap pulsewidth to period. */ + if (pulse > obj->period) { + pulse = obj->period; + } + + obj->percent = (float) pulse / (float) obj->period; + + /* Restart instance with new values. */ + pwmout_write(obj, obj->percent); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) { + return (obj->period) * (obj->percent); +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM_OUT; +} + +#endif // DEVICE_PWMOUT diff --git a/targets/targets.json b/targets/targets.json index 93ff9bb0830..71aa57df06f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9423,6 +9423,7 @@ "I2C", "PORT_IN", "PORT_OUT", + "PWMOUT", "SERIAL", "SPI", "USBDEVICE" From 96c23bf6bab9858ef78d55702be690e7503d2503 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 16:48:58 +0100 Subject: [PATCH 029/227] RP2040: add flow control to SERIAL object --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index 71aa57df06f..d0e00a173c4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9425,6 +9425,7 @@ "PORT_OUT", "PWMOUT", "SERIAL", + "SERIAL_FC", "SPI", "USBDEVICE" ] From 9da0254589cc629d7bc602c1ec2280f333c45748 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 23 Feb 2021 16:52:04 +0100 Subject: [PATCH 030/227] RP2040: add lp and us timer lptimer is deactivated since it's meant to run at 1hz :| --- .../TARGET_RP2040/lp_ticker.c | 114 ++++++++++++++++++ .../TARGET_RP2040/us_ticker.c | 93 ++++++++++++++ targets/targets.json | 2 + 3 files changed, 209 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/lp_ticker.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/lp_ticker.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/lp_ticker.c new file mode 100644 index 00000000000..1e48dcbfd2f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/lp_ticker.c @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "lp_ticker_api.h" +#include "hardware/rtc.h" +#include "hardware/irq.h" +#include "hardware/resets.h" +#include "hardware/clocks.h" +#include "time.h" + +#include "platform/mbed_critical.h" + +#define RTC_COUNTER_BITS 32u +#define RTC_FREQ 1u + +#if DEVICE_LPTICKER + +/* LP ticker counts with 1Hz resolution */ +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + RTC_FREQ, + RTC_COUNTER_BITS + }; + return &info; +} + +static datetime_t now = { + .year = 0, + .month = 1, + .day = 1, + .dotw = 0, + .hour = 0, + .min = 0, + .sec = 0 +}; + +static datetime_t* epoch_to_datetime(timestamp_t epoch, datetime_t* date) { + return NULL; +} + +static timestamp_t datetime_to_epoch(datetime_t* date) { + struct tm t; + time_t t_of_day; + + t.tm_year = date->year; // Year + t.tm_mon = date->month + 1; // Month, where 0 = jan + t.tm_mday = date->day; // Day of the month + t.tm_hour = date->hour; + t.tm_min = date->min; + t.tm_sec = date->sec; + t_of_day = mktime(&t); + + return (long)t_of_day; +} + +void lp_ticker_init(void) +{ + if (rtc_running()) { + // Populates now struct with existing data + lp_ticker_read(); + return; + } + rtc_init(); + rtc_set_datetime(&now); +} + +void lp_ticker_free(void) +{ +} + +uint32_t lp_ticker_read() +{ + rtc_get_datetime(&now); + return 0; //datetime_to_epoch(&now); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + timestamp_t target_ts = lp_ticker_read() + timestamp; + datetime_t target; + epoch_to_datetime(target_ts, &target); + rtc_set_alarm(&target, NULL); +} + +void lp_ticker_fire_interrupt(void) +{ + rtc_get_datetime(&now); + rtc_set_alarm(&now, NULL); +} + +void lp_ticker_disable_interrupt(void) +{ + rtc_disable_alarm(); +} + +void lp_ticker_clear_interrupt(void) +{ +} + +#endif // DEVICE_LPTICKER diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c new file mode 100644 index 00000000000..00edf82830e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "us_ticker_api.h" +#include "mbed_critical.h" +#include "hardware/timer.h" + +#define US_TICKER_COUNTER_BITS 32u +#define US_TICKER_FREQ 1000000 + +/* us ticker is driven by 1MHz clock and counter length is 32 bits */ +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + US_TICKER_FREQ, + US_TICKER_COUNTER_BITS + }; + return &info; +} + +const uint8_t alarm_num = 0; + +void us_ticker_init(void) +{ + hardware_alarm_set_callback(alarm_num, us_ticker_irq_handler); +} + +uint32_t us_ticker_read() +{ + return time_us_32(); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + core_util_critical_section_enter(); + absolute_time_t target = {timestamp}; + hardware_alarm_set_target(alarm_num, target); + core_util_critical_section_exit(); +} + +void us_ticker_fire_interrupt(void) +{ + us_ticker_irq_handler(); +} + +void us_ticker_disable_interrupt(void) +{ + hardware_alarm_cancel(alarm_num); +} + +void us_ticker_clear_interrupt(void) +{ + hardware_alarm_cancel(alarm_num); +} + +void us_ticker_free(void) +{ +} diff --git a/targets/targets.json b/targets/targets.json index d0e00a173c4..6b16afb1ad9 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9421,12 +9421,14 @@ "device_has": [ "ANALOGIN", "I2C", + "INTERRUPTIN", "PORT_IN", "PORT_OUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", + "USTICKER", "USBDEVICE" ] }, From 258f7653add20a8e66b8a8ba1a15ec8d19f16c09 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 26 Feb 2021 12:51:25 +0100 Subject: [PATCH 031/227] RP2040: implement gpio_is_connected() --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c index 7f6131c9727..3d09714881c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c @@ -35,3 +35,6 @@ void gpio_dir(gpio_t *obj, PinDirection direction) } } +int gpio_is_connected(const gpio_t *obj) { + return (obj->pin == NC ? 0 : 1); +} \ No newline at end of file From 8ed4acea9462a625414e5fdf5858dfd3e6defff9 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 5 Mar 2021 17:01:18 +0100 Subject: [PATCH 032/227] RP2040: adapt linker script to mbed --- .../TOOLCHAIN_GCC_ARM/memmap_default.ld | 16 ++++++++++++---- .../rp2_common/pico_standard_link/crt0.S | 14 -------------- targets/targets.json | 1 - 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld index fb2ff6d18aa..d92bd42107f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld @@ -21,6 +21,12 @@ __stack (== StackTop) */ +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + MEMORY { FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k @@ -208,8 +214,9 @@ SECTIONS .heap (COPY): { __end__ = .; - end = __end__; + PROVIDE(end = .); *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; __HeapLimit = .; } > RAM @@ -226,19 +233,20 @@ SECTIONS { *(.stack1*) } > SCRATCH_X + .stack_dummy (COPY): { *(.stack*) - } > SCRATCH_Y + } > RAM .flash_end : { __flash_binary_end = .; } > FLASH /* stack limit is poorly named, but historically is maximum heap ptr */ - __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); - __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); __StackBottom = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S index 38de6086342..3f90b95ee21 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -313,17 +313,3 @@ __get_current_exception: mrs r0, ipsr uxtb r0, r0 bx lr - -// ---------------------------------------------------------------------------- -// Stack/heap dummies to set size - -.section .stack -// align to allow for memory protection (although this alignment is pretty much ignored by linker script) -.align 5 - .equ StackSize, PICO_STACK_SIZE -.space StackSize - -.section .heap -.align 2 - .equ HeapSize, PICO_HEAP_SIZE -.space HeapSize diff --git a/targets/targets.json b/targets/targets.json index 6b16afb1ad9..0d696c3196f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9435,7 +9435,6 @@ "NANO_RP2040_CONNECT": { "inherits": ["RP2040"], "macros_add": [ - "PICO_HEAP_SIZE=0x30000", "PICO_NO_BINARY_INFO=1", "MBED_MPU_CUSTOM", "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", From 309fe15100a5de30a9ea01b26aa9db7b97e25991 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 25 Feb 2021 18:44:50 +0100 Subject: [PATCH 033/227] RP2040: Start adding Flash support --- .../TARGET_RP2040/flash_api.c | 107 ++++++++++++++++++ targets/targets.json | 2 + 2 files changed, 109 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c new file mode 100644 index 00000000000..85e8f5c81fb --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c @@ -0,0 +1,107 @@ +/****************************************************************************** + * INCLUDE + ******************************************************************************/ + +#include "mbed_assert.h" +#include "mbed_critical.h" +#include "hal/flash_api.h" +#include "flash.h" +//#include "hal/lp_ticker_api.h" +//#include "PeripheralPins.h" +#include "PeripheralNames.h" + +/****************************************************************************** + * CONSTANT + ******************************************************************************/ + + + +/****************************************************************************** + * FUNCTION DEFINITION + ******************************************************************************/ + +int32_t flash_init(flash_t *obj) +{ + (void)(obj); + + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + (void)(obj); + + uint32_t address = 0; + + for (int i = 0; i < PICO_FLASH_SIZE_BYTES/FLASH_SECTOR_SIZE; i++ ) { + flash_range_erase(address, FLASH_SECTOR_SIZE); + address = address + FLASH_SECTOR_SIZE; + } + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + (void)(obj); + + flash_range_erase(address, FLASH_SECTOR_SIZE); + + return 0; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + (void)(obj); + + for (int i = 0; i < size; i++) { + data = (const uint8_t *) (XIP_BASE + address + i); + data++; + } + return 0; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + (void)(obj); + + flash_range_program(address, data, size); + + return 0; + +} + +uint32_t flash_get_size(const flash_t *obj) +{ + (void)(obj); + + return PICO_FLASH_SIZE_BYTES; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + (void)(obj); + + return FLASH_SECTOR_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + (void)(obj); + + return FLASH_PAGE_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return XIP_BASE; + +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; + +} \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index 0d696c3196f..ba6bcb69461 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9406,6 +9406,7 @@ }, "RP2040": { "inherits": ["Target"], + "components_add": ["FLASHIAP"], "core": "Cortex-M0+", "supported_toolchains": ["GCC_ARM"], "extra_labels": [ @@ -9420,6 +9421,7 @@ }, "device_has": [ "ANALOGIN", + "FLASH", "I2C", "INTERRUPTIN", "PORT_IN", From d9957ef0a81b3532670d76670d4848ef21d8f47e Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 3 Mar 2021 18:58:02 +0100 Subject: [PATCH 034/227] RP2040: Protect flash operations in critical sections + fix addresses --- .../TARGET_RP2040/flash_api.c | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c index 85e8f5c81fb..01f71958c5a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c @@ -1,14 +1,12 @@ /****************************************************************************** * INCLUDE ******************************************************************************/ +#if DEVICE_FLASH #include "mbed_assert.h" #include "mbed_critical.h" #include "hal/flash_api.h" -#include "flash.h" -//#include "hal/lp_ticker_api.h" -//#include "PeripheralPins.h" -#include "PeripheralNames.h" +#include "hardware/flash.h" /****************************************************************************** * CONSTANT @@ -31,13 +29,6 @@ int32_t flash_free(flash_t *obj) { (void)(obj); - uint32_t address = 0; - - for (int i = 0; i < PICO_FLASH_SIZE_BYTES/FLASH_SECTOR_SIZE; i++ ) { - flash_range_erase(address, FLASH_SECTOR_SIZE); - address = address + FLASH_SECTOR_SIZE; - } - return 0; } @@ -45,7 +36,11 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) { (void)(obj); + address = address - XIP_BASE; + + core_util_critical_section_enter(); flash_range_erase(address, FLASH_SECTOR_SIZE); + core_util_critical_section_exit(); return 0; } @@ -54,9 +49,10 @@ int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) { (void)(obj); + const uint8_t *flash_target_contents = (const uint8_t *) (address); + for (int i = 0; i < size; i++) { - data = (const uint8_t *) (XIP_BASE + address + i); - data++; + data[i] = flash_target_contents[i]; } return 0; } @@ -65,7 +61,11 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, { (void)(obj); + address = address - XIP_BASE; + + core_util_critical_section_enter(); flash_range_program(address, data, size); + core_util_critical_section_exit(); return 0; @@ -95,7 +95,6 @@ uint32_t flash_get_page_size(const flash_t *obj) uint32_t flash_get_start_address(const flash_t *obj) { return XIP_BASE; - } uint8_t flash_get_erase_value(const flash_t *obj) @@ -104,4 +103,6 @@ uint8_t flash_get_erase_value(const flash_t *obj) return 0xFF; -} \ No newline at end of file +} + +#endif \ No newline at end of file From 085758d0fc366cc527c6ba1e6aae2a232f55a4af Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 4 Mar 2021 11:05:14 +0100 Subject: [PATCH 035/227] RP2040: Check alignment + avoid passing const buf to flash_range_program() --- .../TARGET_RP2040/flash_api.c | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c index 01f71958c5a..fb1a28dd7f5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c @@ -38,6 +38,10 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) address = address - XIP_BASE; + if ((address % FLASH_SECTOR_SIZE) != 0) { + return -1; + } + core_util_critical_section_enter(); flash_range_erase(address, FLASH_SECTOR_SIZE); core_util_critical_section_exit(); @@ -63,9 +67,22 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, address = address - XIP_BASE; - core_util_critical_section_enter(); - flash_range_program(address, data, size); - core_util_critical_section_exit(); + if ((address % FLASH_PAGE_SIZE) != 0) { + return -1; + } + + uint8_t buf[FLASH_PAGE_SIZE]; + + for (int j = 0; j < size/FLASH_PAGE_SIZE; j++) { + for (int i = 0; i < FLASH_PAGE_SIZE; i++) { + buf[i] = data[j*FLASH_PAGE_SIZE + i]; + } + address = address + j*FLASH_PAGE_SIZE; + core_util_critical_section_enter(); + flash_range_program(address, buf, FLASH_PAGE_SIZE); + core_util_critical_section_exit(); + } + return 0; From 6bb5719c73273b0e46c401813dc87ec66f5c4610 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 5 Mar 2021 11:38:57 +0100 Subject: [PATCH 036/227] RP2040: Rename pico-sdk's gpio_irq_handler with a '_' to avoid clashes with mbed API --- .../TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c index 7051de309ab..28a137663b9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c @@ -80,7 +80,7 @@ void gpio_set_oeover(uint gpio, uint value) { ); } -static void gpio_irq_handler(void) { +static void _gpio_irq_handler(void) { io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) { @@ -124,7 +124,7 @@ void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled // TODO: Do we want to support a callback per GPIO pin? // Install IRQ handler _callbacks[get_core_num()] = callback; - irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler); + irq_set_exclusive_handler(IO_IRQ_BANK0, _gpio_irq_handler); irq_set_enabled(IO_IRQ_BANK0, true); } From f1b4a2d92d503d4d2cebbbe297dc36d3406f2fc9 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 5 Mar 2021 11:46:46 +0100 Subject: [PATCH 037/227] RP2040: Add gpio interrupt support --- .../TARGET_RP2040/gpio_api.c | 105 +++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c index 3d09714881c..a10a7d6c892 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c @@ -1,8 +1,15 @@ #include "mbed_assert.h" #include "hal/gpio_api.h" +#include "gpio_irq_api.h" #include "pinmap.h" #include "mbed_error.h" +#define GPIO_PIN_COUNT 30 + +static gpio_irq_handler m_irq_handler; +static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0}; +static uint32_t m_pico_events[GPIO_PIN_COUNT] = {0}; + void gpio_write(gpio_t *obj, int value) { gpio_put(obj->pin, value); @@ -16,16 +23,37 @@ int gpio_read(gpio_t *obj) void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; + + if (pin == (PinName)NC) { + return; + } + _gpio_init(obj->pin); } +static uint32_t gpio_convert_event(gpio_irq_event event) +{ + uint32_t irq_event = 0; + + if (event == IRQ_RISE) { + irq_event = GPIO_IRQ_EDGE_RISE; + } else if (event == IRQ_FALL) { + irq_event = GPIO_IRQ_EDGE_FALL; + } + + return irq_event; +} + void gpio_mode(gpio_t *obj, PinMode mode) { + MBED_ASSERT(obj->pin != (PinName)NC); + gpio_set_pulls(obj->pin, mode == PullUp, mode == PullDown); } void gpio_dir(gpio_t *obj, PinDirection direction) { + MBED_ASSERT(obj->pin != (PinName)NC); obj->direction = direction; if (direction == PIN_OUTPUT) { gpio_set_dir(obj->pin, GPIO_OUT); @@ -37,4 +65,79 @@ void gpio_dir(gpio_t *obj, PinDirection direction) int gpio_is_connected(const gpio_t *obj) { return (obj->pin == NC ? 0 : 1); -} \ No newline at end of file +} + + +/*********** + GPIO IRQ +***********/ + +#if DEVICE_INTERRUPTIN + +static void _gpio_irq(uint gpio, uint32_t events) +{ + gpio_irq_event ev; + if (events == GPIO_IRQ_EDGE_RISE) { + ev = IRQ_RISE; + } else if (events == GPIO_IRQ_EDGE_FALL) { + ev = IRQ_FALL; + } else { + ev = IRQ_NONE; + } + m_irq_handler(m_channel_ids[gpio], ev); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if (pin == NC) { + return -1; + } + MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); + + m_channel_ids[pin] = id; + m_irq_handler = handler; + + obj->irq_n = IO_IRQ_BANK0; + obj->pin = pin; + obj->irq_index = id; + + return 0; +} + + +void gpio_irq_free(gpio_irq_t *obj) +{ + gpio_irq_disable(obj); + obj->irq_n = 0; + obj->pin = 0; + obj->irq_index = 0; +} + + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t irq_event = gpio_convert_event(event); + + if (enable) { + m_pico_events[obj->pin] |= irq_event; + obj->event = irq_event; + gpio_irq_enable(obj); + } +} + + +void gpio_irq_enable(gpio_irq_t *obj) +{ + gpio_set_irq_enabled_with_callback(obj->pin, obj->event, true, _gpio_irq); +} + + +void gpio_irq_disable(gpio_irq_t *obj) +{ + gpio_set_irq_enabled(obj->pin, m_pico_events[obj->pin], false); + + obj->event = 0; + m_pico_events[obj->pin] = 0; +} + +#endif From b10230cc4b58ef5f04f89ad273a002a2f8a8e36b Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 8 Mar 2021 10:06:58 +0100 Subject: [PATCH 038/227] RP2040: usb: fix USB_DEVICE_ENUMERATION_FIX linking --- .../TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp | 9 +++++++++ targets/targets.json | 1 + 2 files changed, 10 insertions(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp index 2ef354035d6..c88bdcc573f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp @@ -16,6 +16,11 @@ */ #include "USBPhyHw.h" + +#ifdef __cplusplus +extern "C" { +#endif + // USB register definitions from pico-sdk #include "hardware/regs/usb.h" // USB hardware struct definitions from pico-sdk @@ -29,6 +34,10 @@ #include "rp2040_usb_device_enumeration.h" #endif +#ifdef __cplusplus +} +#endif + // These accessor functions are used to implement bit clear / bit sets through // an atomic alias (this handles the state where both cores can access a register // and cause a bit loss through a read-modify-write access) diff --git a/targets/targets.json b/targets/targets.json index ba6bcb69461..46935c06094 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9437,6 +9437,7 @@ "NANO_RP2040_CONNECT": { "inherits": ["RP2040"], "macros_add": [ + "PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1", "PICO_NO_BINARY_INFO=1", "MBED_MPU_CUSTOM", "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", From 18c7e73078a2ff55190d26194ba93fdb772138c8 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 8 Mar 2021 10:07:26 +0100 Subject: [PATCH 039/227] RP2040: usb: make all unhandled conditions a no-op --- .../TARGET_RP2040/USBPhy_RP2040.cpp | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp index c88bdcc573f..ff24a6dcd69 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp @@ -295,23 +295,17 @@ bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_ void USBPhyHw::endpoint_remove(usb_ep_t endpoint) { - // Halt here, unhandled - volatile int going = true; - while(going); + } void USBPhyHw::endpoint_stall(usb_ep_t endpoint) { - // Halt here, unhandled - volatile int going = true; - while(going); + } void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) { - // Halt here, unhandled - volatile int going = true; - while(going); + } bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) @@ -385,9 +379,7 @@ bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size) void USBPhyHw::endpoint_abort(usb_ep_t endpoint) { - // Unhandled, halt here - volatile int going = true; - while(going); + } void USBPhyHw::process() From c5589b18d389cecf27319d023a6474320d01bdd5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 8 Mar 2021 10:53:48 +0100 Subject: [PATCH 040/227] RP2040: i2c: fix addressing mismatch --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c index 210279b3b01..ae9f0c0fd38 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c @@ -48,7 +48,7 @@ void i2c_frequency(i2c_t *obj, int hz) int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int const bytes_read = i2c_read_blocking(obj->dev, - (uint8_t)address, + (uint8_t)(address >> 1), (uint8_t *)data, (size_t)length, /* nostop = */(stop == 0)); @@ -60,8 +60,17 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + if (length == 0) { + // From pico-sdk: + // static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, + // Synopsys hw accepts start/stop flags alongside data items in the same + // FIFO word, so no 0 byte transfers. + // invalid_params_if(I2C, len == 0); + length = 1; + } + int const bytes_written = i2c_write_blocking(obj->dev, - address, + address >> 1, (const uint8_t *)data, (size_t)length, /* nostop = */(stop == 0)); From 98dadc6fa9da498a229d78f9378933282e31e5b2 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 8 Mar 2021 11:17:31 +0100 Subject: [PATCH 041/227] RP2040: SPI: check SS correctness only if declared --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c index 1cc6bfa0fb8..73129835fab 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c @@ -28,8 +28,9 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(spi_mosi == spi_miso); MBED_ASSERT(spi_miso == spi_sclk); - MBED_ASSERT(spi_sclk == spi_ssel); - MBED_ASSERT(spi_ssel != (SPIName)NC); + if (spi_ssel != (SPIName)NC) { + MBED_ASSERT(spi_sclk == spi_ssel); + } /* Obtain pointer to the SPI module. */ obj->dev = (spi_inst_t *)pinmap_function(mosi, PinMap_SPI_MOSI); From 17d4018f9e5cf28d3fbf59330a0f3b5d62d73b4d Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 25 Feb 2021 12:44:31 +0100 Subject: [PATCH 042/227] RP2040: Add I2C slave --- .../TARGET_RP2040/i2c_api.c | 145 +++++++++++++++++- .../TARGET_RP2040/objects.h | 6 + .../hardware_i2c/include/hardware/i2c.h | 30 +++- targets/targets.json | 1 + 4 files changed, 177 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c index ae9f0c0fd38..9d7510bedfc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c @@ -6,6 +6,23 @@ #include "i2c_api.h" #include "pinmap.h" #include "PeripheralPins.h" +#include "objects.h" +#include "stdio.h" + +/****************************************************************************** + * DEFINE + ******************************************************************************/ + +#if 1 +#define DEBUG_PRINTF(...) printf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) /****************************************************************************** * CONST @@ -24,12 +41,23 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) I2CName const i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); MBED_ASSERT(i2c_sda == i2c_scl); +#if DEVICE_I2CSLAVE + /** was_slave is used to decide which driver call we need + * to use when uninitializing a given instance + */ + obj->was_slave = false; + obj->is_slave = false; + obj->slave_addr = 0; +#endif + /* Obtain the pointer to the I2C hardware instance. */ obj->dev = (i2c_inst_t *)pinmap_function(sda, PinMap_I2C_SDA); - obj->baudrate = DEFAULT_I2C_BAUDRATE; + //obj->baudrate = DEFAULT_I2C_BAUDRATE; + //Call this function because if we are configuring a slave, we don't have to set the frequency + //i2c_frequency(obj->dev, DEFAULT_I2C_BAUDRATE); /* Initialize the I2C module. */ - _i2c_init(obj->dev, obj->baudrate); + _i2c_init(obj->dev, DEFAULT_I2C_BAUDRATE); /* Configure GPIO for I2C as alternate function. */ gpio_set_function(sda, GPIO_FUNC_I2C); @@ -42,6 +70,14 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) void i2c_frequency(i2c_t *obj, int hz) { + DEBUG_PRINTF("obj->is_slave: %d\r\n", obj->is_slave); + +#if DEVICE_I2CSLAVE + /* Slaves automatically get frequency from master */ + if(obj->is_slave) { + return; + } +#endif obj->baudrate = i2c_set_baudrate(obj->dev, hz); } @@ -95,3 +131,108 @@ const PinMap *i2c_master_scl_pinmap() { return PinMap_I2C_SCL; } + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +int i2c_stop(i2c_t *obj) +{ + +} + +#if DEVICE_I2CSLAVE + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive + * @return non-zero if a value is available + */ +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + DEBUG_PRINTF("i2c_slave_mode: %p, %d\r\n", obj, enable_slave); + + obj->is_slave = enable_slave; +} + +/** Check to see if the I2C slave has been addressed. + * @param obj The I2C object + * @return The status - 1 - read addressed, 2 - write to all slaves, + * 3 write addressed, 0 - the slave has not been addressed + */ +int i2c_slave_receive(i2c_t *obj) +{ + int retValue = NoData; + + int rd_req = (obj->dev->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_RD_REQ_BITS) >> 5; + + if (rd_req == I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE) { + DEBUG_PRINTF("Read addressed\r\n"); + return ReadAddressed; + } + + int wr_req = (obj->dev->hw->status & I2C_IC_STATUS_RFNE_BITS) >> 3; + + if (wr_req == I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY) { + DEBUG_PRINTF("Write addressed\r\n"); + return WriteAddressed; + } + + return (retValue); +} + +/** Configure I2C as slave or master. + * @param obj The I2C objecti2c_get_read_availableread + * @return non-zero if a value is available + */ +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + size_t read_len = i2c_read_raw_blocking(obj->dev, (uint8_t *)data, length); + + DEBUG_PRINTF("i2c_slave read %d bytes\r\n", read_len); + + return read_len; +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param data The buffer for sending + * @param length Number of bytes to write + * @return non-zero if a value is available + */ +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + DEBUG_PRINTF("i2c_slave_write\r\n"); + + i2c_write_raw_blocking(obj->dev, (const uint8_t *)data, (size_t)length); + + //Clear interrupt + int clear_read_req = i2c_get_hw(obj->dev)->clr_rd_req; + DEBUG_PRINTF("clear_read_req: %d\n", clear_read_req); + + return length; +} + +/** Configure I2C address. + * @param obj The I2C object + * @param idx Currently not used + * @param address The address to be set + * @param mask Currently not used + */ +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + if (obj->is_slave) { + DEBUG_PRINTF("i2c_slave_address: %p, %d, %d, %d\r\n", obj, idx, address, mask); + + obj->slave_addr = (uint8_t)(address >> 1); + i2c_set_slave_mode(obj->dev, true, obj->slave_addr); + } +} + +#endif // DEVICE_I2CSLAVE diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index 5e5f2f0d6a4..cdbd5655e60 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -95,6 +95,12 @@ struct serial_s { struct i2c_s { i2c_inst_t * dev; unsigned int baudrate; + +#if DEVICE_I2CSLAVE + bool was_slave; + bool is_slave; + uint8_t slave_addr; +#endif }; struct spi_s { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index ead7bf1b1bb..2b5dca7798b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -10,6 +10,7 @@ #include "pico.h" #include "pico/time.h" #include "hardware/structs/i2c.h" +#include "stdio.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c #ifndef PARAM_ASSERTIONS_ENABLED_I2C @@ -289,12 +290,35 @@ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, s * Reads directly from the I2C RX FIFO which us mainly useful for * slave-mode operation. */ -static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { +static inline size_t i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { + + size_t bytes_read = 0; + for (size_t i = 0; i < len; ++i) { - while (!i2c_get_read_available(i2c)) + + while (!i2c_get_read_available(i2c)) { tight_loop_contents(); - *dst++ = i2c_get_hw(i2c)->data_cmd; + } + + *dst = i2c_get_hw(i2c)->data_cmd; + bytes_read++; + + //printf("dst %d ,", *dst); + + //Check stop condition + int stop = (i2c->hw->raw_intr_stat & 0x00000200) >> 9; + if (stop && !i2c_get_read_available(i2c)) { + //Clear stop + int clear_stop = i2c_get_hw(i2c)->clr_stop_det; + printf("clear_stop reg: %d\n", clear_stop); + break; + } else { + *dst++; + } + } + + return bytes_read; } #ifdef __cplusplus diff --git a/targets/targets.json b/targets/targets.json index 46935c06094..f0deb6c2f48 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9423,6 +9423,7 @@ "ANALOGIN", "FLASH", "I2C", + "I2CSLAVE", "INTERRUPTIN", "PORT_IN", "PORT_OUT", From 319315691c1ca8eb564f23d6744712a3efc10230 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Mar 2021 14:53:31 +0100 Subject: [PATCH 043/227] RP2040: PWM: fix asserts --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c index 5f5d8479959..cc2b935bc7b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c @@ -43,6 +43,7 @@ #include "pinmap.h" #include "hardware/pwm.h" #include "hardware/clocks.h" +#include "mbed_assert.h" const uint count_top = 1000; @@ -53,7 +54,7 @@ const uint count_top = 1000; */ void pwmout_init(pwmout_t *obj, PinName pin) { - MBED_ASSERT(obj); + MBED_ASSERT(obj != NULL); /* Populate PWM object with default values. */ obj->slice = pwm_gpio_to_slice_num(pin); @@ -75,7 +76,7 @@ void pwmout_init(pwmout_t *obj, PinName pin) */ void pwmout_free(pwmout_t *obj) { - MBED_ASSERT(obj); + MBED_ASSERT(obj != NULL); pwm_set_enabled(obj->slice, false); } From 9a7f2eed234cf8f3bf13d14ba9545ad15ee02644 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Mar 2021 15:22:43 +0100 Subject: [PATCH 044/227] RP2040: nano connect: fix pinmap --- .../TARGET_NANO_RP2040_CONNECT/PinNames.h | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h index e84e89440c5..bad8f487c68 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h @@ -44,18 +44,35 @@ typedef enum { ADC_TEMP = 0xF0, ADC_VREF = 0xF1, +#ifndef ARDUINO_ARCH_MBED + D0 = p1, + D1 = p0, + D2 = p25, + D3 = p15, + D4 = p16, + D5 = p17, + D6 = p18, + D7 = p19, + D8 = p20, + D9 = p21, + D10 = p5, + D11 = p7, + D12 = p4, + D13 = p6, + A0 = 26, A1 = 27, A2 = 28, A3 = 29, +#endif USBTX = p0, USBRX = p1, - LED1 = p25, - LED2 = p25, - LED3 = p25, - LED4 = p25, + LED1 = p6, + LED2 = p6, + LED3 = p6, + LED4 = p6, // Not connected NC = (int)0xFFFFFFFF From e5cff643110403433a38fd26bbeffd42dab29f4e Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Mar 2021 15:28:08 +0100 Subject: [PATCH 045/227] RP2040: add Raspberry Pico target --- .../TARGET_RASPBERRY_PI_PICO/PinNames.h | 70 +++++++++++++++++++ .../TARGET_RASPBERRY_PI_PICO/board.c | 3 + .../bs2_default_padded_checksummed.S | 23 ++++++ targets/targets.json | 11 +++ 4 files changed, 107 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/bs2_default_padded_checksummed.S diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h new file mode 100644 index 00000000000..6a47df933ae --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h @@ -0,0 +1,70 @@ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "PeripheralNames.h" +#include "boards/pico.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + +#ifndef ARDUINO_ARCH_MBED + A0 = 26, + A1 = 27, + A2 = 28, + A3 = 29, +#endif + + USBTX = p0, + USBRX = p1, + + LED1 = p25, + LED2 = p25, + LED3 = p25, + LED4 = p25, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c new file mode 100644 index 00000000000..1f775638f9b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c @@ -0,0 +1,3 @@ +#include "PinNames.h" + +uint32_t SystemCoreClock = 120000000; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/bs2_default_padded_checksummed.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/bs2_default_padded_checksummed.S new file mode 100644 index 00000000000..fc6bea7df62 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/bs2_default_padded_checksummed.S @@ -0,0 +1,23 @@ +// Padded and checksummed version of: /ssd/rp2040/pico-examples/build/pico-sdk/src/rp2_common/boot_stage2/bs2_default.bin + +.cpu cortex-m0plus +.thumb + +.section .boot2, "ax" + +.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60 +.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61 +.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20 +.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0 +.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0 +.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21 +.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60 +.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21 +.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60 +.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49 +.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20 +.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66 +.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40 +.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00 +.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0 +.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a diff --git a/targets/targets.json b/targets/targets.json index f0deb6c2f48..5e2aa5baaa5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9446,6 +9446,17 @@ "PICO_UART_ENABLE_CRLF_SUPPORT=0" ] }, + "RASPBERRY_PI_PICO": { + "inherits": ["RP2040"], + "macros_add": [ + "PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1", + "PICO_NO_BINARY_INFO=1", + "MBED_MPU_CUSTOM", + "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", + "PICO_ON_DEVICE=1", + "PICO_UART_ENABLE_CRLF_SUPPORT=0" + ] + }, "__build_tools_metadata__": { "version": "1", "public": false From 2ce7ca4982a6eb62979fbdd5312b8d6580a12534 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Mar 2021 15:48:37 +0100 Subject: [PATCH 046/227] RP2040: fix analogin_read_u16 to report full range --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c index 4e95f4551f4..e1773a065c5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c @@ -6,7 +6,7 @@ static float const ADC_VREF_VOLTAGE = 3.3f; /* 3.3V */ static uint16_t const ADC_RESOLUTION_BITS = 12; -static float const ADC_CONVERSION_FACTOR = ADC_VREF_VOLTAGE / (1 << ADC_RESOLUTION_BITS); +static float const ADC_CONVERSION_FACTOR = ADC_VREF_VOLTAGE / (1 << 16); void analogin_init(analogin_t *obj, PinName pin) { @@ -38,7 +38,7 @@ void analogin_init(analogin_t *obj, PinName pin) float analogin_read(analogin_t *obj) { /* Read the raw 12-Bit value from the ADC. */ - uint16_t const analog_in_raw = analogin_read_u16(obj); + float analog_in_raw = (float)analogin_read_u16(obj); /* Convert it to a voltage value. */ return (analog_in_raw * ADC_CONVERSION_FACTOR); } @@ -48,7 +48,7 @@ uint16_t analogin_read_u16(analogin_t *obj) /* Select the desired ADC input channel. */ adc_select_input(obj->channel); /* Read the 16-Bit ADC value. */ - return adc_read(); + return adc_read() << (16 - ADC_RESOLUTION_BITS); } const PinMap *analogin_pinmap() From 0a6144641cbbfb22552c616caf861bebe69316bd Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 16 Mar 2021 09:54:26 +0100 Subject: [PATCH 047/227] RP2040: fix PwmOut enable command --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c index cc2b935bc7b..e4bc4daa806 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c @@ -90,6 +90,7 @@ void pwmout_write(pwmout_t *obj, float percent) { obj->percent = percent; pwm_set_gpio_level(obj->pin, percent * (count_top + 1)); + pwm_set_enabled(obj->slice, true); } /** Read the current float-point output duty-cycle From 282b6b6e0b148d426c5c729b557fa397a66f9cdc Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 15 Mar 2021 16:33:00 +0100 Subject: [PATCH 048/227] RP2040: Implement watchdog --- .../TARGET_RP2040/watchdog_api.c | 46 +++++++++++++++++++ targets/targets.json | 1 + 2 files changed, 47 insertions(+) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c new file mode 100644 index 00000000000..007b79c3221 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c @@ -0,0 +1,46 @@ +#include "watchdog_api.h" +#include "hardware/watchdog.h" +#include "structs/watchdog.h" + +#if DEVICE_WATCHDOG + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + // The pico watchdogs accept a maximum value of 0x7fffff + if ( config->timeout_ms < 0x1 && config->timeout_ms > 0x7FFFFF ) { + return WATCHDOG_STATUS_INVALID_ARGUMENT; + } + + watchdog_enable(config->timeout_ms, true); + + return WATCHDOG_STATUS_OK; +} + +void hal_watchdog_kick(void) +{ + watchdog_update(); +} + +watchdog_status_t hal_watchdog_stop(void) +{ + hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return (watchdog_hw->load / 2000U); +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t features; + + features.max_timeout = 0x7FFFFF; + features.update_config = true; + features.disable_watchdog = true; + return features; + +} + +#endif // DEVICE_WATCHDOG diff --git a/targets/targets.json b/targets/targets.json index 5e2aa5baaa5..87b25d0c3b3 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9432,6 +9432,7 @@ "SERIAL_FC", "SPI", "USTICKER", + "WATCHDOG", "USBDEVICE" ] }, From 686ec9b801c93557d3c123a24f9373a5f5aa23f5 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 15 Mar 2021 17:52:09 +0100 Subject: [PATCH 049/227] RP2040: Implement reset reasons --- .../TARGET_RP2040/reset_reason.c | 33 +++++++++++++++++++ targets/targets.json | 3 +- 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c new file mode 100644 index 00000000000..7e511078c53 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c @@ -0,0 +1,33 @@ +#include "reset_reason_api.h" +#include "hardware/watchdog.h" + +#ifdef DEVICE_RESET_REASON + +#include "structs/resets.h" + +reset_reason_t hal_reset_reason_get(void) +{ + if (watchdog_caused_reboot()) { + return RESET_REASON_WATCHDOG; + } else { + return RESET_REASON_PIN_RESET; + } + + return RESET_REASON_UNKNOWN; +} + + +uint32_t hal_reset_reason_get_raw(void) +{ + return resets_hw->reset; +} + + +void hal_reset_reason_clear(void) +{ + for (int i = 1; i < 25; i++) { + hw_clear_bits(&resets_hw->reset, i); + } +} + +#endif // DEVICE_RESET_REASON diff --git a/targets/targets.json b/targets/targets.json index 87b25d0c3b3..6d8e9131191 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9433,7 +9433,8 @@ "SPI", "USTICKER", "WATCHDOG", - "USBDEVICE" + "USBDEVICE", + "RESET_REASON" ] }, "NANO_RP2040_CONNECT": { From 5a4393de5260ec4f15733be88a51352827879a89 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 16 Mar 2021 11:07:10 +0100 Subject: [PATCH 050/227] RP2040: fix spi.h spurious inclusion in case insensitive filesystems --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore | 5 ++++- .../rp2040/hardware_structs/include/hardware/placeholder.h | 0 .../pico-sdk/rp2_common/hardware_spi/include/placeholder.h | 0 3 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore index f0ee61c1603..c7a477981a5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -18,4 +18,7 @@ pico-sdk/rp2_common/pico_standard_link/new_delete.cpp pico-sdk/rp2_common/pico_standard_link/*.ld pico-sdk/rp2_common/pico_unique_id/* pico-sdk/rp2_common/hardware_divider/* -pico-sdk/host/* \ No newline at end of file +pico-sdk/rp2_common/hardware_spi/include/hardware/* +pico-sdk/rp2040/hardware_structs/include/hardware/structs/* +pico-sdk/rp2040/hardware_regs/include/hardware/regs/* +pico-sdk/host/* diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d From 2c3482e2d00146be3b50fb2506ed7d029c8f298f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 24 Mar 2021 11:55:51 +0100 Subject: [PATCH 051/227] RP2040: UART: baud can't be changed at runtime --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c index 6a90e64323f..8d95f6c2a32 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c @@ -76,7 +76,8 @@ void serial_free(serial_t *obj) void serial_baud(serial_t *obj, int baudrate) { obj->baud = (uint32_t)baudrate; - uart_set_baudrate(obj->dev, obj->baud); + uart_init(obj->dev, obj->baud); + uart_set_fifo_enabled(obj->dev, false); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) From d9106f6a5fed570b26031403a45873656cf5baaf Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 16 Mar 2021 17:19:42 +0100 Subject: [PATCH 052/227] RP2040: i2c: remove debug prints --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c index 9d7510bedfc..2b776562a18 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c @@ -13,7 +13,7 @@ * DEFINE ******************************************************************************/ -#if 1 +#if 0 #define DEBUG_PRINTF(...) printf(__VA_ARGS__) #else #define DEBUG_PRINTF(...) From c78dddb07e58825fc75b4d7c94acaa20199a2feb Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 13 Apr 2021 10:03:51 +0200 Subject: [PATCH 053/227] RP2040 PICO: Add CONSOLE_*X defines --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h | 6 +++--- .../TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h index 67353ffe81d..6f140e03437 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/PeripheralNames.h @@ -70,8 +70,8 @@ typedef enum { PullDefault = PullNone } PinMode; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX +#define STDIO_UART_TX CONSOLE_TX +#define STDIO_UART_RX CONSOLE_RX #define STDIO_UART uart0 // Default peripherals @@ -81,7 +81,7 @@ typedef enum { #define MBED_UART0 p9, p10 #define MBED_UART1 p13, p14 #define MBED_UART2 p28, p27 -#define MBED_UARTUSB USBTX, USBRX +#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX #define MBED_I2C0 p28, p27 #define MBED_I2C1 p9, p10 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h index bad8f487c68..784cfff18fc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/PinNames.h @@ -66,8 +66,8 @@ typedef enum { A3 = 29, #endif - USBTX = p0, - USBRX = p1, + CONSOLE_TX = p0, + CONSOLE_RX = p1, LED1 = p6, LED2 = p6, From 93b4cfb7d73dd467be1a6688e400135a0b007421 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 13 Apr 2021 12:20:06 +0200 Subject: [PATCH 054/227] RP2040: FLASH: fix multipage write --- .../TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c index fb1a28dd7f5..2ebfc40a048 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/flash_api.c @@ -71,18 +71,14 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return -1; } - uint8_t buf[FLASH_PAGE_SIZE]; - - for (int j = 0; j < size/FLASH_PAGE_SIZE; j++) { - for (int i = 0; i < FLASH_PAGE_SIZE; i++) { - buf[i] = data[j*FLASH_PAGE_SIZE + i]; - } - address = address + j*FLASH_PAGE_SIZE; - core_util_critical_section_enter(); - flash_range_program(address, buf, FLASH_PAGE_SIZE); - core_util_critical_section_exit(); + size_t pages = size/FLASH_PAGE_SIZE; + if (size%FLASH_PAGE_SIZE != 0) { + pages += 1; } + core_util_critical_section_enter(); + flash_range_program(address, data, FLASH_PAGE_SIZE * pages); + core_util_critical_section_exit(); return 0; From 43afccc8589f445c1e5a4f2670cbba83278f569f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 14:32:14 +0200 Subject: [PATCH 055/227] RP2040: fix include paths --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c | 2 +- targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c | 2 +- targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c index e1773a065c5..a5cf6995f98 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/analogin_api.c @@ -1,6 +1,6 @@ #include "mbed_assert.h" #include "analogin_api.h" -#include "adc.h" +#include "hardware/adc.h" #include "pinmap.h" #include "PeripheralPins.h" diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c index 7e511078c53..83de2cfb9d7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/reset_reason.c @@ -3,7 +3,7 @@ #ifdef DEVICE_RESET_REASON -#include "structs/resets.h" +#include "hardware/structs/resets.h" reset_reason_t hal_reset_reason_get(void) { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c index 007b79c3221..b7abac8917d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c @@ -1,6 +1,6 @@ #include "watchdog_api.h" #include "hardware/watchdog.h" -#include "structs/watchdog.h" +#include "hardware/structs/watchdog.h" #if DEVICE_WATCHDOG From 2a860e6ae025bcc0de0c7d49ed3243daf6f33626 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 14:32:33 +0200 Subject: [PATCH 056/227] RP2040: silence nasty warning --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index cdbd5655e60..280f166d4d2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -20,6 +20,7 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wtype-limits" #pragma GCC diagnostic ignored "-Wignored-qualifiers" +#pragma GCC diagnostic ignored "-Wunused-value" #ifdef __cplusplus #include From 67dc218f97622882e42708daa9c2bc99613e14ce Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 14:33:02 +0200 Subject: [PATCH 057/227] RP2040: start fixing CMake files for mbed cli 2 --- targets/TARGET_RASPBERRYPI/CMakeLists.txt | 17 ++-- .../TARGET_RP2040/CMakeLists.txt | 85 +++++++++++++++++-- .../TARGET_NANO_RP2040_CONNECT/CMakeLists.txt | 21 +++++ .../TARGET_RASPBERRY_PI_PICO/CMakeLists.txt | 21 +++++ 4 files changed, 130 insertions(+), 14 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt diff --git a/targets/TARGET_RASPBERRYPI/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/CMakeLists.txt index 3ba15e7d898..e526ad51153 100644 --- a/targets/TARGET_RASPBERRYPI/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/CMakeLists.txt @@ -1,11 +1,18 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if("RPI2010" IN_LIST MBED_TARGET_LABELS) - add_subdirectory(TARGET_RPI2040) -endif() +add_subdirectory(TARGET_RP2040 EXCLUDE_FROM_ALL) -target_include_directories(mbed-core +add_library(mbed-raspberrypi INTERFACE) + +target_include_directories(mbed-raspberrypi INTERFACE . ) + +target_sources(mbed-raspberrypi + INTERFACE + . +) + +target_link_libraries(mbed-raspberrypi INTERFACE mbed-cmsis-cortex-m) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt index 9dc92970487..4fadf6091ee 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/CMakeLists.txt @@ -1,12 +1,79 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if("NANO_RP2040_CONNECT" IN_LIST MBED_TARGET_LABELS) - target_include_directories(mbed-core - INTERFACE - TARGET_NANO_RP2040_CONNECT - ) -endif() - -add_subdirectory(rp2_common) -add_subdirectory(rp2040) \ No newline at end of file +add_subdirectory(TARGET_NANO_RP2040_CONNECT EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_RASPBERRY_PI_PICO EXCLUDE_FROM_ALL) + +add_library(mbed-rp2040 INTERFACE) + +target_include_directories(mbed-rp2040 + INTERFACE + pico-sdk/rp2_common/hardware_adc/include + pico-sdk/rp2_common/hardware_gpio/include + pico-sdk/rp2_common/hardware_resets/include + pico-sdk/rp2_common/hardware_pwm/include + pico-sdk/rp2_common/hardware_base/include + pico-sdk/rp2_common/hardware_uart/include + pico-sdk/rp2_common/hardware_spi/include + pico-sdk/rp2_common/hardware_i2c/include + pico-sdk/rp2_common/hardware_irq/include + pico-sdk/rp2_common/hardware_flash/include + pico-sdk/rp2_common/hardware_clocks/include + pico-sdk/rp2_common/hardware_rtc/include + pico-sdk/rp2_common/hardware_watchdog/include + pico-sdk/rp2_common/hardware_timer/include + pico-sdk/rp2_common/hardware_pll/include + pico-sdk/rp2_common/hardware_sync/include + pico-sdk/rp2_common/hardware_xosc/include + pico-sdk/rp2_common/pico_platform/include + pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix + pico-sdk/rp2_common/pico_bootrom/include + pico-sdk/rp2_common/hardware_claim/include + pico-sdk/rp2040/hardware_structs/include + pico-sdk/rp2040/hardware_regs/include + pico-sdk/common/pico_sync/include + pico-sdk/common/pico_time/include + pico-sdk/common/pico_base/include + pico-sdk/common/pico_binary_info/include + pico-sdk/common/pico_util/include + pico-sdk/boards/include + pico-sdk/generated + . +) + +target_sources(mbed-rp2040 + INTERFACE + analogin_api.c + flash_api.c + gpio_api.c + i2c_api.c + lp_ticker.c + mbed_overrides.c + PeripheralPins.c + pwmout_api.c + reset_reason.c + serial_api.c + spi_api.c + us_ticker.c + USBPhy_RP2040.cpp + watchdog_api.c + pico-sdk/rp2_common/pico_standard_link/crt0.S + pico-sdk/rp2_common/hardware_flash/flash.c + pico-sdk/rp2_common/hardware_uart/uart.c + pico-sdk/rp2_common/hardware_spi/spi.c + pico-sdk/rp2_common/hardware_gpio/gpio.c + pico-sdk/rp2_common/hardware_xosc/xosc.c + pico-sdk/rp2_common/hardware_irq/irq.c + pico-sdk/rp2_common/hardware_pll/pll.c + pico-sdk/rp2_common/hardware_watchdog/watchdog.c + pico-sdk/rp2_common/hardware_clocks/clocks.c + pico-sdk/rp2_common/hardware_sync/sync.c + pico-sdk/rp2_common/pico_bootrom/bootrom.c + pico-sdk/rp2_common/pico_runtime/runtime.c + pico-sdk/rp2_common/pico_platform/platform.c + pico-sdk/common/pico_sync/mutex.c + pico-sdk/common/pico_time/time.c + pico-sdk/common/pico_sync/lock_core.c +) + +target_link_libraries(mbed-rp2040 INTERFACE mbed-raspberrypi) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/CMakeLists.txt new file mode 100644 index 00000000000..0917dfe1229 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(LINKER_FILE ../TOOLCHAIN_GCC_ARM/memmap_default.ld) + +add_library(mbed-nano-rp2040-connect INTERFACE) + +target_sources(mbed-nano-rp2040-connect + INTERFACE + board.c + bs2_default_padded_checksummed.S +) + +target_include_directories(mbed-nano-rp2040-connect + INTERFACE + . +) + +mbed_set_linker_script(mbed-nano-rp2040-connect ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-nano-rp2040-connect INTERFACE mbed-rp2040) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt new file mode 100644 index 00000000000..5df188f6818 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(LINKER_FILE ../TOOLCHAIN_GCC_ARM/memmap_default.ld) + +add_library(mbed-raspberrypi-pico INTERFACE) + +target_sources(mbed-raspberrypi-pico + INTERFACE + board.c + bs2_default_padded_checksummed.S +) + +target_include_directories(mbed-raspberrypi-pico + INTERFACE + . +) + +mbed_set_linker_script(mbed-raspberrypi-pico ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-raspberrypi-pico INTERFACE mbed-rp2040) From 471acc1cdc10f44ab348a09319ffee7d41a95a8d Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 3 May 2021 15:12:12 +0200 Subject: [PATCH 058/227] RP2040: fix and update Raspberry Pi Pico target --- .../TARGET_RASPBERRY_PI_PICO/CMakeLists.txt | 10 +++++----- .../TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt index 5df188f6818..fc48f58efad 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/CMakeLists.txt @@ -3,19 +3,19 @@ set(LINKER_FILE ../TOOLCHAIN_GCC_ARM/memmap_default.ld) -add_library(mbed-raspberrypi-pico INTERFACE) +add_library(mbed-raspberry-pi-pico INTERFACE) -target_sources(mbed-raspberrypi-pico +target_sources(mbed-raspberry-pi-pico INTERFACE board.c bs2_default_padded_checksummed.S ) -target_include_directories(mbed-raspberrypi-pico +target_include_directories(mbed-raspberry-pi-pico INTERFACE . ) -mbed_set_linker_script(mbed-raspberrypi-pico ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-raspberry-pi-pico ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-raspberrypi-pico INTERFACE mbed-rp2040) +target_link_libraries(mbed-raspberry-pi-pico INTERFACE mbed-rp2040) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h index 6a47df933ae..2b2e9463ef5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/PinNames.h @@ -51,8 +51,8 @@ typedef enum { A3 = 29, #endif - USBTX = p0, - USBRX = p1, + CONSOLE_TX = p0, + CONSOLE_RX = p1, LED1 = p25, LED2 = p25, From 7635a9f2d322df3a5f1ec2b8b09834de9e02032a Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 7 May 2021 16:08:53 +0200 Subject: [PATCH 059/227] RP2040: USBPhy: implement stall() and unstall() --- .../TARGET_RP2040/USBPhy_RP2040.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp index ff24a6dcd69..eb387af3c37 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp @@ -110,7 +110,11 @@ void USBPhyHw::connect() // and when a setup packet is received usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | - USB_INTS_SETUP_REQ_BITS; + USB_INTS_SETUP_REQ_BITS | + USB_INTS_HOST_CONN_DIS_BITS | + USB_INTS_HOST_RESUME_BITS | + USB_INTS_ERROR_RX_OVERFLOW_BITS | + USB_INTS_STALL_BITS; // Present full speed device by enabling pull up on DP usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; @@ -300,12 +304,14 @@ void USBPhyHw::endpoint_remove(usb_ep_t endpoint) void USBPhyHw::endpoint_stall(usb_ep_t endpoint) { - + int ep_num = endpoint & 0x7f; + usb_dpram->ep_buf_ctrl[ep_num].out |= USB_BUF_CTRL_STALL; } void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) { - + int ep_num = endpoint & 0x7f; + usb_dpram->ep_buf_ctrl[ep_num].out &= ~USB_BUF_CTRL_STALL; } bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) From b2d24587212d35a08c99c8712b00f7531c7c6cf4 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 11 May 2021 09:41:45 +0200 Subject: [PATCH 060/227] RP2040: include multicore library in build --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore | 1 - .../pico-sdk/rp2_common/pico_multicore/multicore.c | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore index c7a477981a5..0581f97d6eb 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -5,7 +5,6 @@ pico-sdk/rp2_common/pico_printf* pico-sdk/boards/include/boards/* pico-sdk/common/pico_base/include/pico/* pico-sdk/rp2_common/boot_stage2/* -pico-sdk/rp2_common/pico_multicore/* pico-sdk/rp2_common/pico_malloc/* pico-sdk/rp2_common/pico_stdlib/ pico-sdk/rp2_common/pico_mem_ops/* diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c index 0ceea4def89..6b2321f12fc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c @@ -4,12 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "pico/stdlib.h" -#include "pico/multicore.h" +#include "hardware/structs/sio.h" +#include "pico/time.h" #include "hardware/sync.h" +#include "pico/multicore.h" #include "hardware/irq.h" #include "hardware/structs/scb.h" -#include "hardware/structs/sio.h" #include "hardware/regs/psm.h" #include "hardware/claim.h" #if PICO_USE_STACK_GUARDS @@ -259,4 +259,4 @@ bool multicore_lockout_end_timeout_us(uint64_t timeout_us) { void multicore_lockout_end_blocking() { multicore_lockout_end_block_until(at_the_end_of_time); -} \ No newline at end of file +} From 5bba62de2e938fb73c2023a95c21ce345fc068db Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 12 May 2021 16:00:01 +0200 Subject: [PATCH 061/227] RP2040: USB: retry handling irqs if some went missing --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp index eb387af3c37..64ae5d3a4ce 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/USBPhy_RP2040.cpp @@ -390,6 +390,9 @@ void USBPhyHw::endpoint_abort(usb_ep_t endpoint) void USBPhyHw::process() { + +again: + // reset interrupt if (usb_hw->ints & USB_INTS_BUS_RESET_BITS) { // Clear the device address @@ -502,7 +505,8 @@ void USBPhyHw::process() { volatile int ints = usb_hw->ints; volatile int going = 1; - while(ints && going); + goto again; + //while(ints && going); } From 41225cddb2c3716ee6ed56998bef08d352132927 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 24 May 2021 16:13:09 +0200 Subject: [PATCH 062/227] Nano RP2040 Connect: force flash size to 16MB --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index 6d8e9131191..0e82d5cff2d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9444,6 +9444,7 @@ "PICO_NO_BINARY_INFO=1", "MBED_MPU_CUSTOM", "PICO_TIME_DEFAULT_ALARM_POOL_DISABLED", + "PICO_FLASH_SIZE_BYTES=16*1024*1024", "PICO_ON_DEVICE=1", "PICO_UART_ENABLE_CRLF_SUPPORT=0" ] From b833489f333cdc7aaa7c25063b800825163da351 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 4 Jun 2021 14:45:38 +0200 Subject: [PATCH 063/227] Save watchdog timeout in a static variable accessible from Arduino APIs --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c index b7abac8917d..9263eb48d5c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c @@ -4,8 +4,11 @@ #if DEVICE_WATCHDOG +static watchdog_config_t watchdogConfig; + watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) { + watchdogConfig = *config; // The pico watchdogs accept a maximum value of 0x7fffff if ( config->timeout_ms < 0x1 && config->timeout_ms > 0x7FFFFF ) { return WATCHDOG_STATUS_INVALID_ARGUMENT; @@ -29,7 +32,11 @@ watchdog_status_t hal_watchdog_stop(void) uint32_t hal_watchdog_get_reload_value(void) { - return (watchdog_hw->load / 2000U); + uint32_t load_value = watchdogConfig.timeout_ms * 1000 * 2; + if (load_value > 0xffffffu) { + load_value = 0xffffffu; + } + return load_value; } watchdog_features_t hal_watchdog_get_platform_features(void) From 5e5d5894449dadfadfb1219d792d86bd0e4b16c2 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 30 Jun 2021 11:50:21 +0200 Subject: [PATCH 064/227] RP2040: us_ticker: fix missing interrupts after 32bit wrap --- .../TARGET_RP2040/us_ticker.c | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c index 00edf82830e..b3b8497188c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/us_ticker.c @@ -53,11 +53,18 @@ const ticker_info_t* us_ticker_get_info() return &info; } -const uint8_t alarm_num = 0; +static const uint8_t alarm_num = 0; + +static void us_ticker_irq_handler_internal(uint alarm_src) { + if (alarm_num == alarm_src) { + us_ticker_irq_handler(); + } +} void us_ticker_init(void) { - hardware_alarm_set_callback(alarm_num, us_ticker_irq_handler); + hardware_alarm_claim(alarm_num); + hardware_alarm_set_callback(alarm_num, us_ticker_irq_handler_internal); } uint32_t us_ticker_read() @@ -68,8 +75,25 @@ uint32_t us_ticker_read() void us_ticker_set_interrupt(timestamp_t timestamp) { core_util_critical_section_enter(); - absolute_time_t target = {timestamp}; + + uint64_t _timestamp = (uint64_t)timestamp; + + if (timestamp < time_us_32()) { + //32 bit timestamp has been wrapped + //We need to provide a 64 bit timestamp able to fire the irq for this round + _timestamp = (((time_us_64() >> 32) + 1) << 32) + timestamp; + } else { + //Then, at the next round, wrap the 64 bit timer to follow the 32 bit one + if ((time_us_64() >> 32) > 0) { + uint64_t current_time = time_us_64(); + uint64_t wrapped_time = current_time - 0xFFFFFFFF; + timer_hw->timelw = (uint32_t)wrapped_time; + timer_hw->timehw = 0; + } + } + absolute_time_t target = { _timestamp }; hardware_alarm_set_target(alarm_num, target); + core_util_critical_section_exit(); } @@ -90,4 +114,5 @@ void us_ticker_clear_interrupt(void) void us_ticker_free(void) { + hardware_alarm_unclaim(alarm_num); } From e017e1bd82a51bc8eadd099fe1d3fc56f73ebd58 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 18 Jun 2021 17:58:21 +0200 Subject: [PATCH 065/227] Nano RP2040 connect: use standard W25Q080 2nd stage Latest boards ship with a different flash chip; QE bit is set during production and should never be set to 0. Since the adesto specific code is not working on the new flash, let's fallback to the standard 2nd stage without PROGRAM_STATUS_REG define --- .../bs2_default_padded_checksummed.S | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S index e9be188191a..fc6bea7df62 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/bs2_default_padded_checksummed.S @@ -5,19 +5,19 @@ .section .boot2, "ax" -.byte 0x00, 0xb5, 0x31, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60 -.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2d, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61 -.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2a, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20 -.byte 0x00, 0xf0, 0x42, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x12, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0 -.byte 0x32, 0xf8, 0x19, 0x6e, 0x31, 0x21, 0x19, 0x66, 0x1a, 0x66, 0x00, 0xf0, 0x2c, 0xf8, 0x19, 0x6e -.byte 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21, 0x08, 0x42, 0xf9, 0xd1 -.byte 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60, 0x1a, 0x49, 0x1b, 0x48 -.byte 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0x20, 0x21, 0x19, 0x66, 0x00, 0xf0 -.byte 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60 -.byte 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49, 0x08, 0x60, 0x03, 0xc8 -.byte 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20, 0x01, 0x42, 0xfb, 0xd0 -.byte 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66, 0x18, 0x66, 0xff, 0xf7 -.byte 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x00, 0x18 -.byte 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x18 -.byte 0x22, 0x20, 0x00, 0x20, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00 -.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb3, 0x64, 0x01, 0x1a +.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60 +.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61 +.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20 +.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0 +.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0 +.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21 +.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60 +.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21 +.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60 +.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49 +.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20 +.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66 +.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40 +.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00 +.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0 +.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a From a95d308b7edf7a217ffd372bb20836eecc1296c6 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 2 Aug 2021 10:23:43 +0200 Subject: [PATCH 066/227] RP2040: optimize flash/ram occupation Since we are not using ROM functions here, just keep everything as default as possible --- .../TOOLCHAIN_GCC_ARM/memmap_default.ld | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld index d92bd42107f..ec8bac7e404 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TOOLCHAIN_GCC_ARM/memmap_default.ld @@ -27,9 +27,15 @@ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif +#if !defined(PICO_FLASH_SIZE_BYTES) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define PICO_FLASH_SIZE_BYTES 2048k +#endif + MEMORY { - FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + FLASH(rx) : ORIGIN = 0x10000000, LENGTH = PICO_FLASH_SIZE_BYTES RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k @@ -70,11 +76,7 @@ SECTIONS KEEP (*(.binary_info_header)) __binary_info_header_end = .; KEEP (*(.reset)) - /* TODO revisit this now memset/memcpy/float in ROM */ - /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from - * FLASH ... we will include any thing excluded here in .data below by default */ KEEP (*(.init)) - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) *(.fini) /* Pull all c'tors into .text */ *crtbegin.o(.ctors) @@ -94,7 +96,6 @@ SECTIONS } > FLASH .rodata : { - *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) . = ALIGN(4); *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) . = ALIGN(4); @@ -136,10 +137,6 @@ SECTIONS *(.time_critical*) - /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ - *(.text*) - . = ALIGN(4); - *(.rodata*) . = ALIGN(4); *(.data*) From 3b391f7d3548bd7d5f9f5b8d441d1ae8fcecb726 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 2 Aug 2021 10:34:57 +0200 Subject: [PATCH 067/227] RP2040: Add weak aliases for ISR handlers Fixes baremetal build --- .../pico-sdk/rp2_common/pico_standard_link/crt0.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S index 3f90b95ee21..97af458711d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -89,10 +89,10 @@ __vectors: // these are separated out for clarity decl_isr_bkpt isr_invalid decl_isr_bkpt isr_nmi -decl_isr_bkpt isr_hardfault -decl_isr_bkpt isr_svcall -decl_isr_bkpt isr_pendsv -decl_isr_bkpt isr_systick +decl_isr_bkpt HardFault_Handler +decl_isr_bkpt SVC_Handler +decl_isr_bkpt PendSV_Handler +decl_isr_bkpt SysTick_Handler .macro decl_isr name .weak \name From 995ff986c770d3348302ad4bb9201295a8c5dd21 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 10 Aug 2021 12:09:30 +0200 Subject: [PATCH 068/227] RP2040: enable led indication on mbed_die() --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h index 280f166d4d2..f5f44a58f4a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/objects.h @@ -129,4 +129,6 @@ typedef struct serial_s serial_t; } #endif +#define LED1 LED1 + #endif From 56ed462e86662344257d0127ad9fb60922e3b24e Mon Sep 17 00:00:00 2001 From: Josep Comas Date: Sat, 31 Jul 2021 18:57:41 +0200 Subject: [PATCH 069/227] check MISO correctness only if it is declared It is very common to have displays without MISO pin connected to MCU, for example, https://www.waveshare.com/pico-lcd-1.3.htm hangs calling spi_init(&spi, p11, NC, p10, NC); --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c index 73129835fab..271cf58d1c1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/spi_api.c @@ -26,8 +26,10 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - MBED_ASSERT(spi_mosi == spi_miso); - MBED_ASSERT(spi_miso == spi_sclk); + if (spi_miso != (SPIName)NC) { + MBED_ASSERT(spi_mosi == spi_miso); + MBED_ASSERT(spi_miso == spi_sclk); + } if (spi_ssel != (SPIName)NC) { MBED_ASSERT(spi_sclk == spi_ssel); } From cd48fa6a9e18f30d582647e960dd285a1e193ae9 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 7 Oct 2021 18:11:59 +0200 Subject: [PATCH 070/227] rp2040: Fix I2CSlave synchronization issue by adding a timeout for the read --- .../TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c index 2b776562a18..ec52728f637 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/i2c_api.c @@ -24,6 +24,8 @@ #define WriteGeneral 2 // the master is writing to all slave #define WriteAddressed 3 // the master is writing to this slave (slave = receiver) +#define BYTE_TIMEOUT_US ((SystemCoreClock / obj->baudrate) * 3 * 10) + /****************************************************************************** * CONST ******************************************************************************/ @@ -193,7 +195,18 @@ int i2c_slave_receive(i2c_t *obj) */ int i2c_slave_read(i2c_t *obj, char *data, int length) { - size_t read_len = i2c_read_raw_blocking(obj->dev, (uint8_t *)data, length); + int read_len = 0; + + int timeout = 120 * (length + 1); + while (!i2c_get_read_available(obj->dev)) { + tight_loop_contents(); + } + while (--timeout != 0) { + if (i2c_get_read_available(obj->dev)) { + data[read_len++] = i2c_get_hw(obj->dev)->data_cmd; + } + wait_us(1); + } DEBUG_PRINTF("i2c_slave read %d bytes\r\n", read_len); From 1ed0653b3bb0acdc5c0d1ecefb19951e9755cb61 Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Mon, 28 Jun 2021 15:03:50 +0200 Subject: [PATCH 071/227] STM32: PWM: add export HRTIM capable pins to PeripheralPins --- .../tools/STM32_gen_PeripheralPins.py | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py index 63f0e875998..44a95f9c023 100644 --- a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py +++ b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py @@ -42,6 +42,7 @@ i2cscl_list = [] #'PIN','name','I2CSCLSignal' i2csda_list = [] #'PIN','name','I2CSDASignal' pwm_list = [] #'PIN','name','PWM' +hrtim_list = [] #'PIN','name','HRTIM' uarttx_list = [] #'PIN','name','UARTtx' uartrx_list = [] #'PIN','name','UARTrx' uartcts_list = [] #'PIN','name','UARTcts' @@ -278,6 +279,10 @@ def store_pwm(pin, name, signal): if "_CH" in signal: pwm_list.append([pin, name, signal]) +# function to store hrtim timers +def store_hrtim(pin, name, signal): + if "_CH" in signal: + hrtim_list.append([pin, name, signal]) # function to store Uart pins def store_uart(pin, name, signal): @@ -567,6 +572,8 @@ def print_all_lists(): print_i2c(i2cscl_list) if print_list_header("PWM", "PWM", pwm_list, "PWMOUT"): print_pwm() + if print_list_header("PWM_HRTIM", "PWM_HRTIM", hrtim_list, "PWMOUT"): + print_hrtim() if print_list_header("SERIAL", "UART_TX", uarttx_list, "SERIAL"): print_uart(uarttx_list) if print_list_header("", "UART_RX", uartrx_list, "SERIAL"): @@ -894,6 +901,71 @@ def print_pwm(): if ADD_DEVICE_IF: out_c_file.write( "#endif\n" ) +def print_hrtim(): + prev_p = '' + alt_index = 0 + + tim_dualcore = "NOT_KNOWN" + for EachTarget in TIM_DUALCORE_LIST: + if EachTarget in mcu_file: + tim_dualcore = TIM_DUALCORE_LIST[EachTarget] + + for parsed_pin in hrtim_list: + result = get_gpio_af_num(parsed_pin[1], parsed_pin[2]) + commented_line = " " + if parsed_pin[1] in PinLabel: + if "STDIO_UART" in PinLabel[parsed_pin[1]]: + commented_line = "//" + if "RCC_OSC" in PinLabel[parsed_pin[1]]: + commented_line = "//" + if "%s_" % TIM_MST in parsed_pin[2]: + commented_line = "//" + if "%s_" % tim_dualcore in parsed_pin[2]: + commented_line = "//" + if commented_line != "//": + if parsed_pin[0] == prev_p: + prev_p = parsed_pin[0] + parsed_pin[0] += '_ALT%d' % alt_index + store_pin(parsed_pin[0], parsed_pin[0], "") + alt_index += 1 + else: + prev_p = parsed_pin[0] + alt_index = 0 + s1 = "%-17s" % (commented_line + " {" + parsed_pin[0] + ',') + # parsed_pin[2] : TIM2_CH1 / TIM15_CH1N + a = parsed_pin[2].split('_') + inst = a[0].replace("HRTIM", "PWM_I") + # if len(inst) == 3: + # inst += '1' + s1 += "%-8s" % (inst + ',') + N = len(a[1]) + + timer = a[1][0: N -1] + chan = a[1][N - 1: N] + + if chan.endswith('1'): + chan = ', 0' + else: + chan = ', 1' + s1 += 'STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, ' + r = result.split(' ') + prev_s1 = "" + for af in r: + if s1 == prev_s1: + continue + else: + prev_s1 = s1 + s2 = s1 + af + ', ' + timer + chan + ')}, // ' + parsed_pin[2] + if parsed_pin[1] in PinLabel: + s2 += ' // Connected to ' + PinLabel[parsed_pin[1]] + s2 += '\n' + out_c_file.write(s2) + out_c_file.write( """ {NC, NC, 0} +}; +""") + if ADD_DEVICE_IF: + out_c_file.write( "#endif\n" ) + def print_uart(l): global ALTERNATE_DEFINITION @@ -1314,6 +1386,8 @@ def sort_my_lists(): i2csda_list.sort(key=natural_sortkey) pwm_list.sort(key=natural_sortkey2) # first sort on name column pwm_list.sort(key=natural_sortkey) + hrtim_list.sort(key=natural_sortkey2) # first sort on name column + hrtim_list.sort(key=natural_sortkey) uarttx_list.sort(key=natural_sortkey_uart) # first sort on name column uartrx_list.sort(key=natural_sortkey_uart) # first sort on name column uartcts_list.sort(key=natural_sortkey_uart) # first sort on name column @@ -1356,6 +1430,7 @@ def clean_all_lists(): del i2cscl_list[:] del i2csda_list[:] del pwm_list[:] + del hrtim_list[:] del uarttx_list[:] del uartrx_list[:] del uartcts_list[:] @@ -1428,6 +1503,8 @@ def parse_pins(): store_i2c(pin, name, sig) if re.match("^TIM", sig) is not None: # ignore HRTIM store_pwm(pin, name, sig) + if re.match("^HRTIM", sig) is not None: # ignore HRTIM + store_hrtim(pin, name, sig) if re.match("^(LPU|US|U)ART", sig) is not None: store_uart(pin, name, sig) if "SPI" in sig: From 9bc7f62edc4ab2d494fa9e1cce346f20a854d56d Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Mon, 28 Jun 2021 15:05:40 +0200 Subject: [PATCH 072/227] STM32H7: add HRTIM capable pins --- targets/TARGET_STM/PeripheralPins.h | 8 ++++++++ .../TARGET_PORTENTA_H7/PeripheralPins.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/targets/TARGET_STM/PeripheralPins.h b/targets/TARGET_STM/PeripheralPins.h index d74f6094b6d..9ca283c8fb9 100644 --- a/targets/TARGET_STM/PeripheralPins.h +++ b/targets/TARGET_STM/PeripheralPins.h @@ -86,6 +86,7 @@ extern const PinMap PinMap_I2C_SCL[]; //*** PWM *** #if DEVICE_PWMOUT extern const PinMap PinMap_PWM[]; +extern const PinMap PinMap_PWM_HRTIM[]; #endif //*** SERIAL *** @@ -143,6 +144,13 @@ extern const PinMap PinMap_OSPI_SSEL[]; #define USE_USB_OTG_HS 2 #define USE_USB_HS_IN_FS 3 +// HRTIM channels +#define CHA 0 +#define CHB 1 +#define CHC 2 +#define CHD 3 +#define CHE 4 + #if DEVICE_USBDEVICE extern const PinMap PinMap_USB_HS[]; extern const PinMap PinMap_USB_FS[]; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c index 26cd9440666..9e7339bcdb5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c @@ -259,6 +259,22 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {NC, NC, 0} }; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + //*** SERIAL *** From e32405e7ec786ad701d61d2acd6da7430a19d725 Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Mon, 28 Jun 2021 15:25:11 +0200 Subject: [PATCH 073/227] STM32: PWM: implement HRTIM based PWM APIs Signed-off-by: Martino Facchin --- targets/TARGET_STM/pwmout_api.c | 196 +++++++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index 8026921c670..1564a1c4d3e 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -39,6 +39,22 @@ static TIM_HandleTypeDef TimHandle; +#if defined(HRTIM1) +#define HRTIM_CHANNEL(Y,X) (uint32_t)(0x00000001 << ((((Y*2)+(X)) & 0xF))) +#define HRTIM_TIMERID(X) (uint32_t)(0x00000001 << (17U + X))// << (X))) + +typedef struct{ + uint8_t timer; + uint32_t channel; + uint32_t timerid; +} hrtim_t; + +static hrtim_t hrtim_timer; +static HRTIM_HandleTypeDef HrtimHandle; +static HRTIM_CompareCfgTypeDef sConfig_compare; +static HRTIM_TimeBaseCfgTypeDef sConfig_time_base; +#endif + /* Convert STM32 Cube HAL channel to LL channel */ uint32_t TIM_ChannelConvert_HAL2LL(uint32_t channel, pwmout_t *obj) { @@ -86,7 +102,6 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) { // Get the peripheral name from the pin and assign it to the object obj->pwm = (PWMName)pinmap->peripheral; - MBED_ASSERT(obj->pwm != (PWMName)NC); // Get the functions (timer channel, (non)inverted) from the pin and assign it to the object uint32_t function = (uint32_t)pinmap->function; @@ -94,6 +109,116 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) obj->channel = STM_PIN_CHANNEL(function); obj->inverted = STM_PIN_INVERTED(function); +#if defined(HRTIM1) + if (obj->pwm == PWM_I) { + + HRTIM_TimerCfgTypeDef sConfig_timer; + HRTIM_OutputCfgTypeDef sConfig_output_config; + + __HAL_RCC_HRTIM1_CLK_ENABLE(); + + if(STM_PORT(pinmap->pin) == 0) { + __HAL_RCC_GPIOA_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 1) { + __HAL_RCC_GPIOB_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 2) { + __HAL_RCC_GPIOC_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 3) { + __HAL_RCC_GPIOD_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 4) { + __HAL_RCC_GPIOE_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 5) { + __HAL_RCC_GPIOF_CLK_ENABLE(); + } else if(STM_PORT(pinmap->pin) == 6) { + __HAL_RCC_GPIOG_CLK_ENABLE(); + } else { + __HAL_RCC_GPIOH_CLK_ENABLE(); + } + + hrtim_timer.timer = obj->channel; + hrtim_timer.channel = HRTIM_CHANNEL(hrtim_timer.timer,obj->inverted); + hrtim_timer.timerid = HRTIM_TIMERID(hrtim_timer.timer); + + pin_function(pinmap->pin, pinmap->function); + pin_mode(pinmap->pin, PullNone); + + obj->period = 1000; + obj->pulse = 500; + obj->prescaler = 0x00000004U; + + // Initialize the HRTIM structure + HrtimHandle.Instance = HRTIM1; + HrtimHandle.Init.HRTIMInterruptResquests = HRTIM_IT_NONE; + HrtimHandle.Init.SyncOptions = HRTIM_SYNCOPTION_NONE; + + HAL_HRTIM_Init(&HrtimHandle); + + // Configure the HRTIM TIME PWM channels 2 + sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; + sConfig_time_base.Period = 10000; + sConfig_time_base.PrescalerRatio = HRTIM_PRESCALERRATIO_DIV4; + sConfig_time_base.RepetitionCounter = 0; + + HAL_HRTIM_TimeBaseConfig(&HrtimHandle, hrtim_timer.timer, &sConfig_time_base); + + sConfig_timer.DMARequests = HRTIM_TIM_DMA_NONE; + sConfig_timer.HalfModeEnable = HRTIM_HALFMODE_DISABLED; + sConfig_timer.StartOnSync = HRTIM_SYNCSTART_DISABLED; + sConfig_timer.ResetOnSync = HRTIM_SYNCRESET_DISABLED; + sConfig_timer.DACSynchro = HRTIM_DACSYNC_NONE; + sConfig_timer.PreloadEnable = HRTIM_PRELOAD_ENABLED; + sConfig_timer.UpdateGating = HRTIM_UPDATEGATING_INDEPENDENT; + sConfig_timer.BurstMode = HRTIM_TIMERBURSTMODE_MAINTAINCLOCK; + sConfig_timer.RepetitionUpdate = HRTIM_UPDATEONREPETITION_ENABLED; + sConfig_timer.ResetUpdate = HRTIM_TIMUPDATEONRESET_DISABLED; + sConfig_timer.InterruptRequests = HRTIM_TIM_IT_NONE; + sConfig_timer.PushPull = HRTIM_TIMPUSHPULLMODE_DISABLED; + sConfig_timer.FaultEnable = HRTIM_TIMFAULTENABLE_NONE; + sConfig_timer.FaultLock = HRTIM_TIMFAULTLOCK_READWRITE; + sConfig_timer.DeadTimeInsertion = HRTIM_TIMDEADTIMEINSERTION_DISABLED; + sConfig_timer.UpdateTrigger = HRTIM_TIMUPDATETRIGGER_NONE; + sConfig_timer.ResetTrigger = HRTIM_TIMRESETTRIGGER_NONE; + + HAL_HRTIM_WaveformTimerConfig(&HrtimHandle, hrtim_timer.timer, &sConfig_timer); + + sConfig_compare.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; + sConfig_compare.AutoDelayedTimeout = 0; + sConfig_compare.CompareValue = 5000; + + HAL_HRTIM_WaveformCompareConfig(&HrtimHandle, hrtim_timer.timer, HRTIM_COMPAREUNIT_2, &sConfig_compare); + + sConfig_output_config.Polarity = HRTIM_OUTPUTPOLARITY_LOW; + sConfig_output_config.SetSource = HRTIM_OUTPUTRESET_TIMCMP2; + sConfig_output_config.ResetSource = HRTIM_OUTPUTSET_TIMPER; + sConfig_output_config.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; + sConfig_output_config.IdleLevel = HRTIM_OUTPUTIDLELEVEL_INACTIVE; + sConfig_output_config.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; + sConfig_output_config.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; + sConfig_output_config.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; + sConfig_output_config.ResetSource = HRTIM_OUTPUTRESET_TIMPER; + sConfig_output_config.SetSource = HRTIM_OUTPUTSET_TIMCMP2; + + HAL_HRTIM_WaveformOutputConfig(&HrtimHandle, hrtim_timer.timer, hrtim_timer.channel, &sConfig_output_config); + + // Start PWM signals generation + if (HAL_HRTIM_WaveformOutputStart(&HrtimHandle, hrtim_timer.channel) != HAL_OK) + { + // PWM Generation Error + return; + } + + // Start HRTIM counter + if (HAL_HRTIM_WaveformCounterStart(&HrtimHandle, hrtim_timer.timerid) != HAL_OK) + { + // PWM Generation Error + return; + } + pwmout_period_us(obj, 1000); // 20 ms per default + + return; + } +#endif + // Enable TIM clock #if defined(TIM1_BASE) if (obj->pwm == PWM_1) { @@ -208,9 +333,17 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) void pwmout_init(pwmout_t *obj, PinName pin) { - int peripheral = (int)pinmap_peripheral(pin, PinMap_PWM); + int peripheral = 0; int function = (int)pinmap_find_function(pin, PinMap_PWM); + // check Function before peripheral because pinmap_peripheral + // assert a error and stop the exectution + if (function == -1) { + peripheral = (int)pinmap_peripheral(pin, PinMap_PWM_HRTIM); + function = (int)pinmap_find_function(pin, PinMap_PWM_HRTIM); + } else { + peripheral = (int)pinmap_peripheral(pin, PinMap_PWM); + } const PinMap static_pinmap = {pin, peripheral, function}; PWM_INIT_DIRECT(obj, &static_pinmap); @@ -224,6 +357,24 @@ void pwmout_free(pwmout_t *obj) void pwmout_write(pwmout_t *obj, float value) { + +#if defined(HRTIM1) + if (obj->pwm == PWM_I) { + if (value < (float)0.0) { + value = 0.0; + } else if (value > (float)1.0) { + value = 1.0; + } + obj->pulse = value; + sConfig_compare.CompareValue = (uint32_t)((float)obj->period * value + 0.5); + if (HAL_HRTIM_WaveformCompareConfig(&HrtimHandle, hrtim_timer.timer, HRTIM_COMPAREUNIT_2, &sConfig_compare) != HAL_OK) + { + return; + } + return; + } +#endif + TIM_OC_InitTypeDef sConfig; int channel = 0; @@ -291,6 +442,13 @@ void pwmout_write(pwmout_t *obj, float value) float pwmout_read(pwmout_t *obj) { float value = 0; + +#if defined(HRTIM1) + if(obj->pwm == PWM_I) { + return obj->pulse; + } +#endif + if (obj->period > 0) { value = (float)(obj->pulse) / (float)(obj->period); } @@ -309,6 +467,40 @@ void pwmout_period_ms(pwmout_t *obj, int ms) void pwmout_period_us(pwmout_t *obj, int us) { + +#if defined(HRTIM1) + if (obj->pwm == PWM_I) { + float dc = pwmout_read(obj); + + /* Parse the pwm / apb mapping table to find the right entry */ + unsigned long frequency = 400; + + /* conversion from us to clock tick*/ + obj->period = frequency * us; + + obj->prescaler = 0x00000004U; + /* In case period or pre-scalers are out of range, loop-in to get valid values */ + /* this upper limit can be increased but degdating the efficiency of the clock*/ + while (obj->period > 50000) { + obj->prescaler = obj->prescaler + 1; + if(obj->prescaler == 8) { + obj->prescaler = 0x00000007U; + break; + } + frequency = frequency/2; + obj->period = frequency *us; + } + sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; + sConfig_time_base.Period = obj->period; + sConfig_time_base.PrescalerRatio = obj->prescaler; + sConfig_time_base.RepetitionCounter = 0; + + HAL_HRTIM_TimeBaseConfig(&HrtimHandle, hrtim_timer.timer, &sConfig_time_base); + pwmout_write(obj, dc); + return; + } +#endif + TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); RCC_ClkInitTypeDef RCC_ClkInitStruct; uint32_t PclkFreq = 0; From bea4beebeaced6d06643b8c1bf1dff64d690fbdd Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 28 Jun 2021 17:04:01 +0200 Subject: [PATCH 074/227] STM32: HRTIM: greatly simplify corner cases --- targets/TARGET_STM/pwmout_api.c | 57 +++++++++++++++------------------ 1 file changed, 25 insertions(+), 32 deletions(-) diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index 1564a1c4d3e..906dc1dcfdc 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -142,9 +142,9 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) pin_function(pinmap->pin, pinmap->function); pin_mode(pinmap->pin, PullNone); - obj->period = 1000; - obj->pulse = 500; - obj->prescaler = 0x00000004U; + obj->period = 0; + obj->pulse = 0; + obj->prescaler = 0; // Initialize the HRTIM structure HrtimHandle.Instance = HRTIM1; @@ -155,7 +155,7 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) // Configure the HRTIM TIME PWM channels 2 sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; - sConfig_time_base.Period = 10000; + sConfig_time_base.Period = 0xFFDFU; sConfig_time_base.PrescalerRatio = HRTIM_PRESCALERRATIO_DIV4; sConfig_time_base.RepetitionCounter = 0; @@ -183,7 +183,7 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) sConfig_compare.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; sConfig_compare.AutoDelayedTimeout = 0; - sConfig_compare.CompareValue = 5000; + sConfig_compare.CompareValue = 0; HAL_HRTIM_WaveformCompareConfig(&HrtimHandle, hrtim_timer.timer, HRTIM_COMPAREUNIT_2, &sConfig_compare); @@ -213,7 +213,7 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) // PWM Generation Error return; } - pwmout_period_us(obj, 1000); // 20 ms per default + pwmout_period_us(obj, 18000); // 550Hz minimum default return; } @@ -336,9 +336,8 @@ void pwmout_init(pwmout_t *obj, PinName pin) int peripheral = 0; int function = (int)pinmap_find_function(pin, PinMap_PWM); // check Function before peripheral because pinmap_peripheral - // assert a error and stop the exectution + // assert a error and stop the execution if (function == -1) { - peripheral = (int)pinmap_peripheral(pin, PinMap_PWM_HRTIM); function = (int)pinmap_find_function(pin, PinMap_PWM_HRTIM); } else { @@ -365,8 +364,8 @@ void pwmout_write(pwmout_t *obj, float value) } else if (value > (float)1.0) { value = 1.0; } - obj->pulse = value; - sConfig_compare.CompareValue = (uint32_t)((float)obj->period * value + 0.5); + obj->pulse = (uint32_t)((float)obj->period * value + 0.5); + sConfig_compare.CompareValue = obj->pulse; if (HAL_HRTIM_WaveformCompareConfig(&HrtimHandle, hrtim_timer.timer, HRTIM_COMPAREUNIT_2, &sConfig_compare) != HAL_OK) { return; @@ -442,13 +441,6 @@ void pwmout_write(pwmout_t *obj, float value) float pwmout_read(pwmout_t *obj) { float value = 0; - -#if defined(HRTIM1) - if(obj->pwm == PWM_I) { - return obj->pulse; - } -#endif - if (obj->period > 0) { value = (float)(obj->pulse) / (float)(obj->period); } @@ -472,24 +464,25 @@ void pwmout_period_us(pwmout_t *obj, int us) if (obj->pwm == PWM_I) { float dc = pwmout_read(obj); - /* Parse the pwm / apb mapping table to find the right entry */ - unsigned long frequency = 400; + uint32_t frequency; + uint32_t clocksource = __HAL_RCC_GET_HRTIM1_SOURCE(); + switch (clocksource) { + case RCC_HRTIM1CLK_TIMCLK: + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_HRTIM1CLK_CPUCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + } - /* conversion from us to clock tick*/ - obj->period = frequency * us; + /* conversion from us to clock tick */ + obj->period = us * (frequency / 1000000) / 4; + obj->prescaler = HRTIM_PRESCALERRATIO_DIV4; - obj->prescaler = 0x00000004U; - /* In case period or pre-scalers are out of range, loop-in to get valid values */ - /* this upper limit can be increased but degdating the efficiency of the clock*/ - while (obj->period > 50000) { - obj->prescaler = obj->prescaler + 1; - if(obj->prescaler == 8) { - obj->prescaler = 0x00000007U; - break; - } - frequency = frequency/2; - obj->period = frequency *us; + if (obj->period > 0xFFDFU) { + obj->period = 0xFFDFU; } + sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; sConfig_time_base.Period = obj->period; sConfig_time_base.PrescalerRatio = obj->prescaler; From 03b68acb864b180b1429c30f2646785beb487bca Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 29 Jun 2021 15:04:33 +0200 Subject: [PATCH 075/227] Portenta: PWM: force PA8 to use HRTIM Since PA8 and PK1 share the same timer/channel mux, using both result in glitches. PA8 also supports HRTIM, so use it. --- .../TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c index 9e7339bcdb5..3b1cf1075bf 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c @@ -171,7 +171,7 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 From cbdb7707cebb46d5887dc7f282e547a9135e5f74 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 16 Aug 2021 17:19:45 +0200 Subject: [PATCH 076/227] STM32H7: CM4: avoid vtor relocation via define --- .../STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 8e0017de2aa..b4a4cc78263 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -232,7 +232,7 @@ __weak void SystemInit (void) /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else +#elif !defined(NO_VTOR_RELOCATE) #include "nvic_addr.h" // MBED SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED #endif From 6f1f7b1def36a77de936cdc2a49bd25040eed389 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 11 Aug 2021 12:14:57 +0200 Subject: [PATCH 077/227] STM32: analogin: use critical section to protect PLL configuration --- targets/TARGET_STM/TARGET_STM32H7/analogin_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 449b3a3e015..8851773c13f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -32,6 +32,8 @@ void analogin_pll_configuration(void) } #endif /* DUAL_CORE */ + core_util_critical_section_enter(); + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInitStruct.PLL2.PLL2M = 4; @@ -47,6 +49,8 @@ void analogin_pll_configuration(void) error("analogin_init HAL_RCCEx_PeriphCLKConfig"); } + core_util_critical_section_exit(); + #if defined(DUAL_CORE) LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); #endif /* DUAL_CORE */ From 531ab8f2cf8da34f4ecb84da172cf9eb0e64ddd9 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 22 Jul 2021 12:04:53 +0200 Subject: [PATCH 078/227] PortentaH7: implement and use get_default_instance for QSPIBD --- .../COMPONENT_WHD/port/wiced_filesystem.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp index b6de4ece122..bea07abdef5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -36,12 +36,18 @@ #define WIFI_DEFAULT_PARTITION 1 #define WIFI_DEFAULT_FS 0 -QSPIFBlockDevice *qspi_bd = NULL; +BlockDevice *qspi_bd = NULL; MBRBlockDevice *mbr_bd = NULL; FATFileSystem *wifi_fs = NULL; wiced_filesystem_t resource_fs_handle; +MBED_WEAK BlockDevice *BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PD_12, PF_7, PD_13, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} + MBED_WEAK void wiced_filesystem_mount_error(void) { WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); @@ -134,7 +140,7 @@ wiced_result_t wiced_filesystem_init(void) { if (mbr_bd == NULL && wifi_fs == NULL) { WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); - qspi_bd = new QSPIFBlockDevice(PD_11, PD_12, PF_7, PD_13, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + qspi_bd = mbed::BlockDevice::get_default_instance(); if (qspi_bd->init() == BD_ERROR_OK) { mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); From 2444478e0643949708b700edf6362491e62336b9 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 23 Jul 2021 11:29:13 +0200 Subject: [PATCH 079/227] PortentaH7: Disable WHD WPRINT_MACRO --- .../COMPONENT_WHD/port/cyhal_hw_types.h | 13 +------------ .../TARGET_PORTENTA_H7/COMPONENT_WHD/whd_config.h | 3 +++ 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_hw_types.h index 7028ab1f166..1f872abb373 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_hw_types.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_hw_types.h @@ -102,19 +102,8 @@ typedef struct void *empty; } cyhal_spi_t; - -#include "whd_debug.h" - -#if defined(WPRINT_ENABLE_WHD_ERROR) || defined(WPRINT_ENABLE_WHD_INFO) || defined(WPRINT_ENABLE_WHD_DEBUG) -/** \} group_hal_hw_types_data_structures */ -#define PRINTF(...) do { \ - (void) printf(__VA_ARGS__); \ - } while (0) -#else -#define PRINTF(...) -#endif - #include "whd_config.h" +#include "whd_debug.h" #if defined(__cplusplus) } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/whd_config.h index da67e0a0363..cc442a6e44d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/whd_config.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/whd_config.h @@ -26,6 +26,9 @@ #include "stm32h7xx_hal.h" #include +/* disable WPRINT_MACRO */ +#define WHD_PRINT_DISABLE + /* please define your configuration , either SDIO or SPI */ #define CY_WHD_CONFIG_USE_SDIO //#define CY_WHD_CONFIG_USE_SPI From 512daf99a458422d09775d84958824508c8361a6 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 27 Nov 2020 10:34:42 +0100 Subject: [PATCH 080/227] Add NICLA target --- .../blockdevice/COMPONENT_SD/mbed_lib.json | 8 +- .../blockdevice/COMPONENT_SPIF/mbed_lib.json | 6 + .../TARGET_NICLA/PinNames.h | 188 ++++++++++++++++++ .../TARGET_MCU_NRF52832/TARGET_NICLA/device.h | 22 ++ targets/targets.json | 25 +++ 5 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/PinNames.h create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/device.h diff --git a/storage/blockdevice/COMPONENT_SD/mbed_lib.json b/storage/blockdevice/COMPONENT_SD/mbed_lib.json index f32740e91e4..cf06319ec0f 100644 --- a/storage/blockdevice/COMPONENT_SD/mbed_lib.json +++ b/storage/blockdevice/COMPONENT_SD/mbed_lib.json @@ -133,6 +133,12 @@ "SPI_MOSI": "SPI_MOSI", "SPI_MISO": "SPI_MISO", "SPI_CLK": "SPI_SCK" - } + }, + "NICLA": { + "SPI_MOSI": "P0_13", + "SPI_MISO": "P0_14", + "SPI_CLK": "P0_12", + "SPI_CS": "P0_16" + } } } diff --git a/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index f8bb387f3c5..d8ace44fde4 100644 --- a/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -67,6 +67,12 @@ "SPI_MISO": "SPI3_MISO", "SPI_CLK": "SPI3_SCK", "SPI_CS": "SPI_CS1" + }, + "NICLA": { + "SPI_MOSI": "SPI_PSELMOSI0", + "SPI_MISO": "SPI_PSELMISO0", + "SPI_CLK": "SPI_PSELSCK0", + "SPI_CS": "CS_FLASH" } } } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/PinNames.h new file mode 100644 index 00000000000..cbe53a622db --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/PinNames.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + // Not connected + NC = (int)0xFFFFFFFF, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + P0_31 = p31, + + LED1 = p11, + LED2 = p11, + LED3 = p11, + LED4 = p11, + + //INT_BQ = p18, + INT_BHI260 = p14, + BQ_CDN = p25, + INT_ESLOV = p19, + //BHI_HOSTBOOT = p25, + RESET_BHI260 = p18, + + BUTTON1 = p21, + + GPIO0 = p24, + GPIO1 = p20, + GPIO2 = p9, + GPIO3 = p10, + + RX_PIN_NUMBER = p9, + TX_PIN_NUMBER = p20, + CTS_PIN_NUMBER = NC, + RTS_PIN_NUMBER = NC, + + CONSOLE_TX = TX_PIN_NUMBER, + CONSOLE_RX = RX_PIN_NUMBER, + + // mBed interface Pins + STDIO_UART_TX = TX_PIN_NUMBER, + STDIO_UART_RX = RX_PIN_NUMBER, + STDIO_UART_CTS = CTS_PIN_NUMBER, + STDIO_UART_RTS = RTS_PIN_NUMBER, + + SPI_PSELSCK0 = p3, + SPI_PSELMISO0 = p5, + SPI_PSELMOSI0 = p4, + SPI_PSELSS0 = p31, + CS_FLASH = p26, + + SPI_PSELSS1 = p29, + SPI_PSELMISO1 = p28, + SPI_PSELMOSI1 = p27, + SPI_PSELSCK1 = p11, + + I2C_SDA0 = p15, + I2C_SCL0 = p16, + + I2C_SDA1 = p22, + I2C_SCL1 = p23, +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/device.h new file mode 100644 index 00000000000..7d91b12ccac --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NICLA/device.h @@ -0,0 +1,22 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/targets.json b/targets/targets.json index 0e82d5cff2d..c7350046e28 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6906,6 +6906,31 @@ ], "device_name": "nRF52832_xxAA" }, + "NICLA": { + "inherits": ["MCU_NRF52832"], + "components_add": [ + "FLASHIAP" + ], + "release_versions": ["5"], + "device_name": "nRF52832_xxAA", + "macros_add": [ + "CONFIG_GPIO_AS_PINRESET", + "NRF52_PAN_12", + "NRF52_PAN_15", + "NRF52_PAN_20", + "NRF52_PAN_30", + "NRF52_PAN_31", + "NRF52_PAN_36", + "NRF52_PAN_51", + "NRF52_PAN_53", + "NRF52_PAN_54", + "NRF52_PAN_55", + "NRF52_PAN_58", + "NRF52_PAN_62", + "NRF52_PAN_63", + "NRF52_PAN_64" + ] + }, "MCU_NRF52840": { "inherits": [ "Target" From 56027aff39458244af7a03681ee70ac549b62c06 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Aug 2021 11:47:20 +0200 Subject: [PATCH 081/227] NICLA: use nfc pins as GPIOs --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index c7350046e28..fe5bcf4d432 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6915,6 +6915,7 @@ "device_name": "nRF52832_xxAA", "macros_add": [ "CONFIG_GPIO_AS_PINRESET", + "CONFIG_NFCT_PINS_AS_GPIOS", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_20", From e556ca3c1e60ad54122cb7dbfaf84d908bc226b1 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 17 Sep 2021 17:04:41 +0200 Subject: [PATCH 082/227] Fix cast error in WHD --- .../wifi-host-driver/src/bus_protocols/whd_bus_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_common.c b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_common.c index 4eacf4869aa..48c401a0a09 100755 --- a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_common.c +++ b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_common.c @@ -179,7 +179,7 @@ static whd_result_t whd_bus_common_download_resource(whd_driver_t whd_driver, wh uint32_t tmp; /* verify reset instruction value */ - result = whd_bus_read_backplane_value(whd_driver, 0, sizeof(tmp), (uint8_t *)&tmp); + result = whd_bus_read_backplane_value(whd_driver, 0, sizeof(tmp), (uint32_t *)&tmp); if ( (result == WHD_SUCCESS) && (tmp != reset_instr) ) { From d28bec851428b2a958f64416fbc50e55b7e9c0d4 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 22 Sep 2021 15:34:24 +0200 Subject: [PATCH 083/227] mbed-client-cli: ns_cmdline: make cmd_class_t cmd private --- features/frameworks/mbed-client-cli/source/ns_cmdline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/frameworks/mbed-client-cli/source/ns_cmdline.c b/features/frameworks/mbed-client-cli/source/ns_cmdline.c index 7e113502b63..1384e278eae 100644 --- a/features/frameworks/mbed-client-cli/source/ns_cmdline.c +++ b/features/frameworks/mbed-client-cli/source/ns_cmdline.c @@ -355,7 +355,7 @@ typedef struct cmd_class_s { input_passthrough_func_t passthrough_fnc; // input passthrough cb function } cmd_class_t; -cmd_class_t cmd = { +static cmd_class_t cmd = { .init = false, .cmd_ptr = NULL, .mutex_wait_fnc = NULL, From 751e46825645cb1ce4e91c3f284f0f9dfef01d72 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 23 Sep 2021 15:16:10 +0200 Subject: [PATCH 084/227] BlockDevice: add mbed namespace to function signatures --- storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp | 2 +- storage/blockdevice/COMPONENT_SPIF/source/SPIFBlockDevice.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 39b8c1c43c6..898141f780d 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -617,7 +617,7 @@ int QSPIFBlockDevice::remove_csel_instance(PinName csel) /*********************************************************/ /********** SFDP Parsing and Detection Functions *********/ /*********************************************************/ -int QSPIFBlockDevice::_sfdp_parse_basic_param_table(Callback sfdp_reader, +int QSPIFBlockDevice::_sfdp_parse_basic_param_table(Callback sfdp_reader, sfdp_hdr_info &sfdp_info) { uint8_t param_table[SFDP_BASIC_PARAMS_TBL_SIZE]; /* Up To 20 DWORDS = 80 Bytes */ diff --git a/storage/blockdevice/COMPONENT_SPIF/source/SPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_SPIF/source/SPIFBlockDevice.cpp index bdbcae9e383..8b7e89b2d44 100644 --- a/storage/blockdevice/COMPONENT_SPIF/source/SPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_SPIF/source/SPIFBlockDevice.cpp @@ -607,7 +607,7 @@ spif_bd_error SPIFBlockDevice::_spi_send_general_command(int instruction, bd_add /*********************************************************/ /********** SFDP Parsing and Detection Functions *********/ /*********************************************************/ -int SPIFBlockDevice::_sfdp_parse_basic_param_table(Callback sfdp_reader, +int SPIFBlockDevice::_sfdp_parse_basic_param_table(Callback sfdp_reader, sfdp_hdr_info &sfdp_info) { uint8_t param_table[SFDP_BASIC_PARAMS_TBL_SIZE]; /* Up To 20 DWORDS = 80 Bytes */ From e997bd0ac4e58c0d2b4e857d72dd432790cd4f00 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 13 Oct 2021 10:48:44 +0200 Subject: [PATCH 085/227] Use ADC clock synchronous with AHB --- targets/TARGET_STM/TARGET_STM32H7/analogin_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 8851773c13f..bdf3277e1c3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -89,7 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin) // Configure ADC object structures obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; obj->handle.Init.Resolution = ADC_RESOLUTION_16B; obj->handle.Init.ScanConvMode = ADC_SCAN_DISABLE; obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; From 5a2377ec9d5bf106c9bac4b0b7968ef725d593a4 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 30 Jul 2021 17:22:36 +0200 Subject: [PATCH 086/227] RP2040: Add basic RTC support --- .../hardware_rtc/include/hardware/rtc.h | 2 +- .../pico-sdk/rp2_common/hardware_rtc/rtc.c | 2 +- .../TARGET_RP2040/rtc_api.c | 91 +++++++++++++++++++ targets/targets.json | 1 + 4 files changed, 94 insertions(+), 2 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/rtc_api.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h index 83d5bdf288c..dcdcd2285f6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h @@ -34,7 +34,7 @@ typedef void (*rtc_callback_t)(void); /*! \brief Initialise the RTC system * \ingroup hardware_rtc */ -void rtc_init(void); +void _rtc_init(void); /*! \brief Set the RTC to the specified time * \ingroup hardware_rtc diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c index 91bd1994c1d..ebd6783ba00 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c @@ -19,7 +19,7 @@ bool rtc_running(void) { return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); } -void rtc_init(void) { +void _rtc_init(void) { // Get clk_rtc freq and make sure it is running uint rtc_freq = clock_get_hz(clk_rtc); assert(rtc_freq != 0); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/rtc_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/rtc_api.c new file mode 100644 index 00000000000..999f5563557 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/rtc_api.c @@ -0,0 +1,91 @@ +#if DEVICE_RTC + +#include "rtc_api.h" +#include "hardware/rtc.h" +#include "hardware/structs/rtc.h" +#include "mbed_mktime.h" + +void rtc_init(void) +{ + _rtc_init(); +} + +void rtc_free(void) +{ + /* RTC clock can not be reset */ +} + +int rtc_isenabled(void) +{ + return rtc_running(); +} + +time_t rtc_read(void) +{ + struct tm timeinfo; + time_t t; + datetime_t date; + + if (!rtc_get_datetime(&date)) { + return 0; + } + + /* Setup a tm structure based on the RTC + struct tm : + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_yday information is ignored by _rtc_maketime + tm_wday information is ignored by _rtc_maketime + tm_isdst information is ignored by _rtc_maketime + */ + timeinfo.tm_year = date.year - 1900; + timeinfo.tm_mon = date.month - 1; + timeinfo.tm_mday = date.day; + timeinfo.tm_wday = date.dotw; + timeinfo.tm_hour = date.hour; + timeinfo.tm_min = date.min; + timeinfo.tm_sec = date.sec; + + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + + return t; +} + +void rtc_write(time_t t) +{ + struct tm timeinfo; + datetime_t date; + + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return; + } + + /* Setup a datetime_t structure based on the RTC + struct datetime_t + year; 0..4095 + month; 1..12, 1 is January + day; 1..28,29,30,31 depending on month + dotw; 0..6, 0 is Sunday + hour; 0..23 + min; 0..59 + sec; 0..59 + */ + date.year = timeinfo.tm_year + 1900; + date.month = timeinfo.tm_mon + 1; + date.day = timeinfo.tm_mday; + date.dotw = timeinfo.tm_wday; + date.hour = timeinfo.tm_hour; + date.min = timeinfo.tm_min; + date.sec = timeinfo.tm_sec; + + rtc_set_datetime(&date); + return; +} + +#endif // DEVICE_RTC diff --git a/targets/targets.json b/targets/targets.json index fe5bcf4d432..5e957dba707 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9457,6 +9457,7 @@ "SERIAL", "SERIAL_FC", "SPI", + "RTC", "USTICKER", "WATCHDOG", "USBDEVICE", From 66802720c1406671a5333eda00d8dcf43729d7b1 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 9 Nov 2021 09:20:36 +0100 Subject: [PATCH 087/227] RP2040: Watchdog: get_reload_value returns 0 if wd is not properly configured --- .../TARGET_RP2040/watchdog_api.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c index 9263eb48d5c..7526f6b6085 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c @@ -4,16 +4,18 @@ #if DEVICE_WATCHDOG -static watchdog_config_t watchdogConfig; +static watchdog_config_t watchdogConfig = { + 0 // timeout_ms +}; watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) { - watchdogConfig = *config; // The pico watchdogs accept a maximum value of 0x7fffff if ( config->timeout_ms < 0x1 && config->timeout_ms > 0x7FFFFF ) { return WATCHDOG_STATUS_INVALID_ARGUMENT; } + watchdogConfig = *config; watchdog_enable(config->timeout_ms, true); return WATCHDOG_STATUS_OK; @@ -32,9 +34,12 @@ watchdog_status_t hal_watchdog_stop(void) uint32_t hal_watchdog_get_reload_value(void) { - uint32_t load_value = watchdogConfig.timeout_ms * 1000 * 2; - if (load_value > 0xffffffu) { - load_value = 0xffffffu; + uint32_t load_value = 0; + if ( watchdogConfig.timeout_ms > 0 ) { + load_value = watchdogConfig.timeout_ms * 1000 * 2; + if (load_value > 0xffffffu) { + load_value = 0xffffffu; + } } return load_value; } From c3e4ce73d19f384ef5d874e7aad0a89ec3d7b80e Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 15 Nov 2021 16:47:42 +0100 Subject: [PATCH 088/227] RP2040: backport p2040_usb_device_enumeration fix --- .../rp2040_usb_device_enumeration.c | 42 +++++++++++++++---- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c index 8319e36cb71..91583205bbb 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c @@ -8,6 +8,8 @@ #include "pico/time.h" #include "hardware/structs/usb.h" #include "hardware/gpio.h" +#include "hardware/structs/iobank0.h" +#include "hardware/structs/padsbank0.h" #include "pico/fix/rp2040_usb_device_enumeration.h" #define LS_SE0 0b00 @@ -36,7 +38,7 @@ static inline uint8_t hw_line_state(void) { return (usb_hw->sie_status & USB_SIE_STATUS_LINE_STATE_BITS) >> USB_SIE_STATUS_LINE_STATE_LSB; } -int64_t hw_enumeration_fix_wait_se0_callback(alarm_id_t id, void *user_data) { +int64_t hw_enumeration_fix_wait_se0_callback(__unused alarm_id_t id, __unused void *user_data) { if (hw_line_state() == LS_SE0) { // Come back in 1ms and check again return 1000; @@ -69,25 +71,42 @@ static void hw_enumeration_fix_wait_se0(void) { hw_enumeration_fix_busy_wait_se0(); } -int64_t hw_enumeration_fix_force_ls_j_done(alarm_id_t id, void *user_data) { +int64_t hw_enumeration_fix_force_ls_j_done(__unused alarm_id_t id, __unused void *user_data) { hw_enumeration_fix_finish(); return 0; } +static uint32_t gpio_ctrl_prev = 0; +static uint32_t pad_ctrl_prev = 0; +static const uint dp = 15; +static const uint dm = 16; + static void hw_enumeration_fix_force_ls_j(void) { - // Force LS_J - const uint dp = 15; - //const uint dm = 16; - gpio_set_function(dp, 8); - // TODO: assert dm is not funcseld to usb + // DM must be 0 for this to work. This is true if it is selected + // to any other function. fn 8 on this pin is only for debug so shouldn't + // be selected + if (gpio_get_function(dm) == 8) { + panic("Not expecting DM to be function 8"); + } + + // Before changing any pin state, take a copy of the current gpio control register + gpio_ctrl_prev = iobank0_hw->io[dp].ctrl; + // Also take a copy of the pads register + pad_ctrl_prev = padsbank0_hw->io[dp]; + + // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect + // pin state + gpio_set_pulls(dp, true, true); + gpio_set_oeover(dp, GPIO_OVERRIDE_LOW); + // Select function 8 (USB debug muxing) without disturbing other controls + hw_write_masked(&iobank0_hw->io[dp].ctrl, + 8 << IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB, IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS); // J state is a differential 1 for a full speed device so // DP = 1 and DM = 0. Don't actually need to set DM low as it // is already gated assuming it isn't funcseld. gpio_set_inover(dp, GPIO_OVERRIDE_HIGH); - // TODO: What to do about existing DP state here? - // Force PHY pull up to stay before switching away from the phy hw_set_alias(usb_hw)->phy_direct = USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS; hw_set_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS; @@ -118,4 +137,9 @@ static void hw_enumeration_fix_finish(void) { // Get rid of DP pullup override hw_clear_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS; + + // Finally, restore the gpio ctrl value back to GPIO15 + iobank0_hw->io[dp].ctrl = gpio_ctrl_prev; + // Restore the pad ctrl value + padsbank0_hw->io[dp] = pad_ctrl_prev; } From 79b674df052e7a5cb6c9b71d65416c23565470ec Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 6 Dec 2021 12:02:28 +0100 Subject: [PATCH 089/227] RP2040: correct system clock frequency Fixes https://github.com/arduino/ArduinoCore-mbed/issues/271 --- .../TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c | 2 +- .../TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c index 1f775638f9b..b9ad1319af5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_NANO_RP2040_CONNECT/board.c @@ -1,3 +1,3 @@ #include "PinNames.h" -uint32_t SystemCoreClock = 120000000; \ No newline at end of file +uint32_t SystemCoreClock = 125000000; \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c index 1f775638f9b..b9ad1319af5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/TARGET_RASPBERRY_PI_PICO/board.c @@ -1,3 +1,3 @@ #include "PinNames.h" -uint32_t SystemCoreClock = 120000000; \ No newline at end of file +uint32_t SystemCoreClock = 125000000; \ No newline at end of file From 6ef2abea8e05eddc813ddd30abd0724fcc945b4e Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 10 Dec 2020 19:23:36 +0100 Subject: [PATCH 090/227] Thales: mbed library porting Wrap changes for Thales inside a library include check Clean up library changes for Thales Fix recv API to correctly handle multiple reads --- .../cellular/framework/API/ATHandler.h | 7 ++ .../cellular/framework/API/CellularContext.h | 7 ++ .../framework/AT/AT_CellularContext.h | 3 + .../framework/AT/AT_CellularContext.cpp | 70 ++++++++++++++++++- .../source/framework/AT/AT_CellularDevice.cpp | 3 +- .../framework/AT/AT_CellularNetwork.cpp | 2 + .../source/framework/device/ATHandler.cpp | 12 +++- .../framework/device/CellularStateMachine.cpp | 8 ++- .../GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 31 ++++++++ .../GEMALTO/CINTERION/GEMALTO_CINTERION.h | 2 + .../GEMALTO_CINTERION_CellularContext.cpp | 20 ++++++ .../GEMALTO_CINTERION_CellularContext.h | 1 + .../GEMALTO_CINTERION_CellularStack.cpp | 50 +++++++++++++ .../GEMALTO_CINTERION_CellularStack.h | 9 +++ 14 files changed, 220 insertions(+), 5 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/API/ATHandler.h b/connectivity/cellular/include/cellular/framework/API/ATHandler.h index da2a6ea124a..bfcff552b9a 100644 --- a/connectivity/cellular/include/cellular/framework/API/ATHandler.h +++ b/connectivity/cellular/include/cellular/framework/API/ATHandler.h @@ -356,6 +356,12 @@ class ATHandler { */ void write_hex_string(const char *str, size_t size, bool quote_string = true); + /** Get the error detected during read_int() + * + * @return the latest negative integer error got from read_int(). + */ + int32_t get_last_read_error(); + /** Reads as string and converts result to integer. Supports only non-negative integers. * * @return the non-negative integer or -1 in case of error. @@ -638,6 +644,7 @@ class ATHandler { rtos::Kernel::Clock::time_point _start_time; // eventqueue event id int _event_id; + int32_t _last_read_error; char _cmd_buffer[MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE]; }; diff --git a/connectivity/cellular/include/cellular/framework/API/CellularContext.h b/connectivity/cellular/include/cellular/framework/API/CellularContext.h index 8281b1c25ed..1061d5d9264 100644 --- a/connectivity/cellular/include/cellular/framework/API/CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/API/CellularContext.h @@ -29,6 +29,12 @@ * */ +/* Radio Access Technology type */ +enum RadioAccessTechnologyType { + CATM1 = 7, + CATNB = 8 +}; + namespace mbed { /** @@ -153,6 +159,7 @@ class CellularContext : public CellularInterface { virtual nsapi_error_t connect(const char *sim_pin, const char *apn = 0, const char *uname = 0, const char *pwd = 0) = 0; virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0) = 0; + virtual void set_access_technology(RadioAccessTechnologyType rat = CATM1) = 0; virtual bool is_connected() = 0; /** Same as NetworkInterface::get_default_instance() diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index b1d8985a9c6..19099c0e083 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -47,6 +47,7 @@ class AT_CellularContext : public CellularContext { virtual nsapi_error_t connect(const char *sim_pin, const char *apn = 0, const char *uname = 0, const char *pwd = 0); virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0); + virtual void set_access_technology(RadioAccessTechnologyType rat = CATM1); // from CellularContext virtual nsapi_error_t get_pdpcontext_params(pdpContextList_t ¶ms_list); @@ -107,6 +108,7 @@ class AT_CellularContext : public CellularContext { * @return NIDD context text, e.g. Non-IP or NONIP */ virtual const char *get_nonip_context_type_str(); + virtual void enable_access_technology(); private: #if NSAPI_PPP_AVAILABLE @@ -132,6 +134,7 @@ class AT_CellularContext : public CellularContext { PinName _dcd_pin; bool _active_high; + RadioAccessTechnologyType _rat; protected: char _found_apn[MAX_APN_LENGTH]; diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index f2b1d632b95..b4678ff0817 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -48,7 +48,7 @@ using namespace rtos; using namespace std::chrono_literals; AT_CellularContext::AT_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) : - _current_op(OP_INVALID), _dcd_pin(NC), _active_high(false), _cp_req(cp_req), _is_connected(false), _at(at) + _current_op(OP_INVALID), _dcd_pin(NC), _active_high(false), _rat(CATM1), _cp_req(cp_req), _is_connected(false), _at(at) { tr_info("New CellularContext %s (%p)", apn ? apn : "", this); _nonip_req = nonip_req; @@ -268,6 +268,27 @@ nsapi_error_t AT_CellularContext::connect(const char *sim_pin, const char *apn, { set_sim_pin(sim_pin); set_credentials(apn, uname, pwd); + +#if defined __has_include +# if __has_include () + set_device_ready(); + + _at.lock(); + bool valid_context = get_context(); + _at.unlock(); + + if(!valid_context) { + set_new_context(_cid); + } + + do_user_authentication(); + + enable_access_technology(); + + do_connect(); +# endif +#endif + return connect(); } @@ -278,6 +299,11 @@ void AT_CellularContext::set_credentials(const char *apn, const char *uname, con _pwd = pwd; } +void AT_CellularContext::set_access_technology(RadioAccessTechnologyType rat) +{ + _rat = rat; +} + // PDP Context handling void AT_CellularContext::delete_current_context() { @@ -352,7 +378,13 @@ bool AT_CellularContext::get_context() int pdp_type_len = _at.read_string(pdp_type_from_context, sizeof(pdp_type_from_context)); if (pdp_type_len > 0) { apn_len = _at.read_string(apn, sizeof(apn)); +#if defined __has_include +# if __has_include () + if (apn_len > 0) { +# else if (apn_len >= 0) { +# endif +#endif if (_apn && (strcmp(apn, _apn) != 0)) { tr_debug("CID %d APN \"%s\"", cid, apn); continue; @@ -370,6 +402,13 @@ bool AT_CellularContext::get_context() set_cid(cid); } } +#if defined __has_include +# if __has_include () + else { + cid_max = 0; + } +# endif +#endif } } @@ -432,6 +471,35 @@ bool AT_CellularContext::set_new_context(int cid) return success; } +void AT_CellularContext::enable_access_technology() +{ + switch (_rat) + { + case CATM1: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.cmd_start_stop("^SCFG", "=","%s%d", "Radio/Band/CatM",80000); + _at.resp_start("^SCFG"); + _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); + _at.resp_start("^SCFG"); + break; + + case CATNB: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.cmd_start_stop("^SCFG", "=","%s%d", "Radio/Band/CatNB",80000); + _at.resp_start("^SCFG"); + _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); + _at.resp_start("^SCFG"); + break; + + default: + break; + } + + _at.cmd_start_stop("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); + _at.resp_start("^SCFG"); + +} + nsapi_error_t AT_CellularContext::do_activate_context() { if (_nonip_req && _cp_in_use) { diff --git a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp index e3fd5b551a3..3ca0f3fc37d 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp @@ -414,7 +414,8 @@ nsapi_error_t AT_CellularDevice::init() _at.flush(); _at.at_cmd_discard("E0", ""); if (_at.get_last_error() == NSAPI_ERROR_OK) { - _at.at_cmd_discard("+CMEE", "=1"); + //Enable verbose error messages + _at.at_cmd_discard("+CMEE", "=2"); _at.at_cmd_discard("+CFUN", "=1"); if (_at.get_last_error() == NSAPI_ERROR_OK) { break; diff --git a/connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp b/connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp index 0afbf88e4a1..cf6781bf434 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp @@ -205,6 +205,7 @@ nsapi_error_t AT_CellularNetwork::get_network_registering_mode(NWRegisteringMode if (error == NSAPI_ERROR_OK) { mode = (NWRegisteringMode)ret; } + return error; } @@ -219,6 +220,7 @@ nsapi_error_t AT_CellularNetwork::set_registration(const char *plmn) return NSAPI_ERROR_DEVICE_ERROR; } if (mode != NWModeAutomatic) { + //Force operator registration return _at.at_cmd_discard("+COPS", "=0"); } return NSAPI_ERROR_OK; diff --git a/connectivity/cellular/source/framework/device/ATHandler.cpp b/connectivity/cellular/source/framework/device/ATHandler.cpp index 034d586a142..f305fd8af58 100644 --- a/connectivity/cellular/source/framework/device/ATHandler.cpp +++ b/connectivity/cellular/source/framework/device/ATHandler.cpp @@ -46,7 +46,7 @@ using namespace std::chrono_literals; #define PROCESS_URC_TIME 20ms // Suppress logging of very big packet payloads, maxlen is approximate due to write/read are cached -#define DEBUG_MAXLEN 60 +#define DEBUG_MAXLEN 120 #define DEBUG_END_MARK "..\r" const char *mbed::OK = "OK\r\n"; @@ -101,7 +101,8 @@ ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, mbed::chrono::millisecon _cmd_start(false), _use_delimiter(true), _start_time(), - _event_id(0) + _event_id(0), + _last_read_error(0) { clear_error(); @@ -677,6 +678,11 @@ ssize_t ATHandler::read_hex_string(char *buf, size_t size) return buf_idx; } +int32_t ATHandler::get_last_read_error() +{ + return (int32_t) _last_read_error; +} + int32_t ATHandler::read_int() { if (!ok_to_proceed() || !_stop_tag || _stop_tag->found) { @@ -691,9 +697,11 @@ int32_t ATHandler::read_int() errno = 0; long result = std::strtol(buff, NULL, 10); if ((result == LONG_MIN || result == LONG_MAX) && errno == ERANGE) { + _last_read_error = result; return -1; // overflow/underflow } if (result < 0) { + _last_read_error = result; return -1; // negative values are unsupported } if (*buff == '\0') { diff --git a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp index 44d67b729a8..35b16839d36 100644 --- a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +++ b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp @@ -28,7 +28,7 @@ using namespace std::chrono_literals; // timeout to wait for AT responses #define TIMEOUT_POWER_ON 1s -#define TIMEOUT_SIM_PIN 1s +#define TIMEOUT_SIM_PIN 10s #define TIMEOUT_NETWORK 10s /** CellularStateMachine does connecting up to packet service attach, and * after that it's up to CellularContext::connect() to connect to PDN. @@ -471,7 +471,13 @@ void CellularStateMachine::state_registering() _cb_data.error = NSAPI_ERROR_OK; send_event_cb(_current_event); // we are already registered, go to attach +#if defined __has_include +# if __has_include () +# else + //This state is not needed for Gemalto TX62-W module enter_to_state(STATE_ATTACHING_NETWORK); +# endif +#endif } else { tr_info("Network registration (timeout %d ms)", _state_timeout_registration.count()); change_timeout(_state_timeout_registration); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index 402e56a52f8..6e062039d46 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -70,6 +70,8 @@ nsapi_error_t GEMALTO_CINTERION::init() init_module_ems31(); } else if (memcmp(model, "EHS5-E", sizeof("EHS5-E") - 1) == 0) { init_module_ehs5e(); + } else if (memcmp(model, "TX62", sizeof("TX62") - 1) == 0) { + init_module_tx62(); } else { tr_error("Cinterion model unsupported %s", model); return NSAPI_ERROR_UNSUPPORTED; @@ -86,6 +88,35 @@ GEMALTO_CINTERION::Module GEMALTO_CINTERION::get_module() return _module; } +void GEMALTO_CINTERION::init_module_tx62() +{ + // TX-62 + static const intptr_t cellular_properties[AT_CellularDevice::PROPERTY_MAX] = { + AT_CellularNetwork::RegistrationModeLAC,// C_EREG + AT_CellularNetwork::RegistrationModeDisable, // C_GREG + AT_CellularNetwork::RegistrationModeDisable, // C_REG + 0, // AT_CGSN_WITH_TYPE + 0, // AT_CGDATA + 1, // AT_CGAUTH + 1, // AT_CNMI + 1, // AT_CSMP + 1, // AT_CMGF + 0, // AT_CSDH + 1, // PROPERTY_IPV4_STACK + 0, // PROPERTY_IPV6_STACK + 0, // PROPERTY_IPV4V6_STACK + 0, // PROPERTY_NON_IP_PDP_TYPE + 0, // PROPERTY_AT_CGEREP + 0, // PROPERTY_AT_COPS_FALLBACK_AUTO + 7, // PROPERTY_SOCKET_COUNT + 1, // PROPERTY_IP_TCP + 1, // PROPERTY_IP_UDP + 100, // PROPERTY_AT_SEND_DELAY + }; + set_cellular_properties(cellular_properties); + _module = ModuleTX62; +} + void GEMALTO_CINTERION::init_module_bgs2() { // BGS2-W_ATC_V00.100 diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h index ca2d6f542ab..73cb7dc67c5 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h @@ -44,6 +44,7 @@ class GEMALTO_CINTERION : public AT_CellularDevice { ModuleBGS2, ModuleEMS31, ModuleEHS5E, + ModuleTX62, }; static Module get_module(); @@ -60,6 +61,7 @@ class GEMALTO_CINTERION : public AT_CellularDevice { void init_module_els61(); void init_module_ems31(); void init_module_ehs5e(); + void init_module_tx62(); }; } // namespace mbed diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 38a5ba48196..ee0a56e57a1 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -30,6 +30,26 @@ GEMALTO_CINTERION_CellularContext::~GEMALTO_CINTERION_CellularContext() { } + +nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() +{ + // if user has defined user name and password we need to call CGAUTH before activating or modifying context + if (_pwd && _uname) { + if (!get_device()->get_property(AT_CellularDevice::PROPERTY_AT_CGAUTH)) { + return NSAPI_ERROR_UNSUPPORTED; + } + + _at.at_cmd_discard("^SGAUTH", "=", "%d%d%s%s", _cid, _authentication_type, _uname, _pwd); + + if (_at.get_last_error() != NSAPI_ERROR_OK) { + return NSAPI_ERROR_AUTH_FAILURE; + } + } + + return NSAPI_ERROR_OK; +} + + #if !NSAPI_PPP_AVAILABLE NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h index 86209eda599..da6e7676d69 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h @@ -30,6 +30,7 @@ class GEMALTO_CINTERION_CellularContext: public AT_CellularContext { #if !NSAPI_PPP_AVAILABLE virtual NetworkStack *get_stack(); #endif // NSAPI_PPP_AVAILABLE + virtual nsapi_error_t do_user_authentication(); }; } /* namespace mbed */ diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 1353c300192..13c1a0b2faf 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -19,6 +19,7 @@ #include "GEMALTO_CINTERION_CellularStack.h" #include "GEMALTO_CINTERION.h" #include "CellularLog.h" +#include "rtos.h" using namespace std::chrono_literals; @@ -151,6 +152,38 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_close_impl(int sock_id) return _at.get_last_error(); } +#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES +nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, SocketAddress *address, + nsapi_version_t version, const char *interface_name) +{ + (void) interface_name; + MBED_ASSERT(host); + MBED_ASSERT(address); + + _at.lock(); + + if (_dns_callback) { + _at.unlock(); + return NSAPI_ERROR_BUSY; + } + + if (!address->set_ip_address(host)) { + //_at.set_at_timeout(1min); + _at.cmd_start_stop("^SISX" , "=" , "%s%d%s", "HostByName" , _cid, host); + _at.resp_start("^SISX: \"HostByName\","); + char ipAddress[NSAPI_IP_SIZE]; + _at.read_string(ipAddress, sizeof(ipAddress)); + _at.restore_at_timeout(); + if (!address->set_ip_address(ipAddress)) { + _at.unlock(); + return NSAPI_ERROR_DNS_FAILURE; + } + } + + return _at.unlock_return_error(); +} +#endif + nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_open_defer(CellularSocket *socket, const SocketAddress *address) { int retry_open = 1; @@ -159,6 +192,11 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_open_defer(CellularSocket int internet_service_id = find_socket_index(socket); bool foundSrvType = false; bool foundConIdType = false; + + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62) { + _at.cmd_start_stop("^SICA", "=", "%d%d", 1, _cid); + } + _at.cmd_start_stop("^SISS", "?"); _at.resp_start("^SISS:"); /* @@ -396,6 +434,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell _at.cmd_start_stop("^SISR", "=", "%d%d", socket->id, size); sisr_retry: + socket->pending_bytes = 1; _at.resp_start("^SISR:"); if (!_at.info_resp()) { tr_error("Socket %d not responding", socket->id); @@ -421,6 +460,11 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell return NSAPI_ERROR_WOULD_BLOCK; } if (len == -1) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62 && _at.get_last_read_error() == -2) { + tr_error("Socket %d recvfrom finished!", socket->id); + socket->pending_bytes = 0; + return NSAPI_ERROR_OK; + } tr_error("Socket %d recvfrom failed!", socket->id); return NSAPI_ERROR_DEVICE_ERROR; } @@ -486,6 +530,12 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::create_connection_profile(int con return NSAPI_ERROR_OK; } + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62) { + _at.cmd_start_stop("^SICA", "=", "%d%d", 1, _cid); + tr_debug("Cinterion profile %d, %s (err %d)", connection_profile_id, (_stack_type == IPV4_STACK) ? "IPv4" : "IPv6", _at.get_last_error()); + return _at.get_last_error(); + } + char conParamType[sizeof("GPRS0") + 1]; std::sprintf(conParamType, "GPRS%d", (_stack_type == IPV4_STACK) ? 0 : 6); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index 01c5b71c652..22711d2173b 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -48,6 +48,10 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address); +#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES + virtual nsapi_error_t gethostbyname(const char *host, SocketAddress *address, nsapi_version_t version, const char *interface_name); +#endif + private: // socket URC handlers as per Cinterion AT manuals void urc_sis(); @@ -67,6 +71,11 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { const char *_apn; const char *_user; const char *_password; + +#ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES + hostbyname_cb_t _dns_callback; + nsapi_version_t _dns_version; +#endif }; } // namespace mbed From 3a3429910d622b6e78e45f964388c33692949c8d Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 13 Jul 2021 13:16:06 +0200 Subject: [PATCH 091/227] Implement connect() and get_context() functions inside GEMALTO stack --- .../framework/AT/AT_CellularContext.cpp | 33 -------- .../GEMALTO_CINTERION_CellularContext.cpp | 82 +++++++++++++++++++ .../GEMALTO_CINTERION_CellularContext.h | 3 + 3 files changed, 85 insertions(+), 33 deletions(-) diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index b4678ff0817..620af5ac765 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -269,26 +269,6 @@ nsapi_error_t AT_CellularContext::connect(const char *sim_pin, const char *apn, set_sim_pin(sim_pin); set_credentials(apn, uname, pwd); -#if defined __has_include -# if __has_include () - set_device_ready(); - - _at.lock(); - bool valid_context = get_context(); - _at.unlock(); - - if(!valid_context) { - set_new_context(_cid); - } - - do_user_authentication(); - - enable_access_technology(); - - do_connect(); -# endif -#endif - return connect(); } @@ -378,13 +358,7 @@ bool AT_CellularContext::get_context() int pdp_type_len = _at.read_string(pdp_type_from_context, sizeof(pdp_type_from_context)); if (pdp_type_len > 0) { apn_len = _at.read_string(apn, sizeof(apn)); -#if defined __has_include -# if __has_include () - if (apn_len > 0) { -# else if (apn_len >= 0) { -# endif -#endif if (_apn && (strcmp(apn, _apn) != 0)) { tr_debug("CID %d APN \"%s\"", cid, apn); continue; @@ -402,13 +376,6 @@ bool AT_CellularContext::get_context() set_cid(cid); } } -#if defined __has_include -# if __has_include () - else { - cid_max = 0; - } -# endif -#endif } } diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index ee0a56e57a1..8f04e1274ae 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -30,6 +30,88 @@ GEMALTO_CINTERION_CellularContext::~GEMALTO_CINTERION_CellularContext() { } +nsapi_error_t GEMALTO_CINTERION_CellularContext::connect(const char *sim_pin, const char *apn, const char *uname, + const char *pwd) +{ + set_sim_pin(sim_pin); + set_credentials(apn, uname, pwd); + + set_device_ready(); + + _at.lock(); + bool valid_context = get_context(); + _at.unlock(); + + if(!valid_context) { + set_new_context(_cid); + } + + do_user_authentication(); + + enable_access_technology(); + + return AT_CellularContext::connect(); +} + +bool GEMALTO_CINTERION_CellularContext::get_context() +{ + _at.cmd_start_stop("+CGDCONT", "?"); + _at.resp_start("+CGDCONT:"); + set_cid(-1); + int cid_max = 0; // needed when creating new context + char apn[MAX_ACCESSPOINT_NAME_LENGTH]; + int apn_len = 0; + + while (_at.info_resp()) { + int cid = _at.read_int(); + if (cid > cid_max) { + cid_max = cid; + } + char pdp_type_from_context[10]; + int pdp_type_len = _at.read_string(pdp_type_from_context, sizeof(pdp_type_from_context)); + if (pdp_type_len > 0) { + apn_len = _at.read_string(apn, sizeof(apn)); + if (apn_len > 0) { + if (_apn && (strcmp(apn, _apn) != 0)) { + tr_debug("CID %d APN \"%s\"", cid, apn); + continue; + } + + // APN matched -> Check PDP type + pdp_type_t pdp_type = string_to_pdp_type(pdp_type_from_context); + tr_debug("CID %d APN \"%s\" pdp_type %u", cid, apn, pdp_type); + + // Accept exact matching PDP context type or dual PDP context for modems that support both IPv4 and IPv6 stacks + if (get_device()->get_property(pdp_type_t_to_cellular_property(pdp_type)) || + ((pdp_type == IPV4V6_PDP_TYPE && (get_device()->get_property(AT_CellularDevice::PROPERTY_IPV4_PDP_TYPE) && + get_device()->get_property(AT_CellularDevice::PROPERTY_IPV6_PDP_TYPE))) && !_nonip_req)) { + _pdp_type = pdp_type; + set_cid(cid); + } + } + else { + cid_max = 0; + } + } + } + + _at.resp_stop(); + if (_cid == -1) { // no suitable context was found so create a new one + if (!set_new_context(cid_max + 1)) { + return false; + } + } + + // save the apn + if (apn_len > 0 && !_apn) { + memcpy(_found_apn, apn, apn_len + 1); + } + + tr_info("Found PDP context %d", _cid); + + return true; +} + nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h index da6e7676d69..0645b2b87ce 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h @@ -25,6 +25,9 @@ class GEMALTO_CINTERION_CellularContext: public AT_CellularContext { public: GEMALTO_CINTERION_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false); virtual ~GEMALTO_CINTERION_CellularContext(); + virtual nsapi_error_t connect(const char *sim_pin, const char *apn = 0, const char *uname = 0, + const char *pwd = 0); + virtual bool get_context(); protected: #if !NSAPI_PPP_AVAILABLE From 25472ac7921e3c0159073edb3efde27391f14c0b Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 13 Jul 2021 13:16:49 +0200 Subject: [PATCH 092/227] Make set_cid() protected to call it from GEMALTO stack --- .../cellular/include/cellular/framework/AT/AT_CellularContext.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index 19099c0e083..0eb83531b06 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -109,6 +109,7 @@ class AT_CellularContext : public CellularContext { */ virtual const char *get_nonip_context_type_str(); virtual void enable_access_technology(); + virtual void set_cid(int cid); private: #if NSAPI_PPP_AVAILABLE @@ -125,7 +126,6 @@ class AT_CellularContext : public CellularContext { nsapi_error_t check_operation(nsapi_error_t err, ContextOperation op); void ciot_opt_cb(mbed::CellularNetwork::CIoT_Supported_Opt ciot_opt); virtual void do_connect_with_retry(); - void set_cid(int cid); private: ContextOperation _current_op; From b1234223bf7f1d63f53eced12dd1903ba32629c7 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 13 Jul 2021 18:17:13 +0200 Subject: [PATCH 093/227] Implement GEMALTO subclass of CellularNetwork --- .../framework/device/CellularStateMachine.cpp | 6 ---- .../GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 6 ++++ .../GEMALTO/CINTERION/GEMALTO_CINTERION.h | 1 + .../GEMALTO_CINTERION_CellularNetwork.cpp | 34 ++++++++++++++++++ .../GEMALTO_CINTERION_CellularNetwork.h | 35 +++++++++++++++++++ 5 files changed, 76 insertions(+), 6 deletions(-) create mode 100644 connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp create mode 100644 connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h diff --git a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp index 35b16839d36..0a452eacb3a 100644 --- a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +++ b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp @@ -471,13 +471,7 @@ void CellularStateMachine::state_registering() _cb_data.error = NSAPI_ERROR_OK; send_event_cb(_current_event); // we are already registered, go to attach -#if defined __has_include -# if __has_include () -# else - //This state is not needed for Gemalto TX62-W module enter_to_state(STATE_ATTACHING_NETWORK); -# endif -#endif } else { tr_info("Network registration (timeout %d ms)", _state_timeout_registration.count()); change_timeout(_state_timeout_registration); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index 6e062039d46..f8f892fccd1 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -17,6 +17,7 @@ #include "GEMALTO_CINTERION_CellularContext.h" #include "GEMALTO_CINTERION_CellularInformation.h" +#include "GEMALTO_CINTERION_CellularNetwork.h" #include "GEMALTO_CINTERION.h" #include "AT_CellularNetwork.h" #include "CellularLog.h" @@ -43,6 +44,11 @@ AT_CellularInformation *GEMALTO_CINTERION::open_information_impl(ATHandler &at) return AT_CellularDevice::open_information_impl(at); } +AT_CellularNetwork *GEMALTO_CINTERION::open_network_impl(ATHandler &at) +{ + return new GEMALTO_CINTERION_CellularNetwork(at, *this); +} + nsapi_error_t GEMALTO_CINTERION::init() { nsapi_error_t err = AT_CellularDevice::init(); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h index 73cb7dc67c5..21d5888383d 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.h @@ -51,6 +51,7 @@ class GEMALTO_CINTERION : public AT_CellularDevice { protected: // AT_CellularDevice virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false); virtual AT_CellularInformation *open_information_impl(ATHandler &at); + virtual AT_CellularNetwork *open_network_impl(ATHandler &at); protected: virtual nsapi_error_t init(); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp new file mode 100644 index 00000000000..37ca733b6e0 --- /dev/null +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "GEMALTO_CINTERION_CellularNetwork.h" + +using namespace mbed; + +GEMALTO_CINTERION_CellularNetwork::GEMALTO_CINTERION_CellularNetwork(ATHandler &at, AT_CellularDevice &device) : AT_CellularNetwork(at, device) +{ +} + +GEMALTO_CINTERION_CellularNetwork::~GEMALTO_CINTERION_CellularNetwork() +{ +} + +nsapi_error_t GEMALTO_CINTERION_CellularNetwork::set_attach() +{ + return NSAPI_ERROR_OK; +} + + /* namespace mbed */ diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h new file mode 100644 index 00000000000..8d5f49cf5ae --- /dev/null +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef GEMALTO_CINTERION_CELLULARNETWORK_H_ +#define GEMALTO_CINTERION_CELLULARNETWORK_H_ + +#include "AT_CellularNetwork.h" + +namespace mbed { + +class GEMALTO_CINTERION_CellularNetwork: public AT_CellularNetwork { +public: + GEMALTO_CINTERION_CellularNetwork(ATHandler &at, AT_CellularDevice &device); + virtual ~GEMALTO_CINTERION_CellularNetwork(); + virtual nsapi_error_t set_attach(); + +protected: +}; + +} /* namespace mbed */ + +#endif // GEMALTO_CINTERION_CELLULARNETWORK_H_ From 6a49ec933d4b87d6ce1a81b99d7137f0edeb978f Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 14 Jul 2021 10:25:40 +0200 Subject: [PATCH 094/227] Handle missing IP address resolution --- .../GEMALTO_CINTERION_CellularStack.cpp | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 13c1a0b2faf..9eb3e27b399 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -172,11 +172,19 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S _at.cmd_start_stop("^SISX" , "=" , "%s%d%s", "HostByName" , _cid, host); _at.resp_start("^SISX: \"HostByName\","); char ipAddress[NSAPI_IP_SIZE]; - _at.read_string(ipAddress, sizeof(ipAddress)); - _at.restore_at_timeout(); - if (!address->set_ip_address(ipAddress)) { - _at.unlock(); - return NSAPI_ERROR_DNS_FAILURE; + int size = _at.read_string(ipAddress, sizeof(ipAddress)); + if (size) { + //Valid string received + tr_info("Read %d bytes. Valid string: %s\n", size, ipAddress); + _at.restore_at_timeout(); + if (!address->set_ip_address(ipAddress)) { + _at.unlock(); + return NSAPI_ERROR_DNS_FAILURE; + } + } else { + //Null string received + tr_info("Read %d bytes. Null string\n", size); + return NSAPI_ERROR_NO_ADDRESS; } } From 36b0ec6936af713c9df91f0cc685815c0c8ebb02 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 14 Jul 2021 12:54:52 +0200 Subject: [PATCH 095/227] Check if username and password are empty strings --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 8f04e1274ae..4aa7f188ea5 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -116,7 +116,7 @@ bool GEMALTO_CINTERION_CellularContext::get_context() nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() { // if user has defined user name and password we need to call CGAUTH before activating or modifying context - if (_pwd && _uname) { + if ((strcmp(_pwd, "") != 0) && (strcmp(_uname, "") != 0)) { if (!get_device()->get_property(AT_CellularDevice::PROPERTY_AT_CGAUTH)) { return NSAPI_ERROR_UNSUPPORTED; } @@ -126,6 +126,8 @@ nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() if (_at.get_last_error() != NSAPI_ERROR_OK) { return NSAPI_ERROR_AUTH_FAILURE; } + } else { + tr_info("Empty pwd and username fields: no need for authentication\n"); } return NSAPI_ERROR_OK; From bd6e7456beb92b44efa228239cead7c5d16654ab Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 19 Jul 2021 14:42:09 +0200 Subject: [PATCH 096/227] Overwrite old context with new one if they are different --- .../CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 4aa7f188ea5..7ee2c8e53c7 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -71,12 +71,7 @@ bool GEMALTO_CINTERION_CellularContext::get_context() int pdp_type_len = _at.read_string(pdp_type_from_context, sizeof(pdp_type_from_context)); if (pdp_type_len > 0) { apn_len = _at.read_string(apn, sizeof(apn)); - if (apn_len > 0) { - if (_apn && (strcmp(apn, _apn) != 0)) { - tr_debug("CID %d APN \"%s\"", cid, apn); - continue; - } - + if (apn_len > 0 && (strcmp(apn, _apn) == 0)) { // APN matched -> Check PDP type pdp_type_t pdp_type = string_to_pdp_type(pdp_type_from_context); tr_debug("CID %d APN \"%s\" pdp_type %u", cid, apn, pdp_type); From bf053d6dc247f653662fe3728f524a7c48afd24f Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 20 Jul 2021 10:40:12 +0200 Subject: [PATCH 097/227] Fix recv implementation --- .../CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 9eb3e27b399..034011d2d2d 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -105,9 +105,9 @@ void GEMALTO_CINTERION_CellularStack::sisr_urc_handler(int sock_id, int urc_code { CellularSocket *sock = find_socket(sock_id); if (sock) { - if (urc_code == 1) { // data available + if (urc_code > 0) { // data available if (sock->_cb) { - sock->pending_bytes = 1; + sock->pending_bytes = urc_code; sock->_cb(sock->_data); } } @@ -442,7 +442,6 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell _at.cmd_start_stop("^SISR", "=", "%d%d", socket->id, size); sisr_retry: - socket->pending_bytes = 1; _at.resp_start("^SISR:"); if (!_at.info_resp()) { tr_error("Socket %d not responding", socket->id); @@ -476,13 +475,9 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell tr_error("Socket %d recvfrom failed!", socket->id); return NSAPI_ERROR_DEVICE_ERROR; } - socket->pending_bytes = 0; + socket->pending_bytes = 1; if (len >= (nsapi_size_or_error_t)size) { len = (nsapi_size_or_error_t)size; - int remain_len = _at.read_int(); - if (remain_len > 0) { - socket->pending_bytes = 1; - } } // UDP Udp_RemClient @@ -525,6 +520,10 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell nsapi_size_or_error_t recv_len = _at.read_bytes((uint8_t *)buffer, len); + if (recv_len < len) { + goto sisr_retry; + } + _at.resp_stop(); return (_at.get_last_error() == NSAPI_ERROR_OK) ? (recv_len ? recv_len : NSAPI_ERROR_WOULD_BLOCK) : NSAPI_ERROR_DEVICE_ERROR; From d24baa365fc9bcf0472c85f0a7b13e356ed5b4b1 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 20 Jul 2021 11:48:06 +0200 Subject: [PATCH 098/227] Add time functions to Gemalto stack --- .../cellular/framework/API/CellularDevice.h | 6 + .../cellular/framework/AT/AT_CellularDevice.h | 7 + .../source/framework/AT/AT_CellularDevice.cpp | 151 ++++++++++++++++++ .../GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 2 +- 4 files changed, 165 insertions(+), 1 deletion(-) diff --git a/connectivity/cellular/include/cellular/framework/API/CellularDevice.h b/connectivity/cellular/include/cellular/framework/API/CellularDevice.h index 236f2d329a1..a5fa3b68fd5 100644 --- a/connectivity/cellular/include/cellular/framework/API/CellularDevice.h +++ b/connectivity/cellular/include/cellular/framework/API/CellularDevice.h @@ -342,6 +342,12 @@ class CellularDevice { */ virtual void set_timeout(int timeout) = 0; + virtual unsigned long get_time() = 0; + + virtual unsigned long get_local_time() = 0; + + virtual bool set_time(unsigned long const epoch, int const timezone = 0) = 0; + public: //Common functions diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h index 07a5f90dad2..4600e9cc778 100755 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h @@ -98,6 +98,12 @@ class AT_CellularDevice : public CellularDevice { virtual void set_timeout(int timeout); + virtual unsigned long get_time(); + + virtual unsigned long get_local_time(); + + virtual bool set_time(unsigned long const epoch, int const timezone = 0); + virtual void modem_debug_on(bool on); virtual nsapi_error_t init(); @@ -184,6 +190,7 @@ class AT_CellularDevice : public CellularDevice { private: void urc_nw_deact(); void urc_pdn_deact(); + nsapi_error_t set_authomatic_time_zone_update(); protected: ATHandler _at; diff --git a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp index 3ca0f3fc37d..6b9fb462d33 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp @@ -144,6 +144,11 @@ void AT_CellularDevice::urc_pdn_deact() send_disconnect_to_context(cid); } +nsapi_error_t AT_CellularDevice::set_authomatic_time_zone_update() +{ + return _at.at_cmd_discard("+CTZU", "=", "%d", 1); +} + void AT_CellularDevice::send_disconnect_to_context(int cid) { tr_debug("send_disconnect_to_context, cid: %d", cid); @@ -398,6 +403,152 @@ void AT_CellularDevice::set_timeout(int timeout) } } +unsigned long AT_CellularDevice::get_time() +{ + tr_info("AT_CellularDevice::get_time\n"); + + struct tm now; + + //Enable authomatic time zone update: + set_authomatic_time_zone_update(); + + _at.lock(); + + //"+CCLK: \"%y/%m/%d,%H:%M:%S+ZZ" + _at.cmd_start_stop("+CCLK", "?"); + _at.resp_start("+CCLK:"); + + char time_str[50]; + int time_len = 0; + while (_at.info_resp()) { + int date_len = _at.read_string(time_str, sizeof(time_str)); + tr_debug("Read %d bytes for the date\n", date_len); + if (date_len > 0) { + char *ptr = time_str; + + now.tm_year = std::strtol(ptr, NULL, 10) + 100; // mktime starts from 1900 + ptr = ptr + 3; // Skip '/' + now.tm_mon = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip '/' + now.tm_mday = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip ',' + now.tm_hour = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip ':' + now.tm_min = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; + now.tm_sec = std::strtol(ptr, NULL, 10); + } + } + _at.resp_stop(); + + _at.unlock(); + + tr_debug("Year: %d, month: %d, day:%d, hour:%d, minute:%d, second:%d\n", now.tm_year, now.tm_mon, now.tm_mday, now.tm_hour, now.tm_min, now.tm_sec); + + // adjust for timezone offset which is +/- in 15 minute increments + long long result = mktime(&now); + time_t delta = ((time_str[18] - '0') * 10 + (time_str[19] - '0')) * (15 * 60); + + if (time_str[17] == '-') { + result = result + delta; + } else if (time_str[17] == '+') { + result = result - delta; + } + + return result; +} + +unsigned long AT_CellularDevice::get_local_time() +{ + tr_info("AT_CellularDevice::get_local_time\n"); + + struct tm now; + + _at.lock(); + + //"+CCLK: \"%y/%m/%d,%H:%M:%S" + _at.cmd_start_stop("+CCLK", "?"); + _at.resp_start("+CCLK:"); + + char time_str[50]; + int time_len = 0; + while (_at.info_resp()) { + int date_len = _at.read_string(time_str, sizeof(time_str)); + tr_debug("Read %d bytes for the date\n", date_len); + if (date_len > 0) { + char *ptr = time_str; + + now.tm_year = std::strtol(ptr, NULL, 10) + 100; // mktime starts from 1900 + ptr = ptr + 3; // Skip '/' + now.tm_mon = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip '/' + now.tm_mday = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip ',' + now.tm_hour = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; // Skip ':' + now.tm_min = std::strtol(ptr, NULL, 10); + ptr = ptr + 3; + now.tm_sec = std::strtol(ptr, NULL, 10); + } + } + _at.resp_stop(); + + _at.unlock(); + + tr_debug("Year: %d, month: %d, day:%d, hour:%d, minute:%d, second:%d\n", now.tm_year, now.tm_mon, now.tm_mday, now.tm_hour, now.tm_min, now.tm_sec); + + long long result = mktime(&now); + + return result; + +} + +bool AT_CellularDevice::set_time(unsigned long const epoch, int const timezone) + { + char time_buf[20]; + const uint8_t daysInMonth [] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30 }; + unsigned long unix_time = epoch - 946684800UL; /* Subtract seconds from 1970 to 2000 */ + + /* Convert unix_time from seconds to days */ + int days = unix_time / (24 * 3600); + int leap; + int year = 0; + while (1) { + leap = year % 4 == 0; + if (days < 365 + leap) { + break; + } + days -= 365 + leap; + year++; + } + + int month; + for (month = 1; month < 12; month++) { + uint8_t daysPerMonth = daysInMonth[month - 1]; + if (leap && month == 2) + daysPerMonth++; + if (days < daysPerMonth) { + break; + } + days -= daysPerMonth; + } + + int hours = (unix_time % 86400L) / 3600; + int minutes = (unix_time % 3600) / 60; + int seconds = unix_time % 60; + + tr_debug("Year: %d, month: %d, day:%d, hour:%d, minute:%d, second:%d\n", year, month, days, hours, minutes, seconds); + + sprintf(time_buf, "%02d/%02d/%02d,%02d:%02d:%02d+%02d", year, month, days, hours, minutes, seconds, timezone); + + _at.lock(); + _at.at_cmd_discard("+CCLK", "=", "%s", time_buf); + _at.unlock(); + + return true; + +} + void AT_CellularDevice::modem_debug_on(bool on) { _modem_debug_on = on; diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index f8f892fccd1..459bba8eb10 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -241,7 +241,7 @@ void GEMALTO_CINTERION::init_module_ehs5e() #if MBED_CONF_GEMALTO_CINTERION_PROVIDE_DEFAULT #include "drivers/BufferedSerial.h" -CellularDevice *CellularDevice::get_default_instance() +CellularDevice *GEMALTO_CINTERION::get_default_instance() { static BufferedSerial serial(MBED_CONF_GEMALTO_CINTERION_TX, MBED_CONF_GEMALTO_CINTERION_RX, MBED_CONF_GEMALTO_CINTERION_BAUDRATE); #if defined(MBED_CONF_GEMALTO_CINTERION_RTS) && defined(MBED_CONF_GEMALTO_CINTERION_CTS) From 9425b4cf5acccbd8f5152efd8e35fd6da1b3a41d Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 5 Aug 2021 15:10:54 +0200 Subject: [PATCH 099/227] AT_CellularStack: return NSAPI_ERROR_NO_CONNECTION on socket closed --- .../cellular/source/framework/AT/AT_CellularStack.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/connectivity/cellular/source/framework/AT/AT_CellularStack.cpp b/connectivity/cellular/source/framework/AT/AT_CellularStack.cpp index 961d101c9b5..ca7d2a786c2 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularStack.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularStack.cpp @@ -332,7 +332,7 @@ nsapi_size_or_error_t AT_CellularStack::socket_recvfrom(nsapi_socket_t handle, S if (socket->closed) { tr_info("recvfrom socket %d closed", socket->id); - return 0; + return NSAPI_ERROR_NO_CONNECTION; } nsapi_size_or_error_t ret_val = NSAPI_ERROR_OK; @@ -357,7 +357,7 @@ nsapi_size_or_error_t AT_CellularStack::socket_recvfrom(nsapi_socket_t handle, S if (socket->closed) { tr_info("recvfrom socket %d closed", socket->id); - return 0; + return NSAPI_ERROR_NO_CONNECTION; } if (ret_val >= 0) { From d74af6c60c8098de8a7839a2af09f0159f673ca5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 5 Aug 2021 15:13:58 +0200 Subject: [PATCH 100/227] SerialBase: implement sw flow control --- drivers/include/drivers/SerialBase.h | 9 ++++++++- drivers/source/SerialBase.cpp | 14 ++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/include/drivers/SerialBase.h b/drivers/include/drivers/SerialBase.h index 9288c271e15..7d8734c7afd 100644 --- a/drivers/include/drivers/SerialBase.h +++ b/drivers/include/drivers/SerialBase.h @@ -26,6 +26,9 @@ #include "platform/mbed_toolchain.h" #include "platform/NonCopyable.h" +#include "drivers/DigitalOut.h" +#include "drivers/DigitalIn.h" + #if DEVICE_SERIAL_ASYNCH #include "platform/CThunk.h" #include "hal/dma_api.h" @@ -71,7 +74,8 @@ class SerialBase : private NonCopyable { Disabled = 0, RTS, CTS, - RTSCTS + RTSCTS, + RTSCTS_SW }; /** Set the transmission format used by the serial port @@ -326,8 +330,11 @@ class SerialBase : private NonCopyable { Flow _flow_type = Disabled; PinName _flow1 = NC; PinName _flow2 = NC; + DigitalIn* _cts_pin; + DigitalOut* _rts_pin; const serial_fc_pinmap_t *_static_pinmap_fc = NULL; void (SerialBase::*_set_flow_control_sp_func)(Flow, const serial_fc_pinmap_t &) = NULL; + bool sw_flow_control = false; #endif #endif diff --git a/drivers/source/SerialBase.cpp b/drivers/source/SerialBase.cpp index 40bf7d0b618..7c21d12e9c4 100644 --- a/drivers/source/SerialBase.cpp +++ b/drivers/source/SerialBase.cpp @@ -71,6 +71,9 @@ int SerialBase::readable() { lock(); int ret = serial_readable(&_serial); + if (sw_flow_control == true && _rts_pin != nullptr) { + *_rts_pin = !!!ret; + } unlock(); return ret; } @@ -80,6 +83,9 @@ int SerialBase::writeable() { lock(); int ret = serial_writable(&_serial); + if (sw_flow_control) { + ret = ret & !(*_cts_pin); + } unlock(); return ret; } @@ -319,6 +325,14 @@ void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) serial_set_flow_control(&_serial, flow_type, flow1, flow2); break; + case RTSCTS_SW: + sw_flow_control = true; + if (_flow1 != NC) + _cts_pin = new DigitalIn(_flow1); + if (_flow2 != NC) + _rts_pin = new DigitalOut(_flow2, 0); + break; + default: break; } From 0b95b1902c27d6121dc33b9b2ff2df5946009fb5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 5 Aug 2021 15:14:13 +0200 Subject: [PATCH 101/227] GEMALTO: fix some corner cases --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 034011d2d2d..06952694e22 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -122,6 +122,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() _at.set_urc_handler("^SIS:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sis)); _at.set_urc_handler("^SISW:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisw)); _at.set_urc_handler("^SISR:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisr)); + _at.set_urc_handler("^SYSSTART", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisr)); } else { // recovery cleanup // close all Internet and connection profiles for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) { @@ -173,7 +174,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S _at.resp_start("^SISX: \"HostByName\","); char ipAddress[NSAPI_IP_SIZE]; int size = _at.read_string(ipAddress, sizeof(ipAddress)); - if (size) { + if (size > 0) { //Valid string received tr_info("Read %d bytes. Valid string: %s\n", size, ipAddress); _at.restore_at_timeout(); @@ -207,6 +208,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_open_defer(CellularSocket _at.cmd_start_stop("^SISS", "?"); _at.resp_start("^SISS:"); + /* * Profile is a list of tag-value map: * ^SISS: , , @@ -439,6 +441,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell size = UDP_PACKET_SIZE; } + tr_info("requesting %d bytes\n", size); _at.cmd_start_stop("^SISR", "=", "%d%d", socket->id, size); sisr_retry: @@ -475,7 +478,6 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell tr_error("Socket %d recvfrom failed!", socket->id); return NSAPI_ERROR_DEVICE_ERROR; } - socket->pending_bytes = 1; if (len >= (nsapi_size_or_error_t)size) { len = (nsapi_size_or_error_t)size; } From 44d77e3fcfa214163aebf738c2db8033294112bf Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 6 Aug 2021 10:28:50 +0200 Subject: [PATCH 102/227] Gemalto: properly handle ^SYSSTART URC --- .../CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 14 +++++++++++++- .../CINTERION/GEMALTO_CINTERION_CellularStack.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 06952694e22..147f5ffc156 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -101,6 +101,18 @@ void GEMALTO_CINTERION_CellularStack::urc_sisr() sisr_urc_handler(sock_id, urc_code); } +void GEMALTO_CINTERION_CellularStack::urc_sysstart() +{ + // close sockets if open + _at.lock(); + for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) { + _at.clear_error(); + socket_close_impl(i); + } + _at.clear_error(); + _at.unlock(); +} + void GEMALTO_CINTERION_CellularStack::sisr_urc_handler(int sock_id, int urc_code) { CellularSocket *sock = find_socket(sock_id); @@ -122,7 +134,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() _at.set_urc_handler("^SIS:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sis)); _at.set_urc_handler("^SISW:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisw)); _at.set_urc_handler("^SISR:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisr)); - _at.set_urc_handler("^SYSSTART", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisr)); + _at.set_urc_handler("^SYSSTART", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sysstart)); } else { // recovery cleanup // close all Internet and connection profiles for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index 22711d2173b..b0ae8d23e19 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -56,6 +56,7 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { // socket URC handlers as per Cinterion AT manuals void urc_sis(); void urc_sisw(); + void urc_sysstart(); void sisw_urc_handler(int sock_id, int urc_code); void urc_sisr(); void sisr_urc_handler(int sock_id, int urc_code); From 9c9b8b4277b7031a67d5f67e1a40c6c83457e240 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 6 Aug 2021 10:29:11 +0200 Subject: [PATCH 103/227] Gemalto: TX62: handle oob before closing the socket --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 147f5ffc156..94975e1b667 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -483,6 +483,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell } if (len == -1) { if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62 && _at.get_last_read_error() == -2) { + _at.process_oob(); tr_error("Socket %d recvfrom finished!", socket->id); socket->pending_bytes = 0; return NSAPI_ERROR_OK; From c88c2590a631f5a8f1dfc8e4b74f8c8da1b82315 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 11 Aug 2021 12:15:43 +0200 Subject: [PATCH 104/227] GEMALTO: implement GNSS --- .../GEMALTO_CINTERION_CellularStack.cpp | 36 +++++++++++++++++++ .../GEMALTO_CINTERION_CellularStack.h | 8 +++++ 2 files changed, 44 insertions(+) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 94975e1b667..917accc916c 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -126,6 +126,40 @@ void GEMALTO_CINTERION_CellularStack::sisr_urc_handler(int sock_id, int urc_code } } + +void GEMALTO_CINTERION_CellularStack::lock() { + _at.lock(); +} + +void GEMALTO_CINTERION_CellularStack::unlock() { + _at.unlock(); +} + +void GEMALTO_CINTERION_CellularStack::urc_gnss() { + printf("urc_gnss called\n"); + printf("%x\n", _gnss_cb); + + char gnss_string[50] = {'$', 'G'}; + if (_gnss_cb) { + _at.set_delimiter('\n'); + _at.read_string(&gnss_string[2], 48); + _at.set_default_delimiter(); + _gnss_cb(gnss_string); + } +} + +void GEMALTO_CINTERION_CellularStack::startGNSS(mbed::Callback gnss_cb) { + _at.lock(); + _gnss_cb = gnss_cb; + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine/StartMode", 0); + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 3); + //_at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Output", "off"); + _at.at_cmd_discard("^SGPSE", "=", "%s%s", "Nmea/Urc", "on"); + _at.clear_error(); + _at.unlock(); +} + + nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() { _at.lock(); @@ -135,6 +169,8 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() _at.set_urc_handler("^SISW:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisw)); _at.set_urc_handler("^SISR:", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sisr)); _at.set_urc_handler("^SYSSTART", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_sysstart)); + _at.set_urc_handler("^SGPSE", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_gnss)); + _at.set_urc_handler("$G", mbed::Callback(this, &GEMALTO_CINTERION_CellularStack::urc_gnss)); } else { // recovery cleanup // close all Internet and connection profiles for (int i = 0; i < _device.get_property(AT_CellularDevice::PROPERTY_SOCKET_COUNT); i++) { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index b0ae8d23e19..163fa3193fd 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -34,6 +34,10 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { */ nsapi_error_t socket_stack_init(); + void lock(); + void unlock(); + void startGNSS(mbed::Callback gnss_cb); + protected: virtual nsapi_error_t socket_close_impl(int sock_id); @@ -61,6 +65,8 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { void urc_sisr(); void sisr_urc_handler(int sock_id, int urc_code); + void urc_gnss(); + // sockets need a connection profile, one profile is enough to support single stack sockets nsapi_error_t create_connection_profile(int connection_profile_id); void close_connection_profile(int connection_profile_id); @@ -73,6 +79,8 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { const char *_user; const char *_password; + mbed::Callback _gnss_cb; + #ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES hostbyname_cb_t _dns_callback; nsapi_version_t _dns_version; From c17b33b8cea304e9aa153f0653dcee3ad97fb5e5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 11 Aug 2021 17:30:39 +0200 Subject: [PATCH 105/227] GEMALTO: TX62: tune AT configuration --- .../cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index 459bba8eb10..3e3bcd41219 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -103,21 +103,21 @@ void GEMALTO_CINTERION::init_module_tx62() AT_CellularNetwork::RegistrationModeDisable, // C_REG 0, // AT_CGSN_WITH_TYPE 0, // AT_CGDATA - 1, // AT_CGAUTH + 0, // AT_CGAUTH 1, // AT_CNMI 1, // AT_CSMP 1, // AT_CMGF - 0, // AT_CSDH + 1, // AT_CSDH 1, // PROPERTY_IPV4_STACK 0, // PROPERTY_IPV6_STACK 0, // PROPERTY_IPV4V6_STACK 0, // PROPERTY_NON_IP_PDP_TYPE - 0, // PROPERTY_AT_CGEREP - 0, // PROPERTY_AT_COPS_FALLBACK_AUTO + 1, // PROPERTY_AT_CGEREP + 1, // PROPERTY_AT_COPS_FALLBACK_AUTO 7, // PROPERTY_SOCKET_COUNT 1, // PROPERTY_IP_TCP 1, // PROPERTY_IP_UDP - 100, // PROPERTY_AT_SEND_DELAY + 0, // PROPERTY_AT_SEND_DELAY }; set_cellular_properties(cellular_properties); _module = ModuleTX62; From e1adbd34286f3da104d4d2fae2c6ff3be294a813 Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Tue, 7 Sep 2021 12:33:02 +0200 Subject: [PATCH 106/227] Add APIs to start and stop gnss functionality the usage of start and stop should allows for switching the usage of gnss with respect for lte gsm operations --- .../GEMALTO_CINTERION_CellularStack.cpp | 45 +++++++++++++++++-- .../GEMALTO_CINTERION_CellularStack.h | 6 ++- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 917accc916c..6961e40f38f 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -148,17 +148,54 @@ void GEMALTO_CINTERION_CellularStack::urc_gnss() { } } -void GEMALTO_CINTERION_CellularStack::startGNSS(mbed::Callback gnss_cb) { +void GEMALTO_CINTERION_CellularStack::beginGNSS(mbed::Callback gnss_cb) { _at.lock(); _gnss_cb = gnss_cb; _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine/StartMode", 0); - _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 3); - //_at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Output", "off"); - _at.at_cmd_discard("^SGPSE", "=", "%s%s", "Nmea/Urc", "on"); + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); + _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); _at.clear_error(); _at.unlock(); } +void GEMALTO_CINTERION_CellularStack::endGNSS() { + _at.lock(); + _gnss_cb = nullptr; + _at.clear_error(); + _at.unlock(); +} + +void GEMALTO_CINTERION_CellularStack::startGNSS() { + _at.lock(); + _engine = false; + _at.cmd_start_stop("^SGPSC", "=", "%s%d", "Engine", 3); + _at.resp_start("^SGPSC: \"Engine\","); + + char respEng[2]; + int resp_len = _at.read_string(respEng, sizeof(respEng)); + if (strcmp(respEng, "3") != 0) { + _engine = false; + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); + _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); + return; + } + _engine = true; + _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "on"); + _at.clear_error(); + _at.unlock(); +} + +void GEMALTO_CINTERION_CellularStack::stopGNSS() { + if(_engine) { + _at.lock(); + _gnss_cb = nullptr; + _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); + _at.clear_error(); + _at.unlock(); + _engine = false; + } +} nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index 163fa3193fd..ffaed501846 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -36,7 +36,10 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { void lock(); void unlock(); - void startGNSS(mbed::Callback gnss_cb); + void beginGNSS(mbed::Callback gnss_cb); + void endGNSS(); + void startGNSS(); + void stopGNSS(); protected: @@ -78,6 +81,7 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { const char *_apn; const char *_user; const char *_password; + bool _engine; mbed::Callback _gnss_cb; From 209cc34d77e8f7434358535ed78fd478127fac27 Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Mon, 13 Sep 2021 11:56:44 +0200 Subject: [PATCH 107/227] Added GNSS/Psm management and bug fixing Added GNSS psm management and removed callback pointer bug introduced in previous PR also set CGAUTH to 1in order to allows for context credential settings. --- .../GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 2 +- .../GEMALTO_CINTERION_CellularStack.cpp | 33 +++++++++++++------ .../GEMALTO_CINTERION_CellularStack.h | 4 ++- 3 files changed, 27 insertions(+), 12 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index 3e3bcd41219..c7790fe348c 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -103,7 +103,7 @@ void GEMALTO_CINTERION::init_module_tx62() AT_CellularNetwork::RegistrationModeDisable, // C_REG 0, // AT_CGSN_WITH_TYPE 0, // AT_CGDATA - 0, // AT_CGAUTH + 1, // AT_CGAUTH 1, // AT_CNMI 1, // AT_CSMP 1, // AT_CMGF diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 6961e40f38f..967d9628b08 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -136,13 +136,10 @@ void GEMALTO_CINTERION_CellularStack::unlock() { } void GEMALTO_CINTERION_CellularStack::urc_gnss() { - printf("urc_gnss called\n"); - printf("%x\n", _gnss_cb); - - char gnss_string[50] = {'$', 'G'}; + char gnss_string[100] = {'$', 'G'}; if (_gnss_cb) { _at.set_delimiter('\n'); - _at.read_string(&gnss_string[2], 48); + _at.read_string(&gnss_string[2], 98); _at.set_default_delimiter(); _gnss_cb(gnss_string); } @@ -165,7 +162,7 @@ void GEMALTO_CINTERION_CellularStack::endGNSS() { _at.unlock(); } -void GEMALTO_CINTERION_CellularStack::startGNSS() { +int GEMALTO_CINTERION_CellularStack::startGNSS() { _at.lock(); _engine = false; _at.cmd_start_stop("^SGPSC", "=", "%s%d", "Engine", 3); @@ -177,18 +174,18 @@ void GEMALTO_CINTERION_CellularStack::startGNSS() { _engine = false; _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); - return; + return 0; } _engine = true; _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "on"); _at.clear_error(); _at.unlock(); + return 1; } void GEMALTO_CINTERION_CellularStack::stopGNSS() { if(_engine) { _at.lock(); - _gnss_cb = nullptr; _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); _at.clear_error(); @@ -197,6 +194,24 @@ void GEMALTO_CINTERION_CellularStack::stopGNSS() { } } +void GEMALTO_CINTERION_CellularStack::PSMEnable() { + if(_engine) { + _at.lock(); + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Power/Psm", 1); + _at.clear_error(); + _at.unlock(); + } +} + +void GEMALTO_CINTERION_CellularStack::PSMDisable() { + if(_engine) { + _at.lock(); + _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Power/Psm", 0); + _at.clear_error(); + _at.unlock(); + } +} + nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_stack_init() { _at.lock(); @@ -231,8 +246,6 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_close_impl(int sock_id) _at.clear_error(); // clear SISS even though SISC fails - _at.at_cmd_discard("^SISS", "=", "%d%s%s", sock_id, "srvType", "none"); - _at.restore_at_timeout(); return _at.get_last_error(); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index ffaed501846..37eee5858a0 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -38,8 +38,10 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { void unlock(); void beginGNSS(mbed::Callback gnss_cb); void endGNSS(); - void startGNSS(); + int startGNSS(); void stopGNSS(); + void PSMEnable(); + void PSMDisable(); protected: From 448bb28235eaa0e21e72392bcce130e2cf6941c7 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 25 Nov 2021 14:55:22 +0100 Subject: [PATCH 108/227] Implement LNA_ENABLE for Thales rev3 --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 967d9628b08..9f111d7da0d 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -151,12 +151,15 @@ void GEMALTO_CINTERION_CellularStack::beginGNSS(mbed::Callback gnss _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine/StartMode", 0); _at.at_cmd_discard("^SGPSC", "=", "%s%d", "Engine", 0); _at.at_cmd_discard("^SGPSC", "=", "%s%s", "Nmea/Urc", "off"); + _at.at_cmd_discard("^SPIO", "=", "%d", 1); + _at.at_cmd_discard("^SCPIN", "=", "%d%d%d%d", 1, 7, 1, 0); _at.clear_error(); _at.unlock(); } void GEMALTO_CINTERION_CellularStack::endGNSS() { _at.lock(); + _at.at_cmd_discard("^SSIO", "=", "%d%d", 7, 0); _gnss_cb = nullptr; _at.clear_error(); _at.unlock(); @@ -165,6 +168,7 @@ void GEMALTO_CINTERION_CellularStack::endGNSS() { int GEMALTO_CINTERION_CellularStack::startGNSS() { _at.lock(); _engine = false; + _at.at_cmd_discard("^SSIO", "=", "%d%d", 7, 1); _at.cmd_start_stop("^SGPSC", "=", "%s%d", "Engine", 3); _at.resp_start("^SGPSC: \"Engine\","); From ee569bd3f2407f7c919a568564f899b921156ca7 Mon Sep 17 00:00:00 2001 From: Riccardo Rizzo Date: Fri, 26 Nov 2021 14:46:40 +0100 Subject: [PATCH 109/227] cmux support - CMUX.h handle ongoig packet from all serial(virtual, real) and route to the correct owner, when also the cmux enable is ready is supposed that this class should also handle and frammentate the packet to be routed in the properly channel, actually should work as a big serialpassthrough because tested over a unique channel(GSMpty.s0) - PTYSerial.h virtual serial buffer - PTYclass.h take two serial and set s1.in to s0.out and viceversa used in CMUXManager.cpp, in mbed-core, during init time to set properly the interfaced used by all actors - GSM.h and GPS.h, in mbed-core, reworked in order to: 1. take the serial as input 2. in begin() method use the serial propagated by input in order to create a device -> get_default_istance() than set this device for cinterion stack usage(GSMPTY.s1 or GPSPTY.s1) - CMUXManager.cpp set the thread that should be used for manage the comunication between the virtuar serial and hw serial provide get method to access the PTYclass serials for stack side https://github.com/Rocketct/ArduinoCore-mbed/tree/cmux_core_211126 modified cellular cstate machine to take enable CMUX when required. added support API for enable and disable CMUX from cellular device. added callback logic to enable virtual channels. --- .../cellular/framework/API/CellularDevice.h | 9 ++++++ .../cellular/framework/AT/AT_CellularDevice.h | 9 ++++++ .../source/framework/AT/AT_CellularDevice.cpp | 31 +++++++++++++++++++ .../framework/device/CellularStateMachine.cpp | 6 ++++ .../GEMALTO/CINTERION/GEMALTO_CINTERION.cpp | 7 +++-- .../GEMALTO_CINTERION_CellularNetwork.cpp | 5 +++ .../GEMALTO_CINTERION_CellularNetwork.h | 2 ++ .../GEMALTO_CINTERION_CellularStack.cpp | 9 +++--- .../GEMALTO_CINTERION_CellularStack.h | 1 + 9 files changed, 73 insertions(+), 6 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/API/CellularDevice.h b/connectivity/cellular/include/cellular/framework/API/CellularDevice.h index a5fa3b68fd5..0c8d1a2db2c 100644 --- a/connectivity/cellular/include/cellular/framework/API/CellularDevice.h +++ b/connectivity/cellular/include/cellular/framework/API/CellularDevice.h @@ -73,6 +73,8 @@ class CellularDevice { */ static CellularDevice *get_default_instance(); + mbed::Callback enableCMUXChannel = nullptr; + /** Return target onboard instance of CellularDevice * * @remark Mbed OS target shall override (non-weak) this function for an onboard modem. @@ -216,6 +218,13 @@ class CellularDevice { */ virtual nsapi_error_t get_sim_state(SimState &state) = 0; + virtual nsapi_error_t enable_cmux() = 0; + + + virtual bool is_cmux_enabled() = 0; + + virtual void set_cmux_status_flag(bool cmux_status) = 0; + /** Creates a new CellularContext interface. * * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h index 4600e9cc778..fa011a09681 100755 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h @@ -84,6 +84,14 @@ class AT_CellularDevice : public CellularDevice { virtual nsapi_error_t get_sim_state(SimState &state); + nsapi_error_t enable_cmux(); + + nsapi_error_t config_cmux(); + + void set_cmux_status_flag(bool cmux_status); + + virtual bool is_cmux_enabled(); + virtual CellularContext *create_context(const char *apn = NULL, bool cp_req = false, bool nonip_req = false); virtual void delete_context(CellularContext *context); @@ -206,6 +214,7 @@ class AT_CellularDevice : public CellularDevice { std::chrono::duration _default_timeout; bool _modem_debug_on; + bool _cmux_status; const intptr_t *_property_array; }; diff --git a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp index 6b9fb462d33..08229ba49ba 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp @@ -241,6 +241,37 @@ nsapi_error_t AT_CellularDevice::get_sim_state(SimState &state) return error; } +nsapi_error_t AT_CellularDevice::enable_cmux() +{ +setup_at_handler(); + + _at.lock(); + for (int retry = 1; retry <= 3; retry++) { + _at.clear_error(); + _at.flush(); + _at.at_cmd_discard("E0", ""); + if (_at.get_last_error() == NSAPI_ERROR_OK) { + _at.at_cmd_discard("+CMUX", "=0"); + if (_at.get_last_error() == NSAPI_ERROR_OK) { + break; + } + } + tr_debug("Wait 100ms to init modem"); + rtos::ThisThread::sleep_for(100ms); // let modem have time to get ready + } + return _at.unlock_return_error(); +} + + +bool AT_CellularDevice::is_cmux_enabled() +{ + return _cmux_status; +} + +void AT_CellularDevice::set_cmux_status_flag(bool cmux_status) +{ + _cmux_status = cmux_status; +} nsapi_error_t AT_CellularDevice::set_pin(const char *sim_pin) { // if SIM is already in ready state then settings the PIN diff --git a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp index 0a452eacb3a..833f1d2239a 100644 --- a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +++ b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp @@ -361,6 +361,12 @@ void CellularStateMachine::state_device_ready() _cb_data.error = _cellularDevice.soft_power_on(); } if (_cb_data.error == NSAPI_ERROR_OK) { + if(_cellularDevice.is_cmux_enabled()){ + _cb_data.error = _cellularDevice.enable_cmux(); + if (_cb_data.error == NSAPI_ERROR_OK) { + _cellularDevice.enableCMUXChannel(); + } + } _cb_data.error = _cellularDevice.init(); if (_cb_data.error == NSAPI_ERROR_OK) { diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index c7790fe348c..1f82199106e 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -51,6 +51,11 @@ AT_CellularNetwork *GEMALTO_CINTERION::open_network_impl(ATHandler &at) nsapi_error_t GEMALTO_CINTERION::init() { + // init CMUX if requested + if(is_cmux_enabled()){ + enable_cmux(); + enableCMUXChannel(); + } nsapi_error_t err = AT_CellularDevice::init(); if (err != NSAPI_ERROR_OK) { return err; @@ -67,7 +72,6 @@ nsapi_error_t GEMALTO_CINTERION::init() tr_error("Cellular model not found!"); return NSAPI_ERROR_DEVICE_ERROR; } - if (memcmp(model, "ELS61", sizeof("ELS61") - 1) == 0) { init_module_els61(); } else if (memcmp(model, "BGS2", sizeof("BGS2") - 1) == 0) { @@ -83,7 +87,6 @@ nsapi_error_t GEMALTO_CINTERION::init() return NSAPI_ERROR_UNSUPPORTED; } tr_info("Cinterion model %s (%d)", model, _module); - set_at_urcs(); return NSAPI_ERROR_OK; diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp index 37ca733b6e0..f749b4e575b 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp @@ -31,4 +31,9 @@ nsapi_error_t GEMALTO_CINTERION_CellularNetwork::set_attach() return NSAPI_ERROR_OK; } +void GEMALTO_CINTERION_CellularNetwork::get_context_state_command() +{ + _at.cmd_start_stop("^SICA", "?"); + _at.resp_start("^SICA:"); +} /* namespace mbed */ diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h index 8d5f49cf5ae..7483c5e019f 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.h @@ -26,6 +26,8 @@ class GEMALTO_CINTERION_CellularNetwork: public AT_CellularNetwork { GEMALTO_CINTERION_CellularNetwork(ATHandler &at, AT_CellularDevice &device); virtual ~GEMALTO_CINTERION_CellularNetwork(); virtual nsapi_error_t set_attach(); + virtual void get_context_state_command(); + protected: }; diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 9f111d7da0d..2993285049d 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -165,6 +165,11 @@ void GEMALTO_CINTERION_CellularStack::endGNSS() { _at.unlock(); } +void GEMALTO_CINTERION_CellularStack::enableCmux() +{ + _at.at_cmd_discard("+CMUX", "=0"); +} + int GEMALTO_CINTERION_CellularStack::startGNSS() { _at.lock(); _engine = false; @@ -304,10 +309,6 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_open_defer(CellularSocket bool foundSrvType = false; bool foundConIdType = false; - if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62) { - _at.cmd_start_stop("^SICA", "=", "%d%d", 1, _cid); - } - _at.cmd_start_stop("^SISS", "?"); _at.resp_start("^SISS:"); diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h index 37eee5858a0..f89da8c3140 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.h @@ -37,6 +37,7 @@ class GEMALTO_CINTERION_CellularStack : public AT_CellularStack { void lock(); void unlock(); void beginGNSS(mbed::Callback gnss_cb); + void enableCmux(); void endGNSS(); int startGNSS(); void stopGNSS(); From 4584ca27e6ea06e52d6ae8f1ca82526c355f5d62 Mon Sep 17 00:00:00 2001 From: Giampaolo Mancini Date: Thu, 3 Feb 2022 09:50:08 +0100 Subject: [PATCH 110/227] Implement Udp_RemClient for TX62 --- .../GEMALTO_CINTERION_CellularStack.cpp | 48 +++++++++++++++++-- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 2993285049d..1eca8f54e02 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -588,12 +588,50 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell // UDP Udp_RemClient if (socket->proto == NSAPI_UDP && GEMALTO_CINTERION::get_module() != GEMALTO_CINTERION::ModuleBGS2) { - char ip_address[NSAPI_IPv6_SIZE + sizeof("[]:12345") - 1 + 1]; - int ip_len = _at.read_string(ip_address, sizeof(ip_address)); - if (ip_len <= 0) { - tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); - return NSAPI_ERROR_DEVICE_ERROR; + + size_t ip_address_len = NSAPI_IPv6_SIZE + sizeof("[]:12345") - 1 + 1; + char ip_address[ip_address_len]; + + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62) { + // Local buffer for parsing Udp_RemClient for TX62 + uint8_t at_buf[ip_address_len]; + size_t ip_len = 0; + + // Skip + nsapi_size_or_error_t rem_len = _at.read_int(); + + // Wait for full in the _at buffer + do { + int len = _at.read_bytes(at_buf + ip_len, 1); + if (len <= 0) { + tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); + return NSAPI_ERROR_DEVICE_ERROR; + } + ip_len += len; + } while (ip_len < ip_address_len && at_buf[ip_len - 2] != '\r' && at_buf[ip_len - 1] != '\n'); + + // if (ip_len < sizeof("0.0.0.0:0")) { + if (ip_len < sizeof("[]:0")) { + tr_error("Socket %d has no address", socket->id); + goto sisr_retry; + } + + // at_buf contains remote client IP information + // in the format ":"\r\n. + + // Terminate the C string at the closing quotation mark + at_buf[ip_len - 3] = '\0'; + // Skip the opening quotation mark + memcpy(ip_address, at_buf + 1, ip_len - 4); + tr_info("ip_address %s (%d)", ip_address, ip_len - 4); + } else { + int ip_len = _at.read_string(ip_address, sizeof(ip_address)); + if (ip_len <= 0) { + tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); + return NSAPI_ERROR_DEVICE_ERROR; + } } + if (address) { char *ip_start = ip_address; char *ip_stop; From 77d1955952707f823666c014a5223389b600718f Mon Sep 17 00:00:00 2001 From: Giampaolo Mancini Date: Mon, 7 Feb 2022 15:13:41 +0100 Subject: [PATCH 111/227] Fix HostByName SISX request --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 1eca8f54e02..33a73bf9a35 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -276,15 +276,16 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S } if (!address->set_ip_address(host)) { - //_at.set_at_timeout(1min); - _at.cmd_start_stop("^SISX" , "=" , "%s%d%s", "HostByName" , _cid, host); + // _at.set_at_timeout(1min); + _at.cmd_start_stop("^SISX", "=", "%s%d%s", "HostByName", _cid, host); _at.resp_start("^SISX: \"HostByName\","); char ipAddress[NSAPI_IP_SIZE]; int size = _at.read_string(ipAddress, sizeof(ipAddress)); + _at.resp_stop(); if (size > 0) { //Valid string received tr_info("Read %d bytes. Valid string: %s\n", size, ipAddress); - _at.restore_at_timeout(); + // _at.restore_at_timeout(); if (!address->set_ip_address(ipAddress)) { _at.unlock(); return NSAPI_ERROR_DNS_FAILURE; From 9179831ca7fe22dcf3c095fd07232e495d2beaa9 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 3 Feb 2022 14:35:55 +0100 Subject: [PATCH 112/227] PwmOut: set pwm period before duty cycle --- drivers/source/PwmOut.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/source/PwmOut.cpp b/drivers/source/PwmOut.cpp index cc717f8e99a..53e6f84f10d 100644 --- a/drivers/source/PwmOut.cpp +++ b/drivers/source/PwmOut.cpp @@ -142,8 +142,8 @@ void PwmOut::resume() core_util_critical_section_enter(); if (!_initialized) { PwmOut::init(); - PwmOut::write(_duty_cycle); PwmOut::period_us(_period_us); + PwmOut::write(_duty_cycle); } core_util_critical_section_exit(); } From 77cd93e7fdaead54ccb98b0a097b9347d166d2c2 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 17 Feb 2021 14:57:44 +0100 Subject: [PATCH 113/227] Initial: add Nicla Vision target Add missing repo for BLE --- .../TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp | 105 + .../TARGET_NICLA_VISION/CMakeLists.txt | 22 + .../COMPONENT_CYW43XXX/CMakeLists.txt | 4 + .../firmware/CMakeLists.txt | 6 + .../COMPONENT_4343W_FS/CMakeLists.txt | 7 + .../w_bt_firmware_controller.c | 2101 ++ .../COMPONENT_WHD/CMakeLists.txt | 34 + .../COMPONENT_WHD/generated_mac_address.txt | 9 + .../COMPONENT_WHD/interface/cy_result.h | 228 + .../COMPONENT_WHD/interface/cyabs_rtos.h | 711 + .../COMPONENT_WHD/interface/cyabs_rtos_impl.h | 77 + .../interface/cyabs_rtos_rtxv5.c | 863 + .../COMPONENT_WHD/interface/cyhal_gpio.h | 247 + .../COMPONENT_WHD/interface/cyhal_sdio.h | 366 + .../COMPONENT_WHD/interface/cyhal_spi.h | 383 + .../COMPONENT_WHD/port/cy_hal.c | 63 + .../COMPONENT_WHD/port/cy_syslib.h | 592 + .../COMPONENT_WHD/port/cy_utils.h | 81 + .../COMPONENT_WHD/port/cybsp.h | 50 + .../COMPONENT_WHD/port/cycfg.h | 20 + .../COMPONENT_WHD/port/cyhal.h | 52 + .../COMPONENT_WHD/port/cyhal_gpio.cpp | 104 + .../COMPONENT_WHD/port/cyhal_hw_types.h | 112 + .../COMPONENT_WHD/port/cyhal_sdio.c | 485 + .../COMPONENT_WHD/port/cyhal_spi.c | 29 + .../COMPONENT_WHD/port/cyhal_system.h | 20 + .../COMPONENT_WHD/port/wiced_bd.h | 49 + .../COMPONENT_WHD/port/wiced_filesystem.cpp | 220 + .../COMPONENT_WHD/port/wiced_filesystem.h | 139 + .../LICENSE-permissive-binary-license-1.0.txt | 49 + .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 25493 ++++++++++++++++ .../COMPONENT_4343W_FS/4343WA1_clm_blob.c | 400 + .../firmware/COMPONENT_4343W_FS/resources.h | 30 + .../resources/nvram/wifi_nvram_image.h | 87 + .../COMPONENT_WHD/whd_config.h | 61 + .../TARGET_NICLA_VISION/PeripheralPins.c | 583 + .../TARGET_NICLA_VISION/PinNames.h | 474 + .../system_clock_override.c | 306 + targets/targets.json | 47 + 39 files changed, 34709 insertions(+) create mode 100644 connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/generated_mac_address.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cy_result.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_impl.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_gpio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_sdio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_spi.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_hal.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_syslib.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_utils.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cybsp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cycfg.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_gpio.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_hw_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_spi.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_system.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_bd.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/whd_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/system_clock_override.c diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp new file mode 100644 index 00000000000..2d668fed9ce --- /dev/null +++ b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp @@ -0,0 +1,105 @@ +/******************************************************************************* +* \file cy_bt_cordio_cfg.cpp +* \version 1.0 +* +* +* Low Power Assist BT Pin configuration implementation. +* +******************************************************************************** +* \copyright +* Copyright 2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "ble/driver/CordioHCIDriver.h" +#include "hci_api.h" +#include "hci_cmd.h" +#include "hci_core.h" +#include "bstream.h" +#include "assert.h" +#include +#include "hci_mbed_os_adaptation.h" +#include "CyH4TransportDriver.h" + +#define cyhal_gpio_to_rtos(x) (x) +#define CYCFG_BT_LP_ENABLED (1) +#define CYCFG_BT_HOST_WAKE_IRQ_EVENT WAKE_EVENT_ACTIVE_LOW +#define CYCFG_BT_DEV_WAKE_POLARITY WAKE_EVENT_ACTIVE_LOW + +/******************************************************************************* +* Function Name: ble_cordio_get_h4_transport_driver +******************************************************************************** +* +* Strong implementation of function which calls CyH4TransportDriver constructor and return it +* +* \param none +* +* \return +* Returns the transport driver object +*******************************************************************************/ +ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver() +{ +#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) + +#if (defined(CYCFG_BT_LP_ENABLED)) + if (CYCFG_BT_LP_ENABLED) { + static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( + /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), + /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), + /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), + /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), + /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), + DEF_BT_BAUD_RATE, + cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), + cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE), + CYCFG_BT_HOST_WAKE_IRQ_EVENT, + CYCFG_BT_DEV_WAKE_POLARITY + ); + return s_transport_driver; + } else { /* CYCFG_BT_LP_ENABLED */ + static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( + /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), + /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), + /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), + /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), + /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), + DEF_BT_BAUD_RATE); + return s_transport_driver; + } +#else /* (defined(CYCFG_BT_LP_ENABLED)) */ + static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( + /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), + /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), + /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), + /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), + /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), + DEF_BT_BAUD_RATE), + cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE) + ); + return s_transport_driver; +#endif /* (defined(CYCFG_BT_LP_ENABLED)) */ + +#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ + static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( + /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), + /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), + /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), + /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), + /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), + DEF_BT_BAUD_RATE); + return s_transport_driver; +#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/CMakeLists.txt new file mode 100644 index 00000000000..2a398afa439 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-disco-h747i INTERFACE) + +target_sources(mbed-disco-h747i + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-disco-h747i + INTERFACE + . +) + +target_link_libraries(mbed-disco-h747i INTERFACE mbed-stm32h747xi mbed-stm32h747xi-cm7) + +add_library(mbed-disco-h747i-cm7 INTERFACE) +target_link_libraries(mbed-disco-h747i-cm7 INTERFACE mbed-stm32h747xi mbed-stm32h747xi-cm7) + +add_library(mbed-disco-h747i-cm4 INTERFACE) +target_link_libraries(mbed-disco-h747i-cm4 INTERFACE mbed-stm32h747xi mbed-stm32h747xi-cm4) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/CMakeLists.txt new file mode 100644 index 00000000000..82be36e1f09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(firmware) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/CMakeLists.txt new file mode 100644 index 00000000000..fbbc3b979de --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("4343W_FS" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_4343W) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt new file mode 100644 index 00000000000..31fecb8fe09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-ble + INTERFACE + w_bt_firmware_controller.c +) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c new file mode 100644 index 00000000000..ac2bc973e1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c @@ -0,0 +1,2101 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = "BCM4343A1_001.002.009.0083.0000_Generic_UART_37_4MHz_wlbga_wiced"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[] = { + 76, 252, 70, 16, 24, 33, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, + 0, 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 18, 161, + 67, 67, 0, 1, 28, 82, 24, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 255, 82, 24, + 33, 0, 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 79, 133, 0, 0, + 3, 3, 40, 66, 67, 77, 52, 51, 52, 51, 65, 49, 32, 85, 65, 82, 84, 32, + 51, 55, 46, 52, 32, 77, 72, 122, 32, 119, 108, 98, 103, 97, 95, 114, + 101, 102, 32, 119, 105, 99, 101, 100, 0, 22, 3, 2, 83, 0, 2, 1, 248, + 3, 8, 1, 50, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 50, 0, 255, 15, 0, 0, + 98, 8, 0, 0, 112, 0, 100, 0, 128, 0, 0, 0, 128, 0, 0, 0, 172, 0, 50, + 0, 255, 255, 255, 1, 0, 0, 47, 0, 140, 0, 50, 0, 0, 240, 255, 15, 0, + 16, 17, 1, 120, 0, 50, 0, 255, 255, 255, 255, 185, 184, 184, 184, 96, + 44, 32, 0, 255, 0, 0, 0, 0, 0, 0, 0, 16, 1, 50, 0, 0, 0, 255, 255, 0, + 0, 24, 24, 108, 1, 96, 0, 255, 255, 255, 255, 11, 0, 0, 0, 112, 1, 96, + 0, 255, 255, 255, 255, 16, 0, 0, 0, 116, 1, 96, 0, 255, 255, 255, 255, + 21, 0, 0, 0, 120, 1, 96, 0, 255, 255, 255, 255, 25, 0, 0, 0, 124, 1, + 96, 0, 255, 255, 0, 0, 29, 0, 0, 0, 132, 1, 96, 0, 255, 255, 255, 255, + 33, 0, 0, 0, 96, 6, 65, 0, 255, 255, 0, 0, 51, 3, 0, 0, 100, 6, 65, + 76, 252, 255, 77, 25, 33, 0, 0, 255, 255, 0, 0, 41, 58, 0, 0, 100, 6, + 65, 0, 255, 255, 0, 0, 41, 58, 0, 0, 104, 6, 65, 0, 255, 255, 0, 0, + 104, 5, 0, 0, 108, 6, 65, 0, 255, 255, 0, 0, 168, 48, 0, 0, 112, 6, + 65, 0, 255, 255, 0, 0, 232, 62, 0, 0, 116, 6, 65, 0, 255, 255, 0, 0, + 28, 50, 0, 0, 120, 6, 65, 0, 255, 255, 0, 0, 187, 51, 0, 0, 124, 6, + 65, 0, 255, 255, 0, 0, 48, 9, 0, 0, 80, 3, 65, 0, 255, 255, 0, 0, 16, + 5, 0, 0, 84, 3, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 92, 3, 65, 0, 255, + 255, 0, 0, 9, 8, 0, 0, 96, 3, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 100, + 3, 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 108, 3, 65, 0, 255, 255, 0, 0, + 14, 9, 0, 0, 116, 3, 65, 0, 255, 255, 0, 0, 5, 9, 0, 0, 120, 3, 65, + 0, 255, 255, 0, 0, 16, 10, 0, 0, 64, 1, 65, 0, 255, 255, 0, 0, 16, 5, + 0, 0, 68, 1, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 76, 1, 65, 0, 255, 255, + 0, 0, 9, 8, 0, 0, 80, 1, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 84, 1, + 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 92, 1, 76, 252, 255, 72, 26, 33, + 0, 65, 0, 255, 255, 0, 0, 14, 9, 0, 0, 96, 1, 65, 0, 255, 255, 0, 0, + 5, 9, 0, 0, 100, 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240, 7, 13, 0, 16, 1, 15, 123, 252, 199, 1, 0, 179, + 240, 254, 191, 0, 0, 252, 7, 13, 0, 16, 1, 15, 124, 100, 200, 1, 0, + 179, 240, 207, 191, 0, 0, 6, 8, 13, 0, 16, 1, 15, 125, 80, 180, 1, 0, + 181, 240, 224, 185, 0, 0, 76, 252, 11, 170, 157, 33, 0, 20, 8, 13, 0, + 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 +}; + +const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/CMakeLists.txt new file mode 100644 index 00000000000..55b7e63ecf3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-portenta-whd-4343w-fw INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS +) +target_sources(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c + resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +) + +add_library(mbed-portenta-whd-4343w-nvram INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-nvram INTERFACE resources/nvram) + +add_library(mbed-portenta-whd INTERFACE) +target_include_directories(mbed-portenta-whd + INTERFACE + . + port + interface +) + +target_sources(mbed-portenta-whd + INTERFACE + port/cyhal.c + port/cyhalgpio.cpp + port/cyhalsdio.c + port/wiced_filesystem.cpp + interface/cyabs_rtos_rtxv5.c +) + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/generated_mac_address.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/generated_mac_address.txt new file mode 100644 index 00000000000..eb735ba173d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during WHD power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:6f:b2:ea" diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cy_result.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cy_result.h new file mode 100644 index 00000000000..8277169ab99 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cy_result.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cy_result.h +* +* \brief +* Basic function result handling. Defines a simple type for conveying +* information about whether something succeeded or details about any issues +* that were detected. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_result Result Type +* \ingroup group_abstraction +* \{ +* \anchor anchor_general_description +* \brief Defines a type and related utilities for function result handling. +* +* The @ref cy_rslt_t type is a structured bitfield which encodes information +* about result type, the originating module, and a code for the specific +* error (or warning etc). In order to extract these individual fields from +* a @ref cy_rslt_t value, the utility macros @ref CY_RSLT_GET_TYPE, @ref CY_RSLT_GET_MODULE, +* and @ref CY_RSLT_GET_CODE are provided. For example: +* \code +* cy_rslt_t result = cy_hal_do_operation(arg); +* // Will be CY_RSLT_TYPE_INFO, CY_RSLT_TYPE_WARNING, CY_RSLT_TYPE_ERROR, or CY_RSLT_TYPE_FATAL +* uint8_t type = CY_RSLT_GET_TYPE(result) +* // See the "Modules" section for possible values +* uint16_t module_id = CY_RSLT_GET_MODULE(result); +* // Specific error codes are defined by each module +* uint16_t error_code = CY_RSLT_GET_CODE(result); +* \endcode +*/ + +#if !defined(CY_RESULT_H) +#define CY_RESULT_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief Provides the result of an operation as a structured bitfield. + * + * See the \ref anchor_general_description "General Description" + * for more details on structure and usage. + */ +typedef uint32_t cy_rslt_t; + +/** @ref cy_rslt_t return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) + +/** \cond INTERNAL */ +/** Mask for the bit at position "x" */ +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) + +/** Bit position of the result type */ +#define CY_RSLT_TYPE_POSITION (16U) +/** Bit width of the result type */ +#define CY_RSLT_TYPE_WIDTH (2U) +/** Bit position of the module identifier */ +#define CY_RSLT_MODULE_POSITION (18U) +/** Bit width of the module identifier */ +#define CY_RSLT_MODULE_WIDTH (14U) +/** Bit position of the result code */ +#define CY_RSLT_CODE_POSITION (0U) +/** Bit width of the result code */ +#define CY_RSLT_CODE_WIDTH (16U) + +/** Mask for the result type */ +#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) +/** Mask for the module identifier */ +#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH) +/** Mask for the result code */ +#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH) + +/** \endcond */ + +/** +* \{ +* @name Fields +* Utility macros for constructing result values and extracting individual fields from existing results. +*/ + +/** + * @brief Get the value of the result type field + * @param x the @ref cy_rslt_t value from which to extract the result type + */ +#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK) +/** + * @brief Get the value of the module identifier field + * @param x the @ref cy_rslt_t value from which to extract the module id + */ +#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) +/** + * @brief Get the value of the result code field + * @param x the @ref cy_rslt_t value from which to extract the result code + */ +#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) + +/** + * @brief Create a new @ref cy_rslt_t value that encodes the specified type, module, and result code. + * @param type one of @ref CY_RSLT_TYPE_INFO, @ref CY_RSLT_TYPE_WARNING, + * @ref CY_RSLT_TYPE_ERROR, @ref CY_RSLT_TYPE_FATAL + * @param module Identifies the module where this result originated; see @ref anchor_modules "Modules". + * @param code a module-defined identifier to identify the specific situation that + * this result describes. + */ +#define CY_RSLT_CREATE(type, module, code) \ + ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ + (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ + (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) + +/** \} fields */ + +/** +* \{ +* @name Result Types +* Defines codes to identify the type of result. +*/ + +/** @brief The result code is informational-only */ +#define CY_RSLT_TYPE_INFO (0U) +/** @brief The result code is warning of a problem but will proceed */ +#define CY_RSLT_TYPE_WARNING (1U) +/** @brief The result code is an error */ +#define CY_RSLT_TYPE_ERROR (2U) +/** @brief The result code is a fatal error */ +#define CY_RSLT_TYPE_FATAL (3U) + +/** \} severity */ + +/** +* \{ +* @name Modules +* @anchor anchor_modules +* Defines codes to identify the module from which an error originated. +* For some large libraries, a range of module codes is defined here; +* see the library documentation for values corresponding to individual modules. +* Valid range is 0x0000-0x4000. +*/ +/**** DRIVER Module codes: 0x0000 - 0x00FF ****/ +/** Base module identifier for peripheral driver library drivers (0x0000 - 0x007F) */ +#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) +/** Base module identifier for wireless host driver library modules (0x0080 - 0x00FF) */ +#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) + +/** Deprecated. Use \ref CY_RSLT_MODULE_ABSTRACTION_HAL */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) +/** Module identifier for the Hardware Abstraction Layer */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL (0x0100U) +/** Module identifier for board support package */ +#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) +/** Module identifier for file system abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) +/** Module identifier for resource abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) +/** Module identifier for rtos abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) +/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ +#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) + +/** Base module identifier for Board Libraries (0x01A0 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_LIB_BASE (0x01A0U) +/** Module identifier for the Retarget IO Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RETARGET_IO (0x1A0U) +/** Module identifier for the RGB LED Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RGB_LED (0x01A1U) +/** Module identifier for the Serial Flash Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH (0x01A2U) +/** Module identifier for the WiFi Host Driver + Board Support Integration Library */ +#define CY_RSLT_MODULE_BOARD_LIB_WHD_INTEGRATION (0x01A3U) + +/** Base module identifier for Shield Board Libraries (0x01B8 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_SHIELD_BASE (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-EPD */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_EPD (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-TFT */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_TFT (0x01B9U) +/** Module identifier for Shield Board CY8CKIT-032 */ +#define CY_RSLT_MODULE_BOARD_SHIELD_032 (0x01BAU) + +/** Base module identifier for Board Hardware Libraries (0x01C0 - 0x01FF) */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BASE (0x01C0U) +/** Module identifier for the BMI160 Motion Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BMI160 (0x01C0U) +/** Module identifier for the E2271CS021 E-Ink Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_E2271CS021 (0x01C1U) +/** Module identifier for the NTC GPIO Thermistor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_THERMISTOR (0x01C2U) +/** Module identifier for the SSD1306 OLED Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_SSD1306 (0x01C3U) +/** Module identifier for the ST7789V TFT Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_ST7789V (0x01C4U) +/** Module identifier for the Light Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_LIGHT_SENSOR (0x01C5U) +/** Module identifier for the AK4954A Audio Codec Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_AK4954A (0x01C6U) + +/** Base module identifier for Middleware Libraries (0x0200 - 0x02FF) */ +#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) + +/** \} modules */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_RESULT_H */ + +/** \} group_result */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos.h new file mode 100644 index 00000000000..e19ffc49f79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos.h @@ -0,0 +1,711 @@ +/***************************************************************************//** +* \file cyabs_rtos.h +* +* \brief +* Defines the Cypress RTOS Interface. Provides prototypes for functions that +* allow Cypress libraries to use RTOS resources such as threads, mutexes & +* timing functions in an abstract way. The APIs are implemented in the Port +* Layer RTOS interface which is specific to the RTOS in use. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef INCLUDED_CY_RTOS_INTERFACE_H_ +#define INCLUDED_CY_RTOS_INTERFACE_H_ + +#include "cyabs_rtos_impl.h" +#include "cy_result.h" +#include +#include +#include + +/** +* \defgroup group_abstraction_rtos_common Common + * General types and defines for working with the RTOS abstraction layer. +* \defgroup group_abstraction_rtos_mutex Mutex + * APIs for acquiring and working with Mutexes. +* \defgroup group_abstraction_rtos_queue Queue + * APIs for creating and working with Queues. +* \defgroup group_abstraction_rtos_semaphore Semaphore + * APIs for acquiring and working with Semaphores. +* \defgroup group_abstraction_rtos_threads Threads + * APIs for creating and working with Threads. +* \defgroup group_abstraction_rtos_time Time + * APIs for getting the current time and waiting. +* \defgroup group_abstraction_rtos_timer Timer + * APIs for creating and working with Timers. +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*********************************************** CONSTANTS **********************************************/ + +/** + * \ingroup group_abstraction_rtos_common + * \{ + */ + +#if defined(DOXYGEN) +//#include "Template/cyabs_rtos_impl.h" + +/** Return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) +#endif + +/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ +#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) + +// +// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty +// queues), the these errors are listed here and the abstraction layer implementation must map from the +// underlying errors to these. If the errors are special cases, the the error \ref CY_RTOS_GENERAL_ERROR +// will be returned and \ref cy_rtos_last_error() can be used to retrieve the RTOS specific error message. +// +/** Requested operation did not complete in the specified time */ +#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) +/** The RTOS could not allocate memory for the specified operation */ +#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) +/** An error occured in the RTOS */ +#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) +/** A bad argument was passed into the APIs */ +#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) +/** A memory alignment issue was detected. Ensure memory provided is aligned per \ref CY_RTOS_ALIGNMENT_MASK */ +#define CY_RTOS_ALIGNMENT_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 6) + +/** \} group_abstraction_rtos_common */ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** The Queue is already full and can't accept any more items at this time */ +#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) +/** The Queue is empty and has nothing to remove */ +#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** TYPES **********************************************/ + +/** + * The state a thread can be in + * + * \ingroup group_abstraction_rtos_threads + */ +typedef enum cy_thread_state +{ + CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ + CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ + CY_THREAD_STATE_RUNNING, /**< thread is currently running */ + CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ + CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ + CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ +} cy_thread_state_t; + +/** + * The type of timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef enum cy_timer_trigger_type +{ + CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ + CY_TIMER_TYPE_ONCE, /**< called once only */ + cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by \ref CY_TIMER_TYPE_PERIODIC */ + cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by \ref CY_TIMER_TYPE_ONCE */ +} cy_timer_trigger_type_t; + +/** + * The type of a function that is the entry point for a thread + * + * @param[in] arg the argument passed from the thread create call to the entry function + * + * \ingroup group_abstraction_rtos_threads + */ +typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg); + +/** + * The callback function to be called by a timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); + +/** + * Return the last error from the RTOS. + * + * The functions in the RTOS abstraction layer adhere to the Cypress return + * results calling convention. The underlying RTOS implementations will not but rather + * will have their own error code conventions. This function is provided as a service + * to the developer, mostly for debugging, and returns the underlying RTOS error code + * from the last RTOS abstraction layer that returned \ref CY_RTOS_GENERAL_ERROR. + * + * @return RTOS specific error code. + * + * \ingroup group_abstraction_rtos_common + */ +cy_rtos_error_t cy_rtos_last_error(); + +/*********************************************** Threads **********************************************/ + +/** + * \ingroup group_abstraction_rtos_threads + * \{ + */ + +/** Create a thread with specific thread argument. + * + * This function is called to startup a new thread. If the thread can exit, it must call + * \ref cy_rtos_exit_thread() just before doing so. All created threads that can terminate, either + * by themselves or forcefully by another thread MUST have \ref cy_rtos_join_thread() called on them + * by another thread in order to cleanup any resources that might have been allocated for them. + * + * @param[out] thread Pointer to a variable which will receive the new thread handle + * @param[in] entry_function Function pointer which points to the main function for the new thread + * @param[in] name String thread name used for a debugger + * @param[in] stack The buffer to use for the thread stack. This must be aligned to + * \ref CY_RTOS_ALIGNMENT_MASK with a size of at least \ref CY_RTOS_MIN_STACK_SIZE. + * If stack is null, cy_rtos_create_thread will allocate a stack from the heap. + * @param[in] stack_size The size of the thread stack in bytes + * @param[in] priority The priority of the thread. Values are operating system specific, but some + * common priority levels are defined: + * CY_THREAD_PRIORITY_LOW + * CY_THREAD_PRIORITY_NORMAL + * CY_THREAD_PRIORITY_HIGH + * @param[in] arg The argument to pass to the new thread + * + * @return The status of thread create request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); + +/** Exit the current thread. + * + * This function is called just before a thread exits. In some cases it is sufficient + * for a thread to just return to exit, but in other cases, the RTOS must be explicitly + * signaled. In cases where a return is sufficient, this should be a null funcition. + * where the RTOS must be signaled, this function should perform that In cases operation. + * In code using RTOS services, this function should be placed at any at any location + * where the main thread function will return, exiting the thread. Threads that can + * exit must still be joined (\ref cy_rtos_join_thread) to ensure their resources are + * fully cleaned up. + * + * @return The status of thread exit request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_exit_thread(); + +/** Terminates another thread. + * + * This function is called to terminate another thread and reap the resources claimed + * by the thread. This should be called both when forcibly terminating another thread + * as well as any time a thread can exit on its own. For some RTOS implementations + * this is not required as the thread resources are claimed as soon as it exits. In + * other cases, this must be called to reclaim resources. Threads that are terminated + * must still be joined (\ref cy_rtos_join_thread) to ensure their resources are fully + * cleaned up. + * + * @param[in] thread Handle of the thread to terminate + * + * @returns The status of the thread terminate. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); + +/** Waits for a thread to complete. + * + * This must be called on any thread that can complete to ensure that any resources that + * were allocated for it are cleaned up. + * + * @param[in] thread Handle of the thread to wait for + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); + +/** Checks if the thread is running + * + * This function is called to determine if a thread is actively running or not. For information on + * the thread state, use the \ref cy_rtos_get_thread_state() function. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] running Returns true if the thread is running, otherwise false + * + * @returns The status of the thread running check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); + +/** Gets the state the thread is currently in + * + * This function is called to determine if a thread is running/blocked/inactive/ready etc. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] state Returns the state the thread is currently in + * + * @returns The status of the thread state check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); + +/** Get current thread handle + * + * Returns the unique thread handle of the current running thread. + * + * @param[out] thread Handle of the current running thread + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread); + +/** \} group_abstraction_rtos_threads */ + +/*********************************************** Mutexes **********************************************/ + +/** + * \ingroup group_abstraction_rtos_mutex + * \{ + */ + +/** Create a recursive mutex. + * + * Creates a binary mutex which can be used to synchronize between threads + * and between threads and ISRs. Created mutexes are recursive and support priority inheritance. + * + * This function has been replaced by \ref cy_rtos_init_mutex2 which allow for specifying + * whether or not the mutex supports recursion or not. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +#define cy_rtos_init_mutex(mutex) cy_rtos_init_mutex2(mutex, true) + +/** Create a mutex which can support recursion or not. + * + * Creates a binary mutex which can be used to synchronize between threads and between threads and + * ISRs. Created mutexes can support priority inheritance if recursive. + * + * \note Not all RTOS implementations support non-recursive mutexes. In this case a recursive + * mutex will be created. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * @param[in] recursive Should the created mutex support recursion or not + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive); + +/** Get a mutex. + * + * If the mutex is available, it is acquired and this function returned. + * If the mutex is not available, the thread waits until the mutex is available + * or until the timeout occurs. + * + * @note This function must not be called from an interrupt context as it may block. + * + * @param[in] mutex Pointer to the mutex handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the mutex. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. + * Must be zero if in_isr is true. + * + * @return The status of the get mutex. Returns timeout if mutex was not acquired + * before timeout_ms period. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); + +/** Set a mutex. + * + * The mutex is released allowing any other threads waiting on the mutex to + * obtain the semaphore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status of the set mutex request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + * + */ +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); + +/** Deletes a mutex. + * + * This function frees the resources associated with a sempahore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status to the delete request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); + +/** \} group_abstraction_rtos_mutex */ + +/*********************************************** Semaphores **********************************************/ + +/** + * \ingroup group_abstraction_rtos_semaphore + * \{ + */ + +/** + * Create a semaphore + * + * This is basically a counting semaphore. + * + * @param[in,out] semaphore Pointer to the semaphore handle to be initialized + * @param[in] maxcount The maximum count for this semaphore + * @param[in] initcount The initial count for this semaphore + * + * @return The status of the semaphore creation. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount); + +/** + * Get/Acquire a semaphore + * + * If the semaphore count is zero, waits until the semaphore count is greater than zero. + * Once the semaphore count is greater than zero, this function decrements + * the count and return. It may also return if the timeout is exceeded. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the semaphore. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. Must + * be zero is in_isr is true + * @param[in] in_isr true if we are trying to get the semaphore from with an ISR + * @return The status of get semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); + +/** + * Set/Release a semaphore + * + * Increments the semaphore count, up to the maximum count for this semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] in_isr Value of true indicates calling from interrupt context + * Value of false indicates calling from normal thread context + * @return The status of set semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); + +/** + * Get the count of a semaphore. + * + * Gets the number of available tokens on the semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[out] count Pointer to the return count + * @return The status of get semaphore count operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count); + +/** + * Deletes a semaphore + * + * This function frees the resources associated with a semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * + * @return The status of semaphore deletion [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); + +/** \} group_abstraction_rtos_semaphore */ + +/*********************************************** Events **********************************************/ + +/** + * \ingroup group_abstraction_rtos_event + * \{ + */ + +/** Create an event. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. + * + * @param[in,out] event Pointer to the event handle to be initialized + * + * @return The status of the event initialization request. + * [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_event(cy_event_t *event); + +/** Set the event flag bits. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. Any threads waiting on this event are released + * + * @param[in] event Pointer to the event handle + * @param[in] bits The value of the 32 bit flags + * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread + * + * @return The status of the set request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** + * Clear the event flag bits + * + * This function clears bits in the event. + * + * @param[in] event Pointer to the event handle + * @param[in] bits Any bits set in this value, will be cleared in the event. + * @param[in] in_isr if true, this is called from an ISR, otherwise from a thread + * + * @return The status of the clear flags request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** Get the event bits. + * + * Returns the current bits for the event. + * + * @param[in] event Pointer to the event handle + * @param[out] bits pointer to receive the value of the event flags + * + * @return The status of the get request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); + +/** Wait for the event and return bits. + * + * Waits for the event to be set and then returns the bits associated + * with the event, or waits for the given timeout period. + * @note This function returns if any bit in the set is set. + * + * @param[in] event Pointer to the event handle + * @param[in,out] bits pointer to receive the value of the event flags + * @param[in] clear if true, clear any bits set that cause the wait to return + * if false, do not clear bits + * @param[in] all if true, all bits in the initial bits value must be set to return + * if false, any one bit in the initial bits value must be set to return + * @param[in] timeout The amount of time to wait in milliseconds + * + * @return The status of the wait for event request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); + +/** Deinitialize a event. + * + * This function frees the resources associated with an event. + * + * @param[in] event Pointer to the event handle + * + * @return The status of the deletion request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); + +/** \} group_abstraction_rtos_event */ + +/*********************************************** Queues **********************************************/ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** Create a queue. + * + * This is a queue of data where entries are placed on the back of the queue + * and removed from the front of the queue. + * + * @param[out] queue Pointer to the queue handle + * @param[in] length The maximum length of the queue in items + * @param[in] itemsize The size of each item in the queue. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); + +/** Put an item in a queue. + * + * This function puts an item in the queue. The item is copied + * into the queue using a memory copy and the data pointed to by item_ptr + * is no longer referenced once the call returns. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the item to place in the queue + * @param[in] timeout_ms The time to wait to place the item in the queue + * @param[in] in_isr If true this is being called from within and ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_FULL] + */ +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Gets an item in a queue. + * + * This function gets an item from the queue. The item is copied + * out of the queue into the memory provide by item_ptr. This space must be + * large enough to hold a queue entry as defined when the queue was initialized. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the memory for the item from the queue + * @param[in] timeout_ms The time to wait to get an item from the queue + * @param[in] in_isr If true this is being called from within an ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_EMPTY] + */ +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Return the number of items in the queue. + * + * This function returns the number of items currently in the queue. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_waiting Pointer to the return count + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); + +/** Return the amount of empty space in the queue. + * + * This function returns the amount of empty space in the + * queue. For instance, if the queue was created with 10 entries max and there + * are currently 2 entries in the queue, this will return 8. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_spaces Pointer to the return count. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); + +/** Reset the queue. + * + * This function sets the queue to empty. + * + * @param[in] queue pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); + +/** Deinitialize the queue handle. + * + * This function de-initializes the queue and returns all + * resources used by the queue. + * + * @param[in] queue Pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** Timers **********************************************/ + +/** + * \ingroup group_abstraction_rtos_timer + * \{ + */ + +/** Create a new timer. + * + * This function initializes a timer object. + * @note The timer is not active until start is called. + * @note The callback may be (likely will be) called from a different thread. + * + * @param[out] timer Pointer to the timer handle to initialize + * @param[in] type Type of timer (periodic or once) + * @param[in] fun The function + * @param[in] arg Argument to pass along to the callback function + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg); + +/** Start a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[in] num_ms The number of milliseconds to wait before the timer fires + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); + +/** Stop a timer. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); + +/** Returns state of a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[out] state Return value for state, true if running, false otherwise + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); + +/** Deinit the timer. + * + * This function deinitializes the timer and frees all consumed resources. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); + +/** \} group_abstraction_rtos_timer */ + +/*********************************************** Time **********************************************/ + +/** + * \ingroup group_abstraction_rtos_time + * \{ + */ + +/** Gets time in milliseconds since RTOS start. + * + * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds + * + * @param[out] tval Pointer to the struct to populate with the RTOS time + * + * @returns Time in milliseconds since the RTOS started. + */ +cy_rslt_t cy_rtos_get_time(cy_time_t *tval); + +/** Delay for a number of milliseconds. + * + * Processing of this function depends on the minimum sleep + * time resolution of the RTOS. The current thread should sleep for + * the longest period possible which is less than the delay required, + * then makes up the difference with a tight loop. + * + * @param[in] num_ms The number of milliseconds to delay for + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); + +/** \} group_abstraction_rtos_time */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_impl.h new file mode 100644 index 00000000000..8b36a68844a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_impl.h @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cyabs_rtos_impl.h +* +* \brief +* Internal definitions for RTOS abstraction layer +* +******************************************************************************** +* \copyright +* Copyright 2019-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + + +#ifndef INCLUDED_CYABS_RTOS_IMPL_H_ +#define INCLUDED_CYABS_RTOS_IMPL_H_ + +#include "cmsis_os2.h" +#include "rtx_os.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size in bytes */ +#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ +#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignment of created RTOS objects */ + + +/****************************************************** +* Type Definitions +******************************************************/ + +/* RTOS thread priority */ +typedef enum +{ + CY_RTOS_PRIORITY_MIN = osPriorityNone, + CY_RTOS_PRIORITY_LOW = osPriorityLow, + CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal, + CY_RTOS_PRIORITY_NORMAL = osPriorityNormal, + CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal, + CY_RTOS_PRIORITY_HIGH = osPriorityHigh, + CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime, + CY_RTOS_PRIORITY_MAX = osPriorityRealtime7 +} cy_thread_priority_t ; + +typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */ +typedef void * cy_thread_arg_t; /** Argument passed to the entry function of a thread */ +typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */ +typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */ +typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */ +typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */ +typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */ +typedef void * cy_timer_callback_arg_t; /** Argument passed to the timer callback function */ +typedef uint32_t cy_time_t; /** Time in milliseconds */ +typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c new file mode 100644 index 00000000000..37c70fe5c74 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c @@ -0,0 +1,863 @@ +/***************************************************************************//** +* \file cyabs_rtos.c +* +* \brief +* Implementation for CMSIS RTOS v2 abstraction +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + + +/****************************************************** +* Error Converter +******************************************************/ + +/* Last received error status */ +static cy_rtos_error_t dbgErr; +cy_rtos_error_t cy_rtos_last_error() { return dbgErr; } + +/* Converts internal error type to external error type */ +static cy_rslt_t error_converter(cy_rtos_error_t internalError) +{ + cy_rslt_t value; + + switch (internalError) + { + case osOK: + value = CY_RSLT_SUCCESS; + break; + case osErrorTimeout: + value = CY_RTOS_TIMEOUT; + break; + case osErrorParameter: + value = CY_RTOS_BAD_PARAM; + break; + case osErrorNoMemory: + value = CY_RTOS_NO_MEMORY; + break; + case osError: + case osErrorResource: + case osErrorISR: + default: + value = CY_RTOS_GENERAL_ERROR; + break; + } + + /* Update the last known error status */ + dbgErr = internalError; + return value; +} + + +/****************************************************** +* Threads +******************************************************/ + +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + osThreadAttr_t attr; + + if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE) + status = CY_RTOS_BAD_PARAM; + else if (stack != NULL && (0 != (((uint32_t)stack) & CY_RTOS_ALIGNMENT_MASK))) + status = CY_RTOS_ALIGNMENT_ERROR; + else + { + attr.name = name; + attr.attr_bits = osThreadJoinable; + attr.cb_size = osRtxThreadCbSize; + attr.stack_size = stack_size; + attr.priority = (osPriority_t)priority; + attr.tz_module = 0; + attr.reserved = 0; + + /* Allocate stack if NULL was passed */ + if ((uint32_t *)stack == NULL) + { + /* Note: 1 malloc so that it can be freed with 1 call when terminating */ + uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK; + attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size); + if (attr.cb_mem != NULL) + attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad); + } + else + { + attr.cb_mem = malloc(osRtxThreadCbSize); + attr.stack_mem = stack; + } + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *thread = osThreadNew((osThreadFunc_t)entry_function, arg, &attr); + CY_ASSERT((*thread == attr.cb_mem) || (*thread == NULL)); + status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_exit_thread() +{ + /* This does not have a return statement because the osThreadExit() function + * does not return so the return statement would be unreachable and causes a + * warning for IAR compiler. + */ + osThreadExit(); +} + +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadTerminate(*thread); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (running == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + switch (osThreadGetState(*thread)) + { + case osThreadInactive: + *state = CY_THREAD_STATE_INACTIVE; + break; + case osThreadReady: + *state = CY_THREAD_STATE_READY; + break; + case osThreadRunning: + *state = CY_THREAD_STATE_RUNNING; + break; + case osThreadBlocked: + *state = CY_THREAD_STATE_BLOCKED; + break; + case osThreadTerminated: + *state = CY_THREAD_STATE_TERMINATED; + break; + case osThreadError: + case osThreadReserved: + default: + *state = CY_THREAD_STATE_UNKNOWN; + break; + } + } + + return status; +} + +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadJoin(*thread); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*thread); + *thread = NULL; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + *thread = osThreadGetId(); + + return status; +} + + +/****************************************************** +* Mutexes +******************************************************/ + +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive) +{ + cy_rslt_t status; + osMutexAttr_t attr; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = osMutexPrioInherit; + if (recursive) + { + attr.attr_bits |= osMutexRecursive; + } + attr.cb_mem = malloc(osRtxMutexCbSize); + attr.cb_size = osRtxMutexCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *mutex = osMutexNew(&attr); + CY_ASSERT((*mutex == attr.cb_mem) || (*mutex == NULL)); + status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexAcquire(*mutex, timeout_ms); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexRelease(*mutex); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexDelete(*mutex); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*mutex); + *mutex = NULL; + } + } + + return status; +} + + +/****************************************************** +* Semaphores +******************************************************/ + +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount) +{ + cy_rslt_t status; + osSemaphoreAttr_t attr; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxSemaphoreCbSize); + attr.cb_size = osRtxSemaphoreCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *semaphore = osSemaphoreNew(maxcount, initcount, &attr); + CY_ASSERT((*semaphore == attr.cb_mem) || (*semaphore == NULL)); + status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreRelease(*semaphore); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count) +{ + cy_rslt_t status; + if (semaphore == NULL || count == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + *count = osSemaphoreGetCount(*semaphore); + status = CY_RSLT_SUCCESS; + } + return status; +} + +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreDelete(*semaphore); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*semaphore); + *semaphore = NULL; + } + } + + return status; +} + + +/****************************************************** +* Events +******************************************************/ + +#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL +#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL + +cy_rslt_t cy_rtos_init_event(cy_event_t *event) +{ + cy_rslt_t status; + osEventFlagsAttr_t attr; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxEventFlagsCbSize); + attr.cb_size = osRtxEventFlagsCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *event = osEventFlagsNew(&attr); + CY_ASSERT((*event == attr.cb_mem) || (*event == NULL)); + status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsSet(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsClear(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *bits = osEventFlagsGet(*event); + + return status; +} + +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + uint32_t flagOption; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny; + if (!clear) + flagOption |= osFlagsNoClear; + + statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL) + *bits = statusInternal; + else + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osEventFlagsDelete(*event); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*event); + *event = NULL; + } + } + + return status; +} + + +/****************************************************** +* Queues +******************************************************/ + +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) +{ + cy_rslt_t status; + osMessageQueueAttr_t attr; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_size = osRtxMessageQueueCbSize; + uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); + attr.mq_size = blockSize * length; + + /* Note: 1 malloc for both so that they can be freed with 1 call */ + uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; + attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); + if (attr.cb_mem != NULL) + attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad); + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *queue = osMessageQueueNew(length, itemsize, &attr); + CY_ASSERT((*queue == attr.cb_mem) || (*queue == NULL)); + status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_waiting == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_waiting = osMessageQueueGetCount(*queue); + + return status; +} + +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_spaces == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_spaces = osMessageQueueGetSpace(*queue); + + return status; +} + +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueReset(*queue); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueDelete(*queue); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*queue); + *queue = NULL; + } + } + + return status; +} + + +/****************************************************** +* Timers +******************************************************/ + +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg) +{ + cy_rslt_t status; + osTimerAttr_t attr; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxTimerCbSize); + attr.cb_size = osRtxTimerCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) + ? osTimerPeriodic + : osTimerOnce; + + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr ); + CY_ASSERT((*timer == attr.cb_mem) || (*timer == NULL)); + status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + uint32_t tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + { + uint32_t ticks = ((num_ms * tick_freq) / 1000); + statusInternal = osTimerStart(*timer, ticks); + status = error_converter(statusInternal); + } + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerStop(*timer); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((timer == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *state = osTimerIsRunning(*timer); + + return status; +} + +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerDelete(*timer); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*timer); + *timer = NULL; + } + } + + return status; +} + + +/****************************************************** +* Time +******************************************************/ + +cy_rslt_t cy_rtos_get_time(cy_time_t *tval) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + uint32_t tick_freq; + + if (tval == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + *tval = (cy_time_t)((osKernelGetTickCount() * 1000LL) / tick_freq); + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + statusInternal = osDelay(num_ms); + status = error_converter(statusInternal); + + return status; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_gpio.h new file mode 100644 index 00000000000..08d4e5bfb13 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_gpio.h @@ -0,0 +1,247 @@ +/***************************************************************************//** +* \file cyhal_gpio.h +* +* \brief +* Provides a high level interface for interacting with the GPIO on Cypress devices. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_gpio GPIO (General Purpose Input Output) +* \ingroup group_hal +* \{ +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/******************************************************************************* +* Defines +*******************************************************************************/ + +/** Integer representation of no connect pin (required to exist in all BSPs) */ +#define CYHAL_NC_PIN_VALUE (NC) + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Pin events */ +typedef enum { + CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ + CYHAL_GPIO_IRQ_RISE = 1 << 0, /**< Interrupt on rising edge */ + CYHAL_GPIO_IRQ_FALL = 1 << 1, /**< Interrupt on falling edge */ + CYHAL_GPIO_IRQ_BOTH = (CYHAL_GPIO_IRQ_RISE | CYHAL_GPIO_IRQ_FALL), /**< Interrupt on both rising and falling edges */ +} cyhal_gpio_event_t; + +/** Pin direction */ +typedef enum { + CYHAL_GPIO_DIR_INPUT, /**< Input pin */ + CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ + CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ +} cyhal_gpio_direction_t; + +/** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ +typedef enum { + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z. Use only for analog purpose */ + CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_STRONG, /**< Strong output. Output only. Output init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULL_NONE, /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ +} cyhal_gpio_drive_mode_t; + +/** GPIO callback function type */ +typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); + +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin + * + * @return The status of the init request + * + * Guidance for using gpio drive modes ( \ref cyhal_gpio_drive_mode_t for details). + * For default use drive modes: + * Input GPIO direction - \ref CYHAL_GPIO_DRIVE_NONE + * Output GPIO direction - \ref CYHAL_GPIO_DRIVE_STRONG + * Bidirectional GPIO - \ref CYHAL_GPIO_DRIVE_PULLUPDOWN + * \warning Don't use \ref CYHAL_GPIO_DRIVE_STRONG for input GPIO direction. It may cause an overcurrent issue. + */ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); + +/** Uninitialize the gpio peripheral and the cyhal_gpio_t object + * + * @param[in] pin Pin number + */ +void cyhal_gpio_free(cyhal_gpio_t pin); + +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. + * + * @param[in] pin The GPIO pin + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * + * @return The status of the configure request + */ +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode); + +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. + * + * @param[in] pin The GPIO object + * @param[in] value The value to be set (high = true, low = false) + */ +void cyhal_gpio_write(cyhal_gpio_t pin, bool value); + +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO object + * @return The value of the IO (true = high, false = low) + */ +bool cyhal_gpio_read(cyhal_gpio_t pin); + +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. + * @param[in] pin The GPIO object + */ +void cyhal_gpio_toggle(cyhal_gpio_t pin); + +/** Register/clear a callback handler for pin events
+ * + * This function will be called when one of the events enabled by \ref cyhal_gpio_enable_event occurs. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The pin number + * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. + * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL + */ +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); + +/** Enable or Disable the specified GPIO event
+ * + * When an enabled event occurs, the function specified by \ref cyhal_gpio_register_callback will be called. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The GPIO object + * @param[in] event The GPIO event + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) +#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; +/** \endcond */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#ifdef CYHAL_GPIO_IMPL_HEADER +#include CYHAL_GPIO_IMPL_HEADER +#endif /* CYHAL_GPIO_IMPL_HEADER */ + +/** \} group_hal_gpio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_sdio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_sdio.h new file mode 100644 index 00000000000..d5600efd997 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_sdio.h @@ -0,0 +1,366 @@ +/***************************************************************************//** +* \file cyhal_sdio.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SDIO interface. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) +* \ingroup group_hal +* \{ +* High level interface to the Secure Digital Input Output (SDIO). +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in \ref cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). +* +* The SDIO protocol is an extension of the SD +* interface for general I/O functions. Refer to the SD Specifications Part 1 SDIO +* Specifications Version 4.10 for more information on the SDIO protocol and specifications. +* +* +* \section subsection_sdio_features Features +* * Supports 4-bit interface +* * Supports Ultra High Speed (UHS-I) mode +* * Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes +* * Supports SDIO card interrupts in both 1-bit and 4-bit modes +* * Supports Standard capacity (SDSC), High capacity (SDHC) and Extended capacity (SDXC) memory +* +* \section subsection_sdio_quickstart Quick Start +* +* \ref cyhal_sdio_init initializes the SDIO peripheral and passes a pointer to the SDIO block through the **obj** object of type \ref cyhal_sdio_t. +* +* \section subsection_sdio_code_snippets Code Snippets +* +* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example +* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration +* +* \snippet sdio.c snippet_cyhal_sdio_simple_init +* +* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt +* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events. +* +* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback +* +* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands +* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands. +* +* \snippet sdio.c snippet_cyhal_sdio_send_command +* +* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer +* The following snippet shows how to start a bulk data transfer. +* +* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer +* +* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer +* +* The following snippet shows how to start an async data transfer. +* \snippet sdio.c snippet_cyhal_sdio_async_transfer +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Defines +*******************************************************************************/ + +#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ +#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ +#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ +#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ +#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ +#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ +#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ + +#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ +#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ +#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ +#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ +#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/ + +/* HAL return value defines */ + +/** \addtogroup group_hal_results_sdio SDIO HAL Results + * SDIO specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Incorrect parameter value define */ +#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT)) +/** Clock initialization error define */ +#define CYHAL_SDIO_RSLT_ERR_CLOCK \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR)) +/** Semaphore not initiated error define */ +#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED)) +/** Error define based on SDIO lower function return value */ +#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal))) +/** Define to indicate canceled operation */ +#define CYHAL_SDIO_RSLT_CANCELED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED)) +/** Transfers are not allowed after the SDIO block has allowed power mode transition. */ +#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR)) + +/** + * \} + */ + + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Commands that can be issued */ +typedef enum +{ + CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!< Go to idle state + CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!< Send a relative address + CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!< Send an OP IO + CYHAL_SDIO_CMD_SELECT_CARD = 7, //!< Send a card select + CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!< Go to inactive state + CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!< Perform a direct read/write + CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!< Perform an extended read/write +} cyhal_sdio_command_t; + +/** Types of transfer that can be performed */ +typedef enum +{ + CYHAL_READ, //!< Read from the card + CYHAL_WRITE //!< Write to the card +} cyhal_transfer_t; + +/** Types of events that could be asserted by SDIO */ +typedef enum { + /* Interrupt-based thread events */ + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!< Command Complete + CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete + CYHAL_SDIO_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped + CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDIO_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDIO_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDIO_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!< The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDIO_INT_A = 0x00200, //!< Reserved: set to 0 + CYHAL_SDIO_INT_B = 0x00400, //!< Reserved: set to 0 + CYHAL_SDIO_INT_C = 0x00800, //!< Reserved: set to 0 + CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!< Reserved: set to 0 + CYHAL_SDIO_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1 + CYHAL_SDIO_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set + + /* Non-interrupt-based thread events */ + CYHAL_SDIO_GOING_DOWN = 0x10000, //!< The interface is going away (eg: powering down for some period of time) + CYHAL_SDIO_COMING_UP = 0x20000, //!< The interface is back up (eg: came back from a low power state) + + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!< Is used to enable/disable all interrupts events +} cyhal_sdio_event_t; + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ + +/** @brief SDIO controller initial configuration */ +typedef struct +{ + uint32_t frequencyhal_hz; //!< Clock frequency, in hertz + uint16_t block_size; //!< Block size +} cyhal_sdio_cfg_t; + +/** Callback for SDIO events */ +typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ +/** Initialize the SDIO peripheral + * + * @param[out] obj Pointer to an SDIO object. + * The caller must allocate the memory for this object but the init + * function will initialize its contents. + * @param[out] clk The pin connected to the clk signal + * @param[in] cmd The pin connected to the command signal + * @param[in] data0 The pin connected to the data0 signal + * @param[in] data1 The pin connected to the data1 signal + * @param[in] data2 The pin connected to the data2 signal + * @param[in] data3 The pin connected to the data3 signal + * @return The status of the init request + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_1 for more information. + */ +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3); + +/** Release the SDIO block. + * + * @param[in,out] obj The SDIO object + */ +void cyhal_sdio_free(cyhal_sdio_t *obj); + +/** Configure the SDIO block with required parameters. Refer \ref cyhal_sdio_cfg_t for more information. + * + * @param[in,out] obj The SDIO object + * @param[in] config The SDIO configuration to apply + * @return The status of the configure request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); + +/** Sends command to the SDIO device. See \ref cyhal_sdio_command_t for list of available commands. + * + * This will block until the command is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] command The command to send to the SDIO device + * @param[in] argument The argument to the command + * @param[out] response The response from the SDIO device + * @return The status of the command transfer. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_3 for more information. + */ +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response); + +/** Performs a bulk data transfer. Sends \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command (CMD=53) which allows writing and reading of a large number of I/O registers with a single command. + * + * This will block until the transfer is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. + * @param[in] length The number of bytes to send + * @param[out] response The response from the SDIO device + * @return The status of the bulk transfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_4 for more information. + */ +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response); + +/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block. + * After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted. + * + * To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy() + * until it returns false. + * The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled + * after the asynchronous transfer is complete and in the condition they were + * enabled in before the transfer operation started. Handle these events in the interrupt callback. + * + * When the transfer is complete, the \ref CYHAL_SDIO_XFER_COMPLETE event will be raised. + * See \ref cyhal_sdio_register_callback and \ref cyhal_sdio_enable_event. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device + * @param[in] length The number of bytes to send + * @return The status of the async tranfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_5 for more information. + */ +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length); + +/** Checks if the specified SDIO is in use + * + * @param[in] obj The SDIO peripheral to check + * @return true if SDIO is in use. false, otherwise. + */ +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); + +/** Abort an SDIO transfer + * + * @param[in] obj The SDIO peripheral to stop + * @return The status of the abort_async request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); + +/** Register an SDIO event callback to be invoked when the event is triggered. + * + * This function will be called when one of the events enabled by \ref cyhal_sdio_enable_event occurs. + * + * @param[in] obj The SDIO object + * @param[in] callback The callback function which will be invoked when the event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when executed + * + * Refer \ref subsection_sdio_use_case_2 for more implementation. + */ +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); + +/** Enables callbacks to be triggered for specified SDIO events. Refer \ref cyhal_sdio_event_t for all events. + * + * @param[in] obj The SDIO object + * @param[in] event The SDIO event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable Set to true to enable events, or false to disable them + * + * Refer \ref subsection_sdio_use_case_2 for more information. + */ +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_sdio_register_irq cyhal_sdio_register_callback +#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; +typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SDIO_IMPL_HEADER +#include CYHAL_SDIO_IMPL_HEADER +#endif /* CYHAL_SDIO_IMPL_HEADER */ + +/** \} group_hal_sdio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_spi.h new file mode 100644 index 00000000000..f5ba47669f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/interface/cyhal_spi.h @@ -0,0 +1,383 @@ +/***************************************************************************//** +* \file cyhal_spi.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SPI. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_spi SPI (Serial Peripheral Interface) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. +* +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_results_spi SPI HAL Results + * SPI specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Bad argument */ +#define CYHAL_SPI_RSLT_BAD_ARGUMENT \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) +/** Failed to initialize SPI clock */ +#define CYHAL_SPI_RSLT_CLOCK_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1)) +/** Failed to Transfer SPI data */ +#define CYHAL_SPI_RSLT_TRANSFER_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2)) +/** Provided clock is not supported by SPI */ +#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6)) +/** The requested resource type is invalid */ +#define CYHAL_SPI_RSLT_ERR_INVALID_PIN \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) +/** Cannot configure SSEL signal */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_CONFIG_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 8)) +/** Cannot switch SSEL - device is busy or incorrect pin provided */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 9)) + +/** + * \} + */ + +/** Compatibility define for cyhal_spi_set_frequency. */ +#define cyhal_spi_frequency cyhal_spi_set_frequency + +/** SPI interrupt triggers */ +typedef enum { + /** All transfer data has been moved into data FIFO */ + CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, + /** Transfer complete. */ + CYHAL_SPI_IRQ_DONE = 1 << 2, + /** An error occurred while transferring data */ + CYHAL_SPI_IRQ_ERROR = 1 << 3, +} cyhal_spi_event_t; + +/** SPI Slave Select polarity */ +typedef enum { + /** SSEL signal is active low */ + CYHAL_SPI_SSEL_ACTIVE_LOW = 0, + /** SSEL signal is active high */ + CYHAL_SPI_SSEL_ACTIVE_HIGH = 1, +} cyhal_spi_ssel_polarity_t; + +/** Handler for SPI interrupts */ +typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); + +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the LSB is sent first. */ +#define CYHAL_SPI_MODE_FLAG_LSB (0x01u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPHA=1. */ +#define CYHAL_SPI_MODE_FLAG_CPHA (0x02u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPOL=1. */ +#define CYHAL_SPI_MODE_FLAG_CPOL (0x04u) +/** Creates a \ref cyhal_spi_mode_t value given the cpol, cpha, lsb values. */ +#define CYHAL_SPI_MODE(cpol, cpha, lsb) (((cpol > 0) ? CYHAL_SPI_MODE_FLAG_CPOL : 0) | \ + ((cpha > 0) ? CYHAL_SPI_MODE_FLAG_CPHA : 0) | \ + (( lsb > 0) ? CYHAL_SPI_MODE_FLAG_LSB : 0)) + +/** SPI operating modes */ +typedef enum +{ + /** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_00_MSB = CYHAL_SPI_MODE(0, 0, 0), + /** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_00_LSB = CYHAL_SPI_MODE(0, 0, 1), + /** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_01_MSB = CYHAL_SPI_MODE(0, 1, 0), + /** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_01_LSB = CYHAL_SPI_MODE(0, 1, 1), + /** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_10_MSB = CYHAL_SPI_MODE(1, 0, 0), + /** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_10_LSB = CYHAL_SPI_MODE(1, 0, 1), + /** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_11_MSB = CYHAL_SPI_MODE(1, 1, 0), + /** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1), +} cyhal_spi_mode_t; + +/** @brief Initial SPI configuration. */ +typedef struct +{ + cyhal_spi_mode_t mode; //!< The operating mode + uint8_t data_bits; //!< The number of bits per transfer + bool is_slave; //!< Whether the peripheral is operating as slave or master +} cyhal_spi_cfg_t; + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj Pointer to a SPI object. The caller must allocate the memory + * for this object but the init function will initialize its contents. + * @param[in] mosi The pin to use for MOSI + * @note At least MOSI or MISO pin should be non-NC + * @param[in] miso The pin to use for MISO + * @note At least MOSI or MISO pin should be non-NC + * @param[in] sclk The pin to use for SCLK + * @note This pin cannot be NC + * @param[in] ssel The pin to use for SSEL + * @note Provided pin will be configured for \ref CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed + * (as well as additional ssel pins can be added) by \ref cyhal_spi_slave_select_config and \ref cyhal_spi_select_active_ssel + * functions. This pin can be NC. + * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[in] bits The number of bits per frame + * @note bits should be 8 or 16 + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] is_slave false for master mode or true for slave mode operation + * @return The status of the init request + */ +cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, + const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave); + +/** Release a SPI object + * + * Return the peripheral, pins and clock owned by the SPI object to their reset state + * @param[in,out] obj The SPI object to deinitialize + */ +void cyhal_spi_free(cyhal_spi_t *obj); + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + * @return The status of the set_frequency request + */ +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); + +/** Configures provided ssel pin to work as SPI slave select with specified polarity. + * + * Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching + * between configured slave select pins is done by \ref cyhal_spi_select_active_ssel function. + * Unless modified with this function, the SSEL pin provided as part of \ref cyhal_spi_init is the default. + * @param[in] obj The SPI object to add slave select for + * @param[in] ssel Slave select pin to be added + * @param[in] polarity Polarity of slave select + * @return The status of ssel pin configuration + */ +cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity); + +/** Selects an active slave select line from one of available. + * + * This function is applicable for the master and slave. + * SSEL pin should be configured by \ref cyhal_spi_slave_select_config or \ref cyhal_spi_init functions prior + * to selecting it as active. The active slave select line will automatically be toggled as part of any transfer. + * @param[in] obj The SPI object for switching + * @param[in] ssel Slave select pin to be set as active + * @return CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL + */ +cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel); + +/** Synchronously get a received value out of the SPI receive buffer + * + * In Master mode - transmits fill-in value and read the data from RxFifo + * In Slave mode - Blocks until a value is available + * + * @param[in] obj The SPI peripheral to read + * @param[in] value The value received + * @return The status of the read request + * @note + * - In Master mode, MISO pin required to be non-NC for this API to operate + * - In Slave mode, MOSI pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); + +/** Synchronously send a byte out + * + * In Master mode transmits value to slave and read/drop a value from the RxFifo. + * In Slave mode writes a value to TxFifo + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return The status of the write request + * @note + * - In Master mode, MOSI pin required to be non-NC for this API to operate + * - In Slave mode, MISO pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); + +/** Synchronously Write a block out and receive a value + * + * The total number of bytes sent and received will be the maximum of tx_length + * and rx_length. The bytes written will be padded (at the end) with the value + * given by write_fill. + * + * This function will block for the duration of the transfer. \ref cyhal_spi_transfer_async + * can be used for non-blocking transfers. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx Pointer to the byte-array of data to write to the device + * @param[in,out] tx_length Number of bytes to write, updated with the number actually written + * @param[out] rx Pointer to the byte-array of data to read from the device + * @param[in,out] rx_length Number of bytes to read, updated with the number actually read + * @param[in] write_fill Default data transmitted while performing a read + * @return The status of the transfer request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill); + +/** Start an asynchronous SPI transfer. + * + * This will transfer `rx_length` bytes into the buffer pointed to by `rx`, while simultaneously transfering + * `tx_length` bytes of data from the buffer pointed to by `tx`, both in the background. + * When the transfer is complete, the @ref CYHAL_SPI_IRQ_DONE event will be raised. + * See @ref cyhal_spi_register_callback and @ref cyhal_spi_enable_event. + * \note For blocking transfers cyhal_spi_transfer can be used. + * + * @param[in] obj The SPI object that holds the transfer information + * @param[in] tx The transmit buffer + * @param[in,out] tx_length The number of bytes to transmit + * @param[out] rx The receive buffer + * @param[in,out] rx_length The number of bytes to receive + * @return The status of the transfer_async request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length); + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return Indication of whether the SPI is still transmitting + */ +bool cyhal_spi_is_busy(cyhal_spi_t *obj); + +/** Abort an SPI transfer + * + * @param[in] obj The SPI peripheral to stop + * @return The status of the abort_async request + */ +cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); + +/** Register a SPI callback handler + * + * This function will be called when one of the events enabled by \ref cyhal_spi_enable_event occurs. + * + * @param[in] obj The SPI object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); + +/** Configure SPI interrupt. This function is used for word-approach + * + * When an enabled event occurs, the function specified by \ref cyhal_spi_register_callback will be called. + * + * @param[in] obj The SPI object + * @param[in] event The SPI event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +typedef cyhal_spi_event_t cyhal_spi_irq_event_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SPI_IMPL_HEADER +#include CYHAL_SPI_IMPL_HEADER +#endif /* CYHAL_SPI_IMPL_HEADER */ + +/** \} group_hal_spi */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_hal.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_hal.c new file mode 100644 index 00000000000..f5a0716697c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_hal.c @@ -0,0 +1,63 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "cyhal.h" +#include "mbed_thread.h" +#include "mbed_wait_api.h" + +static cyhal_sdio_t sdio_obj; + +/* Edit Pin configuration */ +const pinconfig_t PinConfig[] = { + + [CYBSP_WIFI_WL_REG_ON] = WIFI_WL_REG_ON, +#ifdef CYBSP_WIFI_32K_CLK + [CYBSP_WIFI_32K_CLK] = WIFI_32K_CLK, +#endif /* CYBSP_WIFI_32K_CLK */ + [CYBSP_LED1 ] = BSP_LED1, + [CYBSP_LED2 ] = BSP_LED2, + [CYBSP_WIFI_SDIO_CMD] = WIFI_SDIO_CMD, + [CYBSP_WIFI_SDIO_CLK] = WIFI_SDIO_CLK, + [CYBSP_WIFI_SDIO_D0 ] = WIFI_SDIO_D0, + [CYBSP_WIFI_SDIO_D1 ] = WIFI_SDIO_D1, + [CYBSP_WIFI_SDIO_D2 ] = WIFI_SDIO_D2, + [CYBSP_WIFI_SDIO_D3 ] = WIFI_SDIO_D3, + [CYBSP_SDIO_OOB_IRQ ] = WIFI_SDIO_OOB_IRQ //VIKR +}; + +void Cy_SysLib_Delay(uint32_t milliseconds) +{ + thread_sleep_for(milliseconds); +} + +void Cy_SysLib_DelayUs(uint16_t microseconds) +{ + wait_us(microseconds); +} + +void cyhal_system_delay_ms(uint32_t milliseconds) +{ + Cy_SysLib_Delay(milliseconds); +} + +cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_syslib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_syslib.h new file mode 100644 index 00000000000..7671d853cfc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_syslib.h @@ -0,0 +1,592 @@ +/***************************************************************************//** +* \file cy_syslib.h +* \version 2.40.1 +* +* Provides an API declaration of the SysLib driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_syslib +* \{ +* The system libraries provide APIs that can be called in the user application +* to handle the timing, logical checking or register. +* +* The functions and other declarations used in this driver are in cy_syslib.h. +* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* and declarations in the PDL. +* +* The SysLib driver contains a set of different system functions. These functions +* can be called in the application routine. Major features of the system library: +* * Delay functions +* * The register Read/Write macro +* * Assert and Halt +* * Assert Classes and Levels +* * A software reset +* * Reading the reset cause +* * An API to invalidate the flash cache and buffer +* * Data manipulation macro +* * A variable type definition from MISRA-C which specifies signedness +* * Cross compiler compatible attributes +* * Getting a silicon-unique ID API +* * Setting wait states API +* * Resetting the backup domain API +* * APIs to serve Fault handler +* +* \section group_syslib_configuration Configuration Considerations +* Assertion Usage
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the +* program is running correctly. It is a convenient way to insert sanity checks. +* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of +* the PDL library. The behavior of the macro is as follows: if the expression +* passed to the macro is false, output an error message that includes the file +* name and line number, and then halts the CPU. \n +* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function. +* This is a weakly linked function. The default implementation stores the file +* name and line number of the ASSERT into global variables, cy_assertFileName +* and cy_assertLine . It then calls the Cy_SysLib_Halt() function. +* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing. +* +* The PDL source code uses this assert mechanism extensively. It is recommended +* that you enable asserts when debugging firmware. \n +* Assertion Classes and Levels
+* The PDL defines three assert classes, which correspond to different kinds +* of parameters. There is a corresponding assert "level" for each class. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Class MacroLevel MacroType of check
CY_ASSERT_CLASS_1CY_ASSERT_L1A parameter that could change between different PSoC devices +* (e.g. the number of clock paths)
CY_ASSERT_CLASS_2CY_ASSERT_L2A parameter that has fixed limits such as a counter period
CY_ASSERT_CLASS_3CY_ASSERT_L3A parameter that is an enum constant
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. +* This is a compiler command line argument, similar to how the DEBUG / NDEBUG +* macro is passed. \n +* Enabling any class also enables any lower-numbered class. +* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three +* classes. The following example shows the command-line option to enable all +* the assert levels: +* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode +* \note The use of special characters, such as spaces, parenthesis, etc. must +* be protected with quotes. +* +* After CY_ASSERT_LEVEL is defined, firmware can use +* one of the three level macros to make an assertion. For example, if the +* parameter can vary between devices, firmware uses the L1 macro. +* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode +* If the parameter has bounds, firmware uses L2. +* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode +* If the parameter is an enum, firmware uses L3. +* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode +* Each check uses the appropriate level macro for the kind of parameter being checked. +* If a particular assert class/level is not enabled, then the assert does nothing. +* +* \section group_syslib_more_information More Information +* Refer to the technical reference manual (TRM). +* +* \section group_syslib_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.This si required by design of the Cy_SysLib_Halt function.
18.4RUnions shall not be used.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers +* content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be +* defined, redefined or undefined.The driver defines the macros with leading underscores +* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
+* +* \section group_syslib_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.
Minor documentation edits.Documentation update and clarification.
Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
2.20Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.Provided support for the PDL static library in Release mode.
Minor documentation edits.Documentation update and clarification.
2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETRegister access simplification.
Removed the Cy_SysLib_GetNumHfclkResetCause API function.This feature is not supported by SRSS_ver1.
Added register access layer. Use register access macros instead +* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* not need to be recompiled for each supported part number.
2.0.1Minor documentation editsDocumentation update and clarification
2.0 +* Added Cy_SysLib_ResetBackupDomain() API implementation. \n +* Added CY_NOINLINE attribute implementation. \n +* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n +* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n +* Optimized Cy_SysLib_SetWaitStates() API implementation. +* Improvements made based on usability feedback.
Added Assertion Classes and Levels.For error checking, parameter validation and status returns in the PDL API.
Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.To store debug information into a non-zero init area for future analysis.
Removed CY_WEAK attribute implementation.CMSIS __WEAK attribute should be used instead.
1.0Initial version
+* +* \defgroup group_syslib_macros Macros +* \defgroup group_syslib_functions Functions +* \defgroup group_syslib_data_structures Data Structures +* \defgroup group_syslib_enumerated_types Enumerated Types +* +*/ + +#if !defined(CY_SYSLIB_H) +#define CY_SYSLIB_H + +#include +#include + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/** Get the lower 8 bits of a 16-bit value. */ +#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) +/** Get the upper 8 bits of a 16-bit value. */ +#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) + +/** Get the lower 16 bits of a 32-bit value. */ +#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) +/** Get the upper 16 bits of a 32-bit value. */ +#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) + +/** Swap the byte ordering of a 16-bit value */ +#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) + +/** Swap the byte ordering of a 32-bit value */ +#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ + (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) + +/** Swap the byte ordering of a 64-bit value */ +#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ + CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) + +/* MISRA rule 6.3 recommends using specific-length typedef for the basic + * numerical types of signed and unsigned variants of char, float, and double. + */ +typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ +typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ +typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ + + +/******************************************************************************* +* Macro Name: CY_GET_REG8(addr) +****************************************************************************//** +* +* Reads the 8-bit value from the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG8(addr, value) +****************************************************************************//** +* +* Writes an 8-bit value to the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG16(addr) +****************************************************************************//** +* +* Reads the 16-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG16(addr, value) +****************************************************************************//** +* +* Writes the 16-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG24(addr) +****************************************************************************//** +* +* Reads the 24-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) + + +/******************************************************************************* +* Macro Name: CY_SET_REG24(addr, value) +****************************************************************************//** +* +* Writes the 24-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG24(addr, value) do \ + { \ + (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ + (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ + (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ + } \ + while(0) + + +/******************************************************************************* +* Macro Name: CY_GET_REG32(addr) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG32(addr, value) +****************************************************************************//** +* +* Writes the 32-bit value to the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD32U +****************************************************************************//** +* +* The macro for setting a register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the register. +* +*******************************************************************************/ +#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) + + +/******************************************************************************* +* Macro Name: CY_REG32_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 32-bit register. +* +*******************************************************************************/ +#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD16U +****************************************************************************//** +* +* The macro for setting a 16-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 16-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ + ((uint16_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG16_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 16-bit register. +* +*******************************************************************************/ +#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD8U +****************************************************************************//** +* +* The macro for setting a 8-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 8-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ + ((uint8_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG8_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 8-bit register. +* +*******************************************************************************/ +#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _BOOL2FLD +****************************************************************************//** +* +* Returns a field mask if the value is not false. +* Returns 0, if the value is false. +* +*******************************************************************************/ +#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) + + +/******************************************************************************* +* Macro Name: _FLD2BOOL +****************************************************************************//** +* +* Returns true, if the value includes the field mask. +* Returns false, if the value doesn't include the field mask. +* +*******************************************************************************/ +#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUND +****************************************************************************//** +* +* Calculates a / b with rounding to the nearest integer, +* a and b must have the same sign. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUNDUP +****************************************************************************//** +* +* Calculates a / b with rounding up if remainder != 0, +* both a and b must be positive. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) + +typedef uint32_t cy_status; +/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ +typedef uint32_t cystatus; +typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ +typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ +typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ +typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ +typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ +typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ +typedef float float32; /**< Alias to float for backward compatibility */ +typedef double float64; /**< Alias to double for backward compatibility */ +typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ +typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; /**< Alias to char for backward compatibility */ +typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ +typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ +typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ + +/** The ARM 32-bit Return error / status code for backward compatibility. +* Do not use them in your code. +*/ +#define CY_RET_SUCCESS (0x00U) /* Successful */ +#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CY_RET_MEMORY (0x03U) /* A memory-related failure */ +#define CY_RET_LOCKED (0x04U) /* A resource lock failure */ +#define CY_RET_EMPTY (0x05U) /* No more objects available */ +#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CY_RET_FINISHED (0x08U) /* Operation is completed */ +#define CY_RET_CANCELED (0x09U) /* Operation is canceled */ +#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */ +#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */ + +/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. +* Do not use them in your code. +*/ +#define CYRET_SUCCESS (0x00U) /* Successful */ +#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CYRET_MEMORY (0x03U) /* A memory-related failure */ +#define CYRET_LOCKED (0x04U) /* A resource lock failure */ +#define CYRET_EMPTY (0x05U) /* No more objects available */ +#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08U) /* Operation is completed */ +#define CYRET_CANCELED (0x09U) /* Operation is canceled */ +#define CYRET_TIMEOUT (0x10U) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */ + +/** \} group_syslib_functions */ + +#endif /* CY_SYSLIB_H */ + +/** \} group_syslib */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_utils.h new file mode 100644 index 00000000000..db8c143f361 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cy_utils.h @@ -0,0 +1,81 @@ +/***************************************************************************//** +* \file cy_utils.h +* +* \brief +* Basic utility macros and functions. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_utils Utilities +* \ingroup group_abstraction +* \{ +* Basic utility macros and functions. +* +* \defgroup group_utils_macros Macros +*/ + +#pragma once + +#include "stdint.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_utils_macros +* \{ +*/ + +/** Simple macro to supress the unused parameter warning by casting to void. */ +#define CY_UNUSED_PARAMETER(x) ( (void)(x) ) + +/** Halt the processor in the debug state + * @return + */ +static inline uint32_t CY_HALT() +{ + __asm(" bkpt 1"); + return 0; +} + +#ifdef CY_ASSERT +#undef CY_ASSERT +#endif /* ifdef(CY_ASSERT) */ + +/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */ +#if defined(NDEBUG) || defined(CY_NO_ASSERT) + #define CY_ASSERT(x) CY_UNUSED_PARAMETER(x) +#else + #define CY_ASSERT(x) do { \ + if(!(x)) \ + { \ + CY_HALT(); \ + } \ + } while(0) +#endif /* defined(NDEBUG) */ + +/** \} group_utils_macros */ + +#ifdef __cplusplus +} +#endif + +/** \} group_utils */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cybsp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cybsp.h new file mode 100644 index 00000000000..06226f327bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cybsp.h @@ -0,0 +1,50 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cycfg.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cycfg.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cycfg.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal.h new file mode 100644 index 00000000000..e56be0e0132 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal.h @@ -0,0 +1,52 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "whd_config.h" +#include "cyhal_hw_types.h" +#include "cyhal_gpio.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +typedef enum +{ + CYBSP_WIFI_WL_REG_ON, + CYBSP_WIFI_32K_CLK, + CYBSP_LED1, + CYBSP_LED2, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3, + CYBSP_SDIO_OOB_IRQ, + CYBSP_WIFI_MAX, +} wwd_sdio_pin_t; + +void cyhal_system_delay_ms(uint32_t milliseconds); +cy_rslt_t sdio_enable_high_speed(void); + +#if defined(__cplusplus) +} +#endif + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_gpio.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_gpio.cpp new file mode 100644 index 00000000000..55c1498b24a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_gpio.cpp @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 GPIOs on WHD driver + */ + +#include +#include "cyhal.h" +#include "cybsp.h" +#include "mbed.h" +#include "wiced_filesystem.h" + +extern pinconfig_t PinConfig[]; + +/******************************************************************************* +* Internal +*******************************************************************************/ +static mbed::InterruptIn *oob_irq; +static cyhal_gpio_event_t oob_event = CYHAL_GPIO_IRQ_FALL; +static cyhal_gpio_event_callback_t oob_handler; +static void *oob_handler_arg; + +/******************************************************************************* +* Internal Interrrupt Service Routine +*******************************************************************************/ +static void cb() +{ + oob_handler(oob_handler_arg, oob_event); +} + +/******************************************************************************* +* HAL Implementation +*******************************************************************************/ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + // Workaround to enable GPIOJ clock + if (pin == CYBSP_WIFI_WL_REG_ON) { + __HAL_RCC_GPIOG_CLK_ENABLE(); + // Ensure FS and BlockDevice are initialized on time if needed + wiced_filesystem_init(); + } + // Ignore the parameter and take the pin config directly from a static array defintions + HAL_GPIO_Init(PinConfig[pin].port, &PinConfig[pin].config); + if (direction == CYHAL_GPIO_DIR_OUTPUT) { + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (initVal) ? GPIO_PIN_SET : GPIO_PIN_RESET); + } + // Workaround to initialize sdio interface without cypress bsp init + if (pin == CYBSP_WIFI_WL_REG_ON) { + cyhal_sdio_t *sdio_p = cybsp_get_wifi_sdio_obj(); + ret = cyhal_sdio_init(sdio_p, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); + } + return ret; +} + +void cyhal_gpio_write(cyhal_gpio_t pin, bool value) +{ + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (value) ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t handler, void *handler_arg) +{ + if (handler && handler_arg && (oob_irq == NULL)) { + oob_irq = new mbed::InterruptIn(WL_HOST_WAKE); + oob_handler = handler; + oob_handler_arg = handler_arg; + } +} + +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable) +{ + oob_event = event; + if (enable) { + if (event == CYHAL_GPIO_IRQ_RISE) { + oob_irq->rise(cb); + } + if (event == CYHAL_GPIO_IRQ_FALL) { + oob_irq->fall(cb); + } + } else if (oob_irq != NULL) { + delete oob_irq; + } +} + +void cyhal_gpio_free(cyhal_gpio_t pin) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_hw_types.h new file mode 100644 index 00000000000..1f872abb373 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_hw_types.h @@ -0,0 +1,112 @@ +/***************************************************************************//** +* \file cyhal_hw_types_template.h +* +* \brief +* Provides a template for configuration resources used by the HAL. Items +* here need to be implemented for each HAL port. It is up to the environment +* being ported into what the actual types are. There are some suggestions below +* but these are not required. All that is required is that the type is defined; +* it does not matter to the HAL what type is actually chosen for the +* implementation +* All TODOs and references to 'PORT' need to be replaced by with meaningful +* values for the device being supported. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_hw_types PORT Hardware Types + * \ingroup group_hal_PORT + * \{ + * Struct definitions for configuration resources in the PORT. + * + * \defgroup group_hal_hw_types_data_structures Data Structures + */ + +#pragma once +#include +#include "stm32h7xx_hal.h" +#include "PinNames.h" + +/* + #include "TODO: Port specific header file" + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef CYHAL_ISR_PRIORITY_DEFAULT +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ +#define CYHAL_ISR_PRIORITY_DEFAULT (7) +#endif + +/** + * \addtogroup group_hal_hw_types_data_structures + * \{ + */ + +typedef int32_t cyhal_gpio_t; + +/** GPIO object */ +typedef struct +{ + GPIO_TypeDef *port; + GPIO_InitTypeDef config; +} pinconfig_t; + +/** Clock divider object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *div_type; +} cyhal_clock_divider_t; + +/** Clock object */ +typedef struct +{ + //For backwards compatibility with cyhal_clock_divider_t only. Do not use going forward. + int div_type; /*!< Deprecated */ + uint8_t div_num; /*!< Deprecated */ + //End BWC items + int block; + uint8_t channel; + bool reserved; +} cyhal_clock_t; + +/** SDIO object */ +typedef void* *cyhal_sdio_t; + +/** SPI object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *empty; +} cyhal_spi_t; + +#include "whd_config.h" +#include "whd_debug.h" + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_hw_types */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c new file mode 100644 index 00000000000..9044e871800 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c @@ -0,0 +1,485 @@ +/* + * Copyright 2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 SDIO on WHD driver + */ + +#include +#include +#include "whd_thread.h" +#include "bus_protocols/whd_bus_sdio_protocol.h" +#include "cyabs_rtos.h" +#include "cyhal_sdio.h" + +#define SDIO_RESPONSE_SHORT SDMMC_RESPONSE_SHORT +#define SDIO_WAIT_NO SDMMC_WAIT_NO +#define SDIO_CPSM_ENABLE SDMMC_CPSM_ENABLE +#define SDIO_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO_FLAG_CMDACT (SDMMC_STA_CPSMACT | SDMMC_STA_DPSMACT) +#define SDIO_TRANSFER_DIR_TO_SDIO SDMMC_TRANSFER_DIR_TO_SDMMC +#define SDIO_TRANSFER_DIR_TO_CARD SDMMC_TRANSFER_DIR_TO_CARD +#define SDIO_TRANSFER_MODE_BLOCK SDMMC_TRANSFER_MODE_BLOCK +#define SDIO_DPSM_ENABLE SDMMC_DPSM_ENABLE +#define SDIO_DPSM_DISABLE SDMMC_DPSM_DISABLE +#define SDIO_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN /* 1 << 11 */ +#define SDIO_DCTRL_DTMODE_1 SDMMC_DCTRL_DTMODE_1 /* 1<<3 */ +#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR +#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR +#define SDIO_STA_TXACT SDMMC_STA_CPSMACT +#define SDIO_STA_RXACT SDMMC_STA_DPSMACT +#define SDIO_STA_CMDREND SDMMC_STA_CMDREND +#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT +#define SDIO_CMD_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO SDMMC2 + +#define COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS (100000) +#define BUS_LEVEL_MAX_RETRIES 10 + +#define SDIO_CMD_5 5 +#define SDIO_CMD_53 53 + +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!b)?a:b + +extern pinconfig_t PinConfig[]; +extern SD_HandleTypeDef hsd; + +/* for debug prints only */ +//static int num = 0; + +static uint32_t dctrl; + +static whd_driver_t whd_handler; +static cyhal_sdio_irq_handler_t sdio_irq_handler; + +static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +static uint8_t *user_data; +static uint32_t user_data_size; +static uint8_t *dma_data_source; +static uint32_t dma_transfer_size; +static cyhal_transfer_t current_transfer_direction; + +static cy_semaphore_t sdio_transfer_finished_semaphore; +static volatile uint32_t sdio_transfer_failed = 0; +static volatile uint32_t irqstatus = 0; +static int current_command = 0; + +static cy_rslt_t sdio_enable_high_speed(void) +{ + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; + + SDMMC_Init(SDMMC2, sdio_init_structure); + return CY_RSLT_SUCCESS; +} + +static uint32_t find_optimal_block_size(uint32_t data_size) +{ + if (data_size > (uint32_t) 256) { + return 512; + } + if (data_size > (uint32_t) 128) { + return 256; + } + if (data_size > (uint32_t) 64) { + return 128; + } + if (data_size > (uint32_t) 32) { + return 64; + } + if (data_size > (uint32_t) 16) { + return 32; + } + if (data_size > (uint32_t) 8) { + return 16; + } + if (data_size > (uint32_t) 4) { + return 8; + } + if (data_size > (uint32_t) 2) { + return 4; + } + + return 4; +} + +static uint32_t sdio_get_blocksize(uint32_t blocksize) +{ + uint32_t n = 0; + blocksize >>= 1; + while (blocksize) { + n++; + blocksize >>= 1; + } + n <<= 4; + return n; +} + +static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t block_size, uint8_t *data, uint16_t data_size) +{ + /* Setup a single transfer using the temp buffer */ + user_data = data; + user_data_size = data_size; + dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); + + if (direction == CYHAL_WRITE) { + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + memcpy(temp_dma_buffer, data, data_size); + dma_data_source = temp_dma_buffer; + } else { + dma_data_source = (uint8_t *)temp_dma_buffer; + //VIKR + //memset(dma_data_source,0x12,data_size); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Cache-Invalidate the output from DMA */ + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + } + + SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; + SDIO->DLEN = dma_transfer_size; + dctrl = sdio_get_blocksize(block_size) | ((direction == CYHAL_READ) ? SDIO_TRANSFER_DIR_TO_SDIO : SDIO_TRANSFER_DIR_TO_CARD) | SDIO_TRANSFER_MODE_BLOCK | SDIO_DPSM_DISABLE | SDIO_DCTRL_SDIOEN; + SDIO->DCTRL = dctrl; + + SDMMC2->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + SDMMC2->IDMABASE0 = (uint32_t) dma_data_source; +} + +static void sdio_enable_bus_irq(void) +{ + SDMMC2->MASK = SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_CMDREND | SDMMC_IT_CMDSENT; +} + +void SDMMC2_IRQHandler(void) +{ + uint32_t intstatus = SDIO->STA; + + irqstatus = intstatus; + //VIKR | SDIO_STA_STBITERR ) + if ((intstatus & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0) { + WPRINT_WHD_DEBUG(("sdio error flagged\n")); + sdio_transfer_failed = intstatus; + SDIO->ICR = (uint32_t) 0xffffffff; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } else { + if ((intstatus & (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT)) != 0) { + if ((SDMMC2->RESP1 & 0x800) != 0) { + sdio_transfer_failed = irqstatus; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + + /* Clear all command/response interrupts */ + SDMMC2->ICR = (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT); + } + + /* Check whether the external interrupt was triggered */ + if (intstatus & SDMMC_STA_SDIOIT) { + /* Clear the interrupt */ + SDMMC2->ICR = SDMMC_STA_SDIOIT; + /* Inform WICED WWD thread */ + sdio_irq_handler(whd_handler, CYHAL_SDIO_CARD_INTERRUPT); + } + + if (intstatus & SDMMC_STA_DATAEND) { + SDMMC2->ICR = SDMMC_STA_DATAEND; + SDMMC2->DLEN = 0; + SDMMC2->DCTRL = SDMMC_DCTRL_SDIOEN; + SDMMC2->IDMACTRL = SDMMC_DISABLE_IDMA; + SDMMC2->CMD = 0; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + } +} + +//void sdio_dma_irq(void) +//{ +// /* Clear interrupt */ +// DMA2->LIFCR = (uint32_t)(0x3F << 22); +// cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); +//} + +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_SDMMC2_CLK_ENABLE(); + + HAL_GPIO_Init(PinConfig[cmd].port, &PinConfig[cmd].config); + HAL_GPIO_Init(PinConfig[clk].port, &PinConfig[clk].config); + HAL_GPIO_Init(PinConfig[data0].port, &PinConfig[data0].config); + HAL_GPIO_Init(PinConfig[data1].port, &PinConfig[data1].config); + HAL_GPIO_Init(PinConfig[data2].port, &PinConfig[data2].config); + HAL_GPIO_Init(PinConfig[data3].port, &PinConfig[data3].config); + + /* Reset SDIO Block */ + SDMMC_PowerState_OFF(SDMMC2); + __HAL_RCC_SDMMC2_FORCE_RESET(); + __HAL_RCC_SDMMC2_RELEASE_RESET(); + + /* Enable the SDIO Clock */ + __HAL_RCC_SDMMC2_CLK_ENABLE(); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Disable DCache for STM32H7 family */ + SCB_CleanDCache(); + SCB_DisableDCache(); +#endif + + WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); + + // Lower speed configuration + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_INIT_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_1B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + ret = SDMMC_Init(SDMMC2, sdio_init_structure); + ret |= SDMMC_PowerState_ON(SDMMC2); + ret |= SDMMC_SetSDMMCReadWaitMode(SDMMC2, SDMMC_READ_WAIT_MODE_CLK); + if (ret) { + return ret; + } + + /* Clear all SDIO interrupts */ + SDMMC2->ICR = (uint32_t) 0xffffffff; + + /* Turn on SDIO IRQ */ + /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */ + /* otherwise FreeRTOS will not be able to mask the interrupt */ + /* keep in mind that ARMCM7 interrupt priority logic is inverted, the highest value */ + /* is the lowest priority */ + HAL_NVIC_EnableIRQ((IRQn_Type) SDMMC2_IRQn); + HAL_NVIC_SetPriority(SDMMC2_IRQn, 5, 0); + + WPRINT_WHD_DEBUG(("after enable sdio: %p\n", sdio_transfer_finished_semaphore)); + + if (cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0) != WHD_SUCCESS) { + WPRINT_WHD_DEBUG(("Deinitializing semaphore: %p\n", sdio_transfer_finished_semaphore)); + cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); + return -1; + } + + WPRINT_WHD_DEBUG(("cy_rtos_init_semaphore: %p\n", sdio_transfer_finished_semaphore)); + + return CY_RSLT_SUCCESS; +} + +void cyhal_sdio_free(cyhal_sdio_t *obj) +{ + //TODO +} + +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) +{ + return sdio_enable_high_speed(); +} + +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t *response) +{ + uint32_t loop_count = 0; + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t temp_sta; + + if (response != NULL) { + *response = 0; + } + current_command = 0; + +restart: + SDIO->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + result = -1; + goto exit; + } + + /* Send the command */ + SDIO->ARG = argument; + SDIO->CMD = (uint32_t)(command | SDIO_RESPONSE_SHORT | SDIO_WAIT_NO | SDIO_CPSM_ENABLE); + loop_count = (uint32_t) COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS; + do { + temp_sta = SDIO->STA; + loop_count--; + if (loop_count == 0 /*|| ((response != NULL) && ((temp_sta & SDIO_ERROR_MASK) != 0))*/) { + WPRINT_WHD_DEBUG(("Restart single access loop count %ld stat %lx\n", loop_count, temp_sta)); + HAL_Delay(10U); + goto restart; + } + } while ((temp_sta & SDIO_FLAG_CMDACT) != 0); + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + if (result) { + WPRINT_WHD_ERROR(("SDIO->POWER %lx \n", SDIO->POWER)); + WPRINT_WHD_ERROR(("SDIO->CLKCR %lx \n", SDIO->CLKCR)); + WPRINT_WHD_ERROR(("result %lx \n", result)); + WPRINT_WHD_ERROR(("cyhal_sdio_send_cmd %s\n", (result == 0) ? "Passed" : "Failed")); + //while (1); + } + SDMMC2->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 0x%x arg 0x%x resp 0x%x\n",num++,(direction!=CYHAL_READ)?"Write":"Read",command,argument,(response)?*response:0)); + return result; +} + +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length, uint32_t *response) +{ + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t block_size = 64; + sdio_cmd_argument_t arg; + uint32_t cmd; + current_command = SDIO_CMD_53; + current_transfer_direction = direction; + arg.value = argument; + + sdio_enable_bus_irq(); + if (response != NULL) { + *response = 0; + } + +restart: + sdio_transfer_failed = 0; + SDMMC2->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + WPRINT_WHD_ERROR(("Too much attempt\n")); + result = -1; + goto exit; + } + + /* Dodgy STM32 hack to set the CMD53 byte mode size to be the same as the block size */ + if (arg.cmd53.block_mode == 0) { + block_size = find_optimal_block_size(arg.cmd53.count); + if (block_size < SDIO_512B_BLOCK) { + arg.cmd53.count = block_size; + } else { + arg.cmd53.count = 0; + } + argument = arg.value; + } + + SDMMC2->CMD |= SDMMC_CMD_CMDTRANS; + + /* Prepare the SDIO for a data transfer */ + sdio_prepare_data_transfer(direction, block_size, (uint8_t *) data, (uint32_t) length); + + /* Send the command */ + //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); + SDMMC2->ARG = argument; + cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); + SDMMC2->CMD = cmd; + + /* Wait for the whole transfer to complete */ + //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); + result = cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 50, WHD_FALSE); + + if (result != CY_RSLT_SUCCESS) { + WPRINT_WHD_ERROR(("failed getting semaphore\n")); + goto exit; + } + if (sdio_transfer_failed) { + WPRINT_WHD_DEBUG(("try again sdio_transfer_failed %"PRIu32" irq %"PRIu32"\n", sdio_transfer_failed, irqstatus)); + goto restart; + } + /* Check if there were any SDIO errors */ + if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); + goto restart; + } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); + goto restart; + } + + if (direction == CYHAL_READ) { + memcpy(user_data, dma_data_source, (size_t) user_data_size); + } + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + SDMMC2->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 53 argument %lx datasize %d blocknumber 0x%x cmdis %lx %lu dctrl = %x\n", num++, (direction != CYHAL_READ) ? "Write" : "Read", argument, length, arg.cmd53.count, cmd, cmd, dctrl)); + + return result; +} + +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) +{ + return false; +} + +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +{ + whd_handler = (whd_driver_t)handler_arg; + sdio_irq_handler = handler; +} + +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intr_priority, bool enable) +{ + //TODO +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_spi.c new file mode 100644 index 00000000000..162c7a6801f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_spi.c @@ -0,0 +1,29 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides stubs for the WHD driver needed by ARMClang + */ + +#include +#include +#include "cyhal_spi.h" + +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_system.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_system.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_system.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_bd.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_bd.h new file mode 100644 index 00000000000..578b2d9e4eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_bd.h @@ -0,0 +1,49 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" +#include "BlockDevice.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * Mount the physical device + * + * This assumes that the device is ready to read/write immediately. + * + * @param[in] device - physical media to init + * @param[out] fs_handle_out - Receives the filesystem handle. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount(mbed::BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp new file mode 100644 index 00000000000..d66225ffd07 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -0,0 +1,220 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#include +#include +#include +#include +#include "sockets.h" +#include "resources.h" +#include "wiced_filesystem.h" +#include "wiced_bd.h" +#include "QSPIFBlockDevice.h" +#include "MBRBlockDevice.h" +#include "FATFileSystem.h" + +#define WIFI_DEFAULT_FIRMWARE_PATH "/wlan/4343WA1.BIN" +#define WIFI_DEFAULT_MOUNT_NAME "wlan" +#define WIFI_DEFAULT_PARTITION 1 +#define WIFI_DEFAULT_FS 0 + +BlockDevice *qspi_bd = NULL; +MBRBlockDevice *mbr_bd = NULL; +FATFileSystem *wifi_fs = NULL; + +wiced_filesystem_t resource_fs_handle; + +MBED_WEAK BlockDevice *BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PF_9, PE_2, PD_13, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} + +MBED_WEAK void wiced_filesystem_mount_error(void) +{ + WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK void wiced_filesystem_firmware_error(void) +{ + WPRINT_WHD_ERROR(("Please run the \"PortentaWiFiFirmwareUpdater\" sketch once to install the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int mount_err) +{ + DIR *dir; + struct dirent *ent; + std::string dir_name(mounted_name); + if (mount_err) { + wiced_filesystem_mount_error(); + } else { + if ((dir = opendir(mounted_name)) != NULL) { + // print all the files and directories within directory + while ((ent = readdir(dir)) != NULL) { + std::string fullname = "/" + dir_name + "/" + std::string(ent->d_name); + if (fullname == WIFI_DEFAULT_FIRMWARE_PATH) { + closedir(dir); + return WICED_SUCCESS; + } + } + closedir(dir); + } + wiced_filesystem_firmware_error(); + } + return WICED_ERROR; +} + +static wiced_result_t whd_default_firmware_restore(void) +{ +#if MBED_CONF_APP_WIFI_FIRMWARE_RESTORE + size_t ret; + FILE *fp; + + //This should only happen the firs time or if the partition table has been overwritten i.e QSPI tests + WPRINT_WHD_DEBUG(("MBRBlockDevice init failed, repatitioning\n\r")); + if (mbr_bd->partition(qspi_bd, 1, 0x0B, 0, 1024 * 1024) != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice repatitioning OK, reinit\n\r")); + + if (mbr_bd->init() != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice init OK\n\r")); + + wifi_fs = new FATFileSystem(WIFI_DEFAULT_MOUNT_NAME); + + if (wifi_fs->reformat(mbr_bd) != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("FATFileSystem reformat and mount OK\n\r")); + + fp = fopen(WIFI_DEFAULT_FIRMWARE_PATH, "wb"); + if (fp == NULL) { + return WICED_ERROR; + } + ret = fwrite(wifi_firmware_image_data, wifi_firmware_image.size, 1, fp); + if (ret != wifi_firmware_image.size) { + return WICED_ERROR; + } + fclose(fp); + + if (mbr_bd->sync() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Sync BlockDevice OK\n\r")); + + if (wifi_fs->unmount() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Unmount FS\n\r")); + wifi_fs = NULL; +#endif + + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_init(void) +{ + if (mbr_bd == NULL && wifi_fs == NULL) { + WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); + qspi_bd = mbed::BlockDevice::get_default_instance(); + + if (qspi_bd->init() == BD_ERROR_OK) { + mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); + if (mbr_bd->init() == BD_ERROR_OK) { + return WICED_SUCCESS; + } else { + return whd_default_firmware_restore(); + } + } + return WICED_ERROR; + } else { + WPRINT_WHD_DEBUG(("FileSystem initialized with user settings\n\r")); + return WICED_SUCCESS; + } +} + +wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) +{ + wifi_fs = new FATFileSystem(mounted_name); + + int err = wifi_fs->mount(device); + whd_firmware_check_hook(mounted_name, err); + if (!err) { + //fs_handle_out = wifi_fs + return WICED_SUCCESS; + } + return WICED_ERROR; +} + +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) +{ + /* This is called by mbed test system */ + //if (mbr_bd == NULL && wifi_fs == NULL) { + // wiced_filesystem_init(); + //} + //This can be called from user sketch to provide custom block device and mount point before WiFi.beginAP or WiFi.begin + if (wifi_fs == NULL) { + wiced_filesystem_mount(mbr_bd, WIFI_DEFAULT_FS, fs_handle, WIFI_DEFAULT_MOUNT_NAME); + } + + if (wifi_fs == NULL) { + return WICED_ERROR; + } + + *file_handle_out = open(filename, mode); + if (*file_handle_out == -1) { + return WICED_ERROR; + } + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + lseek(*file_handle, offset, whence); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + *returned_bytes_count = read(*file_handle, data, bytes_to_read); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + close(*file_handle); + return WICED_SUCCESS; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h new file mode 100644 index 00000000000..a65aa3c1489 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h @@ -0,0 +1,139 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************** + * Enumerations + ******************************************************/ + +typedef enum { + WICED_FILESYSTEM_OPEN_FOR_READ, /** Specifies read access to the object. Data can be read from the file - equivalent to "r" or "rb" */ + WICED_FILESYSTEM_OPEN_FOR_WRITE, /** Specifies read/write access to the object. Data can be written to the file - equivalent to "r+" or "rb+" or "r+b" */ + WICED_FILESYSTEM_OPEN_WRITE_CREATE, /** Opens for read/write access, creates it if it doesn't exist */ + WICED_FILESYSTEM_OPEN_ZERO_LENGTH, /** Opens for read/write access, Truncates file to zero length if it exists, or creates it if it doesn't - equivalent to "w+", "wb+" or "w+b" */ + WICED_FILESYSTEM_OPEN_APPEND, /** Opens for read/write access, places the current location at the end of the file ready for appending - equivalent to "a", "ab" */ + WICED_FILESYSTEM_OPEN_APPEND_CREATE, /** Opens for read/write access, creates it if it doesn't exist, and places the current location at the end of the file ready for appending - equivalent to "a+", "ab+" or "a+b" */ +} wiced_filesystem_open_mode_t; + +typedef enum { + WICED_FILESYSTEM_SEEK_SET = SEEK_SET, /* Offset from start of file */ + WICED_FILESYSTEM_SEEK_CUR = SEEK_CUR, /* Offset from current position in file */ + WICED_FILESYSTEM_SEEK_END = SEEK_END, /* Offset from end of file */ +} wiced_filesystem_seek_type_t; + +typedef enum { + WICED_SUCCESS = 0, + WICED_ERROR = 1 +} wiced_result_t; + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * File-system Handle Structure + */ +typedef int wiced_filesystem_t; + +/** + * File Handle Structure + * + */ +typedef int wiced_file_t; + +/** + * File-system type Handle Structure + */ +typedef int wiced_filesystem_handle_type_t; + +/** + * Initialise the BlockDevice and filesystem module + * + * Initialises the BlockDevice and filesystem module before mounting a physical device. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_init(void); + +/** + * Open a file for reading or writing + * + * @param[in] fs_handle - The filesystem handle to use - obtained from wiced_filesystem_mount + * @param[out] file_handle_out - a pointer to a wiced_file_t structure which will receive the + * file handle after it is opened + * @param[in] filename - The filename of the file to open + * @param[in] mode - Specifies read or write access + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode); + +/** + * Seek to a location within a file + * + * This is similar to the fseek() in ISO C. + * + * @param[in] file_handle - The file handle on which to perform the seek. + * Must have been previously opened with wiced_filesystem_fopen. + * @param[in] offset - The offset in bytes + * @param[in] whence - WICED_FILESYSTEM_SEEK_SET = Offset from start of file + * WICED_FILESYSTEM_SEEK_CUR = Offset from current position in file + * WICED_FILESYSTEM_SEEK_END = Offset from end of file + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence); + +/** + * Reads data from a file into a memory buffer + * + * @param[in] file_handle - the file handle to read from + * @param[out] data - A pointer to the memory buffer that will + * receive the data that is read + * @param[in] bytes_to_read - the number of bytes to read + * @param[out] returned_item_count - the number of items successfully read. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count); + +/** + * Close a file + * + * This is similar to the fclose() in ISO C. + * + * @param[in] file_handle - the file handle to close + * + * @return WICED_SUCCESS = success + */ +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt new file mode 100644 index 00000000000..cbb51f9c99e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, July 2019 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named �DEPENDENCIES� and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c new file mode 100644 index 00000000000..ddaf0f7188f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c @@ -0,0 +1,25493 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_image_data[421098] = { + 0, 0, 0, 0, 237, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 0, 72, 0, 71, 237, 33, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 68, 66, 80, 80, 128, 109, 4, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 149, 212, 1, 0, 223, 145, 2, 0, 59, 146, 2, 0, 73, 140, + 2, 0, 193, 137, 2, 0, 13, 137, 2, 0, 85, 138, 2, 0, 203, 135, 2, 0, + 167, 136, 2, 0, 181, 146, 2, 0, 189, 146, 2, 0, 141, 135, 2, 0, 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98, 116, 99, 120, 104, 121, 98, 114, 105, + 100, 104, 119, 45, 110, 111, 99, 108, 109, 105, 110, 99, 45, 99, 108, + 109, 95, 109, 105, 110, 45, 102, 98, 116, 45, 109, 102, 112, 45, 115, + 97, 101, 45, 116, 107, 111, 32, 86, 101, 114, 115, 105, 111, 110, 58, + 32, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, 52, + 51, 48, 51, 32, 67, 89, 41, 32, 67, 82, 67, 58, 32, 101, 54, 98, 55, + 57, 50, 97, 54, 32, 68, 97, 116, 101, 58, 32, 84, 104, 117, 32, 50, + 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, 52, 51, 58, 53, + 51, 32, 80, 83, 84, 32, 85, 99, 111, 100, 101, 32, 86, 101, 114, 58, + 32, 49, 48, 52, 51, 46, 50, 49, 51, 55, 32, 70, 87, 73, 68, 32, 48, + 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, + 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 +}; +resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c new file mode 100644 index 00000000000..616bdedf2e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_clm_blob_image_data[7222] = { + 66, 76, 79, 66, 60, 0, 0, 0, 132, 159, 16, 216, 1, 0, 0, 0, 2, 0, 0, + 0, 0, 0, 0, 0, 60, 0, 0, 0, 246, 27, 0, 0, 183, 10, 32, 40, 0, 0, 0, + 0, 0, 0, 0, 0, 50, 28, 0, 0, 4, 0, 0, 0, 42, 255, 237, 159, 0, 0, 0, + 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, 57, 46, 49, 48, + 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 46, 50, 57, 46, + 52, 0, 0, 0, 0, 0, 0, 0, 0, 184, 10, 0, 0, 67, 108, 109, 73, 109, 112, + 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, 109, 45, 48, 46, 48, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 49, 0, 81, 50, 0, 3, 3, 3, 9, 3, 11, + 4, 4, 4, 7, 4, 8, 4, 10, 4, 11, 5, 7, 8, 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20, 28, 38, 2, 2, + 84, 20, 1, 112, 38, 1, 4, 0, 255, 1, 23, 18, 2, 1, 84, 18, 1, 20, 1, + 255, 2, 23, 20, 30, 49, 2, 2, 84, 20, 1, 84, 49, 1, 21, 1, 255, 3, 23, + 20, 30, 37, 30, 46, 2, 2, 84, 21, 1, 84, 46, 1, 26, 1, 255, 3, 23, 20, + 24, 39, 30, 49, 2, 1, 84, 25, 1, 26, 1, 255, 3, 23, 20, 24, 39, 30, + 49, 2, 1, 84, 25, 1, 17, 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 20, 1, + 112, 40, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 30, + 49, 0, 1, 78, 49, 1, 14, 0, 255, 2, 27, 19, 27, 49, 2, 2, 84, 19, 1, + 84, 49, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 20, + 49, 2, 1, 76, 49, 1, 33, 0, 255, 1, 20, 48, 2, 1, 76, 48, 1, 31, 2, + 255, 2, 17, 33, 30, 49, 0, 2, 68, 33, 1, 68, 49, 1, 30, 2, 255, 3, 17, + 33, 24, 38, 30, 49, 0, 3, 56, 33, 1, 68, 38, 1, 68, 49, 1, 28, 2, 255, + 3, 17, 28, 24, 38, 30, 49, 0, 3, 56, 28, 1, 58, 38, 1, 62, 49, 1, 33, + 0, 255, 1, 27, 48, 2, 1, 84, 48, 1, 0, 0, 3, 0, 0, 0, 120, 11, 0, 0, + 16, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1, 18, + 1, 255, 1, 52, 1, 14, 1, 15, 3, 28, 39, 49, 2, 19, 49, 166, 169, 0, + 0 +}; +const resource_hnd_t wifi_firmware_clm_blob = { RESOURCE_IN_MEMORY, 7222, {.mem = { (const char *) wifi_firmware_clm_blob_image_data }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h new file mode 100644 index 00000000000..01bad9226f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Automatically generated file - this comment ensures resources.h file creation */ +/* Auto-generated header file. Do not edit */ +#ifndef INCLUDED_RESOURCES_H_ +#define INCLUDED_RESOURCES_H_ +#include "wiced_resource.h" +#include "wiced_filesystem.h" + +extern wiced_filesystem_t resource_fs_handle; + +extern const resource_hnd_t wifi_firmware_image; +extern const unsigned char wifi_firmware_image_data[421098]; +extern const resource_hnd_t wifi_firmware_clm_blob; +extern const unsigned char wifi_firmware_clm_blob_image_data[7222]; + +#endif /* ifndef INCLUDED_RESOURCES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h new file mode 100644 index 00000000000..3f2279c2be9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * NVRAM file for CY8CKIT-062-WiFi-BT (PSoC6 WiFi-BT Pioneer Kit) using + * Murata's Type 1DX module - Copied from bcm94343wwcd1.txt on 08/04/2019 + * # 2.4 GHz, 20 MHz BW mode; No Antenna Diversity + */ + +#ifndef INCLUDED_NVRAM_IMAGE_H_ +#define INCLUDED_NVRAM_IMAGE_H_ + +#include +#include +#include "generated_mac_address.txt" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Character array of NVRAM image + * + * Generated from cyw94343cy8ckit-062-wifi-bt.txt + */ + +static const char wifi_nvram_image[] = + "manfid=0x2d0" "\x00" + "prodid=0x0726" "\x00" + "vendid=0x14e4" "\x00" + "devid=0x43e2" "\x00" + "boardtype=0x0726" "\x00" + "boardrev=0x1202" "\x00" + "boardnum=22" "\x00" + NVRAM_GENERATED_MAC_ADDRESS "\x00" + "sromrev=11" "\x00" + "boardflags=0x00404201" "\x00" + "boardflags3=0x04000000" "\x00" + "xtalfreq=37400" "\x00" + "nocrc=1" "\x00" + "ag0=0" "\x00" + "aa2g=1" "\x00" + "ccode=ALL" "\x00" + "extpagain2g=0" "\x00" + "pa2ga0=-145,6667,-751" "\x00" + "AvVmid_c0=0x0,0xc8" "\x00" + "cckpwroffset0=2" "\x00" + "maxp2ga0=74" "\x00" + "cckbw202gpo=0" "\x00" + "legofdmbw202gpo=0x88888888" "\x00" + "mcsbw202gpo=0xaaaaaaaa" "\x00" + "propbw202gpo=0xdd" "\x00" + "ofdmdigfilttype=18" "\x00" + "ofdmdigfilttypebe=18" "\x00" + "papdmode=1" "\x00" + "papdvalidtest=1" "\x00" + "pacalidx2g=48" "\x00" + "papdepsoffset=-22" "\x00" + "papdendidx=58" "\x00" + "il0"NVRAM_GENERATED_MAC_ADDRESS "\x00" + "wl0id=0x431b" "\x00" + "muxenab=0x10" "\x00" + "\x00\x00"; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ + +#error Wi-Fi NVRAM image included twice + +#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/whd_config.h new file mode 100644 index 00000000000..690b586bc55 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/whd_config.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides configuration for WHD driver on Arduino Portenta H7 + */ + +#ifndef __WHD_CONFIG__ +#define __WHD_CONFIG__ + +#include "whd_types.h" +#include "stm32h7xx_hal.h" +#include + +/* disable WPRINT_MACRO */ +#define WHD_PRINT_DISABLE + +/* please define your configuration , either SDIO or SPI */ +#define CY_WHD_CONFIG_USE_SDIO +//#define CY_WHD_CONFIG_USE_SPI + +/* select resource implementation */ +#define USES_RESOURCE_GENERIC_FILESYSTEM + +/* if not defined default value is 2 */ +#define CY_WIFI_OOB_INTR_PRIORITY 0 + +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_FALL +#define CYBSP_WIFI_HOST_WAKE CYBSP_SDIO_OOB_IRQ + +#define BSP_LED1 {GPIOK,{.Pin= GPIO_PIN_5 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED2 {GPIOK,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED3 {GPIOK,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} + +/* power pin */ +#define WIFI_WL_REG_ON {GPIOG,{.Pin= GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +//#define WIFI_32K_CLK {GPIOA,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW , .Alternate = GPIO_AF0_MCO}} + +#define WIFI_SDIO_CMD {GPIOD,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF11_SDIO2}} +#define WIFI_SDIO_CLK {GPIOD,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF11_SDIO2}} +#define WIFI_SDIO_D0 {GPIOB,{.Pin= GPIO_PIN_14, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF9_SDIO2}} +#define WIFI_SDIO_D1 {GPIOB,{.Pin= GPIO_PIN_15, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF9_SDIO2}} +#define WIFI_SDIO_D2 {GPIOG,{.Pin= GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF10_SDIO2}} +#define WIFI_SDIO_D3 {GPIOB,{.Pin= GPIO_PIN_4 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF9_SDIO2}} +#define WIFI_SDIO_OOB_IRQ {GPIOD,{.Pin= GPIO_PIN_15 , .Mode = GPIO_MODE_IT_FALLING , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH}} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c new file mode 100644 index 00000000000..c6e8b9cc078 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c @@ -0,0 +1,583 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 // Connected to ARD_A2 + {PA_0C_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INN1 // Connected to ARD_A2 + {PA_0C_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INN1 // Connected to ARD_A2 + {PA_0C_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 // Connected to ARD_A2 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INN16 // Connected to ETH_REF_CLK + {PA_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 // Connected to ETH_REF_CLK + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 // Connected to ARD_A3 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 // Connected to ARD_A3 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 // Connected to ETH_MDIO + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 // Connected to ETH_MDIO + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 // Connected to ULPI_D0 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 // Connected to ULPI_D0 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INN18 // Connected to ULPI_CK + {PA_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 // Connected to ULPI_CK + {PA_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INN18 // Connected to ULPI_CK + {PA_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 // Connected to ULPI_CK + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INN3 // Connected to ETH_CRS_DV + {PA_7_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 // Connected to ETH_CRS_DV + {PA_7_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INN3 // Connected to ETH_CRS_DV + {PA_7_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 // Connected to ETH_CRS_DV + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INN5 // Connected to ULPI_D1 + {PB_0_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 // Connected to ULPI_D1 + {PB_0_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INN5 // Connected to ULPI_D1 + {PB_0_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 // Connected to ULPI_D1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 // Connected to ULPI_D2 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 // Connected to ULPI_D2 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 // Connected to ULPI_STP + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 // Connected to ULPI_STP + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 // Connected to ULPI_STP + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to ETH_MDC/SAI4_D1 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INN11 // Connected to PMOD\#3 + {PC_2_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 // Connected to PMOD\#3 + {PC_2_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INN11 // Connected to PMOD\#3 + {PC_2_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 // Connected to PMOD\#3 + {PC_2_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INN11 // Connected to PMOD\#3 + {PC_2_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 // Connected to PMOD\#3 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 // Connected to ARD_A4 + {PC_2C_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INN1 // Connected to ARD_A4 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INN12 // Connected to PMOD\#2 + {PC_3_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 // Connected to PMOD\#2 + {PC_3_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INN12 // Connected to PMOD\#2 + {PC_3_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 // Connected to PMOD\#2 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 // Connected to ARD_A5 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 // Connected to ETH_RXD0 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 // Connected to ETH_RXD0 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INN4 // Connected to ETH_RXD1 + {PC_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 // Connected to ETH_RXD1 + {PC_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INN4 // Connected to ETH_RXD1 + {PC_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 // Connected to ETH_RXD1 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 // Connected to FMC_A3 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INN5 // Connected to FMC_A4 + {PF_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 // Connected to FMC_A4 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 // Connected to FMC_A5 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INN4 // Connected to QSPI_BK1_IO3 + {PF_6_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 // Connected to QSPI_BK1_IO3 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 // Connected to QSPI_BK1_IO2 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 // Connected to PMOD\#14/ARD_D3 + {PF_8_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INN3 // Connected to PMOD\#14/ARD_D3 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 // Connected to QSPI_BK1_IO1 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 // Connected to ARD_A1 + {PF_10_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INN2 // Connected to ARD_A1 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 // Connected to FMC_SDRAS + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INN2 // Connected to FMC_A6 + {PF_12_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 // Connected to FMC_A6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 // Connected to FMC_A7 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INN2 // Connected to FMC_A8 + {PF_14_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 // Connected to FMC_A8 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 // Connected to QSPI_BK2_IO0 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INN13 // Connected to QSPI_BK2_IO1 + {PH_3_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 // Connected to QSPI_BK2_IO1 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INN14 // Connected to ULPI_NXT + {PH_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 // Connected to ULPI_NXT + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INN15 // Connected to FMC_SDNWE + {PH_5_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 // Connected to FMC_SDNWE + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to ULPI_CK + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_D4 + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SDIO1_D1 + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_A0 + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_A9 + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_SDNWE + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to FMC_D16 + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_D20 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to CEC_CK/MCO1 + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to HDMI_CEC + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, // Connected to HDMI_CEC + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_D3 + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_A1 + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_A8 + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_NXT + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to FMC_SDCKE1 + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_D19 + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D0 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ULPI_D0 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ULPI_D0 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ULPI_CK + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ULPI_CK + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ETH_CRS_DV + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to ETH_CRS_DV + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to CEC_CK/MCO1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to PMOD\#1 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ULPI_D1 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to ULPI_D1 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ULPI_D1 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ULPI_D2 + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to ULPI_D2 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ULPI_D2 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ULPI_D7 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to HDMI_CEC + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to HDMI_CEC + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ULPI_D3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ULPI_D6 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to PMOD\#9 + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to PMOD\#9 + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to PMOD\#9 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to PMOD\#8 + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to PMOD\#8 + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 // Connected to PMOD\#8 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SDIO1_D0 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to SDIO1_D0 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SDIO1_D1 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to SDIO1_D1 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to FMC_D0 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to FMC_D1 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to SAI1_FS_A + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to SAI1_SCK_A + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to SAI1_SD_A + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to FMC_D5 + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to FMC_D6 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to FMC_D7 + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to FMC_D8 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to FMC_D9 + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to FMC_D10 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to FMC_D11 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to QSPI_BK1_IO3 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 // Connected to QSPI_BK1_IO2 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to PMOD\#14/ARD_D3 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to PMOD\#14/ARD_D3 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to QSPI_BK1_IO1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N // Connected to QSPI_BK1_IO1 + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to FMC_SDNE1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 // Connected to FMC_D17 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to FMC_D18 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to FMC_D19 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to FMC_D20 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to FMC_D21 + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to FMC_D22 + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to FMC_D23 +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to FMC_D24 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to FMC_D26 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to FMC_NBL3 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to FMC_D28 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to FMC_D29 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to ARD_D9 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D6 + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ARD_D1 + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to ARD_D1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to ARD_D0 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D0 + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ARD_D11 + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to ARD_D11 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to ARD_D12 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D12 + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ARD_D13 + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to ARD_D13 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to ARD_D10 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ARD_D10 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to SPI2_SCK + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to HDMI_CEC + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to HDMI_CEC + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D3 + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D6 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to PMOD\#9 + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SDIO1_D2 + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to SDIO1_D2 + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_CK + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D3 + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to FMC_D13 + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL1 + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D5 + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO2 + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to QSPI_BK2_IO3 + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D21 + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to ARD_D1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ETH_REF_CLK + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ULPI_D0 + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to CEC_CK/MCO1 + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to PMOD\#1 + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D7 + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D4 + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D5 + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to PMOD\#8 + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SDIO1_D3 + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to SDIO1_D3 + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D2 + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_CMD + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to FMC_D14 + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL0 + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D4 + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO3 + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to QSPI_BK2_IO2 + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D22 + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D30 + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to ARD_D0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI2_SCK + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD\#9 + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#9 + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_D0 + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_D1 + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D6 + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to PMOD\#14/ARD_D3 + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to FMC_SDCLK + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PMOD\#1 + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1 + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ULPI_D1 + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D6 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#8 + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_D1 + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to QSPI_BK1_IO0 + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_D0 + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D7 + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO1 + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD0 + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to FMC_SDCAS + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_CRS_DV + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ETH_CRS_DV + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to QSPI_CLK + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ULPI_D7 + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to ULPI_D7 + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ULPI_D7 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#8 + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_MDC/SAI4_D1 + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#2 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_CK + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPDIF_RX0 + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_SD_A + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D11 + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO1 + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDRAS + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to QSPI_BK2_IO3 + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D27 + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D11 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#9 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#3 + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_D3 + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_SCK_A + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D10 + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to PMOD\#14/ARD_D3 + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_BK2_IO2 + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ETH_TXD1 + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDCKE1 + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D26 + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D12 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ULPI_CK + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ULPI_CK +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to STDIO_UART_TX + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_SCK + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D3 + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D6 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_D2 + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D9 + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO2 + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_TX_EN + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ETH_TXD0 + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDNE1 + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D25 + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D13 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#1 + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D5 + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_FS_A + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D8 + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO3 + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to FMC_SDCLK + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDNWE + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D24 + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D10 + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to PMOD\#1 + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D7 + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D5 + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D2 + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D22 + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D30 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to SPI2_SCK + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to HDMI_CEC + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D6 + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D3 + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D21 + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SDIO1_D1 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to PMOD\#14/ARD_D3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SDIO1_D2 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ETH_REF_CLK + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to ARD_A1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to HDMI_CEC + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF // Connected to CEC_CK/MCO1 +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to STDIO_UART_TX +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID // Connected to STDIO_UART_RX + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM // Connected to PMOD\#1 + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP // Connected to SPI2_SCK + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID // Connected to ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS // Connected to ULPI_D6 + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM // Connected to PMOD\#9 + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP // Connected to PMOD\#8 +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 // Connected to ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK // Connected to ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 // Connected to ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 // Connected to ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 // Connected to ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 // Connected to ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 // Connected to ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 // Connected to ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP // Connected to ULPI_STP + {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR // Connected to PMOD\#3 + {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT // Connected to PMOD\#2 +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PinNames.h new file mode 100644 index 00000000000..9f14a66d67e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PinNames.h @@ -0,0 +1,474 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ALTC 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + + PA_0 = 0x00, + PA_0C = PA_0 | ALTC, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | ALTC, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | ALTC, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | ALTC, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_9_ALT0, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PA_10_ALT0, +#endif + + WL_REG_ON = PG_4, + WL_HOST_WAKE = PD_15, + WL_SDIO_0 = PB_14, + WL_SDIO_1 = PB_15, + WL_SDIO_2 = PG_11, + WL_SDIO_3 = PB_4, + WL_SDIO_CMD = PD_7, + WL_SDIO_CLK = PD_6, + + //Led mappings + LED_RED = PE_3, //Red + LED_GREEN = PC_13, //Green + LED_BLUE = PF_4, //Blue + + //mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + + CYBSP_BT_UART_RX = PB_7, + CYBSP_BT_UART_TX = PB_6, + CYBSP_BT_UART_RTS = PA_12, + CYBSP_BT_UART_CTS = PA_11, + + CYBSP_BT_POWER = PF_14, + CYBSP_BT_HOST_WAKE = PD_14, + CYBSP_BT_DEVICE_WAKE = PE_9, + + USER_BUTTON = PC_13, + + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = CONSOLE_TX, // Virtual Com Port + SERIAL_RX = CONSOLE_RX, // Virtual Com Port + I2C_SCL = PB_8, + I2C_SDA = PB_9, + PWM_OUT = PD_15, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PD_11, + QSPI_FLASH1_IO1 = PF_9, + QSPI_FLASH1_IO2 = PE_2, + QSPI_FLASH1_IO3 = PD_13, + QSPI_FLASH1_SCK = PF_10, + QSPI_FLASH1_CSN = PG_6, + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_DIR_ALT0 = PC_2C, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_NXT_ALT0 = PC_3C, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + DEBUG_JTCK_SWCLK = PA_14, + DEBUG_JTDI = PA_15, + DEBUG_JTDO_SWO = PB_3, + DEBUG_JTMS_SWDIO = PA_13, + DEBUG_JTRST = PB_4, + DEBUG_TRACECLK = PE_2, + DEBUG_TRACED0 = PE_3, + DEBUG_TRACED0_ALT0 = PG_13, + DEBUG_TRACED0_ALT1 = PC_1, + DEBUG_TRACED1 = PE_4, + DEBUG_TRACED1_ALT0 = PG_14, + DEBUG_TRACED1_ALT1 = PC_8, + DEBUG_TRACED2 = PE_5, + DEBUG_TRACED2_ALT0 = PD_2, + DEBUG_TRACED3 = PC_12, + DEBUG_TRACED3_ALT0 = PE_6, + DEBUG_TRGIN = PJ_7, + DEBUG_TRGIO = PC_7, + DEBUG_TRGOUT = PJ_12, + PWR_PVD_IN = PB_7, + PWR_WKUP0 = PA_0, + PWR_WKUP1 = PA_2, + PWR_WKUP2 = PC_13, + PWR_WKUP3 = PI_8, + PWR_WKUP4 = PI_11, + PWR_WKUP5 = PC_1, + + /**** STMOD+ pins ****/ +#ifdef STMOD_UART_SOLDERBRIDGE + STMOD_1 = PA_0, + STMOD_2 = PD_5, + STMOD_3 = PD_6, + STMOD_4 = PD_4, +#else /* default HW configuration */ + STMOD_1 = PA_11, + STMOD_2 = PC_3, + STMOD_3 = PC_2, + STMOD_4 = PA_12, +#endif /* STMOD_UART_SOLDERBRIDGE */ +// STMOD_5 is connected to GND +// STMOD_6 is connected to +5V + STMOD_7 = PD_12, + STMOD_8 = PB_15, + STMOD_9 = PB_14, + STMOD_10 = PD_13, + STMOD_11 = PC_6, + STMOD_12 = PJ_13, + STMOD_13 = PA_4, + STMOD_14 = PF_8, +// STMOD_15 is connected to +5V +// STMOD_16 is connected to GND + STMOD_17 = PC_7, + STMOD_18 = PD_3, + STMOD_19 = PB_9, + STMOD_20 = PB_8, + + /**** PMOD pins ****/ + PMOD_1 = STMOD_1, + PMOD_2 = STMOD_2, + PMOD_3 = STMOD_3, + PMOD_4 = STMOD_4, +// PMOD_5 is connected to GND +// PMOD_6 is connected to +3V3 + PMOD_7 = STMOD_11, + PMOD_8 = STMOD_12, +// PMOD_9 is not connected +// PMOD_10 is not connected +// PMOD_11 is connected to GND +// PMOD_12 is connected to +3V3 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/system_clock_override.c new file mode 100644 index 00000000000..12729780383 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/system_clock_override.c @@ -0,0 +1,306 @@ +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2020 Arduino SA. + * All rights reserved.

+ * + * SPDX-License-Identifier: BSD-3-Clause + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 480 + * AHBCLK (MHz) | 240 + * APB1CLK (MHz) | 120 + * APB2CLK (MHz) | 120 + * APB3CLK (MHz) | 120 + * APB4CLK (MHz) | 120 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ + + bool lowspeed = false; +#if defined(LOWSPEED) && (LOWSPEED == 1) + lowspeed = true; +#endif + +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } +} + +static const uint32_t _keep; +bool isBootloader() { + return ((uint32_t)&_keep < 0x8040000); +} + +bool isBetaBoard() { + uint8_t* bootloader_data = (uint8_t*)(0x801F000); + if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { + return true; + } else { + return (bootloader_data[10] == 27); + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) { + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; + } + } + + /* Enable oscillator pin */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + GPIO_InitTypeDef gpio_osc_init_structure; + gpio_osc_init_structure.Pin = GPIO_PIN_1; + gpio_osc_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_osc_init_structure.Pull = GPIO_PULLUP; + gpio_osc_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure); + HAL_Delay(10); + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1); + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); +#endif + /* Configure the main internal regulator output voltage */ + + if (lowspeed) { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + } else { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + } + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 40; + } else { + RCC_OscInitStruct.PLL.PLLN = 160; + } + +#if HSE_VALUE == 27000000 + RCC_OscInitStruct.PLL.PLLM = 9; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 80; + } else { + RCC_OscInitStruct.PLL.PLLN = 300; + } +#endif + + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (lowspeed) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + return 0; // FAIL + } else { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + return 0; // FAIL + } + + // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); + +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + __HAL_RCC_CSI_ENABLE() ; + + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO); +#endif + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if defined (CORE_CM4) +void HSEM2_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif + +#if defined (CORE_CM7) +void HSEM1_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif diff --git a/targets/targets.json b/targets/targets.json index 5e957dba707..b0c4328b760 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3588,6 +3588,53 @@ "CORE_CM7" ] }, + "NICLA_VISION": { + "inherits": ["MCU_STM32H747xI_CM7"], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "25000000", + "macro_name": "HSE_VALUE" + }, + "lse_bypass": { + "help": "1 to use an oscillator (not a crystal) on 32k LSE", + "value": "1" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_HS" + } + }, + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY", + "clock_source": "USE_PLL_HSE_EXTC", + "lse_available": 0, + "lpticker_delay_ticks": 0 + }, + "components_add": [ + "QSPIF", + "WHD", + "4343W_FS", + "CYW43XXX" + ], + "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", + "CM4_BOOT_BY_APPLICATION", + "QSPI_NO_SAMPLE_SHIFT", + "CYW43XXX_UNBUFFERED_UART" + ], + "device_has_add": [ + "USBDEVICE", + "QSPI" + ], + "extra_labels_add": [ + "CORDIO" + ], + "features": [ + "BLE" + ] + }, "PORTENTA_H7_M4": { "inherits": ["PORTENTA_H7"], "core": "Cortex-M4F", From e21f0a7699f63f51a56f4a9f60a63f00e471505f Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 17 Sep 2021 15:46:29 +0200 Subject: [PATCH 114/227] Nicla Vision: Set WiFi as default interface --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index b0c4328b760..7b8351db6a0 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3609,7 +3609,8 @@ "system_power_supply": "PWR_LDO_SUPPLY", "clock_source": "USE_PLL_HSE_EXTC", "lse_available": 0, - "lpticker_delay_ticks": 0 + "lpticker_delay_ticks": 0, + "network-default-interface-type": "WIFI" }, "components_add": [ "QSPIF", From 730dcf722d74f12ce66911059f312e18f0a255ed Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 20 Sep 2021 17:30:54 +0200 Subject: [PATCH 115/227] Nicla Vision: enable I2C_TIMING_VALUE_ALGO --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 7b8351db6a0..3516696296e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3610,7 +3610,8 @@ "clock_source": "USE_PLL_HSE_EXTC", "lse_available": 0, "lpticker_delay_ticks": 0, - "network-default-interface-type": "WIFI" + "network-default-interface-type": "WIFI", + "i2c_timing_value_algo": true }, "components_add": [ "QSPIF", From ac174a3037a3f9e3b1142e392ca2c12c593dab76 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 24 Dec 2021 09:53:40 +0100 Subject: [PATCH 116/227] Nicla Vision: tune LWIP mem size --- connectivity/lwipstack/mbed_lib.json | 3 +++ 1 file changed, 3 insertions(+) diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index bf7e742a5c8..54ab36d62c3 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -225,6 +225,9 @@ "PORTENTA_H7": { "mem-size": 16000 }, + "NICLA_VISION": { + "mem-size": 16000 + }, "FVP_MPS2_M3": { "mem-size": 36560 }, From 934c8c41414b018c8536462bb16f5717de7aff46 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 6 Dec 2021 15:16:08 +0100 Subject: [PATCH 117/227] Nicla Vision: fix wifi bug related to SDMMC2 Enable flow control + enable SDMMC2 clk before any operation Restore original clock speed --- .../src/bus_protocols/whd_bus_sdio_protocol.c | 5 +++-- .../TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c | 8 +++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_sdio_protocol.c b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_sdio_protocol.c index 5944bf6e7ab..150d3baa66c 100755 --- a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_sdio_protocol.c +++ b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/bus_protocols/whd_bus_sdio_protocol.c @@ -732,8 +732,9 @@ whd_result_t whd_bus_sdio_read_backplane_value(whd_driver_t whd_driver, uint32_t address &= SBSDIO_SB_OFT_ADDR_MASK; - if (register_length == 4) + if (register_length == 4) { address |= SBSDIO_SB_ACCESS_2_4B_FLAG; + } CHECK_RETURN(whd_bus_sdio_transfer(whd_driver, BUS_READ, BACKPLANE_FUNCTION, address, register_length, value, RESPONSE_NEEDED) ); @@ -1002,7 +1003,7 @@ static whd_result_t whd_bus_sdio_download_firmware(whd_driver_t whd_driver) } if (result != WHD_SUCCESS) { - WPRINT_WHD_ERROR( ("Error while waiting for high throughput clock\n") ); + WPRINT_WHD_ERROR( ("Error while reading csr value: %d\n", csr_val) ); /* Reachable after hitting assert */ return result; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c index 9044e871800..521917c8deb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c @@ -251,7 +251,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, __HAL_RCC_SDMMC2_RELEASE_RESET(); /* Enable the SDIO Clock */ - __HAL_RCC_SDMMC2_CLK_ENABLE(); + //__HAL_RCC_SDMMC2_CLK_ENABLE(); #if !(defined(DUAL_CORE) && defined(CORE_CM4)) /* Disable DCache for STM32H7 family */ @@ -414,8 +414,8 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction /* Send the command */ //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); SDMMC2->ARG = argument; - cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); - SDMMC2->CMD = cmd; + cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE); + SDMMC2->CMD |= cmd; /* Wait for the whole transfer to complete */ //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); @@ -432,9 +432,11 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction /* Check if there were any SDIO errors */ if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); + SDMMC2->CMD = 0; goto restart; } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); + SDMMC2->CMD = 0; goto restart; } From fd3895618d06daa92615c260a4603e870173b2d2 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 27 Oct 2021 15:30:07 +0200 Subject: [PATCH 118/227] Nicla Vision: fix LPUART at baudrates higher than 9600 --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 3516696296e..5bfe2292a04 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3611,7 +3611,8 @@ "lse_available": 0, "lpticker_delay_ticks": 0, "network-default-interface-type": "WIFI", - "i2c_timing_value_algo": true + "i2c_timing_value_algo": true, + "lpuart_clock_source": "USE_LPUART_CLK_HSI" }, "components_add": [ "QSPIF", From f413796efdcb68961d12c1b922d6676f42e8a079 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 19 Jan 2022 10:24:06 +0100 Subject: [PATCH 119/227] TEMP: Remove log from .gitignore file --- .gitignore | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitignore b/.gitignore index 3e907cf52c9..7a68e77ae89 100644 --- a/.gitignore +++ b/.gitignore @@ -90,7 +90,6 @@ tags features/FEATURE_BLE/targets/TARGET_CORDIO/stack_backup/ .pytest_cache -log # Icetea related file test_suite.json From f85a33023ff2110462c7c131e195e1a3434115ab Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 18 Jan 2022 14:00:46 +0100 Subject: [PATCH 120/227] Initial import of plug & trust library to COMPONENT_SE050 --- .../COMPONENT_SE050/Apache_2_0.txt | 202 + .../COMPONENT_SE050/BSD3_license.txt | 11 + .../COMPONENT_SE050/ChangeLog.md | 91 + .../COMPONENT_SE050/LICENSE | 2 + .../COMPONENT_SE050/README.rst | 328 + .../ecc_example/CMakeLists.txt | 87 + .../COMPONENT_SE050/fsl_sss_ftr.h | 651 ++ .../hostlib/hostLib/inc/Applet_SE050_Ver.h | 114 + .../hostLib/inc/PlugAndTrust_HostLib_Ver.h | 63 + .../hostLib/inc/PlugAndTrust_Pkg_Ver.h | 62 + .../hostlib/hostLib/inc/nxEnsure.h | 279 + .../hostlib/hostLib/inc/nxScp03_Apis.h | 90 + .../hostlib/hostLib/inc/nxScp03_Const.h | 97 + .../hostlib/hostLib/inc/nxScp03_Types.h | 306 + .../COMPONENT_SE050/hostlib/hostLib/inc/scp.h | 127 + .../hostlib/hostLib/inc/se05x_const.h | 168 + .../hostlib/hostLib/inc/se05x_ecc_curves.h | 19 + .../hostLib/inc/se05x_ecc_curves_inc.h | 268 + .../hostLib/inc/se05x_ecc_curves_values.h | 2801 +++++++ .../hostlib/hostLib/inc/se05x_enums.h | 1030 +++ .../hostlib/hostLib/inc/se05x_ftr.h | 36 + .../hostlib/hostLib/inc/se05x_tlv.h | 370 + .../hostlib/hostLib/inc/sm_const.h | 123 + .../hostLib/libCommon/infra/global_platf.c | 87 + .../hostLib/libCommon/infra/global_platf.h | 28 + .../hostlib/hostLib/libCommon/infra/sm_apdu.c | 880 ++ .../hostlib/hostLib/libCommon/infra/sm_apdu.h | 217 + .../hostlib/hostLib/libCommon/infra/sm_api.h | 119 + .../hostLib/libCommon/infra/sm_connect.c | 655 ++ .../hostLib/libCommon/infra/sm_errors.c | 74 + .../hostLib/libCommon/infra/sm_errors.h | 31 + .../hostLib/libCommon/infra/sm_printf.c | 32 + .../hostLib/libCommon/infra/sm_types.h | 163 + .../hostlib/hostLib/libCommon/log/nxLog.c | 361 + .../hostlib/hostLib/libCommon/log/nxLog.h | 107 + .../hostlib/hostLib/libCommon/log/nxLog_App.h | 183 + .../libCommon/log/nxLog_DefaultConfig.h | 44 + .../hostLib/libCommon/log/nxLog_hostLib.h | 183 + .../hostLib/libCommon/log/nxLog_mbedtls.h | 183 + .../hostlib/hostLib/libCommon/log/nxLog_scp.h | 183 + .../hostLib/libCommon/log/nxLog_smCom.h | 183 + .../hostlib/hostLib/libCommon/log/nxLog_sss.h | 183 + .../hostLib/libCommon/nxScp/nxScp03_Com.c | 429 + .../libCommon/smCom/T1oI2C/phEseStatus.h | 421 + .../libCommon/smCom/T1oI2C/phEseTypes.h | 31 + .../libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c | 202 + .../libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h | 110 + .../smCom/T1oI2C/phNxpEseProto7816_3.c | 1697 ++++ .../smCom/T1oI2C/phNxpEseProto7816_3.h | 443 ++ .../libCommon/smCom/T1oI2C/phNxpEse_Api.c | 766 ++ .../libCommon/smCom/T1oI2C/phNxpEse_Api.h | 70 + .../smCom/T1oI2C/phNxpEse_Internal.h | 54 + .../hostLib/libCommon/smCom/apduComm.h | 65 + .../hostlib/hostLib/libCommon/smCom/smCom.c | 170 + .../hostlib/hostLib/libCommon/smCom/smCom.h | 49 + .../hostLib/libCommon/smCom/smComT1oI2C.c | 200 + .../hostLib/libCommon/smCom/smComT1oI2C.h | 71 + .../hostlib/hostLib/mbedtls/src/ecdh_alt.c | 710 ++ .../hostlib/hostLib/mbedtls/src/rsa_alt.c | 2376 ++++++ .../hostLib/platform/generic/sm_timer.c | 76 + .../hostlib/hostLib/platform/inc/ax_reset.h | 45 + .../hostlib/hostLib/platform/inc/i2c_a7.h | 160 + .../hostlib/hostLib/platform/inc/se05x_apis.h | 18 + .../hostlib/hostLib/platform/inc/sm_printf.h | 40 + .../hostlib/hostLib/platform/inc/sm_timer.h | 31 + .../hostlib/hostLib/platform/linux/i2c_a7.c | 385 + .../hostLib/platform/rsp/se05x_reset.c | 155 + .../hostLib/se05x/src/se05x_ECC_curves.c | 72 + .../hostlib/hostLib/se05x/src/se05x_mw.c | 106 + .../hostlib/hostLib/se05x/src/se05x_tlv.c | 822 ++ .../se05x_03_xx_xx/se05x_04_xx_APDU_apis.h | 1207 +++ .../se05x_03_xx_xx/se05x_04_xx_APDU_impl.h | 1535 ++++ .../hostLib/se05x_03_xx_xx/se05x_APDU.c | 91 + .../hostLib/se05x_03_xx_xx/se05x_APDU.h | 76 + .../hostLib/se05x_03_xx_xx/se05x_APDU_apis.h | 5812 ++++++++++++++ .../hostLib/se05x_03_xx_xx/se05x_APDU_impl.h | 3470 ++++++++ .../mbedtls_cli_srv/CMakeLists.txt | 207 + .../COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c | 175 + .../COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h | 124 + .../COMPONENT_SE050/sss/ex/inc/ex_sss.h | 96 + .../COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h | 180 + .../COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h | 220 + .../sss/ex/inc/ex_sss_main_inc.h | 382 + .../sss/ex/inc/ex_sss_main_inc_linux.h | 25 + .../COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h | 112 + .../COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h | 53 + .../sss/ex/inc/ex_sss_scp03_keys.h | 75 + .../sss/ex/inc/ex_sss_tp_scp03_keys.h | 119 + .../sss/ex/mbedtls/ex_sss_ssl2.c | 2272 ++++++ .../COMPONENT_SE050/sss/ex/src/ex_sss_boot.c | 280 + .../sss/ex/src/ex_sss_boot_connectstring.c | 178 + .../sss/ex/src/ex_sss_boot_int.h | 70 + .../sss/ex/src/ex_sss_scp03_auth.c | 233 + .../COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c | 427 + .../sss/ex/src/ex_sss_se05x_auth.c | 602 ++ .../COMPONENT_SE050/sss/inc/fsl_sscp.h | 428 + .../COMPONENT_SE050/sss/inc/fsl_sss_api.h | 1892 +++++ .../COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h | 64 + .../COMPONENT_SE050/sss/inc/fsl_sss_config.h | 84 + .../sss/inc/fsl_sss_ftr_default.h | 673 ++ .../sss/inc/fsl_sss_keyid_map.h | 182 + .../sss/inc/fsl_sss_lpc55s_apis.h | 115 + .../sss/inc/fsl_sss_mbedtls_apis.h | 837 ++ .../sss/inc/fsl_sss_mbedtls_types.h | 253 + .../sss/inc/fsl_sss_openssl_apis.h | 839 ++ .../sss/inc/fsl_sss_openssl_types.h | 239 + .../COMPONENT_SE050/sss/inc/fsl_sss_policy.h | 221 + .../sss/inc/fsl_sss_se05x_apis.h | 781 ++ .../sss/inc/fsl_sss_se05x_policy.h | 51 + .../sss/inc/fsl_sss_se05x_scp03.h | 56 + .../sss/inc/fsl_sss_se05x_types.h | 613 ++ .../COMPONENT_SE050/sss/inc/fsl_sss_sscp.h | 717 ++ .../sss/inc/fsl_sss_user_apis.h | 627 ++ .../sss/inc/fsl_sss_user_types.h | 144 + .../sss/inc/fsl_sss_util_asn1_der.h | 175 + .../sss/inc/fsl_sss_util_rsa_sign_utils.h | 28 + .../sss/plugin/mbedtls/ecdh_alt_ax.c | 417 + .../sss/plugin/mbedtls/ecdsa_verify_alt.c | 632 ++ .../sss/plugin/mbedtls/ecdsa_verify_alt.h | 12 + .../sss/plugin/mbedtls/ecp_alt.h | 191 + .../sss/plugin/mbedtls/port/ksdk/ecp_alt.c | 3115 ++++++++ .../plugin/mbedtls/port/ksdk/ecp_curves_alt.c | 1485 ++++ .../sss/plugin/mbedtls/rsa_alt.h | 86 + .../sss/plugin/mbedtls/sss_mbedtls.c | 508 ++ .../sss/plugin/mbedtls/sss_mbedtls.h | 102 + .../sss/plugin/mbedtls/sss_mbedtls_rsa.c | 251 + .../plugin/mbedtls/sss_mbedtls_x86_config.h | 3368 ++++++++ .../sss/port/default/fsl_sss_types.h | 62 + .../COMPONENT_SE050/sss/src/fsl_sss_apis.c | 2601 ++++++ .../sss/src/fsl_sss_util_asn1_der.c | 1751 ++++ .../sss/src/fsl_sss_util_rsa_sign_utils.c | 553 ++ .../sss/src/keystore/keystore_cmn.c | 291 + .../sss/src/keystore/keystore_openssl.c | 224 + .../sss/src/keystore/keystore_pc.c | 340 + .../sss/src/mbedtls/fsl_sss_mbedtls_apis.c | 3181 ++++++++ .../sss/src/openssl/fsl_sss_openssl_apis.c | 3737 +++++++++ .../sss/src/se05x/fsl_sss_se05x_apis.c | 7074 +++++++++++++++++ .../sss/src/se05x/fsl_sss_se05x_eckey.c | 534 ++ .../sss/src/se05x/fsl_sss_se05x_mw.c | 509 ++ .../sss/src/se05x/fsl_sss_se05x_policy.c | 392 + .../sss/src/se05x/fsl_sss_se05x_scp03.c | 520 ++ 141 files changed, 79971 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/BSD3_license.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst create mode 100644 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targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c create mode 100644 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targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt new file mode 100644 index 00000000000..d6456956733 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md new file mode 100644 index 00000000000..4b37821827f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md @@ -0,0 +1,91 @@ +# Plug-And-Trust Mini Package Change Log + +## Release v03.03.00 + +- sss_openssl_cipher_one_go() api modified to use EVP calls for AES (ECB, CBC, CTR) + +- sss_se05x_cipher_update() api modified to use block size of 256 to enhance performance. + + +## Release v03.01.00 + +- Extended kSSS_KeyPart_Default for other objectType. + + - Earlier: Object type ``kSSS_KeyPart_Default`` is used for Binary Files, + Certificates, Symmetric Keys, PCR and HMAC-key. + + - Now: UserID and Counter are added for ``kSSS_KeyPart_Default``. + This means objectType of UserID and Counter will be ``kSSS_KeyPart_Default`` after + calling :cpp:type:`sss_key_object_get_handle`. + Comment for enum ``sss_key_part_t`` is updated accordingly. + +- Added new API :cpp:func:`Se05x_API_WritePCR_WithType` with support to + write transient PCR objects also. + +- Deprecated API :cpp:func:`Se05x_API_WritePCR`. Added macro :c:macro:`ENABLE_DEPRECATED_API_WritePCR` + to enable compilation of deprecated API :cpp:func:`Se05x_API_WritePCR`. + Support will be removed by Q1 2022. + +- Bugfix - Handling of result tag in case of failure in :cpp:func:`Se05x_API_AeadOneShot`, + :cpp:func:`Se05x_API_AeadFinal` and + :cpp:func:`Se05x_API_AeadCCMFinal` + +- Bugfix - KVN12 key can be used for PlatformSCP authentication now in SE051. + +- SE05x APDU - Response length set to 0 in error condition - :cpp:func:`tlvGet_u8buf`. + +- Created separate library (``mwlog``) for logging framework. See :numref:`stack-logging` + :ref:`stack-logging` + +- Order of log level reversed. Current log level is - ``{"ERROR", "WARN ", "INFO ", "DEBUG"}``. + +- Mbedtls ALT is extended with ECDSA verify operation using ``MBEDTLS_ECDSA_VERIFY_ALT`` define. (Disabled by default). + Using this all EC public key verify operations can be performed using SE05x. + +- Changed files under BSD3 License with NXP Copyright to Apache2 License. + +- Changed files under Proprietary license to Apache 2 License. + + +## Release v03.00.06 + +- smCom_Init: return type is now *U16* instead of *void*. Return value indicates success/failure to create mutex/semophore. + +- The enumerated type **SE05x_EDSignatureAlgo_t** contained a value **kSE05x_EDSignatureAlgo_ED25519PH_SHA_512**. + The mnemonic name of the value was misleading as it actually corresponded to the `Pure EDDSA algorithm` not the + `Prehashed (PH) EDDSA algorithm`. This has now been corrected. **This will require corresponding update in the application code.** + + - EDDSA signature algorithm enumerated value **kSE05x_EDSignatureAlgo_ED25519PH_SHA_512** is changed into **kSE05x_EDSignatureAlgo_ED25519PURE_SHA_512**. + + - EDDSA attestation algorithm enumerated value **kSE05x_AttestationAlgo_ED25519PH_SHA_512** is changed into as **kSE05x_AttestationAlgo_ED25519PURE_SHA_512**. + +- Fixed typo in example code API: ex_sss_kestore_and_object_init() is now ex_sss_key_store_and_object_init() + +- Added support for SE051 type + +- Extended SE051 specific APDU command and response buffer size to match SE051's capabilities. + +- SSS API blocks SHA512 attestation, signing and verification for RSA512 key + +- Bug Fix : Fix for attestation read of symmetric objects which have no read policy. + +- Added Platform SCP03 keys for SE051 (Variant A2 and C2). + + +## Release v03.00.02 + +- T1oI2C: + + - Fixed: potential null pointer dereference + + - Fixed: RSYNC _ + CRC error results in saving response to uninitialised buffer. + +- ``hostlib/hostLib/platform/linux/i2c_a7.c``: A call to `axI2CTerm()` now closes the I2C file descriptor associated with the + I2C communication channel. + + +## Release v03.00.00 + +- Initial commit + +- Plug & Trust middleware to use secure element SE050 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE new file mode 100644 index 00000000000..546a8e631f5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE @@ -0,0 +1,2 @@ +Unless specifically indicated otherwise in a file, files are licensed +under the Apache 2.0 license, as can be found in: apache-2.0.txt diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst new file mode 100644 index 00000000000..fb71b7bf101 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst @@ -0,0 +1,328 @@ +Introduction on Plug & Trust Middleware Mini Package +==================================================================== + +Plug and Trust middleware mini package contains the minimum files required to +connect to SE05x using t1oi2c protocol. The package is tested on +*Raspberry-Pi* with ``T=1 overI2C``. + +The complete Plug and Trust middleware package can be downloaded from +https://www.nxp.com/products/:SE050. The package has support for other +platforms. + +- iMX6UL, iMX8MQ - Linux +- Freedom K64F, i.MX RT 1060, LPC55S - FreeRTOS/Without RTOS +- Hikey 960 - Android +- Windows PC(Visual Studio) + +It also includes other api usage examples, ssscli (command line tool to use +SE05x), cloud connectivity examples, openssl engine, pkcs11 interface, AWS +Greengrass, OPCUA and more. More details regarding SE05x and other detailed +application notes can be found at https://www.nxp.com/products/:SE050 / +https://www.nxp.com/products/:SE051. + + +Change Log +------------------------------------------------------------- +Refer ChangeLog.md + + + +Folder structure of the Mini Pacakge +------------------------------------------------------------- + +The folder structure of mini package is as under:: + + ├───ecc_example + ├───hostlib + │ └───hostLib + │ ├───inc + │ ├───libCommon + │ │ ├───infra + │ │ ├───nxScp + │ │ └───smCom + │ │ └───T1oI2C + │ ├───mbedtls + │ │ └───src + │ ├───platform + │ │ ├───generic + │ │ ├───inc + │ │ ├───linux + │ │ └───rsp + │ ├───se05x + │ │ └───src + │ └───se05x_03_xx_xx + └───sss + ├───ex + │ ├───ecc + │ ├───inc + │ └───src + ├───inc + ├───plugin + │ └───mbedtls + ├───port + │ └───default + └───src + ├───keystore + ├───mbedtls + ├───openssl + └───se05x + +Important folders are as under: + +:ecc_example: ecc sign and verify example. (Tested on Raspberry Pi with openssl 1.1.1) + +:hostlib: This folder contains the common part of host library e.g. ``T=1oI2C`` communication + protocol stack, SE050 APIs, etc. + +:sss: This folder contains the **SSS APIs** interface to the Application Layer. + + +Prerequisite +------------------------------------------------------------- +- Linux should be running on the Raspberry Pi development board, + the release was tested with Raspbian Buster (``4.19.75-v7l+``) +- SE050 or SE051 connected to i2c-1 port of Raspberry Pi. + + +ECC example +------------------------------------------------------------- + +This example demonstrates Elliptic Curve Cryptography sign and verify +operation using SSS APIs. (``/sss/ex/ecc/ex_sss_ecc.c``) Execute the command +below to test the ecc example:: + + cd ecc_example + mkdir build + cd build + cmake .. + cmake --build . + ./ex_ecc + + +Build Applications using Mini Package +------------------------------------------------------------- + +Use the source file in `sss/ex` folder to open the session to se05x. +Applications code should start with function `ex_sss_entry`:: + + sss_status_t ex_sss_entry(ex_sss_boot_ctx_t *pCtx) + +Refer the example `ecc_example`. +Example File - `/sss/ex/ecc/ex_sss_ecc.c` + + +Use the below macros in ``fsl_sss_ftr.h`` file to enable support for either SE050 or SE051. :: + + /** SE050 */ + #define SSS_HAVE_SE05X_VER_03_XX 1 + + /** SE051 */ + #define SSS_HAVE_SE05X_VER_06_00 0 + + +To enable authenticated session to SE05x, make the following changes, + +1. Enable any host crypto (Mbedtls or openssl or User crypto) in + ``fsl_sss_ftr.h`` file. Refer, + +- For Openssl: Refer section - *Openssl host crypto in mini package* +- For Mbedtls: Refer section - *Mbedtls host crypto in mini package* +- For User Crypto: Refer section - *User host crypto in mini package* + + +2. Enable the below macros in ``fsl_sss_ftr.h`` file: + +- ``#define SSS_HAVE_SCP_SCP03_SSS 1`` +- ``#define SSSFTR_SE05X_AuthSession 1`` + +3. Below settings can be used to authenticate with SE (Refer SE050 - User + Guidelines in https://www.nxp.com/products/:SE050 for more details on session + authentication) + +- ``SSS_HAVE_SE05X_AUTH_USERID`` +- ``SSS_HAVE_SE05X_AUTH_AESKEY`` +- ``SSS_HAVE_SE05X_AUTH_ECKEY`` +- ``SSS_HAVE_SE05X_AUTH_PLATFSCP03`` +- ``SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03`` +- ``SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03`` +- ``SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03`` + + +4. Include the below source files for autheticated session open, + +- ``sss/ex/src/ex_sss_scp03_auth.c`` +- ``sss/src/se05x/fsl_sss_se05x_eckey.c`` +- ``sss/src/se05x/fsl_sss_se05x_scp03.c`` +- ``hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c`` + + +Openssl host crypto in mini package +------------------------------------------------------------- + +Enable/disable the openssl host crypto by changing the below definition in +``fsl_sss_ftr.h`` file:: + + /** Use OpenSSL as host crypto */ + #define SSS_HAVE_HOSTCRYPTO_OPENSSL 1 + +Include the below files for openssl host crypto support +- ``sss/src/openssl/fsl_sss_openssl_apis.c`` +- ``sss/src/keystore/keystore_cmn.c`` +- ``sss/src/keystore/keystore_openssl.c`` +- ``sss/src/keystore/keystore_pc.c`` + +Link the openssl library (version 1.1) as, + TARGET_LINK_LIBRARIES(${PROJECT_NAME} ssl crypto) + + +Mbedtls host crypto in mini package +------------------------------------------------------------- + +Enable/disable the mbedtls host crypto by changing the below definition in +``fsl_sss_ftr.h`` file:: + + /** Use mbedTLS as host crypto */ + #define SSS_HAVE_HOSTCRYPTO_MBEDTLS 1 + +Include the below file for mbedtls host crypto support, + +- ``sss/src/mbedtls/fsl_sss_mbedtls_apis.c`` +- ``sss/src/keystore/keystore_pc.c`` +- ``sss/src/keystore/keystore_cmn.c`` + +Mbedtls applications depend on the following files to use se05x for crypto +operations. Include the following files for compilation along with the mbedtls +stack. (Tested with mbedtls-2.16.2). Mbedtls client server example using the +below files is expalined in the next section, + +- ``/hostlib/hostLib/mbedtls/src/ecdh_alt.c`` +- ``/hostlib/hostLib/mbedtls/src/rsa_alt.c`` +- ``/sss/plugin/mbedtls/ecdh_alt_ax.c`` +- ``/sss/plugin/mbedtls/sss_mbedtls.c`` +- ``/sss/plugin/mbedtls/sss_mbedtls_rsa.c`` +- ``/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c`` +- ``/sss/plugin/mbedtls/port/ksdk/ecp_alt.c`` + +Note: Exclude the file ``mbedtls/library/ecdh.c`` from mbedtls stack for compilation. + +Also add compile defination ``MBEDTLS_CONFIG_FILE`` to use the correct mbedtls config file:: + + TARGET_COMPILE_DEFINITIONS( + ${PROJECT_NAME} + PUBLIC + MBEDTLS_CONFIG_FILE=\"sss_mbedtls_x86_config.h\" + ) + +.. note:: + + Remove linking the openssl library in ``ecc_example/CMakeLists.txt``, if + the example is built for mbedtls, ``TARGET_LINK_LIBRARIES(${PROJECT_NAME} + ssl crypto)`` + + + +TLS Client Server Example using MbedTLS stack +------------------------------------------------------------- + +This example demonstrates TLS client server connection using mbedtls stack. +(``mbedtls_cli_srv``). Mbedtls client example is modified to use the +client key and certificates from secure element. Modified mbedtls client +example - ``sss/ex/mbedtls/ex_sss_ssl2.c`` + +Prerequisite for the demo: + +- Copy mbedtls (``mbedtls-2.16.2``) stack to ``ext/`` location, +- client key provisoned inside SE050 with key id ``0x20181001``, +- client certificate provisoned inside SE050 with key id ``0x20181002``, +- Root CA public key provisoned inside SE050 with key id ``0x7DCCBB22``, + +Enable mbedtls host crypto in ``fsl_sss_ftr.h`` file. Execute the command +below to build mbedtls client and server examples:: + + cd mbedtls_cli_srv + mkdir build + cd build + cmake .. + cmake --build . + + +Run mbedtls server as:: + + ./ssl2_server exchanges=1 \ + force_version=tls1_2 \ + debug_level=1 \ + ca_file= \ + auth_mode=required \ + key_file= \ + crt_file= + +Run mbedtls client as:: + + ./ssl2_client server_name=localhost \ + exchanges=1 \ + force_version=tls1_2 \ + debug_level=1 \ + ca_file= \ + auth_mode=required \ + key_file=none \ + crt_file=none \ + force_ciphersuite=TLS-ECDH-ECDSA-WITH-AES-128-CBC-SHA \ + curves=secp256r1 none + + + +User host crypto in mini package +------------------------------------------------------------- + +Enable/disable the user host crypto by changing the below definition in ``fsl_sss_ftr.h`` file:: + + #define SSS_HAVE_HOSTCRYPTO_USER 1 + +On enabling HOSTCRYPTO_USER, the user has to implement the required cryptographic function. +Implement the functions declared in file ``sss/inc/fsl_sss_user_apis.h``. + +Refer Openssl host crypto implementation in - ``sss/src/mbedtls/fsl_sss_openssl_apis.c``. +Refer Mbedtls host crypto implementation in - ``sss/src/mbedtls/fsl_sss_mbedtls_apis.c``. + + + +Port Mini package to different platform +------------------------------------------------------------- + +To port the mini package to different platform, the i2c interface needs to be +ported. Exsisting implementation for i2c read/write on Raspberry Pi is in - +``hostlib/hostLib/platform/linux/i2c_a7.c``. + +Other file that may require porting is - +``hostlib/hostLib/platform/generic/sm_timer.c`` + + + +Memory Details +------------------------------------------------------------- + +Memory details of ex_ecc example on Raspberry Pi built with, + +- No hostcrypto +- Plain session + +:: + + Text segment -- 184505 Bytes + Data segment -- 416 Bytes + Bss segment --- 2808 Bytes + Total -------- 187729 Bytes + + +Memory details of ex_ecc example on Raspberry Pi built with + +- Openssl hostcrypto +- PlatformSCP + ECKey (EXFL_SE050_AUTH_ECKey_PlatfSCP03 ) session + +:: + + Text segment -- 292336 Bytes + Data segment -- 1116 Bytes + Bss segment --- 3692 Bytes + Total -------- 297144 Bytes + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ecc_example/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ecc_example/CMakeLists.txt new file mode 100644 index 00000000000..5f35c06dd12 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ecc_example/CMakeLists.txt @@ -0,0 +1,87 @@ +CMAKE_MINIMUM_REQUIRED(VERSION 3.5.0) + +project (ex_ecc) + +FILE( + GLOB + SOURCES + ../sss/ex/src/ex_sss_boot.c + ../sss/ex/src/ex_sss_boot_connectstring.c + ../sss/ex/src/ex_sss_se05x.c + ../sss/ex/src/ex_sss_se05x_auth.c + ../sss/src/*.c + + ../sss/src/se05x/fsl_sss_se05x_apis.c + ../sss/src/se05x/fsl_sss_se05x_mw.c + ../sss/src/se05x/fsl_sss_se05x_policy.c + + ../hostlib/hostLib/libCommon/infra/*.c + + ../hostlib/hostLib/libCommon/log/nxLog.c + + ../hostlib/hostLib/libCommon/smCom/smCom.c + ../hostlib/hostLib/platform/rsp/se05x_reset.c + ../hostlib/hostLib/platform/generic/sm_timer.c + + ../hostlib/hostLib/se05x/src/se05x_ECC_curves.c + ../hostlib/hostLib/se05x/src/se05x_mw.c + ../hostlib/hostLib/se05x/src/se05x_tlv.c + ../hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c + + # T1oI2C files + ../hostlib/hostLib/libCommon/smCom/smComT1oI2C.c + ../hostlib/hostLib/libCommon/smCom/T1oI2C/*.c + ../hostlib/hostLib/platform/linux/i2c_a7.c + + ##### Openssl Host crypto support + #../sss/src/openssl/fsl_sss_openssl_apis.c + #../sss/src/keystore/keystore_cmn.c + #../sss/src/keystore/keystore_openssl.c + #../sss/src/keystore/keystore_pc.c + + ##### Mbedtls Host crypto support + #../sss/src/mbedtls/fsl_sss_mbedtls_apis.c + #../sss/src/keystore/keystore_cmn.c + #../sss/src/keystore/keystore_pc.c + + ##### Authenticated session to se05x + #../sss/ex/src/ex_sss_scp03_auth.c + #../sss/src/se05x/fsl_sss_se05x_eckey.c + #../sss/src/se05x/fsl_sss_se05x_scp03.c + #../hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c +) + +add_executable(${PROJECT_NAME} ../sss/ex/ecc/ex_sss_ecc.c ${SOURCES}) + +#TARGET_LINK_LIBRARIES(${PROJECT_NAME} ssl crypto) + + +FILE( + GLOB + INC_DIR + ../sss/inc + ../sss/port/default + ../sss/ex/src + ../sss/ex/inc + ../hostlib/hostLib/inc + ../hostlib/hostLib/libCommon/infra + ../hostlib/hostLib/libCommon/smCom + ../hostlib/hostLib/libCommon/log + ../hostlib/hostLib/libCommon/smCom/T1oI2C + ../hostlib/hostLib/se05x_03_xx_xx + ../hostlib/hostLib/platform/inc + ../hostlib/hostLib/libCommon/smCom +) + +TARGET_INCLUDE_DIRECTORIES( + ${PROJECT_NAME} + PUBLIC + ../ + ${INC_DIR} + ) + + +ADD_DEFINITIONS(-DSSS_USE_FTR_FILE) +ADD_DEFINITIONS(-DSMCOM_T1oI2C) +ADD_DEFINITIONS(-DT1oI2C) +ADD_DEFINITIONS(-DT1oI2C_UM11225) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/fsl_sss_ftr.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/fsl_sss_ftr.h new file mode 100644 index 00000000000..95dd7f92ffb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/fsl_sss_ftr.h @@ -0,0 +1,651 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_FTR_H_ +#define SSS_APIS_INC_FSL_SSS_FTR_H_ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* clang-format off */ + + +/* # CMake Features : Start */ + + +/** Applet : The Secure Element Applet + * + * You can compile host library for different Applets listed below. + * Please note, some of these Applets may be for NXP Internal use only. + */ + +/** Compiling without any Applet Support */ +#define SSS_HAVE_APPLET_NONE 0 + +/** A71CH (ECC) */ +#define SSS_HAVE_APPLET_A71CH 0 + +/** A71CL (RSA) */ +#define SSS_HAVE_APPLET_A71CL 0 + +/** Similar to A71CH */ +#define SSS_HAVE_APPLET_A71CH_SIM 0 + +/** SE050 Type A (ECC) */ +#define SSS_HAVE_APPLET_SE05X_A 0 + +/** SE050 Type B (RSA) */ +#define SSS_HAVE_APPLET_SE05X_B 0 + +/** SE050 (Super set of A + B) */ +#define SSS_HAVE_APPLET_SE05X_C 1 + +/** SE050 (Similar to A71CL) */ +#define SSS_HAVE_APPLET_SE05X_L 0 + +/** NXP Internal testing Applet */ +#define SSS_HAVE_APPLET_LOOPBACK 0 + +#if (( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) > 1) +# error "Enable only one of 'Applet'" +#endif + + +#if (( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) == 0) +# error "Enable at-least one of 'Applet'" +#endif + + + +/** SE05X_Ver : SE05X Applet version. + * + * Selection of Applet version 03_XX enables SE050 features. + * Selection of Applet version 06_00 enables SE051 features. + * + */ + +/** SE050 */ +#define SSS_HAVE_SE05X_VER_03_XX 1 + +/** SE051 */ +#define SSS_HAVE_SE05X_VER_06_00 0 + +#if (( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) > 1) +# error "Enable only one of 'SE05X_Ver'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) == 0) +# error "Enable at-least one of 'SE05X_Ver'" +#endif + + + +/** HostCrypto : Counterpart Crypto on Host + * + * What is being used as a cryptographic library on the host. + * As of now only OpenSSL / mbedTLS is supported + */ + +/** Use mbedTLS as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_MBEDTLS 0 + +/** Use mbed-crypto as host crypto + * Required for ARM-PSA / TF-M */ +#define SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO 0 + +/** Use OpenSSL as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_OPENSSL 0 + +/** User Implementation of Host Crypto + * e.g. Files at ``sss/src/user/crypto`` have low level AES/CMAC primitives. + * The files at ``sss/src/user`` use those primitives. + * This becomes an example for users with their own AES Implementation + * This then becomes integration without mbedTLS/OpenSSL for SCP03 / AESKey. + * + * .. note:: ECKey abstraction is not implemented/available yet. */ +#define SSS_HAVE_HOSTCRYPTO_USER 0 + +/** NO Host Crypto + * Note, this is unsecure and only provided for experimentation + * on platforms that do not have an mbedTLS PORT + * Many :ref:`sssftr-control` have to be disabled to have a valid build. */ +#define SSS_HAVE_HOSTCRYPTO_NONE 0 + +#if (( 0 \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_USER \ + + SSS_HAVE_HOSTCRYPTO_NONE \ + ) > 1) +# error "Enable only one of 'HostCrypto'" +#endif + + +/** mbedTLS_ALT : ALT Engine implementation for mbedTLS + * + * When set to None, mbedTLS would not use ALT Implementation to connect to / use Secure Element. + * This needs to be set to SSS for Cloud Demos over SSS APIs + */ + +/** Use SSS Layer ALT implementation */ +#define SSS_HAVE_MBEDTLS_ALT_SSS 1 + +/** Legacy implementation */ +#define SSS_HAVE_MBEDTLS_ALT_A71CH 0 + +/** Not using any mbedTLS_ALT + * + * When this is selected, cloud demos can not work with mbedTLS */ +#define SSS_HAVE_MBEDTLS_ALT_NONE 0 + +#if (( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) > 1) +# error "Enable only one of 'mbedTLS_ALT'" +#endif + + +#if (( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) == 0) +# error "Enable at-least one of 'mbedTLS_ALT'" +#endif + + + +/** SCP : Secure Channel Protocol + * + * In case we enable secure channel to Secure Element, which interface to be used. + */ + +/** */ +#define SSS_HAVE_SCP_NONE 0 + +/** Use SSS Layer for SCP. Used for SE050 family. */ +#define SSS_HAVE_SCP_SCP03_SSS 0 + +/** Use Host Crypto Layer for SCP03. Legacy implementation. Used for older demos of A71CH Family. */ +#define SSS_HAVE_SCP_SCP03_HOSTCRYPTO 0 + +#if (( 0 \ + + SSS_HAVE_SCP_NONE \ + + SSS_HAVE_SCP_SCP03_SSS \ + + SSS_HAVE_SCP_SCP03_HOSTCRYPTO \ + ) > 1) +# error "Enable only one of 'SCP'" +#endif + + +/** FIPS : Enable or disable FIPS + * + * This selection mostly impacts tests, and generally not the actual Middleware + */ + +/** NO FIPS */ +#define SSS_HAVE_FIPS_NONE 1 + +/** SE050 IC FIPS */ +#define SSS_HAVE_FIPS_SE050 0 + +/** FIPS 140-2 */ +#define SSS_HAVE_FIPS_140_2 0 + +/** FIPS 140-3 */ +#define SSS_HAVE_FIPS_140_3 0 + +#if (( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) > 1) +# error "Enable only one of 'FIPS'" +#endif + + +#if (( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) == 0) +# error "Enable at-least one of 'FIPS'" +#endif + + + +/** SBL : Enable/Disable SBL Bootable support + * + * This option is to enable/disable boot from SBL by switching linker address + */ + +/** Not SBL bootable */ +#define SSS_HAVE_SBL_NONE 1 + +/** SE050 based LPC55S SBL bootable */ +#define SSS_HAVE_SBL_SBL_LPC55S 0 + +#if (( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) > 1) +# error "Enable only one of 'SBL'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) == 0) +# error "Enable at-least one of 'SBL'" +#endif + + + +/** SE05X_Auth : SE050 Authentication + * + * This settings is used by examples to connect using various options + * to authenticate with the Applet. + * The SE05X_Auth options can be changed for KSDK Demos and Examples. + * To change SE05X_Auth option follow below steps. + * Set flag ``SSS_HAVE_SCP_SCP03_SSS`` to 1 and Reset flag ``SSS_HAVE_SCP_NONE`` to 0. + * To change SE05X_Auth option other than ``None`` and ``PlatfSCP03``, + * execute se05x_Delete_and_test_provision.exe in order to provision the Authentication Key. + * To change SE05X_Auth option to ``ECKey`` or ``ECKey_PlatfSCP03``, + * Set additional flag ``SSS_HAVE_HOSTCRYPTO_ANY`` to 1. + */ + +/** Use the default session (i.e. session less) login */ +#define SSS_HAVE_SE05X_AUTH_NONE 1 + +/** Do User Authentication with UserID */ +#define SSS_HAVE_SE05X_AUTH_USERID 0 + +/** Use Platform SCP for connection to SE */ +#define SSS_HAVE_SE05X_AUTH_PLATFSCP03 0 + +/** Do User Authentication with AES Key + * Earlier this was called AppletSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY 0 + +/** Do User Authentication with EC Key + * Earlier this was called FastSCP */ +#define SSS_HAVE_SE05X_AUTH_ECKEY 0 + +/** UserID and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 0 + +/** AESKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 0 + +/** ECKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 0 + +#if (( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) > 1) +# error "Enable only one of 'SE05X_Auth'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) == 0) +# error "Enable at-least one of 'SE05X_Auth'" +#endif + + + +/** A71CH_AUTH : A71CH Authentication + * + * This settings is used by SSS-API based examples to connect using either plain or authenticated to the A71CH. + */ + +/** Plain communication, not authenticated or encrypted */ +#define SSS_HAVE_A71CH_AUTH_NONE 1 + +/** SCP03 enabled */ +#define SSS_HAVE_A71CH_AUTH_SCP03 0 + +#if (( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) > 1) +# error "Enable only one of 'A71CH_AUTH'" +#endif + + +#if (( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) == 0) +# error "Enable at-least one of 'A71CH_AUTH'" +#endif + + +/* ====================================================================== * + * == Feature selection/values ========================================== * + * ====================================================================== */ + + +/** SE05X Secure Element : Symmetric AES */ +#define SSSFTR_SE05X_AES 1 + +/** SE05X Secure Element : Elliptic Curve Cryptography */ +#define SSSFTR_SE05X_ECC 1 + +/** SE05X Secure Element : RSA */ +#define SSSFTR_SE05X_RSA 1 + +/** SE05X Secure Element : KEY operations : SET Key */ +#define SSSFTR_SE05X_KEY_SET 1 + +/** SE05X Secure Element : KEY operations : GET Key */ +#define SSSFTR_SE05X_KEY_GET 1 + +/** SE05X Secure Element : Authenticate via ECKey */ +#define SSSFTR_SE05X_AuthECKey 1 + +/** SE05X Secure Element : Allow creation of user/authenticated session. + * + * If the intended deployment only uses Platform SCP + * Or it is a pure session less integration, this can + * save some code size. */ +#define SSSFTR_SE05X_AuthSession 0 + +/** SE05X Secure Element : Allow creation/deletion of Crypto Objects + * + * If disabled, new Crytpo Objects are neither created and + * old/existing Crypto Objects are not deleted. + * It is assumed that during provisioning phase, the required + * Crypto Objects are pre-created or they are never going to + * be needed. */ +#define SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ 1 + +/** Software : Symmetric AES */ +#define SSSFTR_SW_AES 1 + +/** Software : Elliptic Curve Cryptography */ +#define SSSFTR_SW_ECC 1 + +/** Software : RSA */ +#define SSSFTR_SW_RSA 1 + +/** Software : KEY operations : SET Key */ +#define SSSFTR_SW_KEY_SET 1 + +/** Software : KEY operations : GET Key */ +#define SSSFTR_SW_KEY_GET 1 + +/** Software : Used as a test counterpart + * + * e.g. Major part of the mebdTLS SSS layer is purely used for + * testing of Secure Element implementation, and can be avoided + * fully during many production scenarios. */ +#define SSSFTR_SW_TESTCOUNTERPART 1 + +/* ====================================================================== * + * == Computed Options ================================================== * + * ====================================================================== */ + +/** Symmetric AES */ +#define SSSFTR_AES (SSSFTR_SE05X_AES + SSSFTR_SW_AES) +/** Elliptic Curve Cryptography */ +#define SSSFTR_ECC (SSSFTR_SE05X_ECC + SSSFTR_SW_ECC) +/** RSA */ +#define SSSFTR_RSA (SSSFTR_SE05X_RSA + SSSFTR_SW_RSA) +/** KEY operations : SET Key */ +#define SSSFTR_KEY_SET (SSSFTR_SE05X_KEY_SET + SSSFTR_SW_KEY_SET) +/** KEY operations : GET Key */ +#define SSSFTR_KEY_GET (SSSFTR_SE05X_KEY_GET + SSSFTR_SW_KEY_GET) +/** KEY operations */ +#define SSSFTR_KEY (SSSFTR_KEY_SET + SSSFTR_KEY_GET) +/** KEY operations */ +#define SSSFTR_SE05X_KEY (SSSFTR_SE05X_KEY_SET + SSSFTR_SE05X_KEY_GET) +/** KEY operations */ +#define SSSFTR_SW_KEY (SSSFTR_SW_KEY_SET + SSSFTR_SW_KEY_GET) + + +#define SSS_HAVE_APPLET \ + (SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CL | SSS_HAVE_APPLET_A71CH_SIM | SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C | SSS_HAVE_APPLET_SE05X_L | SSS_HAVE_APPLET_LOOPBACK) + +#define SSS_HAVE_APPLET_SE05X_IOT \ + (SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C) + +#define SSS_HAVE_MBEDTLS_ALT \ + (SSS_HAVE_MBEDTLS_ALT_SSS | SSS_HAVE_MBEDTLS_ALT_A71CH) + +#define SSS_HAVE_HOSTCRYPTO_ANY \ + (SSS_HAVE_HOSTCRYPTO_MBEDTLS | SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO | SSS_HAVE_HOSTCRYPTO_OPENSSL | SSS_HAVE_HOSTCRYPTO_USER) + +#define SSS_HAVE_FIPS \ + (SSS_HAVE_FIPS_SE050 | SSS_HAVE_FIPS_140_2 | SSS_HAVE_FIPS_140_3) + + +/* Version checks GTE - Greater Than Or Equal To */ +#if SSS_HAVE_APPLET_SE05X_IOT +# if SSS_HAVE_SE05X_VER_06_00 +# define SSS_HAVE_SE05X_VER_GTE_06_00 1 +# define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +# endif /* SSS_HAVE_SE05X_VER_06_00 */ +# if SSS_HAVE_SE05X_VER_03_XX +# define SSS_HAVE_SE05X_VER_GTE_06_00 0 +# define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +# endif /* SSS_HAVE_SE05X_VER_03_XX */ +#else //SSS_HAVE_APPLET_SE05X_IOT +# define SSS_HAVE_SE05X_VER_GTE_03_XX 0 +# define SSS_HAVE_SE05X_VER_GTE_06_00 0 +#endif // SSS_HAVE_APPLET_SE05X_IOT +/** Deprecated items. Used here for backwards compatibility. */ + +#define WithApplet_SE05X (SSS_HAVE_APPLET_SE05X_IOT) +#define WithApplet_SE050_A (SSS_HAVE_APPLET_SE05X_A) +#define WithApplet_SE050_B (SSS_HAVE_APPLET_SE05X_B) +#define WithApplet_SE050_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE050_A (SSS_HAVE_APPLET_SE05X_A) +#define SSS_HAVE_SE050_B (SSS_HAVE_APPLET_SE05X_B) +#define SSS_HAVE_SE050_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE05X (SSS_HAVE_APPLET_SE05X_IOT) +#define SSS_HAVE_SE (SSS_HAVE_APPLET) +#define SSS_HAVE_LOOPBACK (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_ALT (SSS_HAVE_MBEDTLS_ALT) +#define WithApplet_None (SSS_HAVE_APPLET_NONE) +#define SSS_HAVE_None (SSS_HAVE_APPLET_NONE) +#define WithApplet_A71CH (SSS_HAVE_APPLET_A71CH) +#define SSS_HAVE_A71CH (SSS_HAVE_APPLET_A71CH) +#define WithApplet_A71CL (SSS_HAVE_APPLET_A71CL) +#define SSS_HAVE_A71CL (SSS_HAVE_APPLET_A71CL) +#define WithApplet_A71CH_SIM (SSS_HAVE_APPLET_A71CH_SIM) +#define SSS_HAVE_A71CH_SIM (SSS_HAVE_APPLET_A71CH_SIM) +#define WithApplet_SE05X_A (SSS_HAVE_APPLET_SE05X_A) +#define SSS_HAVE_SE05X_A (SSS_HAVE_APPLET_SE05X_A) +#define WithApplet_SE05X_B (SSS_HAVE_APPLET_SE05X_B) +#define SSS_HAVE_SE05X_B (SSS_HAVE_APPLET_SE05X_B) +#define WithApplet_SE05X_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE05X_C (SSS_HAVE_APPLET_SE05X_C) +#define WithApplet_SE05X_L (SSS_HAVE_APPLET_SE05X_L) +#define SSS_HAVE_SE05X_L (SSS_HAVE_APPLET_SE05X_L) +#define WithApplet_LoopBack (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_LoopBack (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_MBEDTLS (SSS_HAVE_HOSTCRYPTO_MBEDTLS) +#define SSS_HAVE_MBEDCRYPTO (SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO) +#define SSS_HAVE_OPENSSL (SSS_HAVE_HOSTCRYPTO_OPENSSL) +#define SSS_HAVE_USER (SSS_HAVE_HOSTCRYPTO_USER) +#define SSS_HAVE_NONE (SSS_HAVE_HOSTCRYPTO_NONE) +#define SSS_HAVE_ALT_SSS (SSS_HAVE_MBEDTLS_ALT_SSS) +#define SSS_HAVE_ALT_A71CH (SSS_HAVE_MBEDTLS_ALT_A71CH) +#define SSS_HAVE_ALT_NONE (SSS_HAVE_MBEDTLS_ALT_NONE) +#define SSS_HAVE_SE05X_Auth_None (SSS_HAVE_SE05X_AUTH_NONE) +#define SSS_HAVE_SE05X_Auth_UserID (SSS_HAVE_SE05X_AUTH_USERID) +#define SSS_HAVE_SE05X_Auth_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_AESKey (SSS_HAVE_SE05X_AUTH_AESKEY) +#define SSS_HAVE_SE05X_Auth_ECKey (SSS_HAVE_SE05X_AUTH_ECKEY) +#define SSS_HAVE_SE05X_Auth_UserID_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_AESKey_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_ECKey_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + +/* # CMake Features : END */ + +/* ========= Miscellaneous values : START =================== */ + +/* ECC Mode is available */ +#define SSS_HAVE_ECC 1 + +/* RSA is available */ +#define SSS_HAVE_RSA 1 + +/* TPM BARRETO_NAEHRIG Curve is enabled */ +#define SSS_HAVE_TPM_BN 1 + +/* Edwards Curve is enabled */ +#define SSS_HAVE_EC_ED 1 + +/* Montgomery Curve is enabled */ +#define SSS_HAVE_EC_MONT 1 + +/* MIFARE DESFire is enabled */ +#define SSS_HAVE_MIFARE_DESFIRE 1 + +/* PBKDF2 is enabled */ +#define SSS_HAVE_PBKDF2 1 + +/* TLS handshake support on SE is enabled */ +#define SSS_HAVE_TLS_HANDSHAKE 1 + +/* Import Export Key is enabled */ +#define SSS_HAVE_IMPORT 1 + +/* With NXP NFC Reader Library */ +#define SSS_HAVE_NXPNFCRDLIB 0 + +#define SSS_HAVE_A71XX \ + (SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CH_SIM) + +#define SSS_HAVE_SSCP (SSS_HAVE_A71XX) + +/* For backwards compatibility */ +#define SSS_HAVE_TESTCOUNTERPART (SSSFTR_SW_TESTCOUNTERPART) + +/* ========= Miscellaneous values : END ===================== */ + +/* ========= Calculated values : START ====================== */ + +/* Should we expose, SSS APIs */ +#define SSS_HAVE_SSS ( 0 \ + + SSS_HAVE_SSCP \ + + SSS_HAVE_APPLET_SE05X_IOT \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_USER \ + ) + +/* MBEDCRYPTO is superset of MBEDTLS and exposing that way */ +#if SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO +# undef SSS_HAVE_MBEDTLS +# undef SSS_HAVE_HOSTCRYPTO_MBEDTLS + +# define SSS_HAVE_MBEDTLS 1 +# define SSS_HAVE_HOSTCRYPTO_MBEDTLS 1 +#endif // SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO + +#if SSS_HAVE_HOSTCRYPTO_NONE +# undef SSSFTR_SE05X_AuthSession +# define SSSFTR_SE05X_AuthSession 0 +#endif + +/* Montgomery curves is not supported in SE05X_A*/ +#if SSS_HAVE_APPLET_SE05X_A +# undef SSS_HAVE_EC_MONT +# define SSS_HAVE_EC_MONT 0 +/* ED is not supported in SE050_A */ +#if SSS_HAVE_SE05X_VER_03_XX +# undef SSS_HAVE_EC_ED +# define SSS_HAVE_EC_ED 0 +#endif +#endif + +#if SSS_HAVE_RSA +# define SSS_HAVE_RSA_4K 1 +#endif + +#if SSS_HAVE_ECC +# define SSS_HAVE_EC_NIST_192 1 +# define SSS_HAVE_EC_NIST_224 1 +# define SSS_HAVE_EC_NIST_256 1 +# define SSS_HAVE_EC_NIST_384 1 +# define SSS_HAVE_EC_NIST_521 1 +# define SSS_HAVE_EC_BP 1 +# define SSS_HAVE_EC_NIST_K 1 +# define SSS_HAVE_ECDAA 1 +# define SSS_HAVE_EDDSA 1 +#if SSS_HAVE_APPLET_SE05X_A +# undef SSS_HAVE_ECDAA +# undef SSS_HAVE_EDDSA +# define SSS_HAVE_ECDAA 0 +# define SSS_HAVE_EDDSA 0 +#endif +#endif + +#if SSS_HAVE_APPLET +#define SSS_HAVE_HASH_1 1 +#define SSS_HAVE_HASH_224 1 +#define SSS_HAVE_HASH_512 1 +#endif + + +/* ========= Calculated values : END ======================== */ + +/* clang-format on */ + +#endif /* SSS_APIS_INC_FSL_SSS_FTR_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h new file mode 100644 index 00000000000..51aaf715bb0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h @@ -0,0 +1,114 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef APPLET_SE050_VERSION_INFO_H_INCLUDED +#define APPLET_SE050_VERSION_INFO_H_INCLUDED + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +/* clang-format off */ +//#define APPLET_SE050_PROD_NAME "Applet_SE050" +//#define APPLET_SE050_VER_STRING_NUM "v03.01.00" +//#define APPLET_SE050_PROD_NAME_VER_FULL "Applet_SE050_v03.01.00" + +#if SSS_HAVE_SE05X_VER_04_04 == 1 +# define APPLET_SE050_VER_MAJOR (4u) +# define APPLET_SE050_VER_MINOR (4u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_04_08 == 1 +# define APPLET_SE050_VER_MAJOR (4u) +# define APPLET_SE050_VER_MINOR (8u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_04_12 == 1 +# define APPLET_SE050_VER_MAJOR (4u) +# define APPLET_SE050_VER_MINOR (12u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_00 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (0u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_02 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (2u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_04 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (4u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_08 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (8u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_10 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (10u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_05_12 == 1 +# define APPLET_SE050_VER_MAJOR (5u) +# define APPLET_SE050_VER_MINOR (12u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_SE05X_VER_06_00 == 1 +# define APPLET_SE050_VER_MAJOR (6u) +# define APPLET_SE050_VER_MINOR (0u) +# define APPLET_SE050_VER_DEV (0u) +#elif SSS_HAVE_FIPS +# define APPLET_SE050_VER_MAJOR (3u) +# define APPLET_SE050_VER_MINOR (6u) +# define APPLET_SE050_VER_DEV (0u) +#else +# define APPLET_SE050_VER_MAJOR (3u) +# define APPLET_SE050_VER_MINOR (1u) +# define APPLET_SE050_VER_DEV (0u) +# define APPLET_SE050_VER_DEV_PATCH1 (1u) /* Allow this as well */ +#endif + + +/* v03.01 = 30001u */ +#define APPLET_SE050_VER_MAJOR_MINOR ( 0 \ + | (APPLET_SE050_VER_MAJOR * 10000u) \ + | (APPLET_SE050_VER_MINOR)) + +/* v03.01.00 = 300010000ULL */ +#define APPLET_SE050_VER_MAJOR_MINOR_DEV ( 0 \ + | (APPLET_SE050_VER_MAJOR * 10000*10000u) \ + | (APPLET_SE050_VER_MINOR * 10000u) \ + | (APPLET_SE050_VER_DEV)) + +/* clang-format on */ + +/* Version Information: + * Generated by: + * ..\..\..\scripts\version_info.py (v2019.01.17_00) + * + * Do not edit this file. Update: + * ./version_info.txt instead. + * + * + * prod_name = "Applet_SE050" + * + * prod_desc = "Applet AR6" + * + * lang_c_prefix = prod_name.upper() + * + * lang_namespace = "" + * + * v_major = "03" + * + * v_minor = "01" + * + * v_dev = "00" + * + * v_meta = "" + * + * maturity = "P" + * + */ + +#endif /* APPLET_SE050_VERSION_INFO_H_INCLUDED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h new file mode 100644 index 00000000000..52d7966bef8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h @@ -0,0 +1,63 @@ +/* Copyright 2019-2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * + */ + +#ifndef PLUGANDTRUST_HOSTLIB_VERSION_INFO_H_INCLUDED +#define PLUGANDTRUST_HOSTLIB_VERSION_INFO_H_INCLUDED + + +/* clang-format off */ +#define PLUGANDTRUST_HOSTLIB_PROD_NAME "PlugAndTrust_HostLib" +#define PLUGANDTRUST_HOSTLIB_VER_STRING_NUM "v03.03.00_20210528" +#define PLUGANDTRUST_HOSTLIB_PROD_NAME_VER_FULL "PlugAndTrust_HostLib_v03.03.00_20210528" +#define PLUGANDTRUST_HOSTLIB_VER_MAJOR (3u) +#define PLUGANDTRUST_HOSTLIB_VER_MINOR (3u) +#define PLUGANDTRUST_HOSTLIB_VER_DEV (0u) + +/* v03.03 = 30003u */ +#define PLUGANDTRUST_HOSTLIB_VER_MAJOR_MINOR ( 0 \ + | (PLUGANDTRUST_HOSTLIB_VER_MAJOR * 10000u) \ + | (PLUGANDTRUST_HOSTLIB_VER_MINOR)) + +/* v03.03.00 = 300030000ULL */ +#define PLUGANDTRUST_HOSTLIB_VER_MAJOR_MINOR_DEV ( 0 \ + | (PLUGANDTRUST_HOSTLIB_VER_MAJOR * 10000*10000u) \ + | (PLUGANDTRUST_HOSTLIB_VER_MINOR * 10000u) \ + | (PLUGANDTRUST_HOSTLIB_VER_DEV)) + +/* clang-format on */ + + +/* Version Information: + * Generated by: + * scripts\version_info.py (v2019.01.17_00) + * + * Do not edit this file. Update: + * hostlib/version_info.txt instead. + * + * + * prod_name = "PlugAndTrust_HostLib" + * + * prod_desc = "Host Library" + * + * lang_c_prefix = prod_name.upper() + * + * lang_namespace = "" + * + * v_major = "03" + * + * v_minor = "03" + * + * v_dev = "00" + * + * v_meta = "" + * + * maturity = "B" + * + * + */ + +#endif /* PLUGANDTRUST_HOSTLIB_VERSION_INFO_H_INCLUDED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h new file mode 100644 index 00000000000..61997085540 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h @@ -0,0 +1,62 @@ +/* Copyright 2019-2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * + */ + +#ifndef PLUGANDTRUST_VERSION_INFO_H_INCLUDED +#define PLUGANDTRUST_VERSION_INFO_H_INCLUDED + + +/* clang-format off */ +#define PLUGANDTRUST_PROD_NAME "PlugAndTrust" +#define PLUGANDTRUST_VER_STRING_NUM "v03.03.00_20210528" +#define PLUGANDTRUST_PROD_NAME_VER_FULL "PlugAndTrust_v03.03.00_20210528" +#define PLUGANDTRUST_VER_MAJOR (3u) +#define PLUGANDTRUST_VER_MINOR (3u) +#define PLUGANDTRUST_VER_DEV (0u) + +/* v03.03 = 30003u */ +#define PLUGANDTRUST_VER_MAJOR_MINOR ( 0 \ + | (PLUGANDTRUST_VER_MAJOR * 10000u) \ + | (PLUGANDTRUST_VER_MINOR)) + +/* v03.03.00 = 300030000ULL */ +#define PLUGANDTRUST_VER_MAJOR_MINOR_DEV ( 0 \ + | (PLUGANDTRUST_VER_MAJOR * 10000*10000u) \ + | (PLUGANDTRUST_VER_MINOR * 10000u) \ + | (PLUGANDTRUST_VER_DEV)) + +/* clang-format on */ + + +/* Version Information: + * Generated by: + * scripts\version_info.py (v2019.01.17_00) + * + * Do not edit this file. Update: + * ./version_info.txt instead. + * + * prod_name = "PlugAndTrust" + * + * prod_desc = "Plug And Trust Package" + * + * lang_c_prefix = prod_name.upper() + * + * lang_namespace = "" + * + * v_major = "03" + * + * v_minor = "03" + * + * v_dev = "00" + * + * # Develop Branch + * v_meta = "" + * + * maturity = "B" + * + */ + +#endif /* PLUGANDTRUST_VERSION_INFO_H_INCLUDED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h new file mode 100644 index 00000000000..a58a75f22d1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h @@ -0,0 +1,279 @@ +/* +* +* Copyright 2019 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +/** @file + * + * @addtogroup param_check + * + * @{ + * + * nxEnsure.h: Helper parameter assertion check macros. + * + * Pre Condition: The source file must have included nxLog + * header file. + * + * Project: SecureIoTMW + * + * + */ + +#ifndef HOSTLIB_HOSTLIB_INC_NXENSURE_H_ +#define HOSTLIB_HOSTLIB_INC_NXENSURE_H_ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * MACROS/Defines + * ***************************************************************************************************************** */ + +/** Build time over-ride if we want to enable/disable Warning Prints + * + * During debug builds, it makes sense to print them, + * During retail builds, such loggings would be of any use and remove and reduce code size. + * + */ +#ifndef NX_ENSURE_DO_LOG_MESSAGE +#define NX_ENSURE_DO_LOG_MESSAGE 1 +#endif /* NX_ENSURE_DO_LOG_MESSAGE */ + +/** + * @brief Waring print of the parameter ``strCONDITION`` + * + * @warning NX_ENSURE_MESSAGE is an internal message/API to this file. + * Do not use directly. + * + */ +#if NX_ENSURE_DO_LOG_MESSAGE +# define NX_ENSURE_MESSAGE(strCONDITION) \ + LOG_W("nxEnsure:'" strCONDITION "' failed. At Line:%d Function:%s", __LINE__, __FUNCTION__) +#else /* NX_ENSURE_DO_LOG_MESSAGE */ +# define NX_ENSURE_MESSAGE(strCONDITION) /* No Message */ +#endif /* NX_ENSURE_DO_LOG_MESSAGE */ + +/** + * @brief Waring print of the parameter ``strCONDITION`` + * + * @warning NX_ENSURE_MESSAGE is an internal message/API to this file. + * Do not use directly. + * + */ +#if NX_ENSURE_DO_LOG_MESSAGE +# define NX_ENSURE_MESSAGE(strCONDITION) \ + LOG_W("nxEnsure:'" strCONDITION "' failed. At Line:%d Function:%s", __LINE__, __FUNCTION__) +#else /* NX_ENSURE_DO_LOG_MESSAGE */ +# define NX_ENSURE_MESSAGE(strCONDITION) /* No Message */ +#endif /* NX_ENSURE_DO_LOG_MESSAGE */ + +/** If condition fails, goto :cleanup label + * + * @code{.c} + * + * { + * ... + * + * status = Operation1(); + * ENSURE_OR_GO_CLEANUP(0 == status); + * + * status = Operation2(); + * ENSURE_OR_GO_CLEANUP(0 == status); + * + * ... + * + * cleanup: + * return status; + * } + * + * @endcode + * + */ +#define ENSURE_OR_GO_CLEANUP(CONDITION) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + goto cleanup; \ + } + +/** If condition fails, goto :exit label + * + * @code{.c} + * + * { + * ... + * + * status = Operation1(); + * ENSURE_OR_GO_EXIT(0 == status); + * + * status = Operation2(); + * ENSURE_OR_GO_EXIT(0 == status); + * + * ... + * + * exit: + * return status; + * } + * + * @endcode + * + */ +#define ENSURE_OR_GO_EXIT(CONDITION) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + goto exit; \ + } + +/** If condition fails, break. + * + * Sample Usage: + * + * @code{.c} + * + * int SomeAPI() + * { + * ... + * + * do { + * status = Operation1(); + * ENSURE_OR_BREAK(0 == status); + * + * status = Operation2(); + * ENSURE_OR_BREAK(0 == status); + * + * ... + * + * } while(0); + * + * return status; + * } + * + * @endcode + * + */ +#define ENSURE_OR_BREAK(CONDITION) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + break; \ + } + +/** If condition fails, return + * + * + * @code{.c} + * + * void SomeAPI() + * { + * ... + * + * status = Operation1(); + * ENSURE_OR_RETURN(0 == status); + * + * status = Operation2(); + * ENSURE_OR_RETURN(0 == status); + * + * ... + * + * return; + * } + * + * @endcode + * + * @warning This macro introduces system of mutliple + * returns from a function which is not + * easy to debug/trace through and hence + * not recommended. + * + */ +#define ENSURE_OR_RETURN(CONDITION) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + return; \ + } + +/** If condition fails, return + * + * + * @code{.c} + * + * int SomeAPI() + * { + * ... + * + * status = Operation1(); + * ENSURE_OR_RETURN_ON_ERROR(0 == status, ERR_FAIL); + * + * status = Operation2(); + * ENSURE_OR_RETURN_ON_ERROR(0 == status, ERR_NOT_ENOUGH_SPACE); + * + * ... + * + * return 0; + * } + * + * @endcode + * + * @warning This macro introduces system of mutliple + * returns from a function which is not + * easy to debug/trace through and hence + * not recommended. + * + */ +#define ENSURE_OR_RETURN_ON_ERROR(CONDITION, RETURN_VALUE) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + return RETURN_VALUE; \ + } + +/** If condition fails, goto quit with return value status updated. + * + * + * @code{.c} + * + * int SomeAPI() + * { + int status = 0; + * ... + * + * value = Operation1(); + * ENSURE_OR_QUIT_WITH_STATUS_ON_ERROR(0 == value, status, ERR_FAIL); + * + * value = Operation2(); + * ENSURE_OR_QUIT_WITH_STATUS_ON_ERROR(0 == value, status, ERR_NOT_ENOUGH_SPACE); + * + * ... + * quit: + * return status; + * } + * + * @endcode + * + * @warning This macro introduces system of mutliple + * returns from a function which is not + * easy to debug/trace through and hence + * not recommended. + * + */ +#define ENSURE_OR_EXIT_WITH_STATUS_ON_ERROR(CONDITION, STATUS, RETURN_VALUE) \ + if (!(CONDITION)) { \ + NX_ENSURE_MESSAGE(#CONDITION); \ + STATUS = RETURN_VALUE; \ + goto exit; \ + } + +/* ***************************************************************************************************************** + * Types/Structure Declarations + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Extern Variables + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Function Prototypes + * ***************************************************************************************************************** */ + +/** @} */ + +#endif /* HOSTLIB_HOSTLIB_INC_NXENSURE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h new file mode 100644 index 00000000000..a37357e3fb3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h @@ -0,0 +1,90 @@ +/* +* +* Copyright 2018 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef NXSCP03_APIS_H_ +#define NXSCP03_APIS_H_ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nxScp03_Types.h" +#include "nxScp03_Const.h" + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** +* To Secure the on going communicatation +*/ + +/** +* To Verify SE +*/ +sss_status_t nxScp03_HostLocal_VerifyCardCryptogram( + sss_object_t *keyObj, uint8_t *hostChallenge, uint8_t *cardChallenge, uint8_t *cardCryptogram); + +/** +* To Verify Host +*/ +sss_status_t nxScp03_HostLocal_CalculateHostCryptogram( + sss_object_t *keyObj, uint8_t *hostChallenge, uint8_t *cardChallenge, uint8_t *hostCryptogram); + +/** +* To sending secure Command APDU +*/ +sss_status_t nxSCP03_Encrypt_CommandAPDU( + NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *cmdBuf, size_t *cmdBufLen); +/** +* To provide additional Security with MAC as CRC +*/ +sss_status_t nxpSCP03_CalculateMac_CommandAPDU( + NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pCmdBuf, size_t pCmdBufLen, uint8_t *mac, size_t *macLen); + +/** +* To get Plain Response APDU +*/ +uint16_t nxpSCP03_Decrypt_ResponseAPDU( + NXSCP03_DynCtx_t *pdySCP03SessCtx, size_t cmdBufLen, uint8_t *rspBuf, size_t *pRspBufLen, uint8_t hasle); + +/* +* To set the derivation data +*/ +void nxScp03_setDerivationData( + uint8_t ddA[], uint16_t *pDdALen, uint8_t ddConstant, uint16_t ddL, uint8_t iCounter, uint8_t *context, uint16_t contextLen); + +/** +* To Generate Session Keys +*/ +sss_status_t nxScp03_Generate_SessionKey( + sss_object_t *keyObj, uint8_t *inData, uint32_t inDataLen, uint8_t *outSignature, uint32_t *outSignatureLen); + +/** +* To Maintain count of commands +*/ +void nxpSCP03_Inc_CommandCounter(NXSCP03_DynCtx_t *pdySCP03SessCtx); + +#ifdef __cplusplus +} /* extern "c"*/ +#endif + +#endif /* NXSCP03_APIS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h new file mode 100644 index 00000000000..26890fa45d7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h @@ -0,0 +1,97 @@ +/* +* +* Copyright 2018 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef NXSCP03_CONST_H_ +#define NXSCP03_CONST_H_ +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#define SCP_GP_IU_KEY_DIV_DATA_LEN 10 //!< SCP GP Init Update key Div length +#define SCP_GP_IU_KEY_INFO_LEN 3 //!< SCP GP Init Update key info length +#define SCP_GP_CARD_CHALLENGE_LEN 8 //!< SCP GP Card Challenge length +#define SCP_GP_HOST_CHALLENGE_LEN 8 //!< SCP GP Host Challenge length +#define SCP_GP_IU_CARD_CRYPTOGRAM_LEN 8 //!< SCP GP Card Cryptogram length +#define SCP_GP_IU_SEQ_COUNTER_LEN 3 //!< SCP GP Init Update Sequence Counter length +#define SCP_GP_SW_LEN 2 //!< SCP Status Word length +#define CRYPTO_KEY_CHECK_LEN (3) //!< SCP key check length + +#define ASN_ECC_NIST_256_HEADER_LEN 26 +#define KEY_PARAMETER_REFERENCE_TAG 0xF0 +#define KEY_PARAMETER_REFERENCE_VALUE_LEN 0x01 // Fixed for Nist256key +#define KEY_PARAMETER_REFERENCE_VALUE 0x03 // key parameter value need to check in the spec it is 00 +#define GPCS_KEY_TYPE_ECC_NIST256 0xB0 +#define GPCS_KEY_TYPE_AES 0x88 +#define GPCS_KEY_LEN_AES 16 + +#define SCP_ID 0xAB +#define SCP_CONFIG 0x01 + +#define SCP_MCV_LEN 16 // MAC Chaining Length + +#define CLA_ISO7816 (0x00) //!< ISO7816-4 defined CLA byte +#define CLA_GP_7816 (0x80) //!< GP 7816-4 defined CLA byte +#define CLA_GP_SECURITY_BIT (0x04) //!< GP CLA Security bit + +#define INS_GP_INITIALIZE_UPDATE (0x50) //!< Global platform defined instruction +#define INS_GP_EXTERNAL_AUTHENTICATE (0x82) //!< Global platform defined instruction +#define INS_GP_SELECT (0xA4) //!< Global platform defined instruction +#define INS_GP_PUT_KEY (0xD8) //!< Global platform defined instruction +#define INS_GP_INTERNAL_AUTHENTICATE (0x88) //!< Global platform defined instruction +#define INS_GP_GET_DATA (0xCA) //!< Global platform defined instruction +#define P1_GP_GET_DATA (0xBF) //!< Global platform defined instruction +#define P2_GP_GET_DATA (0x21) //!< Global platform defined instruction + +/* Sizes used in SCP */ +#define AES_KEY_LEN_nBYTE (16) //!< AES key length + +#define SCP_KEY_SIZE (16) +#define SCP_CMAC_SIZE (16) // length of the CMAC calculated (and used as MAC chaining value) +#define SCP_IV_SIZE (16) // length of the Inital Vector +#define SCP_COMMAND_MAC_SIZE (8) // length of the MAC appended in the APDU payload (8 'MSB's) + +#define DATA_CARD_CRYPTOGRAM (0x00) //!< Data card cryptogram +#define DATA_HOST_CRYPTOGRAM (0x01) //!< Data host cryptogram +#define DATA_DERIVATION_SENC (0x04) //!< Data Derivation to generate Sess ENC Key +#define DATA_DERIVATION_SMAC (0x06) //!< Data Derivation to generate Sess MAC Key +#define DATA_DERIVATION_SRMAC (0x07) //!< Data Derivation to generate Sess RMAC Key +#define DATA_DERIVATION_INITIAL_MCV (0x08)//!< Data Derivation to generate Initial MCV +#define DATA_DERIVATION_L_64BIT (0x0040) //!< Data Derivation length +#define DATA_DERIVATION_L_128BIT (0x0080) //!< Data Derivation length +#define DATA_DERIVATION_KDF_CTR (0x01) //!< Data Derivation counter + +#define DD_LABEL_LEN 12 //!< Data Derivation length + +/* defines used to indicate the command type */ +#define C_MAC (0x01) //!< C MAC security +#define C_ENC (0x02) //!< C ENC security +#define R_MAC (0x10) //!< R MAC security +#define R_ENC (0x20) //!< R ENC security + +#define SECLVL_CDEC_RENC_CMAC_RMAC (0x33) //!< Full security + +#define SCP_DATA_PAD_BYTE 0x80 //!< Data Pad Byte + +#define CMAC_SIZE (8) //!< CMAC Compare size + +#define SCP_OK (SW_OK) +#define SCP_UNDEFINED_CHANNEL_ID (0x7041) //!< Undefined SCP channel identifier +#define SCP_FAIL (0x7042) //!< Undefined SCP channel identifier +#define SCP_CARD_CRYPTOGRAM_FAILS_TO_VERIFY (0x7043) //!< Undefined SCP channel identifier +#define SCP_PARAMETER_ERROR (0x7044) //!< Undefined SCP channel identifier + +#define NO_C_MAC_NO_C_ENC_NO_R_MAC_NO_R_ENC 0 //!< No security requested +#define C_MAC_NO_C_ENC_R_MAC_NO_R_ENC (C_MAC | R_MAC) //!< One apply MAC'ing (Not implemented) +#define C_MAC_C_ENC_R_MAC_R_ENC (C_MAC | C_ENC | R_MAC | R_ENC) //!< Apply full security +#define SECURITY_LEVEL C_MAC_C_ENC_R_MAC_R_ENC + +#define APPLET_SCP_INIT_UPDATE_LEN 0x0D //!< Applet SCP Initialize Update Length +#define APPLET_SCP_EXT_AUTH_LEN 0x15 //!< Applet SCP External Authenticate Length + +#endif /*NXSCP03_CONST_H_*/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h new file mode 100644 index 00000000000..0ce5df6231f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h @@ -0,0 +1,306 @@ +/* +* +* Copyright 2018,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef NXSCP03_TYPES_H_ +#define NXSCP03_TYPES_H_ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ +#include +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_MBEDTLS +#include +#endif +#if SSS_HAVE_OPENSSL +#include +#endif +#if SSS_HAVE_HOSTCRYPTO_USER +# include +#endif + +#include "sm_api.h" +#if SSS_HAVE_SSCP +#include "fsl_sscp_a71ch.h" +#endif + +typedef enum +{ + kSSS_AuthType_None = 0, + /** Global platform SCP03 */ + kSSS_AuthType_SCP03 = 1, + /** (e.g. SE05X) UserID based connection */ + kSSS_AuthType_ID = 2, + + /** (e.g. SE05X) Use AESKey for user authentication + * + * Earlier this was called kSSS_AuthType_AppletSCP03 + */ + kSSS_AuthType_AESKey = 3, + /** (e.g. SE05X) Use ECKey for user authentication + * + * Earlier this was called kSSS_AuthType_FastSCP + */ + kSSS_AuthType_ECKey = 4, + + /* ================ Internal ======================= */ + /* Not to be selected by end user... directly */ + + /** + * Used internally, not to be set/used by user. + * + * For the versions of the applet where we have to add + * the a counter during KDF. + */ + kSSS_AuthType_INT_ECKey_Counter = 0x14, + + kSSS_SIZE = 0x7FFFFFFF, +} SE_AuthType_t; + +#define kSSS_AuthType_INT_FastSCP_Counter kSSS_AuthType_INT_ECKey_Counter +#define kSSS_AuthType_FastSCP_Counter kSSS_AuthType_INT_ECKey_Counter +#define kSSS_AuthType_FastSCP kSSS_AuthType_ECKey +#define kSSS_AuthType_AppletSCP03 kSSS_AuthType_AESKey + +/** + * Dynamic SCP03 Context. + * + * This structure is filled **after** establishing + * an SCP03 session. + */ +typedef struct +{ + sss_object_t Enc; //!< session channel encryption key + sss_object_t Mac; //!< session command authentication key + sss_object_t Rmac; //!< session response authentication key + uint8_t MCV[16]; //!< MAC chaining value + uint8_t cCounter[16]; //!< command counter + uint8_t SecurityLevel; //!< security level set + + /** Handle differnt types of auth.. PlatformSCP / AppletSCP */ + SE_AuthType_t authType; +} NXSCP03_DynCtx_t; + +/** + * Static SCP03 Context. + * + * This structure is filled **before** establishing + * an SCP03 session. + * + * Depending on system, these objects may point to keys + * inside other security system. + */ +typedef struct +{ + /** Key version no to use for chanel + authentication in SCP03 */ + uint8_t keyVerNo; + /** Encryption key object */ + sss_object_t Enc; + sss_object_t Mac; //!< static secure channel authentication key obj + sss_object_t Dek; //!< data encryption key obj +} NXSCP03_StaticCtx_t; + +/** +* Static and Dynamic Context in one Context. +* +* +* Depending on system, these objects may point to keys +* inside other security system. +*/ +typedef struct +{ + NXSCP03_StaticCtx_t *pStatic_ctx; //!< .static keys data + NXSCP03_DynCtx_t *pDyn_ctx; //!< session keys data +} NXSCP03_AuthCtx_t; + +/** Static part of keys for FAST SCP */ +typedef struct +{ + /** Host ECDSA Private key */ + sss_object_t HostEcdsaObj; + /** Host ephemeral ECC key pair */ + sss_object_t HostEcKeypair; + /** SE ECC public key */ + sss_object_t SeEcPubKey; + /** Host master Secret */ + sss_object_t masterSec; +} NXECKey03_StaticCtx_t; + +/** Keys to connect for a ECKey Connection */ +typedef struct +{ + /** The Input/Static part of the ECKey Authentication + * + * We start/initiate a session with the keys here. + */ + NXECKey03_StaticCtx_t *pStatic_ctx; + /** The Dynamic part of the ECKey Authentication + * + * We derive/compute the session keys based on the + * ``pStatic_ctx``. + */ + NXSCP03_DynCtx_t *pDyn_ctx; // session keys data +} SE05x_AuthCtx_ECKey_t; + +/** UseID / PIN baed authentication object + * + * This is required to open an UserID / PIN based session to the SE. + */ +typedef struct +{ + /** The corresponding authentication object on the Host */ + sss_object_t * pObj; +} SE05x_AuthCtx_ID_t; + + +/** Legacy, only for A71CH with Host Crypto */ +typedef struct +{ + sss_object_t pKeyEnc; //!< SSS AES Enc Key object + sss_object_t pKeyMac; //!< SSS AES Mac Key object + sss_object_t pKeyDek; //!< SSS AES Dek Key object +} SM_SECURE_SCP03_KEYOBJ; + +/** Authentication mechanims */ +typedef struct _SE_AuthCtx +{ + /** How exactly we are going to authenticat ot the system. + * + * Since ``ctx`` is a union, this is needed to know exactly how + * we are going to authenticate. + */ + + SE_AuthType_t authType; + + /** Depending on ``authType``, the input and output parameters. + * + * This has both input and output parameters. + * + * Input is for Keys that are used to initiate the connection. + * While connecting, session keys/parameters are generated and they + * are also part of this context. + * + * In any case, we connect to only one type + */ + union { + /** For PlatformSCP / Applet SCP. + * + * Same SCP context will be used for platform and applet scp03 */ + NXSCP03_AuthCtx_t scp03; + + /** For ECKey */ + SE05x_AuthCtx_ECKey_t eckey; + + /** For UserID/PIN based based Authentication */ + SE05x_AuthCtx_ID_t idobj; + + /** Legacy, only for A71CH with Host Crypto */ + SM_SECURE_SCP03_KEYOBJ a71chAuthKeys; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_AUTH_MAX_CONTEXT_SIZE]; + } extension; + } ctx; +} SE_AuthCtx_t; + +/** + * When connecting to a secure element, + * + * Extension of sss_connect_ctx_t + */ +typedef struct +{ + /** to support binary compatibility/check, sizeOfStucture helps */ + uint16_t sizeOfStucture; + /** If we need to authenticate, add required objects for authentication */ + SE_AuthCtx_t auth; + /** If some policy restrictions apply when we connect, point it here */ + sss_policy_session_u *session_policy; + + /* =================================== */ + /* Implementation specific part starts */ + /* =================================== */ + + /** If we connect logically, via some software layer */ + sss_tunnel_t *tunnelCtx; + + /** How exactly are we going to connect physically */ + SSS_Conn_Type_t connType; + + /** Connection port name for Socket names, etc. */ + const char *portName; + + /** 12C address on embedded devices. */ + U32 i2cAddress; + + /** If we need to refresh session, SE050 specific */ + uint8_t refresh_session : 1; + + /** In the case of Key Rotation, and other use cases + * where we do not select the IoT Applet and skip + * the selection of the IoT Applet. + * + * One of the use cases is to do platform SCP + * key rotation. + * + * When set to 0: + * Do not skip IoT Applet selection and run as-is. + * + * When set to 1: + * Skip selection of card manager. + * Skip selection of Applet. + * + * Internally, if there is platform SCP selected as + * Auth mechanism during compile time, the internal + * logic would Select the card manager. But, + * skip selection of the Applet. + * + */ + uint8_t skip_select_applet : 1; +} SE_Connect_Ctx_t; + +/** Wrapper strucutre sss_connect_ctx_t */ +typedef struct +{ + /** To support binary compatibility/check, sizeOfStucture helps */ + uint16_t sizeOfStucture; + /** If we need to authenticate, add required objects for authentication */ + SE_AuthCtx_t auth; + /** If some policy restrictions apply when we connect, point it here */ + sss_policy_session_u *session_policy; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_CONNECT_MAX_CONTEXT_SIZE]; + } extension; +} sss_connect_ctx_t; + +/* Deprecated */ + +#define SE05x_AuthCtx_t SE_AuthCtx_t + +#define kSE05x_AuthType_None kSSS_AuthType_None +#define kSE05x_AuthType_SCP03 kSSS_AuthType_SCP03 +#define kSE05x_AuthType_UserID kSSS_AuthType_ID +#define kSE05x_AuthType_AESKey kSSS_AuthType_AESKey +#define kSE05x_AuthType_ECKey kSSS_AuthType_ECKey + +/* For backwards compatibility */ +#define SE05x_AuthType_t SE_AuthType_t + +#endif /* NXSCP03_TYPES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/scp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/scp.h new file mode 100644 index 00000000000..ab59629b204 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/scp.h @@ -0,0 +1,127 @@ +/* +* +* Copyright 2016,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +/** + * @par Description + * This file defines the interface to an APDU transfer function supporting both + * communication in the clear and channel encryption. + * @par History + * + */ + +#ifndef SCP_H +#define SCP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "smCom.h" + +/// @cond +#define HOST_CHANNEL_STATE_IDX 0 +#define ADMIN_CHANNEL_STATE_IDX 1 + +/* Sizes used in SCP */ +#define AES_KEY_LEN_nBYTE (16) +#define DES_KEY_LEN_nBYTE (16) + +#define SCP_CRYPTOGRAM_SIZE (16) +#define SCP_CHALLENGE_SIZE (8) +#define SCP_KEY_SIZE (16) +#define SCP_CMAC_SIZE (16) // length of the CMAC calculated (and used as MAC chaining value) +#define SCP_COMMAND_MAC_SIZE (8) // length of the MAC appended in the APDU payload (8 'MSB's) + +/* defines used to indicate the command type */ +#define C_MAC (0x01) +#define C_ENC (0x02) +#define R_MAC (0x10) +#define R_ENC (0x20) + +#define SECLVL_CDEC_RENC_CMAC_RMAC (0x33) + +#define SCP02_SECLVL_CMAC (0x01) +#define SCP02_SECLVL_CDEC_CMAC (0x03) +#define SCP02_SECLVL_CDEC_CMAC_RMAC (0x13) + +#define SCP03_KEY_ID (0x01) + +#define PUT_KEYS_MULTIPLE_KEYS (0x80) +#define PUT_KEYS_KEY_TYPE_CODING_AES (0x88) +#define PUT_KEYS_KEY_IDENTIFIER ((PUT_KEYS_MULTIPLE_KEYS) | (SCP03_KEY_ID)) + +/* security levels, matching the CLA bytes for each level */ +#define SECLVL_OFF (0x80) +#define SECLVL_MAC (0xC0) +#define SECLVL_ENC (0xE0) + +#define DD_INPUT_SIZE (32) + +#define DD_OFFSET_SESSION_COUNTER (10) +#define DD_OFFSET_DD_CONSTANT (11) +#define DD_OFFSET_L_MSB (13) +#define DD_OFFSET_L_LSB (14) +#define DD_OFFSET_I (15) +#define DD_OFFSET_HOST_CHALLENGE (16) +#define DD_OFFSET_CARD_CHALLENGE (24) + +#define DATA_CARD_CRYPTOGRAM (0x00) +#define DATA_HOST_CRYPTOGRAM (0x01) +#define DATA_DERIVATION_SENC (0x04) +#define DATA_DERIVATION_SMAC (0x06) +#define DATA_DERIVATION_SRMAC (0x07) +#define DATA_DERIVATION_L_64BIT (0x0040) +#define DATA_DERIVATION_L_128BIT (0x0080) +#define DATA_DERIVATION_KDF_CTR (0x01) + +#define DD_LABEL_LEN 12 + +#define SCP_GP_IU_KEY_DIV_DATA_LEN 10 +#define SCP_GP_IU_KEY_INFO_LEN 3 +#define SCP02_GP_IU_KEY_INFO_LEN 2 +#define SCP_GP_CARD_CHALLENGE_LEN 8 +#define SCP02_GP_CARD_CHALLENGE_LEN 6 +#define SCP_GP_HOST_CHALLENGE_LEN 8 +#define SCP_GP_IU_CARD_CRYPTOGRAM_LEN 8 +#define SCP_GP_IU_SEQ_COUNTER_LEN 3 +#define SCP02_GP_IU_SEQ_COUNTER_LEN 2 +#define SCP_GP_SW_LEN 2 +#define CRYPTO_KEY_CHECK_LEN (3) + +#define SCP_MCV_LEN 16 // MAC Chaining Length +/// @endcond + +/** + * Enumerated type encoding the security level requested to be applied to the APDU. + */ +typedef enum +{ + NO_C_MAC_NO_C_ENC_NO_R_MAC_NO_R_ENC = 0, //!< No security requested + C_MAC_NO_C_ENC_R_MAC_NO_R_ENC = (C_MAC | R_MAC), //!< One apply MAC'ing (Not implemented) + C_MAC_C_ENC_R_MAC_R_ENC = (C_MAC | C_ENC | R_MAC | R_ENC) //!< Apply full security +} scp_CommandType_t; + +/** + * Exchanges APDU, applies SCP03 encryption depending on \p type parameter and on the + * authentication status of the SCP03 channel. + * + * @param[in] conn_ctx connection context + * @param[in,out] pApdu apdu_t datastructure + * @param[in] type encryption/mac request + * + * @retval ::SMCOM_OK Operation successful + * @retval ::SMCOM_SND_FAILED Send Failed + * @retval ::SMCOM_RCV_FAILED Receive Failed + * @retval ::ERR_CRYPTO_ENGINE_FAILED Failure in crypto engine + * @retval ::SCP_RSP_MAC_FAIL MAC on response failed to verify + * @retval ::SCP_DECODE_FAIL Encrypted Response did not decode to correctly padded plaintext + */ +U32 scp_Transceive(void *conn_ctx, apdu_t * pApdu, scp_CommandType_t type); + +#ifdef __cplusplus +} +#endif +#endif /* _SCP_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h new file mode 100644 index 00000000000..a2a95fe1166 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h @@ -0,0 +1,168 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef FSL_SSS_SE05X_CONST_H +#define FSL_SSS_SE05X_CONST_H + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT + +#include + +#define SE05X_SESSIONID_LEN (8) + +/* See MAX_APDU_PAYLOAD_LENGTH in SE05x APDU Specifications. + * + * Using 892 so that buffer boundaries are potentially word aligned for Se050. + * Using 1024 for Se051. + * And expecting a failure from OnCard in case host sends a + * larger than expected buffer. + * Please note, depending on choice of: + * {No Auth | UserID Auth | Applet SCP | Fast SCP } + * and combination of either of above along with Platform SCP, + * there is no easy way how many Exact bytes the host can + * send to SE05x. + */ +#if SSS_HAVE_SE05X_VER_GTE_06_00 +/* SE051 MAX_APDU_PAYLOAD_LENGTH 1024 */ +#define SE05X_MAX_BUF_SIZE_CMD (1024) +#define SE05X_MAX_BUF_SIZE_RSP (1024) +#else +/* SE050 MAX_APDU_PAYLOAD_LENGTH 892 */ +#define SE05X_MAX_BUF_SIZE_CMD (892) +#define SE05X_MAX_BUF_SIZE_RSP (892) +#endif + +#define SE050_MODULE_UNIQUE_ID_LEN 18 + +#define SE05X_I2CM_MAX_BUF_SIZE_CMD (271) +#define SE05X_I2CM_MAX_BUF_SIZE_RSP (271) +#define SE05X_I2CM_MAX_TIMESTAMP_SIZE (12) +#define SE05X_I2CM_MAX_FRESHNESS_SIZE (16) +#define SE05X_I2CM_MAX_CHIP_ID_SIZE (18) + +/** How many attestation records + * + * Whle reading RSA Objects, modulus and public exporent get attested separately, */ + +#define SE05X_MAX_ATTST_DATA 2 + +#if SE05X_FTR_32BIT_CURVE_ID +#define START_SE05X_ID_CURVE_START (0x7E000000) +#else +#define START_SE05X_ID_CURVE_START (0) +#endif + +#define CIPHER_BLOCK_SIZE 16 +#define CIPHER_UPDATE_DATA_SIZE 256 +#define AEAD_BLOCK_SIZE 16 +#define BINARY_WRITE_MAX_LEN 500 + +enum Se05x_SYMM_CIPHER_MODES +{ + Se05x_SYMM_MODE_NONE = 0x00, + Se05x_SYMM_CBC = 0x01, + Se05x_SYMM_EBC = 0x02, + Se05x_SYMM_CTR = 0x08, /* For AES */ +}; + +enum Se05x_AES_PADDING +{ + Se05x_AES_PADDING_NONE = 0x00, + Se05x_AES_PAD_NOPAD = 0x01, + Se05x_AES_PAD_ISO9797_M1 = 0x02, + Se05x_AES_PAD_ISO9797_M2 = 0x03, +}; + +enum Se05x_SHA_TYPE +{ + Se05x_SHA_1 = 0x00, + Se05x_SHA_256 = 0x04, + Se05x_SHA_384 = 0x05, + Se05x_SHA_512 = 0x06, +}; + +enum Se05x_MAC_TYPE +{ + Se05x_CMAC = 0x0A, +}; + +enum Se05x_MAC_Sign_verify +{ + Se05x_MAC_Sign = 0x00, + Se05x_MAC_Verify = 0x01, +}; + +enum Se05x_I2CM_RESULT_TYPE +{ + Se05x_I2CM_RESULT_SUCCESS = 0xA5, + Se05x_I2CM_RESULT_FAILURE = 0x96 // The APDU spec defines this as 0x5A, implementation deviates! +}; + +#define MAX_OBJ_PCR_VALUE_SIZE 32 +#define MAX_POLICY_BUFFER_SIZE 256 +#define MAX_OBJ_POLICY_SIZE 47 +#define MAX_OBJ_POLICY_TYPES 6 +#define DEFAULT_OBJECT_POLICY_SIZE 8 +#define OBJ_POLICY_HEADER_OFFSET 5 +#define OBJ_POLICY_LENGTH_OFFSET 0 +#define OBJ_POLICY_AUTHID_OFFSET 1 +#define OBJ_POLICY_EXT_OFFSET 9 +#define OBJ_POLICY_PCR_DATA_SIZE (4 + MAX_OBJ_PCR_VALUE_SIZE) /*4 bytes PCR Obj id + 32 bytes PCR value*/ +#define OBJ_POLICY_AUTH_DATA_SIZE 2 + +#define SESSION_POLICY_LENGTH_OFFSET 0 +#define SESSION_POLICY_AR_HEADER_OFFSET 1 +#define DEFAULT_SESSION_POLICY_SIZE 3 + + +/*below bitmaps are set according to Se050 Applet implementation +Byte Ordering for Policy header:B1 B2 B3 B4 +bits ordering +b8 b7 b6 b5 b4 b3 b2 b1 +example : B1b8 : 0x80000000 +*/ + +/* Access Rules for Object Policy*/ +#define POLICY_OBJ_FORBID_ALL 0x20000000 +#define POLICY_OBJ_ALLOW_SIGN 0x10000000 +#define POLICY_OBJ_ALLOW_VERIFY 0x08000000 +#define POLICY_OBJ_ALLOW_KA 0x04000000 +#define POLICY_OBJ_ALLOW_ENC 0x02000000 +#define POLICY_OBJ_ALLOW_DEC 0x01000000 +#define POLICY_OBJ_ALLOW_KDF 0x00800000 +#define POLICY_OBJ_ALLOW_WRAP 0x00400000 +#define POLICY_OBJ_ALLOW_READ 0x00200000 +#define POLICY_OBJ_ALLOW_WRITE 0x00100000 +#define POLICY_OBJ_ALLOW_GEN 0x00080000 +#define POLICY_OBJ_ALLOW_DELETE 0x00040000 +#define POLICY_OBJ_REQUIRE_SM 0x00020000 +#define POLICY_OBJ_REQUIRE_PCR_VALUE 0x00010000 +#define POLICY_OBJ_ALLOW_ATTESTATION 0x00008000 +#define POLICY_OBJ_ALLOW_DESFIRE_AUTHENTICATION 0x00004000 +#define POLICY_OBJ_ALLOW_DESFIRE_DUMP_SESSION_KEYS 0x00002000 +#define POLICY_OBJ_ALLOW_IMPORT_EXPORT 0x00001000 +#if SSS_HAVE_SE05X_VER_GTE_06_00 // 4.4 +#define POLICY_OBJ_FORBID_DERIVED_OUTPUT 0x00000800 +#endif +#if SSS_HAVE_SE05X_VER_GTE_06_00 // 5.4 +#define POLICY_OBJ_ALLOW_KDF_EXT_RANDOM 0x00000400 +#endif + +/* Access Rules for Session Policy*/ +#define POLICY_SESSION_MAX_APDU 0x8000 +#define POLICY_SESSION_MAX_TIME 0x4000 +#define POLICY_SESSION_ALLOW_REFRESH 0x2000 +/**/ + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ + +#endif /* FSL_SSS_SE05X_CONST_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h new file mode 100644 index 00000000000..88787499ed4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h @@ -0,0 +1,19 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef SE05X_ECC_CURVES_H_INC +#define SE05X_ECC_CURVES_H_INC + +#include "se05x_tlv.h" + +#define PROCESS_ECC_CURVE(NAME) \ + smStatus_t Se05x_API_CreateCurve_##NAME(Se05xSession_t *pSession, uint32_t obj_id) + +#include + +#undef PROCESS_ECC_CURVE + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h new file mode 100644 index 00000000000..636ebef1202 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h @@ -0,0 +1,268 @@ +/* +* +* Copyright 2019 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + + +/* NIST/X9.62/SECG curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(prime192v1); + +/* NIST/SECG curve over a 224 bit prime field */ +PROCESS_ECC_CURVE(secp224r1); + +/* NIST/SECG curve over a 384 bit prime field */ +PROCESS_ECC_CURVE(secp384r1); + +/* X9.62/SECG curve over a 256 bit prime field */ +PROCESS_ECC_CURVE(prime256v1); + +/* NIST/SECG curve over a 521 bit prime field */ +PROCESS_ECC_CURVE(secp521r1); + +/* RFC 5639 curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP160r1); + +/* RFC 5639 curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP160t1); + +/* RFC 5639 curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP192r1); + +/* RFC 5639 curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP192t1); + +/* RFC 5639 curve over a 224 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP224r1); + +/* RFC 5639 curve over a 224 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP224t1); + +/* RFC 5639 curve over a 256 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP256r1); + +/* RFC 5639 curve over a 256 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP256t1); + +/* RFC 5639 curve over a 320 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP320r1); + +/* RFC 5639 curve over a 320 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP320t1); + +/* RFC 5639 curve over a 384 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP384r1); + +/* RFC 5639 curve over a 384 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP384t1); + +/* RFC 5639 curve over a 512 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP512r1); + +/* RFC 5639 curve over a 512 bit prime field */ +PROCESS_ECC_CURVE(brainpoolP512t1); + +/* SECG curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(secp160k1); + +/* SECG curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(secp192k1); + +/* SECG curve over a 224 bit prime field */ +PROCESS_ECC_CURVE(secp224k1); + +/* SECG curve over a 256 bit prime field */ +PROCESS_ECC_CURVE(secp256k1); + +/* BN curve 256 bits */ +PROCESS_ECC_CURVE(tpm_bm_p256); + +#if 0 +/* clang-format off */ +/* SECG/WTLS curve over a 112 bit prime field */ +PROCESS_ECC_CURVE(secp112r1); + +/* SECG curve over a 112 bit prime field */ +PROCESS_ECC_CURVE(secp112r2); + +/* SECG curve over a 128 bit prime field */ +PROCESS_ECC_CURVE(secp128r1); + +/* SECG curve over a 128 bit prime field */ +PROCESS_ECC_CURVE(secp128r2); + +/* SECG curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(secp160r1); + +/* SECG/WTLS curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(secp160r2); + + + +/* X9.62 curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(prime192v2); + +/* X9.62 curve over a 192 bit prime field */ +PROCESS_ECC_CURVE(prime192v3); + +/* X9.62 curve over a 239 bit prime field */ +PROCESS_ECC_CURVE(prime239v1); + +/* X9.62 curve over a 239 bit prime field */ +PROCESS_ECC_CURVE(prime239v2); + +/* X9.62 curve over a 239 bit prime field */ +PROCESS_ECC_CURVE(prime239v3); + + +/* SECG curve over a 113 bit binary field */ +PROCESS_ECC_CURVE(sect113r1); + +/* SECG curve over a 113 bit binary field */ +PROCESS_ECC_CURVE(sect113r2); + +/* SECG/WTLS curve over a 131 bit binary field */ +PROCESS_ECC_CURVE(sect131r1); + +/* SECG curve over a 131 bit binary field */ +PROCESS_ECC_CURVE(sect131r2); + +/* NIST/SECG/WTLS curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(sect163k1); + +/* SECG curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(sect163r1); + +/* NIST/SECG curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(sect163r2); + +/* SECG curve over a 193 bit binary field */ +PROCESS_ECC_CURVE(sect193r1); + +/* SECG curve over a 193 bit binary field */ +PROCESS_ECC_CURVE(sect193r2); + +/* NIST/SECG/WTLS curve over a 233 bit binary field */ +PROCESS_ECC_CURVE(sect233k1); + +/* NIST/SECG/WTLS curve over a 233 bit binary field */ +PROCESS_ECC_CURVE(sect233r1); + +/* SECG curve over a 239 bit binary field */ +PROCESS_ECC_CURVE(sect239k1); + +/* NIST/SECG curve over a 283 bit binary field */ +PROCESS_ECC_CURVE(sect283k1); + +/* NIST/SECG curve over a 283 bit binary field */ +PROCESS_ECC_CURVE(sect283r1); + +/* NIST/SECG curve over a 409 bit binary field */ +PROCESS_ECC_CURVE(sect409k1); + +/* NIST/SECG curve over a 409 bit binary field */ +PROCESS_ECC_CURVE(sect409r1); + +/* NIST/SECG curve over a 571 bit binary field */ +PROCESS_ECC_CURVE(sect571k1); + +/* NIST/SECG curve over a 571 bit binary field */ +PROCESS_ECC_CURVE(sect571r1); + +/* X9.62 curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(c2pnb163v1); + +/* X9.62 curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(c2pnb163v2); + +/* X9.62 curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(c2pnb163v3); + +/* X9.62 curve over a 176 bit binary field */ +PROCESS_ECC_CURVE(c2pnb176v1); + +/* X9.62 curve over a 191 bit binary field */ +PROCESS_ECC_CURVE(c2tnb191v1); + +/* X9.62 curve over a 191 bit binary field */ +PROCESS_ECC_CURVE(c2tnb191v2); + +/* X9.62 curve over a 191 bit binary field */ +PROCESS_ECC_CURVE(c2tnb191v3); + +/* X9.62 curve over a 208 bit binary field */ +PROCESS_ECC_CURVE(c2pnb208w1); + +/* X9.62 curve over a 239 bit binary field */ +PROCESS_ECC_CURVE(c2tnb239v1); + +/* X9.62 curve over a 239 bit binary field */ +PROCESS_ECC_CURVE(c2tnb239v2); + +/* X9.62 curve over a 239 bit binary field */ +PROCESS_ECC_CURVE(c2tnb239v3); + +/* X9.62 curve over a 272 bit binary field */ +PROCESS_ECC_CURVE(c2pnb272w1); + +/* X9.62 curve over a 304 bit binary field */ +PROCESS_ECC_CURVE(c2pnb304w1); + +/* X9.62 curve over a 359 bit binary field */ +PROCESS_ECC_CURVE(c2tnb359v1); + +/* X9.62 curve over a 368 bit binary field */ +PROCESS_ECC_CURVE(c2pnb368w1); + +/* X9.62 curve over a 431 bit binary field */ +PROCESS_ECC_CURVE(c2tnb431r1); + +/* WTLS curve over a 113 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls1); + +/* NIST/SECG/WTLS curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls3); + +/* SECG curve over a 113 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls4); + +/* X9.62 curve over a 163 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls5); + +/* SECG/WTLS curve over a 112 bit prime field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls6); + +/* SECG/WTLS curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls7); + +/* WTLS curve over a 112 bit prime field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls8); + +/* WTLS curve over a 160 bit prime field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls9); + +/* NIST/SECG/WTLS curve over a 233 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls10); + +/* NIST/SECG/WTLS curve over a 233 bit binary field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls11); + +/* WTLS curve over a 224 bit prime field */ +PROCESS_ECC_CURVE(wap_wsg_idm_ecid_wtls12); + +/* + IPSec/IKE/Oakley curve #3 over a 155 bit binary field. + Not suitable for ECDSA. + Questionable extension field! */ +PROCESS_ECC_CURVE(Oakley_EC2N_3); + +/* + IPSec/IKE/Oakley curve #4 over a 185 bit binary field. + Not suitable for ECDSA. + Questionable extension field! */ +PROCESS_ECC_CURVE(Oakley_EC2N_4); + + +/* clang-format on */ + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h new file mode 100644 index 00000000000..c7398db6695 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h @@ -0,0 +1,2801 @@ +/* +* +* Copyright 2018 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef SE05X_ECC_CURVES_LIST_H_INC +#define SE05X_ECC_CURVES_LIST_H_INC + +/* clang-format off */ + +#if 0 +/* secp112r1 : SECG/WTLS curve over a 112 bit prime field */ +#define EC_PARAM_secp112r1_prime \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x66, \ + 0x80, 0x76, 0xBE, 0xAD, 0x20, 0x8B +#define EC_PARAM_secp112r1_a \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x66, \ + 0x80, 0x76, 0xBE, 0xAD, 0x20, 0x88 +#define EC_PARAM_secp112r1_b \ + 0x65, 0x9E, 0xF8, 0xBA, 0x04, 0x39, 0x16, 0xEE, \ + 0xDE, 0x89, 0x11, 0x70, 0x2B, 0x22 +#define EC_PARAM_secp112r1_x \ + 0x09, 0x48, 0x72, 0x39, 0x99, 0x5A, 0x5E, 0xE7, \ + 0x6B, 0x55, 0xF9, 0xC2, 0xF0, 0x98 +#define EC_PARAM_secp112r1_y \ + 0xA8, 0x9C, 0xE5, 0xAF, 0x87, 0x24, 0xC0, 0xA2, \ + 0x3E, 0x0E, 0x0F, 0xF7, 0x75, 0x00 +#define EC_PARAM_secp112r1_order \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x76, \ + 0x28, 0xDF, 0xAC, 0x65, 0x61, 0xC5 +#endif + +#if 0 +/* secp112r2 : SECG curve over a 112 bit prime field */ +#define EC_PARAM_secp112r2_prime \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x66, \ + 0x80, 0x76, 0xBE, 0xAD, 0x20, 0x8B +#define EC_PARAM_secp112r2_a \ + 0x61, 0x27, 0xC2, 0x4C, 0x05, 0xF3, 0x8A, 0x0A, \ + 0xAA, 0xF6, 0x5C, 0x0E, 0xF0, 0x2C +#define EC_PARAM_secp112r2_b \ + 0x51, 0xDE, 0xF1, 0x81, 0x5D, 0xB5, 0xED, 0x74, \ + 0xFC, 0xC3, 0x4C, 0x85, 0xD7, 0x09 +#define EC_PARAM_secp112r2_x \ + 0x4B, 0xA3, 0x0A, 0xB5, 0xE8, 0x92, 0xB4, 0xE1, \ + 0x64, 0x9D, 0xD0, 0x92, 0x86, 0x43 +#define EC_PARAM_secp112r2_y \ + 0xAD, 0xCD, 0x46, 0xF5, 0x88, 0x2E, 0x37, 0x47, \ + 0xDE, 0xF3, 0x6E, 0x95, 0x6E, 0x97 +#define EC_PARAM_secp112r2_order \ + 0x36, 0xDF, 0x0A, 0xAF, 0xD8, 0xB8, 0xD7, 0x59, \ + 0x7C, 0xA1, 0x05, 0x20, 0xD0, 0x4B +#endif + +#if 0 +/* secp128r1 : SECG curve over a 128 bit prime field */ +#define EC_PARAM_secp128r1_prime \ + 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_secp128r1_a \ + 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_secp128r1_b \ + 0xE8, 0x75, 0x79, 0xC1, 0x10, 0x79, 0xF4, 0x3D, \ + 0xD8, 0x24, 0x99, 0x3C, 0x2C, 0xEE, 0x5E, 0xD3 +#define EC_PARAM_secp128r1_x \ + 0x16, 0x1F, 0xF7, 0x52, 0x8B, 0x89, 0x9B, 0x2D, \ + 0x0C, 0x28, 0x60, 0x7C, 0xA5, 0x2C, 0x5B, 0x86 +#define EC_PARAM_secp128r1_y \ + 0xCF, 0x5A, 0xC8, 0x39, 0x5B, 0xAF, 0xEB, 0x13, \ + 0xC0, 0x2D, 0xA2, 0x92, 0xDD, 0xED, 0x7A, 0x83 +#define EC_PARAM_secp128r1_order \ + 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x00, \ + 0x75, 0xA3, 0x0D, 0x1B, 0x90, 0x38, 0xA1, 0x15 +#endif + +#if 0 +/* secp128r2 : SECG curve over a 128 bit prime field */ +#define EC_PARAM_secp128r2_prime \ + 0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_secp128r2_a \ + 0xD6, 0x03, 0x19, 0x98, 0xD1, 0xB3, 0xBB, 0xFE, \ + 0xBF, 0x59, 0xCC, 0x9B, 0xBF, 0xF9, 0xAE, 0xE1 +#define EC_PARAM_secp128r2_b \ + 0x5E, 0xEE, 0xFC, 0xA3, 0x80, 0xD0, 0x29, 0x19, \ + 0xDC, 0x2C, 0x65, 0x58, 0xBB, 0x6D, 0x8A, 0x5D +#define EC_PARAM_secp128r2_x \ + 0x7B, 0x6A, 0xA5, 0xD8, 0x5E, 0x57, 0x29, 0x83, \ + 0xE6, 0xFB, 0x32, 0xA7, 0xCD, 0xEB, 0xC1, 0x40 +#define EC_PARAM_secp128r2_y \ + 0x27, 0xB6, 0x91, 0x6A, 0x89, 0x4D, 0x3A, 0xEE, \ + 0x71, 0x06, 0xFE, 0x80, 0x5F, 0xC3, 0x4B, 0x44 +#define EC_PARAM_secp128r2_order \ + 0x3F, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xBE, 0x00, 0x24, 0x72, 0x06, 0x13, 0xB5, 0xA3 +#endif + +#if 1 +/* secp160k1 : SECG curve over a 160 bit prime field */ +#define EC_PARAM_secp160k1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xAC, 0x73 +#define EC_PARAM_secp160k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_secp160k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x07 +#define EC_PARAM_secp160k1_x \ + 0x3B, 0x4C, 0x38, 0x2C, 0xE3, 0x7A, 0xA1, \ + 0x92, 0xA4, 0x01, 0x9E, 0x76, 0x30, 0x36, 0xF4, \ + 0xF5, 0xDD, 0x4D, 0x7E, 0xBB +#define EC_PARAM_secp160k1_y \ + 0x93, 0x8C, 0xF9, 0x35, 0x31, 0x8F, 0xDC, \ + 0xED, 0x6B, 0xC2, 0x82, 0x86, 0x53, 0x17, 0x33, \ + 0xC3, 0xF0, 0x3C, 0x4F, 0xEE +#define EC_PARAM_secp160k1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xB8, 0xFA, 0x16, 0xDF, 0xAB, \ + 0x9A, 0xCA, 0x16, 0xB6, 0xB3 +#endif + +#if 0 +/* secp160r1 : SECG curve over a 160 bit prime field */ +#define EC_PARAM_secp160r1_prime \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0x7F, 0xFF, 0xFF, 0xFF +#define EC_PARAM_secp160r1_a \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0x7F, 0xFF, 0xFF, 0xFC +#define EC_PARAM_secp160r1_b \ + 0x00, 0x1C, 0x97, 0xBE, 0xFC, 0x54, 0xBD, 0x7A, \ + 0x8B, 0x65, 0xAC, 0xF8, 0x9F, 0x81, 0xD4, 0xD4, \ + 0xAD, 0xC5, 0x65, 0xFA, 0x45 +#define EC_PARAM_secp160r1_x \ + 0x00, 0x4A, 0x96, 0xB5, 0x68, 0x8E, 0xF5, 0x73, \ + 0x28, 0x46, 0x64, 0x69, 0x89, 0x68, 0xC3, 0x8B, \ + 0xB9, 0x13, 0xCB, 0xFC, 0x82 +#define EC_PARAM_secp160r1_y \ + 0x00, 0x23, 0xA6, 0x28, 0x55, 0x31, 0x68, 0x94, \ + 0x7D, 0x59, 0xDC, 0xC9, 0x12, 0x04, 0x23, 0x51, \ + 0x37, 0x7A, 0xC5, 0xFB, 0x32 +#define EC_PARAM_secp160r1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xF4, 0xC8, 0xF9, 0x27, 0xAE, \ + 0xD3, 0xCA, 0x75, 0x22, 0x57 +#endif + +#if 0 +/* secp160r2 : SECG/WTLS curve over a 160 bit prime field */ +#define EC_PARAM_secp160r2_prime \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xAC, 0x73 +#define EC_PARAM_secp160r2_a \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xAC, 0x70 +#define EC_PARAM_secp160r2_b \ + 0x00, 0xB4, 0xE1, 0x34, 0xD3, 0xFB, 0x59, 0xEB, \ + 0x8B, 0xAB, 0x57, 0x27, 0x49, 0x04, 0x66, 0x4D, \ + 0x5A, 0xF5, 0x03, 0x88, 0xBA +#define EC_PARAM_secp160r2_x \ + 0x00, 0x52, 0xDC, 0xB0, 0x34, 0x29, 0x3A, 0x11, \ + 0x7E, 0x1F, 0x4F, 0xF1, 0x1B, 0x30, 0xF7, 0x19, \ + 0x9D, 0x31, 0x44, 0xCE, 0x6D +#define EC_PARAM_secp160r2_y \ + 0x00, 0xFE, 0xAF, 0xFE, 0xF2, 0xE3, 0x31, 0xF2, \ + 0x96, 0xE0, 0x71, 0xFA, 0x0D, 0xF9, 0x98, 0x2C, \ + 0xFE, 0xA7, 0xD4, 0x3F, 0x2E +#define EC_PARAM_secp160r2_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x35, 0x1E, 0xE7, 0x86, 0xA8, \ + 0x18, 0xF3, 0xA1, 0xA1, 0x6B +#endif + +#if 1 +/* secp192k1 : SECG curve over a 192 bit prime field */ +#define EC_PARAM_secp192k1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xEE, 0x37 +#define EC_PARAM_secp192k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_secp192k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 +#define EC_PARAM_secp192k1_x \ + 0xDB, 0x4F, 0xF1, 0x0E, 0xC0, 0x57, 0xE9, 0xAE, \ + 0x26, 0xB0, 0x7D, 0x02, 0x80, 0xB7, 0xF4, 0x34, \ + 0x1D, 0xA5, 0xD1, 0xB1, 0xEA, 0xE0, 0x6C, 0x7D +#define EC_PARAM_secp192k1_y \ + 0x9B, 0x2F, 0x2F, 0x6D, 0x9C, 0x56, 0x28, 0xA7, \ + 0x84, 0x41, 0x63, 0xD0, 0x15, 0xBE, 0x86, 0x34, \ + 0x40, 0x82, 0xAA, 0x88, 0xD9, 0x5E, 0x2F, 0x9D +#define EC_PARAM_secp192k1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE, 0x26, 0xF2, 0xFC, 0x17, \ + 0x0F, 0x69, 0x46, 0x6A, 0x74, 0xDE, 0xFD, 0x8D +#endif + +#if 1 +/* secp224k1 : SECG curve over a 224 bit prime field */ +#define EC_PARAM_secp224k1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xE5, 0x6D +#define EC_PARAM_secp224k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_secp224k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x05 +#define EC_PARAM_secp224k1_x \ + 0xA1, 0x45, 0x5B, 0x33, 0x4D, 0xF0, 0x99, \ + 0xDF, 0x30, 0xFC, 0x28, 0xA1, 0x69, 0xA4, 0x67, \ + 0xE9, 0xE4, 0x70, 0x75, 0xA9, 0x0F, 0x7E, 0x65, \ + 0x0E, 0xB6, 0xB7, 0xA4, 0x5C +#define EC_PARAM_secp224k1_y \ + 0x7E, 0x08, 0x9F, 0xED, 0x7F, 0xBA, 0x34, \ + 0x42, 0x82, 0xCA, 0xFB, 0xD6, 0xF7, 0xE3, 0x19, \ + 0xF7, 0xC0, 0xB0, 0xBD, 0x59, 0xE2, 0xCA, 0x4B, \ + 0xDB, 0x55, 0x6D, 0x61, 0xA5 +#define EC_PARAM_secp224k1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xDC, \ + 0xE8, 0xD2, 0xEC, 0x61, 0x84, 0xCA, 0xF0, 0xA9, \ + 0x71, 0x76, 0x9F, 0xB1, 0xF7 +#endif + +#if 1 +/* secp224r1 : NIST/SECG curve over a 224 bit prime field */ +#define EC_PARAM_secp224r1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_secp224r1_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE +#define EC_PARAM_secp224r1_b \ + 0xB4, 0x05, 0x0A, 0x85, 0x0C, 0x04, 0xB3, 0xAB, \ + 0xF5, 0x41, 0x32, 0x56, 0x50, 0x44, 0xB0, 0xB7, \ + 0xD7, 0xBF, 0xD8, 0xBA, 0x27, 0x0B, 0x39, 0x43, \ + 0x23, 0x55, 0xFF, 0xB4 +#define EC_PARAM_secp224r1_x \ + 0xB7, 0x0E, 0x0C, 0xBD, 0x6B, 0xB4, 0xBF, 0x7F, \ + 0x32, 0x13, 0x90, 0xB9, 0x4A, 0x03, 0xC1, 0xD3, \ + 0x56, 0xC2, 0x11, 0x22, 0x34, 0x32, 0x80, 0xD6, \ + 0x11, 0x5C, 0x1D, 0x21 +#define EC_PARAM_secp224r1_y \ + 0xBD, 0x37, 0x63, 0x88, 0xB5, 0xF7, 0x23, 0xFB, \ + 0x4C, 0x22, 0xDF, 0xE6, 0xCD, 0x43, 0x75, 0xA0, \ + 0x5A, 0x07, 0x47, 0x64, 0x44, 0xD5, 0x81, 0x99, \ + 0x85, 0x00, 0x7E, 0x34 +#define EC_PARAM_secp224r1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x16, 0xA2, \ + 0xE0, 0xB8, 0xF0, 0x3E, 0x13, 0xDD, 0x29, 0x45, \ + 0x5C, 0x5C, 0x2A, 0x3D +#endif + +#if 1 +/* secp256k1 : SECG curve over a 256 bit prime field */ +#define EC_PARAM_secp256k1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F +#define EC_PARAM_secp256k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_secp256k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 +#define EC_PARAM_secp256k1_x \ + 0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, \ + 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07, \ + 0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, \ + 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98 +#define EC_PARAM_secp256k1_y \ + 0x48, 0x3A, 0xDA, 0x77, 0x26, 0xA3, 0xC4, 0x65, \ + 0x5D, 0xA4, 0xFB, 0xFC, 0x0E, 0x11, 0x08, 0xA8, \ + 0xFD, 0x17, 0xB4, 0x48, 0xA6, 0x85, 0x54, 0x19, \ + 0x9C, 0x47, 0xD0, 0x8F, 0xFB, 0x10, 0xD4, 0xB8 +#define EC_PARAM_secp256k1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, \ + 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41 +#endif + +#if 1 +/* secp384r1 : NIST/SECG curve over a 384 bit prime field */ +#define EC_PARAM_secp384r1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_secp384r1_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_secp384r1_b \ + 0xB3, 0x31, 0x2F, 0xA7, 0xE2, 0x3E, 0xE7, 0xE4, \ + 0x98, 0x8E, 0x05, 0x6B, 0xE3, 0xF8, 0x2D, 0x19, \ + 0x18, 0x1D, 0x9C, 0x6E, 0xFE, 0x81, 0x41, 0x12, \ + 0x03, 0x14, 0x08, 0x8F, 0x50, 0x13, 0x87, 0x5A, \ + 0xC6, 0x56, 0x39, 0x8D, 0x8A, 0x2E, 0xD1, 0x9D, \ + 0x2A, 0x85, 0xC8, 0xED, 0xD3, 0xEC, 0x2A, 0xEF +#define EC_PARAM_secp384r1_x \ + 0xAA, 0x87, 0xCA, 0x22, 0xBE, 0x8B, 0x05, 0x37, \ + 0x8E, 0xB1, 0xC7, 0x1E, 0xF3, 0x20, 0xAD, 0x74, \ + 0x6E, 0x1D, 0x3B, 0x62, 0x8B, 0xA7, 0x9B, 0x98, \ + 0x59, 0xF7, 0x41, 0xE0, 0x82, 0x54, 0x2A, 0x38, \ + 0x55, 0x02, 0xF2, 0x5D, 0xBF, 0x55, 0x29, 0x6C, \ + 0x3A, 0x54, 0x5E, 0x38, 0x72, 0x76, 0x0A, 0xB7 +#define EC_PARAM_secp384r1_y \ + 0x36, 0x17, 0xDE, 0x4A, 0x96, 0x26, 0x2C, 0x6F, \ + 0x5D, 0x9E, 0x98, 0xBF, 0x92, 0x92, 0xDC, 0x29, \ + 0xF8, 0xF4, 0x1D, 0xBD, 0x28, 0x9A, 0x14, 0x7C, \ + 0xE9, 0xDA, 0x31, 0x13, 0xB5, 0xF0, 0xB8, 0xC0, \ + 0x0A, 0x60, 0xB1, 0xCE, 0x1D, 0x7E, 0x81, 0x9D, \ + 0x7A, 0x43, 0x1D, 0x7C, 0x90, 0xEA, 0x0E, 0x5F +#define EC_PARAM_secp384r1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xC7, 0x63, 0x4D, 0x81, 0xF4, 0x37, 0x2D, 0xDF, \ + 0x58, 0x1A, 0x0D, 0xB2, 0x48, 0xB0, 0xA7, 0x7A, \ + 0xEC, 0xEC, 0x19, 0x6A, 0xCC, 0xC5, 0x29, 0x73 +#endif + +#if 1 +/* secp521r1 : NIST/SECG curve over a 521 bit prime field */ +#define EC_PARAM_secp521r1_prime \ + 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF +#define EC_PARAM_secp521r1_a \ + 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFC +#define EC_PARAM_secp521r1_b \ + 0x00, 0x51, 0x95, 0x3E, 0xB9, 0x61, 0x8E, 0x1C, \ + 0x9A, 0x1F, 0x92, 0x9A, 0x21, 0xA0, 0xB6, 0x85, \ + 0x40, 0xEE, 0xA2, 0xDA, 0x72, 0x5B, 0x99, 0xB3, \ + 0x15, 0xF3, 0xB8, 0xB4, 0x89, 0x91, 0x8E, 0xF1, \ + 0x09, 0xE1, 0x56, 0x19, 0x39, 0x51, 0xEC, 0x7E, \ + 0x93, 0x7B, 0x16, 0x52, 0xC0, 0xBD, 0x3B, 0xB1, \ + 0xBF, 0x07, 0x35, 0x73, 0xDF, 0x88, 0x3D, 0x2C, \ + 0x34, 0xF1, 0xEF, 0x45, 0x1F, 0xD4, 0x6B, 0x50, \ + 0x3F, 0x00 +#define EC_PARAM_secp521r1_x \ + 0x00, 0xC6, 0x85, 0x8E, 0x06, 0xB7, 0x04, 0x04, \ + 0xE9, 0xCD, 0x9E, 0x3E, 0xCB, 0x66, 0x23, 0x95, \ + 0xB4, 0x42, 0x9C, 0x64, 0x81, 0x39, 0x05, 0x3F, \ + 0xB5, 0x21, 0xF8, 0x28, 0xAF, 0x60, 0x6B, 0x4D, \ + 0x3D, 0xBA, 0xA1, 0x4B, 0x5E, 0x77, 0xEF, 0xE7, \ + 0x59, 0x28, 0xFE, 0x1D, 0xC1, 0x27, 0xA2, 0xFF, \ + 0xA8, 0xDE, 0x33, 0x48, 0xB3, 0xC1, 0x85, 0x6A, \ + 0x42, 0x9B, 0xF9, 0x7E, 0x7E, 0x31, 0xC2, 0xE5, \ + 0xBD, 0x66 +#define EC_PARAM_secp521r1_y \ + 0x01, 0x18, 0x39, 0x29, 0x6A, 0x78, 0x9A, 0x3B, \ + 0xC0, 0x04, 0x5C, 0x8A, 0x5F, 0xB4, 0x2C, 0x7D, \ + 0x1B, 0xD9, 0x98, 0xF5, 0x44, 0x49, 0x57, 0x9B, \ + 0x44, 0x68, 0x17, 0xAF, 0xBD, 0x17, 0x27, 0x3E, \ + 0x66, 0x2C, 0x97, 0xEE, 0x72, 0x99, 0x5E, 0xF4, \ + 0x26, 0x40, 0xC5, 0x50, 0xB9, 0x01, 0x3F, 0xAD, \ + 0x07, 0x61, 0x35, 0x3C, 0x70, 0x86, 0xA2, 0x72, \ + 0xC2, 0x40, 0x88, 0xBE, 0x94, 0x76, 0x9F, 0xD1, \ + 0x66, 0x50 +#define EC_PARAM_secp521r1_order \ + 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFA, 0x51, 0x86, 0x87, 0x83, 0xBF, 0x2F, \ + 0x96, 0x6B, 0x7F, 0xCC, 0x01, 0x48, 0xF7, 0x09, \ + 0xA5, 0xD0, 0x3B, 0xB5, 0xC9, 0xB8, 0x89, 0x9C, \ + 0x47, 0xAE, 0xBB, 0x6F, 0xB7, 0x1E, 0x91, 0x38, \ + 0x64, 0x09 +#endif + +#if 1 +/* prime192v1 : NIST/X9.62/SECG curve over a 192 bit prime field */ +#define EC_PARAM_prime192v1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime192v1_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime192v1_b \ + 0x64, 0x21, 0x05, 0x19, 0xE5, 0x9C, 0x80, 0xE7, \ + 0x0F, 0xA7, 0xE9, 0xAB, 0x72, 0x24, 0x30, 0x49, \ + 0xFE, 0xB8, 0xDE, 0xEC, 0xC1, 0x46, 0xB9, 0xB1 +#define EC_PARAM_prime192v1_x \ + 0x18, 0x8D, 0xA8, 0x0E, 0xB0, 0x30, 0x90, 0xF6, \ + 0x7C, 0xBF, 0x20, 0xEB, 0x43, 0xA1, 0x88, 0x00, \ + 0xF4, 0xFF, 0x0A, 0xFD, 0x82, 0xFF, 0x10, 0x12 +#define EC_PARAM_prime192v1_y \ + 0x07, 0x19, 0x2B, 0x95, 0xFF, 0xC8, 0xDA, 0x78, \ + 0x63, 0x10, 0x11, 0xED, 0x6B, 0x24, 0xCD, 0xD5, \ + 0x73, 0xF9, 0x77, 0xA1, 0x1E, 0x79, 0x48, 0x11 +#define EC_PARAM_prime192v1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0xDE, 0xF8, 0x36, \ + 0x14, 0x6B, 0xC9, 0xB1, 0xB4, 0xD2, 0x28, 0x31 +#endif + +#if 0 +/* prime192v2 : X9.62 curve over a 192 bit prime field */ +#define EC_PARAM_prime192v2_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime192v2_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime192v2_b \ + 0xCC, 0x22, 0xD6, 0xDF, 0xB9, 0x5C, 0x6B, 0x25, \ + 0xE4, 0x9C, 0x0D, 0x63, 0x64, 0xA4, 0xE5, 0x98, \ + 0x0C, 0x39, 0x3A, 0xA2, 0x16, 0x68, 0xD9, 0x53 +#define EC_PARAM_prime192v2_x \ + 0xEE, 0xA2, 0xBA, 0xE7, 0xE1, 0x49, 0x78, 0x42, \ + 0xF2, 0xDE, 0x77, 0x69, 0xCF, 0xE9, 0xC9, 0x89, \ + 0xC0, 0x72, 0xAD, 0x69, 0x6F, 0x48, 0x03, 0x4A +#define EC_PARAM_prime192v2_y \ + 0x65, 0x74, 0xD1, 0x1D, 0x69, 0xB6, 0xEC, 0x7A, \ + 0x67, 0x2B, 0xB8, 0x2A, 0x08, 0x3D, 0xF2, 0xF2, \ + 0xB0, 0x84, 0x7D, 0xE9, 0x70, 0xB2, 0xDE, 0x15 +#define EC_PARAM_prime192v2_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE, 0x5F, 0xB1, 0xA7, 0x24, \ + 0xDC, 0x80, 0x41, 0x86, 0x48, 0xD8, 0xDD, 0x31 +#endif + +#if 0 +/* prime192v3 : X9.62 curve over a 192 bit prime field */ +#define EC_PARAM_prime192v3_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime192v3_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime192v3_b \ + 0x22, 0x12, 0x3D, 0xC2, 0x39, 0x5A, 0x05, 0xCA, \ + 0xA7, 0x42, 0x3D, 0xAE, 0xCC, 0xC9, 0x47, 0x60, \ + 0xA7, 0xD4, 0x62, 0x25, 0x6B, 0xD5, 0x69, 0x16 +#define EC_PARAM_prime192v3_x \ + 0x7D, 0x29, 0x77, 0x81, 0x00, 0xC6, 0x5A, 0x1D, \ + 0xA1, 0x78, 0x37, 0x16, 0x58, 0x8D, 0xCE, 0x2B, \ + 0x8B, 0x4A, 0xEE, 0x8E, 0x22, 0x8F, 0x18, 0x96 +#define EC_PARAM_prime192v3_y \ + 0x38, 0xA9, 0x0F, 0x22, 0x63, 0x73, 0x37, 0x33, \ + 0x4B, 0x49, 0xDC, 0xB6, 0x6A, 0x6D, 0xC8, 0xF9, \ + 0x97, 0x8A, 0xCA, 0x76, 0x48, 0xA9, 0x43, 0xB0 +#define EC_PARAM_prime192v3_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7A, 0x62, 0xD0, 0x31, \ + 0xC8, 0x3F, 0x42, 0x94, 0xF6, 0x40, 0xEC, 0x13 +#endif + +#if 0 +/* prime239v1 : X9.62 curve over a 239 bit prime field */ +#define EC_PARAM_prime239v1_prime \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime239v1_a \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime239v1_b \ + 0x6B, 0x01, 0x6C, 0x3B, 0xDC, 0xF1, 0x89, 0x41, \ + 0xD0, 0xD6, 0x54, 0x92, 0x14, 0x75, 0xCA, 0x71, \ + 0xA9, 0xDB, 0x2F, 0xB2, 0x7D, 0x1D, 0x37, 0x79, \ + 0x61, 0x85, 0xC2, 0x94, 0x2C, 0x0A +#define EC_PARAM_prime239v1_x \ + 0x0F, 0xFA, 0x96, 0x3C, 0xDC, 0xA8, 0x81, 0x6C, \ + 0xCC, 0x33, 0xB8, 0x64, 0x2B, 0xED, 0xF9, 0x05, \ + 0xC3, 0xD3, 0x58, 0x57, 0x3D, 0x3F, 0x27, 0xFB, \ + 0xBD, 0x3B, 0x3C, 0xB9, 0xAA, 0xAF +#define EC_PARAM_prime239v1_y \ + 0x7D, 0xEB, 0xE8, 0xE4, 0xE9, 0x0A, 0x5D, 0xAE, \ + 0x6E, 0x40, 0x54, 0xCA, 0x53, 0x0B, 0xA0, 0x46, \ + 0x54, 0xB3, 0x68, 0x18, 0xCE, 0x22, 0x6B, 0x39, \ + 0xFC, 0xCB, 0x7B, 0x02, 0xF1, 0xAE +#define EC_PARAM_prime239v1_order \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x9E, \ + 0x5E, 0x9A, 0x9F, 0x5D, 0x90, 0x71, 0xFB, 0xD1, \ + 0x52, 0x26, 0x88, 0x90, 0x9D, 0x0B +#endif + +#if 0 +/* prime239v2 : X9.62 curve over a 239 bit prime field */ +#define EC_PARAM_prime239v2_prime \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime239v2_a \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime239v2_b \ + 0x61, 0x7F, 0xAB, 0x68, 0x32, 0x57, 0x6C, 0xBB, \ + 0xFE, 0xD5, 0x0D, 0x99, 0xF0, 0x24, 0x9C, 0x3F, \ + 0xEE, 0x58, 0xB9, 0x4B, 0xA0, 0x03, 0x8C, 0x7A, \ + 0xE8, 0x4C, 0x8C, 0x83, 0x2F, 0x2C +#define EC_PARAM_prime239v2_x \ + 0x38, 0xAF, 0x09, 0xD9, 0x87, 0x27, 0x70, 0x51, \ + 0x20, 0xC9, 0x21, 0xBB, 0x5E, 0x9E, 0x26, 0x29, \ + 0x6A, 0x3C, 0xDC, 0xF2, 0xF3, 0x57, 0x57, 0xA0, \ + 0xEA, 0xFD, 0x87, 0xB8, 0x30, 0xE7 +#define EC_PARAM_prime239v2_y \ + 0x5B, 0x01, 0x25, 0xE4, 0xDB, 0xEA, 0x0E, 0xC7, \ + 0x20, 0x6D, 0xA0, 0xFC, 0x01, 0xD9, 0xB0, 0x81, \ + 0x32, 0x9F, 0xB5, 0x55, 0xDE, 0x6E, 0xF4, 0x60, \ + 0x23, 0x7D, 0xFF, 0x8B, 0xE4, 0xBA +#define EC_PARAM_prime239v2_order \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0xCF, \ + 0xA7, 0xE8, 0x59, 0x43, 0x77, 0xD4, 0x14, 0xC0, \ + 0x38, 0x21, 0xBC, 0x58, 0x20, 0x63 +#endif + +#if 0 +/* prime239v3 : X9.62 curve over a 239 bit prime field */ +#define EC_PARAM_prime239v3_prime \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime239v3_a \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime239v3_b \ + 0x25, 0x57, 0x05, 0xFA, 0x2A, 0x30, 0x66, 0x54, \ + 0xB1, 0xF4, 0xCB, 0x03, 0xD6, 0xA7, 0x50, 0xA3, \ + 0x0C, 0x25, 0x01, 0x02, 0xD4, 0x98, 0x87, 0x17, \ + 0xD9, 0xBA, 0x15, 0xAB, 0x6D, 0x3E +#define EC_PARAM_prime239v3_x \ + 0x67, 0x68, 0xAE, 0x8E, 0x18, 0xBB, 0x92, 0xCF, \ + 0xCF, 0x00, 0x5C, 0x94, 0x9A, 0xA2, 0xC6, 0xD9, \ + 0x48, 0x53, 0xD0, 0xE6, 0x60, 0xBB, 0xF8, 0x54, \ + 0xB1, 0xC9, 0x50, 0x5F, 0xE9, 0x5A +#define EC_PARAM_prime239v3_y \ + 0x16, 0x07, 0xE6, 0x89, 0x8F, 0x39, 0x0C, 0x06, \ + 0xBC, 0x1D, 0x55, 0x2B, 0xAD, 0x22, 0x6F, 0x3B, \ + 0x6F, 0xCF, 0xE4, 0x8B, 0x6E, 0x81, 0x84, 0x99, \ + 0xAF, 0x18, 0xE3, 0xED, 0x6C, 0xF3 +#define EC_PARAM_prime239v3_order \ + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x97, \ + 0x5D, 0xEB, 0x41, 0xB3, 0xA6, 0x05, 0x7C, 0x3C, \ + 0x43, 0x21, 0x46, 0x52, 0x65, 0x51 +#endif + +#if 1 +/* prime256v1 : X9.62/SECG curve over a 256 bit prime field */ +#define EC_PARAM_prime256v1_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x01, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +#define EC_PARAM_prime256v1_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x01, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC +#define EC_PARAM_prime256v1_b \ + 0x5A, 0xC6, 0x35, 0xD8, 0xAA, 0x3A, 0x93, 0xE7, \ + 0xB3, 0xEB, 0xBD, 0x55, 0x76, 0x98, 0x86, 0xBC, \ + 0x65, 0x1D, 0x06, 0xB0, 0xCC, 0x53, 0xB0, 0xF6, \ + 0x3B, 0xCE, 0x3C, 0x3E, 0x27, 0xD2, 0x60, 0x4B +#define EC_PARAM_prime256v1_x \ + 0x6B, 0x17, 0xD1, 0xF2, 0xE1, 0x2C, 0x42, 0x47, \ + 0xF8, 0xBC, 0xE6, 0xE5, 0x63, 0xA4, 0x40, 0xF2, \ + 0x77, 0x03, 0x7D, 0x81, 0x2D, 0xEB, 0x33, 0xA0, \ + 0xF4, 0xA1, 0x39, 0x45, 0xD8, 0x98, 0xC2, 0x96 +#define EC_PARAM_prime256v1_y \ + 0x4F, 0xE3, 0x42, 0xE2, 0xFE, 0x1A, 0x7F, 0x9B, \ + 0x8E, 0xE7, 0xEB, 0x4A, 0x7C, 0x0F, 0x9E, 0x16, \ + 0x2B, 0xCE, 0x33, 0x57, 0x6B, 0x31, 0x5E, 0xCE, \ + 0xCB, 0xB6, 0x40, 0x68, 0x37, 0xBF, 0x51, 0xF5 +#define EC_PARAM_prime256v1_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xBC, 0xE6, 0xFA, 0xAD, 0xA7, 0x17, 0x9E, 0x84, \ + 0xF3, 0xB9, 0xCA, 0xC2, 0xFC, 0x63, 0x25, 0x51 +#endif + +#if 0 +/* sect113r1 : SECG curve over a 113 bit binary field */ +#define EC_PARAM_sect113r1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_sect113r1_a \ + 0x00, 0x30, 0x88, 0x25, 0x0C, 0xA6, 0xE7, 0xC7, \ + 0xFE, 0x64, 0x9C, 0xE8, 0x58, 0x20, 0xF7 +#define EC_PARAM_sect113r1_b \ + 0x00, 0xE8, 0xBE, 0xE4, 0xD3, 0xE2, 0x26, 0x07, \ + 0x44, 0x18, 0x8B, 0xE0, 0xE9, 0xC7, 0x23 +#define EC_PARAM_sect113r1_x \ + 0x00, 0x9D, 0x73, 0x61, 0x6F, 0x35, 0xF4, 0xAB, \ + 0x14, 0x07, 0xD7, 0x35, 0x62, 0xC1, 0x0F +#define EC_PARAM_sect113r1_y \ + 0x00, 0xA5, 0x28, 0x30, 0x27, 0x79, 0x58, 0xEE, \ + 0x84, 0xD1, 0x31, 0x5E, 0xD3, 0x18, 0x86 +#define EC_PARAM_sect113r1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0xD9, 0xCC, 0xEC, 0x8A, 0x39, 0xE5, 0x6F +#endif + +#if 0 +/* sect113r2 : SECG curve over a 113 bit binary field */ +#define EC_PARAM_sect113r2_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_sect113r2_a \ + 0x00, 0x68, 0x99, 0x18, 0xDB, 0xEC, 0x7E, 0x5A, \ + 0x0D, 0xD6, 0xDF, 0xC0, 0xAA, 0x55, 0xC7 +#define EC_PARAM_sect113r2_b \ + 0x00, 0x95, 0xE9, 0xA9, 0xEC, 0x9B, 0x29, 0x7B, \ + 0xD4, 0xBF, 0x36, 0xE0, 0x59, 0x18, 0x4F +#define EC_PARAM_sect113r2_x \ + 0x01, 0xA5, 0x7A, 0x6A, 0x7B, 0x26, 0xCA, 0x5E, \ + 0xF5, 0x2F, 0xCD, 0xB8, 0x16, 0x47, 0x97 +#define EC_PARAM_sect113r2_y \ + 0x00, 0xB3, 0xAD, 0xC9, 0x4E, 0xD1, 0xFE, 0x67, \ + 0x4C, 0x06, 0xE6, 0x95, 0xBA, 0xBA, 0x1D +#define EC_PARAM_sect113r2_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, \ + 0x08, 0x78, 0x9B, 0x24, 0x96, 0xAF, 0x93 +#endif + +#if 0 +/* sect131r1 : SECG/WTLS curve over a 131 bit binary field */ +#define EC_PARAM_sect131r1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, \ + 0x0D +#define EC_PARAM_sect131r1_a \ + 0x07, 0xA1, 0x1B, 0x09, 0xA7, 0x6B, 0x56, 0x21, \ + 0x44, 0x41, 0x8F, 0xF3, 0xFF, 0x8C, 0x25, 0x70, \ + 0xB8 +#define EC_PARAM_sect131r1_b \ + 0x02, 0x17, 0xC0, 0x56, 0x10, 0x88, 0x4B, 0x63, \ + 0xB9, 0xC6, 0xC7, 0x29, 0x16, 0x78, 0xF9, 0xD3, \ + 0x41 +#define EC_PARAM_sect131r1_x \ + 0x00, 0x81, 0xBA, 0xF9, 0x1F, 0xDF, 0x98, 0x33, \ + 0xC4, 0x0F, 0x9C, 0x18, 0x13, 0x43, 0x63, 0x83, \ + 0x99 +#define EC_PARAM_sect131r1_y \ + 0x07, 0x8C, 0x6E, 0x7E, 0xA3, 0x8C, 0x00, 0x1F, \ + 0x73, 0xC8, 0x13, 0x4B, 0x1B, 0x4E, 0xF9, 0xE1, \ + 0x50 +#define EC_PARAM_sect131r1_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x02, 0x31, 0x23, 0x95, 0x3A, 0x94, 0x64, 0xB5, \ + 0x4D +#endif + +#if 0 +/* sect131r2 : SECG curve over a 131 bit binary field */ +#define EC_PARAM_sect131r2_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, \ + 0x0D +#define EC_PARAM_sect131r2_a \ + 0x03, 0xE5, 0xA8, 0x89, 0x19, 0xD7, 0xCA, 0xFC, \ + 0xBF, 0x41, 0x5F, 0x07, 0xC2, 0x17, 0x65, 0x73, \ + 0xB2 +#define EC_PARAM_sect131r2_b \ + 0x04, 0xB8, 0x26, 0x6A, 0x46, 0xC5, 0x56, 0x57, \ + 0xAC, 0x73, 0x4C, 0xE3, 0x8F, 0x01, 0x8F, 0x21, \ + 0x92 +#define EC_PARAM_sect131r2_x \ + 0x03, 0x56, 0xDC, 0xD8, 0xF2, 0xF9, 0x50, 0x31, \ + 0xAD, 0x65, 0x2D, 0x23, 0x95, 0x1B, 0xB3, 0x66, \ + 0xA8 +#define EC_PARAM_sect131r2_y \ + 0x06, 0x48, 0xF0, 0x6D, 0x86, 0x79, 0x40, 0xA5, \ + 0x36, 0x6D, 0x9E, 0x26, 0x5D, 0xE9, 0xEB, 0x24, \ + 0x0F +#define EC_PARAM_sect131r2_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x01, 0x69, 0x54, 0xA2, 0x33, 0x04, 0x9B, 0xA9, \ + 0x8F +#endif + +#if 0 +/* sect163k1 : NIST/SECG/WTLS curve over a 163 bit binary field */ +#define EC_PARAM_sect163k1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xC9 +#define EC_PARAM_sect163k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect163k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect163k1_x \ + 0x02, 0xFE, 0x13, 0xC0, 0x53, 0x7B, 0xBC, 0x11, \ + 0xAC, 0xAA, 0x07, 0xD7, 0x93, 0xDE, 0x4E, 0x6D, \ + 0x5E, 0x5C, 0x94, 0xEE, 0xE8 +#define EC_PARAM_sect163k1_y \ + 0x02, 0x89, 0x07, 0x0F, 0xB0, 0x5D, 0x38, 0xFF, \ + 0x58, 0x32, 0x1F, 0x2E, 0x80, 0x05, 0x36, 0xD5, \ + 0x38, 0xCC, 0xDA, 0xA3, 0xD9 +#define EC_PARAM_sect163k1_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x02, 0x01, 0x08, 0xA2, 0xE0, 0xCC, \ + 0x0D, 0x99, 0xF8, 0xA5, 0xEF +#endif + +#if 0 +/* sect163r1 : SECG curve over a 163 bit binary field */ +#define EC_PARAM_sect163r1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xC9 +#define EC_PARAM_sect163r1_a \ + 0x07, 0xB6, 0x88, 0x2C, 0xAA, 0xEF, 0xA8, 0x4F, \ + 0x95, 0x54, 0xFF, 0x84, 0x28, 0xBD, 0x88, 0xE2, \ + 0x46, 0xD2, 0x78, 0x2A, 0xE2 +#define EC_PARAM_sect163r1_b \ + 0x07, 0x13, 0x61, 0x2D, 0xCD, 0xDC, 0xB4, 0x0A, \ + 0xAB, 0x94, 0x6B, 0xDA, 0x29, 0xCA, 0x91, 0xF7, \ + 0x3A, 0xF9, 0x58, 0xAF, 0xD9 +#define EC_PARAM_sect163r1_x \ + 0x03, 0x69, 0x97, 0x96, 0x97, 0xAB, 0x43, 0x89, \ + 0x77, 0x89, 0x56, 0x67, 0x89, 0x56, 0x7F, 0x78, \ + 0x7A, 0x78, 0x76, 0xA6, 0x54 +#define EC_PARAM_sect163r1_y \ + 0x00, 0x43, 0x5E, 0xDB, 0x42, 0xEF, 0xAF, 0xB2, \ + 0x98, 0x9D, 0x51, 0xFE, 0xFC, 0xE3, 0xC8, 0x09, \ + 0x88, 0xF4, 0x1F, 0xF8, 0x83 +#define EC_PARAM_sect163r1_order \ + 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0x48, 0xAA, 0xB6, 0x89, 0xC2, \ + 0x9C, 0xA7, 0x10, 0x27, 0x9B +#endif + +#if 0 +/* sect163r2 : NIST/SECG curve over a 163 bit binary field */ +#define EC_PARAM_sect163r2_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xC9 +#define EC_PARAM_sect163r2_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect163r2_b \ + 0x02, 0x0A, 0x60, 0x19, 0x07, 0xB8, 0xC9, 0x53, \ + 0xCA, 0x14, 0x81, 0xEB, 0x10, 0x51, 0x2F, 0x78, \ + 0x74, 0x4A, 0x32, 0x05, 0xFD +#define EC_PARAM_sect163r2_x \ + 0x03, 0xF0, 0xEB, 0xA1, 0x62, 0x86, 0xA2, 0xD5, \ + 0x7E, 0xA0, 0x99, 0x11, 0x68, 0xD4, 0x99, 0x46, \ + 0x37, 0xE8, 0x34, 0x3E, 0x36 +#define EC_PARAM_sect163r2_y \ + 0x00, 0xD5, 0x1F, 0xBC, 0x6C, 0x71, 0xA0, 0x09, \ + 0x4F, 0xA2, 0xCD, 0xD5, 0x45, 0xB1, 0x1C, 0x5C, \ + 0x0C, 0x79, 0x73, 0x24, 0xF1 +#define EC_PARAM_sect163r2_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x02, 0x92, 0xFE, 0x77, 0xE7, 0x0C, \ + 0x12, 0xA4, 0x23, 0x4C, 0x33 +#endif + +#if 0 +/* sect193r1 : SECG curve over a 193 bit binary field */ +#define EC_PARAM_sect193r1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, \ + 0x01 +#define EC_PARAM_sect193r1_a \ + 0x00, 0x17, 0x85, 0x8F, 0xEB, 0x7A, 0x98, 0x97, \ + 0x51, 0x69, 0xE1, 0x71, 0xF7, 0x7B, 0x40, 0x87, \ + 0xDE, 0x09, 0x8A, 0xC8, 0xA9, 0x11, 0xDF, 0x7B, \ + 0x01 +#define EC_PARAM_sect193r1_b \ + 0x00, 0xFD, 0xFB, 0x49, 0xBF, 0xE6, 0xC3, 0xA8, \ + 0x9F, 0xAC, 0xAD, 0xAA, 0x7A, 0x1E, 0x5B, 0xBC, \ + 0x7C, 0xC1, 0xC2, 0xE5, 0xD8, 0x31, 0x47, 0x88, \ + 0x14 +#define EC_PARAM_sect193r1_x \ + 0x01, 0xF4, 0x81, 0xBC, 0x5F, 0x0F, 0xF8, 0x4A, \ + 0x74, 0xAD, 0x6C, 0xDF, 0x6F, 0xDE, 0xF4, 0xBF, \ + 0x61, 0x79, 0x62, 0x53, 0x72, 0xD8, 0xC0, 0xC5, \ + 0xE1 +#define EC_PARAM_sect193r1_y \ + 0x00, 0x25, 0xE3, 0x99, 0xF2, 0x90, 0x37, 0x12, \ + 0xCC, 0xF3, 0xEA, 0x9E, 0x3A, 0x1A, 0xD1, 0x7F, \ + 0xB0, 0xB3, 0x20, 0x1B, 0x6A, 0xF7, 0xCE, 0x1B, \ + 0x05 +#define EC_PARAM_sect193r1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0xC7, 0xF3, 0x4A, \ + 0x77, 0x8F, 0x44, 0x3A, 0xCC, 0x92, 0x0E, 0xBA, \ + 0x49 +#endif + +#if 0 +/* sect193r2 : SECG curve over a 193 bit binary field */ +#define EC_PARAM_sect193r2_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, \ + 0x01 +#define EC_PARAM_sect193r2_a \ + 0x01, 0x63, 0xF3, 0x5A, 0x51, 0x37, 0xC2, 0xCE, \ + 0x3E, 0xA6, 0xED, 0x86, 0x67, 0x19, 0x0B, 0x0B, \ + 0xC4, 0x3E, 0xCD, 0x69, 0x97, 0x77, 0x02, 0x70, \ + 0x9B +#define EC_PARAM_sect193r2_b \ + 0x00, 0xC9, 0xBB, 0x9E, 0x89, 0x27, 0xD4, 0xD6, \ + 0x4C, 0x37, 0x7E, 0x2A, 0xB2, 0x85, 0x6A, 0x5B, \ + 0x16, 0xE3, 0xEF, 0xB7, 0xF6, 0x1D, 0x43, 0x16, \ + 0xAE +#define EC_PARAM_sect193r2_x \ + 0x00, 0xD9, 0xB6, 0x7D, 0x19, 0x2E, 0x03, 0x67, \ + 0xC8, 0x03, 0xF3, 0x9E, 0x1A, 0x7E, 0x82, 0xCA, \ + 0x14, 0xA6, 0x51, 0x35, 0x0A, 0xAE, 0x61, 0x7E, \ + 0x8F +#define EC_PARAM_sect193r2_y \ + 0x01, 0xCE, 0x94, 0x33, 0x56, 0x07, 0xC3, 0x04, \ + 0xAC, 0x29, 0xE7, 0xDE, 0xFB, 0xD9, 0xCA, 0x01, \ + 0xF5, 0x96, 0xF9, 0x27, 0x22, 0x4C, 0xDE, 0xCF, \ + 0x6C +#define EC_PARAM_sect193r2_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01, 0x5A, 0xAB, 0x56, \ + 0x1B, 0x00, 0x54, 0x13, 0xCC, 0xD4, 0xEE, 0x99, \ + 0xD5 +#endif + +#if 0 +/* sect233k1 : NIST/SECG/WTLS curve over a 233 bit binary field */ +#define EC_PARAM_sect233k1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect233k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_sect233k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect233k1_x \ + 0x01, 0x72, 0x32, 0xBA, 0x85, 0x3A, 0x7E, 0x73, \ + 0x1A, 0xF1, 0x29, 0xF2, 0x2F, 0xF4, 0x14, 0x95, \ + 0x63, 0xA4, 0x19, 0xC2, 0x6B, 0xF5, 0x0A, 0x4C, \ + 0x9D, 0x6E, 0xEF, 0xAD, 0x61, 0x26 +#define EC_PARAM_sect233k1_y \ + 0x01, 0xDB, 0x53, 0x7D, 0xEC, 0xE8, 0x19, 0xB7, \ + 0xF7, 0x0F, 0x55, 0x5A, 0x67, 0xC4, 0x27, 0xA8, \ + 0xCD, 0x9B, 0xF1, 0x8A, 0xEB, 0x9B, 0x56, 0xE0, \ + 0xC1, 0x10, 0x56, 0xFA, 0xE6, 0xA3 +#define EC_PARAM_sect233k1_order \ + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, \ + 0x9D, 0x5B, 0xB9, 0x15, 0xBC, 0xD4, 0x6E, 0xFB, \ + 0x1A, 0xD5, 0xF1, 0x73, 0xAB, 0xDF +#endif + +#if 0 +/* sect233r1 : NIST/SECG/WTLS curve over a 233 bit binary field */ +#define EC_PARAM_sect233r1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect233r1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect233r1_b \ + 0x00, 0x66, 0x64, 0x7E, 0xDE, 0x6C, 0x33, 0x2C, \ + 0x7F, 0x8C, 0x09, 0x23, 0xBB, 0x58, 0x21, 0x3B, \ + 0x33, 0x3B, 0x20, 0xE9, 0xCE, 0x42, 0x81, 0xFE, \ + 0x11, 0x5F, 0x7D, 0x8F, 0x90, 0xAD +#define EC_PARAM_sect233r1_x \ + 0x00, 0xFA, 0xC9, 0xDF, 0xCB, 0xAC, 0x83, 0x13, \ + 0xBB, 0x21, 0x39, 0xF1, 0xBB, 0x75, 0x5F, 0xEF, \ + 0x65, 0xBC, 0x39, 0x1F, 0x8B, 0x36, 0xF8, 0xF8, \ + 0xEB, 0x73, 0x71, 0xFD, 0x55, 0x8B +#define EC_PARAM_sect233r1_y \ + 0x01, 0x00, 0x6A, 0x08, 0xA4, 0x19, 0x03, 0x35, \ + 0x06, 0x78, 0xE5, 0x85, 0x28, 0xBE, 0xBF, 0x8A, \ + 0x0B, 0xEF, 0xF8, 0x67, 0xA7, 0xCA, 0x36, 0x71, \ + 0x6F, 0x7E, 0x01, 0xF8, 0x10, 0x52 +#define EC_PARAM_sect233r1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, \ + 0xE9, 0x74, 0xE7, 0x2F, 0x8A, 0x69, 0x22, 0x03, \ + 0x1D, 0x26, 0x03, 0xCF, 0xE0, 0xD7 +#endif + +#if 0 +/* sect239k1 : SECG curve over a 239 bit binary field */ +#define EC_PARAM_sect239k1_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect239k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_sect239k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect239k1_x \ + 0x29, 0xA0, 0xB6, 0xA8, 0x87, 0xA9, 0x83, 0xE9, \ + 0x73, 0x09, 0x88, 0xA6, 0x87, 0x27, 0xA8, 0xB2, \ + 0xD1, 0x26, 0xC4, 0x4C, 0xC2, 0xCC, 0x7B, 0x2A, \ + 0x65, 0x55, 0x19, 0x30, 0x35, 0xDC +#define EC_PARAM_sect239k1_y \ + 0x76, 0x31, 0x08, 0x04, 0xF1, 0x2E, 0x54, 0x9B, \ + 0xDB, 0x01, 0x1C, 0x10, 0x30, 0x89, 0xE7, 0x35, \ + 0x10, 0xAC, 0xB2, 0x75, 0xFC, 0x31, 0x2A, 0x5D, \ + 0xC6, 0xB7, 0x65, 0x53, 0xF0, 0xCA +#define EC_PARAM_sect239k1_order \ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5A, \ + 0x79, 0xFE, 0xC6, 0x7C, 0xB6, 0xE9, 0x1F, 0x1C, \ + 0x1D, 0xA8, 0x00, 0xE4, 0x78, 0xA5 +#endif + +#if 0 +/* sect283k1 : NIST/SECG curve over a 283 bit binary field */ +#define EC_PARAM_sect283k1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x10, 0xA1 +#define EC_PARAM_sect283k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_sect283k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect283k1_x \ + 0x05, 0x03, 0x21, 0x3F, 0x78, 0xCA, 0x44, 0x88, \ + 0x3F, 0x1A, 0x3B, 0x81, 0x62, 0xF1, 0x88, 0xE5, \ + 0x53, 0xCD, 0x26, 0x5F, 0x23, 0xC1, 0x56, 0x7A, \ + 0x16, 0x87, 0x69, 0x13, 0xB0, 0xC2, 0xAC, 0x24, \ + 0x58, 0x49, 0x28, 0x36 +#define EC_PARAM_sect283k1_y \ + 0x01, 0xCC, 0xDA, 0x38, 0x0F, 0x1C, 0x9E, 0x31, \ + 0x8D, 0x90, 0xF9, 0x5D, 0x07, 0xE5, 0x42, 0x6F, \ + 0xE8, 0x7E, 0x45, 0xC0, 0xE8, 0x18, 0x46, 0x98, \ + 0xE4, 0x59, 0x62, 0x36, 0x4E, 0x34, 0x11, 0x61, \ + 0x77, 0xDD, 0x22, 0x59 +#define EC_PARAM_sect283k1_order \ + 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xE9, 0xAE, 0x2E, 0xD0, 0x75, 0x77, \ + 0x26, 0x5D, 0xFF, 0x7F, 0x94, 0x45, 0x1E, 0x06, \ + 0x1E, 0x16, 0x3C, 0x61 +#endif + +#if 0 +/* sect283r1 : NIST/SECG curve over a 283 bit binary field */ +#define EC_PARAM_sect283r1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x10, 0xA1 +#define EC_PARAM_sect283r1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect283r1_b \ + 0x02, 0x7B, 0x68, 0x0A, 0xC8, 0xB8, 0x59, 0x6D, \ + 0xA5, 0xA4, 0xAF, 0x8A, 0x19, 0xA0, 0x30, 0x3F, \ + 0xCA, 0x97, 0xFD, 0x76, 0x45, 0x30, 0x9F, 0xA2, \ + 0xA5, 0x81, 0x48, 0x5A, 0xF6, 0x26, 0x3E, 0x31, \ + 0x3B, 0x79, 0xA2, 0xF5 +#define EC_PARAM_sect283r1_x \ + 0x05, 0xF9, 0x39, 0x25, 0x8D, 0xB7, 0xDD, 0x90, \ + 0xE1, 0x93, 0x4F, 0x8C, 0x70, 0xB0, 0xDF, 0xEC, \ + 0x2E, 0xED, 0x25, 0xB8, 0x55, 0x7E, 0xAC, 0x9C, \ + 0x80, 0xE2, 0xE1, 0x98, 0xF8, 0xCD, 0xBE, 0xCD, \ + 0x86, 0xB1, 0x20, 0x53 +#define EC_PARAM_sect283r1_y \ + 0x03, 0x67, 0x68, 0x54, 0xFE, 0x24, 0x14, 0x1C, \ + 0xB9, 0x8F, 0xE6, 0xD4, 0xB2, 0x0D, 0x02, 0xB4, \ + 0x51, 0x6F, 0xF7, 0x02, 0x35, 0x0E, 0xDD, 0xB0, \ + 0x82, 0x67, 0x79, 0xC8, 0x13, 0xF0, 0xDF, 0x45, \ + 0xBE, 0x81, 0x12, 0xF4 +#define EC_PARAM_sect283r1_order \ + 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xEF, 0x90, 0x39, 0x96, 0x60, 0xFC, \ + 0x93, 0x8A, 0x90, 0x16, 0x5B, 0x04, 0x2A, 0x7C, \ + 0xEF, 0xAD, 0xB3, 0x07 +#endif + +#if 0 +/* sect409k1 : NIST/SECG curve over a 409 bit binary field */ +#define EC_PARAM_sect409k1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect409k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_sect409k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect409k1_x \ + 0x00, 0x60, 0xF0, 0x5F, 0x65, 0x8F, 0x49, 0xC1, \ + 0xAD, 0x3A, 0xB1, 0x89, 0x0F, 0x71, 0x84, 0x21, \ + 0x0E, 0xFD, 0x09, 0x87, 0xE3, 0x07, 0xC8, 0x4C, \ + 0x27, 0xAC, 0xCF, 0xB8, 0xF9, 0xF6, 0x7C, 0xC2, \ + 0xC4, 0x60, 0x18, 0x9E, 0xB5, 0xAA, 0xAA, 0x62, \ + 0xEE, 0x22, 0x2E, 0xB1, 0xB3, 0x55, 0x40, 0xCF, \ + 0xE9, 0x02, 0x37, 0x46 +#define EC_PARAM_sect409k1_y \ + 0x01, 0xE3, 0x69, 0x05, 0x0B, 0x7C, 0x4E, 0x42, \ + 0xAC, 0xBA, 0x1D, 0xAC, 0xBF, 0x04, 0x29, 0x9C, \ + 0x34, 0x60, 0x78, 0x2F, 0x91, 0x8E, 0xA4, 0x27, \ + 0xE6, 0x32, 0x51, 0x65, 0xE9, 0xEA, 0x10, 0xE3, \ + 0xDA, 0x5F, 0x6C, 0x42, 0xE9, 0xC5, 0x52, 0x15, \ + 0xAA, 0x9C, 0xA2, 0x7A, 0x58, 0x63, 0xEC, 0x48, \ + 0xD8, 0xE0, 0x28, 0x6B +#define EC_PARAM_sect409k1_order \ + 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFE, 0x5F, 0x83, 0xB2, 0xD4, 0xEA, \ + 0x20, 0x40, 0x0E, 0xC4, 0x55, 0x7D, 0x5E, 0xD3, \ + 0xE3, 0xE7, 0xCA, 0x5B, 0x4B, 0x5C, 0x83, 0xB8, \ + 0xE0, 0x1E, 0x5F, 0xCF +#endif + +#if 0 +/* sect409r1 : NIST/SECG curve over a 409 bit binary field */ +#define EC_PARAM_sect409r1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect409r1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect409r1_b \ + 0x00, 0x21, 0xA5, 0xC2, 0xC8, 0xEE, 0x9F, 0xEB, \ + 0x5C, 0x4B, 0x9A, 0x75, 0x3B, 0x7B, 0x47, 0x6B, \ + 0x7F, 0xD6, 0x42, 0x2E, 0xF1, 0xF3, 0xDD, 0x67, \ + 0x47, 0x61, 0xFA, 0x99, 0xD6, 0xAC, 0x27, 0xC8, \ + 0xA9, 0xA1, 0x97, 0xB2, 0x72, 0x82, 0x2F, 0x6C, \ + 0xD5, 0x7A, 0x55, 0xAA, 0x4F, 0x50, 0xAE, 0x31, \ + 0x7B, 0x13, 0x54, 0x5F +#define EC_PARAM_sect409r1_x \ + 0x01, 0x5D, 0x48, 0x60, 0xD0, 0x88, 0xDD, 0xB3, \ + 0x49, 0x6B, 0x0C, 0x60, 0x64, 0x75, 0x62, 0x60, \ + 0x44, 0x1C, 0xDE, 0x4A, 0xF1, 0x77, 0x1D, 0x4D, \ + 0xB0, 0x1F, 0xFE, 0x5B, 0x34, 0xE5, 0x97, 0x03, \ + 0xDC, 0x25, 0x5A, 0x86, 0x8A, 0x11, 0x80, 0x51, \ + 0x56, 0x03, 0xAE, 0xAB, 0x60, 0x79, 0x4E, 0x54, \ + 0xBB, 0x79, 0x96, 0xA7 +#define EC_PARAM_sect409r1_y \ + 0x00, 0x61, 0xB1, 0xCF, 0xAB, 0x6B, 0xE5, 0xF3, \ + 0x2B, 0xBF, 0xA7, 0x83, 0x24, 0xED, 0x10, 0x6A, \ + 0x76, 0x36, 0xB9, 0xC5, 0xA7, 0xBD, 0x19, 0x8D, \ + 0x01, 0x58, 0xAA, 0x4F, 0x54, 0x88, 0xD0, 0x8F, \ + 0x38, 0x51, 0x4F, 0x1F, 0xDF, 0x4B, 0x4F, 0x40, \ + 0xD2, 0x18, 0x1B, 0x36, 0x81, 0xC3, 0x64, 0xBA, \ + 0x02, 0x73, 0xC7, 0x06 +#define EC_PARAM_sect409r1_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xE2, 0xAA, 0xD6, 0xA6, 0x12, \ + 0xF3, 0x33, 0x07, 0xBE, 0x5F, 0xA4, 0x7C, 0x3C, \ + 0x9E, 0x05, 0x2F, 0x83, 0x81, 0x64, 0xCD, 0x37, \ + 0xD9, 0xA2, 0x11, 0x73 +#endif + +#if 0 +/* sect571k1 : NIST/SECG curve over a 571 bit binary field */ +#define EC_PARAM_sect571k1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25 +#define EC_PARAM_sect571k1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_sect571k1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect571k1_x \ + 0x02, 0x6E, 0xB7, 0xA8, 0x59, 0x92, 0x3F, 0xBC, \ + 0x82, 0x18, 0x96, 0x31, 0xF8, 0x10, 0x3F, 0xE4, \ + 0xAC, 0x9C, 0xA2, 0x97, 0x00, 0x12, 0xD5, 0xD4, \ + 0x60, 0x24, 0x80, 0x48, 0x01, 0x84, 0x1C, 0xA4, \ + 0x43, 0x70, 0x95, 0x84, 0x93, 0xB2, 0x05, 0xE6, \ + 0x47, 0xDA, 0x30, 0x4D, 0xB4, 0xCE, 0xB0, 0x8C, \ + 0xBB, 0xD1, 0xBA, 0x39, 0x49, 0x47, 0x76, 0xFB, \ + 0x98, 0x8B, 0x47, 0x17, 0x4D, 0xCA, 0x88, 0xC7, \ + 0xE2, 0x94, 0x52, 0x83, 0xA0, 0x1C, 0x89, 0x72 +#define EC_PARAM_sect571k1_y \ + 0x03, 0x49, 0xDC, 0x80, 0x7F, 0x4F, 0xBF, 0x37, \ + 0x4F, 0x4A, 0xEA, 0xDE, 0x3B, 0xCA, 0x95, 0x31, \ + 0x4D, 0xD5, 0x8C, 0xEC, 0x9F, 0x30, 0x7A, 0x54, \ + 0xFF, 0xC6, 0x1E, 0xFC, 0x00, 0x6D, 0x8A, 0x2C, \ + 0x9D, 0x49, 0x79, 0xC0, 0xAC, 0x44, 0xAE, 0xA7, \ + 0x4F, 0xBE, 0xBB, 0xB9, 0xF7, 0x72, 0xAE, 0xDC, \ + 0xB6, 0x20, 0xB0, 0x1A, 0x7B, 0xA7, 0xAF, 0x1B, \ + 0x32, 0x04, 0x30, 0xC8, 0x59, 0x19, 0x84, 0xF6, \ + 0x01, 0xCD, 0x4C, 0x14, 0x3E, 0xF1, 0xC7, 0xA3 +#define EC_PARAM_sect571k1_order \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x13, 0x18, 0x50, 0xE1, \ + 0xF1, 0x9A, 0x63, 0xE4, 0xB3, 0x91, 0xA8, 0xDB, \ + 0x91, 0x7F, 0x41, 0x38, 0xB6, 0x30, 0xD8, 0x4B, \ + 0xE5, 0xD6, 0x39, 0x38, 0x1E, 0x91, 0xDE, 0xB4, \ + 0x5C, 0xFE, 0x77, 0x8F, 0x63, 0x7C, 0x10, 0x01 +#endif + +#if 0 +/* sect571r1 : NIST/SECG curve over a 571 bit binary field */ +#define EC_PARAM_sect571r1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25 +#define EC_PARAM_sect571r1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_sect571r1_b \ + 0x02, 0xF4, 0x0E, 0x7E, 0x22, 0x21, 0xF2, 0x95, \ + 0xDE, 0x29, 0x71, 0x17, 0xB7, 0xF3, 0xD6, 0x2F, \ + 0x5C, 0x6A, 0x97, 0xFF, 0xCB, 0x8C, 0xEF, 0xF1, \ + 0xCD, 0x6B, 0xA8, 0xCE, 0x4A, 0x9A, 0x18, 0xAD, \ + 0x84, 0xFF, 0xAB, 0xBD, 0x8E, 0xFA, 0x59, 0x33, \ + 0x2B, 0xE7, 0xAD, 0x67, 0x56, 0xA6, 0x6E, 0x29, \ + 0x4A, 0xFD, 0x18, 0x5A, 0x78, 0xFF, 0x12, 0xAA, \ + 0x52, 0x0E, 0x4D, 0xE7, 0x39, 0xBA, 0xCA, 0x0C, \ + 0x7F, 0xFE, 0xFF, 0x7F, 0x29, 0x55, 0x72, 0x7A +#define EC_PARAM_sect571r1_x \ + 0x03, 0x03, 0x00, 0x1D, 0x34, 0xB8, 0x56, 0x29, \ + 0x6C, 0x16, 0xC0, 0xD4, 0x0D, 0x3C, 0xD7, 0x75, \ + 0x0A, 0x93, 0xD1, 0xD2, 0x95, 0x5F, 0xA8, 0x0A, \ + 0xA5, 0xF4, 0x0F, 0xC8, 0xDB, 0x7B, 0x2A, 0xBD, \ + 0xBD, 0xE5, 0x39, 0x50, 0xF4, 0xC0, 0xD2, 0x93, \ + 0xCD, 0xD7, 0x11, 0xA3, 0x5B, 0x67, 0xFB, 0x14, \ + 0x99, 0xAE, 0x60, 0x03, 0x86, 0x14, 0xF1, 0x39, \ + 0x4A, 0xBF, 0xA3, 0xB4, 0xC8, 0x50, 0xD9, 0x27, \ + 0xE1, 0xE7, 0x76, 0x9C, 0x8E, 0xEC, 0x2D, 0x19 +#define EC_PARAM_sect571r1_y \ + 0x03, 0x7B, 0xF2, 0x73, 0x42, 0xDA, 0x63, 0x9B, \ + 0x6D, 0xCC, 0xFF, 0xFE, 0xB7, 0x3D, 0x69, 0xD7, \ + 0x8C, 0x6C, 0x27, 0xA6, 0x00, 0x9C, 0xBB, 0xCA, \ + 0x19, 0x80, 0xF8, 0x53, 0x39, 0x21, 0xE8, 0xA6, \ + 0x84, 0x42, 0x3E, 0x43, 0xBA, 0xB0, 0x8A, 0x57, \ + 0x62, 0x91, 0xAF, 0x8F, 0x46, 0x1B, 0xB2, 0xA8, \ + 0xB3, 0x53, 0x1D, 0x2F, 0x04, 0x85, 0xC1, 0x9B, \ + 0x16, 0xE2, 0xF1, 0x51, 0x6E, 0x23, 0xDD, 0x3C, \ + 0x1A, 0x48, 0x27, 0xAF, 0x1B, 0x8A, 0xC1, 0x5B +#define EC_PARAM_sect571r1_order \ + 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xE6, 0x61, 0xCE, 0x18, \ + 0xFF, 0x55, 0x98, 0x73, 0x08, 0x05, 0x9B, 0x18, \ + 0x68, 0x23, 0x85, 0x1E, 0xC7, 0xDD, 0x9C, 0xA1, \ + 0x16, 0x1D, 0xE9, 0x3D, 0x51, 0x74, 0xD6, 0x6E, \ + 0x83, 0x82, 0xE9, 0xBB, 0x2F, 0xE8, 0x4E, 0x47 +#endif + +#if 0 +/* c2pnb163v1 : X9.62 curve over a 163 bit binary field */ +#define EC_PARAM_c2pnb163v1_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01, 0x07 +#define EC_PARAM_c2pnb163v1_a \ + 0x07, 0x25, 0x46, 0xB5, 0x43, 0x52, 0x34, 0xA4, \ + 0x22, 0xE0, 0x78, 0x96, 0x75, 0xF4, 0x32, 0xC8, \ + 0x94, 0x35, 0xDE, 0x52, 0x42 +#define EC_PARAM_c2pnb163v1_b \ + 0x00, 0xC9, 0x51, 0x7D, 0x06, 0xD5, 0x24, 0x0D, \ + 0x3C, 0xFF, 0x38, 0xC7, 0x4B, 0x20, 0xB6, 0xCD, \ + 0x4D, 0x6F, 0x9D, 0xD4, 0xD9 +#define EC_PARAM_c2pnb163v1_x \ + 0x07, 0xAF, 0x69, 0x98, 0x95, 0x46, 0x10, 0x3D, \ + 0x79, 0x32, 0x9F, 0xCC, 0x3D, 0x74, 0x88, 0x0F, \ + 0x33, 0xBB, 0xE8, 0x03, 0xCB +#define EC_PARAM_c2pnb163v1_y \ + 0x01, 0xEC, 0x23, 0x21, 0x1B, 0x59, 0x66, 0xAD, \ + 0xEA, 0x1D, 0x3F, 0x87, 0xF7, 0xEA, 0x58, 0x48, \ + 0xAE, 0xF0, 0xB7, 0xCA, 0x9F +#define EC_PARAM_c2pnb163v1_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xE6, 0x0F, 0xC8, 0x82, 0x1C, \ + 0xC7, 0x4D, 0xAE, 0xAF, 0xC1 +#endif + +#if 0 +/* c2pnb163v2 : X9.62 curve over a 163 bit binary field */ +#define EC_PARAM_c2pnb163v2_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01, 0x07 +#define EC_PARAM_c2pnb163v2_a \ + 0x01, 0x08, 0xB3, 0x9E, 0x77, 0xC4, 0xB1, 0x08, \ + 0xBE, 0xD9, 0x81, 0xED, 0x0E, 0x89, 0x0E, 0x11, \ + 0x7C, 0x51, 0x1C, 0xF0, 0x72 +#define EC_PARAM_c2pnb163v2_b \ + 0x06, 0x67, 0xAC, 0xEB, 0x38, 0xAF, 0x4E, 0x48, \ + 0x8C, 0x40, 0x74, 0x33, 0xFF, 0xAE, 0x4F, 0x1C, \ + 0x81, 0x16, 0x38, 0xDF, 0x20 +#define EC_PARAM_c2pnb163v2_x \ + 0x00, 0x24, 0x26, 0x6E, 0x4E, 0xB5, 0x10, 0x6D, \ + 0x0A, 0x96, 0x4D, 0x92, 0xC4, 0x86, 0x0E, 0x26, \ + 0x71, 0xDB, 0x9B, 0x6C, 0xC5 +#define EC_PARAM_c2pnb163v2_y \ + 0x07, 0x9F, 0x68, 0x4D, 0xDF, 0x66, 0x84, 0xC5, \ + 0xCD, 0x25, 0x8B, 0x38, 0x90, 0x02, 0x1B, 0x23, \ + 0x86, 0xDF, 0xD1, 0x9F, 0xC5 +#define EC_PARAM_c2pnb163v2_order \ + 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFD, 0xF6, 0x4D, 0xE1, 0x15, 0x1A, \ + 0xDB, 0xB7, 0x8F, 0x10, 0xA7 +#endif + +#if 0 +/* c2pnb163v3 : X9.62 curve over a 163 bit binary field */ +#define EC_PARAM_c2pnb163v3_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01, 0x07 +#define EC_PARAM_c2pnb163v3_a \ + 0x07, 0xA5, 0x26, 0xC6, 0x3D, 0x3E, 0x25, 0xA2, \ + 0x56, 0xA0, 0x07, 0x69, 0x9F, 0x54, 0x47, 0xE3, \ + 0x2A, 0xE4, 0x56, 0xB5, 0x0E +#define EC_PARAM_c2pnb163v3_b \ + 0x03, 0xF7, 0x06, 0x17, 0x98, 0xEB, 0x99, 0xE2, \ + 0x38, 0xFD, 0x6F, 0x1B, 0xF9, 0x5B, 0x48, 0xFE, \ + 0xEB, 0x48, 0x54, 0x25, 0x2B +#define EC_PARAM_c2pnb163v3_x \ + 0x02, 0xF9, 0xF8, 0x7B, 0x7C, 0x57, 0x4D, 0x0B, \ + 0xDE, 0xCF, 0x8A, 0x22, 0xE6, 0x52, 0x47, 0x75, \ + 0xF9, 0x8C, 0xDE, 0xBD, 0xCB +#define EC_PARAM_c2pnb163v3_y \ + 0x05, 0xB9, 0x35, 0x59, 0x0C, 0x15, 0x5E, 0x17, \ + 0xEA, 0x48, 0xEB, 0x3F, 0xF3, 0x71, 0x8B, 0x89, \ + 0x3D, 0xF5, 0x9A, 0x05, 0xD0 +#define EC_PARAM_c2pnb163v3_order \ + 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFE, 0x1A, 0xEE, 0x14, 0x0F, 0x11, \ + 0x0A, 0xFF, 0x96, 0x13, 0x09 +#endif + +#if 0 +/* c2pnb176v1 : X9.62 curve over a 176 bit binary field */ +#define EC_PARAM_c2pnb176v1_prime \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x07 +#define EC_PARAM_c2pnb176v1_a \ + 0x00, 0xE4, 0xE6, 0xDB, 0x29, 0x95, 0x06, 0x5C, \ + 0x40, 0x7D, 0x9D, 0x39, 0xB8, 0xD0, 0x96, 0x7B, \ + 0x96, 0x70, 0x4B, 0xA8, 0xE9, 0xC9, 0x0B +#define EC_PARAM_c2pnb176v1_b \ + 0x00, 0x5D, 0xDA, 0x47, 0x0A, 0xBE, 0x64, 0x14, \ + 0xDE, 0x8E, 0xC1, 0x33, 0xAE, 0x28, 0xE9, 0xBB, \ + 0xD7, 0xFC, 0xEC, 0x0A, 0xE0, 0xFF, 0xF2 +#define EC_PARAM_c2pnb176v1_x \ + 0x00, 0x8D, 0x16, 0xC2, 0x86, 0x67, 0x98, 0xB6, \ + 0x00, 0xF9, 0xF0, 0x8B, 0xB4, 0xA8, 0xE8, 0x60, \ + 0xF3, 0x29, 0x8C, 0xE0, 0x4A, 0x57, 0x98 +#define EC_PARAM_c2pnb176v1_y \ + 0x00, 0x6F, 0xA4, 0x53, 0x9C, 0x2D, 0xAD, 0xDD, \ + 0xD6, 0xBA, 0xB5, 0x16, 0x7D, 0x61, 0xB4, 0x36, \ + 0xE1, 0xD9, 0x2B, 0xB1, 0x6A, 0x56, 0x2C +#define EC_PARAM_c2pnb176v1_order \ + 0x00, 0x00, 0x01, 0x00, 0x92, 0x53, 0x73, 0x97, \ + 0xEC, 0xA4, 0xF6, 0x14, 0x57, 0x99, 0xD6, 0x2B, \ + 0x0A, 0x19, 0xCE, 0x06, 0xFE, 0x26, 0xAD +#endif + +#if 0 +/* c2tnb191v1 : X9.62 curve over a 191 bit binary field */ +#define EC_PARAM_c2tnb191v1_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_c2tnb191v1_a \ + 0x28, 0x66, 0x53, 0x7B, 0x67, 0x67, 0x52, 0x63, \ + 0x6A, 0x68, 0xF5, 0x65, 0x54, 0xE1, 0x26, 0x40, \ + 0x27, 0x6B, 0x64, 0x9E, 0xF7, 0x52, 0x62, 0x67 +#define EC_PARAM_c2tnb191v1_b \ + 0x2E, 0x45, 0xEF, 0x57, 0x1F, 0x00, 0x78, 0x6F, \ + 0x67, 0xB0, 0x08, 0x1B, 0x94, 0x95, 0xA3, 0xD9, \ + 0x54, 0x62, 0xF5, 0xDE, 0x0A, 0xA1, 0x85, 0xEC +#define EC_PARAM_c2tnb191v1_x \ + 0x36, 0xB3, 0xDA, 0xF8, 0xA2, 0x32, 0x06, 0xF9, \ + 0xC4, 0xF2, 0x99, 0xD7, 0xB2, 0x1A, 0x9C, 0x36, \ + 0x91, 0x37, 0xF2, 0xC8, 0x4A, 0xE1, 0xAA, 0x0D +#define EC_PARAM_c2tnb191v1_y \ + 0x76, 0x5B, 0xE7, 0x34, 0x33, 0xB3, 0xF9, 0x5E, \ + 0x33, 0x29, 0x32, 0xE7, 0x0E, 0xA2, 0x45, 0xCA, \ + 0x24, 0x18, 0xEA, 0x0E, 0xF9, 0x80, 0x18, 0xFB +#define EC_PARAM_c2tnb191v1_order \ + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x04, 0xA2, 0x0E, 0x90, \ + 0xC3, 0x90, 0x67, 0xC8, 0x93, 0xBB, 0xB9, 0xA5 +#endif + +#if 0 +/* c2tnb191v2 : X9.62 curve over a 191 bit binary field */ +#define EC_PARAM_c2tnb191v2_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_c2tnb191v2_a \ + 0x40, 0x10, 0x28, 0x77, 0x4D, 0x77, 0x77, 0xC7, \ + 0xB7, 0x66, 0x6D, 0x13, 0x66, 0xEA, 0x43, 0x20, \ + 0x71, 0x27, 0x4F, 0x89, 0xFF, 0x01, 0xE7, 0x18 +#define EC_PARAM_c2tnb191v2_b \ + 0x06, 0x20, 0x04, 0x8D, 0x28, 0xBC, 0xBD, 0x03, \ + 0xB6, 0x24, 0x9C, 0x99, 0x18, 0x2B, 0x7C, 0x8C, \ + 0xD1, 0x97, 0x00, 0xC3, 0x62, 0xC4, 0x6A, 0x01 +#define EC_PARAM_c2tnb191v2_x \ + 0x38, 0x09, 0xB2, 0xB7, 0xCC, 0x1B, 0x28, 0xCC, \ + 0x5A, 0x87, 0x92, 0x6A, 0xAD, 0x83, 0xFD, 0x28, \ + 0x78, 0x9E, 0x81, 0xE2, 0xC9, 0xE3, 0xBF, 0x10 +#define EC_PARAM_c2tnb191v2_y \ + 0x17, 0x43, 0x43, 0x86, 0x62, 0x6D, 0x14, 0xF3, \ + 0xDB, 0xF0, 0x17, 0x60, 0xD9, 0x21, 0x3A, 0x3E, \ + 0x1C, 0xF3, 0x7A, 0xEC, 0x43, 0x7D, 0x66, 0x8A +#define EC_PARAM_c2tnb191v2_order \ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x50, 0x50, 0x8C, 0xB8, \ + 0x9F, 0x65, 0x28, 0x24, 0xE0, 0x6B, 0x81, 0x73 +#endif + +#if 0 +/* c2tnb191v3 : X9.62 curve over a 191 bit binary field */ +#define EC_PARAM_c2tnb191v3_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_c2tnb191v3_a \ + 0x6C, 0x01, 0x07, 0x47, 0x56, 0x09, 0x91, 0x22, \ + 0x22, 0x10, 0x56, 0x91, 0x1C, 0x77, 0xD7, 0x7E, \ + 0x77, 0xA7, 0x77, 0xE7, 0xE7, 0xE7, 0x7F, 0xCB +#define EC_PARAM_c2tnb191v3_b \ + 0x71, 0xFE, 0x1A, 0xF9, 0x26, 0xCF, 0x84, 0x79, \ + 0x89, 0xEF, 0xEF, 0x8D, 0xB4, 0x59, 0xF6, 0x63, \ + 0x94, 0xD9, 0x0F, 0x32, 0xAD, 0x3F, 0x15, 0xE8 +#define EC_PARAM_c2tnb191v3_x \ + 0x37, 0x5D, 0x4C, 0xE2, 0x4F, 0xDE, 0x43, 0x44, \ + 0x89, 0xDE, 0x87, 0x46, 0xE7, 0x17, 0x86, 0x01, \ + 0x50, 0x09, 0xE6, 0x6E, 0x38, 0xA9, 0x26, 0xDD +#define EC_PARAM_c2tnb191v3_y \ + 0x54, 0x5A, 0x39, 0x17, 0x61, 0x96, 0x57, 0x5D, \ + 0x98, 0x59, 0x99, 0x36, 0x6E, 0x6A, 0xD3, 0x4C, \ + 0xE0, 0xA7, 0x7C, 0xD7, 0x12, 0x7B, 0x06, 0xBE +#define EC_PARAM_c2tnb191v3_order \ + 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, \ + 0x55, 0x55, 0x55, 0x55, 0x61, 0x0C, 0x0B, 0x19, \ + 0x68, 0x12, 0xBF, 0xB6, 0x28, 0x8A, 0x3E, 0xA3 +#endif + +#if 0 +/* c2pnb208w1 : X9.62 curve over a 208 bit binary field */ +#define EC_PARAM_c2pnb208w1_prime \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x07 +#define EC_PARAM_c2pnb208w1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00 +#define EC_PARAM_c2pnb208w1_b \ + 0x00, 0xC8, 0x61, 0x9E, 0xD4, 0x5A, 0x62, 0xE6, \ + 0x21, 0x2E, 0x11, 0x60, 0x34, 0x9E, 0x2B, 0xFA, \ + 0x84, 0x44, 0x39, 0xFA, 0xFC, 0x2A, 0x3F, 0xD1, \ + 0x63, 0x8F, 0x9E +#define EC_PARAM_c2pnb208w1_x \ + 0x00, 0x89, 0xFD, 0xFB, 0xE4, 0xAB, 0xE1, 0x93, \ + 0xDF, 0x95, 0x59, 0xEC, 0xF0, 0x7A, 0xC0, 0xCE, \ + 0x78, 0x55, 0x4E, 0x27, 0x84, 0xEB, 0x8C, 0x1E, \ + 0xD1, 0xA5, 0x7A +#define EC_PARAM_c2pnb208w1_y \ + 0x00, 0x0F, 0x55, 0xB5, 0x1A, 0x06, 0xE7, 0x8E, \ + 0x9A, 0xC3, 0x8A, 0x03, 0x5F, 0xF5, 0x20, 0xD8, \ + 0xB0, 0x17, 0x81, 0xBE, 0xB1, 0xA6, 0xBB, 0x08, \ + 0x61, 0x7D, 0xE3 +#define EC_PARAM_c2pnb208w1_order \ + 0x00, 0x00, 0x01, 0x01, 0xBA, 0xF9, 0x5C, 0x97, \ + 0x23, 0xC5, 0x7B, 0x6C, 0x21, 0xDA, 0x2E, 0xFF, \ + 0x2D, 0x5E, 0xD5, 0x88, 0xBD, 0xD5, 0x71, 0x7E, \ + 0x21, 0x2F, 0x9D +#endif + +#if 0 +/* c2tnb239v1 : X9.62 curve over a 239 bit binary field */ +#define EC_PARAM_c2tnb239v1_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_c2tnb239v1_a \ + 0x32, 0x01, 0x08, 0x57, 0x07, 0x7C, 0x54, 0x31, \ + 0x12, 0x3A, 0x46, 0xB8, 0x08, 0x90, 0x67, 0x56, \ + 0xF5, 0x43, 0x42, 0x3E, 0x8D, 0x27, 0x87, 0x75, \ + 0x78, 0x12, 0x57, 0x78, 0xAC, 0x76 +#define EC_PARAM_c2tnb239v1_b \ + 0x79, 0x04, 0x08, 0xF2, 0xEE, 0xDA, 0xF3, 0x92, \ + 0xB0, 0x12, 0xED, 0xEF, 0xB3, 0x39, 0x2F, 0x30, \ + 0xF4, 0x32, 0x7C, 0x0C, 0xA3, 0xF3, 0x1F, 0xC3, \ + 0x83, 0xC4, 0x22, 0xAA, 0x8C, 0x16 +#define EC_PARAM_c2tnb239v1_x \ + 0x57, 0x92, 0x70, 0x98, 0xFA, 0x93, 0x2E, 0x7C, \ + 0x0A, 0x96, 0xD3, 0xFD, 0x5B, 0x70, 0x6E, 0xF7, \ + 0xE5, 0xF5, 0xC1, 0x56, 0xE1, 0x6B, 0x7E, 0x7C, \ + 0x86, 0x03, 0x85, 0x52, 0xE9, 0x1D +#define EC_PARAM_c2tnb239v1_y \ + 0x61, 0xD8, 0xEE, 0x50, 0x77, 0xC3, 0x3F, 0xEC, \ + 0xF6, 0xF1, 0xA1, 0x6B, 0x26, 0x8D, 0xE4, 0x69, \ + 0xC3, 0xC7, 0x74, 0x4E, 0xA9, 0xA9, 0x71, 0x64, \ + 0x9F, 0xC7, 0xA9, 0x61, 0x63, 0x05 +#define EC_PARAM_c2tnb239v1_order \ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, \ + 0x4D, 0x42, 0xFF, 0xE1, 0x49, 0x2A, 0x49, 0x93, \ + 0xF1, 0xCA, 0xD6, 0x66, 0xE4, 0x47 +#endif + +#if 0 +/* c2tnb239v2 : X9.62 curve over a 239 bit binary field */ +#define EC_PARAM_c2tnb239v2_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_c2tnb239v2_a \ + 0x42, 0x30, 0x01, 0x77, 0x57, 0xA7, 0x67, 0xFA, \ + 0xE4, 0x23, 0x98, 0x56, 0x9B, 0x74, 0x63, 0x25, \ + 0xD4, 0x53, 0x13, 0xAF, 0x07, 0x66, 0x26, 0x64, \ + 0x79, 0xB7, 0x56, 0x54, 0xE6, 0x5F +#define EC_PARAM_c2tnb239v2_b \ + 0x50, 0x37, 0xEA, 0x65, 0x41, 0x96, 0xCF, 0xF0, \ + 0xCD, 0x82, 0xB2, 0xC1, 0x4A, 0x2F, 0xCF, 0x2E, \ + 0x3F, 0xF8, 0x77, 0x52, 0x85, 0xB5, 0x45, 0x72, \ + 0x2F, 0x03, 0xEA, 0xCD, 0xB7, 0x4B +#define EC_PARAM_c2tnb239v2_x \ + 0x28, 0xF9, 0xD0, 0x4E, 0x90, 0x00, 0x69, 0xC8, \ + 0xDC, 0x47, 0xA0, 0x85, 0x34, 0xFE, 0x76, 0xD2, \ + 0xB9, 0x00, 0xB7, 0xD7, 0xEF, 0x31, 0xF5, 0x70, \ + 0x9F, 0x20, 0x0C, 0x4C, 0xA2, 0x05 +#define EC_PARAM_c2tnb239v2_y \ + 0x56, 0x67, 0x33, 0x4C, 0x45, 0xAF, 0xF3, 0xB5, \ + 0xA0, 0x3B, 0xAD, 0x9D, 0xD7, 0x5E, 0x2C, 0x71, \ + 0xA9, 0x93, 0x62, 0x56, 0x7D, 0x54, 0x53, 0xF7, \ + 0xFA, 0x6E, 0x22, 0x7E, 0xC8, 0x33 +#define EC_PARAM_c2tnb239v2_order \ + 0x15, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, \ + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x3C, \ + 0x6F, 0x28, 0x85, 0x25, 0x9C, 0x31, 0xE3, 0xFC, \ + 0xDF, 0x15, 0x46, 0x24, 0x52, 0x2D +#endif + +#if 0 +/* c2tnb239v3 : X9.62 curve over a 239 bit binary field */ +#define EC_PARAM_c2tnb239v3_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_c2tnb239v3_a \ + 0x01, 0x23, 0x87, 0x74, 0x66, 0x6A, 0x67, 0x76, \ + 0x6D, 0x66, 0x76, 0xF7, 0x78, 0xE6, 0x76, 0xB6, \ + 0x69, 0x99, 0x17, 0x66, 0x66, 0xE6, 0x87, 0x66, \ + 0x6D, 0x87, 0x66, 0xC6, 0x6A, 0x9F +#define EC_PARAM_c2tnb239v3_b \ + 0x6A, 0x94, 0x19, 0x77, 0xBA, 0x9F, 0x6A, 0x43, \ + 0x51, 0x99, 0xAC, 0xFC, 0x51, 0x06, 0x7E, 0xD5, \ + 0x87, 0xF5, 0x19, 0xC5, 0xEC, 0xB5, 0x41, 0xB8, \ + 0xE4, 0x41, 0x11, 0xDE, 0x1D, 0x40 +#define EC_PARAM_c2tnb239v3_x \ + 0x70, 0xF6, 0xE9, 0xD0, 0x4D, 0x28, 0x9C, 0x4E, \ + 0x89, 0x91, 0x3C, 0xE3, 0x53, 0x0B, 0xFD, 0xE9, \ + 0x03, 0x97, 0x7D, 0x42, 0xB1, 0x46, 0xD5, 0x39, \ + 0xBF, 0x1B, 0xDE, 0x4E, 0x9C, 0x92 +#define EC_PARAM_c2tnb239v3_y \ + 0x2E, 0x5A, 0x0E, 0xAF, 0x6E, 0x5E, 0x13, 0x05, \ + 0xB9, 0x00, 0x4D, 0xCE, 0x5C, 0x0E, 0xD7, 0xFE, \ + 0x59, 0xA3, 0x56, 0x08, 0xF3, 0x38, 0x37, 0xC8, \ + 0x16, 0xD8, 0x0B, 0x79, 0xF4, 0x61 +#define EC_PARAM_c2tnb239v3_order \ + 0x0C, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, \ + 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xAC, \ + 0x49, 0x12, 0xD2, 0xD9, 0xDF, 0x90, 0x3E, 0xF9, \ + 0x88, 0x8B, 0x8A, 0x0E, 0x4C, 0xFF +#endif + +#if 0 +/* c2pnb272w1 : X9.62 curve over a 272 bit binary field */ +#define EC_PARAM_c2pnb272w1_prime \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x0B +#define EC_PARAM_c2pnb272w1_a \ + 0x00, 0x91, 0xA0, 0x91, 0xF0, 0x3B, 0x5F, 0xBA, \ + 0x4A, 0xB2, 0xCC, 0xF4, 0x9C, 0x4E, 0xDD, 0x22, \ + 0x0F, 0xB0, 0x28, 0x71, 0x2D, 0x42, 0xBE, 0x75, \ + 0x2B, 0x2C, 0x40, 0x09, 0x4D, 0xBA, 0xCD, 0xB5, \ + 0x86, 0xFB, 0x20 +#define EC_PARAM_c2pnb272w1_b \ + 0x00, 0x71, 0x67, 0xEF, 0xC9, 0x2B, 0xB2, 0xE3, \ + 0xCE, 0x7C, 0x8A, 0xAA, 0xFF, 0x34, 0xE1, 0x2A, \ + 0x9C, 0x55, 0x70, 0x03, 0xD7, 0xC7, 0x3A, 0x6F, \ + 0xAF, 0x00, 0x3F, 0x99, 0xF6, 0xCC, 0x84, 0x82, \ + 0xE5, 0x40, 0xF7 +#define EC_PARAM_c2pnb272w1_x \ + 0x00, 0x61, 0x08, 0xBA, 0xBB, 0x2C, 0xEE, 0xBC, \ + 0xF7, 0x87, 0x05, 0x8A, 0x05, 0x6C, 0xBE, 0x0C, \ + 0xFE, 0x62, 0x2D, 0x77, 0x23, 0xA2, 0x89, 0xE0, \ + 0x8A, 0x07, 0xAE, 0x13, 0xEF, 0x0D, 0x10, 0xD1, \ + 0x71, 0xDD, 0x8D +#define EC_PARAM_c2pnb272w1_y \ + 0x00, 0x10, 0xC7, 0x69, 0x57, 0x16, 0x85, 0x1E, \ + 0xEF, 0x6B, 0xA7, 0xF6, 0x87, 0x2E, 0x61, 0x42, \ + 0xFB, 0xD2, 0x41, 0xB8, 0x30, 0xFF, 0x5E, 0xFC, \ + 0xAC, 0xEC, 0xCA, 0xB0, 0x5E, 0x02, 0x00, 0x5D, \ + 0xDE, 0x9D, 0x23 +#define EC_PARAM_c2pnb272w1_order \ + 0x00, 0x00, 0x01, 0x00, 0xFA, 0xF5, 0x13, 0x54, \ + 0xE0, 0xE3, 0x9E, 0x48, 0x92, 0xDF, 0x6E, 0x31, \ + 0x9C, 0x72, 0xC8, 0x16, 0x16, 0x03, 0xFA, 0x45, \ + 0xAA, 0x7B, 0x99, 0x8A, 0x16, 0x7B, 0x8F, 0x1E, \ + 0x62, 0x95, 0x21 +#endif + +#if 0 +/* c2pnb304w1 : X9.62 curve over a 304 bit binary field */ +#define EC_PARAM_c2pnb304w1_prime \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x07 +#define EC_PARAM_c2pnb304w1_a \ + 0x00, 0xFD, 0x0D, 0x69, 0x31, 0x49, 0xA1, 0x18, \ + 0xF6, 0x51, 0xE6, 0xDC, 0xE6, 0x80, 0x20, 0x85, \ + 0x37, 0x7E, 0x5F, 0x88, 0x2D, 0x1B, 0x51, 0x0B, \ + 0x44, 0x16, 0x00, 0x74, 0xC1, 0x28, 0x80, 0x78, \ + 0x36, 0x5A, 0x03, 0x96, 0xC8, 0xE6, 0x81 +#define EC_PARAM_c2pnb304w1_b \ + 0x00, 0xBD, 0xDB, 0x97, 0xE5, 0x55, 0xA5, 0x0A, \ + 0x90, 0x8E, 0x43, 0xB0, 0x1C, 0x79, 0x8E, 0xA5, \ + 0xDA, 0xA6, 0x78, 0x8F, 0x1E, 0xA2, 0x79, 0x4E, \ + 0xFC, 0xF5, 0x71, 0x66, 0xB8, 0xC1, 0x40, 0x39, \ + 0x60, 0x1E, 0x55, 0x82, 0x73, 0x40, 0xBE +#define EC_PARAM_c2pnb304w1_x \ + 0x00, 0x19, 0x7B, 0x07, 0x84, 0x5E, 0x9B, 0xE2, \ + 0xD9, 0x6A, 0xDB, 0x0F, 0x5F, 0x3C, 0x7F, 0x2C, \ + 0xFF, 0xBD, 0x7A, 0x3E, 0xB8, 0xB6, 0xFE, 0xC3, \ + 0x5C, 0x7F, 0xD6, 0x7F, 0x26, 0xDD, 0xF6, 0x28, \ + 0x5A, 0x64, 0x4F, 0x74, 0x0A, 0x26, 0x14 +#define EC_PARAM_c2pnb304w1_y \ + 0x00, 0xE1, 0x9F, 0xBE, 0xB7, 0x6E, 0x0D, 0xA1, \ + 0x71, 0x51, 0x7E, 0xCF, 0x40, 0x1B, 0x50, 0x28, \ + 0x9B, 0xF0, 0x14, 0x10, 0x32, 0x88, 0x52, 0x7A, \ + 0x9B, 0x41, 0x6A, 0x10, 0x5E, 0x80, 0x26, 0x0B, \ + 0x54, 0x9F, 0xDC, 0x1B, 0x92, 0xC0, 0x3B +#define EC_PARAM_c2pnb304w1_order \ + 0x00, 0x00, 0x01, 0x01, 0xD5, 0x56, 0x57, 0x2A, \ + 0xAB, 0xAC, 0x80, 0x01, 0x01, 0xD5, 0x56, 0x57, \ + 0x2A, 0xAB, 0xAC, 0x80, 0x01, 0x02, 0x2D, 0x5C, \ + 0x91, 0xDD, 0x17, 0x3F, 0x8F, 0xB5, 0x61, 0xDA, \ + 0x68, 0x99, 0x16, 0x44, 0x43, 0x05, 0x1D +#endif + +#if 0 +/* c2tnb359v1 : X9.62 curve over a 359 bit binary field */ +#define EC_PARAM_c2tnb359v1_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_c2tnb359v1_a \ + 0x56, 0x67, 0x67, 0x6A, 0x65, 0x4B, 0x20, 0x75, \ + 0x4F, 0x35, 0x6E, 0xA9, 0x20, 0x17, 0xD9, 0x46, \ + 0x56, 0x7C, 0x46, 0x67, 0x55, 0x56, 0xF1, 0x95, \ + 0x56, 0xA0, 0x46, 0x16, 0xB5, 0x67, 0xD2, 0x23, \ + 0xA5, 0xE0, 0x56, 0x56, 0xFB, 0x54, 0x90, 0x16, \ + 0xA9, 0x66, 0x56, 0xA5, 0x57 +#define EC_PARAM_c2tnb359v1_b \ + 0x24, 0x72, 0xE2, 0xD0, 0x19, 0x7C, 0x49, 0x36, \ + 0x3F, 0x1F, 0xE7, 0xF5, 0xB6, 0xDB, 0x07, 0x5D, \ + 0x52, 0xB6, 0x94, 0x7D, 0x13, 0x5D, 0x8C, 0xA4, \ + 0x45, 0x80, 0x5D, 0x39, 0xBC, 0x34, 0x56, 0x26, \ + 0x08, 0x96, 0x87, 0x74, 0x2B, 0x63, 0x29, 0xE7, \ + 0x06, 0x80, 0x23, 0x19, 0x88 +#define EC_PARAM_c2tnb359v1_x \ + 0x3C, 0x25, 0x8E, 0xF3, 0x04, 0x77, 0x67, 0xE7, \ + 0xED, 0xE0, 0xF1, 0xFD, 0xAA, 0x79, 0xDA, 0xEE, \ + 0x38, 0x41, 0x36, 0x6A, 0x13, 0x2E, 0x16, 0x3A, \ + 0xCE, 0xD4, 0xED, 0x24, 0x01, 0xDF, 0x9C, 0x6B, \ + 0xDC, 0xDE, 0x98, 0xE8, 0xE7, 0x07, 0xC0, 0x7A, \ + 0x22, 0x39, 0xB1, 0xB0, 0x97 +#define EC_PARAM_c2tnb359v1_y \ + 0x53, 0xD7, 0xE0, 0x85, 0x29, 0x54, 0x70, 0x48, \ + 0x12, 0x1E, 0x9C, 0x95, 0xF3, 0x79, 0x1D, 0xD8, \ + 0x04, 0x96, 0x39, 0x48, 0xF3, 0x4F, 0xAE, 0x7B, \ + 0xF4, 0x4E, 0xA8, 0x23, 0x65, 0xDC, 0x78, 0x68, \ + 0xFE, 0x57, 0xE4, 0xAE, 0x2D, 0xE2, 0x11, 0x30, \ + 0x5A, 0x40, 0x71, 0x04, 0xBD +#define EC_PARAM_c2tnb359v1_order \ + 0x01, 0xAF, 0x28, 0x6B, 0xCA, 0x1A, 0xF2, 0x86, \ + 0xBC, 0xA1, 0xAF, 0x28, 0x6B, 0xCA, 0x1A, 0xF2, \ + 0x86, 0xBC, 0xA1, 0xAF, 0x28, 0x6B, 0xC9, 0xFB, \ + 0x8F, 0x6B, 0x85, 0xC5, 0x56, 0x89, 0x2C, 0x20, \ + 0xA7, 0xEB, 0x96, 0x4F, 0xE7, 0x71, 0x9E, 0x74, \ + 0xF4, 0x90, 0x75, 0x8D, 0x3B +#endif + +#if 0 +/* c2pnb368w1 : X9.62 curve over a 368 bit binary field */ +#define EC_PARAM_c2pnb368w1_prime \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 +#define EC_PARAM_c2pnb368w1_a \ + 0x00, 0xE0, 0xD2, 0xEE, 0x25, 0x09, 0x52, 0x06, \ + 0xF5, 0xE2, 0xA4, 0xF9, 0xED, 0x22, 0x9F, 0x1F, \ + 0x25, 0x6E, 0x79, 0xA0, 0xE2, 0xB4, 0x55, 0x97, \ + 0x0D, 0x8D, 0x0D, 0x86, 0x5B, 0xD9, 0x47, 0x78, \ + 0xC5, 0x76, 0xD6, 0x2F, 0x0A, 0xB7, 0x51, 0x9C, \ + 0xCD, 0x2A, 0x1A, 0x90, 0x6A, 0xE3, 0x0D +#define EC_PARAM_c2pnb368w1_b \ + 0x00, 0xFC, 0x12, 0x17, 0xD4, 0x32, 0x0A, 0x90, \ + 0x45, 0x2C, 0x76, 0x0A, 0x58, 0xED, 0xCD, 0x30, \ + 0xC8, 0xDD, 0x06, 0x9B, 0x3C, 0x34, 0x45, 0x38, \ + 0x37, 0xA3, 0x4E, 0xD5, 0x0C, 0xB5, 0x49, 0x17, \ + 0xE1, 0xC2, 0x11, 0x2D, 0x84, 0xD1, 0x64, 0xF4, \ + 0x44, 0xF8, 0xF7, 0x47, 0x86, 0x04, 0x6A +#define EC_PARAM_c2pnb368w1_x \ + 0x00, 0x10, 0x85, 0xE2, 0x75, 0x53, 0x81, 0xDC, \ + 0xCC, 0xE3, 0xC1, 0x55, 0x7A, 0xFA, 0x10, 0xC2, \ + 0xF0, 0xC0, 0xC2, 0x82, 0x56, 0x46, 0xC5, 0xB3, \ + 0x4A, 0x39, 0x4C, 0xBC, 0xFA, 0x8B, 0xC1, 0x6B, \ + 0x22, 0xE7, 0xE7, 0x89, 0xE9, 0x27, 0xBE, 0x21, \ + 0x6F, 0x02, 0xE1, 0xFB, 0x13, 0x6A, 0x5F +#define EC_PARAM_c2pnb368w1_y \ + 0x00, 0x7B, 0x3E, 0xB1, 0xBD, 0xDC, 0xBA, 0x62, \ + 0xD5, 0xD8, 0xB2, 0x05, 0x9B, 0x52, 0x57, 0x97, \ + 0xFC, 0x73, 0x82, 0x2C, 0x59, 0x05, 0x9C, 0x62, \ + 0x3A, 0x45, 0xFF, 0x38, 0x43, 0xCE, 0xE8, 0xF8, \ + 0x7C, 0xD1, 0x85, 0x5A, 0xDA, 0xA8, 0x1E, 0x2A, \ + 0x07, 0x50, 0xB8, 0x0F, 0xDA, 0x23, 0x10 +#define EC_PARAM_c2pnb368w1_order \ + 0x00, 0x00, 0x01, 0x00, 0x90, 0x51, 0x2D, 0xA9, \ + 0xAF, 0x72, 0xB0, 0x83, 0x49, 0xD9, 0x8A, 0x5D, \ + 0xD4, 0xC7, 0xB0, 0x53, 0x2E, 0xCA, 0x51, 0xCE, \ + 0x03, 0xE2, 0xD1, 0x0F, 0x3B, 0x7A, 0xC5, 0x79, \ + 0xBD, 0x87, 0xE9, 0x09, 0xAE, 0x40, 0xA6, 0xF1, \ + 0x31, 0xE9, 0xCF, 0xCE, 0x5B, 0xD9, 0x67 +#endif + +#if 0 +/* c2tnb431r1 : X9.62 curve over a 431 bit binary field */ +#define EC_PARAM_c2tnb431r1_prime \ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_c2tnb431r1_a \ + 0x1A, 0x82, 0x7E, 0xF0, 0x0D, 0xD6, 0xFC, 0x0E, \ + 0x23, 0x4C, 0xAF, 0x04, 0x6C, 0x6A, 0x5D, 0x8A, \ + 0x85, 0x39, 0x5B, 0x23, 0x6C, 0xC4, 0xAD, 0x2C, \ + 0xF3, 0x2A, 0x0C, 0xAD, 0xBD, 0xC9, 0xDD, 0xF6, \ + 0x20, 0xB0, 0xEB, 0x99, 0x06, 0xD0, 0x95, 0x7F, \ + 0x6C, 0x6F, 0xEA, 0xCD, 0x61, 0x54, 0x68, 0xDF, \ + 0x10, 0x4D, 0xE2, 0x96, 0xCD, 0x8F +#define EC_PARAM_c2tnb431r1_b \ + 0x10, 0xD9, 0xB4, 0xA3, 0xD9, 0x04, 0x7D, 0x8B, \ + 0x15, 0x43, 0x59, 0xAB, 0xFB, 0x1B, 0x7F, 0x54, \ + 0x85, 0xB0, 0x4C, 0xEB, 0x86, 0x82, 0x37, 0xDD, \ + 0xC9, 0xDE, 0xDA, 0x98, 0x2A, 0x67, 0x9A, 0x5A, \ + 0x91, 0x9B, 0x62, 0x6D, 0x4E, 0x50, 0xA8, 0xDD, \ + 0x73, 0x1B, 0x10, 0x7A, 0x99, 0x62, 0x38, 0x1F, \ + 0xB5, 0xD8, 0x07, 0xBF, 0x26, 0x18 +#define EC_PARAM_c2tnb431r1_x \ + 0x12, 0x0F, 0xC0, 0x5D, 0x3C, 0x67, 0xA9, 0x9D, \ + 0xE1, 0x61, 0xD2, 0xF4, 0x09, 0x26, 0x22, 0xFE, \ + 0xCA, 0x70, 0x1B, 0xE4, 0xF5, 0x0F, 0x47, 0x58, \ + 0x71, 0x4E, 0x8A, 0x87, 0xBB, 0xF2, 0xA6, 0x58, \ + 0xEF, 0x8C, 0x21, 0xE7, 0xC5, 0xEF, 0xE9, 0x65, \ + 0x36, 0x1F, 0x6C, 0x29, 0x99, 0xC0, 0xC2, 0x47, \ + 0xB0, 0xDB, 0xD7, 0x0C, 0xE6, 0xB7 +#define EC_PARAM_c2tnb431r1_y \ + 0x20, 0xD0, 0xAF, 0x89, 0x03, 0xA9, 0x6F, 0x8D, \ + 0x5F, 0xA2, 0xC2, 0x55, 0x74, 0x5D, 0x3C, 0x45, \ + 0x1B, 0x30, 0x2C, 0x93, 0x46, 0xD9, 0xB7, 0xE4, \ + 0x85, 0xE7, 0xBC, 0xE4, 0x1F, 0x6B, 0x59, 0x1F, \ + 0x3E, 0x8F, 0x6A, 0xDD, 0xCB, 0xB0, 0xBC, 0x4C, \ + 0x2F, 0x94, 0x7A, 0x7D, 0xE1, 0xA8, 0x9B, 0x62, \ + 0x5D, 0x6A, 0x59, 0x8B, 0x37, 0x60 +#define EC_PARAM_c2tnb431r1_order \ + 0x00, 0x03, 0x40, 0x34, 0x03, 0x40, 0x34, 0x03, \ + 0x40, 0x34, 0x03, 0x40, 0x34, 0x03, 0x40, 0x34, \ + 0x03, 0x40, 0x34, 0x03, 0x40, 0x34, 0x03, 0x40, \ + 0x34, 0x03, 0x40, 0x34, 0x03, 0x23, 0xC3, 0x13, \ + 0xFA, 0xB5, 0x05, 0x89, 0x70, 0x3B, 0x5E, 0xC6, \ + 0x8D, 0x35, 0x87, 0xFE, 0xC6, 0x0D, 0x16, 0x1C, \ + 0xC1, 0x49, 0xC1, 0xAD, 0x4A, 0x91 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls1 : WTLS curve over a 113 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_x \ + 0x01, 0x66, 0x79, 0x79, 0xA4, 0x0B, 0xA4, 0x97, \ + 0xE5, 0xD5, 0xC2, 0x70, 0x78, 0x06, 0x17 +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_y \ + 0x00, 0xF4, 0x4B, 0x4A, 0xF1, 0xEC, 0xC2, 0x63, \ + 0x0E, 0x08, 0x78, 0x5C, 0xEB, 0xCC, 0x15 +#define EC_PARAM_wap_wsg_idm_ecid_wtls1_order \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFD, 0xBF, 0x91, 0xAF, 0x6D, 0xEA, 0x73 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls3 : NIST/SECG/WTLS curve over a 163 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0xC9 +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_x \ + 0x02, 0xFE, 0x13, 0xC0, 0x53, 0x7B, 0xBC, 0x11, \ + 0xAC, 0xAA, 0x07, 0xD7, 0x93, 0xDE, 0x4E, 0x6D, \ + 0x5E, 0x5C, 0x94, 0xEE, 0xE8 +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_y \ + 0x02, 0x89, 0x07, 0x0F, 0xB0, 0x5D, 0x38, 0xFF, \ + 0x58, 0x32, 0x1F, 0x2E, 0x80, 0x05, 0x36, 0xD5, \ + 0x38, 0xCC, 0xDA, 0xA3, 0xD9 +#define EC_PARAM_wap_wsg_idm_ecid_wtls3_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x02, 0x01, 0x08, 0xA2, 0xE0, 0xCC, \ + 0x0D, 0x99, 0xF8, 0xA5, 0xEF +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls4 : SECG curve over a 113 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_a \ + 0x00, 0x30, 0x88, 0x25, 0x0C, 0xA6, 0xE7, 0xC7, \ + 0xFE, 0x64, 0x9C, 0xE8, 0x58, 0x20, 0xF7 +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_b \ + 0x00, 0xE8, 0xBE, 0xE4, 0xD3, 0xE2, 0x26, 0x07, \ + 0x44, 0x18, 0x8B, 0xE0, 0xE9, 0xC7, 0x23 +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_x \ + 0x00, 0x9D, 0x73, 0x61, 0x6F, 0x35, 0xF4, 0xAB, \ + 0x14, 0x07, 0xD7, 0x35, 0x62, 0xC1, 0x0F +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_y \ + 0x00, 0xA5, 0x28, 0x30, 0x27, 0x79, 0x58, 0xEE, \ + 0x84, 0xD1, 0x31, 0x5E, 0xD3, 0x18, 0x86 +#define EC_PARAM_wap_wsg_idm_ecid_wtls4_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0xD9, 0xCC, 0xEC, 0x8A, 0x39, 0xE5, 0x6F +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls5 : X9.62 curve over a 163 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01, 0x07 +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_a \ + 0x07, 0x25, 0x46, 0xB5, 0x43, 0x52, 0x34, 0xA4, \ + 0x22, 0xE0, 0x78, 0x96, 0x75, 0xF4, 0x32, 0xC8, \ + 0x94, 0x35, 0xDE, 0x52, 0x42 +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_b \ + 0x00, 0xC9, 0x51, 0x7D, 0x06, 0xD5, 0x24, 0x0D, \ + 0x3C, 0xFF, 0x38, 0xC7, 0x4B, 0x20, 0xB6, 0xCD, \ + 0x4D, 0x6F, 0x9D, 0xD4, 0xD9 +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_x \ + 0x07, 0xAF, 0x69, 0x98, 0x95, 0x46, 0x10, 0x3D, \ + 0x79, 0x32, 0x9F, 0xCC, 0x3D, 0x74, 0x88, 0x0F, \ + 0x33, 0xBB, 0xE8, 0x03, 0xCB +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_y \ + 0x01, 0xEC, 0x23, 0x21, 0x1B, 0x59, 0x66, 0xAD, \ + 0xEA, 0x1D, 0x3F, 0x87, 0xF7, 0xEA, 0x58, 0x48, \ + 0xAE, 0xF0, 0xB7, 0xCA, 0x9F +#define EC_PARAM_wap_wsg_idm_ecid_wtls5_order \ + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xE6, 0x0F, 0xC8, 0x82, 0x1C, \ + 0xC7, 0x4D, 0xAE, 0xAF, 0xC1 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls6 : SECG/WTLS curve over a 112 bit prime field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_prime \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x66, \ + 0x80, 0x76, 0xBE, 0xAD, 0x20, 0x8B +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_a \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x66, \ + 0x80, 0x76, 0xBE, 0xAD, 0x20, 0x88 +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_b \ + 0x65, 0x9E, 0xF8, 0xBA, 0x04, 0x39, 0x16, 0xEE, \ + 0xDE, 0x89, 0x11, 0x70, 0x2B, 0x22 +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_x \ + 0x09, 0x48, 0x72, 0x39, 0x99, 0x5A, 0x5E, 0xE7, \ + 0x6B, 0x55, 0xF9, 0xC2, 0xF0, 0x98 +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_y \ + 0xA8, 0x9C, 0xE5, 0xAF, 0x87, 0x24, 0xC0, 0xA2, \ + 0x3E, 0x0E, 0x0F, 0xF7, 0x75, 0x00 +#define EC_PARAM_wap_wsg_idm_ecid_wtls6_order \ + 0xDB, 0x7C, 0x2A, 0xBF, 0x62, 0xE3, 0x5E, 0x76, \ + 0x28, 0xDF, 0xAC, 0x65, 0x61, 0xC5 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls7 : SECG/WTLS curve over a 160 bit prime field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_prime \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xAC, 0x73 +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_a \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFE, 0xFF, 0xFF, 0xAC, 0x70 +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_b \ + 0x00, 0xB4, 0xE1, 0x34, 0xD3, 0xFB, 0x59, 0xEB, \ + 0x8B, 0xAB, 0x57, 0x27, 0x49, 0x04, 0x66, 0x4D, \ + 0x5A, 0xF5, 0x03, 0x88, 0xBA +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_x \ + 0x00, 0x52, 0xDC, 0xB0, 0x34, 0x29, 0x3A, 0x11, \ + 0x7E, 0x1F, 0x4F, 0xF1, 0x1B, 0x30, 0xF7, 0x19, \ + 0x9D, 0x31, 0x44, 0xCE, 0x6D +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_y \ + 0x00, 0xFE, 0xAF, 0xFE, 0xF2, 0xE3, 0x31, 0xF2, \ + 0x96, 0xE0, 0x71, 0xFA, 0x0D, 0xF9, 0x98, 0x2C, \ + 0xFE, 0xA7, 0xD4, 0x3F, 0x2E +#define EC_PARAM_wap_wsg_idm_ecid_wtls7_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x35, 0x1E, 0xE7, 0x86, 0xA8, \ + 0x18, 0xF3, 0xA1, 0xA1, 0x6B +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls8 : WTLS curve over a 112 bit prime field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_prime \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xE7 +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_x \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_y \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +#define EC_PARAM_wap_wsg_idm_ecid_wtls8_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, \ + 0xEC, 0xEA, 0x55, 0x1A, 0xD8, 0x37, 0xE9 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls9 : WTLS curve over a 160 bit prime field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_prime \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFC, 0x80, 0x8F +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x03 +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_x \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_y \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x02 +#define EC_PARAM_wap_wsg_idm_ecid_wtls9_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xCD, 0xC9, 0x8A, 0xE0, 0xE2, \ + 0xDE, 0x57, 0x4A, 0xBF, 0x33 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls10 : NIST/SECG/WTLS curve over a 233 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_x \ + 0x01, 0x72, 0x32, 0xBA, 0x85, 0x3A, 0x7E, 0x73, \ + 0x1A, 0xF1, 0x29, 0xF2, 0x2F, 0xF4, 0x14, 0x95, \ + 0x63, 0xA4, 0x19, 0xC2, 0x6B, 0xF5, 0x0A, 0x4C, \ + 0x9D, 0x6E, 0xEF, 0xAD, 0x61, 0x26 +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_y \ + 0x01, 0xDB, 0x53, 0x7D, 0xEC, 0xE8, 0x19, 0xB7, \ + 0xF7, 0x0F, 0x55, 0x5A, 0x67, 0xC4, 0x27, 0xA8, \ + 0xCD, 0x9B, 0xF1, 0x8A, 0xEB, 0x9B, 0x56, 0xE0, \ + 0xC1, 0x10, 0x56, 0xFA, 0xE6, 0xA3 +#define EC_PARAM_wap_wsg_idm_ecid_wtls10_order \ + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, \ + 0x9D, 0x5B, 0xB9, 0x15, 0xBC, 0xD4, 0x6E, 0xFB, \ + 0x1A, 0xD5, 0xF1, 0x73, 0xAB, 0xDF +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls11 : NIST/SECG/WTLS curve over a 233 bit binary field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_b \ + 0x00, 0x66, 0x64, 0x7E, 0xDE, 0x6C, 0x33, 0x2C, \ + 0x7F, 0x8C, 0x09, 0x23, 0xBB, 0x58, 0x21, 0x3B, \ + 0x33, 0x3B, 0x20, 0xE9, 0xCE, 0x42, 0x81, 0xFE, \ + 0x11, 0x5F, 0x7D, 0x8F, 0x90, 0xAD +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_x \ + 0x00, 0xFA, 0xC9, 0xDF, 0xCB, 0xAC, 0x83, 0x13, \ + 0xBB, 0x21, 0x39, 0xF1, 0xBB, 0x75, 0x5F, 0xEF, \ + 0x65, 0xBC, 0x39, 0x1F, 0x8B, 0x36, 0xF8, 0xF8, \ + 0xEB, 0x73, 0x71, 0xFD, 0x55, 0x8B +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_y \ + 0x01, 0x00, 0x6A, 0x08, 0xA4, 0x19, 0x03, 0x35, \ + 0x06, 0x78, 0xE5, 0x85, 0x28, 0xBE, 0xBF, 0x8A, \ + 0x0B, 0xEF, 0xF8, 0x67, 0xA7, 0xCA, 0x36, 0x71, \ + 0x6F, 0x7E, 0x01, 0xF8, 0x10, 0x52 +#define EC_PARAM_wap_wsg_idm_ecid_wtls11_order \ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, \ + 0xE9, 0x74, 0xE7, 0x2F, 0x8A, 0x69, 0x22, 0x03, \ + 0x1D, 0x26, 0x03, 0xCF, 0xE0, 0xD7 +#endif + +#if 0 +/* wap-wsg-idm-ecid-wtls12 : WTLS curve over a 224 bit prime field */ +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_a \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFE +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_b \ + 0xB4, 0x05, 0x0A, 0x85, 0x0C, 0x04, 0xB3, 0xAB, \ + 0xF5, 0x41, 0x32, 0x56, 0x50, 0x44, 0xB0, 0xB7, \ + 0xD7, 0xBF, 0xD8, 0xBA, 0x27, 0x0B, 0x39, 0x43, \ + 0x23, 0x55, 0xFF, 0xB4 +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_x \ + 0xB7, 0x0E, 0x0C, 0xBD, 0x6B, 0xB4, 0xBF, 0x7F, \ + 0x32, 0x13, 0x90, 0xB9, 0x4A, 0x03, 0xC1, 0xD3, \ + 0x56, 0xC2, 0x11, 0x22, 0x34, 0x32, 0x80, 0xD6, \ + 0x11, 0x5C, 0x1D, 0x21 +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_y \ + 0xBD, 0x37, 0x63, 0x88, 0xB5, 0xF7, 0x23, 0xFB, \ + 0x4C, 0x22, 0xDF, 0xE6, 0xCD, 0x43, 0x75, 0xA0, \ + 0x5A, 0x07, 0x47, 0x64, 0x44, 0xD5, 0x81, 0x99, \ + 0x85, 0x00, 0x7E, 0x34 +#define EC_PARAM_wap_wsg_idm_ecid_wtls12_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x16, 0xA2, \ + 0xE0, 0xB8, 0xF0, 0x3E, 0x13, 0xDD, 0x29, 0x45, \ + 0x5C, 0x5C, 0x2A, 0x3D +#endif + +#if 0 +/* Oakley-EC2N-3 : + IPSec/IKE/Oakley curve #3 over a 155 bit binary field. + Not suitable for ECDSA. + Questionable extension field! */ +#define EC_PARAM_Oakley_EC2N_3_prime \ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_Oakley_EC2N_3_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_Oakley_EC2N_3_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x07, 0x33, 0x8F +#define EC_PARAM_Oakley_EC2N_3_x \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x7B +#define EC_PARAM_Oakley_EC2N_3_y \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x01, 0xC8 +#define EC_PARAM_Oakley_EC2N_3_order \ + 0x02, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, \ + 0xAA, 0xAA, 0xC7, 0xF3, 0xC7, 0x88, 0x1B, 0xD0, \ + 0x86, 0x8F, 0xA8, 0x6C +#endif + +#if 0 +/* Oakley-EC2N-4 : + IPSec/IKE/Oakley curve #4 over a 185 bit binary field. + Not suitable for ECDSA. + Questionable extension field! */ +#define EC_PARAM_Oakley_EC2N_4_prime \ + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_Oakley_EC2N_4_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_Oakley_EC2N_4_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xE9 +#define EC_PARAM_Oakley_EC2N_4_x \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 +#define EC_PARAM_Oakley_EC2N_4_y \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D +#define EC_PARAM_Oakley_EC2N_4_order \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xED, 0xF9, 0x7C, 0x44, \ + 0xDB, 0x9F, 0x24, 0x20, 0xBA, 0xFC, 0xA7, 0x5E +#endif + +#if 1 +/* brainpoolP160r1 : RFC 5639 curve over a 160 bit prime field */ +#define EC_PARAM_brainpoolP160r1_prime \ + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, \ + 0x60, 0xDF, 0xC7, 0xAD, 0x95, 0xB3, 0xD8, 0x13, \ + 0x95, 0x15, 0x62, 0x0F +#define EC_PARAM_brainpoolP160r1_a \ + 0x34, 0x0E, 0x7B, 0xE2, 0xA2, 0x80, 0xEB, 0x74, \ + 0xE2, 0xBE, 0x61, 0xBA, 0xDA, 0x74, 0x5D, 0x97, \ + 0xE8, 0xF7, 0xC3, 0x00 +#define EC_PARAM_brainpoolP160r1_b \ + 0x1E, 0x58, 0x9A, 0x85, 0x95, 0x42, 0x34, 0x12, \ + 0x13, 0x4F, 0xAA, 0x2D, 0xBD, 0xEC, 0x95, 0xC8, \ + 0xD8, 0x67, 0x5E, 0x58 +#define EC_PARAM_brainpoolP160r1_x \ + 0xBE, 0xD5, 0xAF, 0x16, 0xEA, 0x3F, 0x6A, 0x4F, \ + 0x62, 0x93, 0x8C, 0x46, 0x31, 0xEB, 0x5A, 0xF7, \ + 0xBD, 0xBC, 0xDB, 0xC3 +#define EC_PARAM_brainpoolP160r1_y \ + 0x16, 0x67, 0xCB, 0x47, 0x7A, 0x1A, 0x8E, 0xC3, \ + 0x38, 0xF9, 0x47, 0x41, 0x66, 0x9C, 0x97, 0x63, \ + 0x16, 0xDA, 0x63, 0x21 +#define EC_PARAM_brainpoolP160r1_order \ + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, \ + 0x60, 0xDF, 0x59, 0x91, 0xD4, 0x50, 0x29, 0x40, \ + 0x9E, 0x60, 0xFC, 0x09 +#endif + +#if 1 +/* brainpoolP160t1 : RFC 5639 curve over a 160 bit prime field */ +#define EC_PARAM_brainpoolP160t1_prime \ + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, \ + 0x60, 0xDF, 0xC7, 0xAD, 0x95, 0xB3, 0xD8, 0x13, \ + 0x95, 0x15, 0x62, 0x0F +#define EC_PARAM_brainpoolP160t1_a \ + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, \ + 0x60, 0xDF, 0xC7, 0xAD, 0x95, 0xB3, 0xD8, 0x13, \ + 0x95, 0x15, 0x62, 0x0C +#define EC_PARAM_brainpoolP160t1_b \ + 0x7A, 0x55, 0x6B, 0x6D, 0xAE, 0x53, 0x5B, 0x7B, \ + 0x51, 0xED, 0x2C, 0x4D, 0x7D, 0xAA, 0x7A, 0x0B, \ + 0x5C, 0x55, 0xF3, 0x80 +#define EC_PARAM_brainpoolP160t1_x \ + 0xB1, 0x99, 0xB1, 0x3B, 0x9B, 0x34, 0xEF, 0xC1, \ + 0x39, 0x7E, 0x64, 0xBA, 0xEB, 0x05, 0xAC, 0xC2, \ + 0x65, 0xFF, 0x23, 0x78 +#define EC_PARAM_brainpoolP160t1_y \ + 0xAD, 0xD6, 0x71, 0x8B, 0x7C, 0x7C, 0x19, 0x61, \ + 0xF0, 0x99, 0x1B, 0x84, 0x24, 0x43, 0x77, 0x21, \ + 0x52, 0xC9, 0xE0, 0xAD +#define EC_PARAM_brainpoolP160t1_order \ + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, \ + 0x60, 0xDF, 0x59, 0x91, 0xD4, 0x50, 0x29, 0x40, \ + 0x9E, 0x60, 0xFC, 0x09 +#endif + +#if 1 +/* brainpoolP192r1 : RFC 5639 curve over a 192 bit prime field */ +#define EC_PARAM_brainpoolP192r1_prime \ + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, \ + 0xA7, 0xA3, 0x46, 0x30, 0x93, 0xD1, 0x8D, 0xB7, \ + 0x8F, 0xCE, 0x47, 0x6D, 0xE1, 0xA8, 0x62, 0x97 +#define EC_PARAM_brainpoolP192r1_a \ + 0x6A, 0x91, 0x17, 0x40, 0x76, 0xB1, 0xE0, 0xE1, \ + 0x9C, 0x39, 0xC0, 0x31, 0xFE, 0x86, 0x85, 0xC1, \ + 0xCA, 0xE0, 0x40, 0xE5, 0xC6, 0x9A, 0x28, 0xEF +#define EC_PARAM_brainpoolP192r1_b \ + 0x46, 0x9A, 0x28, 0xEF, 0x7C, 0x28, 0xCC, 0xA3, \ + 0xDC, 0x72, 0x1D, 0x04, 0x4F, 0x44, 0x96, 0xBC, \ + 0xCA, 0x7E, 0xF4, 0x14, 0x6F, 0xBF, 0x25, 0xC9 +#define EC_PARAM_brainpoolP192r1_x \ + 0xC0, 0xA0, 0x64, 0x7E, 0xAA, 0xB6, 0xA4, 0x87, \ + 0x53, 0xB0, 0x33, 0xC5, 0x6C, 0xB0, 0xF0, 0x90, \ + 0x0A, 0x2F, 0x5C, 0x48, 0x53, 0x37, 0x5F, 0xD6 +#define EC_PARAM_brainpoolP192r1_y \ + 0x14, 0xB6, 0x90, 0x86, 0x6A, 0xBD, 0x5B, 0xB8, \ + 0x8B, 0x5F, 0x48, 0x28, 0xC1, 0x49, 0x00, 0x02, \ + 0xE6, 0x77, 0x3F, 0xA2, 0xFA, 0x29, 0x9B, 0x8F +#define EC_PARAM_brainpoolP192r1_order \ + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, \ + 0xA7, 0xA3, 0x46, 0x2F, 0x9E, 0x9E, 0x91, 0x6B, \ + 0x5B, 0xE8, 0xF1, 0x02, 0x9A, 0xC4, 0xAC, 0xC1 +#endif + +#if 1 +/* brainpoolP192t1 : RFC 5639 curve over a 192 bit prime field */ +#define EC_PARAM_brainpoolP192t1_prime \ + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, \ + 0xA7, 0xA3, 0x46, 0x30, 0x93, 0xD1, 0x8D, 0xB7, \ + 0x8F, 0xCE, 0x47, 0x6D, 0xE1, 0xA8, 0x62, 0x97 +#define EC_PARAM_brainpoolP192t1_a \ + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, \ + 0xA7, 0xA3, 0x46, 0x30, 0x93, 0xD1, 0x8D, 0xB7, \ + 0x8F, 0xCE, 0x47, 0x6D, 0xE1, 0xA8, 0x62, 0x94 +#define EC_PARAM_brainpoolP192t1_b \ + 0x13, 0xD5, 0x6F, 0xFA, 0xEC, 0x78, 0x68, 0x1E, \ + 0x68, 0xF9, 0xDE, 0xB4, 0x3B, 0x35, 0xBE, 0xC2, \ + 0xFB, 0x68, 0x54, 0x2E, 0x27, 0x89, 0x7B, 0x79 +#define EC_PARAM_brainpoolP192t1_x \ + 0x3A, 0xE9, 0xE5, 0x8C, 0x82, 0xF6, 0x3C, 0x30, \ + 0x28, 0x2E, 0x1F, 0xE7, 0xBB, 0xF4, 0x3F, 0xA7, \ + 0x2C, 0x44, 0x6A, 0xF6, 0xF4, 0x61, 0x81, 0x29 +#define EC_PARAM_brainpoolP192t1_y \ + 0x09, 0x7E, 0x2C, 0x56, 0x67, 0xC2, 0x22, 0x3A, \ + 0x90, 0x2A, 0xB5, 0xCA, 0x44, 0x9D, 0x00, 0x84, \ + 0xB7, 0xE5, 0xB3, 0xDE, 0x7C, 0xCC, 0x01, 0xC9 +#define EC_PARAM_brainpoolP192t1_order \ + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, \ + 0xA7, 0xA3, 0x46, 0x2F, 0x9E, 0x9E, 0x91, 0x6B, \ + 0x5B, 0xE8, 0xF1, 0x02, 0x9A, 0xC4, 0xAC, 0xC1 +#endif + +#if 1 +/* brainpoolP224r1 : RFC 5639 curve over a 224 bit prime field */ +#define EC_PARAM_brainpoolP224r1_prime \ + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, \ + 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD1, 0xD7, 0x87, \ + 0xB0, 0x9F, 0x07, 0x57, 0x97, 0xDA, 0x89, 0xF5, \ + 0x7E, 0xC8, 0xC0, 0xFF +#define EC_PARAM_brainpoolP224r1_a \ + 0x68, 0xA5, 0xE6, 0x2C, 0xA9, 0xCE, 0x6C, 0x1C, \ + 0x29, 0x98, 0x03, 0xA6, 0xC1, 0x53, 0x0B, 0x51, \ + 0x4E, 0x18, 0x2A, 0xD8, 0xB0, 0x04, 0x2A, 0x59, \ + 0xCA, 0xD2, 0x9F, 0x43 +#define EC_PARAM_brainpoolP224r1_b \ + 0x25, 0x80, 0xF6, 0x3C, 0xCF, 0xE4, 0x41, 0x38, \ + 0x87, 0x07, 0x13, 0xB1, 0xA9, 0x23, 0x69, 0xE3, \ + 0x3E, 0x21, 0x35, 0xD2, 0x66, 0xDB, 0xB3, 0x72, \ + 0x38, 0x6C, 0x40, 0x0B +#define EC_PARAM_brainpoolP224r1_x \ + 0x0D, 0x90, 0x29, 0xAD, 0x2C, 0x7E, 0x5C, 0xF4, \ + 0x34, 0x08, 0x23, 0xB2, 0xA8, 0x7D, 0xC6, 0x8C, \ + 0x9E, 0x4C, 0xE3, 0x17, 0x4C, 0x1E, 0x6E, 0xFD, \ + 0xEE, 0x12, 0xC0, 0x7D +#define EC_PARAM_brainpoolP224r1_y \ + 0x58, 0xAA, 0x56, 0xF7, 0x72, 0xC0, 0x72, 0x6F, \ + 0x24, 0xC6, 0xB8, 0x9E, 0x4E, 0xCD, 0xAC, 0x24, \ + 0x35, 0x4B, 0x9E, 0x99, 0xCA, 0xA3, 0xF6, 0xD3, \ + 0x76, 0x14, 0x02, 0xCD +#define EC_PARAM_brainpoolP224r1_order \ + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, \ + 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD0, 0xFB, 0x98, \ + 0xD1, 0x16, 0xBC, 0x4B, 0x6D, 0xDE, 0xBC, 0xA3, \ + 0xA5, 0xA7, 0x93, 0x9F +#endif + +#if 1 +/* brainpoolP224t1 : RFC 5639 curve over a 224 bit prime field */ +#define EC_PARAM_brainpoolP224t1_prime \ + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, \ + 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD1, 0xD7, 0x87, \ + 0xB0, 0x9F, 0x07, 0x57, 0x97, 0xDA, 0x89, 0xF5, \ + 0x7E, 0xC8, 0xC0, 0xFF +#define EC_PARAM_brainpoolP224t1_a \ + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, \ + 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD1, 0xD7, 0x87, \ + 0xB0, 0x9F, 0x07, 0x57, 0x97, 0xDA, 0x89, 0xF5, \ + 0x7E, 0xC8, 0xC0, 0xFC +#define EC_PARAM_brainpoolP224t1_b \ + 0x4B, 0x33, 0x7D, 0x93, 0x41, 0x04, 0xCD, 0x7B, \ + 0xEF, 0x27, 0x1B, 0xF6, 0x0C, 0xED, 0x1E, 0xD2, \ + 0x0D, 0xA1, 0x4C, 0x08, 0xB3, 0xBB, 0x64, 0xF1, \ + 0x8A, 0x60, 0x88, 0x8D +#define EC_PARAM_brainpoolP224t1_x \ + 0x6A, 0xB1, 0xE3, 0x44, 0xCE, 0x25, 0xFF, 0x38, \ + 0x96, 0x42, 0x4E, 0x7F, 0xFE, 0x14, 0x76, 0x2E, \ + 0xCB, 0x49, 0xF8, 0x92, 0x8A, 0xC0, 0xC7, 0x60, \ + 0x29, 0xB4, 0xD5, 0x80 +#define EC_PARAM_brainpoolP224t1_y \ + 0x03, 0x74, 0xE9, 0xF5, 0x14, 0x3E, 0x56, 0x8C, \ + 0xD2, 0x3F, 0x3F, 0x4D, 0x7C, 0x0D, 0x4B, 0x1E, \ + 0x41, 0xC8, 0xCC, 0x0D, 0x1C, 0x6A, 0xBD, 0x5F, \ + 0x1A, 0x46, 0xDB, 0x4C +#define EC_PARAM_brainpoolP224t1_order \ + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, \ + 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD0, 0xFB, 0x98, \ + 0xD1, 0x16, 0xBC, 0x4B, 0x6D, 0xDE, 0xBC, 0xA3, \ + 0xA5, 0xA7, 0x93, 0x9F +#endif + +#if 1 +/* brainpoolP256r1 : RFC 5639 curve over a 256 bit prime field */ +#define EC_PARAM_brainpoolP256r1_prime \ + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, \ + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, \ + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, \ + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77 +#define EC_PARAM_brainpoolP256r1_a \ + 0x7D, 0x5A, 0x09, 0x75, 0xFC, 0x2C, 0x30, 0x57, \ + 0xEE, 0xF6, 0x75, 0x30, 0x41, 0x7A, 0xFF, 0xE7, \ + 0xFB, 0x80, 0x55, 0xC1, 0x26, 0xDC, 0x5C, 0x6C, \ + 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9 +#define EC_PARAM_brainpoolP256r1_b \ + 0x26, 0xDC, 0x5C, 0x6C, 0xE9, 0x4A, 0x4B, 0x44, \ + 0xF3, 0x30, 0xB5, 0xD9, 0xBB, 0xD7, 0x7C, 0xBF, \ + 0x95, 0x84, 0x16, 0x29, 0x5C, 0xF7, 0xE1, 0xCE, \ + 0x6B, 0xCC, 0xDC, 0x18, 0xFF, 0x8C, 0x07, 0xB6 +#define EC_PARAM_brainpoolP256r1_x \ + 0x8B, 0xD2, 0xAE, 0xB9, 0xCB, 0x7E, 0x57, 0xCB, \ + 0x2C, 0x4B, 0x48, 0x2F, 0xFC, 0x81, 0xB7, 0xAF, \ + 0xB9, 0xDE, 0x27, 0xE1, 0xE3, 0xBD, 0x23, 0xC2, \ + 0x3A, 0x44, 0x53, 0xBD, 0x9A, 0xCE, 0x32, 0x62 +#define EC_PARAM_brainpoolP256r1_y \ + 0x54, 0x7E, 0xF8, 0x35, 0xC3, 0xDA, 0xC4, 0xFD, \ + 0x97, 0xF8, 0x46, 0x1A, 0x14, 0x61, 0x1D, 0xC9, \ + 0xC2, 0x77, 0x45, 0x13, 0x2D, 0xED, 0x8E, 0x54, \ + 0x5C, 0x1D, 0x54, 0xC7, 0x2F, 0x04, 0x69, 0x97 +#define EC_PARAM_brainpoolP256r1_order \ + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, \ + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, \ + 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, \ + 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7 +#endif + +#if 1 +/* brainpoolP256t1 : RFC 5639 curve over a 256 bit prime field */ +#define EC_PARAM_brainpoolP256t1_prime \ + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, \ + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, \ + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, \ + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77 +#define EC_PARAM_brainpoolP256t1_a \ + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, \ + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, \ + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, \ + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x74 +#define EC_PARAM_brainpoolP256t1_b \ + 0x66, 0x2C, 0x61, 0xC4, 0x30, 0xD8, 0x4E, 0xA4, \ + 0xFE, 0x66, 0xA7, 0x73, 0x3D, 0x0B, 0x76, 0xB7, \ + 0xBF, 0x93, 0xEB, 0xC4, 0xAF, 0x2F, 0x49, 0x25, \ + 0x6A, 0xE5, 0x81, 0x01, 0xFE, 0xE9, 0x2B, 0x04 +#define EC_PARAM_brainpoolP256t1_x \ + 0xA3, 0xE8, 0xEB, 0x3C, 0xC1, 0xCF, 0xE7, 0xB7, \ + 0x73, 0x22, 0x13, 0xB2, 0x3A, 0x65, 0x61, 0x49, \ + 0xAF, 0xA1, 0x42, 0xC4, 0x7A, 0xAF, 0xBC, 0x2B, \ + 0x79, 0xA1, 0x91, 0x56, 0x2E, 0x13, 0x05, 0xF4 +#define EC_PARAM_brainpoolP256t1_y \ + 0x2D, 0x99, 0x6C, 0x82, 0x34, 0x39, 0xC5, 0x6D, \ + 0x7F, 0x7B, 0x22, 0xE1, 0x46, 0x44, 0x41, 0x7E, \ + 0x69, 0xBC, 0xB6, 0xDE, 0x39, 0xD0, 0x27, 0x00, \ + 0x1D, 0xAB, 0xE8, 0xF3, 0x5B, 0x25, 0xC9, 0xBE +#define EC_PARAM_brainpoolP256t1_order \ + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, \ + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, \ + 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, \ + 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7 +#endif + +#if 1 +/* brainpoolP320r1 : RFC 5639 curve over a 320 bit prime field */ +#define EC_PARAM_brainpoolP320r1_prime \ + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, \ + 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, \ + 0xF9, 0x8F, 0xCF, 0xA6, 0xF6, 0xF4, 0x0D, 0xEF, \ + 0x4F, 0x92, 0xB9, 0xEC, 0x78, 0x93, 0xEC, 0x28, \ + 0xFC, 0xD4, 0x12, 0xB1, 0xF1, 0xB3, 0x2E, 0x27 +#define EC_PARAM_brainpoolP320r1_a \ + 0x3E, 0xE3, 0x0B, 0x56, 0x8F, 0xBA, 0xB0, 0xF8, \ + 0x83, 0xCC, 0xEB, 0xD4, 0x6D, 0x3F, 0x3B, 0xB8, \ + 0xA2, 0xA7, 0x35, 0x13, 0xF5, 0xEB, 0x79, 0xDA, \ + 0x66, 0x19, 0x0E, 0xB0, 0x85, 0xFF, 0xA9, 0xF4, \ + 0x92, 0xF3, 0x75, 0xA9, 0x7D, 0x86, 0x0E, 0xB4 +#define EC_PARAM_brainpoolP320r1_b \ + 0x52, 0x08, 0x83, 0x94, 0x9D, 0xFD, 0xBC, 0x42, \ + 0xD3, 0xAD, 0x19, 0x86, 0x40, 0x68, 0x8A, 0x6F, \ + 0xE1, 0x3F, 0x41, 0x34, 0x95, 0x54, 0xB4, 0x9A, \ + 0xCC, 0x31, 0xDC, 0xCD, 0x88, 0x45, 0x39, 0x81, \ + 0x6F, 0x5E, 0xB4, 0xAC, 0x8F, 0xB1, 0xF1, 0xA6 +#define EC_PARAM_brainpoolP320r1_x \ + 0x43, 0xBD, 0x7E, 0x9A, 0xFB, 0x53, 0xD8, 0xB8, \ + 0x52, 0x89, 0xBC, 0xC4, 0x8E, 0xE5, 0xBF, 0xE6, \ + 0xF2, 0x01, 0x37, 0xD1, 0x0A, 0x08, 0x7E, 0xB6, \ + 0xE7, 0x87, 0x1E, 0x2A, 0x10, 0xA5, 0x99, 0xC7, \ + 0x10, 0xAF, 0x8D, 0x0D, 0x39, 0xE2, 0x06, 0x11 +#define EC_PARAM_brainpoolP320r1_y \ + 0x14, 0xFD, 0xD0, 0x55, 0x45, 0xEC, 0x1C, 0xC8, \ + 0xAB, 0x40, 0x93, 0x24, 0x7F, 0x77, 0x27, 0x5E, \ + 0x07, 0x43, 0xFF, 0xED, 0x11, 0x71, 0x82, 0xEA, \ + 0xA9, 0xC7, 0x78, 0x77, 0xAA, 0xAC, 0x6A, 0xC7, \ + 0xD3, 0x52, 0x45, 0xD1, 0x69, 0x2E, 0x8E, 0xE1 +#define EC_PARAM_brainpoolP320r1_order \ + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, \ + 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, \ + 0xF9, 0x8F, 0xCF, 0xA5, 0xB6, 0x8F, 0x12, 0xA3, \ + 0x2D, 0x48, 0x2E, 0xC7, 0xEE, 0x86, 0x58, 0xE9, \ + 0x86, 0x91, 0x55, 0x5B, 0x44, 0xC5, 0x93, 0x11 +#endif + +#if 1 +/* brainpoolP320t1 : RFC 5639 curve over a 320 bit prime field */ +#define EC_PARAM_brainpoolP320t1_prime \ + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, \ + 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, \ + 0xF9, 0x8F, 0xCF, 0xA6, 0xF6, 0xF4, 0x0D, 0xEF, \ + 0x4F, 0x92, 0xB9, 0xEC, 0x78, 0x93, 0xEC, 0x28, \ + 0xFC, 0xD4, 0x12, 0xB1, 0xF1, 0xB3, 0x2E, 0x27 +#define EC_PARAM_brainpoolP320t1_a \ + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, \ + 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, \ + 0xF9, 0x8F, 0xCF, 0xA6, 0xF6, 0xF4, 0x0D, 0xEF, \ + 0x4F, 0x92, 0xB9, 0xEC, 0x78, 0x93, 0xEC, 0x28, \ + 0xFC, 0xD4, 0x12, 0xB1, 0xF1, 0xB3, 0x2E, 0x24 +#define EC_PARAM_brainpoolP320t1_b \ + 0xA7, 0xF5, 0x61, 0xE0, 0x38, 0xEB, 0x1E, 0xD5, \ + 0x60, 0xB3, 0xD1, 0x47, 0xDB, 0x78, 0x20, 0x13, \ + 0x06, 0x4C, 0x19, 0xF2, 0x7E, 0xD2, 0x7C, 0x67, \ + 0x80, 0xAA, 0xF7, 0x7F, 0xB8, 0xA5, 0x47, 0xCE, \ + 0xB5, 0xB4, 0xFE, 0xF4, 0x22, 0x34, 0x03, 0x53 +#define EC_PARAM_brainpoolP320t1_x \ + 0x92, 0x5B, 0xE9, 0xFB, 0x01, 0xAF, 0xC6, 0xFB, \ + 0x4D, 0x3E, 0x7D, 0x49, 0x90, 0x01, 0x0F, 0x81, \ + 0x34, 0x08, 0xAB, 0x10, 0x6C, 0x4F, 0x09, 0xCB, \ + 0x7E, 0xE0, 0x78, 0x68, 0xCC, 0x13, 0x6F, 0xFF, \ + 0x33, 0x57, 0xF6, 0x24, 0xA2, 0x1B, 0xED, 0x52 +#define EC_PARAM_brainpoolP320t1_y \ + 0x63, 0xBA, 0x3A, 0x7A, 0x27, 0x48, 0x3E, 0xBF, \ + 0x66, 0x71, 0xDB, 0xEF, 0x7A, 0xBB, 0x30, 0xEB, \ + 0xEE, 0x08, 0x4E, 0x58, 0xA0, 0xB0, 0x77, 0xAD, \ + 0x42, 0xA5, 0xA0, 0x98, 0x9D, 0x1E, 0xE7, 0x1B, \ + 0x1B, 0x9B, 0xC0, 0x45, 0x5F, 0xB0, 0xD2, 0xC3 +#define EC_PARAM_brainpoolP320t1_order \ + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, \ + 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, \ + 0xF9, 0x8F, 0xCF, 0xA5, 0xB6, 0x8F, 0x12, 0xA3, \ + 0x2D, 0x48, 0x2E, 0xC7, 0xEE, 0x86, 0x58, 0xE9, \ + 0x86, 0x91, 0x55, 0x5B, 0x44, 0xC5, 0x93, 0x11 +#endif + +#if 1 +/* brainpoolP384r1 : RFC 5639 curve over a 384 bit prime field */ +#define EC_PARAM_brainpoolP384r1_prime \ + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, \ + 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, \ + 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB4, \ + 0x12, 0xB1, 0xDA, 0x19, 0x7F, 0xB7, 0x11, 0x23, \ + 0xAC, 0xD3, 0xA7, 0x29, 0x90, 0x1D, 0x1A, 0x71, \ + 0x87, 0x47, 0x00, 0x13, 0x31, 0x07, 0xEC, 0x53 +#define EC_PARAM_brainpoolP384r1_a \ + 0x7B, 0xC3, 0x82, 0xC6, 0x3D, 0x8C, 0x15, 0x0C, \ + 0x3C, 0x72, 0x08, 0x0A, 0xCE, 0x05, 0xAF, 0xA0, \ + 0xC2, 0xBE, 0xA2, 0x8E, 0x4F, 0xB2, 0x27, 0x87, \ + 0x13, 0x91, 0x65, 0xEF, 0xBA, 0x91, 0xF9, 0x0F, \ + 0x8A, 0xA5, 0x81, 0x4A, 0x50, 0x3A, 0xD4, 0xEB, \ + 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26 +#define EC_PARAM_brainpoolP384r1_b \ + 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26, \ + 0x8B, 0x39, 0xB5, 0x54, 0x16, 0xF0, 0x44, 0x7C, \ + 0x2F, 0xB7, 0x7D, 0xE1, 0x07, 0xDC, 0xD2, 0xA6, \ + 0x2E, 0x88, 0x0E, 0xA5, 0x3E, 0xEB, 0x62, 0xD5, \ + 0x7C, 0xB4, 0x39, 0x02, 0x95, 0xDB, 0xC9, 0x94, \ + 0x3A, 0xB7, 0x86, 0x96, 0xFA, 0x50, 0x4C, 0x11 +#define EC_PARAM_brainpoolP384r1_x \ + 0x1D, 0x1C, 0x64, 0xF0, 0x68, 0xCF, 0x45, 0xFF, \ + 0xA2, 0xA6, 0x3A, 0x81, 0xB7, 0xC1, 0x3F, 0x6B, \ + 0x88, 0x47, 0xA3, 0xE7, 0x7E, 0xF1, 0x4F, 0xE3, \ + 0xDB, 0x7F, 0xCA, 0xFE, 0x0C, 0xBD, 0x10, 0xE8, \ + 0xE8, 0x26, 0xE0, 0x34, 0x36, 0xD6, 0x46, 0xAA, \ + 0xEF, 0x87, 0xB2, 0xE2, 0x47, 0xD4, 0xAF, 0x1E +#define EC_PARAM_brainpoolP384r1_y \ + 0x8A, 0xBE, 0x1D, 0x75, 0x20, 0xF9, 0xC2, 0xA4, \ + 0x5C, 0xB1, 0xEB, 0x8E, 0x95, 0xCF, 0xD5, 0x52, \ + 0x62, 0xB7, 0x0B, 0x29, 0xFE, 0xEC, 0x58, 0x64, \ + 0xE1, 0x9C, 0x05, 0x4F, 0xF9, 0x91, 0x29, 0x28, \ + 0x0E, 0x46, 0x46, 0x21, 0x77, 0x91, 0x81, 0x11, \ + 0x42, 0x82, 0x03, 0x41, 0x26, 0x3C, 0x53, 0x15 +#define EC_PARAM_brainpoolP384r1_order \ + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, \ + 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, \ + 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB3, \ + 0x1F, 0x16, 0x6E, 0x6C, 0xAC, 0x04, 0x25, 0xA7, \ + 0xCF, 0x3A, 0xB6, 0xAF, 0x6B, 0x7F, 0xC3, 0x10, \ + 0x3B, 0x88, 0x32, 0x02, 0xE9, 0x04, 0x65, 0x65 +#endif + +#if 1 +/* brainpoolP384t1 : RFC 5639 curve over a 384 bit prime field */ +#define EC_PARAM_brainpoolP384t1_prime \ + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, \ + 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, \ + 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB4, \ + 0x12, 0xB1, 0xDA, 0x19, 0x7F, 0xB7, 0x11, 0x23, \ + 0xAC, 0xD3, 0xA7, 0x29, 0x90, 0x1D, 0x1A, 0x71, \ + 0x87, 0x47, 0x00, 0x13, 0x31, 0x07, 0xEC, 0x53 +#define EC_PARAM_brainpoolP384t1_a \ + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, \ + 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, \ + 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB4, \ + 0x12, 0xB1, 0xDA, 0x19, 0x7F, 0xB7, 0x11, 0x23, \ + 0xAC, 0xD3, 0xA7, 0x29, 0x90, 0x1D, 0x1A, 0x71, \ + 0x87, 0x47, 0x00, 0x13, 0x31, 0x07, 0xEC, 0x50 +#define EC_PARAM_brainpoolP384t1_b \ + 0x7F, 0x51, 0x9E, 0xAD, 0xA7, 0xBD, 0xA8, 0x1B, \ + 0xD8, 0x26, 0xDB, 0xA6, 0x47, 0x91, 0x0F, 0x8C, \ + 0x4B, 0x93, 0x46, 0xED, 0x8C, 0xCD, 0xC6, 0x4E, \ + 0x4B, 0x1A, 0xBD, 0x11, 0x75, 0x6D, 0xCE, 0x1D, \ + 0x20, 0x74, 0xAA, 0x26, 0x3B, 0x88, 0x80, 0x5C, \ + 0xED, 0x70, 0x35, 0x5A, 0x33, 0xB4, 0x71, 0xEE +#define EC_PARAM_brainpoolP384t1_x \ + 0x18, 0xDE, 0x98, 0xB0, 0x2D, 0xB9, 0xA3, 0x06, \ + 0xF2, 0xAF, 0xCD, 0x72, 0x35, 0xF7, 0x2A, 0x81, \ + 0x9B, 0x80, 0xAB, 0x12, 0xEB, 0xD6, 0x53, 0x17, \ + 0x24, 0x76, 0xFE, 0xCD, 0x46, 0x2A, 0xAB, 0xFF, \ + 0xC4, 0xFF, 0x19, 0x1B, 0x94, 0x6A, 0x5F, 0x54, \ + 0xD8, 0xD0, 0xAA, 0x2F, 0x41, 0x88, 0x08, 0xCC +#define EC_PARAM_brainpoolP384t1_y \ + 0x25, 0xAB, 0x05, 0x69, 0x62, 0xD3, 0x06, 0x51, \ + 0xA1, 0x14, 0xAF, 0xD2, 0x75, 0x5A, 0xD3, 0x36, \ + 0x74, 0x7F, 0x93, 0x47, 0x5B, 0x7A, 0x1F, 0xCA, \ + 0x3B, 0x88, 0xF2, 0xB6, 0xA2, 0x08, 0xCC, 0xFE, \ + 0x46, 0x94, 0x08, 0x58, 0x4D, 0xC2, 0xB2, 0x91, \ + 0x26, 0x75, 0xBF, 0x5B, 0x9E, 0x58, 0x29, 0x28 +#define EC_PARAM_brainpoolP384t1_order \ + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, \ + 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, \ + 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB3, \ + 0x1F, 0x16, 0x6E, 0x6C, 0xAC, 0x04, 0x25, 0xA7, \ + 0xCF, 0x3A, 0xB6, 0xAF, 0x6B, 0x7F, 0xC3, 0x10, \ + 0x3B, 0x88, 0x32, 0x02, 0xE9, 0x04, 0x65, 0x65 +#endif + +#if 1 +/* brainpoolP512r1 : RFC 5639 curve over a 512 bit prime field */ +#define EC_PARAM_brainpoolP512r1_prime \ + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, \ + 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, \ + 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, \ + 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x71, \ + 0x7D, 0x4D, 0x9B, 0x00, 0x9B, 0xC6, 0x68, 0x42, \ + 0xAE, 0xCD, 0xA1, 0x2A, 0xE6, 0xA3, 0x80, 0xE6, \ + 0x28, 0x81, 0xFF, 0x2F, 0x2D, 0x82, 0xC6, 0x85, \ + 0x28, 0xAA, 0x60, 0x56, 0x58, 0x3A, 0x48, 0xF3 +#define EC_PARAM_brainpoolP512r1_a \ + 0x78, 0x30, 0xA3, 0x31, 0x8B, 0x60, 0x3B, 0x89, \ + 0xE2, 0x32, 0x71, 0x45, 0xAC, 0x23, 0x4C, 0xC5, \ + 0x94, 0xCB, 0xDD, 0x8D, 0x3D, 0xF9, 0x16, 0x10, \ + 0xA8, 0x34, 0x41, 0xCA, 0xEA, 0x98, 0x63, 0xBC, \ + 0x2D, 0xED, 0x5D, 0x5A, 0xA8, 0x25, 0x3A, 0xA1, \ + 0x0A, 0x2E, 0xF1, 0xC9, 0x8B, 0x9A, 0xC8, 0xB5, \ + 0x7F, 0x11, 0x17, 0xA7, 0x2B, 0xF2, 0xC7, 0xB9, \ + 0xE7, 0xC1, 0xAC, 0x4D, 0x77, 0xFC, 0x94, 0xCA +#define EC_PARAM_brainpoolP512r1_b \ + 0x3D, 0xF9, 0x16, 0x10, 0xA8, 0x34, 0x41, 0xCA, \ + 0xEA, 0x98, 0x63, 0xBC, 0x2D, 0xED, 0x5D, 0x5A, \ + 0xA8, 0x25, 0x3A, 0xA1, 0x0A, 0x2E, 0xF1, 0xC9, \ + 0x8B, 0x9A, 0xC8, 0xB5, 0x7F, 0x11, 0x17, 0xA7, \ + 0x2B, 0xF2, 0xC7, 0xB9, 0xE7, 0xC1, 0xAC, 0x4D, \ + 0x77, 0xFC, 0x94, 0xCA, 0xDC, 0x08, 0x3E, 0x67, \ + 0x98, 0x40, 0x50, 0xB7, 0x5E, 0xBA, 0xE5, 0xDD, \ + 0x28, 0x09, 0xBD, 0x63, 0x80, 0x16, 0xF7, 0x23 +#define EC_PARAM_brainpoolP512r1_x \ + 0x81, 0xAE, 0xE4, 0xBD, 0xD8, 0x2E, 0xD9, 0x64, \ + 0x5A, 0x21, 0x32, 0x2E, 0x9C, 0x4C, 0x6A, 0x93, \ + 0x85, 0xED, 0x9F, 0x70, 0xB5, 0xD9, 0x16, 0xC1, \ + 0xB4, 0x3B, 0x62, 0xEE, 0xF4, 0xD0, 0x09, 0x8E, \ + 0xFF, 0x3B, 0x1F, 0x78, 0xE2, 0xD0, 0xD4, 0x8D, \ + 0x50, 0xD1, 0x68, 0x7B, 0x93, 0xB9, 0x7D, 0x5F, \ + 0x7C, 0x6D, 0x50, 0x47, 0x40, 0x6A, 0x5E, 0x68, \ + 0x8B, 0x35, 0x22, 0x09, 0xBC, 0xB9, 0xF8, 0x22 +#define EC_PARAM_brainpoolP512r1_y \ + 0x7D, 0xDE, 0x38, 0x5D, 0x56, 0x63, 0x32, 0xEC, \ + 0xC0, 0xEA, 0xBF, 0xA9, 0xCF, 0x78, 0x22, 0xFD, \ + 0xF2, 0x09, 0xF7, 0x00, 0x24, 0xA5, 0x7B, 0x1A, \ + 0xA0, 0x00, 0xC5, 0x5B, 0x88, 0x1F, 0x81, 0x11, \ + 0xB2, 0xDC, 0xDE, 0x49, 0x4A, 0x5F, 0x48, 0x5E, \ + 0x5B, 0xCA, 0x4B, 0xD8, 0x8A, 0x27, 0x63, 0xAE, \ + 0xD1, 0xCA, 0x2B, 0x2F, 0xA8, 0xF0, 0x54, 0x06, \ + 0x78, 0xCD, 0x1E, 0x0F, 0x3A, 0xD8, 0x08, 0x92 +#define EC_PARAM_brainpoolP512r1_order \ + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, \ + 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, \ + 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, \ + 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x70, \ + 0x55, 0x3E, 0x5C, 0x41, 0x4C, 0xA9, 0x26, 0x19, \ + 0x41, 0x86, 0x61, 0x19, 0x7F, 0xAC, 0x10, 0x47, \ + 0x1D, 0xB1, 0xD3, 0x81, 0x08, 0x5D, 0xDA, 0xDD, \ + 0xB5, 0x87, 0x96, 0x82, 0x9C, 0xA9, 0x00, 0x69 +#endif + +#if 1 +/* brainpoolP512t1 : RFC 5639 curve over a 512 bit prime field */ +#define EC_PARAM_brainpoolP512t1_prime \ + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, \ + 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, \ + 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, \ + 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x71, \ + 0x7D, 0x4D, 0x9B, 0x00, 0x9B, 0xC6, 0x68, 0x42, \ + 0xAE, 0xCD, 0xA1, 0x2A, 0xE6, 0xA3, 0x80, 0xE6, \ + 0x28, 0x81, 0xFF, 0x2F, 0x2D, 0x82, 0xC6, 0x85, \ + 0x28, 0xAA, 0x60, 0x56, 0x58, 0x3A, 0x48, 0xF3 +#define EC_PARAM_brainpoolP512t1_a \ + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, \ + 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, \ + 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, \ + 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x71, \ + 0x7D, 0x4D, 0x9B, 0x00, 0x9B, 0xC6, 0x68, 0x42, \ + 0xAE, 0xCD, 0xA1, 0x2A, 0xE6, 0xA3, 0x80, 0xE6, \ + 0x28, 0x81, 0xFF, 0x2F, 0x2D, 0x82, 0xC6, 0x85, \ + 0x28, 0xAA, 0x60, 0x56, 0x58, 0x3A, 0x48, 0xF0 +#define EC_PARAM_brainpoolP512t1_b \ + 0x7C, 0xBB, 0xBC, 0xF9, 0x44, 0x1C, 0xFA, 0xB7, \ + 0x6E, 0x18, 0x90, 0xE4, 0x68, 0x84, 0xEA, 0xE3, \ + 0x21, 0xF7, 0x0C, 0x0B, 0xCB, 0x49, 0x81, 0x52, \ + 0x78, 0x97, 0x50, 0x4B, 0xEC, 0x3E, 0x36, 0xA6, \ + 0x2B, 0xCD, 0xFA, 0x23, 0x04, 0x97, 0x65, 0x40, \ + 0xF6, 0x45, 0x00, 0x85, 0xF2, 0xDA, 0xE1, 0x45, \ + 0xC2, 0x25, 0x53, 0xB4, 0x65, 0x76, 0x36, 0x89, \ + 0x18, 0x0E, 0xA2, 0x57, 0x18, 0x67, 0x42, 0x3E +#define EC_PARAM_brainpoolP512t1_x \ + 0x64, 0x0E, 0xCE, 0x5C, 0x12, 0x78, 0x87, 0x17, \ + 0xB9, 0xC1, 0xBA, 0x06, 0xCB, 0xC2, 0xA6, 0xFE, \ + 0xBA, 0x85, 0x84, 0x24, 0x58, 0xC5, 0x6D, 0xDE, \ + 0x9D, 0xB1, 0x75, 0x8D, 0x39, 0xC0, 0x31, 0x3D, \ + 0x82, 0xBA, 0x51, 0x73, 0x5C, 0xDB, 0x3E, 0xA4, \ + 0x99, 0xAA, 0x77, 0xA7, 0xD6, 0x94, 0x3A, 0x64, \ + 0xF7, 0xA3, 0xF2, 0x5F, 0xE2, 0x6F, 0x06, 0xB5, \ + 0x1B, 0xAA, 0x26, 0x96, 0xFA, 0x90, 0x35, 0xDA +#define EC_PARAM_brainpoolP512t1_y \ + 0x5B, 0x53, 0x4B, 0xD5, 0x95, 0xF5, 0xAF, 0x0F, \ + 0xA2, 0xC8, 0x92, 0x37, 0x6C, 0x84, 0xAC, 0xE1, \ + 0xBB, 0x4E, 0x30, 0x19, 0xB7, 0x16, 0x34, 0xC0, \ + 0x11, 0x31, 0x15, 0x9C, 0xAE, 0x03, 0xCE, 0xE9, \ + 0xD9, 0x93, 0x21, 0x84, 0xBE, 0xEF, 0x21, 0x6B, \ + 0xD7, 0x1D, 0xF2, 0xDA, 0xDF, 0x86, 0xA6, 0x27, \ + 0x30, 0x6E, 0xCF, 0xF9, 0x6D, 0xBB, 0x8B, 0xAC, \ + 0xE1, 0x98, 0xB6, 0x1E, 0x00, 0xF8, 0xB3, 0x32 +#define EC_PARAM_brainpoolP512t1_order \ + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, \ + 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, \ + 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, \ + 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x70, \ + 0x55, 0x3E, 0x5C, 0x41, 0x4C, 0xA9, 0x26, 0x19, \ + 0x41, 0x86, 0x61, 0x19, 0x7F, 0xAC, 0x10, 0x47, \ + 0x1D, 0xB1, 0xD3, 0x81, 0x08, 0x5D, 0xDA, 0xDD, \ + 0xB5, 0x87, 0x96, 0x82, 0x9C, 0xA9, 0x00, 0x69 +#endif + +#if 1 +/* TPM_BM_P256 : TPM_BM_P256 curve over a 256 bit */ +#define EC_PARAM_tpm_bm_p256_prime \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xF0, 0xCD, \ + 0x46, 0xE5, 0xF2, 0x5E, 0xEE, 0x71, 0xA4, 0x9F, \ + 0x0C, 0xDC, 0x65, 0xFB, 0x12, 0x98, 0x0A, 0x82, \ + 0xD3, 0x29, 0x2D, 0xDB, 0xAE, 0xD3, 0x30, 0x13 +#define EC_PARAM_tpm_bm_p256_a \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +#define EC_PARAM_tpm_bm_p256_b \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 +#define EC_PARAM_tpm_bm_p256_x \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +#define EC_PARAM_tpm_bm_p256_y \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 +#define EC_PARAM_tpm_bm_p256_order \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xF0, 0xCD, \ + 0x46, 0xE5, 0xF2, 0x5E, 0xEE, 0x71, 0xA4, 0x9E, \ + 0x0C, 0xDC, 0x65, 0xFB, 0x12, 0x99, 0x92, 0x1A, \ + 0xF6, 0x2D, 0x53, 0x6C, 0xD1, 0x0B, 0x50, 0x0D +#endif + +/* clang-format on */ +#endif /* SE05X_ECC_CURVES_LIST_H_INC */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h new file mode 100644 index 00000000000..cb0191c9180 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h @@ -0,0 +1,1030 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +/** @file */ + +#ifndef SE05x_ENUMS_H +#define SE05x_ENUMS_H + +#include + + +/* + more or less machine Generated */ + +/** Reserved idendntifiers of the Applet */ +typedef enum +{ + /** Invalid */ + kSE05x_AppletResID_NA = 0, + /** An authentication object which allows the user to switch + * LockState of the applet. The LockState defines whether the + * applet is transport locked or not. */ + kSE05x_AppletResID_TRANSPORT = 0x7FFF0200, + /** A device unique NIST P-256 key pair which contains SK.SE.ECKA + * and PK.SE.ECKA in ECKey session context. */ + kSE05x_AppletResID_KP_ECKEY_USER = 0x7FFF0201, + /** A device unique NIST P-256 key pair which contains SK.SE.ECKA + * and PK.SE.ECKA in ECKey session context; A constant card + * challenge (all zeroes) is applicable. */ + kSE05x_AppletResID_KP_ECKEY_IMPORT = 0x7FFF0202, + /* Reserved Key @ location 0x7FFF0203 */ + /** An authentication object which allows the user to change the + applet variant. */ + kSE05x_AppletResID_FEATURE = 0x7FFF0204, + /** An authentication object which allows the user to delete all + objects, except trust provisioned by NXP objects. */ + kSE05x_AppletResID_FACTORY_RESET = 0x7FFF0205, + /** A BinaryFile Secure Object which holds the device unique + * ID. This file cannot be overwritten or deleted. */ + kSE05x_AppletResID_UNIQUE_ID = 0x7FFF0206, + /** An authentication object which allows the user to change the + * platform SCP requirements, i.e. make platform SCP mandatory or + * not, using SetPlatformSCPRequest. Mandatory means full security, + * i.e. command & response MAC and encryption. Only SCP03 will be + * sufficient. */ + kSE05x_AppletResID_PLATFORM_SCP = 0x7FFF0207, + /** An authentication object which grants access to the I2C master + * feature. If the credential is not present, access to I2C master + * is allowed in general. Otherwise, a session using this + * credential shall be established and I2CM commands shall be sent + * within this session. */ + kSE05x_AppletResID_I2CM_ACCESS = 0x7FFF0208, + /** An authentication object which grants access to the + * SetLockState command */ + kSE05x_AppletResID_RESTRICT = 0x7FFF020A, + +} SE05x_AppletResID_t; + +/** Mapping of 2 byte return code */ +typedef enum +{ + /** Invalid */ + kSE05x_SW12_NA = 0, + /** No Error */ + kSE05x_SW12_NO_ERROR = 0x9000, + /** Conditions not satisfied */ + kSE05x_SW12_CONDITIONS_NOT_SATISFIED = 0x6985, + /** Security status not satisfied. */ + kSE05x_SW12_SECURITY_STATUS = 0x6982, + /** Wrong data provided. */ + kSE05x_SW12_WRONG_DATA = 0x6A80, + /** Data invalid - policy set invalid for the given object */ + kSE05x_SW12_DATA_INVALID = 0x6984, + /** Command not allowed - access denied based on object policy */ + kSE05x_SW12_COMMAND_NOT_ALLOWED = 0x6986, +} SE05x_SW12_t; + +/** Values for INS in ISO7816 APDU */ +typedef enum +{ + /** Invalid */ + kSE05x_INS_NA = 0, + /** 3 MSBit for instruction characteristics. */ + kSE05x_INS_MASK_INS_CHAR = 0xE0, + /** 5 LSBit for instruction */ + kSE05x_INS_MASK_INSTRUCTION = 0x1F, + + /** Mask for transient object creation, can only be combined with INS_WRITE. */ + kSE05x_INS_TRANSIENT = 0x80, + /** Mask for authentication object creation, can only be combined with INS_WRITE */ + kSE05x_INS_AUTH_OBJECT = 0x40, + /** Mask for getting attestation data. */ + kSE05x_INS_ATTEST = 0x20, + + /** Write or create a persistent object. */ + kSE05x_INS_WRITE = 0x01, + /** Read the object */ + kSE05x_INS_READ = 0x02, + /** Perform Security Operation */ + kSE05x_INS_CRYPTO = 0x03, + /** General operation */ + kSE05x_INS_MGMT = 0x04, + /** Process session command */ + kSE05x_INS_PROCESS = 0x05, +} SE05x_INS_t; + +/** Values for P1 in ISO7816 APDU */ +typedef enum +{ + /** Invalid */ + kSE05x_P1_NA = 0, + /** Highest bit not used */ + kSE05x_P1_UNUSED = 0x80, + /** 2 MSBit for key type */ + kSE05x_P1_MASK_KEY_TYPE = 0x60, + /** 5 LSBit for credential type */ + kSE05x_P1_MASK_CRED_TYPE = 0x1F, + + /** Key pair (private key + public key) */ + kSE05x_P1_KEY_PAIR = 0x60, + /** Private key */ + kSE05x_P1_PRIVATE = 0x40, + /** Public key */ + kSE05x_P1_PUBLIC = 0x20, + + kSE05x_P1_DEFAULT = 0x00, + kSE05x_P1_EC = 0x01, + kSE05x_P1_RSA = 0x02, + kSE05x_P1_AES = 0x03, + kSE05x_P1_DES = 0x04, + kSE05x_P1_HMAC = 0x05, + kSE05x_P1_BINARY = 0x06, + kSE05x_P1_UserID = 0x07, + kSE05x_P1_COUNTER = 0x08, + kSE05x_P1_PCR = 0x09, + kSE05x_P1_CURVE = 0x0B, + kSE05x_P1_SIGNATURE = 0x0C, + kSE05x_P1_MAC = 0x0D, + kSE05x_P1_CIPHER = 0x0E, + kSE05x_P1_TLS = 0x0F, + kSE05x_P1_CRYPTO_OBJ = 0x10, +#if SSS_HAVE_SE05X_VER_GTE_06_00 + /** Applet >= 4.4 */ + kSE05x_P1_AEAD = 0x11, + /** Applet >= 4.4 */ + kSE05x_P1_AEAD_SP800_38D = 0x12, +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ +} SE05x_P1_t; + +/** Values for P2 in ISO7816 APDU */ +typedef enum +{ + /** Invalid */ + kSE05x_P2_DEFAULT = 0x00, + kSE05x_P2_GENERATE = 0x03, + kSE05x_P2_CREATE = 0x04, + kSE05x_P2_SIZE = 0x07, + kSE05x_P2_SIGN = 0x09, + kSE05x_P2_VERIFY = 0x0A, + kSE05x_P2_INIT = 0x0B, + kSE05x_P2_UPDATE = 0x0C, + kSE05x_P2_FINAL = 0x0D, + kSE05x_P2_ONESHOT = 0x0E, + kSE05x_P2_DH = 0x0F, + kSE05x_P2_DIVERSIFY = 0x10, + // kSE05x_P2_AUTH_PART1 = 0x11, + kSE05x_P2_AUTH_FIRST_PART2 = 0x12, + kSE05x_P2_AUTH_NONFIRST_PART2 = 0x13, + kSE05x_P2_DUMP_KEY = 0x14, + kSE05x_P2_CHANGE_KEY_PART1 = 0x15, + kSE05x_P2_CHANGE_KEY_PART2 = 0x16, + kSE05x_P2_KILL_AUTH = 0x17, + kSE05x_P2_IMPORT = 0x18, + kSE05x_P2_EXPORT = 0x19, + kSE05x_P2_SESSION_CREATE = 0x1B, + kSE05x_P2_SESSION_CLOSE = 0x1C, + kSE05x_P2_SESSION_REFRESH = 0x1E, + kSE05x_P2_SESSION_POLICY = 0x1F, + kSE05x_P2_VERSION = 0x20, + kSE05x_P2_VERSION_EXT = 0x21, + kSE05x_P2_MEMORY = 0x22, + kSE05x_P2_LIST = 0x25, + kSE05x_P2_TYPE = 0x26, + kSE05x_P2_EXIST = 0x27, + kSE05x_P2_DELETE_OBJECT = 0x28, + kSE05x_P2_DELETE_ALL = 0x2A, + kSE05x_P2_SESSION_UserID = 0x2C, + kSE05x_P2_HKDF = 0x2D, + kSE05x_P2_PBKDF = 0x2E, + /* Applet >= 4.4 */ + kSE05x_P2_HKDF_EXPAND_ONLY = 0x2F, + kSE05x_P2_I2CM = 0x30, + kSE05x_P2_I2CM_ATTESTED = 0x31, + kSE05x_P2_MAC = 0x32, + kSE05x_P2_UNLOCK_CHALLENGE = 0x33, + kSE05x_P2_CURVE_LIST = 0x34, + kSE05x_P2_SIGN_ECDAA = 0x35, + kSE05x_P2_ID = 0x36, + kSE05x_P2_ENCRYPT_ONESHOT = 0x37, + kSE05x_P2_DECRYPT_ONESHOT = 0x38, + kSE05x_P2_ATTEST = 0x3A, + kSE05x_P2_ATTRIBUTES = 0x3B, + kSE05x_P2_CPLC = 0x3C, + kSE05x_P2_TIME = 0x3D, + kSE05x_P2_TRANSPORT = 0x3E, + kSE05x_P2_VARIANT = 0x3F, + kSE05x_P2_PARAM = 0x40, + kSE05x_P2_DELETE_CURVE = 0x41, + kSE05x_P2_ENCRYPT = 0x42, + kSE05x_P2_DECRYPT = 0x43, + kSE05x_P2_VALIDATE = 0x44, + kSE05x_P2_GENERATE_ONESHOT = 0x45, + kSE05x_P2_VALIDATE_ONESHOT = 0x46, + kSE05x_P2_CRYPTO_LIST = 0x47, + kSE05x_P2_RANDOM = 0x49, + kSE05x_P2_TLS_PMS = 0x4A, + kSE05x_P2_TLS_PRF_CLI_HELLO = 0x4B, + kSE05x_P2_TLS_PRF_SRV_HELLO = 0x4C, + kSE05x_P2_TLS_PRF_CLI_RND = 0x4D, + kSE05x_P2_TLS_PRF_SRV_RND = 0x4E, + kSE05x_P2_TLS_PRF_BOTH = 0x5A, + kSE05x_P2_RAW = 0x4F, + kSE05x_P2_IMPORT_EXT = 0x51, + kSE05x_P2_SCP = 0x52, + kSE05x_P2_AUTH_FIRST_PART1 = 0x53, + kSE05x_P2_AUTH_NONFIRST_PART1 = 0x54, +#if SSS_HAVE_SE05X_VER_GTE_06_00 + kSE05x_P2_CM_COMMAND = 0x55, + kSE05x_P2_MODE_OF_OPERATION = 0x56, + kSE05x_P2_RESTRICT = 0x57, + kSE05x_P2_SANITY = 0x58, + kSE05x_P2_DH_REVERSE = 0x59, + kSE05x_P2_READ_STATE = 0x5B +#endif +} SE05x_P2_t; + + +/** Data for available memory */ +typedef enum +{ + /** Invalid */ + kSE05x_MemoryType_NA = 0, + /** Persistent memory */ + kSE05x_MemoryType_PERSISTENT = 0x01, + /** Transient memory, clear on reset */ + kSE05x_MemoryType_TRANSIENT_RESET = 0x02, + /** Transient memory, clear on deselect */ + kSE05x_MemoryType_TRANSIENT_DESELECT = 0x03, +} SE05x_MemoryType_t; + +/** Where was this object originated */ +typedef enum +{ + /** Invalid */ + kSE05x_Origin_NA = 0, + /** Generated outside the module. */ + kSE05x_Origin_EXTERNAL = 0x01, + /** Generated inside the module. */ + kSE05x_Origin_INTERNAL = 0x02, + /** Trust provisioned by NXP */ + kSE05x_Origin_PROVISIONED = 0x03, +} SE05x_Origin_t; + +/** Different TAG Values to talk to SE05X IoT Applet */ +typedef enum +{ + /** Invalid */ + kSE05x_TAG_NA = 0, + kSE05x_TAG_SESSION_ID = 0x10, + kSE05x_TAG_POLICY = 0x11, + kSE05x_TAG_MAX_ATTEMPTS = 0x12, + kSE05x_TAG_IMPORT_AUTH_DATA = 0x13, + kSE05x_TAG_IMPORT_AUTH_KEY_ID = 0x14, + kSE05x_TAG_POLICY_CHECK = 0x15, + kSE05x_TAG_1 = 0x41, + kSE05x_TAG_2 = 0x42, + kSE05x_TAG_3 = 0x43, + kSE05x_TAG_4 = 0x44, + kSE05x_TAG_5 = 0x45, + kSE05x_TAG_6 = 0x46, + kSE05x_TAG_7 = 0x47, + kSE05x_TAG_8 = 0x48, + kSE05x_TAG_9 = 0x49, + kSE05x_TAG_10 = 0x4A, + kSE05x_TAG_11 = 0x4B, + kSE05x_GP_TAG_CONTRL_REF_PARM = 0xA6, + kSE05x_GP_TAG_AID = 0x4F, + kSE05x_GP_TAG_KEY_TYPE = 0x80, + kSE05x_GP_TAG_KEY_LEN = 0x81, + kSE05x_GP_TAG_GET_DATA = 0x83, + kSE05x_GP_TAG_DR_SE = 0x85, + kSE05x_GP_TAG_RECEIPT = 0x86, + kSE05x_GP_TAG_SCP_PARMS = 0x90, +} SE05x_TAG_t; + +#ifndef __DOXYGEN__ +#define kSE05x_TAG_GP_CONTRL_REF_PARM kSE05x_GP_TAG_CONTRL_REF_PARM +#endif + +/** Different signature algorithms for EC */ +typedef enum +{ + /** Invalid */ + kSE05x_ECSignatureAlgo_NA = 0, + /** NOT SUPPORTED */ + kSE05x_ECSignatureAlgo_PLAIN = 0x09, + kSE05x_ECSignatureAlgo_SHA = 0x11, + kSE05x_ECSignatureAlgo_SHA_224 = 0x25, + kSE05x_ECSignatureAlgo_SHA_256 = 0x21, + kSE05x_ECSignatureAlgo_SHA_384 = 0x22, + kSE05x_ECSignatureAlgo_SHA_512 = 0x26, +} SE05x_ECSignatureAlgo_t; + +/** Different signature algorithms for ED */ +typedef enum +{ + /** Invalid */ + kSE05x_EDSignatureAlgo_NA = 0, + /** Message input must be plain Data. Pure EDDSA algorithm */ + kSE05x_EDSignatureAlgo_ED25519PURE_SHA_512 = 0xA3, +} SE05x_EDSignatureAlgo_t; + +/** Different signature algorithms for ECDAA */ +typedef enum +{ + /** Invalid */ + kSE05x_ECDAASignatureAlgo_NA = 0, + /** Message input must be pre-hashed (using SHA256) */ + kSE05x_ECDAASignatureAlgo_ECDAA = 0xF4, +} SE05x_ECDAASignatureAlgo_t; + +/** Different signature algorithms for RSA */ +typedef enum +{ + /** Invalid */ + kSE05x_RSASignatureAlgo_NA = 0, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignatureAlgo_SHA1_PKCS1_PSS = 0x15, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignatureAlgo_SHA224_PKCS1_PSS = 0x2B, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignatureAlgo_SHA256_PKCS1_PSS = 0x2C, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignatureAlgo_SHA384_PKCS1_PSS = 0x2D, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignatureAlgo_SHA512_PKCS1_PSS = 0x2E, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignatureAlgo_SHA1_PKCS1 = 0x0A, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignatureAlgo_SHA_224_PKCS1 = 0x27, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignatureAlgo_SHA_256_PKCS1 = 0x28, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignatureAlgo_SHA_384_PKCS1 = 0x29, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignatureAlgo_SHA_512_PKCS1 = 0x2A, +} SE05x_RSASignatureAlgo_t; + +/** Different encryption/decryption algorithms for RSA */ +typedef enum +{ + /** Invalid */ + kSE05x_RSAEncryptionAlgo_NA = 0, + /** Plain RSA, padding required on host. */ + kSE05x_RSAEncryptionAlgo_NO_PAD = 0x0C, + /** RFC8017: RSAES-PKCS1-v1_5 */ + kSE05x_RSAEncryptionAlgo_PKCS1 = 0x0A, + /** RFC8017: RSAES-OAEP */ + kSE05x_RSAEncryptionAlgo_PKCS1_OAEP = 0x0F, +} SE05x_RSAEncryptionAlgo_t; + +/** Size of RSA Key Objects */ +typedef enum +{ + /** Invalid */ + kSE05x_RSABitLength_NA = 0, + kSE05x_RSABitLength_512 = 512, + kSE05x_RSABitLength_1024 = 1024, + kSE05x_RSABitLength_1152 = 1152, + kSE05x_RSABitLength_2048 = 2048, + kSE05x_RSABitLength_3072 = 3072, + kSE05x_RSABitLength_4096 = 4096, +} SE05x_RSABitLength_t; + +/** Part of the RSA Key Objects */ +typedef enum +{ + /** Invalid */ + kSE05x_RSAKeyComponent_NA = 0xFF, + /** Modulus */ + kSE05x_RSAKeyComponent_MOD = 0x00, + /** Public key exponent */ + kSE05x_RSAKeyComponent_PUB_EXP = 0x01, + /** Private key exponent */ + kSE05x_RSAKeyComponent_PRIV_EXP = 0x02, + /** CRT component p */ + kSE05x_RSAKeyComponent_P = 0x03, + /** CRT component q */ + kSE05x_RSAKeyComponent_Q = 0x04, + /** CRT component dp */ + kSE05x_RSAKeyComponent_DP = 0x05, + /** CRT component dq */ + kSE05x_RSAKeyComponent_DQ = 0x06, + /** CRT component q_inv */ + kSE05x_RSAKeyComponent_INVQ = 0x07, +} SE05x_RSAKeyComponent_t; + +/** Hashing/Digest algorithms */ +typedef enum +{ + /** Invalid */ + kSE05x_DigestMode_NA = 0, + kSE05x_DigestMode_NO_HASH = 0x00, + kSE05x_DigestMode_SHA = 0x01, + /** Not supported */ + kSE05x_DigestMode_SHA224 = 0x07, + kSE05x_DigestMode_SHA256 = 0x04, + kSE05x_DigestMode_SHA384 = 0x05, + kSE05x_DigestMode_SHA512 = 0x06, +} SE05x_DigestMode_t; + +/** HMAC/CMAC Algorithms */ +typedef enum +{ + /** Invalid */ + kSE05x_MACAlgo_NA = 0, + kSE05x_MACAlgo_HMAC_SHA1 = 0x18, + kSE05x_MACAlgo_HMAC_SHA256 = 0x19, + kSE05x_MACAlgo_HMAC_SHA384 = 0x1A, + kSE05x_MACAlgo_HMAC_SHA512 = 0x1B, + kSE05x_MACAlgo_CMAC_128 = 0x31, +} SE05x_MACAlgo_t; + +/** AEAD Algorithms */ +typedef enum +{ + /** Invalid */ + kSE05x_AeadAlgo_NA = 0, + kSE05x_AeadGCMAlgo = 0xB0, + kSE05x_AeadGCM_IVAlgo = 0xF3, + kSE05x_AeadCCMAlgo = 0xF4, +} SE05x_AeadAlgo_t; + +/** HKDF Mode */ +typedef enum +{ + /** Invalid */ + kSE05x_HkdfMode_NA = 0x00, + kSE05x_HkdfMode_ExtractExpand = 0x01, + kSE05x_HkdfMode_ExpandOnly = 0x02, +} SE05x_HkdfMode_t; + +/** ECC Curve Identifiers */ +typedef enum +{ + /** Invalid */ + kSE05x_ECCurve_NA = 0x00, + kSE05x_ECCurve_NIST_P192 = 0x01, + kSE05x_ECCurve_NIST_P224 = 0x02, + kSE05x_ECCurve_NIST_P256 = 0x03, + kSE05x_ECCurve_NIST_P384 = 0x04, + kSE05x_ECCurve_NIST_P521 = 0x05, + kSE05x_ECCurve_Brainpool160 = 0x06, + kSE05x_ECCurve_Brainpool192 = 0x07, + kSE05x_ECCurve_Brainpool224 = 0x08, + kSE05x_ECCurve_Brainpool256 = 0x09, + kSE05x_ECCurve_Brainpool320 = 0x0A, + kSE05x_ECCurve_Brainpool384 = 0x0B, + kSE05x_ECCurve_Brainpool512 = 0x0C, + kSE05x_ECCurve_Secp160k1 = 0x0D, + kSE05x_ECCurve_Secp192k1 = 0x0E, + kSE05x_ECCurve_Secp224k1 = 0x0F, + kSE05x_ECCurve_Secp256k1 = 0x10, + kSE05x_ECCurve_TPM_ECC_BN_P256 = 0x11, + /** Not Weierstrass */ + kSE05x_ECCurve_ECC_ED_25519 = 0x40, + kSE05x_ECCurve_ECC_MONT_DH_25519 = 0x41, + /** Not Weierstrass */ + kSE05x_ECCurve_ECC_MONT_DH_448 = 0x43, +} SE05x_ECCurve_t; + +#ifndef __DOXYGEN__ + +/** Same as kSE05x_ECCurve_TPM_ECC_BN_P256 */ +#define kSE05x_ECCurve_RESERVED_ID_ECC_ED_25519 kSE05x_ECCurve_ECC_ED_25519 +#define kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_25519 kSE05x_ECCurve_ECC_MONT_DH_25519 +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#define kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448 kSE05x_ECCurve_ECC_MONT_DH_448 +#endif +#define kSE05x_ECCurve_Total_Weierstrass_Curves kSE05x_ECCurve_TPM_ECC_BN_P256 +#endif + +/** Parameters while setting the curve */ +typedef enum +{ /** Invalid */ + kSE05x_ECCurveParam_NA = 0, + kSE05x_ECCurveParam_PARAM_A = 0x01, + kSE05x_ECCurveParam_PARAM_B = 0x02, + kSE05x_ECCurveParam_PARAM_G = 0x04, + kSE05x_ECCurveParam_PARAM_N = 0x08, + kSE05x_ECCurveParam_PARAM_PRIME = 0x10, +} SE05x_ECCurveParam_t; + +/** Symmetric cipher modes */ +typedef enum +{ + /** Invalid */ + kSE05x_CipherMode_NA = 0, + /** Typically using DESKey identifiers */ + kSE05x_CipherMode_DES_CBC_NOPAD = 0x01, + /** Typically using DESKey identifiers */ + kSE05x_CipherMode_DES_CBC_ISO9797_M1 = 0x02, + /** Typically using DESKey identifiers */ + kSE05x_CipherMode_DES_CBC_ISO9797_M2 = 0x03, + /** NOT SUPPORTED */ + kSE05x_CipherMode_DES_CBC_PKCS5 = 0x04, + /** Typically using DESKey identifiers */ + kSE05x_CipherMode_DES_ECB_NOPAD = 0x05, + /** NOT SUPPORTED */ + kSE05x_CipherMode_DES_ECB_ISO9797_M1 = 0x06, + /** NOT SUPPORTED */ + kSE05x_CipherMode_DES_ECB_ISO9797_M2 = 0x07, + /** NOT SUPPORTED */ + kSE05x_CipherMode_DES_ECB_PKCS5 = 0x08, + /** Typically using AESKey identifiers */ + kSE05x_CipherMode_AES_ECB_NOPAD = 0x0E, + /** Typically using AESKey identifiers */ + kSE05x_CipherMode_AES_CBC_NOPAD = 0x0D, + /** Typically using AESKey identifiers */ + kSE05x_CipherMode_AES_CBC_ISO9797_M1 = 0x16, + /** Typically using AESKey identifiers */ + kSE05x_CipherMode_AES_CBC_ISO9797_M2 = 0x17, + /** NOT SUPPORTED */ + kSE05x_CipherMode_AES_CBC_PKCS5 = 0x18, + /** Typically using AEAD GCM mode */ + kSE05x_CipherMode_AES_GCM = 0xB0, + /** Typically using AESKey identifiers */ + kSE05x_CipherMode_AES_CTR = 0xF0, + /** Typically using AEAD GCM with internal IV Gen */ + kSE05x_CipherMode_AES_GCM_INT_IV = 0xF3, + /** Typically using AEAD CCM mode */ + kSE05x_CipherMode_AES_CCM = 0xF4, +} SE05x_CipherMode_t; + +/** Features which are available / enabled in the Applet */ +typedef enum { + /** Invalid */ + kSE05x_AppletConfig_NA = 0, + /** Use of curve TPM_ECC_BN_P256 */ + kSE05x_AppletConfig_ECDAA = 0x0001, + /** EC DSA and DH support */ + kSE05x_AppletConfig_ECDSA_ECDH_ECDHE = 0x0002, + /** Use of curve RESERVED_ID_ECC_ED_25519 */ + kSE05x_AppletConfig_EDDSA = 0x0004, + /** Use of curve RESERVED_ID_ECC_MONT_DH_25519 */ + kSE05x_AppletConfig_DH_MONT = 0x0008, + /** Writing HMACKey objects */ + kSE05x_AppletConfig_HMAC = 0x0010, + /** Writing RSAKey objects */ + kSE05x_AppletConfig_RSA_PLAIN = 0x0020, + /** Writing RSAKey objects */ + kSE05x_AppletConfig_RSA_CRT = 0x0040, + /** Writing AESKey objects */ + kSE05x_AppletConfig_AES = 0x0080, + /** Writing DESKey objects */ + kSE05x_AppletConfig_DES = 0x0100, + /** PBKDF2 */ + kSE05x_AppletConfig_PBKDF = 0x0200, + /** TLS Handshake support commands (see 4.16) in APDU Spec*/ + kSE05x_AppletConfig_TLS = 0x0400, + /** Mifare DESFire support (see 4.15) in APDU Spec*/ + kSE05x_AppletConfig_MIFARE = 0x0800, + /** RFU1 */ + kSE05x_AppletConfig_RFU1 = 0x1000, + /** I2C Master support (see 4.17) in APDU Spec*/ + kSE05x_AppletConfig_I2CM = 0x2000, + /** RFU2 */ + kSE05x_AppletConfig_RFU2 = 0x4000, +} SE05x_AppletConfig_t; + +/** Transient / Persistent lock */ +typedef enum +{ + /** Invalid */ + kSE05x_LockIndicator_NA = 0, + kSE05x_LockIndicator_TRANSIENT_LOCK = 0x01, + kSE05x_LockIndicator_PERSISTENT_LOCK = 0x02, +} SE05x_LockIndicator_t; + +/** + * Applet >= 4.4 + * + * See @ref Se05x_API_DisableObjCreation */ +typedef enum +{ + kSE05x_RestrictMode_NA = 0, + kSE05x_RestrictMode_RESTRICT_NEW = 0x01, + kSE05x_RestrictMode_RESTRICT_ALL = 0x02, +} SE05x_RestrictMode_t; + +/** + * Lock the sample (until unlocked ) + */ +typedef enum +{ + /** Invalid */ + kSE05x_LockState_NA = 0, + kSE05x_LockState_LOCKED = 0x01, + // kSE05x_LockState_UNLOCKED = Any except 0x01, +} SE05x_LockState_t; + +/** Cryptographic context for operation */ +typedef enum +{ + /** Invalid */ + kSE05x_CryptoContext_NA = 0, + /** For DigestInit/DigestUpdate/DigestFinal */ + kSE05x_CryptoContext_DIGEST = 0x01, + /** For CipherInit/CipherUpdate/CipherFinal */ + kSE05x_CryptoContext_CIPHER = 0x02, + /** For MACInit/MACUpdate/MACFinal */ + kSE05x_CryptoContext_SIGNATURE = 0x03, + /** For AEADInit/AEADUpdate/AEADFinal */ + kSE05x_CryptoContext_AEAD = 0x04, +} SE05x_CryptoContext_t; + +/** Result of operations */ +typedef enum +{ + /** Invalid */ + kSE05x_Result_NA = 0, + kSE05x_Result_SUCCESS = 0x01, + kSE05x_Result_FAILURE = 0x02, +} SE05x_Result_t; + +/** Whether object is transient or persistent */ +typedef enum +{ + /** Invalid */ + kSE05x_TransientIndicator_NA = 0, + kSE05x_TransientIndicator_PERSISTENT = 0x01, + kSE05x_TransientIndicator_TRANSIENT = 0x02, +} SE05x_TransientIndicator_t; + +/** Whether object attribute is set */ +typedef enum +{ + /** Invalid */ + kSE05x_SetIndicator_NA = 0, + kSE05x_SetIndicator_NOT_SET = 0x01, + kSE05x_SetIndicator_SET = 0x02, +} SE05x_SetIndicator_t; + +/** When there are more entries yet to be fetched from few of the APIs */ +typedef enum +{ + /** Invalid */ + kSE05x_MoreIndicator_NA = 0, + /** No more data available */ + kSE05x_MoreIndicator_NO_MORE = 0x01, + /** More data available */ + kSE05x_MoreIndicator_MORE = 0x02, +} SE05x_MoreIndicator_t; + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +/** Health check */ +typedef enum +{ + /** Invalid */ + kSE05x_HealthCheckMode_NA = 0, + /** Performs all on-demand self-tests. Can only be done when + * the module is in FIPS mode. When the test fails, the chip + * goes into TERMINATED state. */ + kSE05x_HealthCheckMode_FIPS = 0xF906, + /** Performs ROM integrity checks. When the test fails, the chip + * triggers the attack counter and the chip will reset. */ + kSE05x_HealthCheckMode_CODE_SIGNATURE = 0xFE01, + /** Performs flash integrity tests. When the test fails, the chip + * triggers the attack counter and the chip will reset. */ + kSE05x_HealthCheckMode_DYNAMIC_FLASH_INTEGRITY = 0xFD02, + /** Performs tests on the active shield protection of the + * hardware. When the test fails, the chip triggers the attack + * counter and the chip will reset. */ + kSE05x_HealthCheckMode_SHIELDING = 0xFB04, + /** Performs self-tests on hardware sensors and reports the + * status. */ + kSE05x_HealthCheckMode_SENSOR = 0xFA05, + /** Performs self-tests on the hardware registers. When the test + * fails, the chip triggers the attack counter and the chip will + * reset. */ + kSE05x_HealthCheckMode_SFR_CHECK = 0xFC03, +} SE05x_HealthCheckMode_t; +#endif + +/** Mandate platform SCP or not */ +typedef enum +{ + /** Invalid */ + kSE05x_PlatformSCPRequest_NA = 0, + /** Platform SCP is required (full enc & MAC) */ + kSE05x_PlatformSCPRequest_REQUIRED = 0x01, + /** No platform SCP required. */ + kSE05x_PlatformSCPRequest_NOT_REQUIRED = 0x02, +} SE05x_PlatformSCPRequest_t; + +/** Crypto object identifiers */ +typedef enum +{ + /** Invalid */ + kSE05x_CryptoObject_NA = 0, + kSE05x_CryptoObject_DIGEST_SHA, + kSE05x_CryptoObject_DIGEST_SHA224, + kSE05x_CryptoObject_DIGEST_SHA256, + kSE05x_CryptoObject_DIGEST_SHA384, + kSE05x_CryptoObject_DIGEST_SHA512, + kSE05x_CryptoObject_DES_CBC_NOPAD, + kSE05x_CryptoObject_DES_CBC_ISO9797_M1, + kSE05x_CryptoObject_DES_CBC_ISO9797_M2, + kSE05x_CryptoObject_DES_CBC_PKCS5, + kSE05x_CryptoObject_DES_ECB_NOPAD, + kSE05x_CryptoObject_DES_ECB_ISO9797_M1, + kSE05x_CryptoObject_DES_ECB_ISO9797_M2, + kSE05x_CryptoObject_DES_ECB_PKCS5, + kSE05x_CryptoObject_AES_ECB_NOPAD, + kSE05x_CryptoObject_AES_CBC_NOPAD, + kSE05x_CryptoObject_AES_CBC_ISO9797_M1, + kSE05x_CryptoObject_AES_CBC_ISO9797_M2, + kSE05x_CryptoObject_AES_CBC_PKCS5, + kSE05x_CryptoObject_AES_CTR, + kSE05x_CryptoObject_HMAC_SHA1, + kSE05x_CryptoObject_HMAC_SHA256, + kSE05x_CryptoObject_HMAC_SHA384, + kSE05x_CryptoObject_HMAC_SHA512, + kSE05x_CryptoObject_CMAC_128, + kSE05x_CryptoObject_AES_GCM, + kSE05x_CryptoObject_AES_GCM_INT_IV, + kSE05x_CryptoObject_AES_CCM, +} SE05x_CryptoObject_t; + +/** @copydoc SE05x_CryptoObject_t */ +#define SE05x_CryptoObjectID_t SE05x_CryptoObject_t + +/** Maximum number of session supported by SE050 */ +#define SE050_MAX_NUMBER_OF_SESSIONS 2 +/** Maximum number of session supported by SE050 */ +#define SE050_OBJECT_IDENTIFIER_SIZE 4 +/** How many bytes can be used for buffer for I2C Master interface */ +#define SE050_MAX_I2CM_COMMAND_LENGTH 255 +/** + * the maximum APDU payload length will be smaller, depending on which protocol applies, etc. + */ +#define SE050_MAX_APDU_PAYLOAD_LENGTH 892 +//#define SE050_DEFAULT_MAX_ATTEMPTS 10 + +/** 3 MSBit for instruction characteristics. */ +#define SE050_INS_MASK_INS_CHAR 0xE0 +/** 5 LSBit for instruction */ +#define SE050_INS_MASK_INSTRUCTION 0x1F + +/** Type of Object */ +typedef enum +{ + /** */ + kSE05x_SecObjTyp_EC_KEY_PAIR = 0x01, + /** */ + kSE05x_SecObjTyp_EC_PRIV_KEY = 0x02, + /** */ + kSE05x_SecObjTyp_EC_PUB_KEY = 0x03, + /** */ + kSE05x_SecObjTyp_RSA_KEY_PAIR = 0x04, + /** */ + kSE05x_SecObjTyp_RSA_KEY_PAIR_CRT = 0x05, + /** */ + kSE05x_SecObjTyp_RSA_PRIV_KEY = 0x06, + /** */ + kSE05x_SecObjTyp_RSA_PRIV_KEY_CRT = 0x07, + /** */ + kSE05x_SecObjTyp_RSA_PUB_KEY = 0x08, + /** */ + kSE05x_SecObjTyp_AES_KEY = 0x09, + /** */ + kSE05x_SecObjTyp_DES_KEY = 0x0A, + /** */ + kSE05x_SecObjTyp_BINARY_FILE = 0x0B, + /** */ + kSE05x_SecObjTyp_UserID = 0x0C, + /** */ + kSE05x_SecObjTyp_COUNTER = 0x0D, + /** */ + kSE05x_SecObjTyp_PCR = 0x0F, + /** */ + kSE05x_SecObjTyp_CURVE = 0x10, + /** */ + kSE05x_SecObjTyp_HMAC_KEY = 0x11, +} SE05x_SecObjTyp_t; + +/** @copydoc SE05x_SecObjTyp_t */ +typedef SE05x_SecObjTyp_t SE05x_SecureObjectType_t; + +/** Type of memory. Used when we query available free size */ +typedef enum +{ + /** Transient memory, clear on reset */ + kSE05x_MemTyp_TRANSIENT_RESET = 0x01, + /** Transient memory, clear on deselect */ + kSE05x_MemTyp_TRANSIENT_DESELECT = 0x02, + /** Persistent memory */ + kSE05x_MemTyp_PERSISTENT = 0x03, +} SE05x_MemTyp_t; + +/** Algorithms for RSA Signature */ +typedef enum +{ + /** Invalid */ + kSE05x_RSASignAlgo_NA = 0, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignAlgo_SHA1_PKCS1_PSS = 0x15, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignAlgo_SHA224_PKCS1_PSS = 0x2B, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignAlgo_SHA256_PKCS1_PSS = 0x2C, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignAlgo_SHA384_PKCS1_PSS = 0x2D, + /** RFC8017: RSASSA-PSS */ + kSE05x_RSASignAlgo_SHA512_PKCS1_PSS = 0x2E, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignAlgo_SHA_224_PKCS1 = 0x27, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignAlgo_SHA_256_PKCS1 = 0x28, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignAlgo_SHA_384_PKCS1 = 0x29, + /** RFC8017: RSASSA-PKCS1-v1_5 */ + kSE05x_RSASignAlgo_SHA_512_PKCS1 = 0x2A, +} SE05x_RSASignAlgo_t; + +// typedef enum +// { +// /** Plain RSA, padding required on host. */ +// kSE05x_RSAEncrAlgo_NO_PAD = 0x0C, +// * RFC8017: RSAES-PKCS1-v1_5 +// kSE05x_RSAEncrAlgo_PKCS1 = 0x0A, +// /** RFC8017: RSAES-OAEP */ +// kSE05x_RSAEncrAlgo_PKCS1_OAEP = 0x0F, +// } SE05x_RSAEncrAlgo_t; + +/** Public part of RSA Keys */ +typedef enum +{ + kSE05x_RSAPubKeyComp_NA = 0, + kSE05x_RSAPubKeyComp_MOD = kSE05x_RSAKeyComponent_MOD, + kSE05x_RSAPubKeyComp_PUB_EXP = kSE05x_RSAKeyComponent_PUB_EXP, +} SE05x_RSAPubKeyComp_t; + +/** Cyrpto module subtype */ +typedef union { + /** In case it's digest */ + SE05x_DigestMode_t digest; + /** In case it's cipher */ + SE05x_CipherMode_t cipher; + /** In case it's mac */ + SE05x_MACAlgo_t mac; + /** In case it's aead */ + SE05x_AeadAlgo_t aead; + /** Accessing 8 bit value for APDUs */ + uint8_t union_8bit; +} SE05x_CryptoModeSubType_t; + +/** @addtogroup se050_i2cm + * + * @{ + */ +/** @brief I2C Master micro operation */ +typedef enum +{ + kSE05x_TAG_I2CM_Config = 0x01, + kSE05x_TAG_I2CM_Write = 0x03, + kSE05x_TAG_I2CM_Read = 0x04, +} SE05x_I2CM_TAG_t; + +/*! +*@} +*/ /* end of se050_i2cm */ + +/** Whether key is transient of persistent */ +typedef enum +{ + kSE05x_TransientType_Persistent = 0, + kSE05x_TransientType_Transient = kSE05x_INS_TRANSIENT, +} SE05x_TransientType_t; + +/** Part of the asymmetric key */ +typedef enum +{ + kSE05x_KeyPart_NA = kSE05x_P1_DEFAULT, + /** Key pair (private key + public key) */ + kSE05x_KeyPart_Pair = kSE05x_P1_KEY_PAIR, + /** Private key */ + kSE05x_KeyPart_Private = kSE05x_P1_PRIVATE, + /** Public key */ + kSE05x_KeyPart_Public = kSE05x_P1_PUBLIC, +} SE05x_KeyPart_t; + +/** Cipher Operation. + * + * Encrypt or decrypt */ +typedef enum +{ + kSE05x_Cipher_Oper_NA = 0, + kSE05x_Cipher_Oper_Encrypt = kSE05x_P2_ENCRYPT, + kSE05x_Cipher_Oper_Decrypt = kSE05x_P2_DECRYPT, +} SE05x_Cipher_Oper_t; + +/** One Shot operations helper */ +typedef enum +{ + kSE05x_Cipher_Oper_OneShot_NA = 0, + kSE05x_Cipher_Oper_OneShot_Encrypt = kSE05x_P2_ENCRYPT_ONESHOT, + kSE05x_Cipher_Oper_OneShot_Decrypt = kSE05x_P2_DECRYPT_ONESHOT, +} SE05x_Cipher_Oper_OneShot_t; + +/** MAC operations */ +typedef enum +{ + kSE05x_Mac_Oper_NA = 0, + kSE05x_Mac_Oper_Generate = kSE05x_P2_GENERATE, + kSE05x_Mac_Oper_Validate = kSE05x_P2_VALIDATE, +} SE05x_Mac_Oper_t; + +/** In case the read is attested */ +typedef enum +{ + kSE05x_AttestationType_None = 0, + kSE05x_AttestationType_AUTH = kSE05x_INS_AUTH_OBJECT, +} SE05x_AttestationType_t; + +/** Symmetric keys */ +typedef enum +{ + kSE05x_SymmKeyType_NA = 0, + kSE05x_SymmKeyType_AES = kSE05x_P1_AES, + kSE05x_SymmKeyType_DES = kSE05x_P1_DES, + kSE05x_SymmKeyType_HMAC = kSE05x_P1_HMAC, + kSE05x_SymmKeyType_CMAC = kSE05x_P1_AES, +} SE05x_SymmKeyType_t; + +/** @copydoc SE05x_AppletConfig_t */ +typedef SE05x_AppletConfig_t SE05x_Variant_t; + +/** TLS Perform PRF */ +typedef enum +{ + kSE05x_TLS_PRF_NA = 0, + kSE05x_TLS_PRF_CLI_HELLO = kSE05x_P2_TLS_PRF_CLI_HELLO, + kSE05x_TLS_PRF_SRV_HELLO = kSE05x_P2_TLS_PRF_SRV_HELLO, + kSE05x_TLS_PRF_CLI_RND = kSE05x_P2_TLS_PRF_CLI_RND, + kSE05x_TLS_PRF_SRV_RND = kSE05x_P2_TLS_PRF_SRV_RND, + kSE05x_TLS_PRF_BOTH = kSE05x_P2_TLS_PRF_BOTH, +} SE05x_TLSPerformPRFType_t; + +/** Attestation */ +typedef enum +{ + kSE05x_AttestationAlgo_NA = 0, + kSE05x_AttestationAlgo_EC_PLAIN = kSE05x_ECSignatureAlgo_PLAIN, + kSE05x_AttestationAlgo_EC_SHA = kSE05x_ECSignatureAlgo_SHA, + kSE05x_AttestationAlgo_EC_SHA_224 = kSE05x_ECSignatureAlgo_SHA_224, + kSE05x_AttestationAlgo_EC_SHA_256 = kSE05x_ECSignatureAlgo_SHA_256, + kSE05x_AttestationAlgo_EC_SHA_384 = kSE05x_ECSignatureAlgo_SHA_384, + kSE05x_AttestationAlgo_EC_SHA_512 = kSE05x_ECSignatureAlgo_SHA_512, + kSE05x_AttestationAlgo_ED25519PURE_SHA_512 = kSE05x_EDSignatureAlgo_ED25519PURE_SHA_512, + kSE05x_AttestationAlgo_ECDAA = kSE05x_ECDAASignatureAlgo_ECDAA, + kSE05x_AttestationAlgo_RSA_SHA1_PKCS1_PSS = kSE05x_RSASignatureAlgo_SHA1_PKCS1_PSS, + kSE05x_AttestationAlgo_RSA_SHA224_PKCS1_PSS = kSE05x_RSASignatureAlgo_SHA224_PKCS1_PSS, + kSE05x_AttestationAlgo_RSA_SHA256_PKCS1_PSS = kSE05x_RSASignatureAlgo_SHA256_PKCS1_PSS, + kSE05x_AttestationAlgo_RSA_SHA384_PKCS1_PSS = kSE05x_RSASignatureAlgo_SHA384_PKCS1_PSS, + kSE05x_AttestationAlgo_RSA_SHA512_PKCS1_PSS = kSE05x_RSASignatureAlgo_SHA512_PKCS1_PSS, + kSE05x_AttestationAlgo_RSA_SHA_224_PKCS1 = kSE05x_RSASignatureAlgo_SHA_224_PKCS1, + kSE05x_AttestationAlgo_RSA_SHA_256_PKCS1 = kSE05x_RSASignatureAlgo_SHA_256_PKCS1, + kSE05x_AttestationAlgo_RSA_SHA_384_PKCS1 = kSE05x_RSASignatureAlgo_SHA_384_PKCS1, + kSE05x_AttestationAlgo_RSA_SHA_512_PKCS1 = kSE05x_RSASignatureAlgo_SHA_512_PKCS1, + +} SE05x_AttestationAlgo_t; + +/** RSA Key format */ +typedef enum +{ + kSE05x_RSAKeyFormat_CRT = kSE05x_P2_DEFAULT, + kSE05x_RSAKeyFormat_RAW = kSE05x_P2_RAW, +} SE05x_RSAKeyFormat_t; + +/** @copydoc SE05x_MACAlgo_t */ +typedef SE05x_MACAlgo_t SE05x_MacOperation_t; + +/** SE05X's key IDs */ +typedef uint32_t SE05x_KeyID_t; +/** Case when there is no KEK */ +#define SE05x_KeyID_KEK_NONE 0 + +/** [Optional: if the authentication key is the same as the key to be replaced, this TAG should not be present]. */ +#define SE05x_KeyID_MFDF_NONE 0 + +/** SE05X key's max attempts */ +typedef uint16_t SE05x_MaxAttemps_t; +/** Fall back to applet default */ +#define SE05x_MaxAttemps_UNLIMITED 0 +/** Identify in code that this is not an AUTH object and hence not applicable */ +#define SE05x_MaxAttemps_NA 0 + +/** When we want to read with attestation */ +#define kSE05x_INS_READ_With_Attestation (kSE05x_INS_READ | kSE05x_INS_ATTEST) + +/** When we want to read I2CM Data with attestation */ +#define kSE05x_INS_I2CM_Attestation (kSE05x_INS_CRYPTO | kSE05x_INS_ATTEST) + +#ifndef __DOXYGEN__ +/* RSA Helper Macros to make code little more readable */ +#define SE05X_RSA_NO_p /* Skip */ NULL, 0 +#define SE05X_RSA_NO_q /* Skip */ NULL, 0 +#define SE05X_RSA_NO_dp /* Skip */ NULL, 0 +#define SE05X_RSA_NO_dq /* Skip */ NULL, 0 +#define SE05X_RSA_NO_qInv /* Skip */ NULL, 0 +#define SE05X_RSA_NO_pubExp /* Skip */ NULL, 0 +#define SE05X_RSA_NO_priv /* Skip */ NULL, 0 +#define SE05X_RSA_NO_pubMod /* Skip */ NULL, 0 +#endif // __DOXYGEN__ + + +#endif /* SE05x_ENUMS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h new file mode 100644 index 00000000000..95ac4a2eeee --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h @@ -0,0 +1,36 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef SE05X_FTR_H +#define SE05X_FTR_H + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT + +#include + +/** @def SE05X_FTR_8BIT_CURVE_ID + * + * Curve IDs are 8bit wide. Else, the follow same 32 bit + * namespace. + */ + +#if APPLET_SE050_VER_MAJOR_MINOR > 10002u +#define SE05X_FTR_8BIT_CURVE_ID (1) +#define SE05X_FTR_32BIT_CURVE_ID (0) +#else +#define SE05X_FTR_8BIT_CURVE_ID (0) +#define SE05X_FTR_32BIT_CURVE_ID (1) +#endif /* APPLET_SE050_VER_MAJOR_MINOR > 10002u */ + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ + +#endif /* SE05X_FTR_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h new file mode 100644 index 00000000000..3c2158ac8e7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h @@ -0,0 +1,370 @@ +/* +* +* Copyright 2019,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef SE05X_TLV_H_INC +#define SE05X_TLV_H_INC + +#include +#include + + +#include "nxLog.h" +#include "nxScp03_Types.h" +//#include + +// #define VERBOSE_APDU_LOGS 1 + + +#define kSE05x_CLA 0x80 + +typedef enum +{ + SM_NOT_OK = 0xFFFF, + SM_OK = 0x9000, + SM_ERR_CONDITIONS_OF_USE_NOT_SATISFIED = 0x6985, + SM_ERR_ACCESS_DENIED_BASED_ON_POLICY = 0x6986, +} smStatus_t; + + +typedef enum +{ + CRED_DEFAULT = 0x00, + CRED_EC = 0x01, + CRED_RSA = 0x02, + CRED_AES = 0x03, + CRED_DES = 0x04, + CRED_BINARY = 0x05, + CRED_PIN = 0x06, + CRED_COUNTER = 0x07, + CRED_PCR = 0x08, + CRED_OBJECT = 0x09, + + CRED_PUB_EC, + CRED_PUB_RSA +} eSE05xType_t; + + +typedef struct +{ + uint8_t *se05xTxBuf; + size_t se05xTxBufLen; + size_t ws_LC; // With Session LC + size_t ws_LCW; // With Session LC Width 1 or 3 bytes + uint8_t *wsSe05x_cmd; // WithSession SE05X command + size_t wsSe05x_cmdLen; // WithSession SE05X command Length + size_t wsSe05x_tag1Len; // WithSession SE05X Tag1 len + size_t wsSe05x_tag1W; // WithSession SE05X Tag1 Width + uint8_t *wsSe05x_tag1Cmd; // WithSession SE05X Tag1 Command Data + size_t wsSe05x_tag1CmdLen; // WithSession SE05X Tag1 Command Data Len + const tlvHeader_t *se05xCmd_hdr; // SE05x Command Header + size_t se05xCmdLC; // SE05x Command LC + size_t se05xCmdLCW; // SE05x Command LC width + uint8_t *se05xCmd; // SE05x Command + size_t se05xCmdLen; // SE05x Command Length + uint8_t *dataToMac; + size_t dataToMacLen; +} Se05xApdu_t; + +struct Se05xSession; +struct _sss_se05x_tunnel_context; + +typedef struct Se05xSession +{ + uint8_t value[8]; + uint8_t hasSession : 1; + SE_AuthType_t authType; + /** Meta Funciton + * + * Internall first calls fp_Transform + * Then calls fp_RawTXn + * Then calls fp_DeCrypt + */ + smStatus_t(*fp_TXn)(struct Se05xSession * pSession, + const tlvHeader_t *hdr, uint8_t *cmdBuf, size_t cmdBufLen, uint8_t *rsp, size_t *rspLen, uint8_t hasle); + + /** API called by fp_TXn. Helps handle UserID/Applet/ECKey to transform buffer. + * + * But this API never sends any data out over any communication link. */ + smStatus_t(*fp_Transform)(struct Se05xSession * pSession, + /** IN */ + const tlvHeader_t *inHdr, + /** IN */ + uint8_t *inCmdBuf, + /** IN */ + size_t inCmdBufLen, + /** OUT: + * For Session less, + * For Platform SCP this will be copy of, inHDR, with outHdr[0] = outHdr[0] | 0x04 + * For Plain Session: Same as inHDR + * + * For With Session: + * This will be with TLV Header for Wrapped Session Command + */ + tlvHeader_t *outHdr, + /** OUT: For Session less, this will be copy of inCmdBuf + * + * For session based impelementation, this will have + * TAG=Session, L=8,V=Session,TAG=TAG1,L=inCmdBufLen,inCmdBuf */ + uint8_t * pTxBuf, + /** IN,OUT: */ + size_t * pTxBufLen, + /** IN */ + uint8_t hasle); + + /* API called by fp_TXn. Helps handle Applet/Fast SCP to decrypt buffer. + * + * But this API never reads any data */ + smStatus_t(*fp_DeCrypt)(struct Se05xSession * pSession, + size_t prevCmdBufLen, + uint8_t *pInRxBuf, + size_t *pInRxBufLen, + uint8_t hasle); +#if SSS_HAVE_APPLET_SE05X_IOT + /* It's either a minimal/single implemntation that calls smCom_TransceiveRaw() + * + * if pTunnelCtx is Null, directly call smCom_TransceiveRaw() + * + * Or an API part of tunnel ctx that can do PlatformSCP */ + smStatus_t (*fp_RawTXn)(void *conn_ctx, + struct _sss_se05x_tunnel_context *pChannelCtx, + SE_AuthType_t currAuth, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle); + + struct _sss_se05x_tunnel_context * pChannelCtx; +#endif +#if SSS_HAVE_SE + smStatus_t(*fp_Transmit)( + SE_AuthType_t currAuth, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle); +#endif + NXSCP03_DynCtx_t *pdynScp03Ctx; + + /**Connection data context */ + void *conn_ctx; +} Se05xSession_t; + + +typedef struct +{ + uint8_t *value; + size_t value_len; +} Se05xPolicy_t; + +typedef struct +{ + uint8_t ts[12]; +} SE05x_TimeStamp_t; + +typedef struct +{ + uint8_t features[30]; +} SE05x_ExtendedFeatures_t; + +typedef struct +{ + SE05x_Variant_t variant; + SE05x_ExtendedFeatures_t *extended_features; +} Se05x_AppletFeatures_t; + +typedef Se05x_AppletFeatures_t *pSe05xAppletFeatures_t; +typedef Se05xSession_t *pSe05xSession_t; +typedef Se05xPolicy_t *pSe05xPolicy_t; + +#if VERBOSE_APDU_LOGS +#define DO_LOG_V(TAG, DESCRIPTION, VALUE) nLog("APDU", NX_LEVEL_DEBUG, #TAG " [" DESCRIPTION "] = 0x%X", VALUE); +#define DO_LOG_A(TAG, DESCRIPTION, ARRAY, ARRAY_LEN) \ + nLog_au8("APDU", NX_LEVEL_DEBUG, #TAG " [" DESCRIPTION "]", ARRAY, ARRAY_LEN); +#else +#define DO_LOG_V(TAG, DESCRIPTION, VALUE) +#define DO_LOG_A(TAG, DESCRIPTION, ARRAY, ARRAY_LEN) +#endif + +#define TLVSET_Se05xSession(DESCRIPTION, PBUF, PBUFLEN, TAG, SESSIONID) \ + TLVSET_u8buf(DESCRIPTION, PBUF, PBUFLEN, TAG, SESSIONID->value, sizeof(SESSIONID->value)) + +#define TLVSET_Se05xPolicy(DESCRIPTION, PBUF, PBUFLEN, TAG, POLICY) \ + tlvSet_Se05xPolicy(DESCRIPTION, PBUF, PBUFLEN, TAG, POLICY) + +#define TLVSET_U8(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_U8(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_U16(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_U16(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_U16Optional(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_U16Optional(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_U32(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_U32(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_U64_SIZE(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE,SIZE) \ + tlvSet_U64_size(PBUF, PBUFLEN, TAG, VALUE,SIZE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_KeyID(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_KeyID(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_MaxAttemps(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_MaxAttemps(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_AttestationAlgo TLVSET_U8 +#define TLVSET_CipherMode TLVSET_U8 + +#define TLVSET_ECCurve(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + tlvSet_ECCurve(PBUF, PBUFLEN, TAG, VALUE); \ + DO_LOG_V(TAG, DESCRIPTION, VALUE) + +#define TLVSET_ECCurveParam TLVSET_U8 +#define TLVSET_ECDAASignatureAlgo TLVSET_U8 +#define TLVSET_ECSignatureAlgo TLVSET_U8 +#define TLVSET_EDSignatureAlgo TLVSET_U8 +#define TLVSET_MacOperation TLVSET_U8 +#define TLVSET_RSAEncryptionAlgo TLVSET_U8 +#define TLVSET_RSAKeyComponent TLVSET_U8 +#define TLVSET_RSASignatureAlgo TLVSET_U8 +#define TLVSET_DigestMode TLVSET_U8 +#define TLVSET_Variant tlvSet_u8buf_features +#define TLVSET_RSAPubKeyComp TLVSET_U8 +#define TLVSET_PlatformSCPRequest TLVSET_U8 +#define TLVSET_MemoryType TLVSET_U8 + +#define TLVSET_CryptoContext TLVSET_U8 +#define TLVSET_CryptoModeSubType(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) \ + TLVSET_U8(DESCRIPTION, PBUF, PBUFLEN, TAG, ((VALUE).union_8bit)) + +#define TLVSET_CryptoObjectID TLVSET_U16 + +// #define TLVSET_pVoid(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) (0) +// #define tlvGet_pVoid(DESCRIPTION, PBUF, PBUFLEN, TAG, VALUE) (0) + +#define TLVSET_u8buf(DESCRIPTION, PBUF, PBUFLEN, TAG, CMD, CMDLEN) \ + tlvSet_u8buf(PBUF, PBUFLEN, TAG, CMD, CMDLEN); \ + DO_LOG_A(TAG, DESCRIPTION, CMD, CMDLEN) + +#define TLVSET_u8bufOptional(DESCRIPTION, PBUF, PBUFLEN, TAG, CMD, CMDLEN) \ + tlvSet_u8bufOptional(PBUF, PBUFLEN, TAG, CMD, CMDLEN); \ + DO_LOG_A(TAG, DESCRIPTION, CMD, CMDLEN) + +#define TLVSET_u8bufOptional_ByteShift(DESCRIPTION, PBUF, PBUFLEN, TAG, CMD, CMDLEN) \ + tlvSet_u8bufOptional_ByteShift(PBUF, PBUFLEN, TAG, CMD, CMDLEN); \ + DO_LOG_A(TAG, DESCRIPTION, CMD, CMDLEN) + + +#define TLVSET_u8buf_I2CM(DESCRIPTION, PBUF, PBUFLEN, TAG, CMD, CMDLEN) \ + tlvSet_u8buf_I2CM(PBUF, PBUFLEN, TAG, CMD, CMDLEN); \ + DO_LOG_A(TAG, DESCRIPTION, CMD, CMDLEN) + + +int tlvSet_U8(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint8_t value); +int tlvSet_U16(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t value); +int tlvSet_U16Optional(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t value); +int tlvSet_U32(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint32_t value); +int tlvSet_U64_size(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint64_t value,uint16_t size); +int tlvSet_u8buf(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen); +int tlvSet_u8bufOptional(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen); +/* Same as tlvSet_u8bufOptional, but some time, Most Significant Byte needs to be shifted and Plus by 1 */ +int tlvSet_u8bufOptional_ByteShift(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen); +int tlvSet_Se05xPolicy(const char *description, uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, Se05xPolicy_t *policy); +int tlvSet_KeyID(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint32_t keyID); +int tlvSet_MaxAttemps(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t maxAttemps); +int tlvSet_ECCurve(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, SE05x_ECCurve_t value); +int tlvSet_u8buf_features(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, pSe05xAppletFeatures_t appletVariant); + +int tlvGet_U8(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint8_t *pRsp); +int tlvGet_U16(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint16_t *pRsp); +int tlvGet_U32(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint32_t *pRsp); + +int tlvGet_u8buf(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint8_t *rsp, size_t *pRspLen); +int tlvGet_ValueIndex(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag); +int tlvGet_Se05xSession( + uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, pSe05xSession_t *pSessionId); +int tlvGet_TimeStamp(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, SE05x_TimeStamp_t *pTs); + +int tlvSet_u8buf_I2CM(uint8_t **buf, size_t *bufLen, SE05x_I2CM_TAG_t tag, const uint8_t *cmd, size_t cmdLen); + +int tlvGet_SecureObjectType(uint8_t *buf, size_t *pBufIndex, size_t bufLen, SE05x_TAG_t tag, SE05x_SecObjTyp_t *pType); + +int tlvGet_Result(uint8_t *buf, size_t *pBufIndex, size_t bufLen, SE05x_TAG_t tag, SE05x_Result_t *presult); + + + +smStatus_t se05x_Transform(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdApduBuf, + const size_t cmdApduBufLen, + tlvHeader_t *out_hdr, + uint8_t *txBuf, + size_t *ptxBufLen, + uint8_t hasle); + +smStatus_t se05x_Transform_scp(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdApduBuf, + const size_t cmdApduBufLen, + tlvHeader_t *outhdr, + uint8_t *txBuf, + size_t *ptxBufLen, + uint8_t hasle); + +smStatus_t se05x_DeCrypt(struct Se05xSession *pSessionCtx, + size_t cmd_cmacLen, + uint8_t *rsp, + size_t *rspLength, + uint8_t hasle); + +smStatus_t DoAPDUTxRx_s_Case2(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen); + +smStatus_t DoAPDUTx_s_Case3(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen); + +smStatus_t DoAPDUTxRx_s_Case4(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen); + +smStatus_t DoAPDUTxRx_s_Case4_ext(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen); + +smStatus_t DoAPDUTxRx(Se05xSession_t *pSessionCtx, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen); + +#if SSS_HAVE_APPLET_SE05X_IOT +smStatus_t Se05x_API_I2CM_Send( + pSe05xSession_t sessionId, const uint8_t *buffer, size_t bufferLen, uint8_t *result, size_t *presultLen); +#endif +#endif // !SE05X_TLV_H_INC diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h new file mode 100644 index 00000000000..7beb37cfa51 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h @@ -0,0 +1,123 @@ +/* +* +* Copyright 2016,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef _A71CH_CONST_H_ +#define _A71CH_CONST_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_A71CH && (!(SSS_HAVE_A71CH_SIM)) +# define APPLET_NAME "a71ch" // 0x61.37.31.63.68 +# define APPLET_NAME_LEN (sizeof(APPLET_NAME) - 1) +# define SE_NAME "A71CH" +#endif +#if SSS_HAVE_LOOPBACK +# define APPLET_NAME \ + { 0xD2, 0x76, 0x00, 0x00, 0x85, 0x54, 0x65, 0x73, \ + 0x74, 0x01, 0x01 } //echo applet +# define APPLET_NAME_LEN (11) +# define SE_NAME "LoopBack" +#endif +#if SSS_HAVE_A71CL +# define APPLET_NAME \ + { 0xA0, 0x00, 0x00, 0x00, 0x41, 0x6C, 0x69, 0x59, \ + 0x75, 0x6E, 0x2E, 0x49, 0x44, 0x32, 0x01}// "Ali Yun" +# define APPLET_NAME_LEN (15) +# define SE_NAME "A71CL" +#endif + +#if SSS_HAVE_SE050_L +# define APPLET_NAME \ +{ 0xA0, 0x00, 0x00, 0x00, 0x41, 0x6C, 0x69, 0x59, \ + 0x75, 0x6E, 0x2E, 0x49, 0x44, 0x32 \ +}// "Ali Yun" + + +# define APPLET_NAME_LEN (14) +# define SE_NAME "SE050_L" +#endif + +#if SSS_HAVE_A71CH_SIM +# define APPLET_NAME \ + {0xa0, 0x00, 0x00, 0x03, 0x96, 0x54, 0x53, 0x00, \ + 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00} +# define APPLET_NAME_LEN (16) +# define SE_NAME "SE050:EAR:CH" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT +# define APPLET_NAME \ + {0xa0, 0x00, 0x00, 0x03, 0x96, 0x54, 0x53, 0x00, \ + 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00} +# define APPLET_NAME_LEN (16) + +# define SSD_NAME \ + { 0xD2, 0x76, 0x00, 0x00, 0x85, 0x30, 0x4A, 0x43, 0x4F, 0x90, 0x03} +#endif + +#if SSS_HAVE_SE05X_A +# define SE_NAME "SE050:A" +#endif +#if SSS_HAVE_SE05X_B +# define SE_NAME "SE050:B" +#endif +#if SSS_HAVE_SE05X_C +# define SE_NAME "SE050:C" +#endif + +#define A71CH_KEY_PAIR_MAX_A 2 //!< Maximum amount of ECC key pairs that can be stored in A71CH (A device) +#define A71CH_PUBLIC_KEY_MAX_A 2 //!< Maximum amount of ECC public keys that can be stored in A71CH (A device) +#define A71CH_SYM_KEY_MAX_A 4 //!< Maximum amount of Symmetric keys that can be stored in A71CH (A device) +#define A71CH_KEY_PAIR_MAX_B 4 //!< Maximum amount of ECC key pairs that can be stored in A71CH (B device) +#define A71CH_PUBLIC_KEY_MAX_B 3 //!< Maximum amount of ECC public keys that can be stored in A71CH (B device) +#define A71CH_SYM_KEY_MAX_B 8 //!< Maximum amount of Symmetric keys that can be stored in A71CH (A device) +#define A71CH_COUNTER_MAX 2 //!< Maximum amount of monotonic counters that can be stored in A71CH (A&B) + +// We cover two A71CH product variants that differ in the amount of credentials that can be stored. +// These two variants are referred to (in this example source code) as +// - TYPE_A (or simply A) - which is the device with lesser storage +// - TYPE_B (or simply B) - which is the device with more storage +// As the example source code depends on the amount of credentials that can be stored +// the ::A71CH_DEVICE_TYPE define must be used to select between either variant at compile time. +#define A71CH_DEVICE_TYPE_A (0x41) //!< Symbolic constant to represent the Initial A71CH device +#define A71CH_DEVICE_TYPE_B (0x42) //!< Synbolic constant to represent the A71CH device with more storage +#define A71CH_DEVICE_TYPE A71CH_DEVICE_TYPE_B //!< Indicate the credential storage capabilities of the A71CH + + +/** @def A71CH_KEY_PAIR_MAX + * Maximum ECC Key Pairs in the Secure module */ +/** @def A71CH_PUBLIC_KEY_MAX + * Maximum ECC Public Keys in the Secure module */ +/** @def A71CH_SYM_KEY_MAX + * Maximum ECC Symmetric Keys in the Secure module */ +/** @def A71CH_GP_STORAGE_SIZE + * Maximum General Purpose Storage in the Secure module */ + +#if A71CH_DEVICE_TYPE == A71CH_DEVICE_TYPE_A +//!< Effective value used in examples +# define A71CH_KEY_PAIR_MAX A71CH_KEY_PAIR_MAX_A +# define A71CH_PUBLIC_KEY_MAX A71CH_PUBLIC_KEY_MAX_A +# define A71CH_SYM_KEY_MAX A71CH_SYM_KEY_MAX_A +# define A71CH_GP_STORAGE_SIZE A71CH_GP_STORAGE_SIZE_A +#else +# define A71CH_KEY_PAIR_MAX A71CH_KEY_PAIR_MAX_B +# define A71CH_PUBLIC_KEY_MAX A71CH_PUBLIC_KEY_MAX_B +# define A71CH_SYM_KEY_MAX A71CH_SYM_KEY_MAX_B +# define A71CH_GP_STORAGE_SIZE A71CH_GP_STORAGE_SIZE_B +#endif + +#ifdef __cplusplus +} +#endif +#endif //_A71CHCONSTL_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c new file mode 100644 index 00000000000..62af6070f66 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c @@ -0,0 +1,87 @@ +/* +* +* Copyright 2016,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#include +#include +#include + +#include "global_platf.h" +#include "smCom.h" + +#include "scp.h" +#include "sm_apdu.h" +#include "sm_errors.h" + +#include "nxLog_hostLib.h" +#include "nxEnsure.h" + +/** + * Send a select command to the card manager + * + * \param[in] appletName Pointer to a buffer containing the applet name. + * \param[in] appletNameLen Length of the applet name. + * \param[out] responseData Pointer to a buffer that will contain response data (excluding status word). + * \param[in,out] responseDataLen IN: size of pResponse buffer passed as argument; OUT: Length of response data retrieved + * + * \retval ::SW_OK Upon successfull execution + */ +U16 GP_Select(void *conn_ctx, const U8 *appletName, U16 appletNameLen, U8 *responseData, U16 *responseDataLen) +{ + U16 rv = ERR_COMM_ERROR; + U32 u32RXLen = *responseDataLen; + + uint8_t tx_buf[MAX_APDU_BUF_LENGTH]; + uint16_t tx_len; + + ENSURE_OR_GO_CLEANUP(NULL != responseData); + ENSURE_OR_GO_CLEANUP(0 != responseDataLen); + ENSURE_OR_GO_CLEANUP(appletNameLen < 255); + /* cla+ins+p1+p2+lc+appletNameLen+le */ + ENSURE_OR_GO_CLEANUP(sizeof(tx_buf) > (6 + appletNameLen)); + + tx_buf[0] = CLA_ISO7816; + tx_buf[1] = INS_GP_SELECT; + tx_buf[2] = 4; + tx_buf[3] = 0; + + tx_len = 0 /* for indentation */ + + 1 /* CLA */ + + 1 /* INS */ + + 1 /* P1 */ + + 1 /* P2 */; + if (appletNameLen > 0) { + tx_buf[4] = (uint8_t)appletNameLen; // We have done ENSURE_OR_GO_CLEANUP(appletNameLen < 255); + tx_len = tx_len + 1 /* Lc */ + + appletNameLen /* Payload */ + + 1 /* Le */; + memcpy(&tx_buf[5], appletName, appletNameLen); + } + else { + tx_len = tx_len /* for indentation */ + + 0 /* No Lc */ + + 1 /* Le */; + } + tx_buf[tx_len - 1] = 0; /* Le */ + + // apdu_t * pApdu = (apdu_t *) &apdu; + // U8 isOk = 0x00; + + // pApdu->cla = CLA_ISO7816; + // pApdu->ins = INS_GP_SELECT; + // pApdu->p1 = 0x04; + // pApdu->p2 = 0x00; + + rv = smCom_TransceiveRaw(conn_ctx, tx_buf, tx_len, responseData, &u32RXLen); + if (rv == SW_OK && u32RXLen >= 2) { + *responseDataLen = u32RXLen - 2; + rv = responseData[u32RXLen - 2]; + rv <<= 8; + rv |= responseData[u32RXLen - 1]; + } + +cleanup: + return rv; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h new file mode 100644 index 00000000000..9e358d42557 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h @@ -0,0 +1,28 @@ +/* +* +* Copyright 2016,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef _GLOBAL_PLATF_ +#define _GLOBAL_PLATF_ + +#include "sm_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CLA_ISO7816 (0x00) //!< ISO7816-4 defined CLA byte + +#define INS_GP_INITIALIZE_UPDATE (0x50) //!< Global platform defined instruction +#define INS_GP_EXTERNAL_AUTHENTICATE (0x82) //!< Global platform defined instruction +#define INS_GP_SELECT (0xA4) //!< Global platform defined instruction +#define INS_GP_PUT_KEY (0xD8) //!< Global platform defined instruction + +U16 GP_Select(void *conn_ctx, const U8 *appletName, U16 appletNameLen, U8 *response, U16 *responseLen); +U16 GP_GetCLAppletVersion(U8 *appletVersion, U16 *verionLength); +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c new file mode 100644 index 00000000000..c5e9c5a3576 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c @@ -0,0 +1,880 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * + * @par Description + * This file implements the high-level APDU handling of the SM module. + * @par History + * 1.0 31-march-2014 : Initial version + * 1.1 10-april-2019 : Removed compile time choice 'USE_MALLOC_FOR_APDU_BUFFER' + * + *****************************************************************************/ +#include +#include +#include +#include + + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include "sm_apdu.h" +// #include "ax_api.h" +#include "scp.h" +#include "nxLog_hostLib.h" +#include "nxEnsure.h" + +static void ReserveLc(apdu_t * pApdu); +static void SetLc(apdu_t * pApdu, U16 lc); +static void AddLe(apdu_t * pApdu, U16 le); + +#if SSS_HAVE_A71CH_SIM +/* Send session ID in trans-receive */ +static U8 session_Tlv[7]; +static U8 gEnableEnc = 0; +#endif + +static U8 sharedApduBuffer[MAX_APDU_BUF_LENGTH]; + +#ifdef TGT_A71CH +#if ( (APDU_HEADER_LENGTH + APDU_STD_MAX_DATA + 1) >= MAX_APDU_BUF_LENGTH ) +#error "Ensure MAX_APDU_BUF_LENGTH is big enough" +#endif +#endif // TGT_A71CH + +/** + * Associates a memory buffer with the APDU buffer. + * + * By default (determined at compile time) the buffer is not allocated with each call, but a reference + * is made to a static data structure. + * + * \param[in,out] pApdu APDU buffer + * \returns always returns 0 + */ +U8 AllocateAPDUBuffer(apdu_t *pApdu) +{ + ENSURE_OR_GO_EXIT(pApdu != NULL); + // In case of e.g. TGT_A7, pApdu is pointing to a structure defined on the stack + // so pApdu->pBuf contains random data + pApdu->pBuf = sharedApduBuffer; + +exit: + return 0; +} + +/** + * Clears the previously referenced APDU buffer. + * + * In case the buffer was effectively malloc'd by ::AllocateAPDUBuffer it will also be freed. + * + * \param[in,out] pApdu APDU buffer + * \return Always returns 0 + */ +U8 FreeAPDUBuffer(apdu_t * pApdu) +{ + ENSURE_OR_GO_EXIT(pApdu != NULL); + + if (pApdu->pBuf) + { + U16 nClear = (pApdu->rxlen > MAX_APDU_BUF_LENGTH) ? MAX_APDU_BUF_LENGTH : pApdu->rxlen; + memset(pApdu->pBuf, 0, nClear); + pApdu->pBuf = 0; + } + +exit: + return 0; +} + +/** + * Sets up the command APDU header. + * \param[in,out] pApdu APDU buffer + * \param[in] extendedLength Indicates if command/response have extended length. Either ::USE_STANDARD_APDU_LEN or ::USE_EXTENDED_APDU_LEN + * \return offset in APDU buffer after the header + */ +U8 SetApduHeader(apdu_t * pApdu, U8 extendedLength) +{ + U8 ret = 0; + // pApdu->edc = eEdc_NoErrorDetection; + ENSURE_OR_GO_EXIT(pApdu != NULL); + + pApdu->pBuf[0] = pApdu->cla; + pApdu->pBuf[1] = pApdu->ins; + pApdu->pBuf[2] = pApdu->p1; + pApdu->pBuf[3] = pApdu->p2; + + pApdu->extendedLength = extendedLength; + pApdu->hasData = false; + pApdu->lcLength = 0; + pApdu->lc = 0; + pApdu->hasLe = false; + + // No LC yet + pApdu->offset = APDU_OFFSET_LC; + + // adapt length + pApdu->buflen = pApdu->offset; + + // Set rxlen to default value + pApdu->rxlen = 0; + + ret = (U8)(pApdu->offset); +exit: + return ret; +} + +#if SSS_HAVE_A71CH_SIM +/** + * Creates session TLV from session ID. Session ID is retrieved as response to auth command. + * \param[in] sessionId + */ +void set_SessionId_Tlv(U32 sessionId) +{ + session_Tlv[0] = 0xBE; + session_Tlv[1] = 0xBE; + session_Tlv[2] = 0x04; + session_Tlv[3] = (U8)(sessionId >> 24); + session_Tlv[4] = (U8)(sessionId >> 16); + session_Tlv[5] = (U8)(sessionId >> 8); + session_Tlv[6] = (U8)(sessionId >> 0); + gEnableEnc = sessionId !=0 ? 1:0; +} +#endif + +/** + * In the final stage before sending the APDU cmd one needs to update the values of lc (and le). + * \param[in,out] pApdu APDU buffer + * \param[in] lc + */ +void smApduAdaptLc(apdu_t *pApdu, U16 lc) +{ + SetLc(pApdu, lc); +} + +/** + * In the final stage before sending the APDU cmd one needs to update the values of le (and lc). + * \param[in,out] pApdu APDU buffer + * \param[in] le + */ +void smApduAdaptLe(apdu_t *pApdu, U16 le) +{ + AddLe(pApdu, le); +} + +/** + * In the final stage before sending the APDU cmd one needs to update the values of lc and le. + * \param[in,out] pApdu APDU buffer + * \param[in] lc + * \param[in] le + */ +void smApduAdaptLcLe(apdu_t *pApdu, U16 lc, U16 le) +{ + SetLc(pApdu, lc); + AddLe(pApdu, le); +} + +/** + * Reserves bytes for the LC in the command APDU and updated the pApdu data structure to match. + * Must be called once in case the APDU cmd has a command data section. + * \pre pApdu->hasData has been set. + * \param[in,out] pApdu APDU buffer + */ +static void ReserveLc(apdu_t * pApdu) +{ + ENSURE_OR_GO_EXIT(pApdu != NULL); + + pApdu->lcLength = 0; + + ENSURE_OR_GO_EXIT(pApdu->hasData != 0); + + if (pApdu->extendedLength) { + pApdu->lcLength = 3; + } + else { + pApdu->lcLength = 1; + } + + pApdu->offset += pApdu->lcLength; + pApdu->buflen += pApdu->lcLength; +exit: + return; +} + +/** + * Sets the LC value in the command APDU. + * @pre ReserveLc(...) has been called or there is no command data section + * @param[in,out] pApdu APDU buffer + * @param[in] lc LC value to be set + */ +static void SetLc(apdu_t * pApdu, U16 lc) +{ + ENSURE_OR_GO_EXIT(pApdu != NULL); + ENSURE_OR_GO_EXIT((pApdu->lcLength != 0) || (pApdu->hasData == 0)); + + // NOTE: + // pApdu->lcLength was set to its proper value in a call to ReserveLc(...) + + if (pApdu->hasData) { + if (pApdu->extendedLength) { + pApdu->lc = lc; + // pApdu->lcLength = 3; + pApdu->pBuf[APDU_OFFSET_LC] = 0x00; + pApdu->pBuf[APDU_OFFSET_LC + 1] = (U8)(lc >> 8); + pApdu->pBuf[APDU_OFFSET_LC + 2] = (U8)(lc & 0xFF); + } + else { + pApdu->lc = lc; + // pApdu->lcLength = 1; + pApdu->pBuf[APDU_OFFSET_LC] = (U8)(lc & 0xFF); + } + } + else { + pApdu->lcLength = 0; + } +exit: + return; +} + +/** + * Adds the LE value to the command APDU. + * @param pApdu [IN/OUT] APDU buffer + * @param le [IN] LE + * @return + */ +static void AddLe(apdu_t * pApdu, U16 le) +{ + ENSURE_OR_GO_EXIT(pApdu != NULL); + + pApdu->hasLe = true; + pApdu->le = le; + + if (pApdu->extendedLength) { + if (pApdu->hasData) { + ENSURE_OR_GO_EXIT( (pApdu->offset + 1) < MAX_APDU_BUF_LENGTH); + pApdu->pBuf[pApdu->offset] = (U8)(le >> 8); + pApdu->pBuf[pApdu->offset + 1] = (U8)(le & 0xFF); + pApdu->leLength = 2; + } + else { + ENSURE_OR_GO_EXIT( (pApdu->offset + 2) < MAX_APDU_BUF_LENGTH); + pApdu->pBuf[pApdu->offset] = 0x00; + pApdu->pBuf[pApdu->offset + 1] = (U8)(le >> 8); + pApdu->pBuf[pApdu->offset + 2] = (U8)(le & 0xFF); + pApdu->leLength = 3; + } + } + else { + // regular length + ENSURE_OR_GO_EXIT(pApdu->offset < MAX_APDU_BUF_LENGTH); + pApdu->pBuf[pApdu->offset] = (U8)(le & 0xFF); + pApdu->leLength = 1; + } + + pApdu->offset += pApdu->leLength; + pApdu->buflen += pApdu->leLength; +exit: + return; +} + + +#if 0 +/** + * @function AddTlvItem + * @description Adds a Tag-Length-Value structure to the command APDU. + * @param pApdu [IN/OUT] APDU buffer. + * @param tag [IN] tag; either a 1-byte tag or a 2-byte tag + * @param dataLength [IN] length of the Value + * @param pValue [IN] Value + * @return SW_OK or ERR_BUF_TOO_SMALL + */ +U16 AddTlvItem(apdu_t * pApdu, U16 tag, U16 dataLength, const U8 *pValue) +{ + U8 msbTag = tag >> 8; + U8 lsbTag = tag & 0xff; + + // If this is the first tag added to the buffer, we needs to ensure + // the correct offset is used writing the data. This depends on + // whether the APDU is a standard or an extended APDU. + if (pApdu->hasData == 0) + { + pApdu->hasData = 1; + ReserveLc(pApdu); + } + + // Ensure no buffer overflow will occur before writing any data to buffer + { + U32 xtraData = 0; + U32 u32_Offset = (U32)(pApdu->offset); + + xtraData = 1; + // Tag + if (msbTag != 0x00) + { + // 2-byte tag + xtraData++; + } + + // Length + if (dataLength <= 0x7f) + { + // 1-byte length + xtraData++; + } + else if (dataLength <= 0xff) + { + // 2-byte length + xtraData += 2; + } + else + { + // 3-byte length + xtraData += 3; + } + xtraData += dataLength; + + // Can we still add 'xtraData' to internal buffer without buffer overwrite? + if ( (u32_Offset + xtraData) > MAX_APDU_BUF_LENGTH) + { + // Bufferflow would occur + return ERR_BUF_TOO_SMALL; + } + } + + // Tag + if (msbTag != 0x00) + { + // 2-byte tag + pApdu->pBuf[pApdu->offset++] = msbTag; + } + pApdu->pBuf[pApdu->offset++] = lsbTag; + + // Length + if (dataLength <= 0x7f) + { + // 1-byte length + pApdu->pBuf[pApdu->offset++] = (U8) dataLength; + pApdu->lc += 2 + dataLength; + } + else if (dataLength <= 0xff) + { + // 2-byte length + pApdu->pBuf[pApdu->offset++] = 0x81; + pApdu->pBuf[pApdu->offset++] = (U8) dataLength; + pApdu->lc += 3 + dataLength; + } + else + { + // 3-byte length + pApdu->pBuf[pApdu->offset++] = 0x82; + pApdu->pBuf[pApdu->offset++] = dataLength >> 8; + pApdu->pBuf[pApdu->offset++] = dataLength & 0xff; + pApdu->lc += 4 + dataLength; + } + + // Value + memcpy(&pApdu->pBuf[pApdu->offset], pValue, dataLength); + pApdu->offset += dataLength; + + // adapt length + pApdu->buflen = pApdu->offset; + + return SW_OK; +} + +/** + * AddStdCmdData + * \deprecated Use ::smApduAppendCmdData instead + */ +U16 AddStdCmdData(apdu_t * pApdu, U16 dataLen, const U8 *data) +{ + + pApdu->hasData = 1; + ReserveLc(pApdu); + + pApdu->lc += dataLen; + + // Value + memcpy(&pApdu->pBuf[pApdu->offset], data, dataLen); + pApdu->offset += dataLen; + + // adapt length + pApdu->buflen = pApdu->offset; + + return pApdu->offset; +} + +/** + * @function ParseResponse + * @description Parses a received Tag-Length-Value structure (response APDU). + * @param pApdu [IN] APDU buffer + * @param expectedTag [IN] expected tag; either a 1-byte tag or a 2-byte tag + * @param pLen [IN,OUT] IN: size of buffer provided; OUT: length of the received Value + * @param pValue [OUT] received Value + * @return status + */ +U16 ParseResponse(apdu_t *pApdu, U16 expectedTag, U16 *pLen, U8 *pValue) +{ + U16 tag = 0; + U16 rv = ERR_GENERAL_ERROR; + int foundTag = 0; + U16 bufferLen = *pLen; + + *pLen = 0; + + if (pApdu->rxlen < 2) /* minimum: 2 byte for response */ + { + return ERR_GENERAL_ERROR; + } + else + { + /* check status returned is okay */ + if ((pApdu->pBuf[pApdu->rxlen - 2] != 0x90) || (pApdu->pBuf[pApdu->rxlen - 1] != 0x00)) + { + return ERR_GENERAL_ERROR; + } + else // response okay + { + pApdu->offset = 0; + + do + { + U16 len = 0; + + // Ensure we don't parse beyond the APDU Response Data + if (pApdu->offset >= (pApdu->rxlen -2)) { break; } + + /* get the tag (see ISO 7816-4 annex D); limited to max 2 bytes */ + if ((pApdu->pBuf[pApdu->offset] & 0x1F) != 0x1F) /* 1 byte tag only */ + { + tag = (pApdu->pBuf[pApdu->offset] & 0x00FF); + pApdu->offset += 1; + } + else /* tag consists out of 2 bytes */ + { + tag = (pApdu->pBuf[pApdu->offset] << 8) + pApdu->pBuf[pApdu->offset + 1]; + pApdu->offset += 2; + } + + // Ensure we don't parse beyond the APDU Response Data + if (pApdu->offset >= (pApdu->rxlen -2)) { break; } + + // tag is OK + /* get the length (see ISO 7816-4 annex D) */ + if ((pApdu->pBuf[pApdu->offset] & 0x80) != 0x80) + { + /* 1 byte length */ + len = (pApdu->pBuf[pApdu->offset++] & 0x00FF); + } + else + { + /* length consists of 2 or 3 bytes */ + + U8 additionalBytesForLength = (pApdu->pBuf[pApdu->offset++] & 0x7F); + + if (additionalBytesForLength == 1) + { + len = pApdu->pBuf[pApdu->offset]; + pApdu->offset += 1; + } + else if (additionalBytesForLength == 2) + { + len = (pApdu->pBuf[pApdu->offset] << 8) + pApdu->pBuf[pApdu->offset + 1]; + pApdu->offset += 2; + } + else + { + return ERR_GENERAL_ERROR; + } + } + + // Ensure we don't parse beyond the APDU Response Data + if (pApdu->offset >= (pApdu->rxlen -2)) { break; } + + if (tag == expectedTag) + { + // copy the value + if ( (len > 0) && (bufferLen >= len) ) + { + *pLen = len; + memcpy(pValue, &pApdu->pBuf[pApdu->offset], *pLen); + rv = SW_OK; + foundTag = 1; + break; + } + else + { + rv = ERR_BUF_TOO_SMALL; + break; + } + } + + // update the offset + pApdu->offset += len; + } while (!foundTag); + } + } + + return rv; +} + +#endif // TGT_A71CH + +/** + * Add or append data to the body of a command APDU. + * WARNING: + * - Bufferoverflow fix not applied for SSS_HAVE_A71CH_SIM + * WARNING for non-TGT_A71CH cases : + * - TGT_A71CL: This function must only be called once in case pApdu->txHasChkSum is set + */ +U16 smApduAppendCmdData(apdu_t *pApdu, const U8 *data, U16 dataLen) +{ + U16 rv = ERR_GENERAL_ERROR; + ENSURE_OR_GO_EXIT(pApdu != NULL); + ENSURE_OR_GO_EXIT(data != NULL); +#ifdef TGT_A71CH + // The maximum amount of data payload depends on (whichever is smaller) + // - STD-APDU (MAX=255 byte) / EXTENDED-APDU (MAX=65536 byte) + // - size of pApdu->pBuf (MAX_APDU_BUF_LENGTH) + // Standard Length APDU's: + // There is a pre-processor macro in place that ensures 'pApdu->pBuf' is of sufficient size + // Extended Length APDU's (not used by A71CH): + // APDU payload restricted by buffersize of 'pApdu->pBuf' + U16 maxPayload_noLe; + + if (pApdu->extendedLength) { + maxPayload_noLe = MAX_APDU_BUF_LENGTH - EXT_CASE4_APDU_OVERHEAD; + } + else { + maxPayload_noLe = APDU_HEADER_LENGTH + APDU_STD_MAX_DATA; + } +#endif // TGT_A71CH + +#ifdef TGT_A71CL + U16 maxPayload_noLe; + + maxPayload_noLe = MAX_APDU_BUF_LENGTH - EXT_CASE4_APDU_OVERHEAD; + if (pApdu->txHasChkSum == 1) { + maxPayload_noLe -= pApdu->txChkSumLength; + } +#endif // TGT_A71CL + + // If this is the first commmand data section added to the buffer, we needs to ensure + // the correct offset is used writing the data. This depends on + // whether the APDU is a standard or an extended APDU. + if (pApdu->hasData == 0) + { + pApdu->hasData = 1; + ReserveLc(pApdu); + } + +#if SSS_HAVE_A71CH_SIM + if (gEnableEnc) + { + pApdu->lc += (dataLen + sizeof(session_Tlv)); + //add SessionId_Tlv + memcpy(&pApdu->pBuf[pApdu->offset], session_Tlv, sizeof(session_Tlv)); + pApdu->offset += sizeof(session_Tlv); + } + else +#endif // SSS_HAVE_A71CH_SIM + { + pApdu->lc += dataLen; + } + +#ifdef TGT_A71CL + /* add for cl */ + if (pApdu->txHasChkSum == 1) { + pApdu->lc += pApdu->txChkSumLength; + pApdu->pBuf[pApdu->offset - 1] = (U8)pApdu->lc; + } +#endif // TGT_A71CL + + // Value +#if defined(TGT_A71CH) || defined(TGT_A71CL) + if (dataLen <= (maxPayload_noLe - pApdu->offset)) + { + memcpy(&pApdu->pBuf[pApdu->offset], data, dataLen); + pApdu->offset += dataLen; + } + else + { + return ERR_INTERNAL_BUF_TOO_SMALL; + } +#else // defined(TGT_A71CH) || defined(TGT_A71CL) + memcpy(&pApdu->pBuf[pApdu->offset], data, dataLen); + pApdu->offset += dataLen; +#endif // defined(TGT_A71CH) || defined(TGT_A71CL) + + // adapt length + pApdu->buflen = pApdu->offset; + + rv = pApdu->offset; +exit: + return rv; +} + +/** + * Gets the Status Word from the APDU. + * @param[in] pApdu Pointer to the APDU. + * @param[in,out] pIsOk IN: Pointer to the error indicator, allowed to be NULL; OUT: Points to '1' in case SW is 0x9000 + * @return Status Word or ::ERR_COMM_ERROR + */ +U16 smGetSw(apdu_t *pApdu, U8 *pIsOk) +{ + U16 sw = ERR_API_ERROR; + U16 offset; + ENSURE_OR_GO_EXIT(pApdu != NULL); + ENSURE_OR_GO_EXIT(pIsOk != NULL); + + if (pApdu->rxlen >= 2) + { + offset = pApdu->rxlen - 2; + sw = (pApdu->pBuf[offset] << 8) + pApdu->pBuf[offset + 1]; + + if (sw == SW_OK) + { + *pIsOk = 1; + } + else + { + *pIsOk = 0; + } + } + else + { + sw = ERR_COMM_ERROR; + *pIsOk = 0; + + } +exit: + return sw; +} + +/** + * verify crc checksum. + * \param[in] pApdu APDU buffer + * \param[in] dataLen data length to be use for crc caluate + * \return offset in APDU buffer after the header + */ +#if defined(TGT_A71CL) +static U8 smVerifyCrc(apdu_t *pApdu, U16 dataLen) +{ + U16 crc = 0; + U16 recvCrc = 0; + + ENSURE_OR_GO_EXIT(pApdu != NULL); + //FIXME: Where is the definition for below function? + //crc = CL_CalCRC(&pApdu->pBuf[pApdu->offset], (U32)dataLen, 0xFFFF); + recvCrc = *(U16*)&pApdu->pBuf[pApdu->offset + dataLen]; + if (crc != recvCrc) { + return 0; + } else { + return 1; + } +exit: + return 0; +} +#endif +/** + * Retrieve the response data of the APDU response, in case the status word matches ::SW_OK + */ +U16 smApduGetResponseBody(apdu_t *pApdu, U8 *buf, U16 *bufLen) +{ + U16 tailInfoLen = 2; + U16 rv = ERR_GENERAL_ERROR; + + ENSURE_OR_GO_EXIT(pApdu != NULL); + if (pApdu->rxlen < 2) /* minimum: 2 byte for response */ + { + *bufLen = 0; + return ERR_GENERAL_ERROR; + } + else + { + /* check status returned is okay */ + if (((pApdu->pBuf[pApdu->rxlen - 2] != 0x90) || (pApdu->pBuf[pApdu->rxlen - 1] != 0x00)) && + (pApdu->pBuf[pApdu->rxlen -2] != 0x63) && + (pApdu->pBuf[pApdu->rxlen - 2] != 0x95)) { + *bufLen = 0; + return ERR_GENERAL_ERROR; + } + else // response okay + { + pApdu->offset = 0; +#if defined(TGT_A71CL) + if (pApdu->rxHasChkSum == 1) { + tailInfoLen += pApdu->rxChkSumLength; + } +#endif + if ((pApdu->rxlen - tailInfoLen) > *bufLen) + { + *bufLen = 0; + return ERR_BUF_TOO_SMALL; + } + else + { + *bufLen = pApdu->rxlen - tailInfoLen; +#if defined(TGT_A71CL) + if (pApdu->rxHasChkSum == 1) { + if (smVerifyCrc(pApdu, *bufLen)) { + memcpy(buf, &(pApdu->pBuf[pApdu->offset]), *bufLen); + } else { + return ERR_CRC_CHKSUM_VERIFY; + } + } + else +#endif + { + if (*bufLen) { + memcpy(buf, &(pApdu->pBuf[pApdu->offset]), *bufLen); + } + } + } + } + } + + rv = SW_OK; +exit: + return rv; +} + +#ifdef TGT_A71CL + +/** + * In the final stage before sending the APDU cmd one needs to update checksum value. + * \param[in,out] pApdu APDU buffer + * \param[in] chksum + */ +U16 smApduAdaptChkSum(apdu_t *pApdu, U16 chkSum) +{ + U16 rv = ERR_GENERAL_ERROR; + // assert(pApdu->txHasChkSum == 1); + // U16 tmpchkSum = (chkSum >> 8)|(chkSum << 8); + + ENSURE_OR_GO_EXIT(pApdu != NULL); + if (pApdu->txHasChkSum) { + memcpy(&pApdu->pBuf[pApdu->offset], &chkSum, pApdu->txChkSumLength); + } + pApdu->buflen += pApdu->txChkSumLength; + pApdu->offset += pApdu->txChkSumLength; + + rv = pApdu->offset; +exit: + return rv; +} +#endif + +bool smApduGetArrayBytes(char *str, size_t *len, uint8_t *buffer, size_t buffer_len) +{ + if ((strlen(str) % 2) != 0) { + LOG_E("Invalid length"); + return false; + } + + *len = strlen(str) / 2; + if (buffer_len < *len) + { + LOG_E("Insufficient buffer size\n"); + *len = 0; + return false; + } + char *pos = str; + for (size_t count = 0; count < *len; count++) { + if (sscanf(pos, "%2hhx", &buffer[count]) < 1) { + *len = 0; + return false; + } + pos += 2; + } + return true; +} + +bool smApduGetTxRxCase(uint8_t *apdu, size_t apduLen, size_t* data_offset, size_t *dataLen, apduTxRx_case_t *apdu_case) +{ + *data_offset = 0; + *dataLen = 0; + *apdu_case = APDU_TXRX_CASE_INVALID; + //Invalid apdu + if (apduLen < 4) + { + LOG_E("Wrong APDU format\n"); + return false; + } + + //Case 1 + if (apduLen == 4) + { + *apdu_case = APDU_TXRX_CASE_1; + return true; + } + //Case 2S + else if (apduLen == 5) + { + *apdu_case = APDU_TXRX_CASE_2; + return true; + } + else + { + size_t byte5 = apdu[4] & 0xFF; + if (byte5 != 0x0) + { + if (apduLen == 5 + byte5) + { + //case 3S + *apdu_case = APDU_TXRX_CASE_3; + *data_offset = 5; + *dataLen = byte5; + } + else if (apduLen == 6 + byte5) + { + //case 4S + *apdu_case = APDU_TXRX_CASE_4; + *data_offset = 5; + *dataLen = byte5; + } + else + { + LOG_E("Wrong APDU format\n"); + return false; + } + } + else if (apduLen == 7) + { + //case 2E + *apdu_case = APDU_TXRX_CASE_2E; + } + else if (apduLen < 7) + { + LOG_E("Wrong APDU format\n"); + return false; + } + else + { + size_t len = ((apdu[5] << (1 * 8)) & 0xFF00) + ((apdu[6] << (0 * 8)) & 0x00FF); + if (apduLen == 7 + len) { + //case 3E + *apdu_case = APDU_TXRX_CASE_3E; + *data_offset = 7; + *dataLen = len; + } + else if (apduLen == 9 + len) { + //Case 4E + *apdu_case = APDU_TXRX_CASE_4E; + *data_offset = 7; + *dataLen = len; + } + else + { + LOG_E("Wrong APDU format\n"); + return false; + } + } + } + return true; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h new file mode 100644 index 00000000000..47a739a5f72 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h @@ -0,0 +1,217 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * This file defines the API of the APDU parser for AX host library. + * @par History + * 1.0 31-mar-2014 : Initial version + * + */ + +#ifndef _SM_APDU_H_ +#define _SM_APDU_H_ + +#include "apduComm.h" +#include "sm_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef A71_IGNORE_PARAM_CHECK +#error "Do not remove API parameter check" +#endif + +/* ------------------------------ */ + +#define MAX_APDU_BUF_LENGTH (256 + 1024) // This value has not been optimized for TGT_A71CH (256+64) + +#define MAX_EXT_APDU_BUF_LENGTH (32769) // extended APDU Max supported Len is 0x7FFF + 2 bytes status code + + +#define APDU_HEADER_LENGTH (5) +#define APDU_EXTENDED_HEADER_LENGTH (7) +#define EXT_CASE4_APDU_OVERHEAD (9) +#define SCP03_OVERHEAD (24) // padding (=16) + mac (=8) +#define RSP_APDU_STATUS_OVERHEAD (2) +#define APDU_STD_MAX_DATA (255) + +// +#ifdef TGT_A70CI +#define TAG_SST_IDENTIFIER (0x01) +#define TAG_SST_INDEX (0x02) +#define TAG_ECC_PRIVATE_KEY (0x03) +#define TAG_ECC_PUBLIC_KEY (0x04) +#define TAG_SHARED_SECRET (0x05) +#define TAG_RSA_PRIVATE_KEY_P (0x06) +#define TAG_RSA_PRIVATE_KEY_Q (0x07) +#define TAG_RSA_PRIVATE_KEY_DP (0x08) +#define TAG_RSA_PRIVATE_KEY_DQ (0x09) +#define TAG_RSA_PRIVATE_KEY_IPQ (0x0A) +#define TAG_PUBLIC_KEY (0x0B) +#define TAG_AES_KEY (0x0C) +#define TAG_AUTH_PUBLIC_KEY_ID (0x0D) +#define TAG_CONTEXT (0x0F) +#define TAG_DIRECTION (0x10) +#define TAG_IV (0x11) +#define TAG_INPUT_DATA (0x12) +#define TAG_OUTPUT_DATA (0x13) +#define TAG_AUTHENTICATION_DATA (0x14) +#define TAG_GMAC_DATA (0x15) +#define TAG_GMAC_LENGTH (0x16) +#define TAG_KEYWRAP_ALGO (0x17) +#define TAG_HASH (0x18) +#define TAG_SIGNATURE (0x19) +#define TAG_VERIFICATION (0x1A) +#define TAG_CERTIFICATE (0x1B) +#define TAG_SIZE (0x1C) +#define TAG_SALT (0x1E) +#elif defined(TGT_A70CM) +#define TAG_DLMS_SECURITY_BYTE (0x00) +#define TAG_SST_IDENTIFIER (0x01) +#define TAG_SST_INDEX (0x02) +#define TAG_ECC_PRIVATE_KEY (0x03) +#define TAG_ECC_PUBLIC_KEY (0x04) +#define TAG_SHARED_SECRET (0x05) +#define TAG_RSA_PRIVATE_KEY_P (0x06) +#define TAG_RSA_PRIVATE_KEY_Q (0x07) +#define TAG_RSA_PRIVATE_KEY_DP (0x08) +#define TAG_RSA_PRIVATE_KEY_DQ (0x09) +#define TAG_RSA_PRIVATE_KEY_IPQ (0x0A) +#define TAG_RSA_PUBLIC_KEY_MOD (0x0B) +#define TAG_AES_KEY (0x0C) +#define TAG_WRAPPED_AES_KEY (0x0D) +#define TAG_CONTEXT (0x0E) +#define TAG_DIRECTION (0x0F) +#define TAG_IV (0x10) +#define TAG_INPUT_DATA (0x11) +#define TAG_OUTPUT_DATA (0x12) +#define TAG_AUTHENTICATION_DATA (0x13) +#define TAG_GMAC_DATA (0x14) +#define TAG_GMAC_LENGTH (0x15) +#define TAG_KEYWRAP_ALGO (0x16) +#define TAG_HASH (0x17) +#define TAG_SIGNATURE (0x18) +#define TAG_DLMS_AK_INDEX (0x19) +#define TAG_VERIFICATION (0x1A) +#define TAG_CERTIFICATE (0x1B) +#define TAG_OFFSET (0x1C) +#define TAG_SIZE (0x1D) +#define TAG_SST_WRAPPING_KEY_INDEX (0x1E) +#else // +/// @cond not_relevant_for_A71ch & A71cl +#define TAG_DLMS_SECURITY_BYTE (0x00) +#define TAG_SST_IDENTIFIER (0x01) +#define TAG_SST_INDEX (0x02) +#define TAG_ECC_PRIVATE_KEY (0x03) +#define TAG_ECC_PUBLIC_KEY (0x04) +#define TAG_SHARED_SECRET (0x05) +#define TAG_RSA_PRIVATE_KEY_P (0x06) +#define TAG_RSA_PRIVATE_KEY_Q (0x07) +#define TAG_RSA_PRIVATE_KEY_DP (0x08) +#define TAG_RSA_PRIVATE_KEY_DQ (0x09) +#define TAG_SST_IDENTIFIER2 (0x0A) +#define TAG_SST_INDEX2 (0x0B) +#define TAG_AES_KEY (0x0C) +#define TAG_WRAPPED_AES_KEY (0x0D) +#define TAG_CONTEXT (0x0E) +#define TAG_DIRECTION (0x0F) +#define TAG_IV (0x10) +#define TAG_INPUT_DATA (0x11) +#define TAG_OUTPUT_DATA (0x12) +#define TAG_AUTHENTICATION_DATA (0x13) +#define TAG_GMAC_DATA (0x14) +#define TAG_GMAC_LENGTH (0x15) +#define TAG_KEYWRAP_ALGO (0x16) +#define TAG_HASH (0x17) +#define TAG_SIGNATURE (0x18) +#define TAG_STATE (0x19) +#define TAG_VERIFICATION (0x1A) +#define TAG_CERTIFICATE (0x1B) +#define TAG_OFFSET (0x1C) +#define TAG_SIZE (0x1D) +#define TAG_SST_WRAPPING_KEY_INDEX (0x1E) +#define TAG_INTERFACE (0x1F) +#define TAG_CHUNK_NUMBER (0x23) +#define TAG_SCP_MIN_SEC_LEVEL (0x24) +#define TAG_STATUS_WORD (0x25) +/// @endcond +#endif // TGT_A70CI +// + +/* ------------------------------ */ +#define AX_CLA (0x80) + +// #define SW_WARNING_FILE_DEACTIVATED (0x6283) +// #define SW_WARNING_FILE_TERMINATED (0x6285) + +#define SW_WRONG_LENGTH (0x6700) //!< ISO7816-4 defined status word: Wrong Length of data +#define SW_SECURE_MESSAGING_NOT_SUPPORTED (0x6882) //!< ISO7816-4 defined status word +#define SW_SECURITY_STATUS_NOT_SATISFIED (0x6982) //!< ISO7816-4 defined status word +#define SW_DATA_INVALID (0x6984) //!< ISO7816-4 defined status word +#define SW_CONDITIONS_NOT_SATISFIED (0x6985) //!< ISO7816-4 defined status word: Conditions of use not satisfied, e.g. a command is not allowed, the provided identifier is not applicable or the index is out of range. +#define SW_COMMAND_NOT_ALLOWED (0x6986) //!< ISO7816-4 defined status word +#define SW_WRONG_DATA (0x6A80) //!< ISO7816-4 defined status word: Wrong data, e.g. the command does not have the right parameters or a parameter is not correct (size, structure). +#define SW_FILE_NOT_FOUND (0x6A82) //!< ISO7816-4 defined status word +#define SW_INCORRECT_P1P2 (0x6A86) //!< ISO7816-4 defined status word: Incorrect P1-P2 parameters +#define SW_INS_NOT_SUPPORTED (0x6D00) //!< ISO7816-4 defined status word: INS byte not supported +#define SW_CLA_NOT_SUPPORTED (0x6E00) //!< ISO7816-4 defined status word: CLA byte not supported +#define SW_NO_ERROR (0x9000) //!< ISO7816-4 defined status word + +#define USE_STANDARD_APDU_LEN 0 //!< Create a standard length APDU. +#define USE_EXTENDED_APDU_LEN 1 //!< Create an extended length APDU. +#define SESSION_ID_LEN 4 + +U8 SetApduHeader(apdu_t * pApdu, U8 extendedLength); +U8 AllocateAPDUBuffer(apdu_t * pApdu); +U8 FreeAPDUBuffer(apdu_t * pApdu); +void smApduAdaptLcLe(apdu_t *pApdu, U16 lc, U16 le); +void smApduAdaptLc(apdu_t *pApdu, U16 lc); +void smApduAdaptLe(apdu_t *pApdu, U16 le); +// U16 GetStatusWord(apdu_t *pApdu); +U16 smGetSw(apdu_t *pApdu, U8 *pIsOk); +void set_SessionId_Tlv(U32 sessionId); + + +U16 AddTlvItem(apdu_t * pApdu, U16 tag, U16 dataLength, const U8 *pValue); +U16 ParseResponse(apdu_t * pApdu, U16 expectedTag, U16 * pLen, U8* pValue); +U16 AddStdCmdData(apdu_t * pApdu, U16 dataLen, const U8 *data); + +U16 smApduGetResponseBody(apdu_t *pApdu, U8 *buf, U16 *bufLen); +U16 smApduAppendCmdData(apdu_t * pApdu, const U8 *data, U16 dataLen); +U16 smApduAdaptChkSum(apdu_t *pApdu, U16 chkSum); + +/** + * @brief Check and convert given hex string to array of bytes to buffer. + * + * Memory allocation needs to be done by the caller, boundary checks on the output + * are performed, null-termination is always added. + * @param[in] str: The binary data to convert. + * @param[in] buffer: buffer to which converted array to be copied. + * @param[in] buffer_len: Size of the available buffer for sanity check. + * @param[out] len: The length of the binary data written to buffer. + * @return True if conversion is successful. + */ +bool smApduGetArrayBytes(char *str, size_t *len, uint8_t * buffer, size_t buffer_len); + +/** + * @brief Parse given apdu command and return command data offset and command data length along with case-id as described in ISO/IEC FDIS 7816-3 spec. + * + * @param[in] apdu: Buffer containing APDU command. + * @param[in] apduLen: The length of APDU command. + * @param[out] data_offset: Offset of data field if present. + * @param[out] dataLen: Length of data field (LC field value) if present. + * @param[out] apdu_case: APDU txrx case accoring to 7816 spec. + * @return True if APDU command has valid format. + */ +bool smApduGetTxRxCase(uint8_t *apdu, size_t apduLen, size_t* data_offset, size_t *dataLen, apduTxRx_case_t *apdu_case); + + +#ifdef __cplusplus +} +#endif +#endif //_SM_APDU_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h new file mode 100644 index 00000000000..6fa2de7321f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h @@ -0,0 +1,119 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** +* @par Description +* This file is the communication specific Host API of the A70CM/CI and A71CH secure module. +* It also customizes the Generic Ax library for this specific product instance +* @par History +* 1.0 27-march-2014 : Initial version +* 7-may-2017 : Unified version for A70CM, CI and A71CH +* +*****************************************************************************/ +#ifndef _SM_API_ +#define _SM_API_ + +#include "sm_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define AX_HOST_LIB_MAJOR (PLUGANDTRUST_HOSTLIB_VER_MAJOR) //!< Major number A71CH Host Library +#define AX_HOST_LIB_MINOR (PLUGANDTRUST_HOSTLIB_VER_MINOR) //!< Minor (High Nibble)/Patch number (Low Nibble) of A71CH Host Library + +/*! +* @addtogroup sss_sscp_a71ch +* @{ +*/ + +#define SE_CONNECT_TYPE_START 0x000 + +typedef enum +{ + kType_SE_Conn_Type_NONE = 0, + /** Used for A71XX Family */ + kType_SE_Conn_Type_SCII2C = SE_CONNECT_TYPE_START + 2, + /** Used for PC/OSX for virtual COM Port */ + kType_SE_Conn_Type_VCOM = SE_CONNECT_TYPE_START + 3, + /** Used for Legacy JRCP V1 protocol with iMX Linux Proxy */ + kType_SE_Conn_Type_JRCP_V1 = SE_CONNECT_TYPE_START + 4, + /** Used for New JRCP Protocol */ + kType_SE_Conn_Type_JRCP_V2 = SE_CONNECT_TYPE_START + 5, + /** Used for T=1 over I2C for SE050 family */ + kType_SE_Conn_Type_T1oI2C = SE_CONNECT_TYPE_START + 6, + /** Used for Use NFC Interface to talk to SE */ + kType_SE_Conn_Type_NFC = SE_CONNECT_TYPE_START + 7, + /** Used for Use a software layer to talk to SE + * This logicaly allows double encryption of packets + * from same host and allows multi-tenenancy + * + * Channel can be deemed as "Secure Channel" where applicable. + * + * Or it may be a plain "arbiter" to allow plain communication from + * multiple threads on the same application. + */ + kType_SE_Conn_Type_Channel = SE_CONNECT_TYPE_START + 8, + + kType_SE_Conn_Type_PCSC = SE_CONNECT_TYPE_START + 9, + + kType_SE_Conn_Type_LAST, + kType_SE_Conn_Type_SIZE = 0x7FFF +} SSS_Conn_Type_t; + +#define SELECT_APPLET 0 //!< Select predefined applet +#define SELECT_NONE 1 //!< Don't issue a select +#define SELECT_SSD 2 //!< Select SSD + +/** + * Contains the information required to resume a connection with the Security Module. + * Its content is only to be interpreted by the Host Library. + * The semantics of the param1 and param2 fields depends on the link layer. + */ +typedef struct { + U16 connType; + U16 param1; //!< Useage depends on link layer + U16 param2; //!< Useage depends on link layer + U16 hostLibVersion; //!< MSByte contains major version (::AX_HOST_LIB_MAJOR); LSByte contains minor version of HostLib (::AX_HOST_LIB_MINOR) + U32 appletVersion; /*!< MSByte contains major version; + 3 leading bits of LSByte contains minor version of Applet; + Last bit of LSByte encodes whether Applet is in Debug Mode, a '1' means 'Debug Mode' is available */ + U16 sbVersion; //!< Expected to be 0x0000 + U8 select; //!< Applet selection mode +} SmCommState_t; + +/** \name Communication functions + @{ */ +U16 SM_Close(void *conn_ctx, U8 mode); +U16 SM_Connect(void *conn_ctx, SmCommState_t *commState, U8 *atr, U16 *atrLen); +U16 SM_ConnectWithAID(SmCommState_t *commState, U8* appletAID, U16 appletAIDLen, U8 *atr, U16 *atrLen); +U16 SM_RjctConnect(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen); +U16 SM_RjctConnectWithAID(const char *connectString, SmCommState_t *commState, U8* appletAID, U16 appletAIDLen, U8 *atr, U16 *atrLen); +U16 SM_I2CConnect(void **conn_ctx, SmCommState_t *commState, U8 *atr, U16 *atrLen, const char *pConnString); + +U16 SM_SendAPDU(U8 *cmd, U16 cmdLen, U8 *resp, U16 *respLen); + +#if defined(SMCOM_JRCP_V1_AM) +U16 SM_LockChannel(); +U16 SM_UnlockChannel(); +#endif + +#if defined(SMCOM_JRCP_V1_AM) +#define SM_LOCK_CHANNEL() SM_LockChannel() +#define SM_UNLOCK_CHANNEL() SM_UnlockChannel() +#else +#define SM_LOCK_CHANNEL() +#define SM_UNLOCK_CHANNEL() +#endif + +/** @}*/ + +#ifdef __cplusplus +} +#endif +#endif //_SM_API_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c new file mode 100644 index 00000000000..d69f8c010ac --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c @@ -0,0 +1,655 @@ +/* + * + * Copyright 2016-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* +* +* @par History +* 1.0 1-oct-2016 : Initial version +* +* +*****************************************************************************/ +/** +* @file sm_connect.c +* @par Description +* Implementation of basic communication functionality between Host and A71CH. +* (This file was renamed from ``a71ch_com.c`` into ``sm_connect.c``.) +*/ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include +#include +#include +#include +#include +#include "sm_api.h" +#include "sm_apdu.h" +#include "sm_errors.h" +#include "sm_types.h" + +#include "nxLog_smCom.h" +#include "nxEnsure.h" + +/// @cond + +//Also do select after opening the connection +#define OPEN_AND_SELECT 0 + +/// @endcond + +#ifdef TDA8029_UART +#include "smComAlpar.h" +#include "smUart.h" +#endif +#if defined(SCI2C) +#include "smComSCI2C.h" +#endif +#if defined(SPI) +#include "smComSCSPI.h" +#endif +#if defined(PCSC) +#include "smComPCSC.h" +#endif +#if defined(SMCOM_JRCP_V1) +#include "smComSocket.h" +#endif +#if defined(SMCOM_JRCP_V2) +#include "smComJRCP.h" +#endif +#if defined(RJCT_VCOM) +#include "smComSerial.h" +#endif +#if defined(T1oI2C) +#include "smComT1oI2C.h" +#endif +#if defined(SMCOM_PN7150) +#include "smComPN7150.h" +#endif +#if defined(SMCOM_THREAD) +#include "smComThread.h" +#endif +#if defined(SMCOM_PCSC) +#include "smComPCSC.h" +#endif +#if defined(SMCOM_RC663_VCOM) +#include "smComNxpNfcRdLib.h" +#endif + +#include "global_platf.h" + +/// @cond Optional diagnostics functionality +// #define FLOW_VERBOSE +#ifdef FLOW_VERBOSE +#define FPRINTF(...) printf(__VA_ARGS__) +#else +#define FPRINTF(...) +#endif +/// @endcond + +#if defined(SMCOM_JRCP_V1) || defined(SMCOM_JRCP_V2) +static U16 getSocketParams(const char *arg, U8 *szServer, U16 szServerLen, unsigned int *port) +{ + // the IP address is in format a.b.c.d:port, e.g. 10.0.0.1:8080 + int nSuccess; + U16 rv = SW_OK; + + ENSURE_OR_EXIT_WITH_STATUS_ON_ERROR(strlen(arg) < szServerLen, rv, ERR_BUF_TOO_SMALL); + + // First attempt at parsing: server IP-address passed, sscanf will return 2 upon successfull parsing + nSuccess = sscanf(arg, "%15[0-9.]:%5u[0-9]", szServer, (unsigned int *)port); + + if (nSuccess == 2) { + return SW_OK; + } + else { + // Second attempt at parsing: server name passed instead of IP-address + unsigned int i; + int fColonFound = 0; + + for (i = 0; i < strlen(arg); i++) { + if (arg[i] == ':') { + szServer[i] = 0; + fColonFound = 1; + // PRINTF("servername: %s\r\n", szServer); + break; + } + else { + szServer[i] = arg[i]; + } + } + + if ((fColonFound == 1) && (i != 0)) { + nSuccess = sscanf(&arg[i], ":%5u[0-9]", (unsigned int *)port); + ENSURE_OR_EXIT_WITH_STATUS_ON_ERROR(nSuccess != 1, rv, SW_OK); + } + } + rv = ERR_NO_VALID_IP_PORT_PATTERN; +exit: + return rv; +} + +/** +* Establishes communication with the Security Module via a Remote JC Terminal Server +* (RJCT-Server). +* Next it will invoke ::SM_Connect and select the A71CH applet on the Secure Module +* +* \note Because connecting via an RJCT-server requires an extra parameter (the server IP:Port) +* an additional function is required on top of ::SM_Connect +* +* @param[in,out] connectString ip:port as string +* @param[in,out] commState +* @param[in,out] atr +* @param[in,out] atrLen +* +* @retval ::SW_OK Upon successful execution +*/ +U16 SM_RjctConnectSocket(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ + U8 szServer[128]; + U16 szServerLen = sizeof(szServer); + U16 rv = 0; + unsigned int port = 0; +#if defined(SMCOM_JRCP_V2) + char hostname[32] = {0}; +#endif + +#ifndef A71_IGNORE_PARAM_CHECK + if ((connectString == NULL) || (commState == NULL) || (atr == NULL) || (atrLen == 0)) { + return ERR_API_ERROR; + } +#endif + + rv = getSocketParams(connectString, szServer, szServerLen, (unsigned int *)&port); + +#if defined(SMCOM_JRCP_V1) + FPRINTF("Connection to secure element over socket to %s\r\n", connectString); + if (rv != SW_OK) { + return rv; + } + // NOTE-MMA: The usage of the sss type kType_SE_Conn_Type_JRCP_V1 leads to a circular + // dependency regarding the inclusion of header files. + // if (commState->connType == kType_SE_Conn_Type_JRCP_V1) { + rv = smComSocket_Open(conn_ctx, szServer, (U16)port, atr, atrLen); + // } + +#endif +#if defined(SMCOM_JRCP_V2) + if (commState->connType == kType_SE_Conn_Type_JRCP_V2) { + if (sizeof(hostname) < strlen(connectString)) { + return ERR_API_ERROR; + } + strncpy(hostname, connectString, strlen(connectString)); + rv = smComJRCP_Open(conn_ctx, strtok(hostname, ":"), port); + } + +#endif + if (rv != SMCOM_OK) { + LOG_E("Error on smComSocket_Open: 0x%04X\r\n", rv); + return rv; + } + + if (conn_ctx == NULL) { + rv = SM_Connect(NULL, commState, atr, atrLen); + } + else { + rv = SM_Connect(*conn_ctx, commState, atr, atrLen); + } + + return rv; +} +#endif /* defined(SMCOM_JRCP_V1) || defined (SMCOM_JRCP_V2) */ + +#ifdef RJCT_VCOM +U16 SM_RjctConnectVCOM(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ + U32 status; + +#ifndef A71_IGNORE_PARAM_CHECK + if ((connectString == NULL) || (commState == NULL) || (atr == NULL) || (atrLen == 0)) { + return ERR_API_ERROR; + } +#endif + + status = smComVCom_Open(conn_ctx, connectString); + + if (status == 0) { + if (conn_ctx == NULL) { + status = smComVCom_GetATR(NULL, atr, atrLen); + if (status == 0) { + status = (U16)SM_Connect(NULL, commState, atr, atrLen); + if (status != SMCOM_OK) { + SM_Close(NULL, 0); + } + } + else { + SM_Close(NULL, 0); + } + } + else { + status = smComVCom_GetATR(*conn_ctx, atr, atrLen); + if (status == 0) { + status = (U16)SM_Connect(*conn_ctx, commState, atr, atrLen); + } + else { + SM_Close(NULL, 0); + } + } + } + else { + *atrLen = 0; + } + + return (U16)status; +} +#endif // RJCT_VCOM + +#ifdef SMCOM_RC663_VCOM +U16 SM_RjctConnectNxpNfcRdLib(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ + U32 status; + + if ((connectString == NULL) || (commState == NULL) || (atr == NULL) || (atrLen == 0)) { + return ERR_API_ERROR; + } + + status = smComNxpNfcRdLib_OpenVCOM(conn_ctx, connectString); + + if (status == 0) { + status = (U16)SM_Connect(conn_ctx, commState, atr, atrLen); + } + else { + *atrLen = 0; + } + if (status == SMCOM_OK) { + *atrLen = 0; + } + + return (U16)status; +} +#endif + +#ifdef SMCOM_PCSC +U16 SM_RjctConnectPCSC(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ + U32 status = SMCOM_OK; + +#ifndef A71_IGNORE_PARAM_CHECK + if ( //(connectString == NULL) || + (commState == NULL) || (atr == NULL) || (atrLen == 0)) { + return ERR_API_ERROR; + } +#endif + + status = smComPCSC_Open(connectString); + + if (status == SMCOM_OK) { + if (conn_ctx == NULL) { + status = (U16)SM_Connect(NULL, commState, atr, atrLen); + } + else { + status = (U16)SM_Connect(*conn_ctx, commState, atr, atrLen); + } + } + else { + *atrLen = 0; + } + + return (U16)status; +} +#endif // RJCT_VCOM + +U16 SM_RjctConnect(void **conn_ctx, const char *connectString, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ +#if RJCT_VCOM || SMCOM_JRCP_V1 || SMCOM_JRCP_V2 || SMCOM_RC663_VCOM + bool is_socket = FALSE; + bool is_vcom = FALSE; + AX_UNUSED_ARG(is_socket); + AX_UNUSED_ARG(is_vcom); +#endif + +#if RJCT_VCOM || SMCOM_RC663_VCOM + if (NULL == connectString) { + is_vcom = FALSE; + } + else if (0 == strncmp("COM", connectString, sizeof("COM") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("\\\\.\\COM", connectString, sizeof("\\\\.\\COM") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("/tty/", connectString, sizeof("/tty/") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("/dev/tty", connectString, sizeof("/dev/tty") - 1)) { + is_vcom = TRUE; + } +#endif +#if SMCOM_JRCP_V1 || SMCOM_JRCP_V2 + if (NULL == connectString) { + LOG_W("connectString is NULL. Aborting."); + return ERR_NO_VALID_IP_PORT_PATTERN; + } + if (NULL != strchr(connectString, ':')) { + is_socket = TRUE; + } +#endif +#if RJCT_VCOM + if (is_vcom) { + return SM_RjctConnectVCOM(conn_ctx, connectString, commState, atr, atrLen); + } + else { + LOG_W("Build is compiled for VCOM. connectString='%s' does not look like COMPort",connectString); + LOG_W("e.g. connectString are COM3, \\\\.\\COM5, /dev/tty.usbmodem1432301, etc."); + } +#endif +#if SMCOM_RC663_VCOM + if (is_vcom) { + return SM_RjctConnectNxpNfcRdLib(conn_ctx, connectString, commState, atr, atrLen); + } + else { + LOG_W("Build is compiled for RC663_VCOM. connectString='%s' does not look like COMPort",connectString); + LOG_W("e.g. connectString are COM3, \\\\.\\COM5, /dev/tty.usbmodem1432301, etc."); + } +#endif +#if SMCOM_JRCP_V1 || SMCOM_JRCP_V2 + if (is_socket) { + return SM_RjctConnectSocket(conn_ctx, connectString, commState, atr, atrLen); + } +#endif +#if SMCOM_PCSC + if (NULL != commState) { + return SM_RjctConnectPCSC(conn_ctx, connectString, commState, atr, atrLen); + } +#endif + LOG_W( + "Can not use connectString='%s' in the current build configuration.\n\tPlease select correct smCom interface " + "and re-compile!\n", + connectString); + return ERR_NO_VALID_IP_PORT_PATTERN; +} + +#if defined(SMCOM_JRCP_V1) || defined(SMCOM_JRCP_V2) || defined(RJCT_VCOM) || \ + defined(SMCOM_PCSC) +#else +U16 SM_I2CConnect(void **conn_ctx, SmCommState_t *commState, U8 *atr, U16 *atrLen, const char *pConnString) +{ + U16 status = SMCOM_COM_FAILED; +#if defined(T1oI2C) + status = smComT1oI2C_Init(conn_ctx, pConnString); +#elif defined (SCI2C) + status = smComSCI2C_Init(conn_ctx, pConnString); +#endif + if (status != SMCOM_OK) { + return status; + } + if (conn_ctx == NULL) { + return SM_Connect(NULL, commState, atr, atrLen); + } + else { + return SM_Connect(*conn_ctx, commState, atr, atrLen); + } +} +#endif + +/** +* Establishes the communication with the Security Module (SM) at the link level and +* selects the A71CH applet on the SM. The physical communication layer used (e.g. I2C) +* is determined at compilation time. +* +* @param[in,out] commState +* @param[in,out] atr +* @param[in,out] atrLen +* +* @retval ::SW_OK Upon successful execution +*/ +U16 SM_Connect(void *conn_ctx, SmCommState_t *commState, U8 *atr, U16 *atrLen) +{ + U16 sw = SW_OK; +#if !defined(IPC) + +#ifdef APPLET_NAME + unsigned char appletName[] = APPLET_NAME; +#endif // APPLET_NAME +#ifdef SSD_NAME + unsigned char ssdName[] = SSD_NAME; +#endif + U16 selectResponseDataLen = 0; + U8 selectResponseData[256] = {0}; + U16 uartBR = 0; + U16 t1BR = 0; +#endif +#ifdef TDA8029_UART + U32 status = 0; +#endif + +#ifndef A71_IGNORE_PARAM_CHECK + ENSURE_OR_EXIT_WITH_STATUS_ON_ERROR(((commState != NULL) && (atr != NULL) && (atrLen != 0)), sw, ERR_API_ERROR) +#endif + +#ifdef TDA8029_UART + if ((*atrLen) <= 33) + return ERR_API_ERROR; + + smComAlpar_Init(); + status = smComAlpar_AtrT1Configure(ALPAR_T1_BAUDRATE_MAX, atr, atrLen, &uartBR, &t1BR); + if (status != SMCOM_ALPAR_OK) { + commState->param1 = 0; + commState->param2 = 0; + FPRINTF("smComAlpar_AtrT1Configure failed: 0x%08X\r\n", status); + return ERR_CONNECT_LINK_FAILED; + } +#elif defined SMCOM_PN7150 + sw = smComPN7150_Open(0, 0x00, atr, atrLen); +#elif defined(SCI2C) + sw = smComSCI2C_Open(conn_ctx, ESTABLISH_SCI2C, 0x00, atr, atrLen); +#elif defined(SPI) + smComSCSPI_Init(ESTABLISH_SCI2C, 0x00, atr, atrLen); +#elif defined(T1oI2C) + sw = smComT1oI2C_Open(conn_ctx, ESE_MODE_NORMAL, 0x00, atr, atrLen); +#elif defined(SMCOM_JRCP_V1) || defined(SMCOM_JRCP_V2) || defined(PCSC) || defined(SMCOM_PCSC) + if (atrLen != NULL) + *atrLen = 0; + AX_UNUSED_ARG(atr); + AX_UNUSED_ARG(atrLen); +#elif defined(RJCT_VCOM) +#elif defined(SMCOM_THREAD) + sw = smComThread_Open(atr, atrLen); +#endif // TDA8029_UART + +#if !defined(IPC) + commState->param1 = t1BR; + commState->param2 = uartBR; + commState->hostLibVersion = (AX_HOST_LIB_MAJOR << 8) + AX_HOST_LIB_MINOR; + commState->appletVersion = 0xFFFF; + commState->sbVersion = 0xFFFF; + +#ifdef APPLET_NAME + if (sw == SMCOM_OK) { + selectResponseDataLen = sizeof(selectResponseData); + /* CARD */ + if (commState->select == SELECT_NONE) { + /* Use Case just Connect to SE (smCom) and no kind of applet selection */ + sw = SMCOM_OK; + selectResponseDataLen = 0; + } + else if (commState->select == SELECT_SSD) { +#ifdef SSD_NAME + /* Rotate keys Use Case Connect to SE and Select SSD */ + /* Select SSD */ + sw = GP_Select(conn_ctx, (U8 *)&ssdName, sizeof(ssdName), selectResponseData, &selectResponseDataLen); +#else + sw = SMCOM_COM_FAILED; +#endif + } + else + { +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM || SSS_HAVE_A71CL + /* Select card manager */ + GP_Select(conn_ctx, (U8 *)&appletName, 0, selectResponseData, &selectResponseDataLen); + selectResponseDataLen = sizeof(selectResponseData); +#endif + /* Select the applet */ + sw = GP_Select(conn_ctx, (U8 *)&appletName, APPLET_NAME_LEN, selectResponseData, &selectResponseDataLen); + } + + if (sw == SW_FILE_NOT_FOUND) { + // Applet can not be selected (most likely it is simply not installed) + LOG_E("Can not select Applet=%s'", SE_NAME); + LOG_MAU8_E("Failed (SW_FILE_NOT_FOUND) selecting Applet. ", appletName, APPLET_NAME_LEN); + return sw; + } + else if (sw != SW_OK) { + LOG_E("SM_CONNECT Failed."); + sw = ERR_CONNECT_SELECT_FAILED; + } + else { +#ifdef FLOW_VERBOSE + if (selectResponseDataLen > 0) { + LOG_MAU8_I("selectResponseData", selectResponseData, selectResponseDataLen); + } +#endif // FLOW_VERBOSE +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM + if (selectResponseDataLen >= 2) { + commState->appletVersion = (selectResponseData[0] << 8) + selectResponseData[1]; + if (selectResponseDataLen == 4) { + commState->sbVersion = (selectResponseData[2] << 8) + selectResponseData[3]; + } + else if (selectResponseDataLen == 2) { + commState->sbVersion = 0x0000; + } + } + else { + sw = ERR_CONNECT_SELECT_FAILED; + } +#elif SSS_HAVE_A71CL + if (selectResponseDataLen == 0) { + commState->appletVersion = 0; + commState->sbVersion = 0x0000; + } +#endif // SSS_HAVE_A71CH / SSS_HAVE_A71CL +#if SSS_HAVE_SE05X + if (selectResponseDataLen == 5 || selectResponseDataLen == 4 || selectResponseDataLen == 7) { + // 2.2.4 returns 4 bytes, 2.2.4.[A,B,C] + // 2.3.0 returns 5 bytes, 2.3.0.[v1].[v2] + // 2.5.3 returns 7 bytes, + commState->appletVersion = 0; + commState->appletVersion |= selectResponseData[0]; + commState->appletVersion <<= 8; + commState->appletVersion |= selectResponseData[1]; + commState->appletVersion <<= 8; + commState->appletVersion |= selectResponseData[2]; + commState->appletVersion <<= 8; + // commState->appletVersion |= selectResponseData[3]; + commState->sbVersion = 0x0000; + } + else { + } +#endif // SSS_HAVE_SE05X + } + } +#endif /* Applet Name*/ +#endif // !defined(IPC) +exit: + return sw; +} + +/** + * Closes the communication with the Security Module + * A new connection can be established by calling ::SM_Connect + * + * @param[in] mode Specific information that may be required on the link layer + * + * @retval ::SW_OK Upon successful execution + */ +U16 SM_Close(void *conn_ctx, U8 mode) +{ + U16 sw = SW_OK; + +#if defined(SCI2C) + sw = smComSCI2C_Close(mode); +#endif +#if defined(SPI) + sw = smComSCSPI_Close(mode); +#endif +#if defined(PCSC) + sw = smComPCSC_Close(mode); +#endif +#if defined(T1oI2C) + sw = smComT1oI2C_Close(conn_ctx, mode); +#endif +#if defined(SMCOM_JRCP_V1) + AX_UNUSED_ARG(mode); + sw = smComSocket_Close(); +#endif +#if defined(SMCOM_JRCP_V2) + AX_UNUSED_ARG(mode); + sw = smComJRCP_Close(conn_ctx, mode); +#endif +#if defined(RJCT_VCOM) + AX_UNUSED_ARG(mode); + sw = smComVCom_Close(conn_ctx); +#endif +#if defined(SMCOM_THREAD) + AX_UNUSED_ARG(mode); + sw = smComThread_Close(); +#endif +#if defined(SMCOM_RC663_VCOM) + AX_UNUSED_ARG(mode); + smComNxpNfcRdLib_Close(); +#endif + smCom_DeInit(); + + return sw; +} + +/** + * Sends the command APDU to the Secure Module and retrieves the response APDU. + * The latter consists of the concatenation of the response data (possibly none) and the status word (2 bytes). + * + * The command APDU and response APDU are not interpreted by the host library. + * + * The command/response APDU sizes must lay within the APDU size limitations + * + * @param[in] cmd command APDU + * @param[in] cmdLen length (in byte) of \p cmd + * @param[in,out] resp response APDU (response data || response status word) + * @param[in,out] respLen IN: Length of resp buffer (\p resp) provided; OUT: effective length of response retrieved. + * + * @retval ::SW_OK Upon successful execution + */ +U16 SM_SendAPDU(U8 *cmd, U16 cmdLen, U8 *resp, U16 *respLen) +{ + U32 status = 0; + U32 respLenLocal; + +#ifndef A71_IGNORE_PARAM_CHECK + ENSURE_OR_RETURN_ON_ERROR(((cmd != NULL) && (resp != NULL) && (respLen != NULL)), ERR_API_ERROR); +#endif + + respLenLocal = *respLen; + + status = smCom_TransceiveRaw(NULL, cmd, cmdLen, resp, &respLenLocal); + *respLen = (U16)respLenLocal; + + return (U16)status; +} + + +#if defined(SMCOM_JRCP_V1_AM) +U16 SM_LockChannel() +{ + return smComSocket_LockChannel(); +} + +U16 SM_UnlockChannel() +{ + return smComSocket_UnlockChannel(); +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c new file mode 100644 index 00000000000..a9170893478 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c @@ -0,0 +1,74 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** +* @par Description +* This file implements generic APDU response evaluation. +* @par History +* 1.0 20-feb-2012 : Initial version +* +*****************************************************************************/ + +#include +#include + +#include "scp.h" +#include "sm_apdu.h" +#include "sm_errors.h" +#include "nxLog_hostLib.h" +#include "nxEnsure.h" + +/** +* Returns the status word of a response APDU when no response data is expected. +* @param[in] pApdu Pointer to the APDU. +* @retval ::ERR_WRONG_RESPONSE In case the response contains more than only the status word +* @returns status word (in case the response is 2 byte long) +*/ +U16 CheckNoResponseData(apdu_t * pApdu) +{ + U16 rv = ERR_GENERAL_ERROR; + U8 isOk = 0x00; + ENSURE_OR_GO_EXIT(pApdu != NULL); + + if (pApdu->rxlen != 2) + { + // printf("%d: pApdu->rxlen = %d", __LINE__, pApdu->rxlen); + rv = ERR_WRONG_RESPONSE; + } + else + { + // printBytestring("CheckNoResponseData", pApdu->pBuf, pApdu->rxlen); + rv = smGetSw(pApdu, &isOk); + } + +exit: + return rv; +} + +/** +* Returns the status word of a response APDU when no response data is expected. +* @param[in] rawResponse Pointer to the raw response +* @param[in] rawResponseLen Length of \p rawResponse +* @retval ::ERR_WRONG_RESPONSE In case the response contains more than only the status word +* @returns status word (in case the response is 2 byte long) +*/ +U16 CheckNoResponseDataRaw(U8 *rawResponse, U16 rawResponseLen) +{ + U16 rv = ERR_GENERAL_ERROR; + ENSURE_OR_GO_EXIT(rawResponse != NULL); + + if (rawResponseLen != 2) + { + rv = ERR_WRONG_RESPONSE; + } + else + { + rv = (rawResponse[0] << 8) + rawResponse[1]; + } + +exit: + return rv; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h new file mode 100644 index 00000000000..b5ba47077aa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h @@ -0,0 +1,31 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * + * @par Description + * This file provides an interface to generic APDU response evaluation. + * @par History + * 1.0 20-feb-2012 : Initial version + * + */ + +#ifndef _SM_ERRORS_ +#define _SM_ERRORS_ + +#include "apduComm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +U16 CheckNoResponseData(apdu_t * pApdu); +U16 CheckNoResponseDataRaw(U8 *rawResponse, U16 rawResponseLen); + +#ifdef __cplusplus +} +#endif +#endif //_SM_ERRORS_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c new file mode 100644 index 00000000000..cdefce11dc4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c @@ -0,0 +1,32 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "sm_printf.h" + + + +#define MAX_SER_BUF_SIZE (1024) + +void sm_printf(uint8_t dev, const char * format, ...) +{ + uint8_t buffer[MAX_SER_BUF_SIZE + 1]; + va_list vArgs; + + //dev = dev; // avoids warning; dev can be used to determine output channel + + va_start(vArgs, format); +#if defined(_WIN32) && defined(_MSC_VER) + vsnprintf_s((char *)buffer, MAX_SER_BUF_SIZE, MAX_SER_BUF_SIZE, (char const *)format, vArgs); +#else + vsnprintf((char *)buffer, MAX_SER_BUF_SIZE, (char const *)format, vArgs); +#endif + va_end(vArgs); + + PRINTF("%s", buffer); +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h new file mode 100644 index 00000000000..56220f1b02e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h @@ -0,0 +1,163 @@ +/* + * + * Copyright 2016-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * This file defines A7-series specific types + * @par History + * 1.0 20-feb-2012 : Initial version + * + */ + +#ifndef _SM_TYPES_H_ +#define _SM_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__GNUC__) || defined(__arm__) || defined(__ICCARM__) +#include +#include +#include +#endif /* __GNUC__ || __arm__ || iccarm */ + +#if defined(__ICCARM__) +#include "stddef.h" +#endif /* __ICCARM__ */ + +#if defined(_MSC_VER) && _MSC_VER >= 1600 +#include +#if _MSC_VER >= 1800 +#include +#endif +#endif /* _MSC_VER */ + +typedef uint8_t U8; +typedef uint16_t U16; +typedef uint32_t U32; + +typedef int8_t S8; +typedef int16_t S16; +typedef int32_t S32; + +#if !defined(__cplusplus) && !defined(__GNUC__) && !defined(__arm__) && !defined(__ICCARM__) +#ifdef _MSC_VER +#if _MSC_VER < 1600 +typedef unsigned char bool; // C++ and GCC has bool. +#define false(0) +#define true(1) +#endif //_MSC_VER < 1600 +#else // _MSC_VER +typedef unsigned char bool; // C++ and GCC has bool. +#endif +#endif /* bool */ + +#ifndef FALSE +#define FALSE false +#endif + +#ifndef TRUE +#define TRUE true +#endif + +/** @define AX_EMBEDDED Plaform is embedded like Kinetis / LPC / i.MX RT / Freedom Series */ +#if defined(FREEDOM) || defined(IMX_RT) || defined(CPU_LPC54018) || defined(LPC_55x) || defined(QN9090DK6) +#define AX_EMBEDDED 1 +#elif defined(AX_EMBEDDED) +/* OK */ +#else +#define AX_EMBEDDED 0 +#endif + +/** + * Identification of ECC curve. Not all turnkey solutions cover all these ECC curves. + */ +typedef enum +{ + ECCCurve_NIST_P192 = 0x01, + ECCCurve_NIST_P224 = 0x02, + ECCCurve_NIST_P256 = 0x03, /**< NIST Curve with 256 bits */ + ECCCurve_BrainPoolP192r1 = 0x04, + ECCCurve_BrainPoolP224r1 = 0x05, + ECCCurve_BrainPoolP256r1 = 0x06 +} ECCCurve_t; + +/** + * Identification of hash algorithm + */ +typedef enum +{ + HASHAlgo_SHA1 = 0x01, + HASHAlgo_SHA256 = 0x02 +} HASHAlgo_t; + +typedef U16 SM_Error_t; + +#define AX_UNUSED_ARG(x) (void)(x) + +// The following defines are visible at the smCom layer +// Because they are also used in the platform specific implementation +// layer, they have ended up in this include file. +// They do not belong here from a structural point of view. +#define SMCOM_CLOSE_MODE_STD 0x00 +#define SMCOM_CLOSE_MODE_TERMINATE 0x01 + +// The following is a set of predefined return values. + +/* Don't use +// Protocol error codes +#define BAD_SEQ_NUMBER 0x8000 +#define UNAUTH_CLIENT 0x8001 +#define SEND_ERROR 0x8002 +#define UNKNOW_ORDER 0x8003 +*/ + +/* ------------------------------ */ +// Error/status word +#define SW_OK (0x9000) //!< Operation successfull + +#define ERR_CONNECT_LINK_FAILED (0x7001) +#define ERR_CONNECT_SELECT_FAILED (0x7002) +#define ERR_COMM_ERROR (0x7003) //!< Generic communication error +#define ERR_NO_VALID_IP_PORT_PATTERN (0x8000) +#define ERR_COM_ALREADY_OPEN (0x7016) //!< Communication link is already open with device + +/* Range 0x701x is reserved for Error codes defined in smCom.h */ +// #define SMCOM_SND_FAILED 0x7010 +// #define SMCOM_RCV_FAILED 0x7011 + +#define ERR_MEMORY (0x7020) //!< Memory allocation error +#define ERR_GENERAL_ERROR (0x7021) //!< Non-specific error code +#define ERR_WRONG_RESPONSE (0x7022) //!< Semantic error discovered while parsing APDU response +#define ERR_API_ERROR (0x7023) //!< Illegal parameter value passed to API +#define ERR_TLV_MISSING (0x7024) //!< Specific TAG is missing from APDU response +#define ERR_HASH_COMPARE_FAILS (0x7025) +#define ERR_BUF_TOO_SMALL (0x7026) //!< Buffer provided is too small +#define ERR_CRYPTO_ENGINE_FAILED \ + (0x7027) //!< The crypto engine (implemented underneath a crypto abstraction layer) failed to provide a crypto service. +#define ERR_PATTERN_COMPARE_FAILED (0x7028) +#define ERR_NOT_IMPLEMENTED (0x7029) +#define ERR_FILE_SYSTEM (0x7030) +#define ERR_NO_PRIVATE_KEY (0x7031) +#define ERR_IDENT_IDX_RANGE (0x7032) //!< Identifier or Index of Reference Key is out of bounds +#define ERR_CRC_CHKSUM_VERIFY (0x7033) //!< CRC checksum verify error +#define ERR_INTERNAL_BUF_TOO_SMALL (0x7034) //!< In A71CH PSP 1.6 this had value 0x7033. Code was already taken by A71CL + +#define SCP_OK (SW_OK) +#define SCP_UNDEFINED_CHANNEL_ID (0x7041) //!< Undefined SCP channel identifier +#define SCP_FAIL (0x7042) +#define SCP_CARD_CRYPTOGRAM_FAILS_TO_VERIFY (0x7043) +#define SCP_PARAMETER_ERROR (0x7044) + +#define SCP_RSP_MAC_FAIL (0x7050) //!< MAC on APDU response is not correct +#define SCP_DECODE_FAIL (0x7051) //!< Encrypted Response did not decode to correctly padded plaintext + +#ifdef __cplusplus +} +#endif + +#endif // _SM_TYPES_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c new file mode 100644 index 00000000000..cfcfda378b2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c @@ -0,0 +1,361 @@ +/* +* +* Copyright 2018,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include "sm_printf.h" + +#if USE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#endif + +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#define USE_LOCK 1 +#else +#define USE_LOCK 0 +#endif +#if defined(_MSC_VER) +#include +#endif + +#define COLOR_RED "\033[0;31m" +#define COLOR_GREEN "\033[0;32m" +#define COLOR_YELLOW "\033[0;33m" +#define COLOR_BLUE "\033[0;34m" +#define COLOR_RESET "\033[0m" + +#define szCRLF "\r\n" +#define szLF "\n" + +static void setColor(int level); +static void reSetColor(void); + +#if defined(_MSC_VER) +static HANDLE sStdOutConsoleHandle = INVALID_HANDLE_VALUE; +static void msvc_setColor(int level); +static void msvc_reSetColor(void); +#define szEOL szLF +#endif + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include +static void ansi_setColor(int level); +static void ansi_reSetColor(void); +#if AX_EMBEDDED +#define szEOL szCRLF +#else +#define szEOL szLF +#endif +#endif /* __GNUC__ && !defined(__ARMCC_VERSION) */ + +#ifndef szEOL +#define szEOL szCRLF +#endif + +/* Set this to do not widen the logs. + * + * When set to 0, and logging is verbose, it looks like this + * + * APDU:DEBUG:ReadECCurveList [] + * smCom:DEBUG:Tx> (Len=4) + * 80 02 0B 25 + * smCom:DEBUG: (Len=4) + * => 80 02 0B 25 + * smCom:DEBUG: 41 82 00 11 01 01 02 01 01 01 01 01 01 01 01 01 + * 01 01 01 01 01 90 00 + * + */ +#define COMPRESSED_LOGGING_STYLE 0 + +/* Set this to 1 if you want colored logs with GCC based compilers */ +#define USE_COLORED_LOGS 1 + +#if NX_LOG_SHORT_PREFIX +static const char *szLevel[] = {"E", "W", "I", "D"}; +#else +static const char *szLevel[] = {"ERROR", "WARN ", "INFO ", "DEBUG"}; +#endif + +#if AX_EMBEDDED +#define TAB_SEPRATOR "\t" +#else +#define TAB_SEPRATOR " " +#endif + +#if defined(SMCOM_JRCP_V2) +#include "smCom.h" +#endif + +#if USE_RTOS +static SemaphoreHandle_t gLogginglock; +#elif (__GNUC__ && !AX_EMBEDDED) +#include +/* Only for base session with os */ +static pthread_mutex_t gLogginglock; +#endif +static void nLog_AcquireLock(); +static void nLog_ReleaseLock(); +#if USE_LOCK +static uint8_t lockInitialised = false; +#endif +static void nLog_AcquireLock() +{ +#if USE_LOCK + if (lockInitialised) { +#if USE_RTOS + if (xSemaphoreTake(gLogginglock, portMAX_DELAY) != pdTRUE) { + PRINTF("Acquiring logging semaphore failed"); + } +#elif (__GNUC__ && !AX_EMBEDDED) + if (pthread_mutex_lock(&gLogginglock) != 0) { + PRINTF("Acquiring logging mutext failed"); + } +#endif + } +#endif +} + +static void nLog_ReleaseLock() +{ +#if USE_LOCK + if (lockInitialised) { +#if USE_RTOS + if (xSemaphoreGive(gLogginglock) != pdTRUE) { + PRINTF("Releasing logging semaphore failed"); + } +#elif (__GNUC__ && !AX_EMBEDDED) + if (pthread_mutex_unlock(&gLogginglock) != 0) { + PRINTF("Releasing logging semaphore failed"); + } +#endif + } +#endif +} + +uint8_t nLog_Init() +{ +#if USE_LOCK +#if USE_RTOS + gLogginglock = xSemaphoreCreateMutex(); + if (gLogginglock == NULL) { + PRINTF("xSemaphoreCreateMutex failed"); + return 1; + } +#elif (__GNUC__ && !AX_EMBEDDED) + if (pthread_mutex_init(&gLogginglock, NULL) != 0) { + PRINTF("pthread_mutex_init failed"); + return 1; + } +#endif + lockInitialised = true; +#endif + return 0; +} + +void nLog_DeInit() +{ +#if USE_LOCK +#if USE_RTOS + if (gLogginglock != NULL) { + vSemaphoreDelete(gLogginglock); + gLogginglock = NULL; + } +#elif (__GNUC__ && !AX_EMBEDDED) + pthread_mutex_destroy(&gLogginglock); +#endif + lockInitialised = false; +#endif +} + +/* Used for scenarios other than LPC55S_NS */ +void nLog(const char *comp, int level, const char *format, ...) +{ + nLog_AcquireLock(); + setColor(level); + PRINTF("%-6s:%s:", comp, szLevel[level-1]); + if (format == NULL) { + /* Nothing */ +#ifdef SMCOM_JRCP_V2 + smCom_Echo(NULL, comp, szLevel[level-1], ""); +#endif // SMCOM_JRCP_V2 + } + else if (format[0] == '\0') { + /* Nothing */ +#ifdef SMCOM_JRCP_V2 + smCom_Echo(NULL, comp, szLevel[level-1], ""); +#endif // SMCOM_JRCP_V2 + } + else { + char buffer[256]; + size_t size_buff = sizeof(buffer) / sizeof(buffer[0]) - 1; + va_list vArgs; + va_start(vArgs, format); + vsnprintf(buffer, size_buff, format, vArgs); + va_end(vArgs); + PRINTF("%s", buffer); +#ifdef SMCOM_JRCP_V2 + smCom_Echo(NULL, comp, szLevel[level-1], buffer); +#endif // SMCOM_JRCP_V2 + } + reSetColor(); + PRINTF(szEOL); + nLog_ReleaseLock(); +} + +void nLog_au8(const char *comp, int level, const char *message, const unsigned char *array, size_t array_len) +{ + size_t i; + nLog_AcquireLock(); + setColor(level); + PRINTF("%-6s:%s:%s (Len=%" PRId32 ")", comp, szLevel[level-1], message, (int32_t)array_len); + for (i = 0; i < array_len; i++) { + if (0 == (i % 16)) { + PRINTF(szEOL); + if (0 == i) { +#if COMPRESSED_LOGGING_STYLE + PRINTF("=>"); +#endif + PRINTF(TAB_SEPRATOR); + } + else { + PRINTF(TAB_SEPRATOR); + } + } +#if !COMPRESSED_LOGGING_STYLE + if (0 == (i % 4)) { + PRINTF(TAB_SEPRATOR); + } +#endif + PRINTF("%02X ", array[i]); + } + reSetColor(); + PRINTF(szEOL); + nLog_ReleaseLock(); +} + +static void setColor(int level) +{ +#if defined(_MSC_VER) + msvc_setColor(level); +#endif +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + ansi_setColor(level); +#endif +} + +static void reSetColor(void) +{ +#if defined(_MSC_VER) + msvc_reSetColor(); +#endif +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + ansi_reSetColor(); +#endif +} + +#if defined(_MSC_VER) && USE_COLORED_LOGS +static void msvc_setColor(int level) +{ +#if USE_COLORED_LOGS + WORD wAttributes = 0; + if (sStdOutConsoleHandle == INVALID_HANDLE_VALUE) { + sStdOutConsoleHandle = GetStdHandle(STD_OUTPUT_HANDLE); + } + switch (level) { + case NX_LEVEL_ERROR: + wAttributes = FOREGROUND_RED | FOREGROUND_INTENSITY; + break; + case NX_LEVEL_WARN: + wAttributes = FOREGROUND_RED | FOREGROUND_BLUE | FOREGROUND_INTENSITY; + break; + case NX_LEVEL_INFO: + wAttributes = FOREGROUND_GREEN; + break; + case NX_LEVEL_DEBUG: + /* As of now put color here. All normal printfs would be in WHITE + * Later, remove this color. + */ + wAttributes = FOREGROUND_RED | FOREGROUND_GREEN; + break; + default: + wAttributes = FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED; + } + SetConsoleTextAttribute(sStdOutConsoleHandle, wAttributes); +#endif // USE_COLORED_LOGS +} + +static void msvc_reSetColor() +{ +#if USE_COLORED_LOGS + msvc_setColor(-1 /* default */); +#endif // USE_COLORED_LOGS +} +#endif + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +static void ansi_setColor(int level) +{ +#if USE_COLORED_LOGS +#if !AX_EMBEDDED + if (!isatty(fileno(stdout))) { + return; + } +#endif + + switch (level) { + case NX_LEVEL_ERROR: + PRINTF(COLOR_RED); + break; + case NX_LEVEL_WARN: + PRINTF(COLOR_YELLOW); + break; + case NX_LEVEL_INFO: + PRINTF(COLOR_BLUE); + break; + case NX_LEVEL_DEBUG: + /* As of now put color here. All normal printfs would be in WHITE + * Later, remove this color. + */ + PRINTF(COLOR_GREEN); + break; + default: + PRINTF(COLOR_RESET); + } +#endif // USE_COLORED_LOGS +} + +static void ansi_reSetColor() +{ +#if USE_COLORED_LOGS +#if !AX_EMBEDDED + if (!isatty(fileno(stdout))) { + return; + } +#endif + PRINTF(COLOR_RESET); +#endif // USE_COLORED_LOGS +} +#endif + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.h new file mode 100644 index 00000000000..a520a5704e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.h @@ -0,0 +1,107 @@ +/* +* +* Copyright 2018 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef NX_LOG_H +#define NX_LOG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * + * Overview + * ========================================== + * + * These set of files help control logging levels in + * the applicaiton. + * + * The overall idea is to + * - Control logging at mutiple levels + * - Fine gain control of logging + * - Easy for the devleoper to add log messages + * - Easy for the devleoper to add/remove log components + * - Focus on embedded systems + * + * + * Control logging at mutiple levels + * ========================================== + * + * Each component can log one of the following levels. + * DEBUG - For the developer. Too much verbsity. + * INFO - General Information. Easy for end user to keep track what is happening. + * WARN - Some error occured, but can be handled + * ERROR - Some erro roccured, but no nice way to handle + * + * For each level, the logging APIs, LOG_D, LOG_I, LOG_W, LOG_E are available. + * + * + * Fine gain control of logging + * ========================================== + * + * Each component get's its own logging file. + * e.g. nxLog_SSS.h for SSS Layer, nxLog_UseCase.h for use cases. + * SSS Layer and UseCase layer's source files include these individual files + * and with that they can control logging level. + * + * Common `nxLog_Config.h` can control the logging levels, + * or individual source files can control their logging levels. + * + * Easy for the devleoper to add log messages + * ========================================== + * + * Within the source code, only include the file for the given component, e.g. `nxLog_SSS.h`. + * And only call LOG_D, LOG_E, etc. within that file. + * + * + * Easy for the devleoper to add/remove log components + * =========================================================================== + * + * When not required, the files like `nxLog_SSS.h` can be deleted. And when needed + * the script nxLog_Gen.py can be run: + * + * python nxLog_Gen.py + * + * + * Focus on embedded systems + * =========================================================================== + * + * Do not take loging level information at run time, but at compile time. + * This enables to reduce the code size. + * + * + **/ + +#include +#include + +#define NX_LEVEL_DEBUG 4 +#define NX_LEVEL_INFO 3 +#define NX_LEVEL_WARN 2 +#define NX_LEVEL_ERROR 1 + +#define NX_LOG_D +#define NX_LOG_I +#define NX_LOG_W +#define NX_LOG_E + +/* + * Initialised the multithreading locks if running on Native or FreeRtos. + * If running on system where mutex or semaphore is not available, return + * success without doing anything. + */ +uint8_t nLog_Init(); +void nLog_DeInit(); + +void nLog(const char *comp, int level, const char *format, ...); + +void nLog_au8(const char *comp, int level, const char *message, const unsigned char *array, size_t array_len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_App.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_App.h new file mode 100644 index 00000000000..c2ad1f90b5e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_App.h @@ -0,0 +1,183 @@ +/* +* +* Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_APP_H +#define NX_LOG_APP_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'App' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_APP_DEBUG +# define NX_LOG_ENABLE_APP_DEBUG (NX_LOG_ENABLE_DEFAULT_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_APP_INFO +# define NX_LOG_ENABLE_APP_INFO (NX_LOG_ENABLE_APP_DEBUG + NX_LOG_ENABLE_DEFAULT_INFO) +#endif +#ifndef NX_LOG_ENABLE_APP_WARN +# define NX_LOG_ENABLE_APP_WARN (NX_LOG_ENABLE_APP_INFO + NX_LOG_ENABLE_DEFAULT_WARN) +#endif +#ifndef NX_LOG_ENABLE_APP_ERROR +# define NX_LOG_ENABLE_APP_ERROR (NX_LOG_ENABLE_APP_WARN + NX_LOG_ENABLE_DEFAULT_ERROR) +#endif + +/* Enable/Set log levels for 'App' - end */ + +#if NX_LOG_ENABLE_APP_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("App", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("App", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_APP_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("App", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("App", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_APP_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("App", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("App", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_APP_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("App", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("App", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("App", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_APP_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h new file mode 100644 index 00000000000..9e37d5616bb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h @@ -0,0 +1,44 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_DEFAULT_CONFIG_H +#define NX_LOG_DEFAULT_CONFIG_H + +/* See Plug & Trust Middleware Docuemntation --> stack --> Logging + for more information */ + +/* + * - 1 => Enable Debug level logging - for all. + * - 0 => Disable Debug level logging. This has to be + * enabled individually by other logging + * header/source files */ +#define NX_LOG_ENABLE_DEFAULT_DEBUG 0 + +/* Same as NX_LOG_ENABLE_DEFAULT_DEBUG but for Info Level */ +#define NX_LOG_ENABLE_DEFAULT_INFO 1 + +/* Same as NX_LOG_ENABLE_DEFAULT_DEBUG but for Warn Level */ +#define NX_LOG_ENABLE_DEFAULT_WARN 1 + +/* Same as NX_LOG_ENABLE_DEFAULT_DEBUG but for Error Level. + * Ideally, this shoudl alwasy be kept enabled */ +#define NX_LOG_ENABLE_DEFAULT_ERROR 1 + + +/* Release - retail build */ +#ifdef FLOW_SILENT +#undef NX_LOG_ENABLE_DEFAULT_DEBUG +#undef NX_LOG_ENABLE_DEFAULT_INFO +#undef NX_LOG_ENABLE_DEFAULT_WARN +#undef NX_LOG_ENABLE_DEFAULT_ERROR + +#define NX_LOG_ENABLE_DEFAULT_DEBUG 0 +#define NX_LOG_ENABLE_DEFAULT_INFO 0 +#define NX_LOG_ENABLE_DEFAULT_WARN 0 +#define NX_LOG_ENABLE_DEFAULT_ERROR 0 +#endif + +#endif /* NX_LOG_DEFAULT_CONFIG_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_hostLib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_hostLib.h new file mode 100644 index 00000000000..65e68a3b967 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_hostLib.h @@ -0,0 +1,183 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_HOSTLIB_H +#define NX_LOG_HOSTLIB_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'hostLib' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_HOSTLIB_DEBUG +# define NX_LOG_ENABLE_HOSTLIB_DEBUG (NX_LOG_ENABLE_DEFAULT_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_HOSTLIB_INFO +# define NX_LOG_ENABLE_HOSTLIB_INFO (NX_LOG_ENABLE_HOSTLIB_DEBUG + NX_LOG_ENABLE_DEFAULT_INFO) +#endif +#ifndef NX_LOG_ENABLE_HOSTLIB_WARN +# define NX_LOG_ENABLE_HOSTLIB_WARN (NX_LOG_ENABLE_HOSTLIB_INFO + NX_LOG_ENABLE_DEFAULT_WARN) +#endif +#ifndef NX_LOG_ENABLE_HOSTLIB_ERROR +# define NX_LOG_ENABLE_HOSTLIB_ERROR (NX_LOG_ENABLE_HOSTLIB_WARN + NX_LOG_ENABLE_DEFAULT_ERROR) +#endif + +/* Enable/Set log levels for 'hostLib' - end */ + +#if NX_LOG_ENABLE_HOSTLIB_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("hostLib", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("hostLib", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_HOSTLIB_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("hostLib", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("hostLib", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_HOSTLIB_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("hostLib", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("hostLib", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_HOSTLIB_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("hostLib", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("hostLib", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("hostLib", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_HOSTLIB_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_mbedtls.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_mbedtls.h new file mode 100644 index 00000000000..cd866fc9c32 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_mbedtls.h @@ -0,0 +1,183 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_MBEDTLS_H +#define NX_LOG_MBEDTLS_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'mbedtls' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_MBEDTLS_DEBUG +# define NX_LOG_ENABLE_MBEDTLS_DEBUG (NX_LOG_ENABLE_SSS_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_MBEDTLS_INFO +# define NX_LOG_ENABLE_MBEDTLS_INFO (NX_LOG_ENABLE_MBEDTLS_DEBUG + NX_LOG_ENABLE_SSS_INFO) +#endif +#ifndef NX_LOG_ENABLE_MBEDTLS_WARN +# define NX_LOG_ENABLE_MBEDTLS_WARN (NX_LOG_ENABLE_MBEDTLS_INFO + NX_LOG_ENABLE_SSS_WARN) +#endif +#ifndef NX_LOG_ENABLE_MBEDTLS_ERROR +# define NX_LOG_ENABLE_MBEDTLS_ERROR (NX_LOG_ENABLE_MBEDTLS_WARN + NX_LOG_ENABLE_SSS_ERROR) +#endif + +/* Enable/Set log levels for 'mbedtls' - end */ + +#if NX_LOG_ENABLE_MBEDTLS_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("mbedtls", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("mbedtls", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_MBEDTLS_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("mbedtls", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("mbedtls", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_MBEDTLS_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("mbedtls", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("mbedtls", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_MBEDTLS_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("mbedtls", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("mbedtls", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("mbedtls", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_MBEDTLS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_scp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_scp.h new file mode 100644 index 00000000000..c8bc4f2adad --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_scp.h @@ -0,0 +1,183 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_SCP_H +#define NX_LOG_SCP_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'scp' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_SCP_DEBUG +# define NX_LOG_ENABLE_SCP_DEBUG (NX_LOG_ENABLE_DEFAULT_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_SCP_INFO +# define NX_LOG_ENABLE_SCP_INFO (NX_LOG_ENABLE_SCP_DEBUG + NX_LOG_ENABLE_DEFAULT_INFO) +#endif +#ifndef NX_LOG_ENABLE_SCP_WARN +# define NX_LOG_ENABLE_SCP_WARN (NX_LOG_ENABLE_SCP_INFO + NX_LOG_ENABLE_DEFAULT_WARN) +#endif +#ifndef NX_LOG_ENABLE_SCP_ERROR +# define NX_LOG_ENABLE_SCP_ERROR (NX_LOG_ENABLE_SCP_WARN + NX_LOG_ENABLE_DEFAULT_ERROR) +#endif + +/* Enable/Set log levels for 'scp' - end */ + +#if NX_LOG_ENABLE_SCP_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("scp", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("scp", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SCP_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("scp", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("scp", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SCP_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("scp", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("scp", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SCP_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("scp", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("scp", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("scp", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_SCP_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_smCom.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_smCom.h new file mode 100644 index 00000000000..7d42451a1c9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_smCom.h @@ -0,0 +1,183 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_SMCOM_H +#define NX_LOG_SMCOM_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'smCom' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_SMCOM_DEBUG +# define NX_LOG_ENABLE_SMCOM_DEBUG (NX_LOG_ENABLE_DEFAULT_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_SMCOM_INFO +# define NX_LOG_ENABLE_SMCOM_INFO (NX_LOG_ENABLE_SMCOM_DEBUG + NX_LOG_ENABLE_DEFAULT_INFO) +#endif +#ifndef NX_LOG_ENABLE_SMCOM_WARN +# define NX_LOG_ENABLE_SMCOM_WARN (NX_LOG_ENABLE_SMCOM_INFO + NX_LOG_ENABLE_DEFAULT_WARN) +#endif +#ifndef NX_LOG_ENABLE_SMCOM_ERROR +# define NX_LOG_ENABLE_SMCOM_ERROR (NX_LOG_ENABLE_SMCOM_WARN + NX_LOG_ENABLE_DEFAULT_ERROR) +#endif + +/* Enable/Set log levels for 'smCom' - end */ + +#if NX_LOG_ENABLE_SMCOM_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("smCom", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("smCom", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SMCOM_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("smCom", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("smCom", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SMCOM_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("smCom", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("smCom", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SMCOM_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("smCom", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("smCom", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("smCom", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_SMCOM_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_sss.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_sss.h new file mode 100644 index 00000000000..fb61c1fdc43 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_sss.h @@ -0,0 +1,183 @@ +/* + * + * Copyright 2018 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NX_LOG_SSS_H +#define NX_LOG_SSS_H + +#include + +/* ############################################################ */ +/* ## AUTO Generated ########################################## */ +/* ############################################################ */ + +/* Default configuration file */ +#include + +/* clang-format off */ + +/* Check if we are double defining these macros */ +#if defined(LOG_D) || defined(LOG_I) || defined(LOG_W) || defined(LOG_E) +/* This should not happen. The only reason this could happn is double inclusion of different log files. */ +# error "LOG_ macro already defined" +#endif /* LOG_E */ + +/* Enable/Set log levels for 'sss' - start */ +/* If source file, or nxLog_Config.h has not set it, set these defines + * + * Do not #undef these values, rather set to 0/1. This way we can + * jump to definition and avoid plain-old-text-search to jump to + * undef. */ + +#ifndef NX_LOG_ENABLE_SSS_DEBUG +# define NX_LOG_ENABLE_SSS_DEBUG (NX_LOG_ENABLE_DEFAULT_DEBUG) +#endif +#ifndef NX_LOG_ENABLE_SSS_INFO +# define NX_LOG_ENABLE_SSS_INFO (NX_LOG_ENABLE_SSS_DEBUG + NX_LOG_ENABLE_DEFAULT_INFO) +#endif +#ifndef NX_LOG_ENABLE_SSS_WARN +# define NX_LOG_ENABLE_SSS_WARN (NX_LOG_ENABLE_SSS_INFO + NX_LOG_ENABLE_DEFAULT_WARN) +#endif +#ifndef NX_LOG_ENABLE_SSS_ERROR +# define NX_LOG_ENABLE_SSS_ERROR (NX_LOG_ENABLE_SSS_WARN + NX_LOG_ENABLE_DEFAULT_ERROR) +#endif + +/* Enable/Set log levels for 'sss' - end */ + +#if NX_LOG_ENABLE_SSS_DEBUG +# define LOG_DEBUG_ENABLED 1 +# define LOG_D(format, ...) \ + nLog("sss", NX_LEVEL_DEBUG, format, ##__VA_ARGS__) +# define LOG_X8_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X16_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_X32_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_D(VALUE) \ + nLog("sss", NX_LEVEL_DEBUG, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_D(ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_DEBUG, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_DEBUG, MESSAGE, ARRAY, LEN) +#else +# define LOG_DEBUG_ENABLED 0 +# define LOG_D(...) +# define LOG_X8_D(VALUE) +# define LOG_U8_D(VALUE) +# define LOG_X16_D(VALUE) +# define LOG_U16_D(VALUE) +# define LOG_X32_D(VALUE) +# define LOG_U32_D(VALUE) +# define LOG_AU8_D(ARRAY, LEN) +# define LOG_MAU8_D(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SSS_INFO +# define LOG_INFO_ENABLED 1 +# define LOG_I(format, ...) \ + nLog("sss", NX_LEVEL_INFO, format, ##__VA_ARGS__) +# define LOG_X8_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X16_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_X32_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_I(VALUE) \ + nLog("sss", NX_LEVEL_INFO, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_I(ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_INFO, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_INFO, MESSAGE, ARRAY, LEN) +#else +# define LOG_INFO_ENABLED 0 +# define LOG_I(...) +# define LOG_X8_I(VALUE) +# define LOG_U8_I(VALUE) +# define LOG_X16_I(VALUE) +# define LOG_U16_I(VALUE) +# define LOG_X32_I(VALUE) +# define LOG_U32_I(VALUE) +# define LOG_AU8_I(ARRAY, LEN) +# define LOG_MAU8_I(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SSS_WARN +# define LOG_WARN_ENABLED 1 +# define LOG_W(format, ...) \ + nLog("sss", NX_LEVEL_WARN, format, ##__VA_ARGS__) +# define LOG_X8_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X16_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_X32_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_W(VALUE) \ + nLog("sss", NX_LEVEL_WARN, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_W(ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_WARN, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_WARN, MESSAGE, ARRAY, LEN) +#else +# define LOG_WARN_ENABLED 0 +# define LOG_W(...) +# define LOG_X8_W(VALUE) +# define LOG_U8_W(VALUE) +# define LOG_X16_W(VALUE) +# define LOG_U16_W(VALUE) +# define LOG_X32_W(VALUE) +# define LOG_U32_W(VALUE) +# define LOG_AU8_W(ARRAY, LEN) +# define LOG_MAU8_W(MESSAGE, ARRAY, LEN) +#endif + +#if NX_LOG_ENABLE_SSS_ERROR +# define LOG_ERROR_ENABLED 1 +# define LOG_E(format, ...) \ + nLog("sss", NX_LEVEL_ERROR, format, ##__VA_ARGS__) +# define LOG_X8_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=0x%02X",#VALUE, VALUE) +# define LOG_U8_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X16_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=0x%04X",#VALUE, VALUE) +# define LOG_U16_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_X32_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=0x%08X",#VALUE, VALUE) +# define LOG_U32_E(VALUE) \ + nLog("sss", NX_LEVEL_ERROR, "%s=%u",#VALUE, VALUE) +# define LOG_AU8_E(ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_ERROR, #ARRAY, ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY,LEN) \ + nLog_au8("sss", NX_LEVEL_ERROR, MESSAGE, ARRAY, LEN) +#else +# define LOG_ERROR_ENABLED 0 +# define LOG_E(...) +# define LOG_X8_E(VALUE) +# define LOG_U8_E(VALUE) +# define LOG_X16_E(VALUE) +# define LOG_U16_E(VALUE) +# define LOG_X32_E(VALUE) +# define LOG_U32_E(VALUE) +# define LOG_AU8_E(ARRAY, LEN) +# define LOG_MAU8_E(MESSAGE, ARRAY, LEN) +#endif + +/* clang-format on */ + +#endif /* NX_LOG_SSS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c new file mode 100644 index 00000000000..771fbd67058 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c @@ -0,0 +1,429 @@ +/* +* +* Copyright 2018,2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#if defined(FLOW_VERBOSE) +#define NX_LOG_ENABLE_SCP_DEBUG 1 +#endif + +#include +#include +#include "smCom.h" +#include +#include "nxScp03_Apis.h" +#include "nxEnsure.h" +#include "se05x_const.h" + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#if defined(SE05X_MAX_BUF_SIZE_CMD) && (SE05X_MAX_BUF_SIZE_CMD != 1024) +# error "Expect hard coded for SE05X_MAX_BUF_SIZE_CMD = 1024" +#endif +#define NX_SCP03_MAX_BUFFER_SIZE 0x400 /* 0x400 = 1024 */ +#else +#if defined(SE05X_MAX_BUF_SIZE_CMD) && (SE05X_MAX_BUF_SIZE_CMD != 892) +# error "Expect hard coded for SE05X_MAX_BUF_SIZE_CMD = 892" +#endif +#define NX_SCP03_MAX_BUFFER_SIZE 0x380 /* 0x380 = 896 */ +#endif +/* ************************************************************************** */ +/* Functions : Private function declaration */ +/* ************************************************************************** */ +/** +* To Apply Encryption on Plain Data +*/ + +static void nxSCP03_PadCommandAPDU(uint8_t *cmdBuf, size_t *pCmdBufLen); +/** +* To Maintain chaining of Sent commands +*/ +static sss_status_t nxSCP03_Calculate_CommandICV(NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pIcv); + + +/** +* To Maintain chaining of Receive commands +*/ +static sss_status_t nxpSCP03_Get_ResponseICV(NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pIcv, bool hasCmd); +/** +* To check plain data +*/ +static uint16_t nxpSCP03_RestoreSw_RAPDU( + uint8_t *rspBuf, size_t *pRspBufLen, uint8_t *plaintextResponse, size_t plaintextRespLen, uint8_t *sw); + +/** +* Decrement counter block for ICV calculation +*/ +static void nxpSCP03_Dec_CommandCounter(uint8_t *pCtrblock); + +sss_status_t nxSCP03_Encrypt_CommandAPDU(NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *cmdBuf, size_t *pCmdBufLen) +{ + sss_status_t sss_status = kStatus_SSS_Fail; + size_t dataLen = 0; + + ENSURE_OR_GO_CLEANUP(pCmdBufLen != NULL); + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input:cmdBuf", cmdBuf, *pCmdBufLen); + + if (*pCmdBufLen != 0) { + sss_symmetric_t symm; + uint8_t iv[16] = {0}; + uint8_t *pIv = (uint8_t *)iv; + uint8_t apduPayloadToEncrypt[NX_SCP03_MAX_BUFFER_SIZE] = {0}; + + /* Prior to encrypting the data, the data shall be padded as defined in section 4.1.4. + This padding becomes part of the data field.*/ + nxSCP03_PadCommandAPDU(cmdBuf, pCmdBufLen); + sss_status = nxSCP03_Calculate_CommandICV(pdySCP03SessCtx, pIv); + ENSURE_OR_GO_CLEANUP(sss_status == kStatus_SSS_Success); + memcpy(apduPayloadToEncrypt, cmdBuf, *pCmdBufLen); + + sss_status = sss_host_symmetric_context_init(&symm, + pdySCP03SessCtx->Enc.keyStore->session, + &pdySCP03SessCtx->Enc, + kAlgorithm_SSS_AES_CBC, + kMode_SSS_Encrypt); + ENSURE_OR_GO_CLEANUP(sss_status == kStatus_SSS_Success); + dataLen = *pCmdBufLen; + LOG_D("Encrypt CommandAPDU"); + sss_status = sss_host_cipher_one_go(&symm, pIv, SCP_KEY_SIZE, apduPayloadToEncrypt, cmdBuf, dataLen); + ENSURE_OR_GO_CLEANUP(sss_status == kStatus_SSS_Success); + LOG_AU8_D(cmdBuf, dataLen); + LOG_MAU8_D("Output: EncryptedcmdBuf", cmdBuf, dataLen); + sss_host_symmetric_context_free(&symm); + } + else { + /* Nothing to encrypt */ + sss_status = kStatus_SSS_Success; + } + + +cleanup: + return sss_status; +} + +uint16_t nxpSCP03_Decrypt_ResponseAPDU( + NXSCP03_DynCtx_t *pdySCP03SessCtx, size_t cmdBufLen, uint8_t *rspBuf, size_t *pRspBufLen, uint8_t hasle) +{ + sss_status_t sss_status = kStatus_SSS_Fail; + uint16_t status = SCP_FAIL; + sss_algorithm_t algorithm = kAlgorithm_SSS_CMAC_AES; + sss_mode_t mode = kMode_SSS_Mac; + sss_mac_t macCtx; + uint8_t sw[SCP_GP_SW_LEN]; + uint8_t respMac[SCP_CMAC_SIZE] = {0}; + size_t signatureLen = sizeof(respMac); + size_t compareoffset = 0; + size_t macSize = SCP_CMAC_SIZE; + uint8_t iv[SCP_IV_SIZE]; + uint8_t *pIv = (uint8_t *)iv; + uint8_t response[NX_SCP03_MAX_BUFFER_SIZE]; + uint8_t plaintextResponse[NX_SCP03_MAX_BUFFER_SIZE]; + sss_algorithm_t algorithm_aes = kAlgorithm_SSS_AES_CBC; + sss_mode_t mode_aes = kMode_SSS_Decrypt; + sss_symmetric_t symm; + size_t actualRespLen = 0; + + ENSURE_OR_GO_EXIT(pRspBufLen != NULL); + ENSURE_OR_GO_EXIT(pdySCP03SessCtx != NULL); + ENSURE_OR_GO_EXIT(rspBuf != NULL); + + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input:rspBuf", rspBuf, *pRspBufLen); + + + if (*pRspBufLen >= (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN)) { + memcpy(sw, &(rspBuf[*pRspBufLen - SCP_GP_SW_LEN]), SCP_GP_SW_LEN); + + sss_status = sss_host_mac_context_init( + &macCtx, pdySCP03SessCtx->Rmac.keyStore->session, &pdySCP03SessCtx->Rmac, algorithm, mode); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_init(&macCtx); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_update(&macCtx, pdySCP03SessCtx->MCV, macSize); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_update(&macCtx, rspBuf, *pRspBufLen - SCP_COMMAND_MAC_SIZE - SCP_GP_SW_LEN); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_update(&macCtx, sw, SCP_GP_SW_LEN); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_finish(&macCtx, respMac, &signatureLen); + + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + LOG_MAU8_D(" Calculated RMAC :", respMac, signatureLen); + sss_host_mac_context_free(&macCtx); + LOG_D("Verify MAC"); + // Do a comparison of the received and the calculated mac + compareoffset = *pRspBufLen - SCP_COMMAND_MAC_SIZE - SCP_GP_SW_LEN; + if (memcmp(respMac, &rspBuf[compareoffset], SCP_COMMAND_MAC_SIZE) != 0) { + LOG_E(" RESPONSE MAC DID NOT VERIFY %04X", status); + return status; + } + } + + LOG_D("RMAC verified successfully...Decrypt Response Data"); + // Decrypt Response Data Field in case Reponse Mac verified OK + if (*pRspBufLen > (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN)) { + // There is data payload in response + size_t dataLen = 0; + memcpy(response, rspBuf, (*pRspBufLen) - (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN)); + //LOG_MAU8_D(" EncResponse", response, (*pRspBufLen) - 10); + + memcpy(sw, &(rspBuf[*pRspBufLen - SCP_GP_SW_LEN]), SCP_GP_SW_LEN); + LOG_MAU8_D("Status Word: ", sw, 2); + + // Calculate ICV to decrypt the response + sss_status = nxpSCP03_Get_ResponseICV(pdySCP03SessCtx, pIv, cmdBufLen == 0 ? FALSE : TRUE); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_symmetric_context_init( + &symm, pdySCP03SessCtx->Enc.keyStore->session, &pdySCP03SessCtx->Enc, algorithm_aes, mode_aes); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + dataLen = (*pRspBufLen) - (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN); + LOG_D("Decrypt the response"); + // Decrypt the response + sss_status = sss_host_cipher_one_go(&symm, pIv, SCP_KEY_SIZE, response, plaintextResponse, dataLen); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + LOG_MAU8_D("PlainText", plaintextResponse, (*pRspBufLen) - (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN)); + sss_host_symmetric_context_free(&symm); + actualRespLen = (*pRspBufLen) - (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN); + /*Remove the padding from the plaintextResponse*/ + sss_status = kStatus_SSS_Fail; + status = nxpSCP03_RestoreSw_RAPDU(rspBuf, pRspBufLen, plaintextResponse, actualRespLen, sw); + if (status == SCP_OK) { + sss_status = kStatus_SSS_Success; + } + } + else if ((*pRspBufLen) == (SCP_COMMAND_MAC_SIZE + SCP_GP_SW_LEN)) { + // There's no data payload in response + memcpy(rspBuf, sw, SCP_GP_SW_LEN); + *pRspBufLen = SCP_GP_SW_LEN; + sss_status = kStatus_SSS_Success; + } + + if (sss_status == kStatus_SSS_Success) { + status = SCP_OK; + } + + if (((pdySCP03SessCtx->authType == kSSS_AuthType_AESKey) || (pdySCP03SessCtx->authType == kSSS_AuthType_ECKey)) || + ((pdySCP03SessCtx->authType == kSSS_AuthType_SCP03) && cmdBufLen > 0)) { + status = SCP_OK; + nxpSCP03_Inc_CommandCounter(pdySCP03SessCtx); + } + +exit: + return status; +} + +static uint16_t nxpSCP03_RestoreSw_RAPDU( + uint8_t *rspBuf, size_t *pRspBufLen, uint8_t *plaintextResponse, size_t plaintextRespLen, uint8_t *sw) +{ + uint16_t status = SCP_DECODE_FAIL; + size_t i; + int removePaddingOk = 0; + + i = plaintextRespLen; + + ENSURE_OR_GO_EXIT(pRspBufLen != NULL); + ENSURE_OR_GO_EXIT(plaintextResponse != NULL); + ENSURE_OR_GO_EXIT(rspBuf != NULL); + ENSURE_OR_GO_EXIT(sw != NULL); + + LOG_D("FN: %s", __FUNCTION__); + + while ((i > 1) && (i > (plaintextRespLen - SCP_KEY_SIZE))) { + if (plaintextResponse[i - 1] == 0x00) { + i--; + } + else if (plaintextResponse[i - 1] == SCP_DATA_PAD_BYTE) { + // We have found padding delimitor + memcpy(&plaintextResponse[i - 1], sw, SCP_GP_SW_LEN); + memcpy(rspBuf, plaintextResponse, i + 1); + *pRspBufLen = (i + 1); + removePaddingOk = 1; + LOG_MAU8_D("PlainText+SW", rspBuf, *pRspBufLen); + break; + } + else { + // We've found a non-padding character while removing padding + // Most likely the cipher text was not properly decoded. + LOG_E("RAPDU Decoding failed No Padding found %04X", status); + break; + } + } + + if (removePaddingOk == 0) { + return status; + } + status = SCP_OK; +exit: + return status; +} + +static sss_status_t nxpSCP03_Get_ResponseICV(NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pIcv, bool hasCmd) +{ + uint8_t ivZero[SCP_IV_SIZE] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + sss_status_t status = kStatus_SSS_Fail; + sss_symmetric_t symm; + size_t dataLen = 0; + uint8_t paddedCounterBlock[SCP_IV_SIZE] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + ENSURE_OR_GO_EXIT(pdySCP03SessCtx != NULL); + LOG_D("FN: %s", __FUNCTION__); + + memcpy(paddedCounterBlock, pdySCP03SessCtx->cCounter, SCP_KEY_SIZE); + if ((pdySCP03SessCtx->authType == kSSS_AuthType_SCP03) && (!hasCmd)) { + nxpSCP03_Dec_CommandCounter(paddedCounterBlock); + } + paddedCounterBlock[0] = SCP_DATA_PAD_BYTE; // MSB padded with 0x80 Section 6.2.7 of SCP03 spec + + LOG_MAU8_D(" Input:Data", paddedCounterBlock, SCP_KEY_SIZE); + + status = sss_host_symmetric_context_init(&symm, + pdySCP03SessCtx->Enc.keyStore->session, + &pdySCP03SessCtx->Enc, + kAlgorithm_SSS_AES_CBC, + kMode_SSS_Encrypt); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + dataLen = SCP_KEY_SIZE; + status = sss_host_cipher_one_go(&symm, ivZero, SCP_KEY_SIZE, paddedCounterBlock, pIcv, dataLen); + sss_host_symmetric_context_free(&symm); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D(" Output:RespICV", pIcv, dataLen); +exit: + return status; +} + +void nxpSCP03_Inc_CommandCounter(NXSCP03_DynCtx_t *pdySCP03SessCtx) +{ + int i = 15; + ENSURE_OR_GO_EXIT(pdySCP03SessCtx != NULL); + while (i > 0) { + if (pdySCP03SessCtx->cCounter[i] < 255) { + pdySCP03SessCtx->cCounter[i] += 1; + break; + } + else { + pdySCP03SessCtx->cCounter[i] = 0; + i--; + } + } + + LOG_MAU8_D("Inc_CommandCounter value ", pdySCP03SessCtx->cCounter, SCP_KEY_SIZE); +exit: + return; +} + +static void nxpSCP03_Dec_CommandCounter(uint8_t *pCtrblock) +{ + int i = 15; + ENSURE_OR_GO_EXIT(pCtrblock != NULL); + while (i > 0) { + if (pCtrblock[i] == 0) { + pCtrblock[i] = 0xFF; + i--; + } + else { + pCtrblock[i]--; + break; + } + } +exit: + return; +} + +sss_status_t nxpSCP03_CalculateMac_CommandAPDU( + NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pCmdBuf, size_t cmdBufLen, uint8_t *mac, size_t *macLen) +{ + sss_status_t sss_status = kStatus_SSS_Fail; + sss_mac_t macCtx; + sss_algorithm_t algorithm = kAlgorithm_SSS_CMAC_AES; + sss_mode_t mode = kMode_SSS_Mac; + + ENSURE_OR_GO_EXIT(pdySCP03SessCtx != NULL); + ENSURE_OR_GO_EXIT(mac != NULL); + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D("Input: cmdBuf", pCmdBuf, cmdBufLen); + + sss_status = + sss_host_mac_context_init(&macCtx, pdySCP03SessCtx->Mac.keyStore->session, &pdySCP03SessCtx->Mac, algorithm, mode); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_init(&macCtx); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_update(&macCtx, pdySCP03SessCtx->MCV, SCP_KEY_SIZE); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_update(&macCtx, pCmdBuf, cmdBufLen); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + + sss_status = sss_host_mac_finish(&macCtx, mac, macLen); + ENSURE_OR_GO_EXIT(sss_status == kStatus_SSS_Success); + LOG_MAU8_D("Output: mac", mac, SCP_COMMAND_MAC_SIZE); + sss_host_mac_context_free(&macCtx); + // Store updated mcv! + memcpy(pdySCP03SessCtx->MCV, mac, SCP_MCV_LEN); + +exit: + return sss_status; +} + +static sss_status_t nxSCP03_Calculate_CommandICV(NXSCP03_DynCtx_t *pdySCP03SessCtx, uint8_t *pIcv) +{ + uint8_t ivZero[SCP_KEY_SIZE] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + sss_status_t status = kStatus_SSS_Fail; + sss_symmetric_t symm; + size_t dataLen = 0; + + ENSURE_OR_GO_EXIT(pdySCP03SessCtx != NULL); + LOG_D("FN: %s", __FUNCTION__); + + + status = sss_host_symmetric_context_init(&symm, + pdySCP03SessCtx->Enc.keyStore->session, + &pdySCP03SessCtx->Enc, + kAlgorithm_SSS_AES_CBC, + kMode_SSS_Encrypt); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + dataLen = SCP_KEY_SIZE; + status = sss_host_cipher_one_go(&symm, ivZero, SCP_KEY_SIZE, pdySCP03SessCtx->cCounter, pIcv, dataLen); + sss_host_symmetric_context_free(&symm); + LOG_MAU8_D(" Output:", pIcv, SCP_COMMAND_MAC_SIZE); +exit: + return status; +} + +static void nxSCP03_PadCommandAPDU(uint8_t *cmdBuf, size_t *pCmdBufLen) +{ + uint16_t zeroBytesToPad = 0; + + ENSURE_OR_GO_EXIT(pCmdBufLen != NULL); + ENSURE_OR_GO_EXIT(cmdBuf != NULL); + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D("Input: cmdBuf", cmdBuf, *pCmdBufLen); + // pad the payload and adjust the length of the APDU + cmdBuf[(*pCmdBufLen)] = SCP_DATA_PAD_BYTE; + *pCmdBufLen += 1; + zeroBytesToPad = (SCP_KEY_SIZE - ((*pCmdBufLen) % SCP_KEY_SIZE)) % SCP_KEY_SIZE; + + while (zeroBytesToPad > 0) { + cmdBuf[(*pCmdBufLen)] = 0x00; + *pCmdBufLen += 1; + zeroBytesToPad--; + } + LOG_MAU8_D("Ouput: cmdBuf", cmdBuf, *pCmdBufLen); + +exit: + return; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h new file mode 100644 index 00000000000..b14761df9ab --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h @@ -0,0 +1,421 @@ +/* + * Copyright 2010-2014,2018-2019 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * ESE Status Values - Function Return Codes + */ + +#ifndef PHESESTATUS_H +#define PHESESTATUS_H + +#include "phEseTypes.h" + +/* Internally required by PHESESTVAL. */ +#define PHESESTSHL8 (8U) +/* Required by PHESESTVAL. */ +#define PHESESTBLOWER ((ESESTATUS)(0x00FFU)) + +/* + * ESE Status Composition Macro + * + * This is the macro which must be used to compose status values. + * + * phEseCompID Component ID, as defined in phEseCompId.h . + * phEseStatus Status values, as defined in phEseStatus.h . + * + * The macro is not required for the ESESTATUS_SUCCESS value. + * This is the only return value to be used directly. + * For all other values it shall be used in assignment and conditional statements, e.g.: + * ESESTATUS status = PHESESTVAL(phEseCompID, phEseStatus); ... + * if (status == PHESESTVAL(phEseCompID, phEseStatus)) ... + */ +#define PHESESTVAL(phEseCompID, phEseStatus) \ + ( ((phEseStatus) == (ESESTATUS_SUCCESS)) ? (ESESTATUS_SUCCESS) : \ + ( (((ESESTATUS)(phEseStatus)) & (PHESESTBLOWER)) | \ + (((uint16_t)(phEseCompID)) << (PHESESTSHL8)) ) ) + +/* + * PHESESTATUS + * Get grp_retval from Status Code + */ +#define PHESESTATUS(phEseStatus) ((phEseStatus) & 0x00FFU) +#define PHESECID(phEseStatus) (((phEseStatus) & 0xFF00U)>>8) + +/* + * Status Codes + * + * Generic Status codes for the ESE components. Combined with the Component ID + * they build the value (status) returned by each function. + * Example: + * grp_comp_id "Component ID" - e.g. 0x10, plus + * status code as listed in this file - e.g. 0x03 + * result in a status value of 0x0003. + */ + +/* + * The function indicates successful completion + */ +#define ESESTATUS_SUCCESS (0x0000) + +/* + * The function indicates successful completion + */ +#define ESESTATUS_OK (ESESTATUS_SUCCESS) + +/* + * At least one parameter could not be properly interpreted + */ +#define ESESTATUS_INVALID_PARAMETER (0x0001) + +/* + * Invalid buffer provided by application + * */ +#define ESESTATUS_INVALID_BUFFER (0x0002) + +/* + * The buffer provided by the caller is too small + */ +#define ESESTATUS_BUFFER_TOO_SMALL (0x0003) + +/* + * Invalid class byte provided by application + * */ +#define ESESTATUS_INVALID_CLA (0x0004) + +/* + * Invalid command pdu type provided by application + * */ +#define ESESTATUS_INVALID_CPDU_TYPE (0x0005) + +/* + * Invalid command LE type provided by application + * */ +#define ESESTATUS_INVALID_LE_TYPE (0x0007) + +/* + * Device specifier/handle value is invalid for the operation + */ +#define ESESTATUS_INVALID_DEVICE (0x0006) + +/* + * The function executed successfully but could have returned + * more information than space provided by the caller + */ +#define ESESTATUS_MORE_FRAME (0x0008) + +/* + * No response from the remote device received: Time-out + */ +#define ESESTATUS_LAST_FRAME (0x0009) + +/* + * CRC Error during data transaction with the device + */ +#define ESESTATUS_CRC_ERROR (0x000A) + +/* + * SOF Error during data transaction with the device + */ +#define ESESTATUS_SOF_ERROR (0x000B) + +/* + * Not enough resources Memory, Timer etc(e.g. allocation failed.) + */ +#define ESESTATUS_INSUFFICIENT_RESOURCES (0x000C) + +/* + * A non-blocking function returns this immediately to indicate + * that an internal operation is in progress + */ +#define ESESTATUS_PENDING (0x000D) + +/* + * A board communication error occurred + * (e.g. Configuration went wrong) + */ +#define ESESTATUS_BOARD_COMMUNICATION_ERROR (0x000F) + +/* + * Invalid State of the particular state machine + */ +#define ESESTATUS_INVALID_STATE (0x0011) + + +/* + * This Layer is Not initialized, hence initialization required. + */ +#define ESESTATUS_NOT_INITIALISED (0x0031) + + +/* + * The Layer is already initialized, hence initialization repeated. + */ +#define ESESTATUS_ALREADY_INITIALISED (0x0032) + + +/* + * Feature not supported + */ +#define ESESTATUS_FEATURE_NOT_SUPPORTED (0x0033) + +/* + * Parity Error + */ +#define ESESTATUS_PARITY_ERROR (0x0034) + + +/* The Registration command has failed because the user wants to register on + * an element for which he is already registered + */ +#define ESESTATUS_ALREADY_REGISTERED (0x0035) + +/* Chained frame is being sent */ +#define ESESTATUS_CHAINED_FRAME (0x0036) + +/* + * Single frame is sent + */ +#define ESESTATUS_SINGLE_FRAME (0x0037) + +/* + * A DESELECT event has occurred + */ +#define ESESTATUS_DESELECTED (0x0038) + +/* + * A RELEASE event has occurred + */ +#define ESESTATUS_RELEASED (0x0039) + +/* + * The operation is currently not possible or not allowed + */ +#define ESESTATUS_NOT_ALLOWED (0x003A) + +/* + * Other indicaated error sent by JCOP. + */ +#define ESESTATUS_OTHER_ERROR (0x003C) +/* + * The system is busy with the firmware download operation. + */ +#define ESESTATUS_DWNLD_BUSY (0x006E) + +/* + * The system is busy with the previous operation. + */ +#define ESESTATUS_BUSY (0x006F) + + +/* NDEF Mapping error codes */ + +/* The remote device (type) is not valid for this request. */ +#define ESESTATUS_INVALID_REMOTE_DEVICE (0x001D) + +/* Read operation failed */ +#define ESESTATUS_READ_FAILED (0x0014) + +/* + * Write operation failed + */ +#define ESESTATUS_WRITE_FAILED (0x0015) + + +/* Non Ndef Compliant */ +#define ESESTATUS_NO_NDEF_SUPPORT (0x0016) + +/* resend the frame with seq_counter 0*/ +#define ESESTATUS_RESET_SEQ_COUNTER_FRAME_RESEND (0x001A) + +/* Incorrect number of bytes received from the card*/ +#define ESESTATUS_INVALID_RECEIVE_LENGTH (0x001B) + +/* The data format/composition is not understood/correct. */ +#define ESESTATUS_INVALID_FORMAT (0x001C) + + +/* There is not sufficient storage available. */ +#define ESESTATUS_INSUFFICIENT_STORAGE (0x001F) + +/* The last command would be re-sent */ +#define ESESTATUS_FRAME_RESEND (0x0023) + +/* The write timeout error */ +#define ESESTATUS_WRITE_TIMEOUT (0x0024) + +/* + * Response Time out for the control message(ESEC not responded) + */ +#define ESESTATUS_RESPONSE_TIMEOUT (0x0025) + +/* + * Resend the last R Frame + */ +#define ESESTATUS_FRAME_RESEND_R_FRAME (0x0026) + +/* + * Send next chained frame + */ +#define ESESTATUS_SEND_NEXT_FRAME (0x0027) + +/* + * Protocol revovery started + */ +#define ESESTATUS_REVOCERY_STARTED (0x0028) + +/* + * Single Target Detected + */ +#define ESESTATUS_SEND_R_FRAME (0x0029) + +/* + * Resend the RNAK + */ + +#define ESESTATUS_FRAME_RESEND_RNAK (0x0030) + +/* + * Resend the last R Frame + */ +#define ESESTATUS_FRAME_SEND_R_FRAME (0x003B) + +/* + * Unknown error Status Codes + */ +#define ESESTATUS_UNKNOWN_ERROR (0x00FE) + +/* + * Status code for failure + */ +#define ESESTATUS_FAILED (0x00FF) + +/* + * The function/command has been aborted + */ +#define ESESTATUS_CMD_ABORTED (0x0002) + +/* + * No target found after poll + */ +#define ESESTATUS_NO_TARGET_FOUND (0x000A) + +/* Attempt to disconnect a not connected remote device. */ +#define ESESTATUS_NO_DEVICE_CONNECTED (0x000B) + + +/* requesting a resynchronization */ +#define ESESTATUS_RESYNCH_REQ (0x000E) + +/* + * acknowledging resynchronization + */ +#define ESESTATUS_RESYNCH_RES (0x0010) + +/* + * S-block offering a maximum size of the information field + */ +#define ESESTATUS_IFS_REQ (0x001E) + +/* S-block offering a maximum size of the information field */ +#define ESESTATUS_IFS_RES (0x0017) + +/* S-block requesting a chain abortion */ +#define ESESTATUS_ABORT_REQ (0x00F0) + + +/*S-block acknowledging the chain abortion*/ +#define ESESTATUS_ABORT_RES (0x00F2) + + +/* S-block requesting a waiting time extension*/ +#define ESESTATUS_WTX_REQ (0x00F5) + +/* S-block acknowledging the waiting time extension */ +#define ESESTATUS_WTX_RES (0x00F6) + +/* S-block interface reset request */ +#define ESESTATUS_RESET_REQ (0x00F7) + +/* S-block interface reset response */ +#define ESESTATUS_RESET_RES (0x00F8) + +/* S-block requesting a end of apdu transfer*/ +#define ESESTATUS_END_APDU_REQ (0x00F9) + +/* S-block acknowledging end of apdu transfer*/ +#define ESESTATUS_END_APDU_RES (0x00FA) + +/* + * Shutdown in progress, cannot handle the request at this time. + */ +#define ESESTATUS_SHUTDOWN (0x0091) + +/* + * Target is no more in RF field + */ +#define ESESTATUS_TARGET_LOST (0x0092) + +/* + * Request is rejected + */ +#define ESESTATUS_REJECTED (0x0093) + +/* + * Target is not connected + */ +#define ESESTATUS_TARGET_NOT_CONNECTED (0x0094) + +/* + * Invalid handle for the operation + */ +#define ESESTATUS_INVALID_HANDLE (0x0095) + +/* + * Process aborted + */ +#define ESESTATUS_ABORTED (0x0096) + +/* + * Requested command is not supported + */ +#define ESESTATUS_COMMAND_NOT_SUPPORTED (0x0097) + +/* + * Tag is not NDEF compilant + */ +#define ESESTATUS_NON_NDEF_COMPLIANT (0x0098) + +/* + * Not enough memory available to complete the requested operation + */ +#define ESESTATUS_NOT_ENOUGH_MEMORY (0x001F) + +/* + * Indicates incoming connection + */ +#define ESESTATUS_INCOMING_CONNECTION (0x0045) + +/* + * Indicates Connection was successful + */ +#define ESESTATUS_CONNECTION_SUCCESS (0x0046) + +/* + * Indicates Connection failed + */ +#define ESESTATUS_CONNECTION_FAILED (0x0047) + +#endif /* PHESESTATUS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h new file mode 100644 index 00000000000..6a511644b53 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h @@ -0,0 +1,31 @@ +/* + * Copyright 2010-2014,2018-2019 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PHESETYPES_H +#define PHESETYPES_H +#include +#include +#include +#include + +typedef uint8_t utf8_t; /* UTF8 Character String */ +typedef uint8_t bool_t; /* boolean data type */ +typedef uint16_t ESESTATUS; /* Return values */ +#define STATIC static + +#define UNUSED(X) (void)X; + +#endif /* PHESETYPES_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c new file mode 100644 index 00000000000..4ee1665c42b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c @@ -0,0 +1,202 @@ +/* + * Copyright 2010-2014,2018-2020 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * DAL i2c port implementation for linux + * + * Project: Trusted ESE Linux + * + */ +#include +#include +#include +#include +#include +#include "i2c_a7.h" + +#ifdef FLOW_VERBOSE +#define NX_LOG_ENABLE_SMCOM_DEBUG 1 +#endif + +#include "nxLog_smCom.h" +#include "sm_timer.h" + +#include "se05x_apis.h" +#if defined(Android) || defined(LINUX) +#include +#include +#include +#include +#endif + +#include + +#define MAX_RETRY_CNT 10 + +/******************************************************************************* +** +** Function phPalEse_i2c_close +** +** Description Closes PN547 device +** +** param[in] pDevHandle - device handle +** +** Returns None +** +*******************************************************************************/ +void phPalEse_i2c_close(void *pDevHandle) +{ +#ifdef Android + if (NULL != pDevHandle) { + close((intptr_t)pDevHandle); + } +#endif + axI2CTerm(pDevHandle, 0); + pDevHandle = NULL; + + return; +} + +/******************************************************************************* +** +** Function phPalEse_i2c_open_and_configure +** +** Description Open and configure pn547 device +** +** param[in] pConfig - hardware information +** +** Returns ESE status: +** ESESTATUS_SUCCESS - open_and_configure operation success +** ESESTATUS_INVALID_DEVICE - device open operation failure +** +*******************************************************************************/ +ESESTATUS phPalEse_i2c_open_and_configure(pphPalEse_Config_t pConfig) +{ + void *conn_ctx = NULL; + int retryCnt = 0; + int i2c_ret = 0; + + LOG_D("%s Opening port", __FUNCTION__); + /* open port */ + /*Disable as interface reset happens on every session open*/ + //se05x_ic_reset(); +retry: + i2c_ret = axI2CInit(&conn_ctx, (const char *)pConfig->pDevName); + if (i2c_ret != I2C_OK) { + LOG_E("%s Failed retry ", __FUNCTION__); + if (i2c_ret == I2C_BUSY) { + retryCnt++; + LOG_E("Retry open eSE driver, retry cnt : %d ", retryCnt); + if (retryCnt < MAX_RETRY_CNT) { + sm_sleep(ESE_POLL_DELAY_MS); + goto retry; + } + } + LOG_E("I2C init Failed: retval %x ", i2c_ret); + pConfig->pDevHandle = NULL; + return ESESTATUS_INVALID_DEVICE; + } + LOG_D("I2C driver Initialized :: fd = [%d] ", i2c_ret); + pConfig->pDevHandle = conn_ctx; + return ESESTATUS_SUCCESS; +} + +/******************************************************************************* +** +** Function phPalEse_i2c_read +** +** Description Reads requested number of bytes from pn547 device into given buffer +** +** param[in] pDevHandle - valid device handle +** param[in] pBuffer - buffer for read data +** param[in] nNbBytesToRead - number of bytes requested to be read +** +** Returns numRead - number of successfully read bytes +** -1 - read operation failure +** +*******************************************************************************/ +int phPalEse_i2c_read(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToRead) +{ + int ret = -1, retryCount = 0; + ; + int numRead = 0; + LOG_D("%s Read Requested %d bytes ", __FUNCTION__, nNbBytesToRead); + //sm_sleep(ESE_POLL_DELAY_MS); + while (numRead != nNbBytesToRead) { + ret = axI2CRead(pDevHandle, I2C_BUS_0, SMCOM_I2C_ADDRESS, pBuffer, nNbBytesToRead); + if (ret != I2C_OK) { + LOG_D("_i2c_read() error : %d ", ret); + if ((ret == I2C_NACK_ON_ADDRESS) && (retryCount < MAX_RETRY_COUNT)) { + retryCount++; + /* 1ms delay to give ESE polling delay */ + /*i2c driver back off delay is providing 1ms wait time so ignoring waiting time at this level*/ + //sm_sleep(ESE_POLL_DELAY_MS); + LOG_D("_i2c_read() failed. Going to retry, counter:%d !", retryCount); + continue; + } + return -1; + } + else { + numRead = nNbBytesToRead; + break; + } + } + return numRead; +} + +/******************************************************************************* +** +** Function phPalEse_i2c_write +** +** Description Writes requested number of bytes from given buffer into pn547 device +** +** param[in] pDevHandle - valid device handle +** param[in] pBuffer - buffer for read data +** param[in] nNbBytesToWrite - number of bytes requested to be written +** +** Returns numWrote - number of successfully written bytes +** -1 - write operation failure +** +*******************************************************************************/ +int phPalEse_i2c_write(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToWrite) +{ + int ret = I2C_OK, retryCount = 0; + int numWrote = 0; + pBuffer[0] = 0x5A; //Recovery if stack forgot to add NAD byte. + do { + /* 1ms delay to give ESE polling delay */ + sm_sleep(ESE_POLL_DELAY_MS); + ret = axI2CWrite(pDevHandle, I2C_BUS_0, SMCOM_I2C_ADDRESS, pBuffer, nNbBytesToWrite); + if (ret != I2C_OK) { + LOG_D("_i2c_write() error : %d ", ret); + if ((ret == I2C_NACK_ON_ADDRESS) && (retryCount < MAX_RETRY_COUNT)) { + retryCount++; + /* 1ms delay to give ESE polling delay */ + /*i2c driver back off delay is providing 1ms wait time so ignoring waiting time at this level*/ + //sm_sleep(ESE_POLL_DELAY_MS); + LOG_D("_i2c_write() failed. Going to retry, counter:%d !", retryCount); + continue; + } + return -1; + } + else { + numWrote = nNbBytesToWrite; + //sm_sleep(ESE_POLL_DELAY_MS); + break; + } + } while (ret != I2C_OK); + return numWrote; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h new file mode 100644 index 00000000000..8b44bc7d69a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h @@ -0,0 +1,110 @@ +/* + * Copyright 2010-2014,2018-2020 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /** + * \addtogroup eSe_PAL_I2C + * \brief PAL I2C port implementation for linux + * @{ */ +#ifndef _PHNXPESE_PAL_I2C_H +#define _PHNXPESE_PAL_I2C_H + +/* Basic type definitions */ +#include + + +/*! + * \brief ESE Poll timeout (min 1 miliseconds) + */ +#define ESE_POLL_DELAY_MS (1) +/*! + * \brief ESE Poll timeout. + * As Max WTX timeout is 1sec, select ESE_NAD_POLLING_MAX count in such a way that WTX request frm SE is not skiped + * select target value is 2 sec. + * + * Note: Here ESE_NAD_POLLING_MAX is depend on platform, If i2c driver does not have backoff delay implemented, + * then set ESE_NAD_POLLING_MAX value to >=300 + * + */ +#if AX_EMBEDDED //back off delay is implemented for AX_EMBEDDED devices + /*TODO:semslite need more than 20 polling count right now max is set to 60 as 46 was the max sof counter observed + SIMW-2927*/ +#if defined(LPC_55x) + #define ESE_NAD_POLLING_MAX (2*250) + #else + #define ESE_NAD_POLLING_MAX (2*30) +#endif +#else + #define ESE_NAD_POLLING_MAX (2*250) +#endif +/*! + * \brief Max retry count for Write + */ +#define MAX_RETRY_COUNT 3 + +/*! + * \brief ESE wakeup delay in case of write error retry + */ +#define WAKE_UP_DELAY_MS 5 //5 ms +/*! + * \brief ESE wakeup delay in case of write error retry + */ +#define NAD_POLLING_SCALER 1 +/*! + * \brief ESE wakeup delay in case of write error retry + */ +#define CHAINED_PKT_SCALER 1 +/*! + * \brief This function is used to set slave address of ESE + * + */ +// #define I2C_MASTER_SLAVE_ADDR_7BIT (0x90U >> 1) //slve bit address is 20U but driver do right shift so set to 40U +#define SMCOM_I2C_ADDRESS (0x90) + +/*! + * \ingroup eSe_PAL_I2C + * + * \brief PAL Configuration exposed to upper layer. + */ +typedef struct phPalEse_Config +{ + int8_t *pDevName; + /*!< Port name connected to ESE + * + * Platform specific canonical device name to which ESE is connected. + * + * e.g. On Linux based systems this would be /dev/p73 + */ + + int8_t DeviceAddress; + /*!< I2C Address of SE connected + */ + + uint32_t dwBaudRate; + /*!< Communication speed between DH and ESE + * + * This is the baudrate of the bus for communication between DH and ESE + */ + + void *pDevHandle; + /*!< Device handle output */ +} phPalEse_Config_t,*pphPalEse_Config_t; /* pointer to phPalEse_Config_t */ + +void phPalEse_i2c_close(void *pDevHandle); +ESESTATUS phPalEse_i2c_open_and_configure(pphPalEse_Config_t pConfig); +int phPalEse_i2c_read(void *pDevHandle, uint8_t * pBuffer, int nNbBytesToRead); +int phPalEse_i2c_write(void *pDevHandle,uint8_t * pBuffer, int nNbBytesToWrite); +/** @} */ +#endif /* _PHNXPESE_PAL_I2C_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c new file mode 100644 index 00000000000..b6d167c71a1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c @@ -0,0 +1,1697 @@ +/* + * Copyright 2012-2014,2018-2020 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include "sm_types.h" +#include "sm_timer.h" + +#ifdef FLOW_VERBOSE +#define NX_LOG_ENABLE_SMCOM_DEBUG 1 +#endif + +#include "nxLog_smCom.h" +#include "nxEnsure.h" + +/** + * \addtogroup ISO7816-3_protocol_lib + * + * @{ */ + +phNxpEseProto7816_t phNxpEseProto7816_3_Var; + +/****************************************************************************** +\section Introduction Introduction + + * This module provide the 7816-3 protocol level implementation for ESE + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SendRawFrame(void* conn_ctx, uint32_t data_len, uint8_t *p_data); +static bool_t phNxpEseProto7816_GetRawFrame(void* conn_ctx, uint32_t *data_len, uint8_t **pp_data); +static uint16_t phNxpEseProto7816_ComputeCRC(unsigned char *p_buff, uint32_t offset, + uint32_t length); +static bool_t phNxpEseProto7816_CheckCRC(uint32_t data_len, uint8_t *p_data); +static bool_t phNxpEseProto7816_SendSFrame(void* conn_ctx, sFrameInfo_t sFrameData); +static bool_t phNxpEseProto7816_SendIframe(void* conn_ctx, iFrameInfo_t iFrameData); +static bool_t phNxpEseProto7816_sendRframe(void* conn_ctx, rFrameTypes_t rFrameType); +static bool_t phNxpEseProto7816_SetFirstIframeContxt(void); +static bool_t phNxpEseProto7816_SetNextIframeContxt(void); +static bool_t phNxpEseProro7816_SaveRxframeData(uint8_t *p_data, uint32_t data_len); +static bool_t phNxpEseProto7816_ResetRecovery(void); +static bool_t phNxpEseProto7816_RecoverySteps(void); +static bool_t phNxpEseProto7816_DecodeFrame(uint8_t *p_data, uint32_t data_len); +static bool_t phNxpEseProto7816_ProcessResponse(void* conn_ctx); +static bool_t TransceiveProcess(void* conn_ctx); +static bool_t phNxpEseProto7816_RSync(void* conn_ctx); + +/****************************************************************************** + * Function phNxpEseProto7816_SendRawFrame + * + * Description This internal function is called send the data to ESE + * + * param[in] uint32_t: number of bytes to be written + * param[in] uint8_t : data buffer + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SendRawFrame(void* conn_ctx, uint32_t data_len, uint8_t *p_data) +{ + ESESTATUS status = ESESTATUS_FAILED; + status = phNxpEse_WriteFrame(conn_ctx, data_len, p_data); + if (ESESTATUS_SUCCESS != status) + { + LOG_E("%s Error phNxpEse_WriteFrame ", __FUNCTION__); + } + + return (status == ESESTATUS_SUCCESS)?TRUE : FALSE; +} + +/****************************************************************************** + * Function phNxpEseProto7816_GetRawFrame + * + * Description This internal function is called read the data from the ESE + * + * param[out] uint32_t: number of bytes read + * param[out] uint8_t : Read data from ESE + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_GetRawFrame(void* conn_ctx, uint32_t *data_len, uint8_t **pp_data) +{ + bool_t bStatus = FALSE; + ESESTATUS status = ESESTATUS_FAILED; + + status = phNxpEse_read(conn_ctx, data_len, pp_data); + if (ESESTATUS_SUCCESS != status) + { + LOG_E("%s phNxpEse_read failed , status : 0x%x ", __FUNCTION__, status); + } + else + { + bStatus = TRUE; + } + return bStatus; +} + +/****************************************************************************** + * Function phNxpEseProto7816_ComputeCRC + * + * Description This internal function is called compute the CRC + * + * param[in] unsigned char: data buffer + * param[in] uint32_t : offset from which CRC to be calculated + * param[in] uint32_t : total length of frame + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static uint16_t phNxpEseProto7816_ComputeCRC(unsigned char *p_buff, uint32_t offset, + uint32_t length) +{ + uint16_t CAL_CRC = 0xFFFF, CRC = 0x0000; + uint32_t i = 0; + + ENSURE_OR_GO_EXIT(p_buff != NULL); + for (i = offset; i < length; i++) + { + CAL_CRC ^= p_buff[i]; + for (int bit = 8; bit > 0; --bit) + { + if ((CAL_CRC & 0x0001) == 0x0001) + { + CAL_CRC = (unsigned short)((CAL_CRC >> 1) ^ 0x8408); + } + else + { + CAL_CRC >>= 1; + } + } + + } + CAL_CRC ^=0xFFFF; +#if defined(T1oI2C_UM11225) + CRC = ((CAL_CRC & 0xFF) << 8) | ((CAL_CRC >> 8) & 0xFF); +#elif defined(T1oI2C_GP1_0) + CRC = CAL_CRC; +#endif +exit: + return (uint16_t) CRC; +} + +/****************************************************************************** + * Function phNxpEseProto7816_CheckCRC + * + * Description This internal function is called compute and compare the + * received CRC of the received data + * + * param[in] uint32_t : frame length + * param[in] uint8_t: data buffer + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_CheckCRC(uint32_t data_len, uint8_t *p_data) +{ + bool_t status = FALSE; + uint16_t calc_crc = 0; + uint16_t recv_crc = 0; + + ENSURE_OR_GO_EXIT(p_data != NULL); + status = TRUE; + + recv_crc = p_data[data_len - 2] <<8 | p_data[data_len - 1] ; //combine 2 byte CRC + + /* calculate the CRC after excluding Recieved CRC */ + /* CRC calculation includes NAD byte, so offset is set to 0 */ + calc_crc = phNxpEseProto7816_ComputeCRC(p_data, 0, (data_len -2)); + LOG_D("Received CRC:0x%x Calculated CRC:0x%x ", recv_crc, calc_crc); + if (recv_crc != calc_crc) + { + status = FALSE; + LOG_E("%s CRC failed ", __FUNCTION__); + } +exit: + return status; +} + +/****************************************************************************** + * Function getMaxSupportedSendIFrameSize + * + * Description This internal function is called to get the max supported + * I-frame size + * + * param[in] void + * + * Returns IFSC_SIZE_SEND + * + ******************************************************************************/ +uint8_t getMaxSupportedSendIFrameSize(void) +{ + return IFSC_SIZE_SEND ; +} + +/****************************************************************************** + * Function phNxpEseProto7816_SendSFrame + * + * Description This internal function is called to send S-frame with all + * updated 7816-3 headers + * + * param[in] sFrameInfo_t: Info about S frame + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SendSFrame(void* conn_ctx, sFrameInfo_t sFrameData) +{ + bool_t status = ESESTATUS_FAILED; + uint32_t frame_len = 0; + uint8_t p_framebuff[7] = {0}; + uint8_t pcb_byte = 0; + sFrameInfo_t sframeData = sFrameData; + uint16_t calc_crc=0; + /* This update is helpful in-case a R-NACK is transmitted from the MW */ + phNxpEseProto7816_3_Var.lastSentNonErrorframeType = SFRAME; + switch(sframeData.sFrameType) + { + case RESYNCH_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; +#if defined(T1oI2C_GP1_0) + /* T =1 GP block format LEN field is of 2 byte*/ + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0; +#endif + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_RESYNCH; + break; +#if defined(T1oI2C_UM11225) + case INTF_RESET_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_RESET; + break; + case PROP_END_APDU_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_END_OF_APDU; + break; + case ATR_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_GET_ATR; + break; +#endif + case WTX_RSP: + frame_len = (PH_PROTO_7816_HEADER_LEN + 1 + PH_PROTO_7816_CRC_LEN); +#if defined(T1oI2C_UM11225) + /* T =1 UM11225 SE050 block format LEN field is of 2 byte*/ + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0x01; +#elif defined(T1oI2C_GP1_0) + /* T =1 GP block format LEN field is of 2 byte*/ + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0x00; + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0x01; +#endif + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x01; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_RSP; + pcb_byte |= PH_PROTO_7816_S_WTX; + break; +#if defined(T1oI2C_UM11225) + case CHIP_RESET_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_CHIP_RST; + break; +#endif +#if defined(T1oI2C_GP1_0) + case SWR_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_SWR; + break; + case RELEASE_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_RELEASE; + break; + case CIP_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_GET_CIP; + break; + case COLD_RESET_REQ: + frame_len = (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] = 0; + p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET] = 0x00; + + pcb_byte |= PH_PROTO_7816_S_BLOCK_REQ; /* PCB */ + pcb_byte |= PH_PROTO_7816_S_COLD_RST; + break; +#endif + default: + LOG_E(" %s :Invalid S-block",__FUNCTION__); + return status; + } + + /* frame the packet */ + p_framebuff[PH_PROPTO_7816_NAD_OFFSET] = 0x5A; /* NAD Byte */ + p_framebuff[PH_PROPTO_7816_PCB_OFFSET] = pcb_byte; /* PCB */ + + calc_crc = phNxpEseProto7816_ComputeCRC(p_framebuff, 0,(frame_len - 2)); + p_framebuff[frame_len - 2] = (calc_crc >> 8) & 0xFF; + p_framebuff[frame_len - 1] = calc_crc & 0xFF; + LOG_D("S-Frame PCB: %x ", p_framebuff[PH_PROPTO_7816_PCB_OFFSET]); + status = phNxpEseProto7816_SendRawFrame(conn_ctx, frame_len, p_framebuff); + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_sendRframe + * + * Description This internal function is called to send R-frame with all + * updated 7816-3 headers + * + * param[in] sFrameInfo_t: Info about R frame + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_sendRframe(void* conn_ctx, rFrameTypes_t rFrameType) +{ + bool_t status = FALSE; +#if defined(T1oI2C_UM11225) + uint8_t recv_ack[5]= {0x5A,0x80,0x00,0x00,0x00}; +#elif defined(T1oI2C_GP1_0) + uint8_t recv_ack[6]= {0x5A,0x80,0x00,0x00,0x00,0x00}; +#endif + uint16_t calc_crc=0; + iFrameInfo_t *pRx_lastRcvdIframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdIframeInfo; + rFrameInfo_t *pNextTx_RframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.RframeInfo; + if(RNACK == rFrameType) /* R-NACK */ + { + switch(pNextTx_RframeInfo->errCode) + { + case PARITY_ERROR: + recv_ack[PH_PROPTO_7816_PCB_OFFSET] |= (0x01 & 0xFF); + break; + + case OTHER_ERROR: + recv_ack[PH_PROPTO_7816_PCB_OFFSET] |= (0x02 & 0xFF); + break; + + case SOF_MISSED_ERROR: + case UNDEFINED_ERROR: + recv_ack[PH_PROPTO_7816_PCB_OFFSET] |= (0x03 & 0xFF); + break; + + default: + break; + } + } + else /* R-ACK*/ + { + /* This update is helpful in-case a R-NACK is transmitted from the MW */ + phNxpEseProto7816_3_Var.lastSentNonErrorframeType = RFRAME; + } + + recv_ack[PH_PROPTO_7816_PCB_OFFSET] |= ((pRx_lastRcvdIframeInfo->seqNo ^ 1) << 4); + LOG_D("%s recv_ack[PH_PROPTO_7816_PCB_OFFSET]:0x%x ", __FUNCTION__, recv_ack[PH_PROPTO_7816_PCB_OFFSET]); + calc_crc = phNxpEseProto7816_ComputeCRC(recv_ack, 0x00, (sizeof(recv_ack) -2)); + + recv_ack[(sizeof(recv_ack) -2)] = (calc_crc >> 8) & 0xFF; + recv_ack[(sizeof(recv_ack) -1)] = calc_crc &0xFF ; + status = phNxpEseProto7816_SendRawFrame(conn_ctx, sizeof(recv_ack), recv_ack); + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_SendIframe + * + * Description This internal function is called to send I-frame with all + * updated 7816-3 headers + * + * param[in] sFrameInfo_t: Info about I frame + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SendIframe(void* conn_ctx, iFrameInfo_t iFrameData) +{ + bool_t status = FALSE; + uint32_t frame_len = 0; + uint8_t p_framebuff[MAX_DATA_LEN]; + uint8_t pcb_byte = 0; + uint16_t calc_crc = 0; + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + + if (0 == iFrameData.sendDataLen) + { + LOG_E("%s Line: [%d] I frame Len is 0, INVALID ",__FUNCTION__,__LINE__); + return FALSE; + } + /* This update is helpful in-case a R-NACK is transmitted from the MW */ + phNxpEseProto7816_3_Var.lastSentNonErrorframeType = IFRAME; + frame_len = (iFrameData.sendDataLen+ PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN); + + /* frame the packet */ + p_framebuff[PH_PROPTO_7816_NAD_OFFSET] = SEND_PACKET_SOF; /* NAD Byte */ + + if (iFrameData.isChained) + { + /* make B6 (M) bit high */ + pcb_byte |= PH_PROTO_7816_CHAINING; + } + + /* Update the send seq no */ + pcb_byte |= (pNextTx_IframeInfo->seqNo << 6); + + /* store the pcb byte */ + p_framebuff[PH_PROPTO_7816_PCB_OFFSET] = pcb_byte; +#if defined(T1oI2C_UM11225) + /* store I frame length */ + /* for T1oI2C_UM11225 LEN field is of 1 byte*/ + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] =iFrameData.sendDataLen; +#elif defined(T1oI2C_GP1_0) + /* store I frame length */ + /* for T1oI2C_GP1_0 LEN field is of 2 byte*/ + p_framebuff[PH_PROPTO_7816_LEN_UPPER_OFFSET] =(((uint16_t)iFrameData.sendDataLen) >> 8 & 0xff); + p_framebuff[PH_PROPTO_7816_LEN_LOWER_OFFSET] =(((uint16_t)iFrameData.sendDataLen) & 0xff); +#endif + /* store I frame */ + phNxpEse_memcpy(&(p_framebuff[PH_PROPTO_7816_INF_BYTE_OFFSET]), iFrameData.p_data + iFrameData.dataOffset, iFrameData.sendDataLen); + calc_crc = phNxpEseProto7816_ComputeCRC(p_framebuff, 0, (frame_len - 2)); + + p_framebuff[frame_len - 2] = (calc_crc >> 8) & 0xff; + p_framebuff[frame_len - 1] = calc_crc & 0xff; + status = phNxpEseProto7816_SendRawFrame(conn_ctx, frame_len, p_framebuff); + + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_SetFirstIframeContxt + * + * Description This internal function is called to set the context for next I-frame. + * Not applicable for the first I-frame of the transceive + * + * param[in] void + * + * Returns Always return TRUE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SetFirstIframeContxt(void) +{ + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + iFrameInfo_t *pLastTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.IframeInfo; + + pNextTx_IframeInfo->dataOffset = 0; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = IFRAME; + pNextTx_IframeInfo->seqNo = pLastTx_IframeInfo->seqNo ^ 1; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_IFRAME; + pRx_EseCntx->pRsp->len = 0; + if (pNextTx_IframeInfo->totalDataLen > pNextTx_IframeInfo->maxDataLen) { + pNextTx_IframeInfo->isChained = TRUE; + pNextTx_IframeInfo->sendDataLen = pNextTx_IframeInfo->maxDataLen; + pNextTx_IframeInfo->totalDataLen = pNextTx_IframeInfo->totalDataLen - pNextTx_IframeInfo->maxDataLen; + } + else + { + pNextTx_IframeInfo->sendDataLen = pNextTx_IframeInfo->totalDataLen; + pNextTx_IframeInfo->isChained = FALSE; + } + LOG_D("I-Frame Data Len: %ld Seq. no:%d ", pNextTx_IframeInfo->sendDataLen, pNextTx_IframeInfo->seqNo); + return TRUE; +} + +/****************************************************************************** + * Function phNxpEseProto7816_SetNextIframeContxt + * + * Description This internal function is called to set the context for next I-frame. + * Not applicable for the first I-frame of the transceive + * + * param[in] void + * + * Returns Always return TRUE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_SetNextIframeContxt(void) +{ + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + iFrameInfo_t *pLastTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.IframeInfo; + + /* Expecting to reach here only after first of chained I-frame is sent and before the last chained is sent */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = IFRAME; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_IFRAME; + + pNextTx_IframeInfo->seqNo = pLastTx_IframeInfo->seqNo ^ 1; + pNextTx_IframeInfo->dataOffset = pLastTx_IframeInfo->dataOffset + pLastTx_IframeInfo->maxDataLen; + pNextTx_IframeInfo->p_data = pLastTx_IframeInfo->p_data; + pNextTx_IframeInfo->maxDataLen = pLastTx_IframeInfo->maxDataLen; + + //if chained + if (pLastTx_IframeInfo->totalDataLen > pLastTx_IframeInfo->maxDataLen) { + LOG_D("%s Process Chained Frame ",__FUNCTION__); + pNextTx_IframeInfo->isChained = TRUE; + pNextTx_IframeInfo->sendDataLen = pLastTx_IframeInfo->maxDataLen; + pNextTx_IframeInfo->totalDataLen = pLastTx_IframeInfo->totalDataLen - pLastTx_IframeInfo->maxDataLen; + } + else + { + pNextTx_IframeInfo->isChained = FALSE; + pNextTx_IframeInfo->sendDataLen = pLastTx_IframeInfo->totalDataLen; + } + LOG_D("I-Frame Data Len: %ld ", pNextTx_IframeInfo->sendDataLen); + return TRUE; +} + +/****************************************************************************** + * Function phNxpEseProro7816_SaveRxframeData + * + * Description This internal function is called to save recv frame data + * + * param[in] uint8_t: data buffer + * param[in] uint32_t: buffer length + * + * Returns Always return TRUE. + * + ******************************************************************************/ +static bool_t phNxpEseProro7816_SaveRxframeData(uint8_t *p_data, uint32_t data_len) +{ + uint32_t offset = 0; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + LOG_D("Data[0]=0x%x len=%ld Data[%ld]=0x%x Data[%ld]=0x%x ", p_data[0], data_len,data_len-1, p_data[data_len-2],p_data[data_len-1]); + if (pRx_EseCntx->pRsp != NULL) { + offset = pRx_EseCntx->pRsp->len; + phNxpEse_memcpy((pRx_EseCntx->pRsp->p_data + offset), p_data, data_len); + pRx_EseCntx->pRsp->len += data_len; + return TRUE; + } + else { + LOG_E("Unsolicited response"); + return FALSE; + } +} + +/****************************************************************************** + * Function phNxpEseProto7816_ResetRecovery + * + * Description This internal function is called to do reset the recovery pareameters + * + * param[in] void + * + * Returns Always return TRUE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_ResetRecovery(void) +{ + phNxpEseProto7816_3_Var.recoveryCounter = 0; + return TRUE; +} + +/****************************************************************************** + * Function phNxpEseProto7816_RecoverySteps + * + * Description This internal function is called when 7816-3 stack failed to recover + * after PH_PROTO_7816_FRAME_RETRY_COUNT, and the interface has to be + * recovered + * + * param[in] void + * + * Returns Always return TRUE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_RecoverySteps(void) +{ + sFrameInfo_t *pRx_lastRcvdSframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdSframeInfo; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + if(phNxpEseProto7816_3_Var.recoveryCounter <= PH_PROTO_7816_FRAME_RETRY_COUNT) + { +#if defined(T1oI2C_UM11225) + pRx_lastRcvdSframeInfo->sFrameType = INTF_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = INTF_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_INTF_RST; +#elif defined(T1oI2C_GP1_0) + pRx_lastRcvdSframeInfo->sFrameType = SWR_REQ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = SWR_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_SWR; +#endif + } + else + { /* If recovery fails */ + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + } + return TRUE; +} + +/****************************************************************************** + * Function phNxpEseProto7816_DecodeSFrameData + * + * Description This internal function is to decode S-frame payload. + * + * param[in] uint8_t; data buffer + * + * Returns void + * + ******************************************************************************/ +static void phNxpEseProto7816_DecodeSFrameData(uint8_t *p_data) +{ + uint8_t maxSframeLen = 0, frameOffset = 0; + + ENSURE_OR_GO_EXIT(p_data != NULL); +#if defined(T1oI2C_UM11225) + frameOffset = PH_PROPTO_7816_LEN_UPPER_OFFSET; +#elif defined(T1oI2C_GP1_0) + /* current GP implementation support max payload of 0x00FE, so considering lower offset */ + frameOffset = PH_PROPTO_7816_LEN_LOWER_OFFSET; +#endif + maxSframeLen = p_data[frameOffset] + frameOffset; /* to be in sync with offset which starts from index 0 */ + while(maxSframeLen > frameOffset) + { + frameOffset += 1; /* To get the Type (TLV) */ + LOG_D("%s frameoffset=%d value=0x%x ", __FUNCTION__, frameOffset, p_data[frameOffset]); + frameOffset += p_data[frameOffset + 1]; /* Goto the end of current marker */ + + } +exit: + return; +} + +/****************************************************************************** + * Function phNxpEseProto7816_DecodeFrame + * + * Description This internal function is used to + * 1. Identify the received frame + * 2. If the received frame is I-frame with expected sequence number, store it or else send R-NACK + 3. If the received frame is R-frame, + 3.1 R-ACK with expected seq. number: Send the next chained I-frame + 3.2 R-ACK with different sequence number: Sebd the R-Nack + 3.3 R-NACK: Re-send the last frame + 4. If the received frame is S-frame, send back the correct S-frame response. + * + * param[in] uint8_t : data buffer + * param[in] uint32_t : buffer length + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_DecodeFrame(uint8_t *p_data, uint32_t data_len) +{ + bool_t status = TRUE; + uint8_t pcb; + phNxpEseProto7816_PCB_bits_t pcb_bits; + iFrameInfo_t *pRx_lastRcvdIframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdIframeInfo; + rFrameInfo_t *pNextTx_RframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.RframeInfo; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + iFrameInfo_t *pLastTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.IframeInfo; + sFrameInfo_t *pLastTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.SframeInfo; + rFrameInfo_t *pRx_lastRcvdRframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdRframeInfo; + sFrameInfo_t *pRx_lastRcvdSframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdSframeInfo; + + LOG_D("Retry Counter = %d ", phNxpEseProto7816_3_Var.recoveryCounter); + + ENSURE_OR_GO_EXIT(p_data != NULL); + + pcb = p_data[PH_PROPTO_7816_PCB_OFFSET]; + phNxpEse_memset(&pcb_bits, 0x00, sizeof(phNxpEseProto7816_PCB_bits_t)); + phNxpEse_memcpy(&pcb_bits, &pcb, sizeof(uint8_t)); + + if (0x00 == pcb_bits.msb) /* I-FRAME decoded should come here */ + { + LOG_D("%s I-Frame Received ", __FUNCTION__); + phNxpEseProto7816_3_Var.wtx_counter = 0; + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = IFRAME ; + if (pRx_lastRcvdIframeInfo->seqNo != pcb_bits.bit7) // != pcb_bits->bit7) + { + LOG_D("%s I-Frame lastRcvdIframeInfo.seqNo:0x%x ", __FUNCTION__, pcb_bits.bit7); + phNxpEseProto7816_ResetRecovery(); + pRx_lastRcvdIframeInfo->seqNo = 0x00; + pRx_lastRcvdIframeInfo->seqNo |= pcb_bits.bit7; + + if (pcb_bits.bit6) + { + pRx_lastRcvdIframeInfo->isChained = TRUE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = RFRAME; + pNextTx_RframeInfo->errCode = NO_ERROR; + phNxpEseProro7816_SaveRxframeData(&p_data[PH_PROPTO_7816_INF_BYTE_OFFSET], data_len - PH_PROTO_7816_INF_FILED); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_ACK ; + } + else + { + pRx_lastRcvdIframeInfo->isChained = FALSE; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + phNxpEseProro7816_SaveRxframeData(&p_data[PH_PROPTO_7816_INF_BYTE_OFFSET], data_len - PH_PROTO_7816_INF_FILED); + } + } + else + { + sm_sleep(DELAY_ERROR_RECOVERY/1000); + if(phNxpEseProto7816_3_Var.recoveryCounter < PH_PROTO_7816_FRAME_RETRY_COUNT) + { + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = RFRAME; + pNextTx_RframeInfo->errCode = OTHER_ERROR; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_NACK ; + phNxpEseProto7816_3_Var.recoveryCounter++; + } + else + { + phNxpEseProto7816_RecoverySteps(); + phNxpEseProto7816_3_Var.recoveryCounter++; + } + } + } + else if ((0x01 == pcb_bits.msb) && (0x00 == pcb_bits.bit7)) /* R-FRAME decoded should come here */ + { + LOG_D("%s R-Frame Received", __FUNCTION__); + phNxpEseProto7816_3_Var.wtx_counter = 0; + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = RFRAME; + pRx_lastRcvdRframeInfo->seqNo = 0; // = 0; + pRx_lastRcvdRframeInfo->seqNo |= pcb_bits.bit5; + + if ((pcb_bits.lsb == 0x00) && (pcb_bits.bit2 == 0x00)) + { + pRx_lastRcvdRframeInfo->errCode = NO_ERROR; + phNxpEseProto7816_ResetRecovery(); + if (pRx_lastRcvdRframeInfo->seqNo != pLastTx_IframeInfo->seqNo) { + phNxpEseProto7816_SetNextIframeContxt(); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_IFRAME; + } + + } /* Error handling 1 : Parity error */ + else if (((pcb_bits.lsb == 0x01) && (pcb_bits.bit2 == 0x00)) || + /* Error handling 2: Other indicated error */ + ((pcb_bits.lsb == 0x00) && (pcb_bits.bit2 == 0x01))) + { + sm_sleep(DELAY_ERROR_RECOVERY/1000); + if((pcb_bits.lsb == 0x00) && (pcb_bits.bit2 == 0x01)) + pRx_lastRcvdRframeInfo->errCode = OTHER_ERROR; + else + pRx_lastRcvdRframeInfo->errCode = PARITY_ERROR; + if(phNxpEseProto7816_3_Var.recoveryCounter < PH_PROTO_7816_FRAME_RETRY_COUNT) + { + if(phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType == IFRAME) + { + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_IFRAME; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = IFRAME; + } + else if(phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType == RFRAME) + { + /* Usecase to reach the below case: + I-frame sent first, followed by R-NACK and we receive a R-NACK with + last sent I-frame sequence number*/ + if ((pRx_lastRcvdRframeInfo->seqNo == pLastTx_IframeInfo->seqNo) && + (phNxpEseProto7816_3_Var.lastSentNonErrorframeType == IFRAME)) { + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_IFRAME; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = IFRAME; + } + /* Usecase to reach the below case: + R-frame sent first, followed by R-NACK and we receive a R-NACK with + next expected I-frame sequence number*/ + else if ((pRx_lastRcvdRframeInfo->seqNo != pLastTx_IframeInfo->seqNo) && + (phNxpEseProto7816_3_Var.lastSentNonErrorframeType == RFRAME)) { + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = RFRAME; + pNextTx_RframeInfo->errCode = NO_ERROR; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_ACK ; + } + /* Usecase to reach the below case: + I-frame sent first, followed by R-NACK and we receive a R-NACK with + next expected I-frame sequence number + all the other unexpected scenarios */ + else + { + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= RFRAME; + pNextTx_RframeInfo->errCode = OTHER_ERROR; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_NACK ; + } + } + else if(phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType == SFRAME) + { + /* Copy the last S frame sent */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx; + } + phNxpEseProto7816_3_Var.recoveryCounter++; + } + else + { + phNxpEseProto7816_RecoverySteps(); + phNxpEseProto7816_3_Var.recoveryCounter++; + } + //resend previously send I frame + } + /* Error handling 3 */ + else if ((pcb_bits.lsb == 0x01) && (pcb_bits.bit2 == 0x01)) + { + sm_sleep(DELAY_ERROR_RECOVERY/1000); + if(phNxpEseProto7816_3_Var.recoveryCounter < PH_PROTO_7816_FRAME_RETRY_COUNT) + { + pRx_lastRcvdRframeInfo->errCode = SOF_MISSED_ERROR; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx; + phNxpEseProto7816_3_Var.recoveryCounter++; + } + else + { + phNxpEseProto7816_RecoverySteps(); + phNxpEseProto7816_3_Var.recoveryCounter++; + } + } + } + else if ((0x01 == pcb_bits.msb) && (0x01 == pcb_bits.bit7)) /* S-FRAME decoded should come here */ + { + LOG_D("%s S-Frame Received ", __FUNCTION__); + int32_t frameType = (int32_t)(pcb & 0x3F); /*discard upper 2 bits */ + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = SFRAME; + if(frameType!=WTX_REQ) + { + phNxpEseProto7816_3_Var.wtx_counter = 0; + } + switch(frameType) + { + case RESYNCH_RSP: + pRx_lastRcvdSframeInfo->sFrameType = RESYNCH_RSP; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + case IFSC_RES: + pRx_lastRcvdSframeInfo->sFrameType = IFSC_RES; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE ; + break; + case ABORT_RES: + pRx_lastRcvdSframeInfo->sFrameType = ABORT_RES; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE ; + break; + case WTX_REQ: + phNxpEseProto7816_3_Var.wtx_counter++; + LOG_D("%s Wtx_counter value - %lu ", __FUNCTION__, phNxpEseProto7816_3_Var.wtx_counter); + LOG_D("%s Wtx_counter wtx_counter_limit - %lu ", __FUNCTION__, phNxpEseProto7816_3_Var.wtx_counter_limit); + /* Previous sent frame is some S-frame but not WTX response S-frame */ + if (pLastTx_SframeInfo->sFrameType != WTX_RSP && + phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType == + SFRAME) { /* Goto recovery if it keep coming here for more than recovery counter max. value */ + if(phNxpEseProto7816_3_Var.recoveryCounter < PH_PROTO_7816_FRAME_RETRY_COUNT) + { /* Re-transmitting the previous sent S-frame */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx; + phNxpEseProto7816_3_Var.recoveryCounter++; + } + else + { + phNxpEseProto7816_RecoverySteps(); + phNxpEseProto7816_3_Var.recoveryCounter++; + } + } + else + { /* Checking for WTX counter with max. allowed WTX count */ + if(phNxpEseProto7816_3_Var.wtx_counter == phNxpEseProto7816_3_Var.wtx_counter_limit) + { +#if defined(T1oI2C_UM11225) + phNxpEseProto7816_3_Var.wtx_counter = 0; + pRx_lastRcvdSframeInfo->sFrameType = INTF_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = INTF_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_INTF_RST; + LOG_E("%s Interface Reset to eSE wtx count reached!!! ", __FUNCTION__); +#elif defined(T1oI2C_GP1_0) + phNxpEseProto7816_3_Var.wtx_counter = 0; + pRx_lastRcvdSframeInfo->sFrameType = SWR_REQ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = SWR_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_SWR; + LOG_E("%s Software Reset to eSE wtx count reached!!! ", __FUNCTION__); +#endif + } + else + { + sm_sleep(DELAY_ERROR_RECOVERY/1000); + pRx_lastRcvdSframeInfo->sFrameType = WTX_REQ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = WTX_RSP; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_WTX_RSP ; + } + } + break; +#if defined(T1oI2C_UM11225) + case INTF_RESET_RSP: + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProro7816_SaveRxframeData(&p_data[PH_PROPTO_7816_INF_BYTE_OFFSET], data_len - PH_PROTO_7816_INF_FILED); + if(phNxpEseProto7816_3_Var.recoveryCounter > PH_PROTO_7816_FRAME_RETRY_COUNT){ + /*Max recovery counter reached, send failure to APDU layer */ + LOG_E("%s Max retry count reached!!! ", __FUNCTION__); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + status = FALSE; + } + else{ + phNxpEseProto7816_ResetProtoParams(); + pRx_lastRcvdSframeInfo->sFrameType = INTF_RESET_RSP; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + } + break; + case PROP_END_APDU_RSP: + pRx_lastRcvdSframeInfo->sFrameType = PROP_END_APDU_RSP; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + case ATR_RES: + pRx_lastRcvdSframeInfo->sFrameType = ATR_RES; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProro7816_SaveRxframeData(&p_data[PH_PROPTO_7816_INF_BYTE_OFFSET], data_len - PH_PROTO_7816_INF_FILED); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + case CHIP_RESET_RES: + pRx_lastRcvdSframeInfo->sFrameType = CHIP_RESET_RES; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; +#endif +#if defined(T1oI2C_GP1_0) + case SWR_RSP: + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + if(phNxpEseProto7816_3_Var.recoveryCounter > PH_PROTO_7816_FRAME_RETRY_COUNT){ + /*Max recovery counter reached, send failure to APDU layer */ + LOG_E("%s Max retry count reached!!! ", __FUNCTION__); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + status = FALSE; + } + else{ + phNxpEseProto7816_ResetProtoParams(); + pRx_lastRcvdSframeInfo->sFrameType = SWR_RSP; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + } + break; + case RELEASE_RES: + pRx_lastRcvdSframeInfo->sFrameType = RELEASE_RES; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + case CIP_RES: + pRx_lastRcvdSframeInfo->sFrameType = CIP_RES; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProro7816_SaveRxframeData(&p_data[PH_PROPTO_7816_INF_BYTE_OFFSET], data_len - PH_PROTO_7816_INF_FILED); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + case COLD_RESET_RES: + pRx_lastRcvdSframeInfo->sFrameType = COLD_RESET_RES; + if(p_data[PH_PROPTO_7816_FRAME_LENGTH_OFFSET] > 0) + phNxpEseProto7816_DecodeSFrameData(p_data); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= UNKNOWN; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; +#endif + default: + LOG_E("%s Wrong S-Frame Received ", __FUNCTION__); + break; + } + } + else + { + LOG_E("%s Wrong-Frame Received ", __FUNCTION__); + } +exit: + return status ; +} + +/****************************************************************************** + * Function phNxpEseProto7816_ProcessResponse + * + * Description This internal function is used to + * 1. Check the CRC + * 2. Initiate decoding of received frame of data. + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_ProcessResponse(void* conn_ctx) +{ + uint32_t data_len = 0; + uint8_t *p_data = NULL; + bool_t status = FALSE; + bool_t checkCrcPass = TRUE; + iFrameInfo_t *pRx_lastRcvdIframeInfo = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdIframeInfo; + rFrameInfo_t *pNextTx_RframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.RframeInfo; + sFrameInfo_t *pLastTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.SframeInfo; + + status = phNxpEseProto7816_GetRawFrame(conn_ctx, &data_len, &p_data); + LOG_D("%s p_data ----> %p len ----> 0x%lx ", __FUNCTION__,p_data, data_len); + if(TRUE == status) + { + /* Resetting the timeout counter */ + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + /* CRC check followed */ + checkCrcPass = phNxpEseProto7816_CheckCRC(data_len, p_data); + if(checkCrcPass == TRUE) + { + /* Resetting the RNACK retry counter */ + phNxpEseProto7816_3_Var.rnack_retry_counter = PH_PROTO_7816_VALUE_ZERO; + status = phNxpEseProto7816_DecodeFrame(p_data, data_len); + } + else + { + LOG_E("%s CRC Check failed ", __FUNCTION__); + if(phNxpEseProto7816_3_Var.rnack_retry_counter < phNxpEseProto7816_3_Var.rnack_retry_limit) + { + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = INVALID ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= RFRAME; + pNextTx_RframeInfo->errCode = PARITY_ERROR; + pNextTx_RframeInfo->seqNo = (!pRx_lastRcvdIframeInfo->seqNo) << 4; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_NACK ; + phNxpEseProto7816_3_Var.rnack_retry_counter++; + } + else + { + phNxpEseProto7816_3_Var.rnack_retry_counter = PH_PROTO_7816_VALUE_ZERO; + /* Re-transmission failed completely, Going to exit */ + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + status = FALSE; + } + } + } + else + { + LOG_E("%s phNxpEseProto7816_GetRawFrame failed starting recovery", __FUNCTION__); + if ((SFRAME == phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType) && + ((WTX_RSP == pLastTx_SframeInfo->sFrameType) || (RESYNCH_RSP == pLastTx_SframeInfo->sFrameType))) { + if(phNxpEseProto7816_3_Var.rnack_retry_counter < phNxpEseProto7816_3_Var.rnack_retry_limit) + { + phNxpEse_clearReadBuffer(conn_ctx); + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = INVALID ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= RFRAME; + pNextTx_RframeInfo->errCode = OTHER_ERROR; + pNextTx_RframeInfo->seqNo = (!pRx_lastRcvdIframeInfo->seqNo) << 4; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_NACK ; + phNxpEseProto7816_3_Var.rnack_retry_counter++; + } + else + { + LOG_E("%s Recovery failed completely, Going to exit ", __FUNCTION__); + phNxpEseProto7816_3_Var.rnack_retry_counter = PH_PROTO_7816_VALUE_ZERO; + /* Recovery failed completely, Going to exit */ + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + } + } + /*ISO7816-3 Rule 7.1 Implementation*/ + else if (IFRAME == phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType) + { + if(phNxpEseProto7816_3_Var.rnack_retry_counter < phNxpEseProto7816_3_Var.rnack_retry_limit) + { + phNxpEse_clearReadBuffer(conn_ctx); + phNxpEseProto7816_3_Var.phNxpEseRx_Cntx.lastRcvdFrameType = INVALID ; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= RFRAME; + pNextTx_RframeInfo->errCode = PARITY_ERROR; + pNextTx_RframeInfo->seqNo = (!pRx_lastRcvdIframeInfo->seqNo) << 4; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_R_NACK ; + phNxpEseProto7816_3_Var.rnack_retry_counter++; + } + else + { + LOG_E("%s Recovery failed completely, Going to exit ", __FUNCTION__); + phNxpEseProto7816_3_Var.rnack_retry_counter = PH_PROTO_7816_VALUE_ZERO; + /* Recovery failed completely, Going to exit */ + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + } + } + else + { + sm_sleep(DELAY_ERROR_RECOVERY/1000); + /* re transmit the frame */ + if(phNxpEseProto7816_3_Var.timeoutCounter < PH_PROTO_7816_TIMEOUT_RETRY_COUNT) + { + phNxpEseProto7816_3_Var.timeoutCounter++; + LOG_E("%s re-transmitting the previous frame ", __FUNCTION__); + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx ; + } + else + { + /* Recovery failed completely, Going to exit */ + LOG_E("%s Recovery failed completely, Going to exit ", __FUNCTION__); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + } + } + } + return status; +} + +/****************************************************************************** + * Function TransceiveProcess + * + * Description This internal function is used to + * 1. Send the raw data received from application after computing CRC + * 2. Receive the the response data from ESE, decode, process and + * store the data. + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t TransceiveProcess(void* conn_ctx) +{ + bool_t status = FALSE; + sFrameInfo_t sFrameInfo; + sFrameInfo.sFrameType = INVALID_REQ_RES; + + sFrameInfo.sFrameType = INVALID_REQ_RES; + + while(phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState != IDLE_STATE) + { + LOG_D("%s nextTransceiveState %x ", __FUNCTION__, phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState); + switch(phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState) + { + case SEND_IFRAME: + status = phNxpEseProto7816_SendIframe(conn_ctx, phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo); + break; + case SEND_R_ACK: + status = phNxpEseProto7816_sendRframe(conn_ctx, RACK); + break; + case SEND_R_NACK: + status = phNxpEseProto7816_sendRframe(conn_ctx, RNACK); + break; + case SEND_S_RSYNC: + sFrameInfo.sFrameType = RESYNCH_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_WTX_RSP: + sFrameInfo.sFrameType = WTX_RSP; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; +#if defined(T1oI2C_UM11225) + case SEND_S_CHIP_RST: + sFrameInfo.sFrameType = CHIP_RESET_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_INTF_RST: + sFrameInfo.sFrameType = INTF_RESET_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_EOS: + sFrameInfo.sFrameType = PROP_END_APDU_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_ATR: + sFrameInfo.sFrameType = ATR_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; +#elif defined(T1oI2C_GP1_0) + case SEND_S_CIP: + sFrameInfo.sFrameType = CIP_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_SWR: + sFrameInfo.sFrameType = SWR_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_RELEASE: + sFrameInfo.sFrameType = RELEASE_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; + case SEND_S_COLD_RST: + sFrameInfo.sFrameType = COLD_RESET_REQ; + status = phNxpEseProto7816_SendSFrame(conn_ctx, sFrameInfo); + break; +#else +#error Either T1oI2C_UM11225 or T1oI2C_GP1_0 must be defined. +#endif + default: + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + break; + } + if(TRUE == status) + { + phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx = phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx; + status = phNxpEseProto7816_ProcessResponse(conn_ctx); + } + else + { + LOG_E("%s Transceive send failed, going to recovery! ", __FUNCTION__); + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + } + }; + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_Transceive + * + * Description This function is used to + * 1. Send the raw data received from application after computing CRC + * 2. Receive the the response data from ESE, decode, process and + * store the data. + * 3. Get the final complete data and sent back to application + * + * param[in] phNxpEse_data: Command to ESE C-APDU + * param[out] phNxpEse_data: Response from ESE R-APDU + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_Transceive(void* conn_ctx, phNxpEse_data *pCmd, phNxpEse_data *pRsp) +{ + bool_t status = FALSE; + uint32_t reqDataLen = 0; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + + LOG_D("Enter %s ", __FUNCTION__); + if((NULL == pCmd) || (NULL == pRsp) || + (phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState != PH_NXP_ESE_PROTO_7816_IDLE)) + return status; + reqDataLen = pRsp->len; + /* Updating the transceive information to the protocol stack */ + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + pNextTx_IframeInfo->p_data = pCmd->p_data; + pNextTx_IframeInfo->totalDataLen = pCmd->len; + pRx_EseCntx->pRsp = pRsp; + LOG_D("Transceive data ptr 0x%p len:%ld ", pCmd->p_data, pCmd->len); + phNxpEseProto7816_SetFirstIframeContxt(); + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* ESE hard reset to be done */ + LOG_E("%s Transceive failed, hard reset to proceed ",__FUNCTION__); + } + else if(pRsp->len > reqDataLen ) + { + LOG_W("Need '%d' bytes. Got '%d' to copy.", pRsp->len, reqDataLen); + pRsp->len = 0; + status = FALSE; + } + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_RSync + * + * Description This function is used to send the RSync command + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +static bool_t phNxpEseProto7816_RSync(void* conn_ctx) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + /* send the end of session s-frame */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = RESYNCH_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_RSYNC; + status = TransceiveProcess(conn_ctx); + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_ResetProtoParams + * + * Description This function is used to reset the 7816 protocol stack instance + * + * param[in] void + * + * Returns Always return TRUE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_ResetProtoParams(void) +{ + unsigned long int tmpWTXCountlimit = PH_PROTO_7816_VALUE_ZERO; + unsigned long int tmpRNACKCountlimit = PH_PROTO_7816_VALUE_ZERO; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + iFrameInfo_t *pLastTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.IframeInfo; + + tmpWTXCountlimit = phNxpEseProto7816_3_Var.wtx_counter_limit; + tmpRNACKCountlimit = phNxpEseProto7816_3_Var.rnack_retry_limit; + phNxpEse_memset(&phNxpEseProto7816_3_Var, PH_PROTO_7816_VALUE_ZERO, sizeof(phNxpEseProto7816_t)); + phNxpEseProto7816_3_Var.wtx_counter_limit = tmpWTXCountlimit; + phNxpEseProto7816_3_Var.rnack_retry_limit = tmpRNACKCountlimit; + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = IDLE_STATE; + pRx_EseCntx->lastRcvdFrameType = INVALID; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType = INVALID; + pNextTx_IframeInfo->maxDataLen = IFSC_SIZE_SEND; + pNextTx_IframeInfo->p_data = NULL; + phNxpEseProto7816_3_Var.phNxpEseLastTx_Cntx.FrameType = INVALID; + pLastTx_IframeInfo->maxDataLen = IFSC_SIZE_SEND; + pLastTx_IframeInfo->p_data = NULL; + /* Initialized with sequence number of the last I-frame sent */ + pNextTx_IframeInfo->seqNo = PH_PROTO_7816_VALUE_ONE; + /* Initialized with sequence number of the last I-frame received */ + pRx_EseCntx->lastRcvdIframeInfo.seqNo = PH_PROTO_7816_VALUE_ONE; + /* Initialized with sequence number of the last I-frame received */ + pLastTx_IframeInfo->seqNo = PH_PROTO_7816_VALUE_ONE; + phNxpEseProto7816_3_Var.recoveryCounter = PH_PROTO_7816_VALUE_ZERO; + phNxpEseProto7816_3_Var.timeoutCounter = PH_PROTO_7816_VALUE_ZERO; + phNxpEseProto7816_3_Var.wtx_counter = PH_PROTO_7816_VALUE_ZERO; + /* This update is helpful in-case a R-NACK is transmitted from the MW */ + phNxpEseProto7816_3_Var.lastSentNonErrorframeType = UNKNOWN; + phNxpEseProto7816_3_Var.rnack_retry_counter = PH_PROTO_7816_VALUE_ZERO; + pRx_EseCntx->pRsp = NULL; + return TRUE; +} + + +/****************************************************************************** + * Function phNxpEseProto7816_Reset + * + * Description This function is used to reset the 7816 protocol stack instance + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_Reset(void) +{ + bool_t status = FALSE; + /* Resetting host protocol instance */ + status = phNxpEseProto7816_ResetProtoParams(); + /* Resynchronising ESE protocol instance */ + //status = phNxpEseProto7816_RSync(); + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_Open + * + * Description This function is used to open the 7816 protocol stack instance + * + * param[in] phNxpEseProto7816InitParam_t: ESE communication mode + * param[out] phNxpEse_data: ATR Response from ESE + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_Open(void* conn_ctx, phNxpEseProto7816InitParam_t initParam, phNxpEse_data *AtrRsp) +{ + bool_t status = FALSE; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + status = phNxpEseProto7816_ResetProtoParams(); + LOG_D("%s: First open completed", __FUNCTION__); + /* Update WTX max. limit */ + phNxpEseProto7816_3_Var.wtx_counter_limit = initParam.wtx_counter_limit; + phNxpEseProto7816_3_Var.rnack_retry_limit = initParam.rnack_retry_limit; + /*Intialise the buffers before hand so that we are able to receive data + if RSync goes to recovery handling*/ + pRx_EseCntx->pRsp = AtrRsp; + pRx_EseCntx->pRsp->len = 0; + if(initParam.interfaceReset) /* Do interface reset */ + { + /*After power ON , initialization state takes 5ms after which slave enters active + state where slave can exchange data with the master */ + sm_sleep(WAKE_UP_DELAY_MS); + phNxpEse_clearReadBuffer(conn_ctx); +#if defined(T1oI2C_UM11225) + /* Interface Reset respond with ATR*/ + status = phNxpEseProto7816_RSync(conn_ctx); + if(status == TRUE) + { + status = phNxpEseProto7816_GetAtr(conn_ctx, AtrRsp); + } + +#elif defined(T1oI2C_GP1_0) + /* For GP soft reset does not respond with CIP so master should send CIP req. seperatly */ + status = phNxpEseProto7816_RSync(conn_ctx); + if(status == TRUE) + { + status = phNxpEseProto7816_GetCip(conn_ctx, AtrRsp); + } +#endif + } + else /* Do R-Sync */ + { + status = phNxpEseProto7816_RSync(conn_ctx); + } + return status; +} + +/****************************************************************************** + * Function phNxpEseProto7816_Close + * + * Description This function is used to close the 7816 protocol stack instance + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_Close(void* conn_ctx) +{ + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + bool_t status = FALSE; + /*Explicitly Initilising to NULL as the Application layer does not intend to receive a response*/ + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + pRx_EseCntx->pRsp = NULL; + + if(phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState != PH_NXP_ESE_PROTO_7816_IDLE) + return status; + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_DEINIT; + phNxpEseProto7816_3_Var.recoveryCounter = 0; + phNxpEseProto7816_3_Var.wtx_counter = 0; +#if defined(T1oI2C_UM11225) + /* send the end of session s-frame */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = PROP_END_APDU_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_EOS; +#elif defined(T1oI2C_GP1_0) + /* send the release request s-frame */ + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = RELEASE_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_RELEASE; +#endif + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status; +} + +#if defined(T1oI2C_UM11225) +/****************************************************************************** + * Function phNxpEseProto7816_IntfReset + * + * Description This function is used to reset just the current interface + and get the ATR response on successful reset + * + * param[in] phNxpEse_data: ATR response from ESE + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_IntfReset(void* conn_ctx, phNxpEse_data *AtrRsp) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + + ENSURE_OR_GO_EXIT(AtrRsp != NULL); + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = INTF_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_INTF_RST; + pRx_EseCntx->pRsp = AtrRsp; + pRx_EseCntx->pRsp->len = 0; + phNxpEse_clearReadBuffer(conn_ctx); + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; +exit: + return status ; +} + +/****************************************************************************** + * Function phNxpEseProto7816_ChipReset + * + * Description This function is used to reset just the current interface + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_ChipReset(void* conn_ctx) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = CHIP_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_CHIP_RST; + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status ; +} +#endif + +#if defined(T1oI2C_GP1_0) +/****************************************************************************** + * Function phNxpEseProto7816_SoftReset + * + * Description This function is used only for T1oI2C GP to reset just the current interface + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_SoftReset(void* conn_ctx) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = SWR_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_SWR; + phNxpEse_clearReadBuffer(conn_ctx); + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status ; +} + +/****************************************************************************** + * Function phNxpEseProto7816_ColdReset + * + * Description This function is used to reset just the current interface + * + * param[in] void + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_ColdReset(void* conn_ctx) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = COLD_RESET_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_COLD_RST; + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; + return status ; +} +#endif +/****************************************************************************** + * Function phNxpEseProto7816_SetIfscSize + * + * Description This function is used to set the max T=1 data send size + * + * param[in] uint16_t IFSC_Size + * + * Returns Always return TRUE (1). + * + ******************************************************************************/ +bool_t phNxpEseProto7816_SetIfscSize(uint16_t IFSC_Size) +{ + iFrameInfo_t *pNextTx_IframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.IframeInfo; + pNextTx_IframeInfo->maxDataLen = IFSC_Size; + return TRUE; +} + + +#if defined(T1oI2C_UM11225) +/****************************************************************************** + * Function phNxpEseProto7816_GetAtr + * + * Description This function is used to reset just the current interface + * + * param[in] phNxpEse_data : ATR response from ESE + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_GetAtr(void* conn_ctx, phNxpEse_data *pRsp) +{ + bool_t status = FALSE; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + + ENSURE_OR_GO_EXIT(pRsp != NULL); + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = ATR_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_ATR; + pRx_EseCntx->pRsp = pRsp; + pRx_EseCntx->pRsp->len = 0; + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; +exit: + return status ; +} +#endif + +#if defined(T1oI2C_GP1_0) +/****************************************************************************** + * Function phNxpEseProto7816_GetCip + * + * Description This function is used only by T1oI2c GP to get CIP response + * + * param[in] phNxpEse_data : CIP response from ESE + * + * Returns On success return TRUE or else FALSE. + * + ******************************************************************************/ +bool_t phNxpEseProto7816_GetCip(void* conn_ctx, phNxpEse_data *pRsp) +{ + bool_t status = FALSE; + phNxpEseRx_Cntx_t *pRx_EseCntx = &phNxpEseProto7816_3_Var.phNxpEseRx_Cntx; + sFrameInfo_t *pNextTx_SframeInfo = &phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.SframeInfo; + + ENSURE_OR_GO_EXIT(pRsp != NULL); + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_TRANSCEIVE; + phNxpEseProto7816_3_Var.phNxpEseNextTx_Cntx.FrameType= SFRAME; + pNextTx_SframeInfo->sFrameType = CIP_REQ; + phNxpEseProto7816_3_Var.phNxpEseProto7816_nextTransceiveState = SEND_S_CIP; + pRx_EseCntx->pRsp = pRsp; + pRx_EseCntx->pRsp->len = 0; + status = TransceiveProcess(conn_ctx); + if(FALSE == status) + { + /* reset all the structures */ + LOG_E("%s TransceiveProcess failed ", __FUNCTION__); + } + + phNxpEseProto7816_3_Var.phNxpEseProto7816_CurrentState = PH_NXP_ESE_PROTO_7816_IDLE; +exit: + return status ; +} +#endif +/** @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h new file mode 100644 index 00000000000..ccfd00e87c5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h @@ -0,0 +1,443 @@ +/* + * Copyright 2010-2014,2018-2020 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _PHNXPESEPROTO7816_3_H_ +#define _PHNXPESEPROTO7816_3_H_ +#include + + +/** + * \addtogroup ISO7816-3_protocol_lib + * \brief 7816-3 PROTOCOL STACK + * @{ */ + +/********************* Definitions and structures *****************************/ + +/*! + * \brief S-Frame types used in 7816-3 protocol stack + */ +typedef enum sFrameTypes { + RESYNCH_REQ = 0x00,/*!< Re-synchronisation request between host and ESE */ + RESYNCH_RSP = 0x20,/*!< Re-synchronisation response between host and ESE */ + IFSC_REQ = 0x01,/*!< IFSC size request */ + IFSC_RES = 0x21,/*!< IFSC size response */ + ABORT_REQ = 0x02,/*!< Abort request */ + ABORT_RES = 0x22,/*!< Abort response */ + WTX_REQ = 0x03,/*!< WTX request */ + WTX_RSP = 0x23,/*!< WTX response */ +#if defined(T1oI2C_UM11225) + INTF_RESET_REQ = 0x0F,/*!< Interface reset request */ + INTF_RESET_RSP = 0x2F,/*!< Interface reset response */ + PROP_END_APDU_REQ = 0x05,/*!< Proprietary Enf of APDU request */ + PROP_END_APDU_RSP = 0x25,/*!< Proprietary Enf of APDU response */ + CHIP_RESET_REQ = 0x06, /*chip reset request*/ + CHIP_RESET_RES = 0x26, /*chip reset response*/ + ATR_REQ = 0x07, /* get ATR request*/ + ATR_RES = 0x27, /*get ATR response*/ +#elif defined(T1oI2C_GP1_0) + SWR_REQ = 0x0F,/*!< Software reset request */ + SWR_RSP = 0x2F,/*!< Software reset response */ + COLD_RESET_REQ = 0x1E, /*cold reset request*/ + COLD_RESET_RES = 0x3E, /*cold reset response*/ + RELEASE_REQ = 0x06, /* Release request*/ + RELEASE_RES = 0x26, /* Release response*/ + CIP_REQ = 0x04,/*!< Get CIP request */ + CIP_RES = 0x24,/*!< Get CIP response */ +#endif + INVALID_REQ_RES /*!< Invalid request */ + } sFrameTypes_t; + +/*! + * \brief R-Frame types used in 7816-3 protocol stack + */ +typedef enum rFrameTypes +{ + RACK = 0x01, /*!< R-frame Acknowledgement frame indicator */ + RNACK = 0x02 /*!< R-frame Negative-Acknowledgement frame indicator */ +}rFrameTypes_t; + +/*! + * \brief R-Frame error types used 7816-3 protocol stack + */ +typedef enum rFrameErrorTypes +{ + NO_ERROR, /*!< R-frame received with success */ + PARITY_ERROR, /*!< R-frame received with parity error */ + OTHER_ERROR, /*!< R-frame received with Other error */ + SOF_MISSED_ERROR, /*!< R-frame received with frame missing error */ + UNDEFINED_ERROR /*!< R-frame received with some undefined error */ +}rFrameErrorTypes_t; + +/*! + * \brief Frame types used in 7816-3 protocol stack + */ +typedef enum phNxpEseProto7816_FrameTypes +{ + IFRAME,/*!< Frame type: I-frame */ + SFRAME,/*!< Frame type: S-frame */ + RFRAME,/*!< Frame type: R-frame */ + INVALID,/*!< Frame type: Invalid */ + UNKNOWN /*!< Frame type: Unknown */ +}phNxpEseProto7816_FrameTypes_t; + +/*! + * \brief 7816-3 protocol stack states + */ +typedef enum phNxpEseProto7816_State +{ + PH_NXP_ESE_PROTO_7816_IDLE,/*!< 7816-3 protocol state: IDLE */ + PH_NXP_ESE_PROTO_7816_TRANSCEIVE,/*!< 7816-3 protocol state: TRANSCEIVE going on */ + PH_NXP_ESE_PROTO_7816_DEINIT /*!< 7816-3 protocol state: DeInit going on */ +}phNxpEseProto7816_State_t; + +/*! + * \brief 7816-3 protocol transceive states + */ +typedef enum phNxpEseProto7816_TransceiveStates +{ + IDLE_STATE, /*!< 7816-3 protocol transceive state: IDLE */ + SEND_IFRAME, /*!< 7816-3 protocol transceive state: I-frame to be sent */ + SEND_R_NACK, /*!< 7816-3 protocol transceive state: R-NACK frame to be sent */ + SEND_R_ACK, /*!< 7816-3 protocol transceive state: R-ACK frame to be sent */ + SEND_S_RSYNC, /*!< 7816-3 protocol transceive state: S-frame re-synchronisation command to be sent */ +#if defined(T1oI2C_UM11225) + SEND_S_INTF_RST, /*!< 7816-3 protocol transceive state: S-frame interface reset command to be sent */ + SEND_S_EOS, /*!< 7816-3 protocol transceive state: S-frame end of session command to be sent */ + SEND_S_ATR, /*!< 7816-3 protocol transceive state: S-frame ATR command to be sent */ + SEND_S_CHIP_RST, /*!< 7816-3 protocol transceive state: S-frame chip reset command to be sent */ +#elif defined(T1oI2C_GP1_0) + SEND_S_SWR, /*!< 7816-3 protocol transceive state: S-frame Software reset command to be sent */ + SEND_S_RELEASE, /*!< 7816-3 protocol transceive state: S-frame RELEASE command to be sent */ + SEND_S_CIP, /*!< 7816-3 protocol transceive state: S-frame CIP command to be sent */ + SEND_S_COLD_RST, /*!< 7816-3 protocol transceive state: S-frame cold reset command to be sent */ +#endif + SEND_S_WTX_REQ, /*!< 7816-3 protocol transceive state: S-frame WTX command to be sent */ + SEND_S_WTX_RSP, /*!< 7816-3 protocol transceive state: S-frame WTX response to be sent */ + +}phNxpEseProto7816_TransceiveStates_t; + +/*! + * \brief I-frame information structure for ISO 7816-3 + * + * This structure holds the information of I-frame used for sending + * and receiving the frame packet. + * + */ +typedef struct iFrameInfo +{ + bool_t isChained; /*!< I-frame: Indicates if more frames to follow in the same data packet or not */ + uint8_t *p_data; /*!< I-frame: Actual data (Information field (INF)) */ + uint8_t seqNo; /*!< I-frame: Sequence number of the I-frame */ + uint32_t maxDataLen; /*!< I-frame: Maximum data length to be allowed in a single I-frame */ + uint32_t dataOffset; /*!< I-frame: Offset to the actual data(INF) for the current frame of the packet */ + uint32_t totalDataLen; /*!< I-frame: Total data left in the packet, used to set the chained flag/calculating offset */ + uint32_t sendDataLen; /*!< I-frame: the length of the I-frame actual data */ +}iFrameInfo_t; + +/*! + * \brief S-frame information structure for ISO 7816-3 + * + * This structure holds the information of S-frame used for sending + * and receiving the frame packet. + * + */ +typedef struct sFrameInfo +{ + sFrameTypes_t sFrameType;/*!< S-frame: Type of S-frame cmd/rsp */ +}sFrameInfo_t; + +/*! + * \brief R-frame information structure for ISO 7816-3 + * + * This structure holds the information of R-frame used for sending + * and receiving the frame packet. + * + */ +typedef struct rFrameInfo +{ + uint8_t seqNo; /*!< R-frame: Sequence number of the expected I-frame */ + rFrameErrorTypes_t errCode; /*!< R-frame: Error type */ +}rFrameInfo_t; + +/*! + * \brief Next/Last Tx information structure holding transceive data + * + * This structure holds the information of the next/last sent + * I-frame/R-frame/S-frame depending on the frame type + * + */ +typedef struct phNxpEseProto7816_NextTx_Info +{ + //union { + iFrameInfo_t + IframeInfo; /*!< Information of the I-frame to be send next or the last sent I-frame depending on the frame type */ + rFrameInfo_t + RframeInfo; /*!< Information of the R-frame to be send next or the last sent R-frame depending on the frame type */ + sFrameInfo_t + SframeInfo; /*!< Information of the S-frame to be send next or the last sent S-frame depending on the frame type */ + //} f; + phNxpEseProto7816_FrameTypes_t FrameType; /*!< Frame (I/R/S frames) type to be sent next */ +}phNxpEseProto7816_NextTx_Info_t; + +/*! + * \brief Last sent Tx ransceive data + * + * This structure holds the information of the last sent + * I-frame/R-frame/S-frame + * + */ +typedef phNxpEseProto7816_NextTx_Info_t phNxpEseProto7816_LastTx_Info_t; + +/*! + * \brief Last Rx information structure holding transceive data + * + * This structure holds the information of the next/last sent + * I-frame/R-frame/S-frame + * + */ +typedef struct phNxpEseRx_Cntx +{ + iFrameInfo_t lastRcvdIframeInfo; /*!< I-frame: Last received frame */ + rFrameInfo_t lastRcvdRframeInfo; /*!< R-frame: Last received frame */ + sFrameInfo_t lastRcvdSframeInfo; /*!< S-frame: Last received frame */ + phNxpEseProto7816_FrameTypes_t lastRcvdFrameType; /*!< Last received frame type */ + phNxpEse_data *pRsp; +}phNxpEseRx_Cntx_t; + +/*! + * \brief 7816-3 protocol stack context structure + * + * This structure holds the complete information of the + * 7816-3 protocol stack context + * + */ +typedef struct phNxpEseProto7816 +{ + phNxpEseProto7816_LastTx_Info_t phNxpEseLastTx_Cntx; /*!< Last transmitted frame information */ + phNxpEseProto7816_NextTx_Info_t phNxpEseNextTx_Cntx; /*!< Next frame to be transmitted */ + phNxpEseRx_Cntx_t phNxpEseRx_Cntx; /*!< Last received frame information */ + phNxpEseProto7816_TransceiveStates_t phNxpEseProto7816_nextTransceiveState; /*!< Next Transceive state. It determines the next + action to be done from host */ + phNxpEseProto7816_State_t phNxpEseProto7816_CurrentState;/*!< Current protocol stack state */ + uint8_t recoveryCounter; /*!< Keeps track of number of error recovery done. Stack exits after it reaches max. count */ + unsigned long int wtx_counter_limit; /*!< Max. WTX counter limit */ + unsigned long int wtx_counter; /*!< WTX count tracker */ + uint8_t timeoutCounter; /*!< Keeps track of number of timeout happened. Stack exits after it reaches max. count */ + phNxpEseProto7816_FrameTypes_t lastSentNonErrorframeType; /*!< Copy of the last sent non-error frame type: R-ACK, S-frame, I-frame */ + unsigned long int rnack_retry_limit; + unsigned long int rnack_retry_counter; +}phNxpEseProto7816_t; + +/*! + * \brief 7816-3 protocol stack init params + * + * This structure holds the parameters to be passed to open 7816-3 protocl stack instance + * + */ +typedef struct phNxpEseProto7816InitParam +{ + unsigned long int wtx_counter_limit; /*!< WTX count limit */ + bool_t interfaceReset; /*!< INTF reset required or not>*/ + unsigned long int rnack_retry_limit; +}phNxpEseProto7816InitParam_t; + +/*! + * \brief 7816-3 protocol PCB bit level structure + * + * This structure holds the bit level information of PCB byte + * as per 7816-3 protocol + * + */ +typedef struct phNxpEseProto7816_PCB_bits { + uint8_t lsb :1; /*!< PCB: lsb */ + uint8_t bit2 :1; /*!< PCB: bit2 */ + uint8_t bit3 :1; /*!< PCB: bit3 */ + uint8_t bit4 :1; /*!< PCB: bit4 */ + uint8_t bit5 :1; /*!< PCB: bit5 */ + uint8_t bit6 :1; /*!< PCB: bit6 */ + uint8_t bit7 :1; /*!< PCB: bit7 */ + uint8_t msb :1; /*!< PCB: msb */ +}phNxpEseProto7816_PCB_bits_t; + +/*! + * \brief 7816_3 protocol stack instance + */ +//phNxpEseProto7816_t phNxpEseProto7816_3_Var; + +/*! + * \brief Max. size of the frame that can be sent + */ +#define IFSC_SIZE_SEND 254 +/*! + * \brief Delay to be used before sending the next frame, after error reported by ESE + */ +#define DELAY_ERROR_RECOVERY 3500 +/*! + * \brief 7816-3 protocol frame header length + */ +#if defined(T1oI2C_UM11225) + #define PH_PROTO_7816_HEADER_LEN 0x03 // LEN field is 1 byte +#elif defined(T1oI2C_GP1_0) + #define PH_PROTO_7816_HEADER_LEN 0x04 // LEN field is 2 byte +#endif +/*! + * \brief 7816-3 protocol frame CRC length + */ +#define PH_PROTO_7816_CRC_LEN 0x02 +/*! + * \brief 7816-3 Chaining flag bit for masking + */ +#define PH_PROTO_7816_CHAINING 0x20 +/*! + * \brief 7816-3 frame length offset + */ +#define PH_PROPTO_7816_FRAME_LENGTH_OFFSET 0x02 +/*! + * \brief 7816-3 S-block request command mask + */ +#define PH_PROTO_7816_S_BLOCK_REQ 0xC0 +/*! + * \brief 7816-3 S-block response mask + */ +#define PH_PROTO_7816_S_BLOCK_RSP 0xE0 +/*! + * \brief 7816-3 S-block reset command mask + */ +#define PH_PROTO_7816_S_RESET 0x0F +/*! + * \brief 7816-3 S-block End of APDU cmd mask + */ +#define PH_PROTO_7816_S_END_OF_APDU 0x05 +/*! + * \brief 7816-3 S-block WTX mask + */ +#define PH_PROTO_7816_S_WTX 0x03 +/*! + * \brief 7816-3 S-block re-sync mask + */ +#define PH_PROTO_7816_S_RESYNCH 0x00 +/*! + * \brief 7816-3 protocol max. error retry counter + */ +#define PH_PROTO_7816_FRAME_RETRY_COUNT 10 +/*! + * \brief 7816-3 protocol max. WTX default count + */ +#define PH_PROTO_WTX_DEFAULT_COUNT 500 +/*! + * \brief 7816-3 protocol max. timeout retry count + */ +#define PH_PROTO_7816_TIMEOUT_RETRY_COUNT 1 +/*! + * \brief 7816-3 to represent magic number zero + */ +#define PH_PROTO_7816_VALUE_ZERO 0x00 +/*! + * \brief 7816-3 to represent magic number one + */ +#define PH_PROTO_7816_VALUE_ONE 0x01 +/*! + * \brief 7816-3 for max retry for CRC error + */ +#define MAX_RNACK_RETRY_LIMIT 0x02 +/*! + * \brief 7816-3 S-block chip reset mask + */ +#if defined(T1oI2C_UM11225) +#define PH_PROTO_7816_S_CHIP_RST 0x06 +#elif defined(T1oI2C_GP1_0) +#define PH_PROTO_7816_S_COLD_RST 0x1E +#endif +/*! + * \brief 7816-3 S-block get atr mask + */ +#define PH_PROTO_7816_S_GET_ATR 0x07 +/*! + * \brief 7816-3 S-block software reset mask + */ +#define PH_PROTO_7816_S_SWR 0x0F +/*! + * \brief 7816-3 S-block release cmd mask + */ +#define PH_PROTO_7816_S_RELEASE 0x06 +/*! + * \brief 7816-3 S-block get CIP cmd mask + */ +#define PH_PROTO_7816_S_GET_CIP 0x04 + +/* T=1 protocol Block format for T1oI2C UM11225_SE050 + ___________________________________________________________________________________________________ +| Prologue Filed (Mandatory) | Information Field (Optional)| Epilogue Filed (Mandatory) | +|________________________________________|_____________________________|____________________________| +|NAD(1 byte) | PCB(1 byte) | LEN(1 byte) | INF(LEN bytes) | CRC(2 bytes) | | +|____________|_____________|_____________|_____________________________|____________________________| | +*/ + +/* T=1 protocol Block format for T1oI2C GP + ___________________________________________________________________________________________________ +| Prologue Filed (Mandatory) | Information Field (Optional)| Epilogue Filed (Mandatory) | +|________________________________________|_____________________________|____________________________| +|NAD(1 byte) | PCB(1 byte) | LEN(2 byte) | INF(LEN bytes) | CRC(2 bytes) | | +|____________|_____________|_____________|_____________________________|____________________________| | +*/ + +#define PH_PROPTO_7816_NAD_OFFSET 0 +#define PH_PROPTO_7816_PCB_OFFSET 1 +#define PH_PROPTO_7816_LEN_UPPER_OFFSET 2 +#define PH_PROPTO_7816_LEN_LOWER_OFFSET 3 /* for GP lower byte will be a part of T=1 protocol frame*/ +#define PH_PROPTO_7816_INF_BYTE_OFFSET (PH_PROTO_7816_HEADER_LEN) + + + +/*! + * \brief Start of frame marker + * \ communication Direction NAD value + * \ SE host to SE 0x5A + * \ SE to SE host 0xA5 + * \ eUICC host to Euicc 0x4B + * \ eUICC to eUICC host 0xB4 + */ +#define SEND_PACKET_SOF 0x5A +/*! + * \Retrieve Information Filed from 7816-3 T=1 protocol frame + * NAD -1 byte + * PCB -1 byte + * LEN -(1 or 3 bytes for UM11225_SE050) & (2 bytes for GP) + * CRC16 -2 bytes + */ +#define PH_PROTO_7816_INF_FILED (PH_PROTO_7816_HEADER_LEN + PH_PROTO_7816_CRC_LEN) +/* + * APIs exposed from the 7816-3 protocol layer + */ + +#if defined(T1oI2C_UM11225) +bool_t phNxpEseProto7816_IntfReset(void* conn_ctx, phNxpEse_data *AtrRsp); +bool_t phNxpEseProto7816_GetAtr(void* conn_ctx, phNxpEse_data *pRsp); +bool_t phNxpEseProto7816_ChipReset(void* conn_ctx); +#endif +bool_t phNxpEseProto7816_Close(void* conn_ctx); +bool_t phNxpEseProto7816_Open(void* conn_ctx, phNxpEseProto7816InitParam_t initParam , phNxpEse_data *AtrRsp); +bool_t phNxpEseProto7816_Transceive(void* conn_ctx, phNxpEse_data *pCmd, phNxpEse_data *pRsp); +bool_t phNxpEseProto7816_Reset(void); +bool_t phNxpEseProto7816_SetIfscSize(uint16_t IFSC_Size); +bool_t phNxpEseProto7816_ResetProtoParams(void); +#if defined(T1oI2C_GP1_0) +bool_t phNxpEseProto7816_SoftReset(void* conn_ctx); +bool_t phNxpEseProto7816_GetCip(void* conn_ctx, phNxpEse_data *pRsp); +bool_t phNxpEseProto7816_ColdReset(void* conn_ctx); +#endif +uint8_t getMaxSupportedSendIFrameSize(void); +/** @} */ +#endif /* _PHNXPESEPROTO7816_3_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c new file mode 100644 index 00000000000..beb535004ad --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c @@ -0,0 +1,766 @@ +/* + * Copyright 2012-2014,2018-2020 NXP + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include "sm_types.h" +#include "sm_timer.h" +#include + +#ifdef FLOW_VERBOSE +#define NX_LOG_ENABLE_SMCOM_DEBUG 1 +#endif + +#include "nxLog_smCom.h" +#include "nxEnsure.h" + +#if defined(USE_RTOS) && USE_RTOS == 1 +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#endif + +#define RECIEVE_PACKET_SOF 0xA5 +#define CHAINED_PACKET_WITHSEQN 0x60 +#define CHAINED_PACKET_WITHOUTSEQN 0x20 +static int phNxpEse_readPacket(void* conn_ctx, void *pDevHandle, uint8_t * pBuffer, int nNbBytesToRead); +static int poll_sof_chained_delay = 0; + +/*********************** Global Variables *************************************/ + +/* ESE Context structure */ +phNxpEse_Context_t gnxpese_ctxt; + +/****************************************************************************** + * Function phNxpEse_init + * + * Description This function is called by smCom during the + * initialization of the ESE. It initializes protocol stack instance variable + * + * param[in] connection context + * param[in] phNxpEse_initParams: ESE communication mode + * param[out] phNxpEse_data: ATR Response from ESE + * + * Returns This function return ESESTATUS_SUCCES (0) in case of success + * In case of failure returns other failure value. + * + ******************************************************************************/ +ESESTATUS phNxpEse_init(void *conn_ctx, phNxpEse_initParams initParams, phNxpEse_data *AtrRsp) +{ + ESESTATUS wConfigStatus = ESESTATUS_SUCCESS; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + bool_t status = FALSE; + phNxpEseProto7816InitParam_t protoInitParam; + phNxpEse_memset(&protoInitParam, 0x00, sizeof(phNxpEseProto7816InitParam_t)); + protoInitParam.rnack_retry_limit = MAX_RNACK_RETRY_LIMIT; + protoInitParam.wtx_counter_limit = PH_PROTO_WTX_DEFAULT_COUNT; + + if (ESE_MODE_NORMAL == initParams.initMode) /* TZ/Normal wired mode should come here*/ + { + protoInitParam.interfaceReset = TRUE; + } + else + { + protoInitParam.interfaceReset = FALSE; + /*RFU*/ + } + + /* T=1 Protocol layer open */ + status = phNxpEseProto7816_Open((void*)nxpese_ctxt, protoInitParam , AtrRsp); + if(FALSE == status) + { + wConfigStatus = ESESTATUS_FAILED; + LOG_E("phNxpEseProto7816_Open failed "); + } + return wConfigStatus; +} + +/****************************************************************************** + * Function phNxpEse_open + * + * Description This function is called by smCom during the + * initialization of the ESE. It opens the physical connection + * with ESE and initializes the protocol stack + * + * param[in] Pointer to connection context + * param[in] phNxpEse_initParams: ESE communication mode + * + * Returns This function return ESESTATUS_SUCCES (0) in case of success + * In case of failure returns other failure value. + * + ******************************************************************************/ +ESESTATUS phNxpEse_open(void **conn_ctx, phNxpEse_initParams initParams, const char *pConnString) +{ + phPalEse_Config_t tPalConfig; + phNxpEse_Context_t *pnxpese_ctxt = NULL; + ESESTATUS wConfigStatus = ESESTATUS_SUCCESS; + + if (conn_ctx == NULL) { + pnxpese_ctxt = &gnxpese_ctxt; + } + else { + pnxpese_ctxt = (phNxpEse_Context_t*)phNxpEse_memalloc(sizeof(phNxpEse_Context_t)); + phNxpEse_memset(pnxpese_ctxt, 0, sizeof(phNxpEse_Context_t)); + *conn_ctx = pnxpese_ctxt; + } + + /*When I2C channel is already opened return status as FAILED*/ + if(pnxpese_ctxt->EseLibStatus != ESE_STATUS_CLOSE) + { + LOG_E(" Session already opened"); + return ESESTATUS_BUSY; + } + + phNxpEse_memset(pnxpese_ctxt, 0x00, sizeof(phNxpEse_Context_t)); + phNxpEse_memset(&tPalConfig, 0x00, sizeof(tPalConfig)); + + tPalConfig.pDevName = (int8_t *)pConnString; //"/dev/p73"; /*RFU*/ + /* Initialize PAL layer */ + wConfigStatus = phPalEse_i2c_open_and_configure(&tPalConfig); + if (wConfigStatus != ESESTATUS_SUCCESS) + { + LOG_E("phPalEse_Init Failed"); + goto clean_and_return; + } + /* Copying device handle to ESE Lib context*/ + pnxpese_ctxt->pDevHandle = tPalConfig.pDevHandle; + /* STATUS_OPEN */ + pnxpese_ctxt->EseLibStatus = ESE_STATUS_OPEN; + phNxpEse_memcpy(&pnxpese_ctxt->initParams, &initParams, sizeof(phNxpEse_initParams)); + return wConfigStatus; + + clean_and_return: + if (NULL != pnxpese_ctxt->pDevHandle) + { + phPalEse_i2c_close(pnxpese_ctxt->pDevHandle); + phNxpEse_memset (pnxpese_ctxt, 0x00, sizeof (phNxpEse_Context_t)); + } + pnxpese_ctxt->EseLibStatus = ESE_STATUS_CLOSE; + return ESESTATUS_FAILED; +} + +/****************************************************************************** + * Function phNxpEse_Transceive + * + * Description This function validate ESE state & C-APDU data before sending + * it to 7816 protocol + * + * param[in] connection context + * param[in] phNxpEse_data: Command to ESE C-APDU + * param[out] phNxpEse_data: Response from ESE R-APDU + * + * Returns On Success ESESTATUS_SUCCESS else proper error code + * + ******************************************************************************/ +ESESTATUS phNxpEse_Transceive(void* conn_ctx, phNxpEse_data *pCmd, phNxpEse_data *pRsp) +{ + ESESTATUS status = ESESTATUS_FAILED; + bool_t bStatus = FALSE; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + if((NULL == pCmd) || (NULL == pRsp)) + return ESESTATUS_INVALID_PARAMETER; + + if ((pCmd->len == 0) || pCmd->p_data == NULL ) + { + LOG_E(" phNxpEse_Transceive - Invalid Parameter no data"); + return ESESTATUS_INVALID_PARAMETER; + } + else if ((ESE_STATUS_CLOSE == nxpese_ctxt->EseLibStatus)) + { + LOG_E(" %s ESE Not Initialized ", __FUNCTION__); + return ESESTATUS_NOT_INITIALISED; + } + else if ((ESE_STATUS_BUSY == nxpese_ctxt->EseLibStatus)) + { + LOG_E(" %s ESE - BUSY ", __FUNCTION__); + return ESESTATUS_BUSY; + } + else + { + nxpese_ctxt->EseLibStatus = ESE_STATUS_BUSY; + bStatus = phNxpEseProto7816_Transceive((void*)nxpese_ctxt, pCmd, pRsp); + if(TRUE == bStatus) + { + status = ESESTATUS_SUCCESS; + } + else + { + status = ESESTATUS_FAILED; + } + + if (ESESTATUS_SUCCESS != status) + { + LOG_E(" %s phNxpEseProto7816_Transceive- Failed ", __FUNCTION__); + } + if (nxpese_ctxt->EseLibStatus != ESE_STATUS_CLOSE) { + nxpese_ctxt->EseLibStatus = ESE_STATUS_IDLE; + } + + LOG_D(" %s Exit status 0x%x ", __FUNCTION__, status); + return status; + } +} + +/****************************************************************************** + * Function phNxpEse_reset + * + * Description This function reset the ESE interface and free all + * + * param[in] connection context + * + * Returns It returns ESESTATUS_SUCCESS (0) if the operation is successful else + * ESESTATUS_FAILED(1) + ******************************************************************************/ +ESESTATUS phNxpEse_reset(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_FAILED; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + //bool_t bStatus = phNxpEseProto7816_IntfReset(&AtrRsp); + status = phNxpEse_chipReset((void*)nxpese_ctxt); + if (status != ESESTATUS_SUCCESS) + { + LOG_E("phNxpEse_reset Failed"); + } + return status; +} + +/****************************************************************************** + * Function phNxpEse_EndOfApdu + * + * Description This function is used to send S-frame to indicate END_OF_APDU + * + * param[in] connection context + * + * Returns It returns ESESTATUS_SUCCESS (0) if the operation is successful else + * ESESTATUS_FAILED(1) + * + ******************************************************************************/ +ESESTATUS phNxpEse_EndOfApdu(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_SUCCESS; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + bool_t bStatus = phNxpEseProto7816_Close((void*)nxpese_ctxt); + if(!bStatus) + status = ESESTATUS_FAILED; + return status; +} + + +/****************************************************************************** + * Function phNxpEse_chipReset + * + * Description This function is used to reset the ESE. + * + * param[in] connection context + * + * Returns On Success ESESTATUS_SUCCESS (0) else ESESTATUS_FAILED (1). + * + ******************************************************************************/ +ESESTATUS phNxpEse_chipReset(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_SUCCESS; + bool_t bStatus = FALSE; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + bStatus = phNxpEseProto7816_Reset(); + if(!bStatus) + { + status = ESESTATUS_FAILED; + LOG_E("phNxpEseProto7816_Reset Failed"); + } +#if defined(T1oI2C_UM11225) + bStatus = phNxpEseProto7816_ChipReset((void*)nxpese_ctxt); +#elif defined(T1oI2C_GP1_0) + bStatus = phNxpEseProto7816_ColdReset((void*)nxpese_ctxt); +#endif + if (bStatus != TRUE) + { + LOG_E("phNxpEse_chipReset Failed"); + } + return status; +} + +/****************************************************************************** + * Function phNxpEse_deInit + * + * Description This function de-initializes all the ESE protocol params + * + * param[in] connection context + * + * Returns On Success ESESTATUS_SUCCESS (0) else ESESTATUS_FAILED (1). + * + ******************************************************************************/ +ESESTATUS phNxpEse_deInit(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_SUCCESS; + //bool_t bStatus = FALSE; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + /*bStatus = phNxpEseProto7816_ResetProtoParams(); + if(!bStatus) + { + status = ESESTATUS_FAILED; + }*/ + phPalEse_i2c_close(nxpese_ctxt->pDevHandle); + phNxpEse_memset (nxpese_ctxt, 0x00, sizeof (*nxpese_ctxt)); + //status= phNxpEse_close(); + return status; +} + +/****************************************************************************** + * Function phNxpEse_close + * + * Description This function close the ESE interface and free all + * resources. + * + * param[in] connection context + * + * Returns On Success ESESTATUS_SUCCESS else proper error code. + * + ******************************************************************************/ +ESESTATUS phNxpEse_close(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_SUCCESS; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + if ((ESE_STATUS_CLOSE == nxpese_ctxt->EseLibStatus)) + { + LOG_E(" %s ESE Not Initialized previously ", __FUNCTION__); + return ESESTATUS_NOT_INITIALISED; + } + + phPalEse_i2c_close(nxpese_ctxt->pDevHandle); + phNxpEse_memset (nxpese_ctxt, 0x00, sizeof (*nxpese_ctxt)); + LOG_D("phNxpEse_close - ESE Context deinit completed"); + /* Return success always */ + if(conn_ctx != NULL){ + /*free the memory allocated during phNxpEse_open*/ + phNxpEse_free(conn_ctx); + } + return status; +} + +/****************************************************************************** + * Function phNxpEse_clearReadBuffer + * + * Description This function read out complete data from SE FIFO read buffer + * interface (e.g. I2C) using the driver interface. + * Just to make sure that if host is unable to read complete data + * during previous transaction + * + * param[in] void*: connection context + * + * Returns void + * + ******************************************************************************/ +void phNxpEse_clearReadBuffer(void* conn_ctx) +{ + int ret = -1; + uint8_t readBuf[MAX_DATA_LEN]; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + LOG_D("%s Enter ..", __FUNCTION__); + + ret = phPalEse_i2c_read(nxpese_ctxt->pDevHandle, readBuf, MAX_DATA_LEN); + if(ret < 0) + { + /* Do nothing as nothing to read*/ + } + else + { + LOG_W("Previous transaction buffer is now cleard"); + LOG_MAU8_D("RAW Rx<",readBuf,ret ); + } + return; +} + + +/****************************************************************************** + * Function phNxpEse_read + * + * Description This function read the data from ESE through physical + * interface (e.g. I2C) using the driver interface. + * + * param[in] void*: connection context + * param[out] uint32_t: number of bytes read + * param[out] uint8_t : Read data from ESE + * + * Returns It returns ESESTATUS_SUCCESS (0) if read successful else + * ESESTATUS_FAILED(1) + * + ******************************************************************************/ +ESESTATUS phNxpEse_read(void* conn_ctx, uint32_t *data_len, uint8_t **pp_data) +{ + ESESTATUS status = ESESTATUS_FAILED; + int ret = -1; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + LOG_D("%s Enter ..", __FUNCTION__); + + ENSURE_OR_GO_EXIT(data_len != NULL); + ENSURE_OR_GO_EXIT(pp_data != NULL); + + ret = phNxpEse_readPacket((void*)nxpese_ctxt, nxpese_ctxt->pDevHandle, nxpese_ctxt->p_read_buff, MAX_DATA_LEN); + if(ret < 0) + { + LOG_E("PAL Read status error status = %x", status); + status = ESESTATUS_FAILED; + } + else + { + LOG_MAU8_D("RAW Rx<",nxpese_ctxt->p_read_buff,ret ); + *data_len = ret; + *pp_data = nxpese_ctxt->p_read_buff; + status = ESESTATUS_SUCCESS; + } +exit: + return status; +} + +/****************************************************************************** + * Function phNxpEse_readPacket + * + * Description This function Reads requested number of bytes from + * ESE device into given buffer. + * + * param[in] void*: connection context + * param[in] void: ESE Context + * param[in] uint8_t: pointer to read buffer + * param[in] int : MAX bytes to read + * + * Returns ret - number of successfully read bytes + * -1 - read operation failure + * + ******************************************************************************/ +static int phNxpEse_readPacket(void* conn_ctx, void *pDevHandle, uint8_t * pBuffer, int nNbBytesToRead) +{ + int ret = -1; + int sof_counter = 0;/* one read may take 1 ms*/ + int total_count = 0 ,numBytesToRead=0, headerIndex=0; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + ENSURE_OR_GO_EXIT(pBuffer != NULL); + memset(pBuffer,0,nNbBytesToRead); + do + { + sof_counter++; + ret = -1; + sm_sleep(ESE_POLL_DELAY_MS); /* 1ms delay to give ESE polling delay */ + ret = phPalEse_i2c_read(pDevHandle, pBuffer, 2); /*read NAD PCB byte first*/ + if (ret < 0) + { + /*Polling for read on i2c, hence Debug log*/ + LOG_D("_i2c_read() [HDR]errno : %x ret : %X", errno, ret); + } + if(pBuffer[0] == RECIEVE_PACKET_SOF) + { + /* Read the HEADR of Two bytes*/ + LOG_D("%s Read HDR", __FUNCTION__); + pBuffer[0] = RECIEVE_PACKET_SOF; +#if defined(T1oI2C_UM11225) + numBytesToRead = 1; +#elif defined(T1oI2C_GP1_0) + numBytesToRead = 2; +#endif + headerIndex = 1; + break; + } + if(pBuffer[1] == RECIEVE_PACKET_SOF) + { + /* Read the HEADR of Two bytes*/ + LOG_D("%s Read HDR", __FUNCTION__); + pBuffer[0] = RECIEVE_PACKET_SOF; +#if defined(T1oI2C_UM11225) + numBytesToRead = 2; +#elif defined(T1oI2C_GP1_0) + numBytesToRead = 3; +#endif + headerIndex = 0; + break; + } + /*if host writes invalid frame and host and SE are out of sync*/ + if((pBuffer[0] == 0x00)&&((pBuffer[1] == 0x82)||(pBuffer[1] == 0x92))) + { + LOG_W("%s Recieved NAD byte 0x%x ",__FUNCTION__,pBuffer[0]); + LOG_W("%s NAD error, clearing the read buffer ", __FUNCTION__); + /*retry to get all data*/ +#if defined(T1oI2C_UM11225) + numBytesToRead = 1; +#elif defined(T1oI2C_GP1_0) + numBytesToRead = 2; +#endif + headerIndex = 1; + ret = phPalEse_i2c_read(pDevHandle, &pBuffer[1+headerIndex], numBytesToRead); +#if defined(T1oI2C_UM11225) + total_count = 3; + nNbBytesToRead = pBuffer[2]; +#elif defined(T1oI2C_GP1_0) + total_count = 4; + nNbBytesToRead = (pBuffer[2] << 8 & 0xFF) | (pBuffer[3] & 0xFF) ; +#endif + /* Read the Complete data + two byte CRC*/ + ret = phPalEse_i2c_read(pDevHandle, &pBuffer[PH_PROTO_7816_HEADER_LEN], (nNbBytesToRead+PH_PROTO_7816_CRC_LEN)); + if (ret < 0) + { + LOG_D("_i2c_read() [HDR]errno : %x ret : %X", errno, ret); + ret = -1; + } + else + { + ret = (total_count + (nNbBytesToRead + PH_PROTO_7816_CRC_LEN)); + } + break; + } + /*If it is Chained packet wait for 1 ms*/ + if(poll_sof_chained_delay == 1) + { + LOG_D("%s Chained Pkt, delay read %dms",__FUNCTION__,ESE_POLL_DELAY_MS * CHAINED_PKT_SCALER); + sm_sleep(ESE_POLL_DELAY_MS); + } + else + { + LOG_D("%s Normal Pkt, delay read %dms",__FUNCTION__,ESE_POLL_DELAY_MS * NAD_POLLING_SCALER); + sm_sleep(ESE_POLL_DELAY_MS); + } + } while ((sof_counter < ESE_NAD_POLLING_MAX) && (nxpese_ctxt->EseLibStatus!= ESE_STATUS_CLOSE)); + if((pBuffer[0] == RECIEVE_PACKET_SOF) && (ret > 0)) + { + LOG_D("%s SOF FOUND", __FUNCTION__); + /* Read the HEADR of one/Two bytes based on how two bytes read A5 PCB or 00 A5*/ + ret = phPalEse_i2c_read(pDevHandle, &pBuffer[1+headerIndex], numBytesToRead); + if (ret < 0) + { + LOG_D("_i2c_read() [HDR]errno : %x ret : %X", errno, ret); + } + if((pBuffer[1] == CHAINED_PACKET_WITHOUTSEQN) || (pBuffer[1] == CHAINED_PACKET_WITHSEQN)) + { + poll_sof_chained_delay = 1; + LOG_D("poll_sof_chained_delay value is %d ", poll_sof_chained_delay); + } + else + { + poll_sof_chained_delay = 0; + LOG_D("poll_sof_chained_delay value is %d ", poll_sof_chained_delay); + } +#if defined(T1oI2C_UM11225) + total_count = 3; + nNbBytesToRead = pBuffer[2]; +#elif defined(T1oI2C_GP1_0) + total_count = 4; + nNbBytesToRead = (pBuffer[2] << 8 & 0xFF) | (pBuffer[3] & 0xFF) ; +#endif + /* Read the Complete data + two byte CRC*/ + ret = phPalEse_i2c_read(pDevHandle, &pBuffer[PH_PROTO_7816_HEADER_LEN], (nNbBytesToRead+PH_PROTO_7816_CRC_LEN)); + if (ret < 0) + { + LOG_D("_i2c_read() [HDR]errno : %x ret : %X", errno, ret); + ret = -1; + } + else + { + ret = (total_count + (nNbBytesToRead+PH_PROTO_7816_CRC_LEN)); + } + } + else + { + ret=-1; + } +exit: + return ret; +} +/****************************************************************************** + * Function phNxpEse_WriteFrame + * + * Description This function writes the data to ESE. + * It waits till write callback provide the result of write + * process. + * + * param[in] void*: connection context + * param[in] uint32_t: number of bytes to be written + * param[in] uint8_t : data buffer + * + * Returns It returns ESESTATUS_SUCCESS (0) if write successful else + * ESESTATUS_FAILED(1) + * + ******************************************************************************/ +ESESTATUS phNxpEse_WriteFrame(void* conn_ctx, uint32_t data_len, const uint8_t *p_data) +{ + ESESTATUS status = ESESTATUS_INVALID_PARAMETER; + int32_t dwNoBytesWrRd = 0; + phNxpEse_Context_t* nxpese_ctxt = (conn_ctx == NULL) ? &gnxpese_ctxt : (phNxpEse_Context_t*)conn_ctx; + + /* Create local copy of cmd_data */ + LOG_D("%s Enter ..", __FUNCTION__); + phNxpEse_memcpy(nxpese_ctxt->p_cmd_data, p_data, data_len); + nxpese_ctxt->cmd_len = data_len; + if(nxpese_ctxt->EseLibStatus != ESE_STATUS_CLOSE) + { + dwNoBytesWrRd = phPalEse_i2c_write(nxpese_ctxt->pDevHandle, + nxpese_ctxt->p_cmd_data, + nxpese_ctxt->cmd_len + ); + if (-1 == dwNoBytesWrRd) + { + LOG_E(" - Error in I2C Write....."); + status = ESESTATUS_FAILED; + } + else if (-2 == dwNoBytesWrRd) + { + status = ESESTATUS_INVALID_STATE; + } + else + { + status = ESESTATUS_SUCCESS; + LOG_MAU8_D("RAW Tx>",nxpese_ctxt->p_cmd_data, nxpese_ctxt->cmd_len ); + } + } + else + status = ESESTATUS_INVALID_STATE; + return status; +} + +/****************************************************************************** + * Function phNxpEse_setIfsc + * + * Description This function sets the IFSC size to 240/254 support JCOP OS Update. + * + * param[in] uint16_t IFSC_Size + * + * Returns Always return ESESTATUS_SUCCESS (0). + * + ******************************************************************************/ +ESESTATUS phNxpEse_setIfsc(uint16_t IFSC_Size) +{ + /*SET the IFSC size to 240 bytes*/ + phNxpEseProto7816_SetIfscSize(IFSC_Size); + return ESESTATUS_SUCCESS; +} + +/****************************************************************************** + * Function phNxpEse_memset + * + * Description This function updates destination buffer with val + * data in len size + * + * param[in] buff - Array to be udpated + * param[in] val - value to be updated + * param[in] len - length of array to be updated + * + * Returns Always return ESESTATUS_SUCCESS (0). + * + ******************************************************************************/ +void* phNxpEse_memset(void *buff, int val, size_t len) +{ + return memset(buff, val, len); +} + +/****************************************************************************** + * Function phNxpEse_memcpy + * + * Description This function copies source buffer to destination buffer + * data in len size + * + * param[in] dest - Destination array to be updated + * param[in] src - Source array to be updated + * param[in] len - length of array to be updated + * + * Returns Return pointer to allocated memory location. + * + ******************************************************************************/ +void* phNxpEse_memcpy(void *dest, const void *src, size_t len) +{ + return memcpy(dest, src, len); +} + +/****************************************************************************** + * Function phNxpEse_Memalloc + * + * Description This function allocation memory + * + * param[in] uint32_t size + * + * Returns Return pointer to allocated memory or NULL. + * + ******************************************************************************/ +void *phNxpEse_memalloc(uint32_t size) +{ + return SSS_MALLOC(size); +} + + +/****************************************************************************** + * Function phNxpEse_free + * + * Description This function de-allocation memory + * + * param[in] ptr - Address pointer to previous allocation + * + * Returns void. + * + ******************************************************************************/ +void phNxpEse_free(void* ptr) +{ + ENSURE_OR_GO_EXIT(ptr != NULL); + SSS_FREE(ptr); +exit: + return; +} + +#if defined(T1oI2C_UM11225) +/****************************************************************************** + * Function phNxpEse_getAtr + * + * Description This function get ATR from ESE. + * + * param[out] phNxpEse_data: Response from ESE + * + * Returns On Success ESESTATUS_SUCCESS else ESESTATUS_FAILED. + * + ******************************************************************************/ +ESESTATUS phNxpEse_getAtr(void* conn_ctx, phNxpEse_data *pRsp) +{ + bool_t status = FALSE; + status =phNxpEseProto7816_GetAtr(conn_ctx, pRsp); + if (status == FALSE) + { + LOG_E("%s Get ATR Failed ", __FUNCTION__); + return ESESTATUS_FAILED; + } + return ESESTATUS_SUCCESS; +} +#endif + +#if defined(T1oI2C_GP1_0) +/****************************************************************************** + * Function phNxpEse_getCip + * + * Description This function get CIP from ESE. + * + * param[out] phNxpEse_data: Response from ESE + * + * Returns On Success ESESTATUS_SUCCESS else ESESTATUS_FAILED. + * + ******************************************************************************/ +ESESTATUS phNxpEse_getCip(void* conn_ctx, phNxpEse_data *pRsp) +{ + bool_t status = FALSE; + status =phNxpEseProto7816_GetCip(conn_ctx, pRsp); + if (status == FALSE) + { + LOG_E("%s Get CIP Failed ", __FUNCTION__); + return ESESTATUS_FAILED; + } + return ESESTATUS_SUCCESS; +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h new file mode 100644 index 00000000000..6b8e2025bcc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h @@ -0,0 +1,70 @@ +/* + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * + * \brief ESE Lib layer interface to application + * @{ */ + +#ifndef _PHNXPESE_API_H_ +#define _PHNXPESE_API_H_ + +#include +#include +#include +#include "smComT1oI2C.h" + +#include "phEseStatus.h" + +/** + * + * \brief Ese data buffer + * + */ +typedef struct phNxpEse_data +{ + uint32_t len; /*!< length of the buffer */ + uint8_t *p_data; /*!< pointer to a buffer */ +} phNxpEse_data; + + +/** + * + * \brief Ese library init parameters to be set while calling phNxpEse_init + * + */ +typedef struct phNxpEse_initParams +{ + phNxpEse_initMode initMode; /*!< Ese communication mode */ +} phNxpEse_initParams; + + +ESESTATUS phNxpEse_init(void *conn_ctx, phNxpEse_initParams initParams, phNxpEse_data *AtrRsp); +ESESTATUS phNxpEse_open(void **conn_ctx, phNxpEse_initParams initParams, const char *pConnString); +ESESTATUS phNxpEse_Transceive(void* conn_ctx, phNxpEse_data *pCmd, phNxpEse_data *pRsp); +ESESTATUS phNxpEse_deInit(void* conn_ctx); +ESESTATUS phNxpEse_close(void* conn_ctx); +ESESTATUS phNxpEse_reset(void* conn_ctx); +ESESTATUS phNxpEse_chipReset(void* conn_ctx); +ESESTATUS phNxpEse_setIfsc(uint16_t IFSC_Size); +ESESTATUS phNxpEse_EndOfApdu(void* conn_ctx); +void* phNxpEse_memset(void *buff, int val, size_t len); +void* phNxpEse_memcpy(void *dest, const void *src, size_t len); +void *phNxpEse_memalloc(uint32_t size); +void phNxpEse_free(void* ptr); +ESESTATUS phNxpEse_getAtr(void* conn_ctx, phNxpEse_data *pRsp); +ESESTATUS phNxpEse_getCip(void* conn_ctx, phNxpEse_data *pRsp); +/** @} */ +#endif /* _PHNXPESE_API_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h new file mode 100644 index 00000000000..cea3c0c4bca --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h @@ -0,0 +1,54 @@ +/* + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _PHNXPESE_INTERNAL_H_ +#define _PHNXPESE_INTERNAL_H_ + +#include +#include + +#ifdef T1oI2C_UM1225_SE050 +/* MW version 02.13.00 onwards */ +# error Do not define T1oI2C_UM1225_SE050, define T1oI2C_UM11225 instead. +#endif + +/********************* Definitions and structures *****************************/ + +typedef enum +{ + ESE_STATUS_CLOSE = 0x00, + ESE_STATUS_BUSY, + ESE_STATUS_RECOVERY, + ESE_STATUS_IDLE, + ESE_STATUS_OPEN, +} phNxpEse_LibStatus; + +/* I2C Control structure */ +typedef struct phNxpEse_Context +{ + phNxpEse_LibStatus EseLibStatus; /* Indicate if Ese Lib is open or closed */ + void *pDevHandle; + + uint8_t p_read_buff[MAX_DATA_LEN]; + uint16_t cmd_len; + uint8_t p_cmd_data[MAX_DATA_LEN]; + phNxpEse_initParams initParams; +} phNxpEse_Context_t; + + +ESESTATUS phNxpEse_WriteFrame(void* conn_ctx, uint32_t data_len, const uint8_t *p_data); +ESESTATUS phNxpEse_read(void* conn_ctx, uint32_t *data_len, uint8_t **pp_data); +void phNxpEse_clearReadBuffer(void* conn_ctx); + +#endif /* _PHNXPESE_INTERNAL_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h new file mode 100644 index 00000000000..b87c5d4009a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h @@ -0,0 +1,65 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _APDUCOMM_H_ +#define _APDUCOMM_H_ + +#include "sm_types.h" +/// @cond +#define APDU_OFFSET_CLA (0) +#define APDU_OFFSET_INS (1) +#define APDU_OFFSET_P1 (2) +#define APDU_OFFSET_P2 (3) +/// @endcond +#define APDU_OFFSET_LC (4) //!< Zero index based offset into the APDU of the LC field. + +/** + * Contains APDU exchanged between Host and Secure Modulde. + */ +typedef struct +{ + U8 cla; + U8 ins; + U8 p1; + U8 p2; + U8* pBuf; + U16 buflen; + U16 rxlen; + U8 extendedLength; + U8 hasData; + U16 lc; + U8 lcLength; + U8 hasLe; + U16 le; + U8 leLength; + U16 offset; + +#ifdef TGT_A71CL + U8 txHasChkSum; + U16 txChkSum; + U16 txChkSumLength; + U8 rxHasChkSum; + U16 rxChkSum; + U16 rxChkSumLength; +#endif + +} apdu_t; + +/** + * Contains APDU TxRx case as described in ISO/IEC FDIS 7816-3 spec. + */ +typedef enum +{ + APDU_TXRX_CASE_1 = 0x00, + APDU_TXRX_CASE_2 = 0x01, + APDU_TXRX_CASE_2E = 0x02, + APDU_TXRX_CASE_3 = 0x03, + APDU_TXRX_CASE_3E = 0x04, + APDU_TXRX_CASE_4 = 0x05, + APDU_TXRX_CASE_4E = 0x06, + APDU_TXRX_CASE_INVALID = 0xFF, +} apduTxRx_case_t; +#endif //_APDUCOMM_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c new file mode 100644 index 00000000000..0412ae65d10 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c @@ -0,0 +1,170 @@ +/* + * + * Copyright 2016-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * Implements installable communication layer to exchange APDU's between Host and Secure Module. + * Allows the top half of the Host Library to be independent of the actual interconnect + * between Host and Secure Module + */ +#include +#include "smCom.h" +#include "nxLog_smCom.h" + +#if USE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#endif + +#if defined(SMCOM_JRCP_V2) +#include "smComJRCP.h" +#endif + +#if USE_RTOS + static SemaphoreHandle_t gSmComlock; +#elif (__GNUC__ && !AX_EMBEDDED) +#include + /* Only for base session with os */ + static pthread_mutex_t gSmComlock; +#endif + +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#define USE_LOCK 1 +#else +#define USE_LOCK 0 +#endif + +#if USE_RTOS +#define LOCK_TXN() \ + LOG_D("Trying to Acquire Lock"); \ + if (xSemaphoreTake(gSmComlock, portMAX_DELAY) == pdTRUE) \ + LOG_D("LOCK Acquired"); \ + else \ + LOG_D("LOCK Acquisition failed"); +#define UNLOCK_TXN() \ + LOG_D("Trying to Released Lock"); \ + if (xSemaphoreGive(gSmComlock) == pdTRUE) \ + LOG_D("LOCK Released"); \ + else \ + LOG_D("LOCK Releasing failed"); +#elif (__GNUC__ && !AX_EMBEDDED) +#define LOCK_TXN() \ + LOG_D("Trying to Acquire Lock thread: %ld", pthread_self()); \ + pthread_mutex_lock(&gSmComlock); \ + LOG_D("LOCK Acquired by thread: %ld", pthread_self()); + +#define UNLOCK_TXN() \ + LOG_D("Trying to Released Lock by thread: %ld", pthread_self()); \ + pthread_mutex_unlock(&gSmComlock); \ + LOG_D("LOCK Released by thread: %ld", pthread_self()); +#else +#define LOCK_TXN() LOG_D("no lock mode"); +#define UNLOCK_TXN() LOG_D("no lock mode"); +#endif + +static ApduTransceiveFunction_t pSmCom_Transceive = NULL; +static ApduTransceiveRawFunction_t pSmCom_TransceiveRaw = NULL; + +/** + * Install interconnect and protocol specific implementation of APDU transfer functions. + * + */ +U16 smCom_Init(ApduTransceiveFunction_t pTransceive, ApduTransceiveRawFunction_t pTransceiveRaw) +{ + U16 ret = SMCOM_COM_INIT_FAILED; +#if USE_RTOS + gSmComlock = xSemaphoreCreateMutex(); + if (gSmComlock == NULL) { + LOG_E("\n xSemaphoreCreateMutex failed"); + return ret; + } +#elif (__GNUC__ && !AX_EMBEDDED) + if (pthread_mutex_init(&gSmComlock, NULL) != 0) + { + LOG_E("\n mutex init has failed"); + return ret; + } +#endif + pSmCom_Transceive = pTransceive; + pSmCom_TransceiveRaw = pTransceiveRaw; + ret = SMCOM_OK; + return ret; +} + +void smCom_DeInit(void) +{ +#if USE_RTOS + if (gSmComlock != NULL) { + vSemaphoreDelete(gSmComlock); + gSmComlock = NULL; + } +#elif (__GNUC__ && !AX_EMBEDDED) + pthread_mutex_destroy(&gSmComlock); +#endif + pSmCom_Transceive = NULL; + pSmCom_TransceiveRaw = NULL; +} + +/** + * Exchanges APDU without interpreting the message exchanged + * + * @param[in,out] pApdu apdu_t datastructure + * + * @retval ::SMCOM_OK Operation successful + * @retval ::SMCOM_SND_FAILED Send Failed + * @retval ::SMCOM_RCV_FAILED Receive Failed + */ +U32 smCom_Transceive(void *conn_ctx, apdu_t * pApdu) +{ + U32 ret = SMCOM_NO_PRIOR_INIT; + if (pSmCom_Transceive != NULL) + { + LOCK_TXN(); + ret = pSmCom_Transceive(conn_ctx, pApdu); + UNLOCK_TXN(); + } + return ret; +} + +/** + * Exchanges APDU without interpreting the message exchanged + * + * @param[in] pTx Command to be sent to secure module + * @param[in] txLen Length of command to be sent + * @param[in,out] pRx IN: Buffer to contain response; OUT: Response received from secure module + * @param[in,out] pRxLen IN: [TBD]; OUT: Length of response received + * + * @retval ::SMCOM_OK Operation successful + * @retval ::SMCOM_SND_FAILED Send Failed + * @retval ::SMCOM_RCV_FAILED Receive Failed + */ +U32 smCom_TransceiveRaw(void *conn_ctx, U8 * pTx, U16 txLen, U8 * pRx, U32 * pRxLen) +{ + U32 ret = SMCOM_NO_PRIOR_INIT; + if (pSmCom_TransceiveRaw != NULL) + { + LOCK_TXN(); + ret = pSmCom_TransceiveRaw(conn_ctx, pTx, txLen, pRx, pRxLen); + UNLOCK_TXN(); + } + return ret; +} + +#if defined(SMCOM_JRCP_V2) +void smCom_Echo(void *conn_ctx, const char *comp, const char *level, const char *buffer) +{ +#if USE_LOCK + /* If this function is called before smcom init + then Lock fails, return without echo */ + if (pSmCom_TransceiveRaw == NULL) { + return; + } +#endif + LOCK_TXN(); + smComJRCP_Echo(conn_ctx, comp, level, buffer); + UNLOCK_TXN(); +} +#endif \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h new file mode 100644 index 00000000000..797d5b1a0e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h @@ -0,0 +1,49 @@ +/* + * + * Copyright 2016-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * Interface of installable communication layer to exchange APDU's between Host and Secure Module. + */ + +#ifndef _SCCOM_H_ +#define _SCCOM_H_ + +#include "sm_types.h" +#include "apduComm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SMCOM_OK 0x9000 //!< Communication successful +#define SMCOM_SND_FAILED 0x7010 //!< Communication failed while sending data +#define SMCOM_RCV_FAILED 0x7011 //!< Communication failed while receiving data +#define SMCOM_COM_FAILED 0x7012 //!< Cannot open communication link with ax device +#define SMCOM_PROTOCOL_FAILED 0x7013 //!< APDU exchange protocol failed to be established successfully +#define SMCOM_NO_ATR 0x7014 //!< No ATR can be retrieved +#define SMCOM_NO_PRIOR_INIT 0x7015 //!< The callbacks doing the actual transfer have not been installed +#define SMCOM_COM_ALREADY_OPEN 0x7016 //!< Communication link is already open with device +#define SMCOM_COM_INIT_FAILED 0x7017 //!< Communication init failed + + +/* ------------------------------------------------------------------------- */ +typedef U32 (*ApduTransceiveFunction_t) (void* conn_ctx, apdu_t * pAdpu); +typedef U32 (*ApduTransceiveRawFunction_t) (void* conn_ctx, U8 * pTx, U16 txLen, U8 * pRx, U32 * pRxLen); + +U16 smCom_Init(ApduTransceiveFunction_t pTransceive, ApduTransceiveRawFunction_t pTransceiveRaw); +void smCom_DeInit(void); +U32 smCom_Transceive(void *conn_ctx, apdu_t *pApdu); +U32 smCom_TransceiveRaw(void *conn_ctx, U8 *pTx, U16 txLen, U8 *pRx, U32 *pRxLen); + +#if defined(SMCOM_JRCP_V2) +void smCom_Echo(void *conn_ctx, const char *comp, const char *level, const char *buffer); +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c new file mode 100644 index 00000000000..c16c51d8aec --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c @@ -0,0 +1,200 @@ +/* + * + * Copyright 2016-2018,2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * This file implements the SmCom T1oI2C communication layer. + * + *****************************************************************************/ + +#ifdef T1oI2C + +#include + +#include "smComT1oI2C.h" +#include "phNxpEse_Api.h" +#include "phNxpEseProto7816_3.h" + +#include "i2c_a7.h" +#include "sm_printf.h" +#include "phEseStatus.h" +#include "sm_apdu.h" + +#ifdef FLOW_VERBOSE +#define NX_LOG_ENABLE_SMCOM_DEBUG 1 +#else +//#define NX_LOG_ENABLE_SMCOM_DEBUG 1 +#endif + +#include "nxLog_smCom.h" +#include "nxEnsure.h" + +static U32 smComT1oI2C_Transceive(void* conn_ctx, apdu_t * pApdu); +static U32 smComT1oI2C_TransceiveRaw(void* conn_ctx, U8 * pTx, U16 txLen, U8 * pRx, U32 * pRxLen); +U16 smComT1oI2C_AnswerToReset(void* conn_ctx, U8 *T1oI2Catr, U16 *T1oI2CatrLen); + +U16 smComT1oI2C_Close(void *conn_ctx, U8 mode) +{ + ESESTATUS status; + if (conn_ctx) { + status=phNxpEse_EndOfApdu(conn_ctx); + //status=phNxpEse_chipReset(); + if(status ==ESESTATUS_SUCCESS) + { + status = phNxpEse_close(conn_ctx); + if(status != ESESTATUS_SUCCESS) + { + LOG_E("Failed to close ESE interface and free all resources "); + return SMCOM_COM_FAILED; + } + } + else + { + LOG_E("Failed to close session "); + return SMCOM_COM_FAILED; + } + } + else { + LOG_W("Invalid conn_ctx"); + } + return SMCOM_OK; +} + + +U16 smComT1oI2C_Init(void **conn_ctx, const char *pConnString) +{ + ESESTATUS ret; + phNxpEse_initParams initParams; + initParams.initMode = ESE_MODE_NORMAL; + + if(conn_ctx != NULL) { + *conn_ctx = NULL; + } + ret = phNxpEse_open(conn_ctx, initParams, pConnString); + if (ret != ESESTATUS_SUCCESS) + { + LOG_E(" Failed to create physical connection with ESE "); + return SMCOM_COM_FAILED; + } + return SMCOM_OK; +} + +U16 smComT1oI2C_Open(void *conn_ctx, U8 mode, U8 seqCnt, U8 *T1oI2Catr, U16 *T1oI2CatrLen) +{ + ESESTATUS ret; + phNxpEse_data AtrRsp; + phNxpEse_initParams initParams; + initParams.initMode = ESE_MODE_NORMAL; + AtrRsp.len = *T1oI2CatrLen; + AtrRsp.p_data = T1oI2Catr; + + if (conn_ctx == NULL) { + // Connection context is stored in global variable contained in phNxpEse_Api.c + smComT1oI2C_Init(NULL, NULL); + } + + ret=phNxpEse_init(conn_ctx, initParams, &AtrRsp); + if (ret != ESESTATUS_SUCCESS) + { + *T1oI2CatrLen=0; + LOG_E(" Failed to Open session "); + return SMCOM_COM_FAILED; + } + else + { + *T1oI2CatrLen = AtrRsp.len ; /*Retrive INF FIELD*/ + } + return smCom_Init(&smComT1oI2C_Transceive, &smComT1oI2C_TransceiveRaw); +} + +static U32 smComT1oI2C_Transceive(void* conn_ctx, apdu_t * pApdu) +{ + U32 respLen= MAX_APDU_BUF_LENGTH; + U32 retCode = SMCOM_COM_FAILED; + + ENSURE_OR_GO_EXIT(pApdu != NULL); + + retCode = smComT1oI2C_TransceiveRaw(conn_ctx, (U8 *)pApdu->pBuf, pApdu->buflen, pApdu->pBuf, &respLen); + pApdu->rxlen = (U16)respLen; +exit: + return retCode; +} + +static U32 smComT1oI2C_TransceiveRaw(void* conn_ctx, U8 * pTx, U16 txLen, U8 * pRx, U32 * pRxLen) +{ + phNxpEse_data pCmdTrans; + phNxpEse_data pRspTrans={0}; + ESESTATUS txnStatus; + + pCmdTrans.len = txLen; + pCmdTrans.p_data = pTx; + + pRspTrans.len = *pRxLen; + pRspTrans.p_data = pRx; + + LOG_MAU8_D("APDU Tx>", pTx, txLen); + txnStatus = phNxpEse_Transceive(conn_ctx, &pCmdTrans, &pRspTrans); + if ( txnStatus == ESESTATUS_SUCCESS ) + { + *pRxLen = pRspTrans.len; + LOG_MAU8_D("APDU Rx<", pRx, pRspTrans.len); + } + else + { + *pRxLen = 0; + LOG_E(" Transcive Failed "); + return SMCOM_SND_FAILED; + } + + return SMCOM_OK; +} + +U16 smComT1oI2C_AnswerToReset(void* conn_ctx, U8 *T1oI2Catr, U16 *T1oI2CatrLen) +{ + phNxpEse_data pRsp= {0}; + ESESTATUS txnStatus; + U16 status = SMCOM_NO_ATR; + + ENSURE_OR_GO_EXIT(T1oI2Catr != NULL); + ENSURE_OR_GO_EXIT(T1oI2CatrLen != NULL); +#if defined(T1oI2C_UM11225) + txnStatus= phNxpEse_getAtr(conn_ctx, &pRsp); +#elif defined(T1oI2C_GP1_0) + txnStatus= phNxpEse_getCip(conn_ctx, &pRsp); +#endif + if(txnStatus == ESESTATUS_SUCCESS) + { + *T1oI2CatrLen = pRsp.len; + if (pRsp.len > 0) { + memcpy(T1oI2Catr, pRsp.p_data, pRsp.len); + status = SMCOM_OK; + } + else { + LOG_E(" ATR/CIP Length is improper!!!"); + } + } + else + { + *T1oI2CatrLen = 0; + LOG_E(" Failed to Retrieve ATR/CIP status "); + } +exit: + return status; +} + +U16 smComT1oI2C_ComReset(void* conn_ctx) +{ + ESESTATUS status = ESESTATUS_SUCCESS; + status = phNxpEse_deInit(conn_ctx); + if(status !=ESESTATUS_SUCCESS) + { + LOG_E("Failed to Reset 7816 protocol instance "); + return SMCOM_COM_FAILED; + } + return SMCOM_OK; +} + +#endif /* T1oI2C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h new file mode 100644 index 00000000000..6def7131b72 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h @@ -0,0 +1,71 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * This file provides the API of the SmCom T1oI2C communication layer. + * + *****************************************************************************/ + +#ifndef _SMCOMT1OI2C_H_ +#define _SMCOMT1OI2C_H_ + +#include "smCom.h" + +/** + * \ingroup spi_libese + * \brief Ese Channel mode + * + */ +typedef enum +{ + ESE_MODE_NORMAL = 0, /*!< All wired transaction other OSU */ + ESE_MODE_OSU /*!< Jcop Os update mode */ +} phNxpEse_initMode; + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * closes the T=1 o I2C communication layer. + * @param conn_ctx connection context + * @param mode Ese Communication mode either + * ESE_MODE_NORMAL: All wired transaction other OSU or + * ESE_MODE_OSU :Jcop Os update mode + * @return + */ +U16 smComT1oI2C_Close(void *conn_ctx, U8 mode); + +/** + * @param conn_ctx connection context + * Reset the T=1 o protocol instance. + * @return + */ +U16 smComT1oI2C_ComReset(void *conn_ctx); + +/** + * Initializes or resumes the T=1 o I2C communication layer. + * @param conn_ctx IN: connection context + * @param mode Ese Communication mode either ESE_MODE_NORMAL: All wired transaction other OSU or ESE_MODE_OSU :Jcop Os update mode + * @param T1oI2Catr IN: Pointer to buffer to contain SCI2C_ATR value + * @param T1oI2CatrLen IN: Size of buffer provided; OUT: Actual length of atr retrieved + * @return + */ +U16 smComT1oI2C_Open(void *conn_ctx, U8 mode, U8 seqCnt, U8 *T1oI2Catr, U16 *T1oI2CatrLen); + +/** +* Open I2C device. +* @param conn_ctx IN: pointer connection context +* @param pConnParam IN: I2C address +* @return +*/ +U16 smComT1oI2C_Init(void **conn_ctx, const char *pConnString); + +#if defined(__cplusplus) +} +#endif +#endif /* _SMCOMT1OI2C_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c new file mode 100644 index 00000000000..af6f5d57ded --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c @@ -0,0 +1,710 @@ +/* + * Elliptic curve Diffie-Hellman + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2017-2018,2020, NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * RFC 4492 + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDH_C) +#if defined(MBEDTLS_ECDH_ALT) +#include "mbedtls/ecdh.h" +#include "mbedtls/platform_util.h" + +#include + +/* Parameter validation macros based on platform_util.h */ +#define ECDH_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECDH_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) +typedef mbedtls_ecdh_context mbedtls_ecdh_context_mbed; +#endif + +#if 0 +static mbedtls_ecp_group_id mbedtls_ecdh_grp_id( + const mbedtls_ecdh_context *ctx ) +{ +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ctx->grp.id ); +#else + return( ctx->grp_id ); +#endif +} +#endif + +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) +/* + * Generate public key (restartable version) + * + * Note: this internal function relies on its caller preserving the value of + * the output parameter 'd' across continuation calls. This would not be + * acceptable for a public function but is OK here as we control call sites. + */ +int ecdh_gen_public_restartable_o( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + + /* If multiplication is in progress, we already generated a privkey */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, Q, d, &grp->G, + f_rng, p_rng, rs_ctx ) ); + +cleanup: + return( ret ); +} + +/* + * Generate public key + */ +int mbedtls_ecdh_gen_public_o( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECDH_VALIDATE_RET( grp != NULL ); + ECDH_VALIDATE_RET( d != NULL ); + ECDH_VALIDATE_RET( Q != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + return( ecdh_gen_public_restartable_o( grp, d, Q, f_rng, p_rng, NULL ) ); +} +#endif /* !MBEDTLS_ECDH_GEN_PUBLIC_ALT */ + +#if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) +/* + * Compute shared secret (SEC1 3.3.1) + */ +int ecdh_compute_shared_restartable_o( mbedtls_ecp_group *grp, + mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point P; + + mbedtls_ecp_point_init( &P ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, &P, d, Q, + f_rng, p_rng, rs_ctx ) ); + + if( mbedtls_ecp_is_zero( &P ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( z, &P.X ) ); + +cleanup: + mbedtls_ecp_point_free( &P ); + + return( ret ); +} + +/* + * Compute shared secret (SEC1 3.3.1) + */ +int mbedtls_ecdh_compute_shared_o( mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECDH_VALIDATE_RET( grp != NULL ); + ECDH_VALIDATE_RET( Q != NULL ); + ECDH_VALIDATE_RET( d != NULL ); + ECDH_VALIDATE_RET( z != NULL ); + return( ecdh_compute_shared_restartable_o( grp, z, Q, d, + f_rng, p_rng, NULL ) ); +} +#endif /* !MBEDTLS_ECDH_COMPUTE_SHARED_ALT */ + +static void ecdh_init_internal( mbedtls_ecdh_context_mbed *ctx ) +{ + mbedtls_ecp_group_init( &ctx->grp ); + mbedtls_mpi_init( &ctx->d ); + mbedtls_ecp_point_init( &ctx->Q ); + mbedtls_ecp_point_init( &ctx->Qp ); + mbedtls_mpi_init( &ctx->z ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_init( &ctx->rs ); +#endif +} + +/* + * Initialize context + */ +void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx ) +{ + ECDH_VALIDATE( ctx != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + ecdh_init_internal( ctx ); + mbedtls_ecp_point_init( &ctx->Vi ); + mbedtls_ecp_point_init( &ctx->Vf ); + mbedtls_mpi_init( &ctx->_d ); +#else + memset( ctx, 0, sizeof( mbedtls_ecdh_context ) ); + + ctx->var = MBEDTLS_ECDH_VARIANT_NONE; +#endif + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; +#if defined(MBEDTLS_ECP_RESTARTABLE) + ctx->restart_enabled = 0; +#endif +} + +static int ecdh_setup_internal( mbedtls_ecdh_context_mbed *ctx, + mbedtls_ecp_group_id grp_id ) +{ + int ret; + + ret = mbedtls_ecp_group_load( &ctx->grp, grp_id ); + if( ret != 0 ) + { + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } + + return( 0 ); +} + +/* + * Setup context + */ +int mbedtls_ecdh_setup( mbedtls_ecdh_context *ctx, mbedtls_ecp_group_id grp_id ) +{ + ECDH_VALIDATE_RET( ctx != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_setup_internal( ctx, grp_id ) ); +#else + switch( grp_id ) + { + default: + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; + ctx->var = MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0; + ctx->grp_id = grp_id; + ecdh_init_internal( &ctx->ctx.mbed_ecdh ); + return( ecdh_setup_internal( &ctx->ctx.mbed_ecdh, grp_id ) ); + } +#endif +} + +static void ecdh_free_internal( mbedtls_ecdh_context_mbed *ctx ) +{ + mbedtls_ecp_group_free( &ctx->grp ); + mbedtls_mpi_free( &ctx->d ); + mbedtls_ecp_point_free( &ctx->Q ); + mbedtls_ecp_point_free( &ctx->Qp ); + mbedtls_mpi_free( &ctx->z ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_free( &ctx->rs ); +#endif +} + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Enable restartable operations for context + */ +void mbedtls_ecdh_enable_restart( mbedtls_ecdh_context *ctx ) +{ + ECDH_VALIDATE( ctx != NULL ); + + ctx->restart_enabled = 1; +} +#endif + +/* + * Free context + */ +void mbedtls_ecdh_free( mbedtls_ecdh_context *ctx ) +{ + if( ctx == NULL ) + return; + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + mbedtls_ecp_point_free( &ctx->Vi ); + mbedtls_ecp_point_free( &ctx->Vf ); + mbedtls_mpi_free( &ctx->_d ); + ecdh_free_internal( ctx ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + ecdh_free_internal( &ctx->ctx.mbed_ecdh ); + break; + default: + break; + } + + ctx->point_format = MBEDTLS_ECP_PF_UNCOMPRESSED; + ctx->var = MBEDTLS_ECDH_VARIANT_NONE; + ctx->grp_id = MBEDTLS_ECP_DP_NONE; +#endif +} + +static int ecdh_make_params_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, int point_format, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; + size_t grp_len, pt_len; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_gen_public_restartable( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng, rs_ctx ) ) != 0 ) + return( ret ); +#else + if( ( ret = mbedtls_ecdh_gen_public( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng ) ) != 0 ) + return( ret ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + if( ( ret = mbedtls_ecp_tls_write_group( &ctx->grp, &grp_len, buf, + blen ) ) != 0 ) + return( ret ); + + buf += grp_len; + blen -= grp_len; + + if( ( ret = mbedtls_ecp_tls_write_point( &ctx->grp, &ctx->Q, point_format, + &pt_len, buf, blen ) ) != 0 ) + return( ret ); + + *olen = grp_len + pt_len; + return( 0 ); +} + +/* + * Setup and write the ServerKeyExhange parameters (RFC 4492) + * struct { + * ECParameters curve_params; + * ECPoint public; + * } ServerECDHParams; + */ +int mbedtls_ecdh_make_params( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_make_params_internal( ctx, olen, ctx->point_format, buf, blen, + f_rng, p_rng, restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_make_params_internal( &ctx->ctx.mbed_ecdh, olen, + ctx->point_format, buf, blen, + f_rng, p_rng, + restart_enabled ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_read_params_internal( mbedtls_ecdh_context_mbed *ctx, + const unsigned char **buf, + const unsigned char *end ) +{ + return( mbedtls_ecp_tls_read_point( &ctx->grp, &ctx->Qp, buf, + end - *buf ) ); +} + +/* + * Read the ServerKeyExhange parameters (RFC 4492) + * struct { + * ECParameters curve_params; + * ECPoint public; + * } ServerECDHParams; + */ +int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx, + const unsigned char **buf, + const unsigned char *end ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( *buf != NULL ); + ECDH_VALIDATE_RET( end != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, end - *buf ) ) + != 0 ) + return( ret ); + + if( ( ret = mbedtls_ecdh_setup( ctx, grp_id ) ) != 0 ) + return( ret ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_read_params_internal( ctx, buf, end ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_read_params_internal( &ctx->ctx.mbed_ecdh, + buf, end ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +int ecdh_get_params_internal( mbedtls_ecdh_context_mbed *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ); + +int ecdh_get_params_internal_o( mbedtls_ecdh_context_mbed *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ) +{ + int ret; + + /* If it's not our key, just import the public part as Qp */ + if( side == MBEDTLS_ECDH_THEIRS ) + return( mbedtls_ecp_copy( &ctx->Qp, &key->Q ) ); + + /* Our key: import public (as Q) and private parts */ + if( side != MBEDTLS_ECDH_OURS ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_copy( &ctx->Q, &key->Q ) ) != 0 || + ( ret = mbedtls_mpi_copy( &ctx->d, &key->d ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +/* + * Get parameters from a keypair + */ +#if 0 +int mbedtls_ecdh_get_params_o( mbedtls_ecdh_context *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side ) +{ + int ret; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( key != NULL ); + ECDH_VALIDATE_RET( side == MBEDTLS_ECDH_OURS || + side == MBEDTLS_ECDH_THEIRS ); + + if( mbedtls_ecdh_grp_id( ctx ) == MBEDTLS_ECP_DP_NONE ) + { + /* This is the first call to get_params(). Set up the context + * for use with the group. */ + if( ( ret = mbedtls_ecdh_setup( ctx, key->grp.id ) ) != 0 ) + return( ret ); + } + else + { + /* This is not the first call to get_params(). Check that the + * current key's group is the same as the context's, which was set + * from the first key's group. */ + if( mbedtls_ecdh_grp_id( ctx ) != key->grp.id ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_get_params_internal( ctx, key, side ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_get_params_internal( &ctx->ctx.mbed_ecdh, + key, side ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} +#else +int mbedtls_ecdh_get_params_o(mbedtls_ecdh_context *ctx, const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side) +{ + int ret; + + if ((ret = mbedtls_ecp_group_copy(&ctx->grp, &key->grp)) != 0) + return(ret); + + /* If it's not our key, just import the public part as Qp */ + if (side == MBEDTLS_ECDH_THEIRS) + return(mbedtls_ecp_copy(&ctx->Qp, &key->Q)); + + /* Our key: import public (as Q) and private parts */ + if (side != MBEDTLS_ECDH_OURS) + return(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + + if ((ret = mbedtls_ecp_copy(&ctx->Q, &key->Q)) != 0 || + (ret = mbedtls_mpi_copy(&ctx->d, &key->d)) != 0) + return(ret); + + return(0); +} +#endif +static int ecdh_make_public_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, int point_format, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_gen_public_restartable( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng, rs_ctx ) ) != 0 ) + return( ret ); +#else + if( ( ret = mbedtls_ecdh_gen_public( &ctx->grp, &ctx->d, &ctx->Q, + f_rng, p_rng ) ) != 0 ) + return( ret ); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + return mbedtls_ecp_tls_write_point( &ctx->grp, &ctx->Q, point_format, olen, + buf, blen ); +} + +/* + * Setup and export the client public value + */ +int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + ECDH_VALIDATE_RET( f_rng != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_make_public_internal( ctx, olen, ctx->point_format, buf, blen, + f_rng, p_rng, restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_make_public_internal( &ctx->ctx.mbed_ecdh, olen, + ctx->point_format, buf, blen, + f_rng, p_rng, + restart_enabled ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_read_public_internal( mbedtls_ecdh_context_mbed *ctx, + const unsigned char *buf, size_t blen ) +{ + int ret; + const unsigned char *p = buf; + + if( ( ret = mbedtls_ecp_tls_read_point( &ctx->grp, &ctx->Qp, &p, + blen ) ) != 0 ) + return( ret ); + + if( (size_t)( p - buf ) != blen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + return( 0 ); +} + +/* + * Parse and import the client's public value + */ +int mbedtls_ecdh_read_public( mbedtls_ecdh_context *ctx, + const unsigned char *buf, size_t blen ) +{ + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_read_public_internal( ctx, buf, blen ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_read_public_internal( &ctx->ctx.mbed_ecdh, + buf, blen ) ); + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +#endif +} + +static int ecdh_calc_secret_internal( mbedtls_ecdh_context_mbed *ctx, + size_t *olen, unsigned char *buf, + size_t blen, + int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng, + int restart_enabled ) +{ + int ret; +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx *rs_ctx = NULL; +#endif + + if( ctx == NULL || ctx->grp.pbits == 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( restart_enabled ) + rs_ctx = &ctx->rs; +#else + (void) restart_enabled; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ( ret = ecdh_compute_shared_restartable( &ctx->grp, &ctx->z, &ctx->Qp, + &ctx->d, f_rng, p_rng, + rs_ctx ) ) != 0 ) + { + return( ret ); + } +#else + if( ( ret = mbedtls_ecdh_compute_shared( &ctx->grp, &ctx->z, &ctx->Qp, + &ctx->d, f_rng, p_rng ) ) != 0 ) + { + return( ret ); + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + if( mbedtls_mpi_size( &ctx->z ) > blen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + *olen = ctx->grp.pbits / 8 + ( ( ctx->grp.pbits % 8 ) != 0 ); + return mbedtls_mpi_write_binary( &ctx->z, buf, *olen ); +} + +/* + * Derive and export the shared secret + */ +int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int restart_enabled = 0; + ECDH_VALIDATE_RET( ctx != NULL ); + ECDH_VALIDATE_RET( olen != NULL ); + ECDH_VALIDATE_RET( buf != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + restart_enabled = ctx->restart_enabled; +#endif + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + return( ecdh_calc_secret_internal( ctx, olen, buf, blen, f_rng, p_rng, + restart_enabled ) ); +#else + switch( ctx->var ) + { + case MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0: + return( ecdh_calc_secret_internal( &ctx->ctx.mbed_ecdh, olen, buf, + blen, f_rng, p_rng, + restart_enabled ) ); + default: + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } +#endif +} + + + +#endif /*#if defined(MBEDTLS_ECDH_ALT) */ +#endif /* MBEDTLS_ECDH_C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c new file mode 100644 index 00000000000..72be4a536c0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c @@ -0,0 +1,2376 @@ +/* + * The RSA public-key cryptosystem + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019, NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * The following sources were referenced in the design of this implementation + * of the RSA algorithm: + * + * [1] A method for obtaining digital signatures and public-key cryptosystems + * R Rivest, A Shamir, and L Adleman + * http://people.csail.mit.edu/rivest/pubs.html#RSA78 + * + * [2] Handbook of Applied Cryptography - 1997, Chapter 8 + * Menezes, van Oorschot and Vanstone + * + * [3] Malware Guard Extension: Using SGX to Conceal Cache Attacks + * Michael Schwarz, Samuel Weiser, Daniel Gruss, Clémentine Maurice and + * Stefan Mangard + * https://arxiv.org/abs/1702.08719v2 + * + */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_RSA_C) + +#include "mbedtls/rsa.h" +#include "mbedtls/rsa_internal.h" +#include "mbedtls/oid.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_RSA_ALT) + +#if SSS_HAVE_ALT_SSS +# include "sss_mbedtls.h" +#else +# include "ax_mbedtls.h" +#endif + +#if defined(MBEDTLS_PKCS1_V21) +#include "mbedtls/md.h" +#endif + +#if defined(MBEDTLS_PKCS1_V15) && !defined(__OpenBSD__) +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#if defined(MBEDTLS_PKCS1_V15) +/* constant-time buffer comparison */ +static inline int mbedtls_safer_memcmp( const void *a, const void *b, size_t n ) +{ + size_t i; + const unsigned char *A = (const unsigned char *) a; + const unsigned char *B = (const unsigned char *) b; + unsigned char diff = 0; + + for( i = 0; i < n; i++ ) + diff |= A[i] ^ B[i]; + + return( diff ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +int mbedtls_rsa_import( mbedtls_rsa_context *ctx, + const mbedtls_mpi *N, + const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, const mbedtls_mpi *E ) +{ + int ret; + + if( ( N != NULL && ( ret = mbedtls_mpi_copy( &ctx->N, N ) ) != 0 ) || + ( P != NULL && ( ret = mbedtls_mpi_copy( &ctx->P, P ) ) != 0 ) || + ( Q != NULL && ( ret = mbedtls_mpi_copy( &ctx->Q, Q ) ) != 0 ) || + ( D != NULL && ( ret = mbedtls_mpi_copy( &ctx->D, D ) ) != 0 ) || + ( E != NULL && ( ret = mbedtls_mpi_copy( &ctx->E, E ) ) != 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + + if( N != NULL ) + ctx->len = mbedtls_mpi_size( &ctx->N ); + + return( 0 ); +} + +int mbedtls_rsa_import_raw( mbedtls_rsa_context *ctx, + unsigned char const *N, size_t N_len, + unsigned char const *P, size_t P_len, + unsigned char const *Q, size_t Q_len, + unsigned char const *D, size_t D_len, + unsigned char const *E, size_t E_len ) +{ + int ret = 0; + + if( N != NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->N, N, N_len ) ); + ctx->len = mbedtls_mpi_size( &ctx->N ); + } + + if( P != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->P, P, P_len ) ); + + if( Q != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->Q, Q, Q_len ) ); + + if( D != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->D, D, D_len ) ); + + if( E != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->E, E, E_len ) ); + +cleanup: + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + + return( 0 ); +} + +/* + * Checks whether the context fields are set in such a way + * that the RSA primitives will be able to execute without error. + * It does *not* make guarantees for consistency of the parameters. + */ +static int rsa_check_context( mbedtls_rsa_context const *ctx, int is_priv, + int blinding_needed ) +{ +#if !defined(MBEDTLS_RSA_NO_CRT) + /* blinding_needed is only used for NO_CRT to decide whether + * P,Q need to be present or not. */ + ((void) blinding_needed); +#endif + + if( ctx->len != mbedtls_mpi_size( &ctx->N ) || + ctx->len > MBEDTLS_MPI_MAX_SIZE ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + + /* + * 1. Modular exponentiation needs positive, odd moduli. + */ + + /* Modular exponentiation wrt. N is always used for + * RSA public key operations. */ + if( mbedtls_mpi_cmp_int( &ctx->N, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->N, 0 ) == 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Modular exponentiation for P and Q is only + * used for private key operations and if CRT + * is used. */ + if( is_priv && + ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->P, 0 ) == 0 || + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->Q, 0 ) == 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif /* !MBEDTLS_RSA_NO_CRT */ + + /* + * 2. Exponents must be positive + */ + + /* Always need E for public key operations */ + if( mbedtls_mpi_cmp_int( &ctx->E, 0 ) <= 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_RSA_NO_CRT) + /* For private key operations, use D or DP & DQ + * as (unblinded) exponents. */ + if( is_priv && mbedtls_mpi_cmp_int( &ctx->D, 0 ) <= 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); +#else + if( is_priv && + ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) <= 0 || + mbedtls_mpi_cmp_int( &ctx->DQ, 0 ) <= 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Blinding shouldn't make exponents negative either, + * so check that P, Q >= 1 if that hasn't yet been + * done as part of 1. */ +#if defined(MBEDTLS_RSA_NO_CRT) + if( is_priv && blinding_needed && + ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 || + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif + + /* It wouldn't lead to an error if it wasn't satisfied, + * but check for QP >= 1 nonetheless. */ +#if !defined(MBEDTLS_RSA_NO_CRT) + if( is_priv && + mbedtls_mpi_cmp_int( &ctx->QP, 0 ) <= 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif + + return( 0 ); +} + +int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ) +{ + int ret = 0; + + const int have_N = ( mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 ); + const int have_P = ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 ); + const int have_Q = ( mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 ); + const int have_D = ( mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 ); + const int have_E = ( mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0 ); + + /* + * Check whether provided parameters are enough + * to deduce all others. The following incomplete + * parameter sets for private keys are supported: + * + * (1) P, Q missing. + * (2) D and potentially N missing. + * + */ + + const int n_missing = have_P && have_Q && have_D && have_E; + const int pq_missing = have_N && !have_P && !have_Q && have_D && have_E; + const int d_missing = have_P && have_Q && !have_D && have_E; + const int is_pub = have_N && !have_P && !have_Q && !have_D && have_E; + + /* These three alternatives are mutually exclusive */ + const int is_priv = n_missing || pq_missing || d_missing; + + if( !is_priv && !is_pub ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Step 1: Deduce N if P, Q are provided. + */ + + if( !have_N && have_P && have_Q ) + { + if( ( ret = mbedtls_mpi_mul_mpi( &ctx->N, &ctx->P, + &ctx->Q ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + + ctx->len = mbedtls_mpi_size( &ctx->N ); + } + + /* + * Step 2: Deduce and verify all remaining core parameters. + */ + + if( pq_missing ) + { + ret = mbedtls_rsa_deduce_primes( &ctx->N, &ctx->E, &ctx->D, + &ctx->P, &ctx->Q ); + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + + } + else if( d_missing ) + { + if( ( ret = mbedtls_rsa_deduce_private_exponent( &ctx->P, + &ctx->Q, + &ctx->E, + &ctx->D ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + } + + /* + * Step 3: Deduce all additional parameters specific + * to our current RSA implementation. + */ + +#if !defined(MBEDTLS_RSA_NO_CRT) + if( is_priv ) + { + ret = mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ); + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* + * Step 3: Basic sanity checks + */ + + return( rsa_check_context( ctx, is_priv, 1 ) ); +} + +int mbedtls_rsa_export_raw( const mbedtls_rsa_context *ctx, + unsigned char *N, size_t N_len, + unsigned char *P, size_t P_len, + unsigned char *Q, size_t Q_len, + unsigned char *D, size_t D_len, + unsigned char *E, size_t E_len ) +{ + int ret = 0; + + /* Check if key is private or public */ + const int is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + { + /* If we're trying to export private parameters for a public key, + * something must be wrong. */ + if( P != NULL || Q != NULL || D != NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + } + + if( N != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->N, N, N_len ) ); + + if( P != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->P, P, P_len ) ); + + if( Q != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->Q, Q, Q_len ) ); + + if( D != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->D, D, D_len ) ); + + if( E != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->E, E, E_len ) ); + +cleanup: + + return( ret ); +} + +int mbedtls_rsa_export( const mbedtls_rsa_context *ctx, + mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, + mbedtls_mpi *D, mbedtls_mpi *E ) +{ + int ret; + + /* Check if key is private or public */ + int is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + { + /* If we're trying to export private parameters for a public key, + * something must be wrong. */ + if( P != NULL || Q != NULL || D != NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + } + + /* Export all requested core parameters. */ + + if( ( N != NULL && ( ret = mbedtls_mpi_copy( N, &ctx->N ) ) != 0 ) || + ( P != NULL && ( ret = mbedtls_mpi_copy( P, &ctx->P ) ) != 0 ) || + ( Q != NULL && ( ret = mbedtls_mpi_copy( Q, &ctx->Q ) ) != 0 ) || + ( D != NULL && ( ret = mbedtls_mpi_copy( D, &ctx->D ) ) != 0 ) || + ( E != NULL && ( ret = mbedtls_mpi_copy( E, &ctx->E ) ) != 0 ) ) + { + return( ret ); + } + + return( 0 ); +} + +/* + * Export CRT parameters + * This must also be implemented if CRT is not used, for being able to + * write DER encoded RSA keys. The helper function mbedtls_rsa_deduce_crt + * can be used in this case. + */ +int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx, + mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP ) +{ + int ret; + + /* Check if key is private or public */ + int is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Export all requested blinding parameters. */ + if( ( DP != NULL && ( ret = mbedtls_mpi_copy( DP, &ctx->DP ) ) != 0 ) || + ( DQ != NULL && ( ret = mbedtls_mpi_copy( DQ, &ctx->DQ ) ) != 0 ) || + ( QP != NULL && ( ret = mbedtls_mpi_copy( QP, &ctx->QP ) ) != 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#else + if( ( ret = mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + DP, DQ, QP ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#endif + + return( 0 ); +} + +/* + * Initialize an RSA context + */ +void mbedtls_rsa_init( mbedtls_rsa_context *ctx, + int padding, + int hash_id ) +{ + memset( ctx, 0, sizeof( mbedtls_rsa_context ) ); + + mbedtls_rsa_set_padding( ctx, padding, hash_id ); + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_init( &ctx->mutex ); +#endif +} + +/* + * Set padding for an existing RSA context + */ +void mbedtls_rsa_set_padding( mbedtls_rsa_context *ctx, int padding, int hash_id ) +{ + ctx->padding = padding; + ctx->hash_id = hash_id; +} + +/* + * Get length in bytes of RSA modulus + */ + +size_t mbedtls_rsa_get_len( const mbedtls_rsa_context *ctx ) +{ + return( ctx->len ); +} + + +#if defined(MBEDTLS_GENPRIME) + +/* + * Generate an RSA keypair + * + * This generation method follows the RSA key pair generation procedure of + * FIPS 186-4 if 2^16 < exponent < 2^256 and nbits = 2048 or nbits = 3072. + */ +int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + unsigned int nbits, int exponent ) +{ + int ret; + mbedtls_mpi H, G, L; + + if( f_rng == NULL || nbits < 128 || exponent < 3 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( nbits % 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &H ); + mbedtls_mpi_init( &G ); + mbedtls_mpi_init( &L ); + + /* + * find primes P and Q with Q < P so that: + * 1. |P-Q| > 2^( nbits / 2 - 100 ) + * 2. GCD( E, (P-1)*(Q-1) ) == 1 + * 3. E^-1 mod LCM(P-1, Q-1) > 2^( nbits / 2 ) + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &ctx->E, exponent ) ); + + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->P, nbits >> 1, 0, + f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->Q, nbits >> 1, 0, + f_rng, p_rng ) ); + + /* make sure the difference between p and q is not too small (FIPS 186-4 §B.3.3 step 5.4) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &H, &ctx->P, &ctx->Q ) ); + if( mbedtls_mpi_bitlen( &H ) <= ( ( nbits >= 200 ) ? ( ( nbits >> 1 ) - 99 ) : 0 ) ) + continue; + + /* not required by any standards, but some users rely on the fact that P > Q */ + if( H.s < 0 ) + mbedtls_mpi_swap( &ctx->P, &ctx->Q ); + + /* Temporarily replace P,Q by P-1, Q-1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &ctx->P, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &ctx->Q, &ctx->Q, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &H, &ctx->P, &ctx->Q ) ); + + /* check GCD( E, (P-1)*(Q-1) ) == 1 (FIPS 186-4 §B.3.1 criterion 2(a)) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &G, &ctx->E, &H ) ); + if( mbedtls_mpi_cmp_int( &G, 1 ) != 0 ) + continue; + + /* compute smallest possible D = E^-1 mod LCM(P-1, Q-1) (FIPS 186-4 §B.3.1 criterion 3(b)) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &G, &ctx->P, &ctx->Q ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_div_mpi( &L, NULL, &H, &G ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &ctx->D, &ctx->E, &L ) ); + + if( mbedtls_mpi_bitlen( &ctx->D ) <= ( ( nbits + 1 ) / 2 ) ) // (FIPS 186-4 §B.3.1 criterion 3(a)) + continue; + + break; + } + while( 1 ); + + /* Restore P,Q */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &ctx->P, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &ctx->Q, &ctx->Q, 1 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->N, &ctx->P, &ctx->Q ) ); + + ctx->len = mbedtls_mpi_size( &ctx->N ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* + * DP = D mod (P - 1) + * DQ = D mod (Q - 1) + * QP = Q^-1 mod P + */ + MBEDTLS_MPI_CHK( mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ) ); +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Double-check */ + MBEDTLS_MPI_CHK( mbedtls_rsa_check_privkey( ctx ) ); + +cleanup: + + mbedtls_mpi_free( &H ); + mbedtls_mpi_free( &G ); + mbedtls_mpi_free( &L ); + + if( ret != 0 ) + { + mbedtls_rsa_free( ctx ); + return( MBEDTLS_ERR_RSA_KEY_GEN_FAILED + ret ); + } + + return( 0 ); +} + +#endif /* MBEDTLS_GENPRIME */ + +/* + * Check a public RSA key + */ +int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx ) +{ + if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) != 0 ) + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + + if( mbedtls_mpi_bitlen( &ctx->N ) < 128 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_mpi_get_bit( &ctx->E, 0 ) == 0 || + mbedtls_mpi_bitlen( &ctx->E ) < 2 || + mbedtls_mpi_cmp_mpi( &ctx->E, &ctx->N ) >= 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + return( 0 ); +} + +/* + * Check for the consistency of all fields in an RSA private key context + */ +int mbedtls_rsa_check_privkey( const mbedtls_rsa_context *ctx ) +{ + if( mbedtls_rsa_check_pubkey( ctx ) != 0 || + rsa_check_context( ctx, 1 /* private */, 1 /* blinding */ ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_rsa_validate_params( &ctx->N, &ctx->P, &ctx->Q, + &ctx->D, &ctx->E, NULL, NULL ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + else if( mbedtls_rsa_validate_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } +#endif + + return( 0 ); +} + +/* + * Check if contexts holding a public and private key match + */ +int mbedtls_rsa_check_pub_priv( const mbedtls_rsa_context *pub, + const mbedtls_rsa_context *prv ) +{ + if( mbedtls_rsa_check_pubkey( pub ) != 0 || + mbedtls_rsa_check_privkey( prv ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_mpi_cmp_mpi( &pub->N, &prv->N ) != 0 || + mbedtls_mpi_cmp_mpi( &pub->E, &prv->E ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + return( 0 ); +} + +#if !defined(MBEDTLS_RSA_PUBLIC_ALT) +/* + * Do an RSA public key operation + */ +int mbedtls_rsa_public( mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + size_t olen; + mbedtls_mpi T; + + if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T ); + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) + return( ret ); +#endif + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &T, input, ctx->len ) ); + + if( mbedtls_mpi_cmp_mpi( &T, &ctx->N ) >= 0 ) + { + ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + + olen = ctx->len; + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, &ctx->E, &ctx->N, &ctx->RN ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &T, output, olen ) ); + +cleanup: +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 ) + return( MBEDTLS_ERR_THREADING_MUTEX_ERROR ); +#endif + + mbedtls_mpi_free( &T ); + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_PUBLIC_FAILED + ret ); + + return( 0 ); +} + +#endif /* MBEDTLS_RSA_PUBLIC_ALT */ + +/* + * Generate or update blinding values, see section 10 of: + * KOCHER, Paul C. Timing attacks on implementations of Diffie-Hellman, RSA, + * DSS, and other systems. In : Advances in Cryptology-CRYPTO'96. Springer + * Berlin Heidelberg, 1996. p. 104-113. + */ +static int rsa_prepare_blinding( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret, count = 0; + + if( ctx->Vf.p != NULL ) + { + /* We already have blinding values, just update them by squaring */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vi, &ctx->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vf, &ctx->Vf, &ctx->Vf ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vf, &ctx->Vf, &ctx->N ) ); + + goto cleanup; + } + + /* Unblinding value: Vf = random number, invertible mod N */ + do { + if( count++ > 10 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &ctx->Vf, ctx->len - 1, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &ctx->Vi, &ctx->Vf, &ctx->N ) ); + } while( mbedtls_mpi_cmp_int( &ctx->Vi, 1 ) != 0 ); + + /* Blinding value: Vi = Vf^(-e) mod N */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &ctx->Vi, &ctx->Vf, &ctx->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &ctx->Vi, &ctx->Vi, &ctx->E, &ctx->N, &ctx->RN ) ); + + +cleanup: + return( ret ); +} + +/* + * Exponent blinding supposed to prevent side-channel attacks using multiple + * traces of measurements to recover the RSA key. The more collisions are there, + * the more bits of the key can be recovered. See [3]. + * + * Collecting n collisions with m bit long blinding value requires 2^(m-m/n) + * observations on avarage. + * + * For example with 28 byte blinding to achieve 2 collisions the adversary has + * to make 2^112 observations on avarage. + * + * (With the currently (as of 2017 April) known best algorithms breaking 2048 + * bit RSA requires approximately as much time as trying out 2^112 random keys. + * Thus in this sense with 28 byte blinding the security is not reduced by + * side-channel attacks like the one in [3]) + * + * This countermeasure does not help if the key recovery is possible with a + * single trace. + */ +#define RSA_EXPONENT_BLINDING 28 + +/* + * Do an RSA private key operation + */ +int mbedtls_rsa_private( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + size_t olen; + + /* Temporary holding the result */ + mbedtls_mpi T; + + /* Temporaries holding P-1, Q-1 and the + * exponent blinding factor, respectively. */ + mbedtls_mpi P1, Q1, R; + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Temporaries holding the results mod p resp. mod q. */ + mbedtls_mpi TP, TQ; + + /* Temporaries holding the blinded exponents for + * the mod p resp. mod q computation (if used). */ + mbedtls_mpi DP_blind, DQ_blind; + + /* Pointers to actual exponents to be used - either the unblinded + * or the blinded ones, depending on the presence of a PRNG. */ + mbedtls_mpi *DP = &ctx->DP; + mbedtls_mpi *DQ = &ctx->DQ; +#else + /* Temporary holding the blinded exponent (if used). */ + mbedtls_mpi D_blind; + + /* Pointer to actual exponent to be used - either the unblinded + * or the blinded one, depending on the presence of a PRNG. */ + mbedtls_mpi *D = &ctx->D; +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Temporaries holding the initial input and the double + * checked result; should be the same in the end. */ + mbedtls_mpi I, C; + + if( rsa_check_context( ctx, 1 /* private key checks */, + f_rng != NULL /* blinding y/n */ ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) + return( ret ); +#endif + + /* MPI Initialization */ + mbedtls_mpi_init( &T ); + + mbedtls_mpi_init( &P1 ); + mbedtls_mpi_init( &Q1 ); + mbedtls_mpi_init( &R ); + + if( f_rng != NULL ) + { +#if defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_init( &D_blind ); +#else + mbedtls_mpi_init( &DP_blind ); + mbedtls_mpi_init( &DQ_blind ); +#endif + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_init( &TP ); mbedtls_mpi_init( &TQ ); +#endif + + mbedtls_mpi_init( &I ); + mbedtls_mpi_init( &C ); + + /* End of MPI initialization */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &T, input, ctx->len ) ); + if( mbedtls_mpi_cmp_mpi( &T, &ctx->N ) >= 0 ) + { + ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &I, &T ) ); + + if( f_rng != NULL ) + { + /* + * Blinding + * T = T * Vi mod N + */ + MBEDTLS_MPI_CHK( rsa_prepare_blinding( ctx, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &T, &ctx->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &T, &ctx->N ) ); + + /* + * Exponent blinding + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &P1, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &Q1, &ctx->Q, 1 ) ); + +#if defined(MBEDTLS_RSA_NO_CRT) + /* + * D_blind = ( P - 1 ) * ( Q - 1 ) * R + D + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &D_blind, &P1, &Q1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &D_blind, &D_blind, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &D_blind, &D_blind, &ctx->D ) ); + + D = &D_blind; +#else + /* + * DP_blind = ( P - 1 ) * R + DP + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DP_blind, &P1, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &DP_blind, &DP_blind, + &ctx->DP ) ); + + DP = &DP_blind; + + /* + * DQ_blind = ( Q - 1 ) * R + DQ + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DQ_blind, &Q1, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &DQ_blind, &DQ_blind, + &ctx->DQ ) ); + + DQ = &DQ_blind; +#endif /* MBEDTLS_RSA_NO_CRT */ + } + +#if defined(MBEDTLS_RSA_NO_CRT) + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, D, &ctx->N, &ctx->RN ) ); +#else + /* + * Faster decryption using the CRT + * + * TP = input ^ dP mod P + * TQ = input ^ dQ mod Q + */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &TP, &T, DP, &ctx->P, &ctx->RP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &TQ, &T, DQ, &ctx->Q, &ctx->RQ ) ); + + /* + * T = (TP - TQ) * (Q^-1 mod P) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &TP, &TQ ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &TP, &T, &ctx->QP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &TP, &ctx->P ) ); + + /* + * T = TQ + T * Q + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &TP, &T, &ctx->Q ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &T, &TQ, &TP ) ); +#endif /* MBEDTLS_RSA_NO_CRT */ + + if( f_rng != NULL ) + { + /* + * Unblind + * T = T * Vf mod N + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &T, &ctx->Vf ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &T, &ctx->N ) ); + } + + /* Verify the result to prevent glitching attacks. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &C, &T, &ctx->E, + &ctx->N, &ctx->RN ) ); + if( mbedtls_mpi_cmp_mpi( &C, &I ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto cleanup; + } + + olen = ctx->len; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &T, output, olen ) ); + +cleanup: +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 ) + return( MBEDTLS_ERR_THREADING_MUTEX_ERROR ); +#endif + + mbedtls_mpi_free( &P1 ); + mbedtls_mpi_free( &Q1 ); + mbedtls_mpi_free( &R ); + + if( f_rng != NULL ) + { +#if defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &D_blind ); +#else + mbedtls_mpi_free( &DP_blind ); + mbedtls_mpi_free( &DQ_blind ); +#endif + } + + mbedtls_mpi_free( &T ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &TP ); mbedtls_mpi_free( &TQ ); +#endif + + mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &I ); + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_PRIVATE_FAILED + ret ); + + return( 0 ); +} + +#if defined(MBEDTLS_PKCS1_V21) +/** + * Generate and apply the MGF1 operation (from PKCS#1 v2.1) to a buffer. + * + * \param dst buffer to mask + * \param dlen length of destination buffer + * \param src source of the mask generation + * \param slen length of the source buffer + * \param md_ctx message digest context to use + */ +static int mgf_mask( unsigned char *dst, size_t dlen, unsigned char *src, + size_t slen, mbedtls_md_context_t *md_ctx ) +{ + unsigned char mask[MBEDTLS_MD_MAX_SIZE]; + unsigned char counter[4]; + unsigned char *p; + unsigned int hlen; + size_t i, use_len; + int ret = 0; + + memset( mask, 0, MBEDTLS_MD_MAX_SIZE ); + memset( counter, 0, 4 ); + + hlen = mbedtls_md_get_size( md_ctx->md_info ); + + /* Generate and apply dbMask */ + p = dst; + + while( dlen > 0 ) + { + use_len = hlen; + if( dlen < hlen ) + use_len = dlen; + + if( ( ret = mbedtls_md_starts( md_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( md_ctx, src, slen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( md_ctx, counter, 4 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_finish( md_ctx, mask ) ) != 0 ) + goto exit; + + for( i = 0; i < use_len; ++i ) + *p++ ^= mask[i]; + + counter[3]++; + + dlen -= use_len; + } + +exit: + mbedtls_platform_zeroize( mask, sizeof( mask ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSAES-OAEP-ENCRYPT function + */ +int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + size_t olen; + int ret; + unsigned char *p = output; + unsigned int hlen; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( f_rng == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + hlen = mbedtls_md_get_size( md_info ); + + /* first comparison checks for overflow */ + if( ilen + 2 * hlen + 2 < ilen || olen < ilen + 2 * hlen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + memset( output, 0, olen ); + + *p++ = 0; + + /* Generate a random octet string seed */ + if( ( ret = f_rng( p_rng, p, hlen ) ) != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + p += hlen; + + /* Construct DB */ + if( ( ret = mbedtls_md( md_info, label, label_len, p ) ) != 0 ) + return( ret ); + p += hlen; + p += olen - 2 * hlen - 2 - ilen; + *p++ = 1; + memcpy( p, input, ilen ); + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + /* maskedDB: Apply dbMask to DB */ + if( ( ret = mgf_mask( output + hlen + 1, olen - hlen - 1, output + 1, hlen, + &md_ctx ) ) != 0 ) + goto exit; + + /* maskedSeed: Apply seedMask to seed */ + if( ( ret = mgf_mask( output + 1, hlen, output + hlen + 1, olen - hlen - 1, + &md_ctx ) ) != 0 ) + goto exit; + +exit: + mbedtls_md_free( &md_ctx ); + + if( ret != 0 ) + return( ret ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, output, output ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, output, output ) ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSAES-PKCS1-V1_5-ENCRYPT function + */ +int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + size_t nb_pad, olen; + int ret; + unsigned char *p = output; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + // We don't check p_rng because it won't be dereferenced here + if( f_rng == NULL || input == NULL || output == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + + /* first comparison checks for overflow */ + if( ilen + 11 < ilen || olen < ilen + 11 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + nb_pad = olen - 3 - ilen; + + *p++ = 0; + if( mode == MBEDTLS_RSA_PUBLIC ) + { + *p++ = MBEDTLS_RSA_CRYPT; + + while( nb_pad-- > 0 ) + { + int rng_dl = 100; + + do { + ret = f_rng( p_rng, p, 1 ); + } while( *p == 0 && --rng_dl && ret == 0 ); + + /* Check if RNG failed to generate data */ + if( rng_dl == 0 || ret != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + p++; + } + } + else + { + *p++ = MBEDTLS_RSA_SIGN; + + while( nb_pad-- > 0 ) + *p++ = 0xFF; + } + + *p++ = 0; + memcpy( p, input, ilen ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, output, output ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, output, output ) ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Add the message padding, then do an RSA operation + */ +int mbedtls_rsa_pkcs1_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsaes_pkcs1_v15_encrypt( ctx, f_rng, p_rng, mode, ilen, + input, output ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsaes_oaep_encrypt( ctx, f_rng, p_rng, mode, NULL, 0, + ilen, input, output ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSAES-OAEP-DECRYPT function + */ +int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ) +{ + int ret; + size_t ilen, i, pad_len; + unsigned char *p, bad, pad_done; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + unsigned char lhash[MBEDTLS_MD_MAX_SIZE]; + unsigned int hlen; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + + /* + * Parameters sanity checks + */ + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ilen = ctx->len; + + if( ilen < 16 || ilen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + + // checking for integer underflow + if( 2 * hlen + 2 > ilen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * RSA operation + */ + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, input, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, input, buf ); + + if( ret != 0 ) + goto cleanup; + + /* + * Unmask data and generate lHash + */ + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + { + mbedtls_md_free( &md_ctx ); + goto cleanup; + } + + /* seed: Apply seedMask to maskedSeed */ + if( ( ret = mgf_mask( buf + 1, hlen, buf + hlen + 1, ilen - hlen - 1, + &md_ctx ) ) != 0 || + /* DB: Apply dbMask to maskedDB */ + ( ret = mgf_mask( buf + hlen + 1, ilen - hlen - 1, buf + 1, hlen, + &md_ctx ) ) != 0 ) + { + mbedtls_md_free( &md_ctx ); + goto cleanup; + } + + mbedtls_md_free( &md_ctx ); + + /* Generate lHash */ + if( ( ret = mbedtls_md( md_info, label, label_len, lhash ) ) != 0 ) + goto cleanup; + + /* + * Check contents, in "constant-time" + */ + p = buf; + bad = 0; + + bad |= *p++; /* First byte must be 0 */ + + p += hlen; /* Skip seed */ + + /* Check lHash */ + for( i = 0; i < hlen; i++ ) + bad |= lhash[i] ^ *p++; + + /* Get zero-padding len, but always read till end of buffer + * (minus one, for the 01 byte) */ + pad_len = 0; + pad_done = 0; + for( i = 0; i < ilen - 2 * hlen - 2; i++ ) + { + pad_done |= p[i]; + pad_len += ((pad_done | (unsigned char)-pad_done) >> 7) ^ 1; + } + + p += pad_len; + bad |= *p++ ^ 0x01; + + /* + * The only information "leaked" is whether the padding was correct or not + * (eg, no data is copied if it was not correct). This meets the + * recommendations in PKCS#1 v2.2: an opponent cannot distinguish between + * the different error conditions. + */ + if( bad != 0 ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto cleanup; + } + + if( ilen - ( p - buf ) > output_max_len ) + { + ret = MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE; + goto cleanup; + } + + *olen = ilen - (p - buf); + memcpy( output, p, *olen ); + ret = 0; + +cleanup: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + mbedtls_platform_zeroize( lhash, sizeof( lhash ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSAES-PKCS1-V1_5-DECRYPT function + */ +int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len) +{ + int ret; + size_t ilen, pad_count = 0, i; + unsigned char *p, bad, pad_done = 0; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ilen = ctx->len; + + if( ilen < 16 || ilen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, input, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, input, buf ); + + if( ret != 0 ) + goto cleanup; + + p = buf; + bad = 0; + + /* + * Check and get padding len in "constant-time" + */ + bad |= *p++; /* First byte must be 0 */ + + /* This test does not depend on secret data */ + if( mode == MBEDTLS_RSA_PRIVATE ) + { + bad |= *p++ ^ MBEDTLS_RSA_CRYPT; + + /* Get padding len, but always read till end of buffer + * (minus one, for the 00 byte) */ + for( i = 0; i < ilen - 3; i++ ) + { + pad_done |= ((p[i] | (unsigned char)-p[i]) >> 7) ^ 1; + pad_count += ((pad_done | (unsigned char)-pad_done) >> 7) ^ 1; + } + + p += pad_count; + bad |= *p++; /* Must be zero */ + } + else + { + bad |= *p++ ^ MBEDTLS_RSA_SIGN; + + /* Get padding len, but always read till end of buffer + * (minus one, for the 00 byte) */ + for( i = 0; i < ilen - 3; i++ ) + { + pad_done |= ( p[i] != 0xFF ); + pad_count += ( pad_done == 0 ); + } + + p += pad_count; + bad |= *p++; /* Must be zero */ + } + + bad |= ( pad_count < 8 ); + + if( bad ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto cleanup; + } + + if( ilen - ( p - buf ) > output_max_len ) + { + ret = MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE; + goto cleanup; + } + + *olen = ilen - (p - buf); + memcpy( output, p, *olen ); + ret = 0; + +cleanup: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation, then remove the message padding + */ +int mbedtls_rsa_pkcs1_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len) +{ + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsaes_pkcs1_v15_decrypt( ctx, f_rng, p_rng, mode, olen, + input, output, output_max_len ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsaes_oaep_decrypt( ctx, f_rng, p_rng, mode, NULL, 0, + olen, input, output, + output_max_len ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PSS-SIGN function + */ +int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + size_t olen; + unsigned char *p = sig; + unsigned char salt[MBEDTLS_MD_MAX_SIZE]; + unsigned int slen, hlen, offset = 0; + int ret; + size_t msb; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( f_rng == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + + if( md_alg != MBEDTLS_MD_NONE ) + { + /* Gather length of hash to sign */ + md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + } + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + slen = hlen; + + if( olen < hlen + slen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + memset( sig, 0, olen ); + + /* Generate salt of length slen */ + if( ( ret = f_rng( p_rng, salt, slen ) ) != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + /* Note: EMSA-PSS encoding is over the length of N - 1 bits */ + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + p += olen - hlen * 2 - 2; + *p++ = 0x01; + memcpy( p, salt, slen ); + p += slen; + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + /* Generate H = Hash( M' ) */ + if( ( ret = mbedtls_md_starts( &md_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, p, 8 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, hash, hashlen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, salt, slen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_finish( &md_ctx, p ) ) != 0 ) + goto exit; + + /* Compensate for boundary condition when applying mask */ + if( msb % 8 == 0 ) + offset = 1; + + /* maskedDB: Apply dbMask to DB */ + if( ( ret = mgf_mask( sig + offset, olen - hlen - 1 - offset, p, hlen, + &md_ctx ) ) != 0 ) + goto exit; + + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + sig[0] &= 0xFF >> ( olen * 8 - msb ); + + p += hlen; + *p++ = 0xBC; + + mbedtls_platform_zeroize( salt, sizeof( salt ) ); + +exit: + mbedtls_md_free( &md_ctx ); + + if( ret != 0 ) + return( ret ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, sig ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, sig ) ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PKCS1-V1_5-SIGN function + */ + +/* Construct a PKCS v1.5 encoding of a hashed message + * + * This is used both for signature generation and verification. + * + * Parameters: + * - md_alg: Identifies the hash algorithm used to generate the given hash; + * MBEDTLS_MD_NONE if raw data is signed. + * - hashlen: Length of hash in case hashlen is MBEDTLS_MD_NONE. + * - hash: Buffer containing the hashed message or the raw data. + * - dst_len: Length of the encoded message. + * - dst: Buffer to hold the encoded message. + * + * Assumptions: + * - hash has size hashlen if md_alg == MBEDTLS_MD_NONE. + * - hash has size corresponding to md_alg if md_alg != MBEDTLS_MD_NONE. + * - dst points to a buffer of size at least dst_len. + * + */ +static int rsa_rsassa_pkcs1_v15_encode( mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + size_t dst_len, + unsigned char *dst ) +{ + size_t oid_size = 0; + size_t nb_pad = dst_len; + unsigned char *p = dst; + const char *oid = NULL; + + /* Are we signing hashed or raw data? */ + if( md_alg != MBEDTLS_MD_NONE ) + { + const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( mbedtls_oid_get_oid_by_md( md_alg, &oid, &oid_size ) != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + + /* Double-check that 8 + hashlen + oid_size can be used as a + * 1-byte ASN.1 length encoding and that there's no overflow. */ + if( 8 + hashlen + oid_size >= 0x80 || + 10 + hashlen < hashlen || + 10 + hashlen + oid_size < 10 + hashlen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Static bounds check: + * - Need 10 bytes for five tag-length pairs. + * (Insist on 1-byte length encodings to protect against variants of + * Bleichenbacher's forgery attack against lax PKCS#1v1.5 verification) + * - Need hashlen bytes for hash + * - Need oid_size bytes for hash alg OID. + */ + if( nb_pad < 10 + hashlen + oid_size ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + nb_pad -= 10 + hashlen + oid_size; + } + else + { + if( nb_pad < hashlen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + nb_pad -= hashlen; + } + + /* Need space for signature header and padding delimiter (3 bytes), + * and 8 bytes for the minimal padding */ + if( nb_pad < 3 + 8 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + nb_pad -= 3; + + /* Now nb_pad is the amount of memory to be filled + * with padding, and at least 8 bytes long. */ + + /* Write signature header and padding */ + *p++ = 0; + *p++ = MBEDTLS_RSA_SIGN; + memset( p, 0xFF, nb_pad ); + p += nb_pad; + *p++ = 0; + + /* Are we signing raw data? */ + if( md_alg == MBEDTLS_MD_NONE ) + { + memcpy( p, hash, hashlen ); + return( 0 ); + } + + /* Signing hashed data, add corresponding ASN.1 structure + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm DigestAlgorithmIdentifier, + * digest Digest } + * DigestAlgorithmIdentifier ::= AlgorithmIdentifier + * Digest ::= OCTET STRING + * + * Schematic: + * TAG-SEQ + LEN [ TAG-SEQ + LEN [ TAG-OID + LEN [ OID ] + * TAG-NULL + LEN [ NULL ] ] + * TAG-OCTET + LEN [ HASH ] ] + */ + *p++ = MBEDTLS_ASN1_SEQUENCE | MBEDTLS_ASN1_CONSTRUCTED; + *p++ = (unsigned char)( 0x08 + oid_size + hashlen ); + *p++ = MBEDTLS_ASN1_SEQUENCE | MBEDTLS_ASN1_CONSTRUCTED; + *p++ = (unsigned char)( 0x04 + oid_size ); + *p++ = MBEDTLS_ASN1_OID; + *p++ = (unsigned char) oid_size; + memcpy( p, oid, oid_size ); + p += oid_size; + *p++ = MBEDTLS_ASN1_NULL; + *p++ = 0x00; + *p++ = MBEDTLS_ASN1_OCTET_STRING; + *p++ = (unsigned char) hashlen; + memcpy( p, hash, hashlen ); + p += hashlen; + + /* Just a sanity-check, should be automatic + * after the initial bounds check. */ + if( p != dst + dst_len ) + { + mbedtls_platform_zeroize( dst, dst_len ); + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + + return( 0 ); +} + +/* + * Do an RSA operation to sign the message digest + */ +int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + int ret; + unsigned char *sig_try = NULL, *verif = NULL; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Prepare PKCS1-v1.5 encoding (padding and hash identifier) + */ + + if( ( ret = rsa_rsassa_pkcs1_v15_encode( md_alg, hashlen, hash, + ctx->len, sig ) ) != 0 ) + return( ret ); + + /* + * Call respective RSA primitive + */ + + if( mode == MBEDTLS_RSA_PUBLIC ) + { + /* Skip verification on a public key operation */ + return( mbedtls_rsa_public( ctx, sig, sig ) ); + } + + /* Private key operation + * + * In order to prevent Lenstra's attack, make the signature in a + * temporary buffer and check it before returning it. + */ + + sig_try = mbedtls_calloc( 1, ctx->len ); + if( sig_try == NULL ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + verif = mbedtls_calloc( 1, ctx->len ); + if( verif == NULL ) + { + mbedtls_free( sig_try ); + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + } + + MBEDTLS_MPI_CHK( mbedtls_rsa_private( ctx, f_rng, p_rng, sig, sig_try ) ); + MBEDTLS_MPI_CHK( mbedtls_rsa_public( ctx, sig_try, verif ) ); + + if( mbedtls_safer_memcmp( verif, sig, ctx->len ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_PRIVATE_FAILED; + goto cleanup; + } + + memcpy( sig, sig_try, ctx->len ); + +cleanup: + mbedtls_free( sig_try ); + mbedtls_free( verif ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation to sign the message digest + */ +int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsassa_pkcs1_v15_sign( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsassa_pss_sign( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PSS-VERIFY function + */ +int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + mbedtls_md_type_t mgf1_hash_id, + int expected_salt_len, + const unsigned char *sig ) +{ + int ret; + size_t siglen; + unsigned char *p; + unsigned char *hash_start; + unsigned char result[MBEDTLS_MD_MAX_SIZE]; + unsigned char zeros[8]; + unsigned int hlen; + size_t observed_salt_len, msb; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + siglen = ctx->len; + + if( siglen < 16 || siglen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, buf ); + + if( ret != 0 ) + return( ret ); + + p = buf; + + if( buf[siglen - 1] != 0xBC ) + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + + if( md_alg != MBEDTLS_MD_NONE ) + { + /* Gather length of hash to sign */ + md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + } + + md_info = mbedtls_md_info_from_type( mgf1_hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + + memset( zeros, 0, 8 ); + + /* + * Note: EMSA-PSS verification is over the length of N - 1 bits + */ + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + + if( buf[0] >> ( 8 - siglen * 8 + msb ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* Compensate for boundary condition when applying mask */ + if( msb % 8 == 0 ) + { + p++; + siglen -= 1; + } + + if( siglen < hlen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + hash_start = p + siglen - hlen - 1; + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + ret = mgf_mask( p, siglen - hlen - 1, hash_start, hlen, &md_ctx ); + if( ret != 0 ) + goto exit; + + buf[0] &= 0xFF >> ( siglen * 8 - msb ); + + while( p < hash_start - 1 && *p == 0 ) + p++; + + if( *p++ != 0x01 ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto exit; + } + + observed_salt_len = hash_start - p; + + if( expected_salt_len != MBEDTLS_RSA_SALT_LEN_ANY && + observed_salt_len != (size_t) expected_salt_len ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto exit; + } + + /* + * Generate H = Hash( M' ) + */ + ret = mbedtls_md_starts( &md_ctx ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, zeros, 8 ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, hash, hashlen ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, p, observed_salt_len ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_finish( &md_ctx, result ); + if ( ret != 0 ) + goto exit; + + if( memcmp( hash_start, result, hlen ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto exit; + } + +exit: + mbedtls_md_free( &md_ctx ); + + return( ret ); +} + +/* + * Simplified PKCS#1 v2.1 RSASSA-PSS-VERIFY function + */ +int mbedtls_rsa_rsassa_pss_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + mbedtls_md_type_t mgf1_hash_id = ( ctx->hash_id != MBEDTLS_MD_NONE ) + ? (mbedtls_md_type_t) ctx->hash_id + : md_alg; + + return( mbedtls_rsa_rsassa_pss_verify_ext( ctx, f_rng, p_rng, mode, + md_alg, hashlen, hash, + mgf1_hash_id, MBEDTLS_RSA_SALT_LEN_ANY, + sig ) ); + +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PKCS1-v1_5-VERIFY function + */ +int mbedtls_rsa_rsassa_pkcs1_v15_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + int ret = 0; + const size_t sig_len = ctx->len; + unsigned char *encoded = NULL, *encoded_expected = NULL; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Prepare expected PKCS1 v1.5 encoding of hash. + */ + + if( ( encoded = mbedtls_calloc( 1, sig_len ) ) == NULL || + ( encoded_expected = mbedtls_calloc( 1, sig_len ) ) == NULL ) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + goto cleanup; + } + + if( ( ret = rsa_rsassa_pkcs1_v15_encode( md_alg, hashlen, hash, sig_len, + encoded_expected ) ) != 0 ) + goto cleanup; + + /* + * Apply RSA primitive to get what should be PKCS1 encoded hash. + */ + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, encoded ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, encoded ); + if( ret != 0 ) + goto cleanup; + + /* + * Compare + */ + + if( ( ret = mbedtls_safer_memcmp( encoded, encoded_expected, + sig_len ) ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto cleanup; + } + +cleanup: + + if( encoded != NULL ) + { + mbedtls_platform_zeroize( encoded, sig_len ); + mbedtls_free( encoded ); + } + + if( encoded_expected != NULL ) + { + mbedtls_platform_zeroize( encoded_expected, sig_len ); + mbedtls_free( encoded_expected ); + } + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation and check the message digest + */ +int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsassa_pkcs1_v15_verify( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsassa_pss_verify( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +/* + * Copy the components of an RSA key + */ +int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src ) +{ + int ret; + + dst->ver = src->ver; + dst->len = src->len; + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->N, &src->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->E, &src->E ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->D, &src->D ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->P, &src->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Q, &src->Q ) ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->DP, &src->DP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->DQ, &src->DQ ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->QP, &src->QP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RP, &src->RP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RQ, &src->RQ ) ); +#endif + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RN, &src->RN ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Vi, &src->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Vf, &src->Vf ) ); + + dst->padding = src->padding; + dst->hash_id = src->hash_id; + +cleanup: + if( ret != 0 ) + mbedtls_rsa_free( dst ); + + return( ret ); +} + +/* + * Free the components of an RSA key + */ +void mbedtls_rsa_free( mbedtls_rsa_context *ctx ) +{ + mbedtls_mpi_free( &ctx->Vi ); mbedtls_mpi_free( &ctx->Vf ); + mbedtls_mpi_free( &ctx->RN ); mbedtls_mpi_free( &ctx->D ); + mbedtls_mpi_free( &ctx->Q ); mbedtls_mpi_free( &ctx->P ); + mbedtls_mpi_free( &ctx->E ); mbedtls_mpi_free( &ctx->N ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &ctx->RQ ); mbedtls_mpi_free( &ctx->RP ); + mbedtls_mpi_free( &ctx->QP ); mbedtls_mpi_free( &ctx->DQ ); + mbedtls_mpi_free( &ctx->DP ); +#endif /* MBEDTLS_RSA_NO_CRT */ + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_free( &ctx->mutex ); +#endif +} + +#endif /* !MBEDTLS_RSA_ALT */ + +#if defined(MBEDTLS_SELF_TEST) + +#include "mbedtls/sha1.h" +#if 0 +/* + * Example RSA-1024 keypair, for test purposes + */ +#define KEY_LEN 128 + +#define RSA_N "9292758453063D803DD603D5E777D788" \ + "8ED1D5BF35786190FA2F23EBC0848AEA" \ + "DDA92CA6C3D80B32C4D109BE0F36D6AE" \ + "7130B9CED7ACDF54CFC7555AC14EEBAB" \ + "93A89813FBF3C4F8066D2D800F7C38A8" \ + "1AE31942917403FF4946B0A83D3D3E05" \ + "EE57C6F5F5606FB5D4BC6CD34EE0801A" \ + "5E94BB77B07507233A0BC7BAC8F90F79" + +#define RSA_E "10001" + +#define RSA_D "24BF6185468786FDD303083D25E64EFC" \ + "66CA472BC44D253102F8B4A9D3BFA750" \ + "91386C0077937FE33FA3252D28855837" \ + "AE1B484A8A9A45F7EE8C0C634F99E8CD" \ + "DF79C5CE07EE72C7F123142198164234" \ + "CABB724CF78B8173B9F880FC86322407" \ + "AF1FEDFDDE2BEB674CA15F3E81A1521E" \ + "071513A1E85B5DFA031F21ECAE91A34D" + +#define RSA_P "C36D0EB7FCD285223CFB5AABA5BDA3D8" \ + "2C01CAD19EA484A87EA4377637E75500" \ + "FCB2005C5C7DD6EC4AC023CDA285D796" \ + "C3D9E75E1EFC42488BB4F1D13AC30A57" + +#define RSA_Q "C000DF51A7C77AE8D7C7370C1FF55B69" \ + "E211C2B9E5DB1ED0BF61D0D9899620F4" \ + "910E4168387E3C30AA1E00C339A79508" \ + "8452DD96A9A5EA5D9DCA68DA636032AF" +#endif +#define PT_LEN 24 +#define RSA_PT "\xAA\xBB\xCC\x03\x02\x01\x00\xFF\xFF\xFF\xFF\xFF" \ + "\x11\x22\x33\x0A\x0B\x0C\xCC\xDD\xDD\xDD\xDD\xDD" + +#if defined(MBEDTLS_PKCS1_V15) +static int myrand( void *rng_state, unsigned char *output, size_t len ) +{ +#if !defined(__OpenBSD__) + size_t i; + + if( rng_state != NULL ) + rng_state = NULL; + + for( i = 0; i < len; ++i ) + output[i] = rand(); +#else + if( rng_state != NULL ) + rng_state = NULL; + + arc4random_buf( output, len ); +#endif /* !OpenBSD */ + + return( 0 ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Checkup routine + */ +int mbedtls_rsa_self_test( int verbose ) +{ + int ret = 0; +#if defined(MBEDTLS_PKCS1_V15) + size_t len; + mbedtls_pk_context pk; + mbedtls_rsa_context *rsa; + unsigned char rsa_plaintext[PT_LEN]; + unsigned char rsa_decrypted[PT_LEN]; +#if defined(MBEDTLS_SHA1_C) + unsigned char sha1sum[20]; +#endif +#if defined(FREESCALE_PKHA_LONG_OPERANDS_ENABLE) \ + || (defined(FREESCALE_PKHA_INT_MAX_BYTES) && (FREESCALE_PKHA_INT_MAX_BYTES >= ((4096 / 8) * 2))) + unsigned char rsa_ciphertext[4096 / 8]; + const char *rsa_keys[] = { RSA_PRIVATE_KEY_1024, RSA_PRIVATE_KEY_2048, RSA_PRIVATE_KEY_4096 }; +#elif defined(FREESCALE_PKHA_INT_MAX_BYTES) && (FREESCALE_PKHA_INT_MAX_BYTES >= ((2048 / 8) * 2)) + unsigned char rsa_ciphertext[2048 / 8]; + const char *rsa_keys[] = { RSA_PRIVATE_KEY_1024, RSA_PRIVATE_KEY_2048 }; +#else + unsigned char rsa_ciphertext[1024 / 8]; + const char *rsa_keys[] = { RSA_PRIVATE_KEY_1024 }; +#endif + size_t i; + + for (i = 0; i < sizeof(rsa_keys) / sizeof(rsa_keys[0]); i++) + { + mbedtls_pk_init(&pk); + + if( verbose != 0 ) + mbedtls_printf( " RSA parse key #%d : ", i + 1 ); + + MBEDTLS_MPI_CHK( mbedtls_pk_parse_key(&pk, (const unsigned char *)rsa_keys[i], strlen(rsa_keys[i]) + 1, NULL, 0) ); + + rsa = mbedtls_pk_rsa(pk); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r RSA-%d key validation: ", mbedtls_pk_get_bitlen( &pk ) ); + + MBEDTLS_MPI_CHK( mbedtls_rsa_check_pubkey( rsa ) ); + MBEDTLS_MPI_CHK( mbedtls_rsa_check_privkey( rsa ) ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r PKCS#1 encryption : " ); + + memcpy( rsa_plaintext, RSA_PT, PT_LEN ); + + MBEDTLS_MPI_CHK( mbedtls_rsa_pkcs1_encrypt( rsa, myrand, NULL, MBEDTLS_RSA_PUBLIC, PT_LEN, + rsa_plaintext, rsa_ciphertext ) ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r PKCS#1 decryption : " ); + + MBEDTLS_MPI_CHK( mbedtls_rsa_pkcs1_decrypt( rsa, myrand, NULL, MBEDTLS_RSA_PRIVATE, &len, + rsa_ciphertext, rsa_decrypted, + sizeof(rsa_decrypted) ) ); + + MBEDTLS_MPI_CHK( memcmp( rsa_decrypted, rsa_plaintext, len ) ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r" ); + + #if defined(MBEDTLS_SHA1_C) + if( verbose != 0 ) + mbedtls_printf( " PKCS#1 data sign : " ); + + mbedtls_sha1( rsa_plaintext, PT_LEN, sha1sum ); + + MBEDTLS_MPI_CHK( mbedtls_rsa_pkcs1_sign( rsa, myrand, NULL, MBEDTLS_RSA_PRIVATE, MBEDTLS_MD_SHA1, 0, + sha1sum, rsa_ciphertext ) ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r PKCS#1 sig. verify : " ); + + MBEDTLS_MPI_CHK( mbedtls_rsa_pkcs1_verify( rsa, NULL, NULL, MBEDTLS_RSA_PUBLIC, MBEDTLS_MD_SHA1, 0, + sha1sum, rsa_ciphertext ) ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n\r" ); + #endif /* MBEDTLS_SHA1_C */ + + if( verbose != 0 ) + mbedtls_printf( "\n\r" ); + + cleanup: + mbedtls_pk_free( &pk ); + if( ret != 0 ) + { + if( verbose != 0 ) + mbedtls_printf( "failed\n\r" ); + + return( 1 ); + } + #else /* MBEDTLS_PKCS1_V15 */ + ((void) verbose); + #endif /* MBEDTLS_PKCS1_V15 */ + } + + return( 0 ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_RSA_C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c new file mode 100644 index 00000000000..4196d778b38 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c @@ -0,0 +1,76 @@ +/* + * + * Copyright 2017 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** +* +* @par Description +* This file implements implements platform independent sleep functionality +* @par History +* +*****************************************************************************/ + +#include +#if defined(__gnu_linux__) || defined(__clang__) +#include +#endif +#include +#include "sm_timer.h" + +#if defined(USE_RTOS) && USE_RTOS == 1 +#include "FreeRTOS.h" +#include "task.h" +#endif + +/* initializes the system tick counter + * return 0 on succes, 1 on failure */ +uint32_t sm_initSleep() +{ + return 0; +} + +#if defined(USE_RTOS) && USE_RTOS == 1 +#ifndef MSEC_TO_TICK +#define MSEC_TO_TICK(msec) \ + ((((uint32_t)configTICK_RATE_HZ * (uint32_t)(msec))) / 1000L) +#endif /* MSEC_TO_TICK */ +#endif /* USE_RTOS */ + +/** + * Implement a blocking (for the calling thread) wait for a number of milliseconds. + */ +void sm_sleep(uint32_t msec) +{ +#ifdef __OSX_AVAILABLE + clock_t goal = msec + clock(); + while (goal > clock()); +#elif defined(__gnu_linux__) || defined __clang__ + useconds_t microsec = msec*1000; + usleep(microsec); +#elif defined(USE_RTOS) && USE_RTOS == 1 + vTaskDelay(1 >= pdMS_TO_TICKS(msec) ? 1 : pdMS_TO_TICKS(msec)); +#else + clock_t goal = msec + clock(); + while (goal > clock()); +#endif +} + +/** + * Implement a blocking (for the calling thread) wait for a number of microseconds + */ +void sm_usleep(uint32_t microsec) +{ +#ifdef __OSX_AVAILABLE + // no usleep +#elif defined(_WIN32) + #pragma message ( "No sm_usleep implemented" ) +#elif defined(__gnu_linux__) || defined __clang__ + usleep(microsec); +#elif defined(__OpenBSD__) + #warning "No sm_usleep implemented" +#else + //#warning "No sm_usleep implemented" +#endif +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h new file mode 100644 index 00000000000..0ef2fb0f3e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h @@ -0,0 +1,45 @@ +/* + * + * Copyright 2018-2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _AX_RESET_H +#define _AX_RESET_H + +#include "sm_types.h" + +/* + * Where applicable, Configure the PINs on the Host + * + */ +void axReset_HostConfigure(void); + +/* + * Where applicable, PowerCycle the SE + * + * Pre-Requistie: @ref axReset_Configure has been called + */ +void axReset_ResetPluseDUT(void); + +/* + * Where applicable, put SE in low power/standby mode + * + * Pre-Requistie: @ref axReset_Configure has been called + */ +void axReset_PowerDown(void); + +/* + * Where applicable, put SE in powered/active mode + * + * Pre-Requistie: @ref axReset_Configure has been called + */ +void axReset_PowerUp(void); + +/* + * Where applicable, Unconfigure the PINs on the Host + * + */ +void axReset_HostUnconfigure(void); + +#endif // _AX_RESET_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h new file mode 100644 index 00000000000..dc1b7208602 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h @@ -0,0 +1,160 @@ +/* + * + * Copyright 2017-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * + * I2C API used by SCI2C & T=1 over I2C protocol implementation. + * + * - SCIIC / SCI2C is the protocol used by A71CH / A71CL family of secure elements. + * + * - T=1 over I2C is the protocol used by SE050 family of secure elements. + * + * - T=1 over I2C with GP is the protocol used by other secure elements. + * + * These APIs are to be implemented when porting the Middleware stack to a new + * host platform. + * + * @note Few APIs are only required for the SCI2C protocol and few are only + * needed for T=1 over I2C Protocol. They are marked by the defines + * ``SCI2C`` , ``T1oI2C`` and ``T1oI2C_GP1_0`` + * + * # Convention of the APIs. + * + * + * APIs for which a buffer is input. e.g.:: + * + * i2c_error_t axI2CWrite(unsigned char bus, unsigned char addr, + * unsigned char * pTx, unsigned short txLen); + * + * + * In the above case :samp:`pTx` is a buffer input. It is assumed that + * the lengh as set in :samp:`txLen` is same as that pointed to by + * :samp:`pTx`. This parameter is used as is and any mistake by the + * calling/implemented API will have unpredictable errors. + * + * + * APIs for which a buffer is output. e.g.:: + * + * i2c_error_t axI2CWriteRead(unsigned char bus, + * unsigned char addr, + * unsigned char *pTx, + * unsigned short txLen, + * unsigned char *pRx, + * unsigned short *pRxLen); + * + * + * In the above case :samp:`pRx` is a buffer output and :samp:`pRxLen` + * is both input and output. It is assumed that the lengh as set in + * :samp:`pRxLen` is set to the maximum as available to the pointer + * pointed by :samp:`pRx`. This parameter is used as is and any mistake + * by the calling/implemented API will have unpredictable errors. + * + * @par History + * + **/ + +#ifndef _I2C_A7_H +#define _I2C_A7_H + +#include "sm_types.h" + +#define SCI2C_T_CMDG 180 //!< Minimum delay between stop of Wakeup command and start of subsequent command (Value in micro seconds) + +#define I2C_IDLE 0 +#define I2C_STARTED 1 +#define I2C_RESTARTED 2 +#define I2C_REPEATED_START 3 +#define DATA_ACK 4 +#define DATA_NACK 5 +#define I2C_BUSY 6 +#define I2C_NO_DATA 7 +#define I2C_NACK_ON_ADDRESS 8 +#define I2C_NACK_ON_DATA 9 +#define I2C_ARBITRATION_LOST 10 +#define I2C_TIME_OUT 11 +#define I2C_OK 12 +#define I2C_FAILED 13 + +typedef unsigned int i2c_error_t; +#define I2C_BUS_0 (0) + +#if defined(__cplusplus) +extern "C"{ +#endif +/** Initialize the I2C platform HW/Driver*/ + +/* MAX data supported by respective protocol in single read/write*/ +#if defined(SCI2C) +#define MAX_DATA_LEN 270 +#elif defined(T1oI2C) +#define MAX_DATA_LEN 260 +#endif + + +i2c_error_t axI2CInit(void **conn_ctx, const char *pDevName); + +/** Terminate / de-initialize the I2C platform HW/Driver + * + * + * @param[in] connection context. + * @param[in] mode Can be either 0 or 1. + * + * Where applicable, and implemented a value of 0 corresponds + * to a 'light-weight' terminate. + * + * In genral, this is not used for most of the porting + * platforms and use cases. + * + * + */ +void axI2CTerm(void* conn_ctx, int mode); + +#if AX_EMBEDDED +/** Smarter handling of back off logic + * + * When we get a NAK from SE, we back off and keep on increasing the delay for next I2C Read/Write. + * + * When we get an ACK from SE, we reset this back off delay. + */ +void axI2CResetBackoffDelay( void ); +#endif /* FREEDOM */ + +#if defined(SCI2C) /* Means SCI2C SCIIC */ +/** Write a byte. + * + * Needed only for SCI2C */ +i2c_error_t axI2CWriteByte(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx); +/** Write and read only after an ACK. + * + * Needed only for SCI2C */ +i2c_error_t axI2CWriteRead(void* conn_ctx, + unsigned char bus, + unsigned char addr, + unsigned char *pTx, + unsigned short txLen, + unsigned char *pRx, + unsigned short *pRxLen); +#endif + +#if defined(SCI2C) /* Means SCI2C SCIIC */ || defined(T1oI2C) +/** Write a frame. + * + * Needed for SCI2C and T=1 over I2C */ +i2c_error_t axI2CWrite(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, unsigned short txLen); +#endif + +#ifdef T1oI2C +/** Read a byte. + * + * Needed only for T=1 over I2C */ +i2c_error_t axI2CRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pRx, unsigned short rxLen); +#endif /* T1oI2C */ +#if defined(__cplusplus) +} +#endif + +#endif // _I2C_A7_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h new file mode 100644 index 00000000000..8db632e6750 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h @@ -0,0 +1,18 @@ +/* + * + * Copyright 2018-2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SE05X_API_H +#define _SE05X_API_H + +/* + * Define Reset logic for reset pin on SE + * Active high for SE050 + */ +#define SE_RESET_LOGIC 1 + +void se05x_ic_reset(void); + +#endif // _SE05X_API_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h new file mode 100644 index 00000000000..eabfb652a71 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h @@ -0,0 +1,40 @@ +/* + * + * Copyright 2016-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SM_PRINTF_H_ +#define _SM_PRINTF_H_ +#include +#include +#include "sm_types.h" +#ifdef __cplusplus +extern "C" { +#endif + + +#if AX_EMBEDDED \ + && (!defined (__MBED__)) +# include "fsl_debug_console.h" +#else +# define PRINTF printf +# define SCANF scanf +# define PUTCHAR putchar +# define GETCHAR getchar +#endif + +#define CONSOLE (0x01) +#define MEMORY (0x02) +#define LOGFILE (0x04) +#define DBGOUT_ALL (CONSOLE|MEMORY|LOGFILE) + +#define DBGOUT CONSOLE + +void sm_printf(unsigned char dev, const char * format, ...); +void AssertZeroAllocation(void); + +#ifdef __cplusplus +} +#endif +#endif // _SM_PRINTF_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h new file mode 100644 index 00000000000..72c35126454 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h @@ -0,0 +1,31 @@ +/* + * + * Copyright 2016 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SM_TIMER_H_ +#define _SM_TIMER_H_ + +#include +#ifdef __gnu_linux__ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Change this value to tick rate used by the controller */ +#define TICK_RATE_HZ 1000 +#define MS_TO_TICKS(msec) (( (msec) * (TICK_RATE_HZ) ) / (1000)) + +/* function used for delay loops */ +uint32_t sm_initSleep(void); +void sm_sleep(uint32_t msec); +void sm_usleep(uint32_t microsec); + +#ifdef __cplusplus +} +#endif +#endif // _SM_TIMER_H_ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c new file mode 100644 index 00000000000..f28cf17e39d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c @@ -0,0 +1,385 @@ +/* + * + * Copyright 2017-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * MCIMX6UL-EVK / MCIMX8M-EVK board specific & Generic i2c code + * @par History + * + **/ +#include "i2c_a7.h" +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// #define NX_LOG_ENABLE_SMCOM_DEBUG 1 + +#include "nxLog_smCom.h" + +static char* default_axSmDevice_name = "/dev/i2c-1"; +static int default_axSmDevice_addr = 0x48; // 7-bit address + +#define DEV_NAME_BUFFER_SIZE 64 + +/** +* Opens the communication channel to I2C device +*/ +i2c_error_t axI2CInit(void **conn_ctx, const char *pDevName) +{ + unsigned long funcs; + int axSmDevice = 0; + char *pdev_name = NULL; + char *pdev_addr_str = NULL; + U32 dev_addr = 0x00; + char temp[DEV_NAME_BUFFER_SIZE] = { 0, }; + + if (pDevName != NULL && (strcasecmp("none", pDevName) != 0) ) { + if ((strlen(pDevName) + 1) < DEV_NAME_BUFFER_SIZE) { + memcpy(temp, pDevName, strlen(pDevName)); + temp[strlen(pDevName)] = '\0'; + } + else { + LOG_E("Connection string passed as argument is too long (%d).", strlen(pDevName)); + LOG_I("Pass i2c device address in the format :."); + LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); + } + + pdev_name = strtok(temp, ":"); + if (pdev_name == NULL) { + perror("Invalid connection string"); + LOG_I("Pass i2c device address in the format :."); + LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); + return I2C_FAILED; + } + + pdev_addr_str = strtok(NULL, ":"); + if (pdev_addr_str != NULL) { + dev_addr = strtol(pdev_addr_str, NULL, 0); + } + else { + dev_addr = default_axSmDevice_addr; + } + } + else { + pdev_name = default_axSmDevice_name; + dev_addr = default_axSmDevice_addr; + } + + LOG_D("I2CInit: opening %s\n", pdev_name); + + if ((axSmDevice = open(pdev_name, O_RDWR)) < 0) + { + LOG_E("opening failed..."); + perror("Failed to open the i2c bus"); + LOG_I("Pass i2c device address in the format :."); + LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); + return I2C_FAILED; + } + + if (ioctl(axSmDevice, I2C_SLAVE, dev_addr) < 0) + { + LOG_E("I2C driver failed setting address\n"); + } + + // clear PEC flag + if (ioctl(axSmDevice, I2C_PEC, 0) < 0) + { + LOG_E("I2C driver: PEC flag clear failed\n"); + } + else + { + LOG_D("I2C driver: PEC flag cleared\n"); + } + + // Query functional capacity of I2C driver + if (ioctl(axSmDevice, I2C_FUNCS, &funcs) < 0) + { + LOG_E("Cannot get i2c adapter functionality\n"); + close(axSmDevice); + return I2C_FAILED; + } + else + { + if (funcs & I2C_FUNC_I2C) + { + LOG_D("I2C driver supports plain i2c-level commands.\n"); +#if defined(SCI2C) //if SCI2C is enabled + if ( (funcs & I2C_FUNC_SMBUS_READ_BLOCK_DATA) == I2C_FUNC_SMBUS_READ_BLOCK_DATA ) + { + LOG_D("I2C driver supports Read Block.\n"); + } + else + { + LOG_E("I2C driver does not support Read Block!\n"); + close(axSmDevice); + return I2C_FAILED; + } +#endif + } + else + { + LOG_E("I2C driver CANNOT support plain i2c-level commands!\n"); + close(axSmDevice); + return I2C_FAILED; + } + } + + *conn_ctx = malloc(sizeof(int)); + *(int*)(*conn_ctx) = axSmDevice; + return I2C_OK; +} + +/** +* Closes the communication channel to I2C device +*/ +void axI2CTerm(void* conn_ctx, int mode) +{ + AX_UNUSED_ARG(mode); + // printf("axI2CTerm (enter) i2c device = %d\n", *(int*)(conn_ctx)); + if (conn_ctx != NULL) { + if (close(*(int*)(conn_ctx)) != 0) { + LOG_E("Failed to close i2c device %d.\n", *(int*)(conn_ctx)); + } + else { + LOG_D("Close i2c device %d.\n", *(int*)(conn_ctx)); + } + free(conn_ctx); + } + // printf("axI2CTerm (exit)\n"); + return; +} + +#if defined(SCI2C) +/** + * Write a single byte to the slave device. + * In the context of the SCI2C protocol, this command is only invoked + * to trigger a wake-up of the attached secure module. As such this + * wakeup command 'wakes' the device, but does not receive a valid response. + * \note \par bus is currently not used to distinguish between I2C masters. +*/ +i2c_error_t axI2CWriteByte(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx) +{ + int nrWritten = -1; + i2c_error_t rv; + int axSmDevice = *(int*)conn_ctx; + + if (bus != I2C_BUS_0) + { + LOG_E("axI2CWriteByte on wrong bus %x (addr %x)\n", bus, addr); + } + + nrWritten = write(axSmDevice, pTx, 1); + if (nrWritten < 0) + { + // I2C_LOG_PRINTF("Failed writing data (nrWritten=%d).\n", nrWritten); + rv = I2C_FAILED; + } + else + { + if (nrWritten == 1) + { + rv = I2C_OK; + } + else + { + rv = I2C_FAILED; + } + } + + return rv; +} +#endif // defined(SCI2C) + +#if defined(SCI2C) || defined(T1oI2C) +i2c_error_t axI2CWrite(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, unsigned short txLen) +{ + int nrWritten = -1; + i2c_error_t rv; + int axSmDevice = *(int*)conn_ctx; +#ifdef LOG_I2C + int i = 0; +#endif + + if(pTx == NULL || txLen > MAX_DATA_LEN) + { + return I2C_FAILED; + } + + if (bus != I2C_BUS_0) + { + LOG_E("axI2CWrite on wrong bus %x (addr %x)\n", bus, addr); + } + LOG_MAU8_D("TX (axI2CWrite) > ",pTx,txLen); + nrWritten = write(axSmDevice, pTx, txLen); + if (nrWritten < 0) + { + LOG_E("Failed writing data (nrWritten=%d).\n", nrWritten); + rv = I2C_FAILED; + } + else + { + if (nrWritten == txLen) // okay + { + rv = I2C_OK; + } + else + { + rv = I2C_FAILED; + } + } + LOG_D("Done with rv = %02x ", rv); + + return rv; +} +#endif // defined(SCI2C) || defined(T1oI2C) + +#if defined(SCI2C) +i2c_error_t axI2CWriteRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, + unsigned short txLen, unsigned char * pRx, unsigned short * pRxLen) +{ + struct i2c_rdwr_ioctl_data packets; + struct i2c_msg messages[2]; + int r = 0; + int i = 0; + int axSmDevice = *(int*)conn_ctx; + + if(pTx == NULL || txLen > MAX_DATA_LEN) + { + return I2C_FAILED; + } + + if(pRx == NULL || *pRxLen > MAX_DATA_LEN) + { + return I2C_FAILED; + } + + if (bus != I2C_BUS_0) // change if bus 0 is not the correct bus + { + LOG_E("axI2CWriteRead on wrong bus %x (addr %x)\n", bus, addr); + } + + messages[0].addr = default_axSmDevice_addr; + messages[0].flags = 0; + messages[0].len = txLen; + messages[0].buf = pTx; + + // NOTE: + // By setting the 'I2C_M_RECV_LEN' bit in 'messages[1].flags' one ensures + // the I2C Block Read feature is used. + messages[1].addr = default_axSmDevice_addr; + messages[1].flags = I2C_M_RD | I2C_M_RECV_LEN; + messages[1].len = 256; + messages[1].buf = pRx; + messages[1].buf[0] = 1; + + // NOTE: + // By passing the two message structures via the packets structure as + // a parameter to the ioctl call one ensures a Repeated Start is triggered. + packets.msgs = messages; + packets.nmsgs = 2; + + LOG_MAU8_D("TX (axI2CWriteRead ) > ",&packets.msgs[0].buf[i], txLen); + + // Send the request to the kernel and get the result back + r = ioctl(axSmDevice, I2C_RDWR, &packets); + + // NOTE: + // The ioctl return value in case of a NACK on the write address is '-1' + // This impacts the error handling routine of the caller. + // If possible distinguish between a general I2C error and a NACK on address + // The way to do this is platform specific (depends on I2C bus driver). + if (r < 0) + { + // LOG_E("axI2CWriteRead: ioctl cmd I2C_RDWR fails with value %d (errno: 0x%08X)\n", r, errno); + // perror("Errorstring: "); +#ifdef PLATFORM_IMX + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0) + #define E_NACK_I2C_IMX ENXIO + // #warning "ENXIO" + #else + #define E_NACK_I2C_IMX EIO + // #warning "EIO" + #endif // LINUX_VERSION_CODE + // In case of IMX, errno == E_NACK_I2C_IMX is not exclusively bound to NACK on address, + // it can also signal a NACK on a data byte + if (errno == E_NACK_I2C_IMX) { + // I2C_LOG_PRINTF("axI2CWriteRead: ioctl signal NACK (errno = %d)\n", errno); + return I2C_NACK_ON_ADDRESS; + } + else { + // printf("axI2CWriteRead: ioctl error (errno = %d)\n", errno); + return I2C_FAILED; + } +#else + // I2C_LOG_PRINTF("axI2CWriteRead: ioctl cmd I2C_RDWR fails with value %d (errno: 0x%08X)\n", r, errno); + return I2C_FAILED; +#endif // PLATFORM_IMX + } + else + { + int rlen = packets.msgs[1].buf[0]+1; + + //I2C_LOG_PRINTF("packets.msgs[1].len is %d \n", packets.msgs[1].len); + LOG_MAU8_D("RX (axI2CWriteRead) < ",&packets.msgs[1].buf[i], rlen); + for (i = 0; i < rlen; i++) + { + pRx[i] = packets.msgs[1].buf[i]; + } + *pRxLen = rlen; + } + + return I2C_OK; +} +#endif // defined(SCI2C) + +#ifdef T1oI2C +i2c_error_t axI2CRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pRx, unsigned short rxLen) +{ + int nrRead = -1; + i2c_error_t rv; + int axSmDevice = *(int*)conn_ctx; + + if(pRx == NULL || rxLen > MAX_DATA_LEN) + { + return I2C_FAILED; + } + + if (bus != I2C_BUS_0) + { + LOG_E("axI2CRead on wrong bus %x (addr %x)\n", bus, addr); + } + + nrRead = read(axSmDevice, pRx, rxLen); + if (nrRead < 0) + { + //LOG_E("Failed Read data (nrRead=%d).\n", nrRead); + rv = I2C_FAILED; + } + else + { + if (nrRead == rxLen) // okay + { + rv = I2C_OK; + } + else + { + rv = I2C_FAILED; + } + } + LOG_D("Done with rv = %02x ", rv); + LOG_MAU8_D("TX (axI2CRead): ",pRx,rxLen); + return rv; +} +#endif // T1oI2C diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c new file mode 100644 index 00000000000..6d5fc8015d3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c @@ -0,0 +1,155 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "sm_timer.h" +#include "ax_reset.h" +#include "se05x_apis.h" + +#define EN_PIN 22 + +void axReset_HostConfigure() +{ + int fd; + char buf[50]; + /* Open export file to export GPIO */ + fd = open("/sys/class/gpio/export", O_WRONLY); + if (fd < 0) { + perror("Failed to open GPIO export file "); + return; + } + /* Export GPIO pin to toggle */ + snprintf(buf, sizeof(buf), "%d", EN_PIN); + if (write(fd, buf, strlen(buf)) < 1) { + perror("Failed to export Enable pin "); + goto exit; + } + close(fd); + + /* Open direction file to configure GPIO direction */ + snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/direction", EN_PIN); + fd = open(buf, O_WRONLY); + if (fd < 0) { + sm_usleep(1000 * 1000); + fd = open(buf, O_WRONLY); + if (fd < 0) { + axReset_HostUnconfigure(); + perror("Failed to open GPIO direction file "); + return; + } + } + /* Configure direction of exported GPIO */ + if (write(fd, "out", 3) < 1) { + perror("Failed to Configure Enable pin "); + axReset_HostUnconfigure(); + goto exit; + } + +exit: + close(fd); + return; +} + +void axReset_HostUnconfigure() +{ + int fd; + char buf[50]; + fd = open("/sys/class/gpio/unexport", O_WRONLY); + if (fd < 0) { + perror("Failed to open unexport file "); + return; + } + + snprintf(buf, sizeof(buf), "%d", EN_PIN); + if (write(fd, buf, strlen(buf)) < 1) { + perror("Failed to unexport GPIO "); + } + + close(fd); + return; +} + +/* + * Where applicable, PowerCycle the SE + * + * Pre-Requisite: @ref axReset_Configure has been called + */ +void axReset_ResetPluseDUT() +{ + axReset_PowerDown(); + sm_usleep(2000); + axReset_PowerUp(); + return; +} + +/* + * Where applicable, put SE in low power/standby mode + * + * Pre-Requisite: @ref axReset_Configure has been called + */ +void axReset_PowerDown() +{ + int fd; + char buf[50]; + char logic[10]; + snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/value", EN_PIN); + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("Failed to open GPIO value file "); + axReset_HostUnconfigure(); + return; + } + + snprintf(logic, sizeof(logic), "%d", !SE_RESET_LOGIC); + if (write(fd, logic, 1) < 1) { + perror("Failed to toggle GPIO high "); + axReset_HostUnconfigure(); + } + + close(fd); +} + +/* + * Where applicable, put SE in powered/active mode + * + * Pre-Requisite: @ref axReset_Configure has been called + */ +void axReset_PowerUp() +{ + int fd; + char buf[50]; + char logic[10]; + snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/value", EN_PIN); + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("Failed to open GPIO value file "); + axReset_HostUnconfigure(); + return; + } + + snprintf(logic, sizeof(logic), "%d", SE_RESET_LOGIC); + if (write(fd, logic, 1) < 1) { + perror("Failed to toggle GPIO high "); + axReset_HostUnconfigure(); + } + + close(fd); +} + +#if SSS_HAVE_SE05X || SSS_HAVE_LOOPBACK + +void se05x_ic_reset() +{ + axReset_ResetPluseDUT(); + smComT1oI2C_ComReset(); + sm_usleep(3000); + return; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c new file mode 100644 index 00000000000..2712b353814 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c @@ -0,0 +1,72 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_SE05X && SSSFTR_SE05X_ECC + +#include "se05x_ecc_curves.h" +#include "se05x_APDU.h" + +#include "se05x_ecc_curves_values.h" +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / (sizeof(array[0]))) +#endif + +#define PROCESS_ECC_CURVE(NAME) \ + smStatus_t Se05x_API_CreateCurve_##NAME(Se05xSession_t *pSession, uint32_t obj_id) \ + { \ + smStatus_t status; \ + const uint8_t ecc_prime[] = {EC_PARAM_##NAME##_prime}; \ + const uint8_t ecc_a[] = {EC_PARAM_##NAME##_a}; \ + const uint8_t ecc_b[] = {EC_PARAM_##NAME##_b}; \ + const uint8_t ecc_G[] = {0x04, EC_PARAM_##NAME##_x, EC_PARAM_##NAME##_y}; \ + const uint8_t ecc_ordern[] = {EC_PARAM_##NAME##_order}; \ + \ + status = Se05x_API_CreateECCurve(pSession, (SE05x_ECCurve_t)obj_id); \ + if (status != SM_OK) { \ + return status; \ + } \ + \ + status = Se05x_API_SetECCurveParam( \ + pSession, (SE05x_ECCurve_t)obj_id, kSE05x_ECCurveParam_PARAM_A, ecc_a, ARRAY_SIZE(ecc_a)); \ + if (status != SM_OK) { \ + return status; \ + } \ + \ + status = Se05x_API_SetECCurveParam( \ + pSession, (SE05x_ECCurve_t)obj_id, kSE05x_ECCurveParam_PARAM_B, ecc_b, ARRAY_SIZE(ecc_b)); \ + if (status != SM_OK) { \ + return status; \ + } \ + \ + status = Se05x_API_SetECCurveParam( \ + pSession, (SE05x_ECCurve_t)obj_id, kSE05x_ECCurveParam_PARAM_G, ecc_G, ARRAY_SIZE(ecc_G)); \ + if (status != SM_OK) { \ + return status; \ + } \ + \ + status = Se05x_API_SetECCurveParam( \ + pSession, (SE05x_ECCurve_t)obj_id, kSE05x_ECCurveParam_PARAM_N, ecc_ordern, ARRAY_SIZE(ecc_ordern)); \ + if (status != SM_OK) { \ + return status; \ + } \ + \ + status = Se05x_API_SetECCurveParam( \ + pSession, (SE05x_ECCurve_t)obj_id, kSE05x_ECCurveParam_PARAM_PRIME, ecc_prime, ARRAY_SIZE(ecc_prime)); \ + return status; \ + } + +#include "se05x_ecc_curves_inc.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c new file mode 100644 index 00000000000..f01c86bec0d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c @@ -0,0 +1,106 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +//#include +#include +#include +#include +#include "sm_const.h" +#include "nxEnsure.h" +#include +// For SIMW-656 +// #include "../../sss/ex/inc/ex_sss_objid.h" + +#if APPLET_SE050_VER_MAJOR_MINOR >= 20000u + +smStatus_t Se05x_API_DeleteAll_Iterative(pSe05xSession_t session_ctx) +{ + uint8_t pmore = kSE05x_MoreIndicator_NA; + uint8_t list[1024]; + size_t listlen = sizeof(list); + size_t i; + smStatus_t retStatus = SM_NOT_OK; + uint16_t outputOffset = 0; + do { + retStatus = Se05x_API_ReadIDList(session_ctx, outputOffset, 0xFF, &pmore, list, &listlen); + if (retStatus != SM_OK) { + return retStatus; + } + outputOffset = (uint16_t)listlen; + for (i = 0; i < listlen; i += 4) { + uint32_t id = 0 | (list[i + 0] << (3 * 8)) | (list[i + 1] << (2 * 8)) | (list[i + 2] << (1 * 8)) | + (list[i + 3] << (0 * 8)); + if (SE05X_OBJID_SE05X_APPLET_RES_START == SE05X_OBJID_SE05X_APPLET_RES_MASK(id)) { + LOG_D("Not erasing ObjId=0x%08X (Reserved)", id); + /* In Reserved space */ + } + else if (EX_SSS_OBJID_DEMO_AUTH_START == EX_SSS_OBJID_DEMO_AUTH_MASK(id)) { + LOG_D("Not erasing ObjId=0x%08X (Demo Auth)", id); + /* Not reasing default authentication object */ + } + else if (EX_SSS_OBJID_IOT_HUB_A_START == EX_SSS_OBJID_IOT_HUB_A_MASK(id)) { + LOG_D("Not erasing ObjId=0x%08X (IoT Hub)", id); + /* Not reasing IoT Hub object */ + } + else if (!SE05X_OBJID_TP_MASK(id) && id) { + LOG_D("Not erasing Trust Provisioned objects"); + } + else { + retStatus = Se05x_API_DeleteSecureObject(session_ctx, id); + if (retStatus != SM_OK) { + LOG_W("Error in erasing ObjId=0x%08X (Others)", id); + } + } + } + } while (pmore == kSE05x_MoreIndicator_MORE); +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + retStatus = Se05x_API_ReadCryptoObjectList(session_ctx, list, &listlen); + if (retStatus != SM_OK) { + goto cleanup; + } + for (i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + SE05x_CryptoObjectID_t ecryptoObjectId = (SE05x_CryptoObjectID_t)cryptoObjectId; + retStatus = Se05x_API_DeleteCryptoObject(session_ctx, ecryptoObjectId); + if (retStatus != SM_OK) { + LOG_W("Error in erasing CryptoObject=%04X", cryptoObjectId); + } + } +cleanup: +#endif + return retStatus; +} + +#endif + +bool Se05x_IsInValidRangeOfUID(uint32_t uid) +{ +#if 0 + // For SIMW-656 + bool retVal = TRUE; + if (uid >= EX_SSS_OBJID_DEMO_START && uid <= EX_SSS_OBJID_DEMO_END) + { + retVal = FALSE; + } + else if (uid >= SE05X_OBJID_SE05X_APPLET_RES_START && uid <= SE05X_OBJID_SE05X_APPLET_RES_END) + { + retVal = FALSE; + } + else if (uid >= EX_SSS_OBJID_TEST_START && uid <= EX_SSS_OBJID_TEST_END) + { + retVal = FALSE; + } + if (retVal == TRUE) { + LOG_E("Not allowing 0x%X uid", uid); + } + return retVal; +#else + return FALSE; +#endif +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c new file mode 100644 index 00000000000..d7abb74f592 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c @@ -0,0 +1,822 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "se05x_tlv.h" +#include "se05x_const.h" +#include // memcpy +#include +#include +#include "nxEnsure.h" +#include "smCom.h" +#include "sm_apdu.h" + +#ifdef FLOW_VERBOSE +#define VERBOSE_APDU_LOGS 1 +#else +#define VERBOSE_APDU_LOGS 0 +#endif + +#if SSS_HAVE_SE05X +#define SE05X_TLV_BUF_SIZE_CMD SE05X_MAX_BUF_SIZE_CMD +#define SE05X_TLV_BUF_SIZE_RSP SE05X_MAX_BUF_SIZE_RSP +#else +#define SE05X_TLV_BUF_SIZE_CMD 900 +#define SE05X_TLV_BUF_SIZE_RSP 900 +#endif + +int tlvSet_U8(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint8_t value) +{ + uint8_t *pBuf = *buf; + const size_t size_of_tlv = 1 + 1 + 1; + if (((*bufLen) + size_of_tlv) > SE05X_TLV_BUF_SIZE_CMD) + return 1; + *pBuf++ = (uint8_t)tag; + *pBuf++ = 1; + *pBuf++ = value; + *buf = pBuf; + *bufLen += size_of_tlv; + return 0; +} + +int tlvSet_U16Optional(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t value) +{ + if (value == 0) + return 0; + else + return tlvSet_U16(buf, bufLen, tag, value); +} + +int tlvSet_U16(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t value) +{ + const size_t size_of_tlv = 1 + 1 + 2; + uint8_t *pBuf = *buf; + if (((*bufLen) + size_of_tlv) > SE05X_TLV_BUF_SIZE_CMD) + return 1; + *pBuf++ = (uint8_t)tag; + *pBuf++ = 2; + *pBuf++ = (uint8_t)((value >> 1 * 8) & 0xFF); + *pBuf++ = (uint8_t)((value >> 0 * 8) & 0xFF); + *buf = pBuf; + *bufLen += size_of_tlv; + return 0; +} + +int tlvSet_U32(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint32_t value) +{ + const size_t size_of_tlv = 1 + 1 + 4; + uint8_t *pBuf = *buf; + if (((*bufLen) + size_of_tlv) > SE05X_TLV_BUF_SIZE_CMD) + return 1; + *pBuf++ = (uint8_t)tag; + *pBuf++ = 4; + *pBuf++ = (uint8_t)((value >> 3 * 8) & 0xFF); + *pBuf++ = (uint8_t)((value >> 2 * 8) & 0xFF); + *pBuf++ = (uint8_t)((value >> 1 * 8) & 0xFF); + *pBuf++ = (uint8_t)((value >> 0 * 8) & 0xFF); + *buf = pBuf; + *bufLen += size_of_tlv; + return 0; +} + +int tlvSet_U64_size(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint64_t value, uint16_t size) +{ + int8_t pos = 0; + pos = (uint8_t)size; + const size_t size_of_tlv = 1 + 1 + size; + uint8_t *pBuf = *buf; + if (((*bufLen) + size_of_tlv) > SE05X_TLV_BUF_SIZE_CMD) + return 1; + *pBuf++ = (uint8_t)tag; + *pBuf++ = pos; + pos--; + for (; pos >= 0; pos--) { + *pBuf++ = (uint8_t)((value >> pos * 8) & 0xFF); + } + *buf = pBuf; + *bufLen += size_of_tlv; + return 0; +} + +int tlvSet_Se05xPolicy(const char *description, uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, Se05xPolicy_t *policy) +{ + int tlvRet = 0; + if ((policy != NULL) && (policy->value != NULL)) { + tlvRet = tlvSet_u8buf(buf, bufLen, tag, policy->value, policy->value_len); +#if VERBOSE_APDU_LOGS + nLog("APDU", NX_LEVEL_DEBUG, "kSE05x_TAG_POLICY"); + nLog_au8("APDU", NX_LEVEL_DEBUG, description, policy->value, policy->value_len); +#endif + return tlvRet; + } + else { +#if VERBOSE_APDU_LOGS + nLog("APDU", NX_LEVEL_INFO, "Policy is NULL"); +#endif + } + + return tlvRet; +} + +int tlvSet_ECCurve(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, SE05x_ECCurve_t value) +{ + int retVal = 0; + if (value != kSE05x_ECCurve_NA) + retVal = tlvSet_U8(buf, bufLen, tag, (uint8_t)value); + return retVal; +} + +int tlvSet_u8bufOptional(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen) +{ + if (cmdLen == 0) + return 0; + else + return tlvSet_u8buf(buf, bufLen, tag, cmd, cmdLen); +} + +int tlvSet_u8bufOptional_ByteShift(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen) +{ + int ret = 1; + if (cmdLen == 0) { + ret = 0; + } + else if (0 == (cmdLen & 1)) { + /* LSB is 0 */ + ret = tlvSet_u8buf(buf, bufLen, tag, cmd, cmdLen); + } + else { + uint8_t localBuff[SE05X_MAX_BUF_SIZE_CMD]; + ENSURE_OR_GO_CLEANUP((cmdLen + 1) < sizeof(localBuff)); + localBuff[0] = '\0'; + memcpy(localBuff + 1, cmd, cmdLen); + ret = tlvSet_u8buf(buf, bufLen, tag, localBuff, cmdLen + 1); + } + +cleanup: + return ret; +} + +int tlvSet_u8buf(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, const uint8_t *cmd, size_t cmdLen) +{ + uint8_t *pBuf = *buf; + + /* if < 0x7F + * len = 1 byte + * elif if < 0xFF + * '0x81' + len == 2 Bytes + * elif if < 0xFFFF + * '0x82' + len_msb + len_lsb == 3 Bytes + */ + const size_t size_of_length = (cmdLen <= 0x7f ? 1 : (cmdLen <= 0xFf ? 2 : 3)); + const size_t size_of_tlv = 1 + size_of_length + cmdLen; + + if (((*bufLen) + size_of_tlv) > SE05X_TLV_BUF_SIZE_CMD) { + LOG_E("Not enough buffer"); + return 1; + } + *pBuf++ = (uint8_t)tag; + + if (cmdLen <= 0x7Fu) { + *pBuf++ = (uint8_t)cmdLen; + } + else if (cmdLen <= 0xFFu) { + *pBuf++ = (uint8_t)(0x80 /* Extended */ | 0x01 /* Additional Length */); + *pBuf++ = (uint8_t)((cmdLen >> 0 * 8) & 0xFF); + } + else if (cmdLen <= 0xFFFFu) { + *pBuf++ = (uint8_t)(0x80 /* Extended */ | 0x02 /* Additional Length */); + *pBuf++ = (uint8_t)((cmdLen >> 1 * 8) & 0xFF); + *pBuf++ = (uint8_t)((cmdLen >> 0 * 8) & 0xFF); + } + else { + return 1; + } + if ((cmdLen > 0) && (cmd != NULL)) { + while (cmdLen-- > 0) { + *pBuf++ = *cmd++; + } + } + + *bufLen += size_of_tlv; + *buf = pBuf; + + return 0; +} + +int tlvSet_u8buf_features(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, pSe05xAppletFeatures_t appletVariant) +{ + uint8_t features[32] = {0}; + size_t features_size = 0; + features[0] = (uint8_t)((appletVariant->variant >> 1 * 8) & 0xFF); + features_size++; + features[1] = (uint8_t)((appletVariant->variant >> 0 * 8) & 0xFF); + features_size++; + if (appletVariant->extended_features) { + memcpy(&features[2], + appletVariant->extended_features->features, + sizeof(appletVariant->extended_features->features)); + features_size += sizeof(appletVariant->extended_features->features); + } + + return tlvSet_u8buf(buf, bufLen, tag, &features[0], features_size); +} + +int tlvGet_U8(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint8_t *pRsp) +{ + int retVal = 1; + uint8_t *pBuf = buf + (*pBufIndex); + uint8_t got_tag = *pBuf++; + size_t rspLen; + + if ((*pBufIndex) > bufLen) { + goto cleanup; + } + + if (got_tag != tag) + goto cleanup; + rspLen = *pBuf++; + if (rspLen > 1) + goto cleanup; + *pRsp = *pBuf; + *pBufIndex += (1 + 1 + (rspLen)); + retVal = 0; +cleanup: + return retVal; +} + +int tlvSet_KeyID(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint32_t keyID) +{ + int retVal = 0; + if (keyID != 0) { + retVal = tlvSet_U32(buf, bufLen, tag, keyID); + } + return retVal; +} + +int tlvSet_MaxAttemps(uint8_t **buf, size_t *bufLen, SE05x_TAG_t tag, uint16_t maxAttemps) +{ + int retVal = 0; + if (maxAttemps != 0) { + retVal = tlvSet_U16(buf, bufLen, tag, maxAttemps); + } + return retVal; +} + +int tlvGet_SecureObjectType(uint8_t *buf, size_t *pBufIndex, size_t bufLen, SE05x_TAG_t tag, SE05x_SecObjTyp_t *pType) +{ + uint8_t uType = 0; + int retVal = tlvGet_U8(buf, pBufIndex, bufLen, tag, &uType); + *pType = (SE05x_SecObjTyp_t)uType; + return retVal; +} + +int tlvGet_Result(uint8_t *buf, size_t *pBufIndex, size_t bufLen, SE05x_TAG_t tag, SE05x_Result_t *presult) +{ + uint8_t uType = 0; + size_t uTypeLen = 1; + int retVal = tlvGet_u8buf(buf, pBufIndex, bufLen, tag, &uType, &uTypeLen); + *presult = (SE05x_Result_t)uType; + return retVal; +} + +int tlvGet_U16(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint16_t *pRsp) +{ + int retVal = 1; + uint8_t *pBuf = buf + (*pBufIndex); + uint8_t got_tag = *pBuf++; + size_t rspLen; + + if ((*pBufIndex) > bufLen) { + goto cleanup; + } + + if (got_tag != tag) { + goto cleanup; + } + rspLen = *pBuf++; + if (rspLen > 2) { + goto cleanup; + } + *pRsp = (*pBuf++) << 8; + *pRsp |= *pBuf++; + *pBufIndex += (1 + 1 + (rspLen)); + retVal = 0; +cleanup: + return retVal; +} + +//ISO 7816-4 Annex D. +int tlvGet_u8buf(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, uint8_t *rsp, size_t *pRspLen) +{ + int retVal = 1; + uint8_t *pBuf = buf + (*pBufIndex); + uint8_t got_tag = *pBuf++; + size_t extendedLen; + size_t rspLen; + //size_t len; + + if (rsp == NULL) { + goto cleanup; + } + + if (pRspLen == NULL) { + goto cleanup; + } + + if ((*pBufIndex) > bufLen) { + goto cleanup; + } + + if (got_tag != tag) { + goto cleanup; + } + rspLen = *pBuf++; + + if (rspLen <= 0x7FU) { + extendedLen = rspLen; + *pBufIndex += (1 + 1); + } + else if (rspLen == 0x81) { + extendedLen = *pBuf++; + *pBufIndex += (1 + 1 + 1); + } + else if (rspLen == 0x82) { + extendedLen = *pBuf++; + extendedLen = (extendedLen << 8) | *pBuf++; + *pBufIndex += (1 + 1 + 2); + } + else { + goto cleanup; + } + + if (extendedLen > *pRspLen) + goto cleanup; + if (extendedLen > bufLen) + goto cleanup; + + *pRspLen = extendedLen; + *pBufIndex += extendedLen; + while (extendedLen-- > 0) { + *rsp++ = *pBuf++; + } + retVal = 0; +cleanup: + if (retVal != 0) { + if (pRspLen != NULL) { + *pRspLen = 0; + } + } + return retVal; +} + +int tlvGet_ValueIndex(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag) +{ + int retVal = 1; + uint8_t *pBuf = buf + (*pBufIndex); + uint8_t got_tag = *pBuf++; + size_t extendedLen; + size_t rspLen; + + if ((*pBufIndex) > bufLen) { + goto cleanup; + } + + if (got_tag != tag) { + goto cleanup; + } + rspLen = *pBuf++; + + if (rspLen <= 0x7FU) { + extendedLen = rspLen; + *pBufIndex += (1 + 1); + } + else if (rspLen == 0x81) { + extendedLen = *pBuf++; + *pBufIndex += (1 + 1 + 1); + } + else if (rspLen == 0x82) { + extendedLen = *pBuf++; + extendedLen = (extendedLen << 8) | *pBuf++; + *pBufIndex += (1 + 1 + 2); + } + else { + goto cleanup; + } + + if (extendedLen > bufLen) + goto cleanup; + + retVal = 0; +cleanup: + return retVal; +} + +int tlvGet_TimeStamp(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, SE05x_TAG_t tag, SE05x_TimeStamp_t *pTs) +{ + size_t rspBufSize = sizeof(pTs->ts); + return tlvGet_u8buf(buf, pBufIndex, bufLen, tag, pTs->ts, &rspBufSize); +} + +smStatus_t DoAPDUTx_s_Case3(Se05xSession_t *pSessionCtx, const tlvHeader_t *hdr, uint8_t *cmdBuf, size_t cmdBufLen) +{ + uint8_t rxBuf[SE05X_TLV_BUF_SIZE_RSP + 2]; + size_t rxBufLen = sizeof(rxBuf); + smStatus_t apduStatus = SM_NOT_OK; + if (pSessionCtx->fp_TXn == NULL) { + apduStatus = SM_NOT_OK; + } + else { + apduStatus = pSessionCtx->fp_TXn(pSessionCtx, hdr, cmdBuf, cmdBufLen, rxBuf, &rxBufLen, 0); + } + return apduStatus; +} + +smStatus_t DoAPDUTxRx_s_Case2(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen) +{ + smStatus_t apduStatus; + if (pSessionCtx->fp_TXn == NULL) { + apduStatus = SM_NOT_OK; + } + else { + apduStatus = pSessionCtx->fp_TXn(pSessionCtx, hdr, cmdBuf, cmdBufLen, rspBuf, pRspBufLen, 0); + } + return apduStatus; +} + +smStatus_t DoAPDUTxRx_s_Case4(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen) +{ + smStatus_t apduStatus; + if (pSessionCtx->fp_TXn == NULL) { + apduStatus = SM_NOT_OK; + } + else { + apduStatus = pSessionCtx->fp_TXn(pSessionCtx, hdr, cmdBuf, cmdBufLen, rspBuf, pRspBufLen, 0); + } + return apduStatus; +} + +smStatus_t DoAPDUTxRx_s_Case4_ext(Se05xSession_t *pSessionCtx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rspBuf, + size_t *pRspBufLen) +{ + smStatus_t apduStatus = SM_NOT_OK; + if (pSessionCtx->fp_TXn == NULL) { + apduStatus = SM_NOT_OK; + } + else { + apduStatus = pSessionCtx->fp_TXn(pSessionCtx, hdr, cmdBuf, cmdBufLen, rspBuf, pRspBufLen, 1); + } + return apduStatus; +} + +smStatus_t DoAPDUTxRx( + Se05xSession_t *pSessionCtx, uint8_t *cmdBuf, size_t cmdBufLen, uint8_t *rspBuf, size_t *pRspBufLen) +{ + smStatus_t apduStatus = SM_NOT_OK; + size_t data_offset = 0; + size_t dataLen = 0; + apduTxRx_case_t apdu_case = APDU_TXRX_CASE_INVALID; + + if (smApduGetTxRxCase(cmdBuf, cmdBufLen, &data_offset, &dataLen, &apdu_case)) { + switch (apdu_case) { + case APDU_TXRX_CASE_1: + case APDU_TXRX_CASE_2: + case APDU_TXRX_CASE_2E: + apduStatus = DoAPDUTxRx_s_Case2( + pSessionCtx, (tlvHeader_t *)cmdBuf, cmdBuf + data_offset, dataLen, rspBuf, pRspBufLen); + break; + case APDU_TXRX_CASE_3: + case APDU_TXRX_CASE_4: + // Using case 4 here (also for case 3 apdus) to retrieve status word in response buffer. + apduStatus = DoAPDUTxRx_s_Case4( + pSessionCtx, (tlvHeader_t *)cmdBuf, cmdBuf + data_offset, dataLen, rspBuf, pRspBufLen); + break; + + case APDU_TXRX_CASE_3E: + case APDU_TXRX_CASE_4E: + // Using case 4 here (also for case 3 apdus) to retrieve status word in response buffer. + apduStatus = DoAPDUTxRx_s_Case4_ext( + pSessionCtx, (tlvHeader_t *)cmdBuf, cmdBuf + data_offset, dataLen, rspBuf, pRspBufLen); + break; + default: + LOG_E("Invalid APDU TxRX case"); + break; + } + } + return apduStatus; +} + +#if SSS_HAVE_SE05X +int tlvSet_u8buf_I2CM(uint8_t **buf, size_t *bufLen, SE05x_I2CM_TAG_t tag, const uint8_t *cmd, size_t cmdLen) +{ + /* if < 0x7F + * len = 1 byte + * elif if < 0xFF + * '0x81' + len == 2 Bytes + * elif if < 0xFFFF + * '0x82' + len_msb + len_lsb == 3 Bytes + */ + const size_t size_of_length = 2; + const size_t size_of_tlv = 1 + size_of_length + cmdLen; + uint8_t *pBuf = *buf; + if (((*bufLen) + size_of_tlv) > SE05X_I2CM_MAX_BUF_SIZE_CMD) { + LOG_E("Not enough buffer"); + return 1; + } + *pBuf++ = (uint8_t)tag; + if (cmdLen <= 0xFFFFu) { + *pBuf++ = (uint8_t)((cmdLen >> 1 * 8) & 0xFF); + *pBuf++ = (uint8_t)((cmdLen >> 0 * 8) & 0xFF); + } + else { + return 1; + } + if (cmdLen) { + while (cmdLen-- > 0) { + *pBuf++ = *cmd++; + } + *buf = pBuf; + *bufLen += size_of_tlv; + } + return 0; +} +#endif + +smStatus_t se05x_Transform(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdApduBuf, + const size_t cmdApduBufLen, + tlvHeader_t *out_hdr, + uint8_t *txBuf, + size_t *ptxBufLen, + uint8_t hasle) +{ + size_t i = 0; + + out_hdr->hdr[0] = hdr->hdr[0]; + out_hdr->hdr[1] = hdr->hdr[1]; + out_hdr->hdr[2] = hdr->hdr[2]; + out_hdr->hdr[3] = hdr->hdr[3]; + + if (pSession->hasSession) { +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession + + size_t SCmd_Lc = (cmdApduBufLen == 0) ? 0 : (((cmdApduBufLen < 0xFF) && !hasle) ? 1 : 3); + + size_t STag1_Len = 0 + /* cla ins */ + + 4 + SCmd_Lc + cmdApduBufLen; + + out_hdr->hdr[i++] = kSE05x_CLA; + out_hdr->hdr[i++] = kSE05x_INS_PROCESS; + out_hdr->hdr[i++] = kSE05x_P1_DEFAULT; + out_hdr->hdr[i++] = kSE05x_P2_DEFAULT; + + i = 0; + txBuf[i++] = kSE05x_TAG_SESSION_ID; + txBuf[i++] = sizeof(pSession->value); + memcpy(&txBuf[i], pSession->value, sizeof(pSession->value)); + i += sizeof(pSession->value); + txBuf[i++] = kSE05x_TAG_1; + if (STag1_Len <= 0x7Fu) { + txBuf[i++] = (uint8_t)STag1_Len; + } + else if (STag1_Len <= 0xFFu) { + txBuf[i++] = (uint8_t)(0x80 /* Extended */ | 0x01 /* Additional Length */); + txBuf[i++] = (uint8_t)((STag1_Len >> 0 * 8) & 0xFF); + } + else if (STag1_Len <= 0xFFFFu) { + txBuf[i++] = (uint8_t)(0x80 /* Extended */ | 0x02 /* Additional Length */); + txBuf[i++] = (uint8_t)((STag1_Len >> 8) & 0xFF); + txBuf[i++] = (uint8_t)((STag1_Len)&0xFF); + } + memcpy(&txBuf[i], hdr, sizeof(*hdr)); + i += sizeof(*hdr); + // In case there is a payload, indicate how long it is + // in Lc in the header. Do not include an Lc in case there + //is no payload. + if (cmdApduBufLen > 0) { + // The Lc field must be extended in case the length does not fit + // into a single byte (Note, while the standard would allow to + // encode 0x100 as 0x00 in the Lc field, nobody who is sane in his mind + // would actually do that). + if ((cmdApduBufLen < 0xFF) && !hasle) { + txBuf[i++] = (uint8_t)cmdApduBufLen; + } + else { + txBuf[i++] = 0x00; + txBuf[i++] = 0xFFu & (cmdApduBufLen >> 8); + txBuf[i++] = 0xFFu & (cmdApduBufLen); + } + } +#endif + } + + if (cmdApduBufLen > 0) { + memcpy(&txBuf[i], cmdApduBuf, cmdApduBufLen); + i += cmdApduBufLen; + } + + *ptxBufLen = i; + return SM_OK; +} + +smStatus_t se05x_DeCrypt( + struct Se05xSession *pSessionCtx, size_t cmd_cmacLen, uint8_t *rsp, size_t *rspLength, uint8_t hasle) +{ + U16 rv = SM_NOT_OK; + + if (*rspLength >= 2) { + rv = rsp[(*rspLength) - 2] << 8 | rsp[(*rspLength) - 1]; + if ((rv == SM_OK) && (pSessionCtx->pdynScp03Ctx != NULL)) { +#if SSS_HAVE_SCP_SCP03_SSS + rv = nxpSCP03_Decrypt_ResponseAPDU(pSessionCtx->pdynScp03Ctx, cmd_cmacLen, rsp, rspLength, hasle); +#else + LOG_W("Decrypting without SSS_HAVE_SCP_SCP03_SSS"); + rv = SM_NOT_OK; +#endif + } +#if SSS_HAVE_SCP_SCP03_SSS + else { /*Counter to be increament only in case of authentication is all kind of SCP + and response is not 9000 */ + if ((rv != SM_OK) && (pSessionCtx->pdynScp03Ctx != NULL)) { + if (((pSessionCtx->pdynScp03Ctx->authType == kSSS_AuthType_AESKey) || + (pSessionCtx->pdynScp03Ctx->authType == kSSS_AuthType_ECKey)) || + ((pSessionCtx->pdynScp03Ctx->authType == kSSS_AuthType_SCP03) && (cmd_cmacLen - 8) > 0)) { + nxpSCP03_Inc_CommandCounter(pSessionCtx->pdynScp03Ctx); + } + } + } +#endif + } + else { + rv = SM_NOT_OK; + } + + return rv; +} + +#if SSS_HAVE_SCP_SCP03_SSS +smStatus_t se05x_Transform_scp(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdApduBuf, + const size_t cmdApduBufLen, + tlvHeader_t *outhdr, + uint8_t *txBuf, + size_t *ptxBufLen, + uint8_t hasle) +{ + smStatus_t apduStatus = SM_NOT_OK; + sss_status_t sss_status = kStatus_SSS_Fail; + uint8_t macToAdd[16]; + size_t macLen = 16; + size_t i = 0; + + Se05xApdu_t se05xApdu = {0}; + + se05xApdu.se05xTxBuf = txBuf; + se05xApdu.se05xTxBufLen = *ptxBufLen; + se05xApdu.se05xCmd_hdr = hdr; + se05xApdu.se05xCmd = cmdApduBuf; + se05xApdu.se05xCmdLen = cmdApduBufLen; + + /*Encrypt the Tx APDU */ + sss_status = nxSCP03_Encrypt_CommandAPDU(pSession->pdynScp03Ctx, se05xApdu.se05xCmd, &(se05xApdu.se05xCmdLen)); + ENSURE_OR_GO_CLEANUP(sss_status == kStatus_SSS_Success); + + if (pSession->hasSession) { +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession + /*With session Final wrapping handled by transcive + * Copy the Wrapped header in the outhdr buffer */ + outhdr->hdr[0] = kSE05x_CLA; + outhdr->hdr[1] = kSE05x_INS_PROCESS; + outhdr->hdr[2] = kSE05x_P1_DEFAULT; + outhdr->hdr[3] = kSE05x_P2_DEFAULT; + + /* Add CMAC Length in SE05X command LC */ + se05xApdu.se05xCmdLC = se05xApdu.se05xCmdLen + SCP_GP_IU_CARD_CRYPTOGRAM_LEN; + se05xApdu.se05xCmdLCW = (se05xApdu.se05xCmdLC == 0) ? 0 : (((se05xApdu.se05xCmdLC < 0xFF) && !(hasle)) ? 1 : 3); + + se05xApdu.wsSe05x_tag1Len = sizeof(*(se05xApdu.se05xCmd_hdr)) + se05xApdu.se05xCmdLCW + se05xApdu.se05xCmdLC; + se05xApdu.wsSe05x_tag1W = + ((se05xApdu.wsSe05x_tag1Len <= 0x7F) ? 1 : (se05xApdu.wsSe05x_tag1Len <= 0xFF) ? 2 : 3); + + se05xApdu.wsSe05x_cmd = se05xApdu.se05xTxBuf; + uint8_t *wsCmd = se05xApdu.wsSe05x_cmd; + + wsCmd[i++] = kSE05x_TAG_SESSION_ID; + wsCmd[i++] = sizeof(pSession->value); + memcpy(&wsCmd[i], pSession->value, sizeof(pSession->value)); + i += sizeof(pSession->value); + + wsCmd[i++] = kSE05x_TAG_1; + + if (se05xApdu.wsSe05x_tag1W == 1) { + wsCmd[i++] = (uint8_t)se05xApdu.wsSe05x_tag1Len; + } + else if (se05xApdu.wsSe05x_tag1W == 2) { + wsCmd[i++] = (uint8_t)(0x80 /* Extended */ | 0x01 /* Additional Length */); + wsCmd[i++] = (uint8_t)((se05xApdu.wsSe05x_tag1Len >> 0 * 8) & 0xFF); + } + else if (se05xApdu.wsSe05x_tag1W == 3) { + wsCmd[i++] = (uint8_t)(0x80 /* Extended */ | 0x02 /* Additional Length */); + wsCmd[i++] = (uint8_t)((se05xApdu.wsSe05x_tag1Len >> 8) & 0xFF); + wsCmd[i++] = (uint8_t)((se05xApdu.wsSe05x_tag1Len) & 0xFF); + } + + se05xApdu.wsSe05x_tag1Cmd = &wsCmd[i]; + se05xApdu.wsSe05x_tag1CmdLen = + sizeof(*(se05xApdu.se05xCmd_hdr)) + se05xApdu.se05xCmdLCW + se05xApdu.se05xCmdLen; + + memcpy(&wsCmd[i], se05xApdu.se05xCmd_hdr, sizeof(*(se05xApdu.se05xCmd_hdr))); + /* Pad CLA byte with 0x04 to indicate use of SCP03*/ + wsCmd[i] |= 0x04; + i += sizeof(*(se05xApdu.se05xCmd_hdr)); + + // In case there is a payload, indicate how long it is + // in Lc in the header. Do not include an Lc in case there + //is no payload. + if (se05xApdu.se05xCmdLCW > 0) { + // The Lc field must be extended in case the length does not fit + // into a single byte (Note, while the standard would allow to + // encode 0x100 as 0x00 in the Lc field, nobody who is sane in his mind + // would actually do that). + if (se05xApdu.se05xCmdLCW == 1) { + wsCmd[i++] = (uint8_t)se05xApdu.se05xCmdLC; + } + else { + wsCmd[i++] = 0x00; + wsCmd[i++] = 0xFFu & (se05xApdu.se05xCmdLC >> 8); + wsCmd[i++] = 0xFFu & (se05xApdu.se05xCmdLC); + } + } + memcpy(&wsCmd[i], se05xApdu.se05xCmd, se05xApdu.se05xCmdLen); + i += se05xApdu.se05xCmdLen; + se05xApdu.wsSe05x_cmdLen = i; + se05xApdu.dataToMac = se05xApdu.wsSe05x_tag1Cmd; + se05xApdu.dataToMacLen = se05xApdu.wsSe05x_tag1CmdLen; +#endif + } + else { + /* If there is no session create the tx buffer with SE05X command only*/ + se05xApdu.se05xCmdLC = se05xApdu.se05xCmdLen + SCP_GP_IU_CARD_CRYPTOGRAM_LEN; + se05xApdu.se05xCmdLCW = (se05xApdu.se05xCmdLC == 0) ? 0 : (((se05xApdu.se05xCmdLC < 0xFF) && !(hasle)) ? 1 : 3); + + se05xApdu.dataToMac = &txBuf[i]; /* Mac is calculated from this data */ + se05xApdu.dataToMacLen = sizeof(*(se05xApdu.se05xCmd_hdr)) + se05xApdu.se05xCmdLCW + se05xApdu.se05xCmdLC - + SCP_GP_IU_CARD_CRYPTOGRAM_LEN; + + memcpy(&txBuf[i], se05xApdu.se05xCmd_hdr, sizeof(*se05xApdu.se05xCmd_hdr)); + txBuf[i] |= 0x4; + i += sizeof(*se05xApdu.se05xCmd_hdr); + + if (se05xApdu.se05xCmdLCW > 0) { + if (se05xApdu.se05xCmdLCW == 1) { + txBuf[i++] = (uint8_t)se05xApdu.se05xCmdLC; + } + else { + txBuf[i++] = 0x00; + txBuf[i++] = 0xFFu & (se05xApdu.se05xCmdLC >> 8); + txBuf[i++] = 0xFFu & (se05xApdu.se05xCmdLC); + } + } + memcpy(&txBuf[i], se05xApdu.se05xCmd, se05xApdu.se05xCmdLen); + i += se05xApdu.se05xCmdLen; + } + + ///*Calculate MAC over encrypted APDU */ + sss_status = nxpSCP03_CalculateMac_CommandAPDU( + pSession->pdynScp03Ctx, se05xApdu.dataToMac, se05xApdu.dataToMacLen, macToAdd, &macLen); + ENSURE_OR_GO_CLEANUP(sss_status == kStatus_SSS_Success); + memcpy(&txBuf[i], macToAdd, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + i += SCP_GP_IU_CARD_CRYPTOGRAM_LEN; + + if (!pSession->hasSession) { + if (hasle) { + txBuf[i++] = 0x00; + txBuf[i++] = 0x00; + } + } + se05xApdu.se05xTxBufLen = i; + *ptxBufLen = se05xApdu.se05xTxBufLen; + apduStatus = SM_OK; +cleanup: + return apduStatus; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h new file mode 100644 index 00000000000..02ce2e31831 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h @@ -0,0 +1,1207 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +/* OK */ +#else +#error "Only with SE051 based build" +#endif + +/** Se05x_API_AeadOneShot + * + * Authenticated encryption or decryption with associated data in one shot mode. + * + * The key object must be either an AES key or DES key. + * + * The AEADOneShot command returns the computed GMAC (when P2 equals + * P2_ENCRYPT_ONESHOT) or indicates whether the GMAC is correct (when P2 equals + * P2_DECRYPT_ONESHOT). The length of the GMAC is always 16 bytes when P2 equals + * P2_ENCRYPT_ONESHOT. + * + * When P2 equals P2_DECRYPT_ONESHOT: + * + * * the minimum tag length to pass is 4 bytes. + * + * * when the GMAC tag is not correct, only the result will be returned, no output data will be present. + * + * Note: on applet v4.4.0, the maximum lengths are not yet enforced and might + * differ from the values listed in the C-APDU. + * + * # Command to Applet + * + * @rst + * +---------+---------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+===========================+================================================+ + * | CLA | 0x80 | | + * +---------+---------------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+---------------------------+------------------------------------------------+ + * | P1 | P1_AEAD or P1_AEAD_INT_IV | See :cpp:type:`SE05x_P1_t` | + * +---------+---------------------------+------------------------------------------------+ + * | P2 | P2_ENCRYPT_ONESHOT or | See :cpp:type:`SE05x_P2_t` | + * | | P2_DECRYPT_ONESHOT | | + * +---------+---------------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+---------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the AESKey Secure object. | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 1-byte AEADMode | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data. Maximum | + * | | | length = 256 bytes. [Optional] | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_4] | Byte array containing Additional Authenticated | + * | | | Data. Maximum length = 64 bytes. [Optional] | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing an initialization vector | + * | | | (if P1 equals P1_AEAD) or 2-byte value | + * | | | containing the initialization vector length | + * | | | (if P1 equals P1_AEAD_SP800_108). Maximum IV | + * | | | length = 60 bytes. [Optional] | + * | | | [Conditional: required when P1 equals | + * | | | P1_AEAD_INT_IV] | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_6] | Byte array containing the GMAC tag to verify. | + * | | | [Conditional: when P2 equals | + * | | | P2_DECRYPT_ONESHOT] | + * +---------+---------------------------+------------------------------------------------+ + * | Le | 0x00 | Expecting return data. | + * +---------+---------------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------------------+ + * | Value | Description | + * +============+==============================================+ + * | TLV[TAG_1] | Byte array containing output data. | + * +------------+----------------------------------------------+ + * | TLV[TAG_2] | Byte array containing tag (if P2 = | + * | | P2_ENCRYPT_ONESHOT) or byte array containing | + * | | Result (if P2 = P2_DECRYPT_ONESHOT) | + * +------------+----------------------------------------------+ + * | TLV[TAG_3] | Byte array containing the initialization | + * | | vector (if P1 = P1_AEAD_INT_IV and P2 = | + * | | P2_ENCRYPT_ONESHOT). | + * +------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] cipherMode The cipher mode + * @param[in] inputData The input data + * @param[in] inputDataLen The input data length + * @param[in] aad The aad + * @param[in] aadLen The aad length + * @param[in] IV The iv + * @param[in] IVLen The iv length + * @param tagData The tag data + * @param tagDataLen The tag data length + * @param outputData The output data + * @param poutputDataLen The poutput data length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadOneShot(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *IV, + size_t IVLen, + uint8_t *tagData, + size_t *tagDataLen, + uint8_t *outputData, + size_t *poutputDataLen, + const SE05x_Cipher_Oper_OneShot_t operation); + +/** Se05x_API_AeadInit + * + * Initialize an authentication encryption or decryption with associated data. + * The Crypto Object keeps the state of the AEAD operation until it's finalized + * or deleted. Once the AEADFinal function is executed successfully, the Crypto + * Object state returns to the state immediately after the previous AEADInit + * function. + * + * When P1 equals P1_AEAD_INT_IV and P2 equals P1_ENCRYPT, TLV[TAG_5] must + * includes the length of the initialization vector. In that case, the + * initialization vector is generated internally and passed back in the response + * command. When the device is in FIPS mode (see FIPS Compliance), P1 equal to + * P1_AEAD will result in SW_CONDITIONS_NOT_SATISFIED. + * + * # Command to Applet + * + * @rst + * +---------+---------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+===========================+================================================+ + * | CLA | 0x80 | | + * +---------+---------------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+---------------------------+------------------------------------------------+ + * | P1 | P1_AEAD or P1_AEAD_INT_IV | See :cpp:type:`SE05x_P1_t` | + * +---------+---------------------------+------------------------------------------------+ + * | P2 | P2_ENCRYPT or P2_DECRYPT | See :cpp:type:`SE05x_P2_t` | + * +---------+---------------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+---------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the AESKey Secure object. | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+---------------------------+------------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing the initialization | + * | | | vector (if P1 equals P1_AEAD or P1 equals | + * | | | P1_AEAD and P2 equals P2_DECRYPT) or 2-byte | + * | | | value containing the initialization vector | + * | | | length (if P1 equals P1_AEAD_INT_IV and P2 | + * | | | equals P2_ENCRYPT) [Optional] | + * | | | [Conditional: required when P1 equals | + * | | | P1_AEAD_INT_IV and P2 equals P2_ENCRYPT] | + * +---------+---------------------------+------------------------------------------------+ + * | Le | - | | + * +---------+---------------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------------------+ + * | Value | Description | + * +============+===============================================+ + * | TLV[TAG_3] | Byte array containing the used initialization | + * | | vector. It remains valid until deselect, | + * | | AEADInit, AEADFinal or AEADOneShot is called. | + * | | [Conditional: Only when P1 equals | + * | | P1_AEAD_INT_IV and P2 equals P2_ENCRYPT] | + * +------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] cryptoObjectID The crypto object id + * @param[in] pIV { parameter_description } + * @param[in] IVLen The iv length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *pIV, + size_t IVLen, + const SE05x_Cipher_Oper_t operation); + +/** Se05x_API_AeadCCMInit + * + * Initialize an authentication encryption or decryption with associated data. + * The Crypto Object keeps the state of the AEAD operation until it's finalized + * or deleted. Once the AEADFinal function is executed successfully, the Crypto + * Object state returns to the state immediately after the previous AEADInit + * function.AEAD in CCM mode. + * + * # Command to Applet + * + * @rst + * +---------+--------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+==========================+================================================+ + * | CLA | 0x80 | | + * +---------+--------------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+--------------------------+------------------------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------------------+------------------------------------------------+ + * | P2 | P2_ENCRYPT or P2_DECRYPT | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the AESKey Secure object. | + * +---------+--------------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+--------------------------+------------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing the initialization | + * | | | vector [12 bytes until 60 bytes] or a 2-byte | + * | | | value containing the initialization vector | + * | | | length, depending on the AEADMode of the | + * | | | Crypto Object. | + * +---------+--------------------------+------------------------------------------------+ + * | | TLV[TAG_6] | Byte array containing 2-byte AAD length. | + * | | | [Conditional: needed if AEADMode equals | + * | | | AES_CCM] | + * +---------+--------------------------+------------------------------------------------+ + * | | TLV[TAG_7] | Byte array containing 2-byte message length. | + * | | | [Conditional: needed if AEADMode equals | + * | | | AES_CCM] | + * +---------+--------------------------+------------------------------------------------+ + * | | TLV[TAG_8] | Byte array containing 2-byte tag size. | + * | | | [Conditional: needed if AEADMode equals | + * | | | AES_CCM]. | + * +---------+--------------------------+------------------------------------------------+ + * | Le | - | | + * +---------+--------------------------+------------------------------------------------+ + * @endrst + * + * + * # R-APDU Body + * NA + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] cryptoObjectID The crypto object id + * @param[in] pIV { parameter_description } + * @param[in] IVLen The iv length + * @param[in] aadLen The aad length + * @param[in] payloadLen The payloadLen length + * @param[in] tagLen The tag length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadCCMInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *pIV, + size_t IVLen, + size_t aadLen, + size_t payloadLen, + size_t tagLen, + const SE05x_Cipher_Oper_t operation); + +/** + * @brief Se05x_API_AeadCCMLastUpdate + * + * # Command to Applet + * + * @rst + * +------------+---------------+------------------------------------------------+ + * | Field | Value | Description | + * +============+===============+================================================+ + * | CLA | 0x80 | | + * +------------+---------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+---------------+------------------------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +------------+---------------+------------------------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +------------+---------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +------------+---------------+------------------------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+---------------+------------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data | + * | | | [Conditional: only when | + * | | | TLV[TAG_4] is not present] | + * | | | [Optional] | + * +------------+---------------+------------------------------------------------+ + * | Le | 0x00 | Expecting returned data. | + * +------------+---------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * NA + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * + * + * @param[in] session_ctx The session context + * @param[in] cryptoObjectID The crypto object id + * @param[in] pInputData The input data + * @param[in] inputDataLen The input data length + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadCCMLastUpdate( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *pInputData, size_t inputDataLen); + +/** Se05x_API_AeadCCMFinal + * + * Finish a sequence of AES_CCM AEAD operations. + * + * # Command to Applet + * + * @rst + * +------------+----------------------------------+---------------------------------+ + * | Field | Value | Description | + * +============+==================================+=================================+ + * | CLA | 0x80 | | + * +------------+----------------------------------+---------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+----------------------------------+---------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +------------+----------------------------------+---------------------------------+ + * | P2 | P2_FINAL | See :cpp:type:`SE05x_P2_t` | + * +------------+----------------------------------+---------------------------------+ + * | Lc | #(Payload) | | + * +------------+----------------------------------+---------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+----------------------------------+---------------------------------+ + * | TLV[TAG_6] | Byte array containing tag to | | + * | | verify [Conditional] When the | | + * | | mode is decrypt and verify (i.e. | | + * | | AEADInit has been called with | | + * | | P2 = P2_DECRYPT). | | + * +------------+----------------------------------+---------------------------------+ + * | Le | 0x00 | Expected returned data. | + * +------------+----------------------------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | Output data | + * | | | + * +------------+------------------------------------------------+ + * | TLV[TAG_2] | Byte array containing tag (if P2 = P2_ENCRYPT) | + * | | or byte array containing Result (if P2 = | + * | | P2_DECRYPT) | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] cryptoObjectID The crypto object id + * @param[out] pOutputData The output data + * @param[out] pOutputLen The output length + * @param tag The tag + * @param tagLen The tag length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadCCMFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *pOutputData, + size_t *pOutputLen, + uint8_t *pTag, + size_t *pTagLen, + const SE05x_Cipher_Oper_t operation); + +/** Se05x_API_AeadUpdate_aad + * + * Update a Crypto Object of type CC_AEAD. + * + * The user either needs to send input data or Additional Authenticated Data + * (AAD), but not both at once. + * + * # Command to Applet + * + * @rst + * +------------+----------------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +============+==================================+================================================+ + * | CLA | 0x80 | | + * +------------+----------------------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+----------------------------------+------------------------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +------------+----------------------------------+------------------------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +------------+----------------------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +------------+----------------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+----------------------------------+------------------------------------------------+ + * | | TLV[TAG_4] | Byte array containing Additional Authenticated | + * | | | Data. [Conditional: only when TLV[TAG_3] is | + * | | | not present] [Optional] | + * +------------+----------------------------------+------------------------------------------------+ + * | Le | 0x00 | Expecting returned data. | + * +------------+----------------------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] cryptoObjectID The crypto object id + * @param[in] pAadData The aad data + * @param[in] aadDataLen The aad data length + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadUpdate_aad( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *pAadData, size_t aadDataLen); + +/** + * @brief Se05x_API_AeadUpdate + * + * # Command to Applet + * + * @rst + * +------------+---------------+------------------------------------------------+ + * | Field | Value | Description | + * +============+===============+================================================+ + * | CLA | 0x80 | | + * +------------+---------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+---------------+------------------------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +------------+---------------+------------------------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +------------+---------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +------------+---------------+------------------------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+---------------+------------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data | + * | | | [Conditional: only when | + * | | | TLV[TAG_4] is not present] | + * | | | [Optional] | + * +------------+---------------+------------------------------------------------+ + * | Le | 0x00 | Expecting returned data. | + * +------------+---------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+---------------------------------------+ + * | Value | Description | + * +============+=======================================+ + * | TLV[TAG_1] | Output data [Conditional: only when | + * | | TLV[TAG_3] is passed as input] | + * +------------+---------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * + * + * @param[in] session_ctx The session context + * @param[in] cryptoObjectID The crypto object id + * @param[in] pInputData The input data + * @param[in] inputDataLen The input data length + * @param pOutputData The output data + * @param pOutputLen The output length + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadUpdate(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *pInputData, + size_t inputDataLen, + uint8_t *pOutputData, + size_t *pOutputLen); + +/** Se05x_API_AeadFinal + * + * Finish a sequence of AEAD operations. The AEADFinal command provides the + * computed GMAC or indicates whether the GMAC is correct depending on the P2 + * parameters passed during AEADInit. The length of the GMAC is always 16 bytes + * when P2 equals P2_ENCRYPT. When P2 equals P2_DECRYPT, the minimum tag length + * to pass is 4 bytes. + * + * # Command to Applet + * + * @rst + * +------------+----------------------------------+---------------------------------+ + * | Field | Value | Description | + * +============+==================================+=================================+ + * | CLA | 0x80 | | + * +------------+----------------------------------+---------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+----------------------------------+---------------------------------+ + * | P1 | P1_AEAD | See :cpp:type:`SE05x_P1_t` | + * +------------+----------------------------------+---------------------------------+ + * | P2 | P2_FINAL | See :cpp:type:`SE05x_P2_t` | + * +------------+----------------------------------+---------------------------------+ + * | Lc | #(Payload) | | + * +------------+----------------------------------+---------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+----------------------------------+---------------------------------+ + * | TLV[TAG_6] | Byte array containing tag to | | + * | | verify [Conditional] When the | | + * | | mode is decrypt and verify (i.e. | | + * | | AEADInit has been called with | | + * | | P2 = P2_DECRYPT). | | + * +------------+----------------------------------+---------------------------------+ + * | Le | 0x00 | Expected returned data. | + * +------------+----------------------------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_2] | Byte array containing tag (if P2 = P2_ENCRYPT) | + * | | or byte array containing Result (if P2 = | + * | | P2_DECRYPT) | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] cryptoObjectID The crypto object id + * @param tag The tag + * @param tagLen The tag length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_AeadFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *tag, + size_t *tagLen, + const SE05x_Cipher_Oper_t operation); + +/** Se05x_API_DisableObjCreation + * + * + * # Command to Applet + * + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] lockIndicator [1:kSE05x_TAG_1] + * @param[in] restrictMode [2:kSE05x_TAG_2] + */ +smStatus_t Se05x_API_DisableObjCreation( + pSe05xSession_t session_ctx, SE05x_LockIndicator_t lockIndicator, SE05x_RestrictMode_t restrictMode); + +/** Se05x_API_ReadObjectAttributes + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[out] data [0:kSE05x_TAG_2] + * @param[in,out] pdataLen Length for data + */ +smStatus_t Se05x_API_ReadObjectAttributes( + pSe05xSession_t session_ctx, uint32_t objectID, uint8_t *data, size_t *pdataLen); + +/** Se05x_API_TriggerSelfTest + * + * Trigger a system health check for the system. When calling this command, a self-test is + * triggered in the operating system. When the test fails, the device might not respond with + * a R-APDU as the chip is reset. + * If HealthCheckMode is set to HCM_FIPS, the test will only work if the device is running in + * FIPS approved mode of operation. + * + * # Command to Applet + * + * + * @rst + * +------------+---------------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +============+=================================+================================================+ + * | CLA | 0x80 | | + * +------------+---------------------------------+------------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t`. In addition to | + * | | | INS_CRYPTO, users can set the INS_ATTEST | + * | | | flag. In that case, attestation applies. | + * +------------+---------------------------------+------------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +------------+---------------------------------+------------------------------------------------+ + * | P2 | P2_SANITY | See :cpp:type:`SE05x_P2_t` | + * +------------+---------------------------------+------------------------------------------------+ + * | Lc | #(Payload) | Payload length | + * +------------+---------------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 2-byte value from HealthCheckMode | + * +------------+---------------------------------+------------------------------------------------+ + * | Le | 0x00 | 2-byte response + attested data (if INS_ATTEST | + * | | | is set). | + * +------------+---------------------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | TLV containing 1-byte Result. | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] HealthCheckMode The health check mode + * @param result The result of Self Test + * + * @return The sm status. + */ + +smStatus_t Se05x_API_TriggerSelfTest( + pSe05xSession_t session_ctx, SE05x_HealthCheckMode_t healthCheckMode, uint8_t *result); + +/** Se05x_API_TriggerSelfTest_W_Attst + * + * Trigger a system health check for the system. When calling this command, a self-test is + * triggered in the operating system. When the test fails, the device might not respond with + * a R-APDU as the chip is reset. + * If HealthCheckMode is set to HCM_FIPS, the test will only work if the device is running in + * FIPS approved mode of operation. + * + * # Command to Applet + * + * + * @rst + * +------------+---------------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +============+=================================+================================================+ + * | CLA | 0x80 | | + * +------------+---------------------------------+------------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t`. In addition to | + * | | | INS_CRYPTO, users can set the INS_ATTEST | + * | | | flag. In that case, attestation applies. | + * +------------+---------------------------------+------------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +------------+---------------------------------+------------------------------------------------+ + * | P2 | P2_SANITY | See :cpp:type:`SE05x_P2_t` | + * +------------+---------------------------------+------------------------------------------------+ + * | Lc | #(Payload) | Payload length | + * +------------+---------------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 2-byte value from HealthCheckMode | + * +------------+---------------------------------+------------------------------------------------+ + * | TLV[TAG_5] | 4-byte attestation object | | + * | | identifier. [Optional] | | + * | | [Conditional: only when | | + * | | INS_ATTEST is set] | | + * +------------+---------------------------------+------------------------------------------------+ + * | TLV[TAG_6] | 1-byte AttestationAlgo | | + * | | [Optional] [Conditional: only | | + * | | when INS_ATTEST is set] | | + * +------------+---------------------------------+------------------------------------------------+ + * | TLV[TAG_7] | 16-byte freshness random | | + * | | [Optional] [Conditional: only | | + * | | when INS_ATTEST is set] | | + * +------------+---------------------------------+------------------------------------------------+ + * | Le | 0x00 | 2-byte response + attested data (if INS_ATTEST | + * | | | is set). | + * +------------+---------------------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | TLV containing 1-byte Result. | + * +------------+------------------------------------------------+ + * | TLV[TAG_3] | TLV containing 12-byte timestamp | + * | | [Conditional: only when C-APDU contains | + * | | INS_ATTEST] | + * +------------+------------------------------------------------+ + * | TLV[TAG_4] | TLV containing 16-byte freshness (random) | + * | | [Conditional: only when C-APDU contains | + * | | INS_ATTEST] | + * +------------+------------------------------------------------+ + * | TLV[TAG_5] | TLV containing 18-byte chip unique ID | + * | | [Conditional: only when C-APDU contains | + * | | INS_ATTEST] | + * +------------+------------------------------------------------+ + * | TLV[TAG_6] | TLV containing signature over the concatenated | + * | | values of TLV[TAG_1], TLV[TAG_3], TLV[TAG_4] | + * | | and TLV[TAG_5]. [Conditional: only when | + * | | C-APDU contains INS_ATTEST] | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] HealthCheckMode The health check mode + * @param[in] attestID The attest id + * @param[in] attestAlgo The attest algorithm + * @param[in] random The random + * @param[in] randomLen The random length + * @param result The result of Self Test + * @param ptimeStamp The ptime stamp + * @param outrandom The outrandom + * @param poutrandomLen The poutrandom length + * @param chipId The chip identifier + * @param pchipIdLen The pchip identifier length + * @param signature The signature + * @param psignatureLen The psignature length + * + * @return The sm status. + */ +smStatus_t Se05x_API_TriggerSelfTest_W_Attst(pSe05xSession_t session_ctx, + SE05x_HealthCheckMode_t healthCheckMode, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *result, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ECDHGenerateSharedSecret_InObject + * + * See @ref Se05x_API_ECDHGenerateSharedSecret + * + */ +smStatus_t Se05x_API_ECDHGenerateSharedSecret_InObject(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *pubKey, + size_t pubKeyLen, + uint32_t sharedSecretID, + uint8_t invertEndianness); + +/* +* @param[in] session_ctx Session Context[0:kSE05x_pSession] +* @param[in] keyPairId keyPairId[1:kSE05x_TAG_1] +* @param[in] pskId pskId[2:kSE05x_TAG_2] +* @param[in] hmacKeyId hmacKeyId[3:kSE05x_TAG_3] +* @param[in] inputData inputData[4:kSE05x_TAG_4] +* @param[in] inputDataLen Length of inputData +* @param[in] clientVersion client version[6:kSE05x_TAG_6] +* @param[in] clientVersionLen Length of client version +*/ + +smStatus_t Se05x_API_TLSCalculateRsaPreMasterSecret(pSe05xSession_t session_ctx, + uint32_t keyPairId, + uint32_t pskId, + uint32_t hmacKeyId, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *clientVersion, + size_t clientVersionLen); + +/** Se05x_API_WriteRSAKey_Ver +* +* See @ref Se05x_API_WriteRSAKey. Also allows to set key version (4 bytes). +* +*/ +smStatus_t Se05x_API_WriteRSAKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + uint32_t version); + +/** Se05x_API_UpdateRSAKey_Ver +* +* See @ref Se05x_API_WriteRSAKey. Also allows to set key version (4 bytes). +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +*/ +smStatus_t Se05x_API_UpdateRSAKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + uint32_t version); + +#define Se05x_API_WriteECKey_with_version Se05x_API_WriteECKey_Ver +/** Se05x_API_WriteECKey_Ver +* +* See @ref Se05x_API_WriteECKey. Also allows to set key version (4 bytes). +* +*/ +smStatus_t Se05x_API_WriteECKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + uint32_t version); + +/** Se05x_API_UpdateECKey_Ver +* +* See @ref Se05x_API_WriteECKey. Also allows to set key version (4 bytes). +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +*/ +smStatus_t Se05x_API_UpdateECKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + uint32_t version); + +/** Se05x_API_WriteSymmKey_Ver +* +* See @ref Se05x_API_WriteSymmKey. Also allows to set key version (4 bytes). +* +*/ +smStatus_t Se05x_API_WriteSymmKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + uint32_t version); + +/** Se05x_API_UpdateSymmKey_Ver +* +* See @ref Se05x_API_WriteSymmKey. Also allows to set key version (4 bytes). +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +*/ +smStatus_t Se05x_API_UpdateSymmKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + uint32_t version); + +/** Se05x_API_WriteBinary_Ver +* +* See @ref Se05x_API_WriteBinary. Also allows to set key version (4 bytes). +* +*/ +smStatus_t Se05x_API_WriteBinary_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t version); + +/** Se05x_API_UpdateBinary_Ver +* +* See @ref Se05x_API_WriteBinary. Also allows to set key version (4 bytes). +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +* +*/ +smStatus_t Se05x_API_UpdateBinary_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t version); + +/** Se05x_API_ReadState +* +* +* # Command to Applet +* +* +* # R-APDU Body +* +* NA +* +* # R-APDU Trailer +* +* +* +* +* @param[in] session_ctx Session Context [0:kSE05x_pSession] +* @param[out] pstateValues [1:kSE05x_TAG_1] +*/ +smStatus_t Se05x_API_ReadState(pSe05xSession_t session_ctx, uint8_t *pstateValues, size_t *pstateValuesLen); + +/** Se05x_API_GetExtVersion +* +* Gets the applet extended version information. +* +* This will return 37-byte VersionInfo (including major, minor and patch version +* of the applet, supported applet features and secure box version). +* +* # Command to Applet +* +* @rst +* +-------+------------------------------+----------------------------------------------+ +* | Field | Value | Description | +* +=======+==============================+==============================================+ +* | CLA | 0x80 | | +* +-------+------------------------------+----------------------------------------------+ +* | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | +* +-------+------------------------------+----------------------------------------------+ +* | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | +* +-------+------------------------------+----------------------------------------------+ +* | P2 | P2_VERSION or P2_VERSION_EXT | See :cpp:type:`SE05x_P2_t` | +* +-------+------------------------------+----------------------------------------------+ +* | Lc | #(Payload) | | +* +-------+------------------------------+----------------------------------------------+ +* | Le | 0x00 | Expecting TLV with 7-byte data (when P2 = | +* | | | P2_VERSION) or a TLV with 37 byte data (when | +* | | | P2= P2_VERSION_EXT). | +* +-------+------------------------------+----------------------------------------------+ +* @endrst +* +* +* # R-APDU Body +* +* @rst +* +------------+------------------------------------------------+ +* | Value | Description | +* +============+================================================+ +* | TLV[TAG_1] | 7-byte :cpp:type:`VersionInfoRef` (if P2 = | +* | | P2_VERSION) or 7-byte VersionInfo followed by | +* | | 30 bytes extendedFeatureBits (if P2 = | +* | | P2_VERSION_EXT) | +* +------------+------------------------------------------------+ +* @endrst +* +* # R-APDU Trailer +* +* @rst +* +-------------+--------------------------------+ +* | SW | Description | +* +=============+================================+ +* | SW_NO_ERROR | Data is returned successfully. | +* +-------------+--------------------------------+ +* @endrst +* +* @param[in] session_ctx The session context +* @param pappletVersion The papplet version +* @param appletVersionLen The applet version length +* +* @return The sm status. +*/ +smStatus_t Se05x_API_GetExtVersion(pSe05xSession_t session_ctx, uint8_t *pappletVersion, size_t *appletVersionLen); + +/**Se05x_API_SendCardManagerCmd +* +* Sends a command to the Card Manager. +* +* This APDU will send command to Card Manager +* +* # Command to Card Manager +* +* @rst +* +---------+---------------+--------------------------------------+ +* | Field | Value | Description | +* +=========+===============+======================================+ +* | CLA | 0x80 | | +* +---------+---------------+--------------------------------------+ +* | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | +* +---------+---------------+--------------------------------------+ +* | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | +* +---------+---------------+--------------------------------------+ +* | P2 | P2_CM_COMMAND | See :cpp:type:`SE05x_P2_t` | +* +---------+---------------+--------------------------------------+ +* | Lc | #(Payload) | Payload length | +* +---------+---------------+--------------------------------------+ +* | Payload | TLV[TAG_1] | APDU to be sent to the Card Manager. | +* +---------+---------------+--------------------------------------+ +* | Le | 0x00 | Expected response length | +* +---------+---------------+--------------------------------------+ +* @endrst +* +* # R-APDU Body +* +* @rst +* +------------+----------------------------------------+ +* | Value | Description | +* +============+========================================+ +* | TLV[TAG_1] | Byte array containing the Card Manager | +* | | response. | +* +------------+----------------------------------------+ +* @endrst +* +* # R-APDU Trailer +* +* @rst +* +-------------+--------------------------------------+ +* | SW | Description | +* +=============+======================================+ +* | SW_NO_ERROR | The command is handled successfully. | +* +-------------+--------------------------------------+ +* @endrst +* +* @param[in] session_ctx The session context +* @param[in] pCmdData The command input data +* @param[in] cmdDataLen The command input data length +* @param[out] pOutputData The response data +* @param[out] pOutputDataLen The response data length +* +* @return The sm status. +*/ +smStatus_t Se05x_API_SendCardManagerCmd( + pSe05xSession_t session_ctx, uint8_t *pCmdData, size_t cmdDataLen, uint8_t *pOutputData, size_t *pOutputDataLen); + +/** Se05x_API_UpdatePCR +* +* See @ref Se05x_API_WritePCR. +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +*/ +smStatus_t Se05x_API_UpdatePCR( + pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t pcrID, const uint8_t *inputData, size_t inputDataLen); + +/** Se05x_API_UpdateCounter +* +* See @ref Se05x_API_SetCounterValue. +* Called to update the value of already existing object. If policy is passed, +* it should match with existing policy on object. +*/ +smStatus_t Se05x_API_UpdateCounter( + pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t objectID, uint16_t size, uint64_t value); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h new file mode 100644 index 00000000000..ac531d92be9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h @@ -0,0 +1,1535 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#if defined(NONSECURE_WORLD) +#include "veneer_printf_table.h" +#endif + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +/* OK */ +#else +#error "Only with SE051 based build" +#endif + +#ifndef NEWLINE +#define NEWLINE must be already defined +#endif + +smStatus_t Se05x_API_AeadOneShot(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + const uint8_t *pInputData, + size_t inputDataLen, + const uint8_t *pAad, + size_t aadLen, + uint8_t *pIV, + size_t IVLen, + uint8_t *pTagData, + size_t *pTagDataLen, + uint8_t *pOutputData, + size_t *pOutputDataLen, + const SE05x_Cipher_Oper_OneShot_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, operation}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + SE05x_Result_t result; + uint16_t ivlen16 = (uint16_t)IVLen; + size_t ivlen32 = IVLen; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadOneShot []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CipherMode("cipherMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cipherMode); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, pInputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("AdditionalData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pAad, aadLen); + if (0 != tlvRet) { + goto cleanup; + } + + if ((cipherMode == kSE05x_CipherMode_AES_GCM) || + ((cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV) && (operation == kSE05x_Cipher_Oper_OneShot_Decrypt))) { + tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, pIV, IVLen); + if (0 != tlvRet) { + goto cleanup; + } + } + else { + tlvRet = TLVSET_U16("IVLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, ivlen16); + if (0 != tlvRet) { + goto cleanup; + } + } + if (operation == kSE05x_Cipher_Oper_OneShot_Decrypt) { + tlvRet = TLVSET_u8bufOptional("tag", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, pTagData, *pTagDataLen); + if (0 != tlvRet) { + goto cleanup; + } + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + if (inputDataLen != 0) { + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pOutputData, pOutputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + } + if (operation == kSE05x_Cipher_Oper_OneShot_Encrypt) { + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, pTagData, pTagDataLen); + if (0 != tlvRet) { + goto cleanup; + } + } + if (operation == kSE05x_Cipher_Oper_OneShot_Decrypt) { + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, &result); + if (0 != tlvRet) { + goto cleanup; + } + if (result != kSE05x_Result_SUCCESS) { + goto cleanup; + } + } + if ((operation == kSE05x_Cipher_Oper_OneShot_Encrypt) && (cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV)) { + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, pIV, &ivlen32); + if (0 != tlvRet) { + goto cleanup; + } + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *pIV, + size_t IVLen, + const SE05x_Cipher_Oper_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, operation}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + uint16_t ivlen16 = (uint16_t)IVLen; + size_t ivlen32 = IVLen; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadInit []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + if ((cipherMode == kSE05x_CipherMode_AES_GCM) || + ((cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV) && (operation == kSE05x_Cipher_Oper_Decrypt))) { + tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, pIV, IVLen); + if (0 != tlvRet) { + goto cleanup; + } + } + else { + tlvRet = TLVSET_U16("IVLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, ivlen16); + if (0 != tlvRet) { + goto cleanup; + } + } + if ((cipherMode == kSE05x_CipherMode_AES_GCM) || + ((cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV) && (operation == kSE05x_Cipher_Oper_Decrypt))) { + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + } + else { + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pIV, &ivlen32); + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + } +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadCCMInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *pIV, + size_t IVLen, + size_t aadLen, + size_t payloadLen, + size_t tagLen, + const SE05x_Cipher_Oper_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, operation}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint16_t aadLen16 = (uint16_t)aadLen; + uint16_t payloadLen16 = (uint16_t)payloadLen; + uint16_t tagLen16 = (uint16_t)tagLen; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadCCMInit []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, pIV, IVLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("aadLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, aadLen16); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("payloadLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, payloadLen16); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("tagLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_8, tagLen16); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadUpdate_aad( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *pAadData, size_t aadDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadUpdate_aad []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("aad", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pAadData, aadDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadUpdate(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *pInputData, + size_t inputDataLen, + uint8_t *pOutputData, + size_t *pOutputLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadUpdate []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, pInputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pOutputData, pOutputLen); + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadCCMLastUpdate( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *pInputData, size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadUpdate []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, pInputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadCCMFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *pOutputData, + size_t *pOutputLen, + uint8_t *pTag, + size_t *pTagLen, + const SE05x_Cipher_Oper_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, kSE05x_P2_FINAL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + size_t tagLen = *pTagLen; + SE05x_Result_t result; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadFinal []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + if (operation == kSE05x_Cipher_Oper_Decrypt) { + tlvRet = TLVSET_u8bufOptional("tag", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, pTag, tagLen); + if (0 != tlvRet) { + goto cleanup; + } + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pOutputData, pOutputLen); + if (0 != tlvRet) { + goto cleanup; + } + if (operation == kSE05x_Cipher_Oper_Encrypt) { + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, pTag, pTagLen); + if (0 != tlvRet) { + goto cleanup; + } + } + if (operation == kSE05x_Cipher_Oper_Decrypt) { + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, &result); + if (0 != tlvRet) { + goto cleanup; + } + + if (result != kSE05x_Result_SUCCESS) { + goto cleanup; + } + } + + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_AeadFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + uint8_t *pTag, + size_t *pTagLen, + const SE05x_Cipher_Oper_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, kSE05x_P2_FINAL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + size_t tagLen = *pTagLen; + SE05x_Result_t result; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "AeadFinal []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + if (operation == kSE05x_Cipher_Oper_Decrypt) { + tlvRet = TLVSET_u8bufOptional("tag", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, pTag, tagLen); + if (0 != tlvRet) { + goto cleanup; + } + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + if (operation == kSE05x_Cipher_Oper_Encrypt) { + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, pTag, pTagLen); + if (0 != tlvRet) { + goto cleanup; + } + } + if (operation == kSE05x_Cipher_Oper_Decrypt) { + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, &result); + if (0 != tlvRet) { + goto cleanup; + } + if (result != kSE05x_Result_SUCCESS) { + goto cleanup; + } + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DisableObjCreation( + pSe05xSession_t session_ctx, SE05x_LockIndicator_t lockIndicator, SE05x_RestrictMode_t restrictMode) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_RESTRICT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DisableObjCreation []"); +#endif /* VERBOSE_APDU_LOGS */ + + tlvRet = TLVSET_U8("lockIndicator", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, lockIndicator); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("restrictMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, restrictMode); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_TriggerSelfTest( + pSe05xSession_t session_ctx, SE05x_HealthCheckMode_t healthCheckMode, uint8_t *result) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SANITY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TriggerSelfTest []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U16("health check mode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, healthCheckMode); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, result); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_TriggerSelfTest_W_Attst(pSe05xSession_t session_ctx, + SE05x_HealthCheckMode_t healthCheckMode, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *result, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT | kSE05x_INS_ATTEST, kSE05x_P1_DEFAULT, kSE05x_P2_SANITY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TriggerSelfTest []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U16("health check mode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, healthCheckMode); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("attestID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, attestID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("attestAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, attestAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, random, randomLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, result); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_4, outrandom, poutrandomLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_5, chipId, pchipIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_6, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadObjectAttributes( + pSe05xSession_t session_ctx, uint32_t objectID, uint8_t *data, size_t *pdataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_ATTRIBUTES}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadObjectAttributes []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadObjectAttributes_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ_With_Attestation, kSE05x_P1_DEFAULT, kSE05x_P2_ATTRIBUTES}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadObjectAttributes_W_Attst []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("attestID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, attestID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_AttestationAlgo("attestAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, attestAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, random, randomLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_4, outrandom, poutrandomLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_5, chipId, pchipIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_6, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ECDHGenerateSharedSecret_InObject(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *pubKey, + size_t pubKeyLen, + uint32_t sharedSecretID, + uint8_t invertEndianness) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = { + {kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_EC, invertEndianness == 0x01 ? kSE05x_P2_DH_REVERSE : kSE05x_P2_DH}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ECDHGenerateSharedSecret []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("pubKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, pubKey, pubKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("sharedSecretID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, sharedSecretID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + if (2 == rspbufLen) { + retStatus = (rspbuf[0] << 8) | (rspbuf[1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_TLSCalculateRsaPreMasterSecret(pSe05xSession_t session_ctx, + uint32_t keyPairId, + uint32_t pskId, + uint32_t hmacKeyId, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *clientVersion, + size_t clientVersionLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_TLS, kSE05x_P2_TLS_PMS}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TLSCalculateRsaPreMasterSecret []"); +#endif /* VERBOSE_APDU_LOGS */ + if (pskId != 0) { + tlvRet = TLVSET_U32("pskId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, pskId); + if (0 != tlvRet) { + goto cleanup; + } + } + tlvRet = TLVSET_U32("keyPairId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, keyPairId); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("hmacKeyId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, hmacKeyId); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("clientVersion", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, clientVersion, clientVersionLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteRSAKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_RSA | key_part, rsa_format}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_WriteRSAKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("To be Checked(last 3 not pdf)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("size in bits", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, size); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("p", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, p, pLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("q", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, q, qLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, dp, dpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dq", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, dq, dqLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("qnv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, qInv, qInvLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("public exp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_8, pubExp, pubExpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("priv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_9, priv, privLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("public mod", &pCmdbuf, &cmdbufLen, kSE05x_TAG_10, pubMod, pubModLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteECKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_EC | key_part, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_WriteECKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECCurve("curveID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, curveID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("privKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, privKey, privKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("pubKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pubKey, pubKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteSymmKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, type, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_WriteSymmKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_KeyID("KEK id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, kekID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("key value", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, keyValue, keyValueLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteBinary_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_BINARY, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_WriteBinary_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("input data", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadState(pSe05xSession_t session_ctx, uint8_t *pstateValues, size_t *pstateValuesLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_READ_STATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadState []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pstateValues, pstateValuesLen); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetExtVersion(pSe05xSession_t session_ctx, uint8_t *pappletVersion, size_t *appletVersionLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_VERSION_EXT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetVersion []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pappletVersion, appletVersionLen); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SendCardManagerCmd( + pSe05xSession_t session_ctx, uint8_t *pCmdData, size_t cmdDataLen, uint8_t *pOutputData, size_t *pOutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_CM_COMMAND}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SendCardManagerCmd []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("cmdData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, pCmdData, cmdDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pOutputData, pOutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdateRSAKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_RSA | key_part, rsa_format}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_UpdateRSAKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + /* Tag policy Check is not applicable for Generate key */ + if (((p != NULL) && (pLen != 0)) || ((pubExp != NULL) && (pubExpLen != 0)) || ((priv != NULL) && (privLen != 0))) { + tlvRet = TLVSET_Se05xPolicy("check policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("size in bits", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, size); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("p", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, p, pLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("q", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, q, qLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, dp, dpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dq", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, dq, dqLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("qnv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, qInv, qInvLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("public exp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_8, pubExp, pubExpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("priv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_9, priv, privLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("public mod", &pCmdbuf, &cmdbufLen, kSE05x_TAG_10, pubMod, pubModLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdateECKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_EC | key_part, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_UpdateECKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + + /* Tag policy Check is not applicable for Generate key */ + if (((privKey != NULL) && (privKeyLen != 0)) || ((pubKey != NULL) && (pubKeyLen != 0))) { + tlvRet = TLVSET_Se05xPolicy("check policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + } + + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECCurve("curveID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, curveID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("privKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, privKey, privKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("pubKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pubKey, pubKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdateBinary_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_BINARY, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_UpdateBinary_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("check policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("input data", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdateSymmKey_Ver(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + uint32_t version) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, type, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_UpdateSymmKey_Ver []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_Se05xPolicy("check policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_KeyID("KEK id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, kekID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("key value", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, keyValue, keyValueLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("version", &pCmdbuf, &cmdbufLen, kSE05x_TAG_11, version); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdatePCR( + pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t pcrID, const uint8_t *inputData, size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_PCR, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(pcrID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_UpdatePCR []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("check policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, pcrID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_UpdateCounter( + pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t objectID, uint16_t size, uint64_t value) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_COUNTER, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_CreateCounter []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy check", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY_CHECK, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + + if ((size > 0) && (size <= 8)) { + if (value != 0) { + tlvRet = TLVSET_U64_SIZE("value", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, value, size); + if (0 != tlvRet) { + goto cleanup; + } + } + } + else { + LOG_E("Wrong size provided"); + goto cleanup; + } + + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c new file mode 100644 index 00000000000..1549fa76a15 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c @@ -0,0 +1,91 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_SE05X + +#ifdef FLOW_VERBOSE +#define VERBOSE_APDU_LOGS 1 +#else +#define VERBOSE_APDU_LOGS 0 +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / (sizeof(array[0]))) +#endif + +#include "nxLog_hostLib.h" + +/* TLV APIs */ +#include "se05x_tlv.h" +/* Used constants */ +#include "se05x_const.h" + +#include "se05x_APDU.h" + +/* Generated implementation */ +#include "se05x_APDU_impl.h" + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#include "se05x_04_xx_APDU_impl.h" +#endif + +smStatus_t Se05x_API_I2CM_Send( + pSe05xSession_t session_ctx, const uint8_t *buffer, size_t bufferLen, uint8_t *result, size_t *presultLen) +{ + smStatus_t retStatus = SM_NOT_OK; + const tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_I2CM}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + uint8_t *pCmdbuf = &cmdbuf[0]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + + /*tlvRet = TLVSET_Se05xSession("session identifier", &pCmdbuf, &cmdbufLen, kSE05x_TAG_SESSION_ID, session_ctx); + if (0 != tlvRet) { + goto cleanup; + }*/ + tlvRet = TLVSET_u8buf("TLV Buffer", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, buffer, bufferLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + + LOG_AU8_D(rspbuf, rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, result, presultLen); + if (0 != tlvRet) { //Response check is skipped to be corrected. + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } +cleanup: + return retStatus; +} +#endif // SSS_HAVE_SE05X + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h new file mode 100644 index 00000000000..b01f5421665 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h @@ -0,0 +1,76 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ + +#ifndef SE050X_APDU_H +#define SE050X_APDU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "se05x_tlv.h" +#include "se05x_const.h" +#include "se05x_APDU_apis.h" + +/** Se05x_API_DeleteAll_Iterative + * + * Go through each object and delete it individually. + * + * This API does not use the Applet API @ref Se05x_API_DeleteAll. It + * does not delete ALL objects and purposefully skips few objects. + * + * Instead, this API uses @ref Se05x_API_ReadIDList and @ref + * Se05x_API_ReadCryptoObjectList to first fetch list of objects to host, and + * **selectitvely** deletes. + * + * For e.g. It does not kill objects from: + * - The range SE05X_OBJID_SE05X_APPLET_RES_START to + * SE05X_OBJID_SE05X_APPLET_RES_END. This range is used by applet. + * - The range EX_SSS_OBJID_DEMO_AUTH_START to EX_SSS_OBJID_DEMO_AUTH_END, + * which is used by middleware DEMOS for authentication. + * - And others. + * + * Kindly see the Implementation of is API Se05x_API_DeleteAll_Iterative to see + * the list of ranges that are skipped. + * + * @param[in] session_ctx Session Context + * + * @return The status of API. + */ +smStatus_t Se05x_API_DeleteAll_Iterative(pSe05xSession_t session_ctx); + +/** + * @brief Get the Curve ID for existing Key. + * + * This API is functionally same as @ref Se05x_API_GetECCurveId + * but uses @ref SE05x_ECCurve_t as a type instead of uint8_t. + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param pcurveId The pcurve identifier + * + * + * @return The sm status. + */ +smStatus_t Se05x_API_EC_CurveGetId(pSe05xSession_t session_ctx, uint32_t objectID, SE05x_ECCurve_t *pcurveId); + +/** Wrapper for @ref Se05x_API_ECDHGenerateSharedSecret */ + +#define Se05x_API_ECGenSharedSecret Se05x_API_ECDHGenerateSharedSecret + +/** Wrapper for @ref Se05x_API_DigestOneShot */ +#define Se05x_API_SHAOneShot Se05x_API_DigestOneShot + +// For SIMW-656 +bool Se05x_IsInValidRangeOfUID(uint32_t uid); + +#ifdef __cplusplus +} +#endif + +#endif /* SE050X_APDU_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h new file mode 100644 index 00000000000..ca095d260b2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h @@ -0,0 +1,5812 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ + +#ifndef SE050X_APDU_APIS_H_INC +#define SE050X_APDU_APIS_H_INC + +#include "se05x_enums.h" +#include "se05x_tlv.h" + +/* Enable compilation of deprecated API Se05x_API_WritePCR + * Deprecated from Q1 2021. + * Support will be removed by Q1 2022 + */ +#define ENABLE_DEPRECATED_API_WritePCR 1 + +/** Se05x_API_CreateSession + * + * Creates a session on SE05X . + * + * Depending on the authentication object being referenced, a specific method of + * authentication applies. The response needs to adhere to this authentication + * method. + * + * + * # Command to Applet + * + * @rst + * +---------+-------------------+------------------------------+ + * | Field | Value | Description | + * +=========+===================+==============================+ + * | CLA | 0x80 | | + * +---------+-------------------+------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+-------------------+------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+-------------------+------------------------------+ + * | P2 | P2_SESSION_CREATE | See :cpp:type:`SE05x_P2_t` | + * +---------+-------------------+------------------------------+ + * | Lc | #(Payload) | Payload length. | + * +---------+-------------------+------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte authentication object | + * | | | identifier. | + * +---------+-------------------+------------------------------+ + * | Le | 0x0A | Expecting TLV with 8-byte | + * | | | session ID. | + * +---------+-------------------+------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------+ + * | Value | Description | + * +============+============================+ + * | TLV[TAG_1] | 8-byte session identifier. | + * +------------+----------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * SW_NO_ERROR: + * * The command is handled successfully. + * + * SW_CONDITIONS_NOT_SATISFIED: + * * The authenticator does not exist + * * The provided input data are incorrect. + * * The session is invalid. + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] authObjectID auth [1:kSE05x_TAG_1] + * @param[out] sessionId [0:kSE05x_TAG_1] + * @param[in,out] psessionIdLen Length for sessionId + * + * + */ +smStatus_t Se05x_API_CreateSession( + pSe05xSession_t session_ctx, uint32_t authObjectID, uint8_t *sessionId, size_t *psessionIdLen); + +/** Se05x_API_ExchangeSessionData + * + * Sets session policies for the current session. + * + * + * # Command to Applet + * + * @rst + * +---------+-------------------+-----------------------------+ + * | Field | Value | Description | + * +=========+===================+=============================+ + * | CLA | 0x80 or 0x84 | - | + * +---------+-------------------+-----------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+-------------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+-------------------+-----------------------------+ + * | P2 | P2_SESSION_POLICY | See P2 | + * +---------+-------------------+-----------------------------+ + * | Lc | #(Payload) | Payload length. | + * +---------+-------------------+-----------------------------+ + * | Payload | TLV[TAG_1] | Session policies | + * +---------+-------------------+-----------------------------+ + * | | C-MAC | If applicable | + * +---------+-------------------+-----------------------------+ + * | Le | 0x00 | - | + * +---------+-------------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +-------+----------------------------+ + * | Value | Description | + * +=======+============================+ + * | R-MAC | Optional, depending on | + * | | established security level | + * +-------+----------------------------+ + * @endrst + * + * + * @rst + * +-----------------------------+------------------------+ + * | SW | Description | + * +=============================+========================+ + * | SW_NO_ERROR | The command is handled | + * | | successfully. | + * +-----------------------------+------------------------+ + * | SW_CONDITIONS_NOT_SATISFIED | Invalid policies | + * +-----------------------------+------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] policy Check pdf [1:kSE05x_TAG_1] + * + */ +smStatus_t Se05x_API_ExchangeSessionData(pSe05xSession_t session_ctx, pSe05xPolicy_t policy); + +/** Se05x_API_RefreshSession + * + * Refreshes a session on , the policy of the running session can be updated; the + * rest of the session state remains. + * + * # Command to Applet + * + * @rst + * +-------+--------------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+====================+===============================================+ + * | CLA | 0x80 | - | + * +-------+--------------------+-----------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+--------------------+-----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------------+-----------------------------------------------+ + * | P2 | P2_SESSION_REFRESH | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------------+-----------------------------------------------+ + * | Lc | #(Payload) | Payload length. | + * +-------+--------------------+-----------------------------------------------+ + * | | TLV[TAG_POLICY] | Byte array containing the policy to attach to | + * | | | the session. [Optional] | + * +-------+--------------------+-----------------------------------------------+ + * | Le | - | | + * +-------+--------------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] policy policy [1:kSE05x_TAG_POLICY] + */ +smStatus_t Se05x_API_RefreshSession(pSe05xSession_t session_ctx, pSe05xPolicy_t policy); + +/** Se05x_API_CloseSession + * + * Closes a running session. + * + * When a session is closed, it cannot be reopened. + * + * All session parameters are transient. + * + * # Command to Applet + * + * @rst + * +-------+------------------+-----------------------------+ + * | Field | Value | Description | + * +=======+==================+=============================+ + * | CLA | 0x80 | | + * +-------+------------------+-----------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------+-----------------------------+ + * | P2 | P2_SESSION_CLOSE | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+-------------------------------------+ + * | SW | Description | + * +=============+=====================================+ + * | SW_NO_ERROR | The session is closed successfully. | + * +-------------+-------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + */ +smStatus_t Se05x_API_CloseSession(pSe05xSession_t session_ctx); + +/** Se05x_API_VerifySessionUserID + * + * Verifies the session user identifier (UserID) in order to allow setting up a + * session. If the UserID is correct, the session establishment is successful; + * otherwise the session cannot be opened (SW_CONDITIONS_NOT_SATISFIED is + * returned). + * + * # Command to Applet + * + * @rst + * +-------+-------------------+-----------------------------+ + * | Field | Value | Description | + * +=======+===================+=============================+ + * | CLA | 0x80 | | + * +-------+-------------------+-----------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+-------------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+-------------------+-----------------------------+ + * | P2 | P2_SESSION_USERID | See :cpp:type:`SE05x_P2_t` | + * +-------+-------------------+-----------------------------+ + * | Lc | #(Payload) | Payload length. | + * +-------+-------------------+-----------------------------+ + * | | TLV[TAG_1] | UserID value | + * +-------+-------------------+-----------------------------+ + * | Le | - | | + * +-------+-------------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] userId userId [1:kSE05x_TAG_1] + * @param[in] userIdLen Length of userId + */ +smStatus_t Se05x_API_VerifySessionUserID(pSe05xSession_t session_ctx, const uint8_t *userId, size_t userIdLen); + +/** Se05x_API_SetLockState + * + * Sets the applet transport lock (locked or unlocked). There is a Persistent + * lock and a Transient Lock. If the Persistent lock is UNLOCKED, the device is + * unlocked (regardless of the Transient lock). If the Persistent lock is LOCKED, + * the device is only unlocked when the Transient lock is UNLOCKED and the device + * will be locked again after deselect of the applet. + * + * Note that regardless of the lock state, the credential RESERVED_ID_TRANSPORT + * allows access to all features. For example, it is possible to write/update + * objects within the session opened by RESERVED_ID_TRANSPORT, even if the applet + * is locked. + * + * The default TRANSIENT_LOCK state is LOCKED; there is no default + * PERSISTENT_LOCK state (depends on product configuration). + * + * This command can only be used in a session that used the credential with + * identifier RESERVED_ID_TRANSPORT as authentication object. + * + * @rst + * +-----------------+----------------+-----------------------------------------------+ + * | PERSISTENT_LOCK | TRANSIENT_LOCK | Behavior | + * +=================+================+===============================================+ + * | UNLOCKED | UNLOCKED | Unlocked until PERSISTENT_LOCK set to LOCKED. | + * +-----------------+----------------+-----------------------------------------------+ + * | UNLOCKED | LOCKED | Unlocked until PERSISTENT_LOCK set to LOCKED. | + * +-----------------+----------------+-----------------------------------------------+ + * | LOCKED | UNLOCKED | Unlocked until deselect or TRANSIENT_LOCK set | + * | | | to LOCKED. | + * +-----------------+----------------+-----------------------------------------------+ + * | LOCKED | LOCKED | Locked until PERSISTENT_LOCK set to UNLOCKED. | + * +-----------------+----------------+-----------------------------------------------+ + * @endrst + * + * + * # Command to Applet + * + * @rst + * +---------+--------------+-------------------------------------+ + * | Field | Value | Description | + * +=========+==============+=====================================+ + * | CLA | 0x80 | | + * +---------+--------------+-------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+--------------+-------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------+-------------------------------------+ + * | P2 | P2_TRANSPORT | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------+-------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------+-------------------------------------+ + * | Payload | TLV[TAG_1] | 1-byte :cpp:type:`LockIndicatorRef` | + * +---------+--------------+-------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`LockStateRef` | + * +---------+--------------+-------------------------------------+ + * | Le | | | + * +---------+--------------+-------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] lockIndicator lock indicator [1:kSE05x_TAG_1] + * @param[in] lockState lock state [2:kSE05x_TAG_2] + */ +smStatus_t Se05x_API_SetLockState(pSe05xSession_t session_ctx, uint8_t lockIndicator, uint8_t lockState); + +/** Se05x_API_SetPlatformSCPRequest + * + * Sets the required state for platform SCP (required or not required). This is a + * persistent state. + * + * If platform SCP is set to SCP_REQUIRED, any applet APDU command will be + * refused by the applet when platform SCP is not enabled. Enabled means full + * encryption and MAC, both on C-APDU and R-APDU. Any other level is not + * sufficient and will not be accepted. SCP02 will not be accepted (as there is + * no response MAC and encryption). + * + * If platform SCP is set to "not required," any applet APDU command will be + * accepted by the applet. + * + * This command can only be used in a session that used the credential with + * identifier RESERVED_ID_PLATFORM_SCP as authentication object. + * + * Note that the default state is SCP_NOT_REQUIRED. + * + * + * # Command to Applet + * + * @rst + * +---------+------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=========+============+===============================================+ + * | CLA | 0x80 | | + * +---------+------------+-----------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+------------+-----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+-----------------------------------------------+ + * | P2 | P2_SCP | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+-----------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+------------+-----------------------------------------------+ + * | Payload | TLV[TAG_1] | 1-byte :cpp:type:`SE05x_PlatformSCPRequest_t` | + * +---------+------------+-----------------------------------------------+ + * | Le | | | + * +---------+------------+-----------------------------------------------+ + * @endrst + * + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] platformSCPRequest platf scp req [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_SetPlatformSCPRequest(pSe05xSession_t session_ctx, SE05x_PlatformSCPRequest_t platformSCPRequest); + +/** Se05x_API_SetAppletFeatures + * + * Sets the applet features that are supported. To successfully execute this + * command, the session must be authenticated using the RESERVED_ID_FEATURE. + * + * The 2-byte input value is a pre-defined AppletConfig value. + * + * # Command to Applet + * + * @rst + * +---------+------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=========+============+===============================================+ + * | CLA | 0x80 | | + * +---------+------------+-----------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+------------+-----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+-----------------------------------------------+ + * | P2 | P2_VARIANT | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+-----------------------------------------------+ + * | Lc | #(Payload) | Payload length | + * +---------+------------+-----------------------------------------------+ + * | Payload | TLV[TAG_1] | 2-byte Variant from | + * | | | :cpp:type:`SE05x_AppletConfig_t` | + * +---------+------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] variant variant [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_SetAppletFeatures(pSe05xSession_t session_ctx, pSe05xAppletFeatures_t appletVariant); + +/** Se05x_API_WriteECKey + * + * Write or update an EC key object. + * + * P1KeyPart indicates the key type to be created (if the object does not yet + * exist). + * + * If P1KeyPart = P1_KEY_PAIR, Private Key Value (TLV[TAG_3]) and Public Key + * Value (TLV[TAG_4) must both be present, or both be absent. If absent, the key + * pair is generated in the SE05X . + * + * If the object already exists, P1KeyPart is ignored. + * + * @rst + * +---------+------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+========================+================================================+ + * | P1 | :cpp:type:`SE05x_P1_t` | See :cpp:type:`SE05x_P1_t` , P1KeyType | + * | | | P1_EC | should only be set for new objects. | + * +---------+------------------------+------------------------------------------------+ + * | P2 | P2_DEFAULT | See P2 | + * +---------+------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional - only when the object | + * | | | identifier is not in use yet] | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_MAX_ATTEMPTS] | 2-byte maximum number of attempts. If 0 is | + * | | | given, this means unlimited. [Optional: | + * | | | default unlimited] [Conditional: only when | + * | | | the object identifier is not in use yet and | + * | | | INS includes INS_AUTH_OBJECT; see | + * | | | AuthenticationObjectPolicies ] | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 1-byte curve identifier, see ECCurve | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet; ] | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_3] | Private key value (see :cpp:type:`ECKeyRef` | + * | | | ) [Conditional: only when the private key is | + * | | | externally generated and P1KeyType is either | + * | | | P1_KEY_PAIR or P1_PRIVATE] | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_4] | Public key value (see :cpp:type:`ECKeyRef` ) | + * | | | [Conditional: only when the public key is | + * | | | externally generated and P1KeyType is either | + * | | | P1_KEY_PAIR or P1_PUBLIC] | + * +---------+------------------------+------------------------------------------------+ + * | | TLV[TAG_11] | 4-byte version [Optional] | + * +---------+------------------------+------------------------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] policy The policy + * @param[in] maxAttempt The maximum attempt + * @param[in] objectID The object id + * @param[in] curveID The curve id + * @param[in] privKey The priv key + * @param[in] privKeyLen The priv key length + * @param[in] pubKey The pub key + * @param[in] pubKeyLen The pub key length + * @param[in] ins_type The insert type + * @param[in] key_part The key part + * + * @return The sm status. + */ +smStatus_t Se05x_API_WriteECKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part); + +/** Se05x_API_WriteRSAKey + * + * Creates or writes an RSA key or a key component. + * + * Supported key sizes are listed in RSABitLength. Other values are not + * supported. + * + * An RSA key creation requires multiple ADPUs to be sent: + * + * * The first APDU must contain: + * + * * Policy (optional, so only if non-default applies) + * + * * Object identifier + * + * * Key size + * + * * 1 of the key components. + * + * * Each next APDU must contain 1 of the key components. + * + * The policy applies only once all key components are set. + * + * Once an RSAKey object has been created, its format remains fixed and cannot + * be updated (so CRT or raw mode, no switch possible). + * + * If the object already exists, P1KeyType is ignored. + * + * For key pairs, if no component is present (TAG_3 until TAG_9), the key pair + * will be generated on chip; otherwise the key pair will be constructed + * starting with the given component. + * + * For private keys or public keys, there should always be exactly one of the + * tags TAG_3 until TAG_10. + * + * * TLV[TAG_8] and TLV[TAG_10] must only contain a value if the key pair is + * to be set to a known value and P1KeyType is either P1_KEY_PAIR or + * P1_PUBLIC; otherwise the value must be absent and the length must be + * equal to 0. + * + * * TLV[TAG_9] must only contain a value it the key is to be set in raw mode + * to a known value and P1KeyType is either P1_KEY_PAIR or P1_PRIVATE; + * otherwise the value must be absent and the length must be equal to 0. + * + * * If TLV[TAG_3] up to TLV[TAG_10] are absent (except TLV[TAG_8]), the RSA + * key will be generated on chip in case the object does not yet exist; + * otherwise it will be regenerated. This only applies to RSA key pairs. + * + * * Keys can be set by setting the different components of a key; only 1 + * component can be set at a time in this case. + * + * + * @rst + * +---------+-------------------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+===============================+================================================+ + * | P1 | :cpp:type:`SE05x_KeyPart_t` | | See :cpp:type:`SE05x_P1_t` | + * | | P1_RSA | | + * +---------+-------------------------------+------------------------------------------------+ + * | P2 | P2_DEFAULT or P2_RAW | See :cpp:type:`SE05x_P2_t`; P2_RAW only in | + * | | | case P1KeyPart = P1_KEY_PAIR and TLV[TAG_3] | + * | | | until TLV[TAG_10] is empty and the must | + * | | | generate a raw RSA key pair; all other cases: | + * | | | P2_DEFAULT. | + * +---------+-------------------------------+------------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 2-byte key size in bits | + * | | | (:cpp:type:`SE05x_RSABitLength_t`) | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_3] | P component [Conditional: only when the | + * | | | object identifier is in CRT mode and the key | + * | | | is generated externally and P1KeyPart is | + * | | | either P1_KEY_PAIR or P1_PRIVATE] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_4] | Q component [Conditional: only when the | + * | | | object identifier is in CRT mode and the key | + * | | | is generated externally and P1KeyPart is | + * | | | either P1_KEY_PAIR or P1_PRIVATE] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_5] | DP component [Conditional: only when the | + * | | | object identifier is in CRT mode and the key | + * | | | is generated externally and P1KeyPart is | + * | | | either P1_KEY_PAIR or P1_PRIVATE] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_6] | DQ component [Conditional: only when the | + * | | | object identifier is in CRT mode and the key | + * | | | is generated externally and P1KeyPart is | + * | | | either P1_KEY_PAIR or P1_PRIVATE] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_7] | INV_Q component [Conditional: only when the | + * | | | object identifier is in CRT mode and the key | + * | | | is generated externally and P1KeyPart is | + * | | | either P1_KEY_PAIR or P1_PRIVATE] | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_8] | Public exponent | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_9] | Private Key (non-CRT mode only) | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_10] | Public Key (Modulus) | + * +---------+-------------------------------+------------------------------------------------+ + * | | TLV[TAG_11] | 4-byte version [Optional] | + * +---------+-------------------------------+------------------------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] policy The policy + * @param[in] objectID The object id + * @param[in] size The size + * @param[in] p The part p + * @param[in] pLen The p length + * @param[in] q The quarter + * @param[in] qLen The quarter length + * @param[in] dp The part dp + * @param[in] dpLen The dp length + * @param[in] dq The part dq + * @param[in] dqLen The dq length + * @param[in] qInv The quarter inv + * @param[in] qInvLen The quarter inv length + * @param[in] pubExp The pub exponent + * @param[in] pubExpLen The pub exponent length + * @param[in] priv The priv + * @param[in] privLen The priv length + * @param[in] pubMod The pub modifier + * @param[in] pubModLen The pub modifier length + * @param[in] transient_type The transient type + * @param[in] key_part The key part + * @param[in] rsa_format The rsa format + * + * @return The sm status. + */ + +smStatus_t Se05x_API_WriteRSAKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t transient_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format); + +/** Se05x_API_WriteSymmKey + * + * Creates or writes an AES key, DES key or HMAC key, indicated by P1: + * + * * P1_AES + * + * * P1_DES + * + * * P1_HMAC + * + * Users can pass RFC3394 wrapped keys by indicating the KEK in TLV[TAG_2]. Note + * that RFC3394 required 8-byte aligned input, so this can only be used when the + * key has an 8-byte aligned length. + * + * # Command to Applet + * + * @rst + * +---------+-----------------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=========+=======================+===============================================+ + * | P1 | See above | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------------+-----------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+-----------------------+-----------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_MAX_ATTEMPTS] | 2-byte maximum number of attempts. If 0 is | + * | | | given, this means unlimited. [Optional: | + * | | | default unlimited] [Conditional: only when | + * | | | the object identifier is not in use yet and | + * | | | INS includes INS_AUTH_OBJECT; see | + * | | | AuthenticationObjectPolicies] | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 4-byte KEK identifier [Conditional: only | + * | | | when the key value is RFC3394 wrapped] | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_3] | Key value, either plain or RFC3394 wrapped. | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_4] | Tag length for GCM/GMAC. Will only be used if | + * | | | the object is an AESKey. [Optional] | + * +---------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_11] | 4-byte version [Optional] | + * +---------+-----------------------+-----------------------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] policy The policy + * @param[in] maxAttempt The maximum attempt + * @param[in] objectID The object id + * @param[in] kekID The kek id + * @param[in] keyValue The key value + * @param[in] keyValueLen The key value length + * @param[in] ins_type The insert type + * @param[in] type The type + * + * @return The sm status. + */ +smStatus_t Se05x_API_WriteSymmKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type); + +/** Se05x_API_WriteBinary + * + * Creates or writes to a binary file object. Data are written to either the + * start of the file or (if specified) to the offset passed to the function. + * + * # Command to Applet + * + * @rst + * +---------+-----------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=========+=================+===============================================+ + * | P1 | P1_BINARY | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------+-----------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+-----------------+-----------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-----------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +---------+-----------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 2-byte file offset [Optional: default = 0] | + * +---------+-----------------+-----------------------------------------------+ + * | | TLV[TAG_3] | 2-byte file length (up to 0x7FFF). | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-----------------+-----------------------------------------------+ + * | | TLV[TAG_4] | Data to be written [Optional: if not given, | + * | | | TAG_3 must be filled] | + * +---------+-----------------+-----------------------------------------------+ + * | | TLV[TAG_11] | 4-byte version [Optional] | + * +---------+-----------------+-----------------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] policy policy [1:kSE05x_TAG_POLICY] + * @param[in] objectID object id [2:kSE05x_TAG_1] + * @param[in] offset offset [3:kSE05x_TAG_2] + * @param[in] length length [4:kSE05x_TAG_3] + * @param[in] inputData input data [5:kSE05x_TAG_4] + * @param[in] inputDataLen Length of inputData + */ + +smStatus_t Se05x_API_WriteBinary(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen); + +/** Se05x_API_WriteUserID + * + * Creates a UserID object, setting the user identifier value. The policy defines + * the maximum number of attempts that can be performed as comparison. + * + * # Command to Applet + * + * @rst + * +-------+-----------------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+=======================+===============================================+ + * | P1 | P1_USERID | See :cpp:type:`SE05x_P1_t` | + * +-------+-----------------------+-----------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +-------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +-------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_MAX_ATTEMPTS] | 2-byte maximum number of attempts. If 0 is | + * | | | given, this means unlimited. For pins, the | + * | | | maximum number of attempts must be smaller | + * | | | than 256. [Optional: default = 0] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet and INS includes | + * | | | INS_AUTH_OBJECT; see :cpp:type:`-`] | + * +-------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier. | + * +-------+-----------------------+-----------------------------------------------+ + * | | TLV[TAG_2] | Byte array containing 4 to 16 bytes user | + * | | | identifier value. | + * +-------+-----------------------+-----------------------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] policy The policy + * @param[in] maxAttempt The maximum attempt + * @param[in] objectID The object id + * @param[in] userId The user identifier + * @param[in] userIdLen The user identifier length + * @param[in] attestation_type The attestation type + * + * @return The sm status. + */ +smStatus_t Se05x_API_WriteUserID(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + const uint8_t *userId, + size_t userIdLen, + const SE05x_AttestationType_t attestation_type); + +/** Se05x_API_CreateCounter + * + * Creates a new counter object. + * + * Counters can only be incremented, not decremented. + * + * When a counter reaches its maximum value (e.g., 0xFFFFFFFF for a 4-byte + * counter), they cannot be incremented again. + * + * An input value (TAG_3) must always have the same length as the existing + * counter (if it exists); otherwise the command will return an error. + * + * # Command to Applet + * + * @rst + * +---------+-----------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+=================+================================================+ + * | P1 | P1_COUNTER | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------+------------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+-----------------+------------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte counter identifier. | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_2] | 2-byte counter size (1 up to 8 bytes). | + * | | | [Conditional: only if object doesn't exist yet | + * | | | and TAG_3 is not given] | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_3] | Counter value [Optional: - if object doesn't | + * | | | exist: must be present if TAG_2 is not given. | + * | | | - if object exists: if not present, increment | + * | | | by 1. if present, set counter to value.] | + * +---------+-----------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * NA + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] policy policy [1:kSE05x_TAG_POLICY] + * @param[in] objectID object id [2:kSE05x_TAG_1] + * @param[in] size size [3:kSE05x_TAG_2] + */ +smStatus_t Se05x_API_CreateCounter( + pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t objectID, uint16_t size); + +/** Se05x_API_SetCounterValue + * + * See @ref Se05x_API_CreateCounter + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[in] size size [3:kSE05x_TAG_2] + * @param[in] value value [4:kSE05x_TAG_3] + */ +smStatus_t Se05x_API_SetCounterValue(pSe05xSession_t session_ctx, uint32_t objectID, uint16_t size, uint64_t value); + +/** Se05x_API_IncCounter + * + * See @ref Se05x_API_CreateCounter + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_IncCounter(pSe05xSession_t session_ctx, uint32_t objectID); + +/** Se05x_API_WritePCR + * + * Creates or writes to a PCR object. + * + * A PCR is a hash to which data can be appended; i.e., writing data to a PCR + * will update the value of the PCR to be the hash of all previously inserted + * data concatenated with the new input data. + * + * A PCR will always use DigestMode = DIGEST_SHA256; no other configuration + * possible. + * + * If TAG_2 and TAG_3 is not passed, the PCR is reset to its initial value (i.e., + * the value set when the PCR was created). + * + * This reset is controlled under the POLICY_OBJ_ALLOW_DELETE policy, so users + * that can delete the PCR can also reset the PCR to initial value. + * + * # Command to Applet + * + * @rst + * +---------+-----------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+=================+================================================+ + * | P1 | P1_PCR | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------+------------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+-----------------+------------------------------------------------+ + * | Payload | TLV[TAG_POLICY] | Byte array containing the object policy. | + * | | | [Optional: default policy applies] | + * | | | [Conditional: only when the object identifier | + * | | | is not in use yet] | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte PCR identifier. | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_2] | Initial hash value [Conditional: only when | + * | | | the object identifier is not in use yet] | + * +---------+-----------------+------------------------------------------------+ + * | | TLV[TAG_3] | Data to be extended to the existing PCR. | + * | | | [Conditional: only when the object identifier | + * | | | is already in use] [Optional: not present if | + * | | | a Reset is requested] | + * +---------+-----------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] policy policy [1:kSE05x_TAG_POLICY] + * @param[in] pcrID object id [2:kSE05x_TAG_1] + * @param[in] initialValue initialValue [3:kSE05x_TAG_2] + * @param[in] initialValueLen Length of initialValue + * @param[in] inputData inputData [4:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + */ +#if ENABLE_DEPRECATED_API_WritePCR +smStatus_t Se05x_API_WritePCR(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t pcrID, + const uint8_t *initialValue, + size_t initialValueLen, + const uint8_t *inputData, + size_t inputDataLen); +#endif // ENABLE_DEPRECATED_API_WritePCR +smStatus_t Se05x_API_WritePCR_WithType(pSe05xSession_t session_ctx, + const SE05x_INS_t ins_type, + pSe05xPolicy_t policy, + uint32_t pcrID, + const uint8_t *initialValue, + size_t initialValueLen, + const uint8_t *inputData, + size_t inputDataLen); + +/** Se05x_API_ImportObject + * + * Writes a serialized Secure Object to the SE05X (i.e., "import") + * + * # Command to Applet + * + * @rst + * +---------+------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=========+============+===============================================+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+-----------------------------------------------+ + * | P2 | P2_IMPORT | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+-----------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier. | + * +---------+------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSAKeyComponent_t` | + * | | | [Conditional: only when the identifier refers | + * | | | to an RSAKey object] | + * +---------+------------+-----------------------------------------------+ + * | | TLV[TAG_3] | Serialized object (encrypted). | + * +---------+------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[in] rsaKeyComp rsaKeyComp [2:kSE05x_TAG_2] + * @param[in] serializedObject serializedObject [3:kSE05x_TAG_3] + * @param[in] serializedObjectLen Length of serializedObject + */ +smStatus_t Se05x_API_ImportObject(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAKeyComponent_t rsaKeyComp, + const uint8_t *serializedObject, + size_t serializedObjectLen); + +/** Se05x_API_ImportExternalObject + * + * Combined with the INS_IMPORT_EXTERNAL mask, enables users to send a + * WriteSecureObject APDU (WriteECKey until WritePCR) protected by a + * secure channel. + * + * Secure Objects can be imported into the SE05X through a secure channel which + * does not require the establishment of a session. This feature is also referred + * to single side import and can only be used to create or update objects. + * + * The mechanism is based on ECKey session to protect the Secure Object content + * and is summarized in the following figure. + * + * External import flow + * + * The flow above can be summarized in the following steps: + * + * 1. The user obtains the SE public key for import via the to get + * the public key from the device's key pair. Key ID 0x02 will + * return the public key of the EC key pair with + * RESERVED_ID_EXTERNAL_IMPORT. The response is signed by the + * same key pair. + * + * 2. The user calls with input: + * * the applet AID (e.g.A0000003965453000000010300000000) + * + * * the SCPparameters + * + * * 1-byte SCP identifier, must equal0xAB + * + * * 2-byte SCP parameter, must equal 0x01 followed by 1-byte + * security level (which follows the GlobalPlatform security + * level definition, see: . + * + * * key type, must be 0x88 (AES keytype) + * + * * key length, must be 0x10 (AES128key) + * + * * host public key (65-byte NIST P-256 publickey) + * + * * host public key curve identifier (must be 0x03 (=NIST_P256)) + * + * * ASN.1 signature over the TLV with tags 0xA6 and0x7F49. + * + * The applet will then calculate the master key by performing SHA256 + * over a byte array containing (in order): + * + * * 4-byte counter value being0x00000001 + * + * * shared secret (ECDH calculation according [IEEE P1363] using + * the private keyfrom RESERVED_ID_ECKEY_SESSION and the public + * key provided as input to ECKeySessionInternalAuthenticate. The + * length depends on the curve used (e.g. 32 byte for NIST P-256 + * curve). + * + * * 16-byte random generated by the SE05X. + * + * * 2-byte SCP parameter, must equal 0x01 followed by 1-byte + * security level (which follows the GlobalPlatform security level + * definition, see: . + * + * * 1-byte keytype + * + * * 1-byte keylength + * + * The master key will then be the 16 MSB's of the hash output. + * + * Using the master key, the 3 session keys are derived by following the + * GlobalPlatform specification to derive session keys, e.g. derivation input: + * + * * ENCsession key = CMAC(MK, 00000000000000000000000400008001) + * + * * CMACsession key = CMAC(MK, 00000000000000000000000600008001) + * + * * RMACsession key = CMAC(MK, 00000000000000000000000700008001) + * + * The Authentication Object ID needs to be passed using TAG_IMPORT_AUTH_KEY_ID, + * followed by the Write APDU command (using tag TAG_1). + * + * The Write APDU command needs to be constructed as follows: + * + * * Encrypt the command encryption counter (starting with + * 0x00000000000000000000000000000001) using the S_ENC key. This + * becomes the IV for the encrypted APDU. + * + * * Get the APDU command payload and pad it (ISO9797 M2 padding). + * + * * Encrypt the payload in AES CBC mode using the S_ENC key. + * + * * Set the Secure Messaging bit in the CLA (0x04). + * + * * Concatenate the MAC chaining value with the full APDU. + * + * * Then calculate the MAC on this byte array and append the 8-byte + * MAC value to the APDU. + * + * * Finally increment the encryption counter for the next command. + * + * A receipt will be generated by doing a CMAC operation on the input from tag + * 0xA6 and 0x7F49 using the RMAC session key, + * + * Receipt = CMAC(RMAC session key, ) + * + * There is no need to establish a session; therefore, the ImportExternalObject + * commands are always sent in the default session. The ImportExternalObject + * commands are replayable. + * + * The P1 and P2 parameters shall be coded as per the intended operation. For + * example, to import an EC Key, the P1 and P2 parameters as defined in + * WriteECKey shall be specified. + * + * # Command to Applet + * + * @rst + * +---------+-----------------------------+---------------------------------------------+ + * | Field | Value | Description | + * +=========+=============================+=============================================+ + * | CLA | 0x80 | | + * +---------+-----------------------------+---------------------------------------------+ + * | INS | INS_IMPORT_EXTERNAL | See :cpp:type:`SE05x_INS_t` | + * +---------+-----------------------------+---------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------------------+---------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+-----------------------------+---------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+-----------------------------+---------------------------------------------+ + * | Payload | TLV[TAG_IMPORT_AUTH_DATA] | Authentication data | + * +---------+-----------------------------+---------------------------------------------+ + * | | TLV[TAG_IMPORT_AUTH_KEY_ID] | Host public key Identifier | + * +---------+-----------------------------+---------------------------------------------+ + * | | TLV[TAG_1]... | Wraps a complete WriteSecureObject command, | + * | | | protected by ECKey session secure messaging | + * +---------+-----------------------------+---------------------------------------------+ + * | | TLV[TAG_11] | 4-byte version [Optional] | + * +---------+-----------------------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] ECKeydata ECKeydata [1:kSE05x_TAG_2] + * @param[in] ECKeydataLen Length of ECKeydata + * @param[in] serializedObject serializedObject [2:kSE05x_TAG_3] + * @param[in] serializedObjectLen Length of serializedObject + */ +smStatus_t Se05x_API_ImportExternalObject(pSe05xSession_t session_ctx, + const uint8_t *ECKeydata, + size_t ECKeydataLen, + const uint8_t *ECAuthKeyID, + size_t ECAuthKeyIDLen, + const uint8_t *serializedObject, + size_t serializedObjectLen); + +/** Se05x_API_ReadObject + * + * Reads the content of a Secure Object. + * + * * If the object is a key pair, the command will return the key + * pair's public key. + * + * * If the object is a public key, the command will return the public + * key. + * + * * If the object is a private key or a symmetric key or a userID, + * the command will return SW_CONDITIONS_NOT_SATISFIED. + * + * * If the object is a binary file, the file content is read, giving + * the offset in TLV[TAG_2] and the length to read in + * TLV[TAG_3]. Both TLV[TAG_2] and TLV[TAG_3] are bound together; + * i.e.. either both tags are present, or both are absent. If both + * are absent, the whole file content is returned. + * + * * If the object is a monotonic counter, the counter value is + * returned. + * + * * If the object is a PCR, the PCR value is returned. + * + * * If TLV[TAG_4] is filled, only the modulus or public exponent of + * an RSA key pair or RSA public key is read. It does not apply to + * other Secure Object types. + * + * # Command to Applet + * + * @rst + * +-------+------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+==============================================+ + * | CLA | 0x80 | | + * +-------+------------+----------------------------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t`, in addition to | + * | | | INS_READ, users can set the INS_ATTEST flag. | + * | | | In that case, attestation applies. | + * +-------+------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+----------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+----------------------------------------------+ + * | Lc | #(Payload) | Payload Length. | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_2] | 2-byte offset [Optional: default 0] | + * | | | [Conditional: only when the object is a | + * | | | BinaryFile object] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_3] | 2-byte length [Optional: default 0] | + * | | | [Conditional: only when the object is a | + * | | | BinaryFile object] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_4] | 1-byte :cpp:type:`SE05x_RSAKeyComponent_t`: | + * | | | either RSA_COMP_MOD or RSA_COMP_PUB_EXP. | + * | | | [Optional] [Conditional: only for RSA key | + * | | | components] | + * +-------+------------+----------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_1] | Data read from the secure object. | + * +------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | The read is done successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[in] offset offset [2:kSE05x_TAG_2] + * @param[in] length length [3:kSE05x_TAG_3] + * @param[out] data [0:kSE05x_TAG_1] + * @param[in,out] pdataLen Length for data + */ +smStatus_t Se05x_API_ReadObject( + pSe05xSession_t session_ctx, uint32_t objectID, uint16_t offset, uint16_t length, uint8_t *data, size_t *pdataLen); + +/** Se05x_API_ReadObject_W_Attst + * + * Read with attestation. + * + * See @ref Se05x_API_ReadObject + * + * When INS_ATTEST is set in addition to INS_READ, the secure object is read with + * attestation. In addition to the response in TLV[TAG_1], there are additional + * tags: + * + * TLV[TAG_2] will hold the object attributes (see ObjectAttributes). + * + * TLV[TAG_3] relative timestamp when the object has been retrieved + * + * TLV[TAG_4] will hold freshness random data + * + * TLV[TAG_5] will hold the unique ID of the device. + * + * TLV[TAG_6] will hold the signature over all concatenated Value fields tags of + * the response (TAG_1 until and including TAG_5). + * + * # Command to Applet + * + * @rst + * +-------+------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+==============================================+ + * | CLA | 0x80 | | + * +-------+------------+----------------------------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t`, in addition to | + * | | | INS_READ, users can set the INS_ATTEST flag. | + * | | | In that case, attestation applies. | + * +-------+------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+----------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+----------------------------------------------+ + * | Lc | #(Payload) | Payload Length. | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_2] | 2-byte offset [Optional: default 0] | + * | | | [Conditional: only when the object is a | + * | | | BinaryFile object] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_3] | 2-byte length [Optional: default 0] | + * | | | [Conditional: only when the object is a | + * | | | BinaryFile object] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_4] | 1-byte :cpp:type:`SE05x_RSAKeyComponent_t`: | + * | | | either RSA_COMP_MOD or RSA_COMP_PUB_EXP. | + * | | | [Optional] [Conditional: only for RSA key | + * | | | components] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_5] | 4-byte attestation object identifier. | + * | | | [Optional] [Conditional: only when | + * | | | INS_ATTEST is set] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_6] | 1-byte :cpp:type:`SE05x_AttestationAlgo_t` | + * | | | [Optional] [Conditional: only when | + * | | | INS_ATTEST is set] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_7] | 16-byte freshness random [Optional] | + * | | | [Conditional: only when INS_ATTEST is set] | + * +-------+------------+----------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------+----------------------------------------------+ + * @endrst + * + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_1] | Data read from the secure object. | + * +------------+--------------------------------------------+ + * | TLV[TAG_2] | (only when INS_ATTEST is set) Byte array | + * | | containing the attributes (see | + * | | :cpp:type:`ObjectAttributesRef`). | + * +------------+--------------------------------------------+ + * | TLV[TAG_3] | (only when INS_ATTEST is set) 12-byte | + * | | timestamp | + * +------------+--------------------------------------------+ + * | TLV[TAG_4] | (only when INS_ATTEST is set) 16-byte | + * | | freshness random | + * +------------+--------------------------------------------+ + * | TLV[TAG_5] | (only when INS_ATTEST is set) 18-byte Chip | + * | | unique ID | + * +------------+--------------------------------------------+ + * | TLV[TAG_6] | (only when INS_ATTEST is set) Signature | + * | | applied over the value of TLV[TAG_1], | + * | | TLV[TAG_2], TLV[TAG_3], TLV[TAG_4] and | + * | | TLV[TAG_5]. | + * +------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_1] | Data read from the secure object. | + * +------------+--------------------------------------------+ + * | TLV[TAG_2] | (only when INS_ATTEST is set) Byte array | + * | | containing the attributes (see | + * | | :cpp:type:`ObjectAttributesRef`). | + * +------------+--------------------------------------------+ + * | TLV[TAG_3] | (only when INS_ATTEST is set) 12-byte | + * | | timestamp | + * +------------+--------------------------------------------+ + * | TLV[TAG_4] | (only when INS_ATTEST is set) 16-byte | + * | | freshness random | + * +------------+--------------------------------------------+ + * | TLV[TAG_5] | (only when INS_ATTEST is set) 18-byte Chip | + * | | unique ID | + * +------------+--------------------------------------------+ + * | TLV[TAG_6] | (only when INS_ATTEST is set) Signature | + * | | applied over the value of TLV[TAG_1], | + * | | TLV[TAG_2], TLV[TAG_3], TLV[TAG_4] and | + * | | TLV[TAG_5]. | + * +------------+--------------------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] offset The offset + * @param[in] length The length + * @param[in] attestID The attest id + * @param[in] attestAlgo The attest algorithm + * @param[in] random The random + * @param[in] randomLen The random length + * @param data The data + * @param pdataLen The pdata length + * @param attribute The attribute + * @param pattributeLen The pattribute length + * @param ptimeStamp The ptime stamp + * @param outrandom The outrandom + * @param poutrandomLen The poutrandom length + * @param chipId The chip identifier + * @param pchipIdLen The pchip identifier length + * @param signature The signature + * @param psignatureLen The psignature length + * + * @return The sm status. + */ +smStatus_t Se05x_API_ReadObject_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + uint8_t *attribute, + size_t *pattributeLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ReadRSA + * + * See @ref Se05x_API_ReadObject + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[in] offset offset [2:kSE05x_TAG_2] + * @param[in] length length [3:kSE05x_TAG_3] + * @param[in] rsa_key_comp rsa_key_comp [4:kSE05x_TAG_4] + * @param[out] data [0:kSE05x_TAG_1] + * @param[in,out] pdataLen Length for data + */ +smStatus_t Se05x_API_ReadRSA(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + SE05x_RSAPubKeyComp_t rsa_key_comp, + uint8_t *data, + size_t *pdataLen); + +/** Se05x_API_ReadRSA_W_Attst + * + * See @ref Se05x_API_ReadObject_W_Attst + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] offset The offset + * @param[in] length The length + * @param[in] rsa_key_comp The rsa key component + * @param[in] attestID The attest id + * @param[in] attestAlgo The attest algorithm + * @param[in] random The random + * @param[in] randomLen The random length + * @param data The data + * @param pdataLen The pdata length + * @param attribute The attribute + * @param pattributeLen The pattribute length + * @param ptimeStamp The ptime stamp + * @param outrandom The outrandom + * @param poutrandomLen The poutrandom length + * @param chipId The chip identifier + * @param pchipIdLen The pchip identifier length + * @param signature The signature + * @param psignatureLen The psignature length + * + * @return The sm status. + */ +smStatus_t Se05x_API_ReadRSA_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + SE05x_RSAPubKeyComp_t rsa_key_comp, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + uint8_t *attribute, + size_t *pattributeLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ReadObjectAttributes_W_Attst + * + * Reads the attributes of a Secure Object (without the value of the Secure + * Object). + * + * Each Secure Object has a number of attributes assigned to it. These attributes + * are listed in for Authentication Objects and in for non-Authentication + * Objects. + * + * # Authentication Object attributes + * + * @rst + * +----------------------------------+--------------+------------------------------------------------+ + * | Attribute | Size (bytes) | Description | + * +==================================+==============+================================================+ + * | Object identifier | 4 | See :cpp:type:`identifiersRef` | + * +----------------------------------+--------------+------------------------------------------------+ + * | Object type | 1 | One of SecureObjectType | + * +----------------------------------+--------------+------------------------------------------------+ + * | Authentication attribute | 1 | One of :cpp:type:`SetIndicatorRef` | + * +----------------------------------+--------------+------------------------------------------------+ + * | Object counter | 2 | Number of failed attempts for an | + * | | | authentication object if the Maximum | + * | | | Authentication Attempts has been set. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Authentication object identifier | 4 | "Owner" of the secure object; i.e., the | + * | | | identifier of the session authentication | + * | | | object when the object has been created. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Maximum authentication attempts | 2 | Maximum number of authentication attempts. 0 | + * | | | means unlimited. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Policy | Variable | Policy attached to the object | + * +----------------------------------+--------------+------------------------------------------------+ + * | Origin | 1 | One of :cpp:type:`OriginRef`; indicates the | + * | | | origin of the Secure Object, either | + * | | | externally set, internally generated or trust | + * | | | provisioned by NXP. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Version | 1 | The Secure Object version. Default = 0. See | + * | | | FIPS compliance for details about versioning | + * | | | of Secure Objects. | + * +----------------------------------+--------------+------------------------------------------------+ + * @endrst + * + * # Non-Authentication Objects + * + * @rst + * +----------------------------------+--------------+------------------------------------------------+ + * | Attribute | Size (bytes) | Description | + * +==================================+==============+================================================+ + * | Object identifier | 4 | See Object identifiers | + * +----------------------------------+--------------+------------------------------------------------+ + * | Object type | 1 | One of SecureObjectType | + * +----------------------------------+--------------+------------------------------------------------+ + * | Authentication attribute | 1 | One of :cpp:type:`SetIndicatorRef` | + * +----------------------------------+--------------+------------------------------------------------+ + * | Tag length | 2 | Set to 0x0000, except for AESKey objects: for | + * | | | AESKey objects, this indicates the GMAC | + * | | | length that applies when doing AEAD | + * | | | operations. If the value is set to 0 and AEAD | + * | | | operations are done, the GMAC length shall be | + * | | | 128 bit. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Authentication object identifier | 4 | "Owner" of the secure object; i.e., the | + * | | | identifier of the session authentication | + * | | | object when the object has been created. | + * +----------------------------------+--------------+------------------------------------------------+ + * | RFU | 2 | Set to 0x0000. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Policy | Variable | Policy attached to the object | + * +----------------------------------+--------------+------------------------------------------------+ + * | Origin | 1 | One of :cpp:type:`OriginRef`; indicates the | + * | | | origin of the Secure Object, either | + * | | | externally set, internally generated or trust | + * | | | provisioned by NXP. | + * +----------------------------------+--------------+------------------------------------------------+ + * | Version | 1 | The Secure Object version. Default = 0. See | + * | | | FIPS compliance for details about versioning | + * | | | of Secure Objects. | + * +----------------------------------+--------------+------------------------------------------------+ + * @endrst + * + * + * # Command to Applet + * + * @rst + * +-------+---------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+===============+===============================================+ + * | CLA | 0x80 | | + * +-------+---------------+-----------------------------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t`, in addition to | + * | | | INS_READ, users can set the INS_ATTEST flag. | + * | | | In that case, attestation applies. | + * +-------+---------------+-----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------+-----------------------------------------------+ + * | P2 | P2_ATTRIBUTES | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------+-----------------------------------------------+ + * | Lc | #(Payload) | Payload Length. | + * +-------+---------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +-------+---------------+-----------------------------------------------+ + * | | TLV[TAG_5] | 4-byte attestation object identifier. | + * | | | [Optional] [Conditional: only when | + * | | | INS_ATTEST is set] | + * +-------+---------------+-----------------------------------------------+ + * | | TLV[TAG_6] | 1-byte AttestationAlgo [Optional] | + * | | | [Conditional: only when INS_ATTEST is set] | + * +-------+---------------+-----------------------------------------------+ + * | | TLV[TAG_7] | 16-byte freshness random [Optional] | + * | | | [Conditional: only when INS_ATTEST is set] | + * +-------+---------------+-----------------------------------------------+ + * | Le | 0x00 | | + * +-------+---------------+-----------------------------------------------+ + * @endrst + * + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_2] | Byte array containing the attributes (see | + * | | Object Attributes). | + * +------------+--------------------------------------------+ + * | TLV[TAG_3] | (only when INS_ATTEST is set) 12-byte | + * | | timestamp | + * +------------+--------------------------------------------+ + * | TLV[TAG_4] | (only when INS_ATTEST is set) 16-byte | + * | | freshness random | + * +------------+--------------------------------------------+ + * | TLV[TAG_5] | (only when INS_ATTEST is set) 18-byte Chip | + * | | unique ID | + * +------------+--------------------------------------------+ + * | TLV[TAG_6] | (only when INS_ATTEST is set) Signature | + * | | applied over the value of TLV[TAG_2], | + * | | TLV[TAG_2], TLV[TAG_3], TLV[TAG_4] and | + * | | TLV[TAG_5]. | + * +------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | The read is done successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] attestID The attest id + * @param[in] attestAlgo The attest algorithm + * @param[in] random The random + * @param[in] randomLen The random length + * @param data The data + * @param pdataLen The pdata length + * @param ptimeStamp The ptime stamp + * @param outrandom The outrandom + * @param poutrandomLen The poutrandom length + * @param chipId The chip identifier + * @param pchipIdLen The pchip identifier length + * @param signature The signature + * @param psignatureLen The psignature length + * + * @return The sm status. + */ +smStatus_t Se05x_API_ReadObjectAttributes_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ExportObject + * + * Reads a transient Secure Object from SE05X. + * + * Secure Objects can be serialized so the Secure Object can be represented as a + * byte array. The byte array contains all attributes of the Secure Object, as + * well as the value (including the secret part!) of the object. + * + * The purpose of the serialization is to be able to allow export and import of + * Secure Objects. Serialized Secure Objects can be reconstructed so they can be + * used as a (normal) Secure Object. Any operation like key or file management + * and crypto operation can only be done on a deserialized Secure Object. + * + * Users can export transient Secure Objects to a non-trusted environment (e.g., + * host controller). The object must be AESKey, DESKey, RSAKey or ECCKey. + * + * Exported credentials are always encrypted and MAC'ed. + * + * The following steps are taken: + * + * * The secure element holds a randomly generated persistent + * 256-bit AES cipher and an 128-bit AES CMAC key. Both keys do + * not require user interaction, they are internal to the SE05X . + * + * * A Secure Object that is identified for export is + * serialized. This means the key value as well as all Secure + * Object attributes are stored as byte array (see Object + * attributes for attribute details). + * + * * The serialized Secure Object is encrypted using AES CBC (no + * padding) and using the default IV. + * + * * A CMAC is applied to the serialized Secure Object + metadata + * using the AES CMAC key. + * + * * The byte array is exported. + * + * An object may only be imported into the store if the SecureObject ID and type + * are the same as the exported object. Therefore, it is not possible to import + * if the corresponding object in the applet has been deleted. + * + * NOTES: + * + * * The exported object is not deleted automatically. + * + * * The timestamp has a 100msec granularity, so it is possible to + * export multiple times with the same timestamp. The freshness + * (user input) should avoid duplicate attestation results as the + * user has to provide different freshness input. + * + * # Command to Applet + * + * @rst + * +-------+------------+--------------------------------------------+ + * | Field | Value | Description | + * +=======+============+============================================+ + * | CLA | 0x80 | | + * +-------+------------+--------------------------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t`. | + * +-------+------------+--------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+--------------------------------------------+ + * | P2 | P2_EXPORT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+--------------------------------------------+ + * | Lc | #(Payload) | Payload Length. | + * +-------+------------+--------------------------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier | + * +-------+------------+--------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSAKeyComponent_t` | + * | | | (only applies to Secure Objects of type | + * | | | RSAKey). | + * +-------+------------+--------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------------------+ + * | Value | Description | + * +============+==============================================+ + * | TLV[TAG_1] | Byte array containing exported Secure Object | + * | | data. | + * +------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+----------------------------------------------+ + * | SW | Description | + * +=============+==============================================+ + * | SW_NO_ERROR | The file is created or updated successfully. | + * +-------------+----------------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[in] rsaKeyComp rsaKeyComp [2:kSE05x_TAG_2] + * @param[out] data [0:kSE05x_TAG_1] + * @param[in,out] pdataLen Length for data + */ +smStatus_t Se05x_API_ExportObject(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAKeyComponent_t rsaKeyComp, + uint8_t *data, + size_t *pdataLen); + +/** Se05x_API_ReadType + * + * Get the type of a Secure Object. + * + * # Command to Applet + * + * @rst + * +-------+------------+-----------------------------+ + * | Field | Value | Description | + * +=======+============+=============================+ + * | CLA | 0x80 | | + * +-------+------------+-----------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-----------------------------+ + * | P2 | P2_TYPE | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-----------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-----------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier. | + * +-------+------------+-----------------------------+ + * | Le | 0x00 | | + * +-------+------------+-----------------------------+ + * @endrst + * + + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------+ + * | Value | Description | + * +============+===================================+ + * | TLV[TAG_1] | Type of the Secure Object: one of | + * | | :cpp:type:`SE05x_SecObjTyp_t` | + * +------------+-----------------------------------+ + * | TLV[TAG_2] | :cpp:type:`TransientIndicatorRef` | + * +------------+-----------------------------------+ + * @endrst + * + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param ptype The ptype + * @param pisTransient The pis transient + * @param[in] attestation_type The attestation type + * + * @return The sm status. + */ +smStatus_t Se05x_API_ReadType(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_SecureObjectType_t *ptype, + uint8_t *pisTransient, + const SE05x_AttestationType_t attestation_type); + +/** Se05x_API_ReadSize + * + * ReadSize + * + * Get the size of a Secure Object (in bytes): + * + * * For EC keys: the size of the curve is returned. + * + * * For RSA keys: the key size is returned. + * + * * For AES/DES/HMAC keys, the key size is returned. + * + * * For binary files: the file size is returned + * + * * For userIDs: nothing is returned (SW_CONDITIONS_NOT_SATISFIED). + * + * * For counters: the counter length is returned. + * + * * For PCR: the PCR length is returned. + * + * # Command to Applet + * + * @rst + * +-------+------------+-----------------------------+ + * | Field | Value | Description | + * +=======+============+=============================+ + * | CLA | 0x80 | | + * +-------+------------+-----------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-----------------------------+ + * | P2 | P2_SIZE | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-----------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-----------------------------+ + * | | TLV[TAG_1] | 4-byte object identifier. | + * +-------+------------+-----------------------------+ + * | Le | 0x00 | | + * +-------+------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------+ + * | Value | Description | + * +============+=============================+ + * | TLV[TAG_1] | Byte array containing size. | + * +------------+-----------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param psize The psize + * + * @return The sm status. + */ +smStatus_t Se05x_API_ReadSize(pSe05xSession_t session_ctx, uint32_t objectID, uint16_t *psize); + +/** Se05x_API_ReadIDList + * + * Get a list of present Secure Object identifiers. + * + * The offset in TAG_1 is an 0-based offset in the list of object. As the user + * does not know how many objects would be returned, the offset needs to be based + * on the return values from the previous ReadIDList. If the applet only returns + * a part of the result, it will indicate that more identifiers are available (by + * setting TLV[TAG_1] in the response to 0x01). The user can then retrieve the + * next chunk of identifiers by calling ReadIDList with an offset that equals the + * amount of identifiers listed in the previous response. + * + * _Example 1:_ first ReadIDList command TAG_1=0, response TAG_1=0, + * TAG_2=complete list + * + * _Example 2:_ first ReadIDList command TAG_1=0, response TAG_1=1, TAG_2=first + * chunk (m entries) second ReadIDList command TAG_1=m, response TAG_1=1, + * TAG_2=second chunk (n entries) thirst ReadIDList command TAG_1=(m+n), response + * TAG_1=0, TAG_2=third last chunk + * + * # Command to Applet + * + * @rst + * +-------+------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+===============================================+ + * | CLA | 0x80 | | + * +-------+------------+-----------------------------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-----------------------------------------------+ + * | P2 | P2_LIST | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 2-byte offset | + * +-------+------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte type filter: 1 byte from | + * | | | :cpp:type:`SE05x_SecObjTyp_t` or 0xFF for all | + * | | | types. | + * +-------+------------+-----------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------------------------------------+ + * | Value | Description | + * +============+===========================================+ + * | TLV[TAG_1] | 1-byte :cpp:type:`MoreIndicatorRef` | + * +------------+-------------------------------------------+ + * | TLV[TAG_2] | Byte array containing 4-byte identifiers. | + * +------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] outputOffset output offset [1:kSE05x_TAG_1] + * @param[in] filter filter [2:kSE05x_TAG_2] + * @param[out] pmore If more ids are present [0:kSE05x_TAG_1] + * @param[out] idlist Byte array containing 4-byte identifiers [1:kSE05x_TAG_2] + * @param[in,out] pidlistLen Length for idlist + */ +smStatus_t Se05x_API_ReadIDList(pSe05xSession_t session_ctx, + uint16_t outputOffset, + uint8_t filter, + uint8_t *pmore, + uint8_t *idlist, + size_t *pidlistLen); + +/** Se05x_API_CheckObjectExists + * + * + * Check if a Secure Object with a certain identifier exists or not. + * + * # Command to Applet + * + * @rst + * +-------+------------+-------------------------------------------+ + * | Field | Value | Description | + * +=======+============+===========================================+ + * | CLA | 0x80 | | + * +-------+------------+-------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-------------------------------------------+ + * | P2 | P2_EXIST | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-------------------------------------------+ + * | | TLV[TAG_1] | 4-byte existing Secure Object identifier. | + * +-------+------------+-------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------+ + * | Value | Description | + * +============+===================================+ + * | TLV[TAG_1] | 1-byte :cpp:type:`SE05x_Result_t` | + * +------------+-----------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[out] presult [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_CheckObjectExists(pSe05xSession_t session_ctx, uint32_t objectID, SE05x_Result_t *presult); + +/** Se05x_API_DeleteSecureObject + * + * Deletes a Secure Object. + * + * If the object origin = ORIGIN_PROVISIONED, an error will be returned and the + * object is not deleted. + * + * + * # Command to Applet + * + * @rst + * +-------+------------------+-------------------------------------------+ + * | Field | Value | Description | + * +=======+==================+===========================================+ + * | CLA | 0x80 | | + * +-------+------------------+-------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------------+-------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------+-------------------------------------------+ + * | P2 | P2_DELETE_OBJECT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------+-------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------+-------------------------------------------+ + * | | TLV[TAG_1] | 4-byte existing Secure Object identifier. | + * +-------+------------------+-------------------------------------------+ + * | Le | - | | + * +-------+------------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+----------------------------------------------+ + * | SW | Description | + * +=============+==============================================+ + * | SW_NO_ERROR | The file is created or updated successfully. | + * +-------------+----------------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_DeleteSecureObject(pSe05xSession_t session_ctx, uint32_t objectID); + +/** Se05x_API_CreateECCurve + * + * Create an EC curve listed in ECCurve. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+-------------------------------+ + * | Field | Value | Description | + * +=======+============+===============================+ + * | CLA | 0x80 | | + * +-------+------------+-------------------------------+ + * | INS | INS_WRITE | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-------------------------------+ + * | P1 | P1_CURVE | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-------------------------------+ + * | P2 | P2_CREATE | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-------------------------------+ + * | | TLV[TAG_1] | 1-byte curve identifier (from | + * | | | :cpp:type:`SE05x_ECCurve_t`). | + * +-------+------------+-------------------------------+ + * | Le | | | + * +-------+------------+-------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] curveID curve id [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_CreateECCurve(pSe05xSession_t session_ctx, SE05x_ECCurve_t curveID); + +/** Se05x_API_SetECCurveParam + * + * Set a curve parameter. The curve must have been created first by + * CreateEcCurve. + * + * All parameters must match the expected value for the listed curves. If the + * curve parameters are not correct, the curve cannot be used. + * + * Users have to set all 5 curve parameters for the curve to be usable. Once all + * curve parameters are given, the secure element will check if all parameters + * are correct and return SW_NO_ERROR.. + * + * # Command to Applet + * + * @rst + * +-------+------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+==============================================+ + * | CLA | 0x80 | | + * +-------+------------+----------------------------------------------+ + * | INS | INS_WRITE | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+----------------------------------------------+ + * | P1 | P1_CURVE | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+----------------------------------------------+ + * | P2 | P2_PARAM | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_1] | 1-byte curve identifier, from | + * | | | :cpp:type:`SE05x_ECCurve_t` | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_ECCurveParam_t` | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_3] | Bytestring containing curve parameter value. | + * +-------+------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] curveID curve id [1:kSE05x_TAG_1] + * @param[in] ecCurveParam ecCurveParam [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + */ +smStatus_t Se05x_API_SetECCurveParam(pSe05xSession_t session_ctx, + SE05x_ECCurve_t curveID, + SE05x_ECCurveParam_t ecCurveParam, + const uint8_t *inputData, + size_t inputDataLen); + +/** Se05x_API_GetECCurveId + * + * Get the curve associated with an EC key. + * + * + * # Command to Applet + * + * @rst + * +---------+------------+-----------------------------+ + * | Field | Value | Description | + * +=========+============+=============================+ + * | CLA | 0x80 | | + * +---------+------------+-----------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +---------+------------+-----------------------------+ + * | P1 | P1_CURVE | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+-----------------------------+ + * | P2 | P2_ID | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+-----------------------------+ + * | Lc | #(Payload) | | + * +---------+------------+-----------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier | + * +---------+------------+-----------------------------+ + * | Le | 0x00 | | + * +---------+------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------------------------+ + * | Value | Description | + * +============+===============================+ + * | TLV[TAG_1] | 1-byte curve identifier (from | + * | | :cpp:type:`SE05x_ECCurve_t`) | + * +------------+-------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID object id [1:kSE05x_TAG_1] + * @param[out] pcurveId [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_GetECCurveId(pSe05xSession_t session_ctx, uint32_t objectID, uint8_t *pcurveId); + +/** Se05x_API_ReadECCurveList + * + * Get a list of (Weierstrass) EC curves that are instantiated. + * + * + * # Command to Applet + * + * @rst + * +-------+----------+-----------------------------+ + * | Field | Value | Description | + * +=======+==========+=============================+ + * | CLA | 0x80 | | + * +-------+----------+-----------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +-------+----------+-----------------------------+ + * | P1 | P1_CURVE | See :cpp:type:`SE05x_P1_t` | + * +-------+----------+-----------------------------+ + * | P2 | P2_LIST | See :cpp:type:`SE05x_P2_t` | + * +-------+----------+-----------------------------+ + * | Le | 0x00 | | + * +-------+----------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | Byte array listing all curve identifiers in | + * | | :cpp:type:`SE05x_ECCurve_t` (excluding UNUSED) | + * | | where the curve identifier < 0x40; for each | + * | | curve, a 1-byte :cpp:type:`SetIndicatorRef` is | + * | | returned. | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[out] curveList [0:kSE05x_TAG_1] + * @param[in,out] pcurveListLen Length for curveList + */ +smStatus_t Se05x_API_ReadECCurveList(pSe05xSession_t session_ctx, uint8_t *curveList, size_t *pcurveListLen); + +/** Se05x_API_DeleteECCurve + * + * Deletes an EC curve. + * + * # Command to Applet + * + * @rst + * +-------+------------------+-------------------------------+ + * | Field | Value | Description | + * +=======+==================+===============================+ + * | CLA | 0x80 | | + * +-------+------------------+-------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------------+-------------------------------+ + * | P1 | P1_CURVE | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------+-------------------------------+ + * | P2 | P2_DELETE_OBJECT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------+-------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------+-------------------------------+ + * | | TLV[TAG_1] | 1-byte curve identifier (from | + * | | | :cpp:type:`SE05x_ECCurve_t`) | + * +-------+------------------+-------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] curveID curve id [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_DeleteECCurve(pSe05xSession_t session_ctx, SE05x_ECCurve_t curveID); + +/** Se05x_API_CreateCryptoObject + * + * Creates a Crypto Object on the SE05X . Once the Crypto Object is created, it + * is bound to the user who created the Crypto Object. + * + * A CryptoObject is a 2-byte value consisting of a CryptoContext in MSB and one + * of the following in LSB: + * + * * DigestMode in case CryptoContext = CC_DIGEST + * + * * CipherMode in case CryptoContext = CC_CIPHER + * + * * MACAlgo in case CryptoContext = CC_SIGNATURE + * + * * AEADMode in case CryptoContext = CC_AEAD + * + * # Command to Applet + * + * @rst + * +---------+---------------+-------------------------------------------+ + * | Field | Value | Description | + * +=========+===============+===========================================+ + * | CLA | 0x80 | | + * +---------+---------------+-------------------------------------------+ + * | INS | INS_WRITE | See :cpp:type:`SE05x_INS_t` | + * +---------+---------------+-------------------------------------------+ + * | P1 | P1_CRYPTO_OBJ | See :cpp:type:`SE05x_P1_t` | + * +---------+---------------+-------------------------------------------+ + * | P2 | P2_DEFAULT | See :cpp:type:`SE05x_P2_t` | + * +---------+---------------+-------------------------------------------+ + * | Lc | #(Payload) | Payload length | + * +---------+---------------+-------------------------------------------+ + * | Payload | TLV[TAG_1] | 2-byte Crypto Object identifier | + * +---------+---------------+-------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_CryptoObject_t` | + * +---------+---------------+-------------------------------------------+ + * | | TLV[TAG_3] | 1-byte Crypto Object subtype, either from | + * | | | :cpp:type:`DigestModeRef`, CipherMode, | + * | | | MACAlgo (depending on TAG_2) or AEADMode. | + * +---------+---------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+----------------------------------------------+ + * | SW | Description | + * +=============+==============================================+ + * | SW_NO_ERROR | The file is created or updated successfully. | + * +-------------+----------------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_1] + * @param[in] cryptoContext cryptoContext [2:kSE05x_TAG_2] + * + * @param[in] subtype 1-byte Crypto Object subtype, either from + * DigestMode, CipherMode or MACAlgo (depending on + * TAG_2). [3:kSE05x_TAG_3] + */ +smStatus_t Se05x_API_CreateCryptoObject(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + SE05x_CryptoContext_t cryptoContext, + SE05x_CryptoModeSubType_t subtype); + +/** Se05x_API_ReadCryptoObjectList + * + * Get the list of allocated Crypto Objects indicating the identifier, the + * CryptoContext and the sub type of the CryptoContext. + * + * # Command to Applet + * + * @rst + * +-------+---------------+-----------------------------+ + * | Field | Value | Description | + * +=======+===============+=============================+ + * | CLA | 0x80 | | + * +-------+---------------+-----------------------------+ + * | INS | INS_READ | See :cpp:type:`SE05x_INS_t` | + * +-------+---------------+-----------------------------+ + * | P1 | P1_CRYPTO_OBJ | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------+-----------------------------+ + * | P2 | P2_LIST | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------+-----------------------------+ + * | Le | 0x00 | | + * +-------+---------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------------------+ + * | Value | Description | + * +============+===============================================+ + * | TLV[TAG_1] | Byte array containing a list of 2-byte Crypto | + * | | Object identifiers, followed by 1-byte | + * | | CryptoContext and 1-byte subtype for each | + * | | Crypto Object (so 4 bytes for each Crypto | + * | | Object). | + * +------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[out] idlist If more ids are present [0:kSE05x_TAG_1] + * @param[in,out] pidlistLen Length for idlist + */ +smStatus_t Se05x_API_ReadCryptoObjectList(pSe05xSession_t session_ctx, uint8_t *idlist, size_t *pidlistLen); + +/** Se05x_API_DeleteCryptoObject + * + * Deletes a Crypto Object on the SE05X . + * + * Note: when a Crypto Object is deleted, the memory (as mentioned in ) is de- + * allocated, but the transient memory is only freed when de-selecting the + * applet! + * + * # Command to Applet + * + * @rst + * +---------+------------------+---------------------------------+ + * | Field | Value | Description | + * +=========+==================+=================================+ + * | CLA | 0x80 | | + * +---------+------------------+---------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +---------+------------------+---------------------------------+ + * | P1 | P1_CRYPTO_OBJ | See :cpp:type:`SE05x_P1_t` | + * +---------+------------------+---------------------------------+ + * | P2 | P2_DELETE_OBJECT | See :cpp:type:`SE05x_P2_t` | + * +---------+------------------+---------------------------------+ + * | Lc | #(Payload) | Payload length | + * +---------+------------------+---------------------------------+ + * | Payload | TLV[TAG_1] | 2-byte Crypto Object identifier | + * +---------+------------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+----------------------------------------------+ + * | SW | Description | + * +=============+==============================================+ + * | SW_NO_ERROR | The file is created or updated successfully. | + * +-------------+----------------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_DeleteCryptoObject(pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID); + +/** Se05x_API_ECDSASign + * + * The ECDSASign command signs external data using the indicated key pair or + * private key. + * + * The ECSignatureAlgo indicates the ECDSA algorithm that is used, but the + * hashing of data always must be done on the host. E.g., if ECSignatureAlgo = + * SIG_ ECDSA_SHA256, the user must have applied SHA256 on the input data + * already. + * + * The user must take care of providing the correct input length; i.e., the data + * input length (TLV[TAG_3]) must match the digest indicated in the signature + * algorithm (TLV[TAG_2]). + * + * In any case, the APDU payload must be smaller than MAX_APDU_PAYLOAD_LENGTH. + * + * This is performed according to the ECDSA algorithm as specified in [ANSI + * X9.62]. The signature (a sequence of two integers 'r' and 's') as + * returned in the response adheres to the ASN.1 DER encoded formatting rules for + * integers. + * + * # Command to Applet + * + * @rst + * +-------+--------------+---------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+=============================================+ + * | CLA | 0x80 | | + * +-------+--------------+---------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+---------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+---------------------------------------------+ + * | P2 | P2_SIGN | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+---------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of EC key pair or private | + * | | | key. | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_2] | 1-byte ECSignatureAlgo. | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data. | + * +-------+--------------+---------------------------------------------+ + * | Le | 0x00 | Expecting ASN.1 signature | + * +-------+--------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------+ + * | Value | Description | + * +============+==================================+ + * | TLV[TAG_1] | ECDSA Signature in ASN.1 format. | + * +------------+----------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] ecSignAlgo ecSignAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] signature [0:kSE05x_TAG_1] + * @param[in,out] psignatureLen Length for signature + */ +smStatus_t Se05x_API_ECDSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECSignatureAlgo_t ecSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_EdDSASign + * + * The EdDSASign command signs external data using the indicated key pair or + * private key (using a Twisted Edwards curve). This is performed according to + * the EdDSA algorithm as specified in [RFC8032]. + * + * The input data need to be the plain data (not hashed). + * + * The signature as returned in the response is a 64-byte array, being the + * concatenation of the signature r and s component (without leading zeroes for + * sign indication). + * + * # Command to Applet + * + * @rst + * +-------+--------------+---------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+=============================================+ + * | CLA | 0x80 | | + * +-------+--------------+---------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+---------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+---------------------------------------------+ + * | P2 | P2_SIGN | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+---------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of EC key pair or private | + * | | | key. | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_2] | 1-byte EDSignatureAlgo | + * +-------+--------------+---------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing plain input data. | + * +-------+--------------+---------------------------------------------+ + * | Le | 0x00 | Expecting signature | + * +-------+--------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------+ + * | Value | Description | + * +============+==========================================+ + * | TLV[TAG_1] | EdDSA Signature (r concatenated with s). | + * +------------+------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] edSignAlgo edSignAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] signature [0:kSE05x_TAG_1] + * @param[in,out] psignatureLen Length for signature + */ +smStatus_t Se05x_API_EdDSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_EDSignatureAlgo_t edSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ECDAASign + * + * The ECDAASign command signs external data using the indicated key pair or + * private key. This is performed according to ECDAA. The generated signature is: + * + * * r = random mod n + * + * * s = (r + T.ds) mod n where d is the private key + * + * The ECDAASignatureAlgo indicates the applied algorithm. + * + * This APDU command should be used with a key identifier linked to + * TPM_ECC_BN_P256 curve. + * + * _Note:_ The applet allows the random input to be 32 bytes of zeroes; the user + * must take care that this is not considered as valid input. Only input in the + * interval [1, n-1] must be considered as valid. + * + * # Command to Applet + * + * @rst + * +-------+--------------+------------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+================================================+ + * | CLA | 0x80 | | + * +-------+--------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+------------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+------------------------------------------------+ + * | P2 | P2_SIGN | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of EC key pair or private | + * | | | key. | + * +-------+--------------+------------------------------------------------+ + * | | TLV[TAG_2] | 1-byte ECDAASignatureAlgo | + * +-------+--------------+------------------------------------------------+ + * | | TLV[TAG_3] | T = 32-byte array containing hashed input | + * | | | data. | + * +-------+--------------+------------------------------------------------+ + * | | TLV[TAG_4] | r = 32-byte array containing random data, must | + * | | | be in the interval [1, n-1] where n is the | + * | | | order of the curve. | + * +-------+--------------+------------------------------------------------+ + * | Le | 0x00 | Expecting signature | + * +-------+--------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------+ + * | Value | Description | + * +============+==========================================+ + * | TLV[TAG_1] | ECDSA Signature (r concatenated with s). | + * +------------+------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] ecdaaSignAlgo ecdaaSignAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[in] randomData randomData [4:kSE05x_TAG_4] + * @param[in] randomDataLen Length of randomData + * @param[out] signature [0:kSE05x_TAG_1] + * @param[in,out] psignatureLen Length for signature + */ +smStatus_t Se05x_API_ECDAASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECDAASignatureAlgo_t ecdaaSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *randomData, + size_t randomDataLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_ECDSAVerify + * + * The ECDSAVerify command verifies whether the signature is correct for a given + * (hashed) data input using an EC public key or EC key pair's public key. + * + * The ECSignatureAlgo indicates the ECDSA algorithm that is used, but the + * hashing of data must always be done on the host. E.g., if ECSignatureAlgo = + * SIG_ ECDSA_SHA256, the user must have applied SHA256 on the input data + * already. + * + * The key cannot be passed externally to the command directly. In case users + * want to use the command to verify signatures using different public keys or + * the public key value regularly changes, the user should create a transient key + * object to which the key value is written and then the identifier of that + * transient secure object can be used by this ECDSAVerify command. + * + * # Command to Applet + * + * @rst + * +-------+--------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+===============================================+ + * | CLA | 0x80 | | + * +-------+--------------+-----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+-----------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+-----------------------------------------------+ + * | P2 | P2_VERIFY | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+-----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of the key pair or public | + * | | | key. | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte ECSignatureAlgo. | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing ASN.1 signature | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing hashed data to compare. | + * +-------+--------------+-----------------------------------------------+ + * | Le | 0x03 | Expecting TLV with :cpp:type:`SE05x_Result_t` | + * +-------+--------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------+ + * | Value | Description | + * +============+======================================+ + * | TLV[TAG_1] | Result of the signature verification | + * | | (:cpp:type:`SE05x_Result_t`). | + * +------------+--------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-----------------------------+--------------------------------------+ + * | SW | Description | + * +=============================+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-----------------------------+--------------------------------------+ + * | SW_CONDITIONS_NOT_SATISFIED | Incorrect data | + * +-----------------------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] ecSignAlgo ecSignAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[in] signature signature [4:kSE05x_TAG_5] + * @param[in] signatureLen Length of signature + * @param[out] presult [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_ECDSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECSignatureAlgo_t ecSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult); + +/** Se05x_API_EdDSAVerify + * + * The EdDSAVerify command verifies whether the signature is correct for a given + * data input (hashed using SHA512) using an EC public key or EC key pair's + * public key. The signature needs to be given as concatenation of r and s. + * + * The data needs to be compared with the plain message without being hashed. + * + * _Note_ : See chapter 7 for correct byte order as both r and s need to be byte + * swapped. + * + * This is performed according to the EdDSA algorithm as specified in [RFC8032]. + * + * The key cannot be passed externally to the command directly. In case users + * want to use the command to verify signatures using different public keys or + * the public key value regularly changes, the user should create a transient key + * object to which the key value is written and then the identifier of that + * transient secure object can be used by this EdDSAVerify command. + * + * # Command to Applet + * + * @rst + * +-------+--------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+===============================================+ + * | CLA | 0x80 | | + * +-------+--------------+-----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+-----------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+-----------------------------------------------+ + * | P2 | P2_VERIFY | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+-----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of the key pair or public | + * | | | key. | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`EDSignatureAlgoRef`. | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_3] | 64-byte array containing the signature | + * | | | (concatenation of r and s). | + * +-------+--------------+-----------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing plain data to compare. | + * +-------+--------------+-----------------------------------------------+ + * | Le | 0x03 | Expecting TLV with :cpp:type:`SE05x_Result_t` | + * +-------+--------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------+ + * | Value | Description | + * +============+======================================+ + * | TLV[TAG_1] | Result of the signature verification | + * | | (:cpp:type:`SE05x_Result_t`). | + * +------------+--------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-----------------------------+--------------------------------------+ + * | SW | Description | + * +=============================+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-----------------------------+--------------------------------------+ + * | SW_CONDITIONS_NOT_SATISFIED | Incorrect data | + * +-----------------------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] edSignAlgo edSignAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[in] signature signature [4:kSE05x_TAG_5] + * @param[in] signatureLen Length of signature + * @param[out] presult [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_EdDSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_EDSignatureAlgo_t edSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult); + +/** Se05x_API_ECDHGenerateSharedSecret + * + * The ECDHGenerateSharedSecret command generates a shared secret ECC point on + * the curve using an EC private key on SE05X and an external public key provided + * by the caller. The output shared secret is returned to the caller. + * + * All curves from ECCurve are supported, except ECC_ED_25519. + * + * Note that ECDHGenerateSharedSecret commands with EC keys using curve + * ID_ECC_MONT_DH_25519 or ID_ECC_MONT_DH_448 cause NVM write operations for each + * call. This is not the case for the other curves. + * + * When CONFIG_FIPS_MODE_DISABLED is not set, this function will always return + * SW_CONDTIONS_NOT_SATISFIED. + * + * The shared secret can only be received when the Secure Object containing the + * key pair or private key (TLV[TAG_1]) does not contain the policy + * POLICY_OBJ_FORBID_DERIVED_OUTPUT. If that is the case, the user must provide + * TLV[TAG_7} to store the shared secret in an HMACKey object. The user is + * responsible to assign the correct size of the HMACKey object: this must equal + * the size of the shared secret exactly. + * + * On applet 4.4.0, the policy POLICY_OBJ_FORBID_DERIVED_OUTPUT is not yet + * verified for this function. It will always be allowed. + * + * # Command to Applet + * + * @rst + * +------------+------------------------------+----------------------------------------------+ + * | Field | Value | Description | + * +============+==============================+==============================================+ + * | CLA | 0x80 | | + * +------------+------------------------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+------------------------------+----------------------------------------------+ + * | P1 | P1_EC | See :cpp:type:`SE05x_P1_t` | + * +------------+------------------------------+----------------------------------------------+ + * | P2 | P2_DH | See :cpp:type:`SE05x_P2_t` | + * +------------+------------------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +------------+------------------------------+----------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key pair or private | + * | | | key. | + * +------------+------------------------------+----------------------------------------------+ + * | TLV[TAG_2] | External public key (see | | + * | | :cpp:type:`ECKeyRef`). | | + * +------------+------------------------------+----------------------------------------------+ + * | TLV[TAG_7] | 4-byte HMACKey identifier to | | + * | | store output. [Optional] | | + * +------------+------------------------------+----------------------------------------------+ + * | Le | 0x00 | Expected shared secret length. | + * +------------+------------------------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------------------+ + * | Value | Description | + * +============+==============================================+ + * | TLV[TAG_1] | The returned shared secret. [Conditional: | + * | | only when the input does not contain | + * | | TLV[TAG_7].} | + * +------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] pubKey pubKey [2:kSE05x_TAG_2] + * @param[in] pubKeyLen Length of pubKey + * @param[out] sharedSecret [0:kSE05x_TAG_1] + * @param[in,out] psharedSecretLen Length for sharedSecret + */ +smStatus_t Se05x_API_ECDHGenerateSharedSecret(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *pubKey, + size_t pubKeyLen, + uint8_t *sharedSecret, + size_t *psharedSecretLen); + +/** Se05x_API_RSASign + * + * The RSASign command signs the input message using an RSA private key. + * + * @rst + * +----------------------+-------+----------------------------+ + * | Name | Value | Description | + * +======================+=======+============================+ + * | RSA_SHA1_PKCS1_PSS | 0x15 | RFC8017: RSASSA-PSS | + * +----------------------+-------+----------------------------+ + * | RSA_SHA224_PKCS1_PSS | 0x2B | RFC8017: RSASSA-PSS | + * +----------------------+-------+----------------------------+ + * | RSA_SHA256_PKCS1_PSS | 0x2C | RFC8017: RSASSA-PSS | + * +----------------------+-------+----------------------------+ + * | RSA_SHA384_PKCS1_PSS | 0x2D | RFC8017: RSASSA-PSS | + * +----------------------+-------+----------------------------+ + * | RSA_SHA512_PKCS1_PSS | 0x2E | RFC8017: RSASSA-PSS | + * +----------------------+-------+----------------------------+ + * | RSA_SHA1_PKCS1 | 0x0A | RFC8017: RSASSA-PKCS1-v1_5 | + * +----------------------+-------+----------------------------+ + * | RSA_SHA_224_PKCS1 | 0x27 | RFC8017: RSASSA-PKCS1-v1_5 | + * +----------------------+-------+----------------------------+ + * | RSA_SHA_256_PKCS1 | 0x28 | RFC8017: RSASSA-PKCS1-v1_5 | + * +----------------------+-------+----------------------------+ + * | RSA_SHA_384_PKCS1 | 0x29 | RFC8017: RSASSA-PKCS1-v1_5 | + * +----------------------+-------+----------------------------+ + * | RSA_SHA_512_PKCS1 | 0x2A | RFC8017: RSASSA-PKCS1-v1_5 | + * +----------------------+-------+----------------------------+ + * @endrst + * + * # Command to Applet + * + * @rst + * +-------+--------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+==============================================+ + * | CLA | 0x80 | | + * +-------+--------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+----------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+----------------------------------------------+ + * | P2 | P2_SIGN | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of the key pair or private | + * | | | key. | + * +-------+--------------+----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSASignAlgo_t` | + * +-------+--------------+----------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data. | + * +-------+--------------+----------------------------------------------+ + * | Le | 0x00 | Expecting ASN.1 signature. | + * +-------+--------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------+ + * | Value | Description | + * +============+================================+ + * | TLV[TAG_1] | RSA signature in ASN.1 format. | + * +------------+--------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] rsaSigningAlgo rsaSigningAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] signature [0:kSE05x_TAG_1] + * @param[in,out] psignatureLen Length for signature + */ +smStatus_t Se05x_API_RSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSASignatureAlgo_t rsaSigningAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen); + +/** Se05x_API_RSAVerify + * + * The RSAVerify command verifies the given signature and returns the result. + * + * The key cannot be passed externally to the command directly. In case users + * want to use the command to verify signatures using different public keys or + * the public key value regularly changes, the user should create a transient key + * object to which the key value is written and then the identifier of that + * transient secure object can be used by this RSAVerify command. + * + * # Command to Applet + * + * @rst + * +---------+--------------+---------------------------------------------+ + * | Field | Value | Description | + * +=========+==============+=============================================+ + * | CLA | 0x80 | | + * +---------+--------------+---------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+--------------+---------------------------------------------+ + * | P1 | P1_SIGNATURE | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------+---------------------------------------------+ + * | P2 | P2_VERIFY | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------+---------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------+---------------------------------------------+ + * | Payload | | | + * +---------+--------------+---------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of the key pair or public | + * | | | key. | + * +---------+--------------+---------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSASignAlgo_t` | + * +---------+--------------+---------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing data to be verified. | + * +---------+--------------+---------------------------------------------+ + * | | TLV[TAG_5] | Byte array containing ASN.1 signature. | + * +---------+--------------+---------------------------------------------+ + * | Le | 0x03 | Expecting Result in TLV | + * +---------+--------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------+ + * | Value | Description | + * +============+==========================================+ + * | TLV[TAG_1] | :cpp:type:`SE05x_Result_t`: Verification | + * | | result | + * +------------+------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] rsaSigningAlgo rsaSigningAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[in] signature signature [4:kSE05x_TAG_5] + * @param[in] signatureLen Length of signature + * @param[out] presult [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_RSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSASignatureAlgo_t rsaSigningAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult); + +/** Se05x_API_RSAEncrypt + * + * The RSAEncrypt command encrypts data. + * + * # Command to Applet + * + * @rst + * +---------+--------------------+----------------------------------------------+ + * | Field | Value | Description | + * +=========+====================+==============================================+ + * | CLA | 0x80 | | + * +---------+--------------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+--------------------+----------------------------------------------+ + * | P1 | P1_RSA | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------------+----------------------------------------------+ + * | P2 | P2_ENCRYPT_ONESHOT | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------------+----------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key pair or public | + * | | | key. | + * +---------+--------------------+----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSAEncryptionAlgo_t` | + * +---------+--------------------+----------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing data to be encrypted. | + * +---------+--------------------+----------------------------------------------+ + * | Le | 0x00 | Expected TLV with encrypted data. | + * +---------+--------------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------+ + * | Value | Description | + * +============+================+ + * | TLV[TAG_1] | Encrypted data | + * +------------+----------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] rsaEncryptionAlgo rsaEncryptionAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] encryptedData [0:kSE05x_TAG_1] + * @param[in,out] pencryptedDataLen Length for encryptedData + */ +smStatus_t Se05x_API_RSAEncrypt(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *encryptedData, + size_t *pencryptedDataLen); + +/** Se05x_API_RSADecrypt + * + * The RSADecrypt command decrypts data. + * + * + * # Command to Applet + * + * @rst + * +---------+--------------------+----------------------------------------------+ + * | Field | Value | Description | + * +=========+====================+==============================================+ + * | CLA | 0x80 | | + * +---------+--------------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+--------------------+----------------------------------------------+ + * | P1 | P1_RSA | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------------+----------------------------------------------+ + * | P2 | P2_DECRYPT_ONESHOT | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------------+----------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key pair or private | + * | | | key. | + * +---------+--------------------+----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_RSAEncryptionAlgo_t` | + * +---------+--------------------+----------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing data to be decrypted. | + * +---------+--------------------+----------------------------------------------+ + * | Le | 0x00 | Expected TLV with decrypted data. | + * +---------+--------------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------+ + * | Value | Description | + * +============+================+ + * | TLV[TAG_1] | Encrypted data | + * +------------+----------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] rsaEncryptionAlgo rsaEncryptionAlgo [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] decryptedData [0:kSE05x_TAG_1] + * @param[in,out] pdecryptedDataLen Length for decryptedData + */ +smStatus_t Se05x_API_RSADecrypt(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *decryptedData, + size_t *pdecryptedDataLen); + +/** Se05x_API_CipherInit + * + * Initialize a symmetric encryption or decryption. The Crypto Object keeps the + * state of the cipher operation until it's finalized or deleted. Once the + * CipherFinal function is executed successfully, the Crypto Object state returns + * to the state immediately after the previous CipherInit function. + * + * # Command to Applet + * + * @rst + * +---------+--------------------------+--------------------------------------------+ + * | Field | Value | Description | + * +=========+==========================+============================================+ + * | CLA | 0x80 | | + * +---------+--------------------------+--------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+--------------------------+--------------------------------------------+ + * | P1 | P1_CIPHER | See :cpp:type:`SE05x_P1_t` | + * +---------+--------------------------+--------------------------------------------+ + * | P2 | P2_ENCRYPT or P2_DECRYPT | See :cpp:type:`SE05x_P2_t` | + * +---------+--------------------------+--------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+--------------------------+--------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key object. | + * +---------+--------------------------+--------------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+--------------------------+--------------------------------------------+ + * | | TLV[TAG_4] | Initialization Vector [Optional] | + * | | | [Conditional: only when the Crypto Object | + * | | | type equals CC_CIPHER and subtype is not | + * | | | including ECB] | + * +---------+--------------------------+--------------------------------------------+ + * | Le | - | | + * +---------+--------------------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] cryptoObjectID cryptoObjectID [2:kSE05x_TAG_2] + * @param[in] IV IV [3:kSE05x_TAG_4] + * @param[in] IVLen Length of IV + * @param[in] operation See @ref SE05x_Cipher_Oper_t + */ +smStatus_t Se05x_API_CipherInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *IV, + size_t IVLen, + const SE05x_Cipher_Oper_t operation); + +/** Se05x_API_CipherUpdate + * + * Update a cipher context. + * + * + * # Command to Applet + * + * @rst + * +------------+----------------------------------+---------------------------------+ + * | Field | Value | Description | + * +============+==================================+=================================+ + * | CLA | 0x80 | | + * +------------+----------------------------------+---------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+----------------------------------+---------------------------------+ + * | P1 | P1_CIPHER | See :cpp:type:`SE05x_P1_t` | + * +------------+----------------------------------+---------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +------------+----------------------------------+---------------------------------+ + * | Lc | #(Payload) | | + * +------------+----------------------------------+---------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+----------------------------------+---------------------------------+ + * | TLV[TAG_3] | Byte array containing input data | | + * +------------+----------------------------------+---------------------------------+ + * | Le | 0x00 | Expecting returned data. | + * +------------+----------------------------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------+ + * | Value | Description | + * +============+=============+ + * | TLV[TAG_1] | Output data | + * +------------+-------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_2] + * @param[in] inputData inputData [2:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] outputData [0:kSE05x_TAG_1] + * @param[in,out] poutputDataLen Length for outputData + */ +smStatus_t Se05x_API_CipherUpdate(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen); + +/** Se05x_API_CipherFinal + * + * Finish a sequence of cipher operations. + * + * # Command to Applet + * + * @rst + * +------------+------------+---------------------------------+ + * | Field | Value | Description | + * +============+============+=================================+ + * | CLA | 0x80 | | + * +------------+------------+---------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+------------+---------------------------------+ + * | P1 | P1_CIPHER | See :cpp:type:`SE05x_P1_t` | + * +------------+------------+---------------------------------+ + * | P2 | P2_FINAL | See :cpp:type:`SE05x_P2_t` | + * +------------+------------+---------------------------------+ + * | Lc | #(Payload) | | + * +------------+------------+---------------------------------+ + * | Payload | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +------------+------------+---------------------------------+ + * | TLV[TAG_3] | Input data | | + * +------------+------------+---------------------------------+ + * | Le | 0x00 | Expected returned data. | + * +------------+------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------+ + * | Value | Description | + * +============+=============+ + * | TLV[TAG_1] | Output data | + * +------------+-------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_2] + * @param[in] inputData inputData [2:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] outputData [0:kSE05x_TAG_1] + * @param[in,out] poutputDataLen Length for outputData + */ +smStatus_t Se05x_API_CipherFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen); + +/** + * @brief Se05x_API_CipherOneShot + * + * Encrypt or decrypt data in one shot mode. + * + * The key object must be either an AES key or DES key. + * + * # Command to Applet + * + * @rst + * +---------+-----------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=========+=======================+================================================+ + * | CLA | 0x80 | | + * +---------+-----------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+-----------------------+------------------------------------------------+ + * | P1 | P1_CIPHER | See :cpp:type:`SE05x_P1_t` | + * +---------+-----------------------+------------------------------------------------+ + * | P2 | P2_ENCRYPT_ONESHOT or | See :cpp:type:`SE05x_P2_t` | + * | | P2_DECRYPT_ONESHOT | | + * +---------+-----------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+-----------------------+------------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key object. | + * +---------+-----------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 1-byte CipherMode | + * +---------+-----------------------+------------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing input data. | + * +---------+-----------------------+------------------------------------------------+ + * | | TLV[TAG_4] | Byte array containing an initialization | + * | | | vector. [Optional] [Conditional: only when | + * | | | the Crypto Object type equals CC_CIPHER and | + * | | | subtype is not including ECB] | + * +---------+-----------------------+------------------------------------------------+ + * | Le | 0x00 | Expecting return data. | + * +---------+-----------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------+ + * | Value | Description | + * +============+=============+ + * | TLV[TAG_1] | Output data | + * +------------+-------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] cipherMode The cipher mode + * @param[in] inputData The input data + * @param[in] inputDataLen The input data length + * @param[in] IV Initial vector + * @param[in] IVLen The iv length + * @param outputData The output data + * @param poutputDataLen The poutput data length + * @param[in] operation The operation + * + * @return The sm status. + */ +smStatus_t Se05x_API_CipherOneShot(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *IV, + size_t IVLen, + uint8_t *outputData, + size_t *poutputDataLen, + const SE05x_Cipher_Oper_OneShot_t operation); + +/** Se05x_API_MACInit + * + * Initiate a MAC operation. The state of the MAC operation is kept in the Crypto + * Object until it's finalized or deleted. + * + * The 4-byte identifier of the key must refer to an AESKey, DESKey or HMACKey. + * + * + * # Command to Applet + * + * @rst + * +---------+----------------------------+-----------------------------------+ + * | Field | Value | Description | + * +=========+============================+===================================+ + * | CLA | 0x80 | | + * +---------+----------------------------+-----------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+----------------------------+-----------------------------------+ + * | P1 | P1_MAC | See :cpp:type:`SE05x_P1_t` | + * +---------+----------------------------+-----------------------------------+ + * | P2 | P2_GENERATE or P2_VALIDATE | See :cpp:type:`SE05x_P2_t` | + * +---------+----------------------------+-----------------------------------+ + * | Lc | #(Payload) | | + * +---------+----------------------------+-----------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the MAC key. | + * +---------+----------------------------+-----------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+----------------------------+-----------------------------------+ + * | Le | 0x00 | | + * +---------+----------------------------+-----------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] cryptoObjectID cryptoObjectID [2:kSE05x_TAG_2] + * @param[in] mac_oper The Operation + */ +smStatus_t Se05x_API_MACInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const SE05x_Mac_Oper_t mac_oper); + +/** Se05x_API_MACUpdate + * + * Update MAC + * + * # Command to Applet + * + * @rst + * +---------+------------+-------------------------------------------+ + * | Field | Value | Description | + * +=========+============+===========================================+ + * | CLA | 0x80 | | + * +---------+------------+-------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+------------+-------------------------------------------+ + * | P1 | P1_MAC | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+-------------------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+-------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+------------+-------------------------------------------+ + * | Payload | TLV[TAG_1] | Byte array containing data to be taken as | + * | | | input to MAC. | + * +---------+------------+-------------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+------------+-------------------------------------------+ + * | Le | - | | + * +---------+------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] inputData inputData [1:kSE05x_TAG_1] + * @param[in] inputDataLen Length of inputData + * @param[in] cryptoObjectID cryptoObjectID [2:kSE05x_TAG_2] + */ +smStatus_t Se05x_API_MACUpdate( + pSe05xSession_t session_ctx, const uint8_t *inputData, size_t inputDataLen, SE05x_CryptoObjectID_t cryptoObjectID); + +/** Se05x_API_MACFinal + * + * # Command to Applet + * + * @rst + * +---------+------------+--------------------------------------------+ + * | Field | Value | Description | + * +=========+============+============================================+ + * | CLA | 0x80 | | + * +---------+------------+--------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+------------+--------------------------------------------+ + * | P1 | P1_MAC | See :cpp:type:`SE05x_P1_t` | + * +---------+------------+--------------------------------------------+ + * | P2 | P2_FINAL | See :cpp:type:`SE05x_P2_t` | + * +---------+------------+--------------------------------------------+ + * | Payload | TLV[TAG_1] | Byte array containing data to be taken as | + * | | | input to MAC. | + * +---------+------------+--------------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +---------+------------+--------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing MAC to validate. | + * | | | [Conditional: only applicable the crypto | + * | | | object is set for validating (MACInit P2 = | + * | | | P2_VALIDATE)] | + * +---------+------------+--------------------------------------------+ + * | Le | 0x00 | Expecting MAC or result. | + * +---------+------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------------------+ + * | Value | Description | + * +============+===============================================+ + * | TLV[TAG_1] | MAC value (when MACInit had P2 = P2_GENERATE) | + * | | or :cpp:type:`SE05x_Result_t` (when MACInit | + * | | had P2 = P2_VERIFY). | + * +------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] inputData inputData [1:kSE05x_TAG_1] + * @param[in] inputDataLen Length of inputData + * @param[in] cryptoObjectID cryptoObjectID [2:kSE05x_TAG_2] + * @param[in] macValidateData macValidateData [3:kSE05x_TAG_3] + * @param[in] macValidateDataLen Length of macValidateData + * @param[out] macValue [0:kSE05x_TAG_1] + * @param[in,out] pmacValueLen Length for macValue + */ +smStatus_t Se05x_API_MACFinal(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *macValidateData, + size_t macValidateDataLen, + uint8_t *macValue, + size_t *pmacValueLen); + +/** Se05x_API_MACOneShot_G + * + * Generate. See @ref Se05x_API_MACOneShot_V for Verfiication. + * + * Performs a MAC operation in one shot (without keeping state). + * + * The 4-byte identifier of the key must refer to an AESKey, DESKey or HMACKey. + * + * # Command to Applet + * + * @rst + * +---------+------------------------+---------------------------------------------+ + * | Field | Value | Description | + * +=========+========================+=============================================+ + * | CLA | 0x80 | | + * +---------+------------------------+---------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +---------+------------------------+---------------------------------------------+ + * | P1 | P1_MAC | See :cpp:type:`SE05x_P1_t` | + * +---------+------------------------+---------------------------------------------+ + * | P2 | P2_GENERATE_ONESHOT or | See :cpp:type:`SE05x_P2_t` | + * | | P2_VALIDATE_ONESHOT | | + * +---------+------------------------+---------------------------------------------+ + * | Lc | #(Payload) | | + * +---------+------------------------+---------------------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte identifier of the key object. | + * +---------+------------------------+---------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`MACAlgoRef` | + * +---------+------------------------+---------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing data to be taken as | + * | | | input to MAC. | + * +---------+------------------------+---------------------------------------------+ + * | | TLV[TAG_5] | MAC to verify (when P2=P2_VALIDATE_ONESHOT) | + * +---------+------------------------+---------------------------------------------+ + * | Le | 0x00 | Expecting MAC or Result. | + * +---------+------------------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+---------------------------------------+ + * | Value | Description | + * +============+=======================================+ + * | TLV[TAG_1] | MAC value (P2=P2_GENERATE_ONESHOT) or | + * | | :cpp:type:`SE05x_Result_t` (when | + * | | p2=P2_VALIDATE_ONESHOT). | + * +------------+---------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] macOperation macOperation [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] macValue [0:kSE05x_TAG_1] + * @param[in,out] pmacValueLen Length for macValue + */ +smStatus_t Se05x_API_MACOneShot_G(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t macOperation, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *macValue, + size_t *pmacValueLen); + +/** Se05x_API_MACOneShot_V + * + * Validate. See @ref Se05x_API_MACOneShot_G for Generation. + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] macOperation macOperation [2:kSE05x_TAG_2] + * @param[in] inputData inputData [3:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[in] MAC MAC to verify (when P2=P2_VALIDATE_ONESHOT) [4:kSE05x_TAG_5] + * @param[in] MACLen Length of MAC + * @param[out] macValue [0:kSE05x_TAG_1] + * @param[in,out] pmacValueLen Length for macValue + */ +smStatus_t Se05x_API_MACOneShot_V(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t macOperation, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *MAC, + size_t MACLen, + uint8_t *macValue, + size_t *pmacValueLen); + +/** Se05x_API_HKDF + * + * Note that this KDF is equal to the KDF in Feedback Mode described in [NIST + * SP800-108] with the PRF being HMAC with SHA256 and with an 8-bit counter at + * the end of the iteration variable. + * + * The full HKDF algorithm is executed, i.e. Extract-And-Expand. + * + * The caller must provide a salt length (0 up to 64 bytes). If salt length + * equals 0 or salt is not provided as input, the default salt will be used. + * + * The output of the HKDF functions can be either: + * + * * send back to the caller => _precondition_ : none of the input Secure Objects -if present- shall have a policy POLICY_OBJ_FORBID_DERIVED_OUTPUT set. + * + * * be stored in a Secure Object => _precondition_ : the Secure Object must be created upfront and the size must exactly match the expected length. + * + * + * # Command to Applet + * + * @rst + * +------------+--------------------------------+-----------------------------------+ + * | Field | Value | Description | + * +============+================================+===================================+ + * | CLA | 0x80 | | + * +------------+--------------------------------+-----------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+--------------------------------+-----------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +------------+--------------------------------+-----------------------------------+ + * | P2 | P2_HKDF | See :cpp:type:`SE05x_P2_t` | + * +------------+--------------------------------+-----------------------------------+ + * | Lc | #(Payload) | | + * +------------+--------------------------------+-----------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte HMACKey identifier (= IKM) | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_2] | 1-byte DigestMode (except | | + * | | DIGEST_NO_HASH) | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_3] | Byte array (0-64 bytes) | | + * | | containing salt. [Optional] | | + * | | [Conditional: only when | | + * | | TLV[TAG_6] is absent.] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_4] | Info: The context and | | + * | | information to apply (1 to 80 | | + * | | bytes). [Optional] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_5] | 2-byte requested length (L): 1 | | + * | | up to MAX_APDU_PAYLOAD_LENGTH | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_6] | 4-byte HMACKey identifier | | + * | | containing salt. [Optional] | | + * | | [Conditional: only when | | + * | | TLV[TAG_3] is absent] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_7] | 4-byte HMACKey identifier to | | + * | | store output. [Optional] | | + * +------------+--------------------------------+-----------------------------------+ + * | Le | 0x00 | | + * +------------+--------------------------------+-----------------------------------+ + * @endrst + * + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_1] | HKDF output. [Conditional: only when the | + * | | input does not contain TLV[TAG-7]] | + * +------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+------------------------------------+ + * | SW | Description | + * +=============+====================================+ + * | SW_NO_ERROR | The HKDF is executed successfully. | + * +-------------+------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] hmacID hmacID [1:kSE05x_TAG_1] + * @param[in] digestMode digestMode [2:kSE05x_TAG_2] + * @param[in] salt salt [3:kSE05x_TAG_3] + * @param[in] saltLen Length of salt + * @param[in] info info [4:kSE05x_TAG_4] + * @param[in] infoLen Length of info + * @param[in] deriveDataLen 2-byte requested length (L) [5:kSE05x_TAG_5] + * @param[out] hkdfOuput [0:kSE05x_TAG_1] + * @param[in,out] phkdfOuputLen Length for hkdfOuput + */ +smStatus_t Se05x_API_HKDF(pSe05xSession_t session_ctx, + uint32_t hmacID, + SE05x_DigestMode_t digestMode, + const uint8_t *salt, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + uint16_t deriveDataLen, + uint8_t *hkdfOuput, + size_t *phkdfOuputLen); + +/** Se05x_API_HKDF_Extended + * + * Only step 2 of the algorithm is executed, i.e. Expand only. + * + * Using an IV as input parameter results in a FIPS compliant SP800-108 KDF in + * Feedback Mode where K[0] is the provided IV. This KDF is then using a 8-bit + * counter, AFTER_FIXED counter location. + * + * # Command to Applet + * + * @rst + * +------------+--------------------------------+-----------------------------------+ + * | Field | Value | Description | + * +============+================================+===================================+ + * | CLA | 0x80 | | + * +------------+--------------------------------+-----------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +------------+--------------------------------+-----------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +------------+--------------------------------+-----------------------------------+ + * | P2 | P2_HKDF_EXPAND_ONLY | See :cpp:type:`SE05x_P2_t` | + * +------------+--------------------------------+-----------------------------------+ + * | Lc | #(Payload) | | + * +------------+--------------------------------+-----------------------------------+ + * | Payload | TLV[TAG_1] | 4-byte HMACKey identifier (= PRK) | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_2] | 1-byte DigestMode (except | | + * | | DIGEST_NO_HASH) | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_3] | Byte array (0-64 bytes) | | + * | | containing IV. [Optional] | | + * | | [Conditional: only when | | + * | | TLV[TAG_6] is absent.] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_4] | Info: The context and | | + * | | information to apply (1 to 80 | | + * | | bytes). [Optional] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_5] | 2-byte requested length (L): 1 | | + * | | up to MAX_APDU_PAYLOAD_LENGTH | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_6] | 4-byte HMACKey identifier | | + * | | containing IV. [Optional] | | + * | | [Conditional: only when | | + * | | TLV[TAG_3] is absent] | | + * +------------+--------------------------------+-----------------------------------+ + * | TLV[TAG_7] | 4-byte HMACKey identifier to | | + * | | store output. [Optional] | | + * +------------+--------------------------------+-----------------------------------+ + * | Le | 0x00 | | + * +------------+--------------------------------+-----------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------------+ + * | Value | Description | + * +============+============================================+ + * | TLV[TAG_1] | HKDF output. [Conditional: only when the | + * | | input does not contain TLV[TAG-7]] | + * +------------+--------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+------------------------------------+ + * | SW | Description | + * +=============+====================================+ + * | SW_NO_ERROR | The HKDF is executed successfully. | + * +-------------+------------------------------------+ + * + * + */ +smStatus_t Se05x_API_HKDF_Extended(pSe05xSession_t session_ctx, + uint32_t hmacID, + SE05x_DigestMode_t digestMode, + SE05x_HkdfMode_t hkdfMode, + const uint8_t *salt, + size_t saltLen, + uint32_t saltID, + const uint8_t *info, + size_t infoLen, + uint32_t derivedKeyID, + uint16_t deriveDataLen, + uint8_t *hkdfOuput, + size_t *phkdfOuputLen); + +/** Se05x_API_PBKDF2 + * + * Password Based Key Derivation Function 2 (PBKDF2) according [RFC8018]. + * + * The password is an input to the KDF and must be stored inside the . + * + * The output is returned to the host. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+==============================================+ + * | CLA | 0x80 | | + * +-------+------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+----------------------------------------------+ + * | P2 | P2_PBKDF | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte password identifier (object type must | + * | | | be HMACKey) | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_2] | Salt (0 to 64 bytes) [Optional] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_3] | 2-byte Iteration count: 1 up to 0x7FFF. | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_4] | 2-byte Requested length: 1 up to 512 bytes. | + * +-------+------------+----------------------------------------------+ + * | Le | 0x00 | Expecting derived key material. | + * +-------+------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------------------------------+ + * | Value | Description | + * +============+=====================================+ + * | TLV[TAG_1] | Derived key material (session key). | + * +------------+-------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID 4-byte password identifier (object type must be HMACKey) [1:kSE05x_TAG_1] + * @param[in] salt salt [2:kSE05x_TAG_2] + * @param[in] saltLen Length of salt + * @param[in] count count [3:kSE05x_TAG_3] + * @param[in] requestedLen requestedLen [4:kSE05x_TAG_4] + * @param[out] derivedSessionKey [0:kSE05x_TAG_1] + * @param[in,out] pderivedSessionKeyLen Length for derivedSessionKey + */ +smStatus_t Se05x_API_PBKDF2(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *salt, + size_t saltLen, + uint16_t count, + uint16_t requestedLen, + uint8_t *derivedSessionKey, + size_t *pderivedSessionKeyLen); + +/** Se05x_API_DFDiversifyKey + * + * + * Create a Diversified Key. Input is _divInput_ 1 up to 31 bytes. + * + * Note that users need to create the diversified key object before calling this + * function. + * + * Both the master key and the diversified key need the policy + * POLICY_OBJ_ALLOW_DESFIRE_AUTHENTICATION to be set. + * + * # Command to Applet + * + * @rst + * +-------+--------------+------------------------------------------+ + * | Field | Value | Description | + * +=======+==============+==========================================+ + * | CLA | 0x80 | | + * +-------+--------------+------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+------------------------------------------+ + * | P2 | P2_DIVERSIFY | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+------------------------------------------+ + * | | TLV[TAG_1] | 4-byte master key identifier. | + * +-------+--------------+------------------------------------------+ + * | | TLV[TAG_2] | 4-byte diversified key identifier. | + * +-------+--------------+------------------------------------------+ + * | | TLV[TAG_3] | Byte array containing divInput (up to 31 | + * | | | bytes). | + * +-------+--------------+------------------------------------------+ + * | Le | | | + * +-------+--------------+------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-----------------------------+--------------------------------------+ + * | SW | Description | + * +=============================+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-----------------------------+--------------------------------------+ + * | SW_CONDITIONS_NOT_SATISFIED | No master key found. | + * +-----------------------------+--------------------------------------+ + * | | Wrong length for divInput. | + * +-----------------------------+--------------------------------------+ + * @endrst + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] masterKeyID masterKeyID [1:kSE05x_TAG_1] + * @param[in] diversifiedKeyID diversifiedKeyID [2:kSE05x_TAG_2] + * @param[in] divInputData divInputData [3:kSE05x_TAG_3] + * @param[in] divInputDataLen Length of divInputData + */ +smStatus_t Se05x_API_DFDiversifyKey(pSe05xSession_t session_ctx, + uint32_t masterKeyID, + uint32_t diversifiedKeyID, + const uint8_t *divInputData, + size_t divInputDataLen); + +/** Se05x_API_DFAuthenticateFirstPart1 + * + * MIFARE DESFire support + * + * MIFARE DESFire EV2 Key derivation (S-mode). This is limited to AES128 keys + * only. + * + * The SE05X can be used by a card reader to setup a session where the SE05X + * stores the master key(s) and the session keys are generated and passed to the + * host. + * + * The SE05X keeps an internal state of MIFARE DESFire authentication data during + * authentication setup. This state is fully transient, so it is lost on deselect + * of the applet. + * + * The MIFARE DESFire state is owned by 1 user at a time; i.e., the user who + * calls DFAuthenticateFirstPart1 owns the MIFARE DESFire context until + * DFAuthenticateFirstPart1 is called again or until DFKillAuthentication is + * called. + * + * The SE05X can also be used to support a ChangeKey command, either supporting + * ChangeKey or ChangeKeyEV2. To establish a correct use case, policies need to + * be applied to the keys to indicate keys can be used for ChangeKey or not, etc. + * (to be detailed) + * + * # Command to Applet + * + * @rst + * +-------+---------------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+=====================+==============================================+ + * | CLA | 0x80 | | + * +-------+---------------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+---------------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------------+----------------------------------------------+ + * | P2 | P2_AUTH_FIRST_PART1 | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+---------------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte key identifier. | + * +-------+---------------------+----------------------------------------------+ + * | | TLV[TAG_2] | 16-byte encrypted card challenge: E(Kx,RndB) | + * +-------+---------------------+----------------------------------------------+ + * | Le | 0x00 | | + * +-------+---------------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+---------------------------------------------+ + * | Value | Description | + * +============+=============================================+ + * | TLV[TAG_1] | 32-byte output data: E(Kx, RandA || RandB') | + * +------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] inputData inputData [2:kSE05x_TAG_2] + * @param[in] inputDataLen Length of inputData + * @param[out] outputData [0:kSE05x_TAG_1] + * @param[in,out] poutputDataLen Length for outputData + */ +smStatus_t Se05x_API_DFAuthenticateFirstPart1(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen); + +/** Se05x_API_DFAuthenticateNonFirstPart1 + * + * + * # Command to Applet + * + * @rst + * +-------+------------------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+========================+==============================================+ + * | CLA | 0x80 | | + * +-------+------------------------+----------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+------------------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------------+----------------------------------------------+ + * | P2 | P2_AUTH_NONFIRST_PART1 | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte key identifier. | + * +-------+------------------------+----------------------------------------------+ + * | | TLV[TAG_2] | 16-byte encrypted card challenge: E(Kx,RndB) | + * +-------+------------------------+----------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+---------------------------------------------+ + * | Value | Description | + * +============+=============================================+ + * | TLV[TAG_1] | 32-byte output data: E(Kx, RandA || RandB') | + * +------------+---------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] objectID objectID [1:kSE05x_TAG_1] + * @param[in] inputData inputData [2:kSE05x_TAG_2] + * @param[in] inputDataLen Length of inputData + * @param[out] outputData [0:kSE05x_TAG_1] + * @param[in,out] poutputDataLen Length for outputData + */ +smStatus_t Se05x_API_DFAuthenticateNonFirstPart1(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen); + +/** Se05x_API_DFAuthenticateFirstPart2 + * + * For First part 2, the key identifier is implicitly set to the identifier used + * for the First authentication. DFAuthenticateFirstPart1 needs to be called + * before; otherwise an error is returned. + * + * # Command to Applet + * + * @rst + * +-------+---------------------+------------------------------------+ + * | Field | Value | Description | + * +=======+=====================+====================================+ + * | CLA | 0x80 | | + * +-------+---------------------+------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+---------------------+------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------------+------------------------------------+ + * | P2 | P2_AUTH_FIRST_PART2 | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------------+------------------------------------+ + * | Lc | #(Payload) | | + * +-------+---------------------+------------------------------------+ + * | | TLV[TAG_1] | 32 byte input: | + * | | | E(Kx,TI||RndA'||PDcap2||PCDcap2) | + * +-------+---------------------+------------------------------------+ + * | Le | 0x00 | | + * +-------+---------------------+------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------+ + * | Value | Description | + * +============+==========================================+ + * | TLV[TAG_1] | 12-byte array returning PDcap2||PCDcap2. | + * +------------+------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-----------------------------+--------------------------------------+ + * | SW | Description | + * +=============================+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-----------------------------+--------------------------------------+ + * | SW_WRONG_DATA | | + * +-----------------------------+--------------------------------------+ + * | SW_CONDITIONS_NOT_SATISFIED | | + * +-----------------------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] inputData inputData [1:kSE05x_TAG_1] + * @param[in] inputDataLen Length of inputData + * @param[out] outputData [0:kSE05x_TAG_1] + * @param[in,out] poutputDataLen Length for outputData + */ +smStatus_t Se05x_API_DFAuthenticateFirstPart2(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen); + +/** Se05x_API_DFAuthenticateNonFirstPart2 + * + * For NonFirst part 2, the key identifier is implicitly set to the identifier + * used for the NonFirst part 1 authentication. DFAuthenticateNonFirstPart1 needs + * to be called before; otherwise an error is returned. + * + * If authentication fails, SW_WRONG_DATA will be returned. + * + * # Command to Applet + * + * @rst + * +-------+------------------------+----------------------------+ + * | Field | Value | Description | + * +=======+========================+============================+ + * | CLA | 0x80 | | + * +-------+------------------------+----------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+------------------------+----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------------+----------------------------+ + * | P2 | P2_AUTH_NONFIRST_PART2 | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------------+----------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------------+----------------------------+ + * | | TLV[TAG_1] | 16-byte E(Kx, RndA') | + * +-------+------------------------+----------------------------+ + * | Le | 0x00 | | + * +-------+------------------------+----------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] inputData inputData [1:kSE05x_TAG_1] + * @param[in] inputDataLen Length of inputData + */ +smStatus_t Se05x_API_DFAuthenticateNonFirstPart2( + pSe05xSession_t session_ctx, const uint8_t *inputData, size_t inputDataLen); + +/** Se05x_API_DFDumpSessionKeys + * + * Dump the Transaction Identifier and the session keys to the host. + * + * + * # Command to Applet + * + * @rst + * +-------+-------------+-----------------------------------+ + * | Field | Value | Description | + * +=======+=============+===================================+ + * | CLA | 0x80 | | + * +-------+-------------+-----------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+-------------+-----------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+-------------+-----------------------------------+ + * | P2 | P2_DUMP_KEY | See :cpp:type:`SE05x_P2_t` | + * +-------+-------------+-----------------------------------+ + * | Lc | #(Payload) | | + * +-------+-------------+-----------------------------------+ + * | Le | 0x28 | Expecting TLV with 38 bytes data. | + * +-------+-------------+-----------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------------------------------+ + * | Value | Description | + * +============+======================================+ + * | TLV[TAG_1] | 38 bytes: KeyID.SesAuthENCKey || | + * | | KeyID.SesAuthMACKey || TI || Cmd-Ctr | + * +------------+--------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[out] sessionData 38 bytes: KeyID.SesAuthENCKey || KeyID.SesAuthMACKey || TI || Cmd-Ctr [0:kSE05x_TAG_1] + * @param[in,out] psessionDataLen Length for sessionData + */ +smStatus_t Se05x_API_DFDumpSessionKeys(pSe05xSession_t session_ctx, uint8_t *sessionData, size_t *psessionDataLen); + +/** Se05x_API_DFChangeKeyPart1 + * + * + * The DFChangeKeyPart1 command is supporting the function to change keys on the + * DESFire PICC. The command generates the cryptogram required to perform such + * operation. + * + * The new key and, if used, the current (or old) key must be stored in the SE05X + * and have the POLICY_OBJ_ALLOW_DESFIRE_AUTHENTICATION associated to execute + * this command. This means the new PICC key must have been loaded into the SE05X + * prior to issuing this command. + * + * The 1-byte key set number indicates whether DESFire ChangeKey or DESFire + * ChangeKeyEV2 is used. When key set equals 0xFF, ChangeKey is used. + * + * + * # Command to Applet + * + * @rst + * +-------+---------------------+------------------------------------------------+ + * | Field | Value | Description | + * +=======+=====================+================================================+ + * | CLA | 0x80 | | + * +-------+---------------------+------------------------------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+---------------------+------------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------------+------------------------------------------------+ + * | P2 | P2_CHANGE_KEY_PART1 | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+---------------------+------------------------------------------------+ + * | | TLV[TAG_1] | 4-byte identifier of the old key. [Optional: | + * | | | if the authentication key is the same as the | + * | | | key to be replaced, this TAG should not be | + * | | | present]. | + * +-------+---------------------+------------------------------------------------+ + * | | TLV[TAG_2] | 4-byte identifier of the new key. | + * +-------+---------------------+------------------------------------------------+ + * | | TLV[TAG_3] | 1-byte key set number [Optional: default = | + * | | | 0xC6] | + * +-------+---------------------+------------------------------------------------+ + * | | TLV[TAG_4] | 1-byte DESFire key number to be targeted. | + * +-------+---------------------+------------------------------------------------+ + * | | TLV[TAG_5] | 1-byte key version | + * +-------+---------------------+------------------------------------------------+ + * | Le | 0x00 | | + * +-------+---------------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------+ + * | Value | Description | + * +============+=============================+ + * | TLV[TAG_1] | Cryptogram holding key data | + * +------------+-----------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] oldObjectID oldObjectID [1:kSE05x_TAG_1] + * @param[in] newObjectID newObjectID [2:kSE05x_TAG_2] + * @param[in] keySetNr keySetNr [3:kSE05x_TAG_3] + * @param[in] keyNoDESFire keyNoDESFire [4:kSE05x_TAG_4] + * @param[in] keyVer keyVer [5:kSE05x_TAG_5] + * @param[out] KeyData [0:kSE05x_TAG_1] + * @param[in,out] pKeyDataLen Length for KeyData + */ +smStatus_t Se05x_API_DFChangeKeyPart1(pSe05xSession_t session_ctx, + uint32_t oldObjectID, + uint32_t newObjectID, + uint8_t keySetNr, + uint8_t keyNoDESFire, + uint8_t keyVer, + uint8_t *KeyData, + size_t *pKeyDataLen); + +/** Se05x_API_DFChangeKeyPart2 + * + * The DFChangeKeyPart2 command verifies the MAC returned by ChangeKey or + * ChangeKeyEV2. Note that this function only needs to be called if a MAC is + * returned (which is not the case if the currently authenticated key is changed + * on the DESFire card). + * + * # Command to Applet + * + * @rst + * +-------+---------------------+----------------------------+ + * | Field | Value | Description | + * +=======+=====================+============================+ + * | CLA | 0x80 | | + * +-------+---------------------+----------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+---------------------+----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------------+----------------------------+ + * | P2 | P2_CHANGE_KEY_PART2 | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------------+----------------------------+ + * | Lc | #(Payload) | | + * +-------+---------------------+----------------------------+ + * | | TLV[TAG_1] | MAC | + * +-------+---------------------+----------------------------+ + * | Le | 0x00 | | + * +-------+---------------------+----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-----------------------------------+ + * | Value | Description | + * +============+===================================+ + * | TLV[TAG_1] | 1-byte :cpp:type:`SE05x_Result_t` | + * +------------+-----------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] MAC MAC [1:kSE05x_TAG_1] + * @param[in] MACLen Length of MAC + * @param[out] presult [0:kSE05x_TAG_1] + */ +smStatus_t Se05x_API_DFChangeKeyPart2(pSe05xSession_t session_ctx, const uint8_t *MAC, size_t MACLen, uint8_t *presult); + +/** Se05x_API_DFKillAuthentication + * + * DFKillAuthentication invalidates any authentication and clears the internal + * DESFire state. Keys used as input (master keys or diversified keys) are not + * touched. + * + * # Command to Applet + * + * @rst + * +-------+--------------+----------------------------+ + * | Field | Value | Description | + * +=======+==============+============================+ + * | CLA | 0x80 | | + * +-------+--------------+----------------------------+ + * | INS | INS_CRYPTO | :cpp:type:`SE05x_INS_t` | + * +-------+--------------+----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+--------------+----------------------------+ + * | P2 | P2_KILL_AUTH | See :cpp:type:`SE05x_P2_t` | + * +-------+--------------+----------------------------+ + * | Lc | #(Payload) | | + * +-------+--------------+----------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + */ +smStatus_t Se05x_API_DFKillAuthentication(pSe05xSession_t session_ctx); + +/** Se05x_API_TLSGenerateRandom + * + * Generates a random that is stored in the SE05X and used by TLSPerformPRF. + * + * # Command to Applet + * + * @rst + * +-------+------------+-----------------------------------+ + * | Field | Value | Description | + * +=======+============+===================================+ + * | CLA | 0x80 | | + * +-------+------------+-----------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-----------------------------------+ + * | P1 | P1_TLS | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-----------------------------------+ + * | P2 | P2_RANDOM | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-----------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-----------------------------------+ + * | Le | 0x22 | Expecting TLV with 32 bytes data. | + * +-------+------------+-----------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------+ + * | Value | Description | + * +============+======================+ + * | TLV[TAG_1] | 32-byte random value | + * +------------+----------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[out] randomValue [0:kSE05x_TAG_1] + * @param[in,out] prandomValueLen Length for randomValue + */ +smStatus_t Se05x_API_TLSGenerateRandom(pSe05xSession_t session_ctx, uint8_t *randomValue, size_t *prandomValueLen); + +/** Se05x_API_TLSCalculatePreMasterSecret + * + * The command TLSCalculatePreMasterSecret will compute the pre-master secret for + * TLS according [RFC5246]. The pre-master secret will always be stored in an + * HMACKey object (TLV[TAG_3]). The HMACKey object must be created before; + * otherwise the calculation of the pre-master secret will fail. + * + * It can use one of these algorithms: - - - - + * + * * PSK Key Exchange algorithm as defined in [RFC4279] + * + * * RSA_PSK Key Exchange algorithm as defined in [RFC4279] + * + * * ECDHE_PSK Key Exchange algorithm as defined in [RFC5489] + * + * * EC Key Exchange algorithm as defined in [RFC4492] + * + * * RSA Key Exchange algorithm as defined in [RFC5246] + * + * + * TLV[TAG_1] needs to be an (existing) HMACKey identifier containing the pre- + * shared Key. + * + * Input data in TLV[TAG_4] are: + * + * * An EC public key when TLV[TAG_2] refers to an EC key pair. + * + * * An RSA encrypted secret when TLV[TAG_2] refers to an RSA key pair. + * + * * Empty when TLV[TAG_2] is absent or empty. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+============+==============================================+ + * | CLA | 0x80 | | + * +-------+------------+----------------------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+----------------------------------------------+ + * | P1 | P1_TLS | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+----------------------------------------------+ + * | P2 | P2_PMS | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte PSK identifier referring to a 16, 32, | + * | | | 48 or 64-byte Pre Shared Key. [Optional] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_2] | 4-byte key pair identifier. [Optional] | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_3] | 4-byte target HMACKey identifier. | + * +-------+------------+----------------------------------------------+ + * | | TLV[TAG_4] | Byte array containing input data. | + * +-------+------------+----------------------------------------------+ + * | Le | - | | + * +-------+------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] keyPairId keyPairId [1:kSE05x_TAG_1] + * @param[in] pskId pskId [2:kSE05x_TAG_2] + * @param[in] hmacKeyId hmacKeyId [3:kSE05x_TAG_3] + * @param[in] inputData inputData [4:kSE05x_TAG_4] + * @param[in] inputDataLen Length of inputData + */ +smStatus_t Se05x_API_TLSCalculatePreMasterSecret(pSe05xSession_t session_ctx, + uint32_t keyPairId, + uint32_t pskId, + uint32_t hmacKeyId, + const uint8_t *inputData, + size_t inputDataLen); + +/** Se05x_API_TLSPerformPRF + * + * The command TLSPerformPRF will compute either: + * + * * the master secret for TLS according [RFC5246], section 8.1 + * + * * key expansion data from a master secret for TLS according [RFC5246], section 6.3 + * + * Each time before calling this function, TLSGenerateRandom must be called. + * Executing this function will clear the random that is stored in the SE05X . + * + * The function can be called as client or as server and either using the pre- + * master secret or master secret as input, stored in an HMACKey. The input + * length must be either 16, 32, 48 or 64 bytes. + * + * This results in P2 having 4 possibilities: + * + * * P2_TLS_PRF_CLI_HELLO: pass the clientHelloRandom to calculate a master secret, the serverHelloRandom is in SE05X , generated by TLSGenerateRandom. + * + * * P2_TLS_PRF_SRV_HELLO: pass the serverHelloRandom to calculate a master secret, the clientHelloRandom is in SE05X , generated by TLSGenerateRandom. + * + * * P2_TLS_PRF_CLI_RANDOM: pass the clientRandom to generate key expansion data, the serverRandom is in SE05X , generated by TLSGenerateRandom. + * + * * P2_TLS_PRF_SRV_RANDOM: pass the serverRandom to generate key expansion data, the clientRandom is in SE05X + * + * + * # Command to Applet + * + * @rst + * +-------+------------------------+-----------------------------------------------+ + * | Field | Value | Description | + * +=======+========================+===============================================+ + * | CLA | 0x80 | | + * +-------+------------------------+-----------------------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------------------+-----------------------------------------------+ + * | P1 | P1_TLS | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------------+-----------------------------------------------+ + * | P2 | See description above. | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------------+-----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------------+-----------------------------------------------+ + * | | TLV[TAG_1] | 4-byte HMACKey identifier. | + * +-------+------------------------+-----------------------------------------------+ + * | | TLV[TAG_2] | 1-byte :cpp:type:`SE05x_DigestMode_t`, except | + * | | | DIGEST_NO_HASH. | + * +-------+------------------------+-----------------------------------------------+ + * | | TLV[TAG_3] | Label (1 to 64 bytes) | + * +-------+------------------------+-----------------------------------------------+ + * | | TLV[TAG_4] | 32-byte random | + * +-------+------------------------+-----------------------------------------------+ + * | | TLV[TAG_5] | 2-byte requested length | + * +-------+------------------------+-----------------------------------------------+ + * | Le | 0x00 | | + * +-------+------------------------+-----------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------------------+ + * | Value | Description | + * +============+==============================================+ + * | TLV[TAG_1] | Byte array containing requested output data. | + * +------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * + * @param[in] session_ctx The session context + * @param[in] objectID The object id + * @param[in] digestAlgo The digest algorithm + * @param[in] label The label + * @param[in] labelLen The label length + * @param[in] random The random + * @param[in] randomLen The random length + * @param[in] reqLen The request length + * @param outputData The output data + * @param poutputDataLen The poutput data length + * @param[in] tlsprf The tlsprf + * + * @return The sm status. + */ +smStatus_t Se05x_API_TLSPerformPRF(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t digestAlgo, + const uint8_t *label, + size_t labelLen, + const uint8_t *random, + size_t randomLen, + uint16_t reqLen, + uint8_t *outputData, + size_t *poutputDataLen, + const SE05x_TLSPerformPRFType_t tlsprf); + +/** Se05x_API_I2CM_ExecuteCommandSet + * + * Execute one or multiple I2C commands in master mode. Execution is conditional + * to the presence of the authentication object identified by + * RESERVED_ID_I2CM_ACCESS. If the credential is not present in the eSE, access + * is allowed in general. Otherwise, a session shall be established before + * executing this command. In this case, the I2CM_ExecuteCommandSet command shall + * be sent within the mentioned session. + * + * The I2C command set is constructed as a sequence of instructions described in + * with the following rules: + * + * * The length should be limited to MAX_I2CM_COMMAND_LENGTH. + * + * * The data to be read cannot exceed MAX_I2CM_COMMAND_LENGTH, including protocol overhead. + * + * # Command to Applet + * + * @rst + * +-------+------------+------------------------------------------------+ + * | Field | Value | Description | + * +=======+============+================================================+ + * | CLA | 0x80 | | + * +-------+------------+------------------------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t`, in addition to | + * | | | INS_CRYPTO, users can set the INS_ATTEST flag. | + * | | | In that case, attestation applies. | + * +-------+------------+------------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+------------------------------------------------+ + * | P2 | P2_I2CM | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+------------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+------------------------------------------------+ + * | | TLV[TAG_1] | Byte array containing I2C Command set as TLV | + * | | | array. | + * +-------+------------+------------------------------------------------+ + * | | TLV[TAG_2] | 4-byte attestation object identifier. | + * | | | [Optional] [Conditional: only when | + * | | | INS_ATTEST is set] | + * +-------+------------+------------------------------------------------+ + * | | TLV[TAG_3] | 1-byte :cpp:type:`SE05x_AttestationAlgo_t` | + * | | | [Optional] [Conditional: only when | + * | | | INS_ATTEST is set] | + * +-------+------------+------------------------------------------------+ + * | | TLV[TAG_7] | 16-byte freshness random [Optional] | + * | | | [Conditional: only when INS_ATTEST is set] | + * +-------+------------+------------------------------------------------+ + * | Le | 0x00 | Expecting TLV with return data. | + * +-------+------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | Read response, a bytestring containing a | + * | | sequence of: * CONFIGURE (0x01), | + * | | followed by 1 byte of return code (0x5A = | + * | | SUCCESS). * WRITE (0x03), | + * | | followed by 1 byte of return code * | + * | | READ (0x04), followed by - | + * | | Length: 2 bytes in big endian encoded without | + * | | TLV length encoding - | + * | | Read bytes * | + * | | 0xFF followed by the error return code in case | + * | | of a structural error of the incoming buffer | + * | | (too long, for example) | + * +------------+------------------------------------------------+ + * | TLV[TAG_3] | TLV containing 12-byte timestamp | + * +------------+------------------------------------------------+ + * | TLV[TAG_4] | TLV containing 16-byte freshness (random) | + * +------------+------------------------------------------------+ + * | TLV[TAG_5] | TLV containing 18-byte chip unique ID | + * +------------+------------------------------------------------+ + * | TLV[TAG_6] | TLV containing signature over the concatenated | + * | | values of TLV[TAG_1], TLV[TAG_3], TLV[TAG_4] | + * | | and TLV[TAG_5]. | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * + * + * @param[in] session_ctx The session context + * @param[in] inputData The input data + * @param[in] inputDataLen The input data length + * @param[in] attestationID The attestation id + * @param[in] attestationAlgo The attestation algorithm + * @param response The response + * @param presponseLen The presponse length + * @param ptimeStamp The ptime stamp + * @param freshness The freshness + * @param pfreshnessLen The pfreshness length + * @param chipId The chip identifier + * @param pchipIdLen The pchip identifier length + * @param signature The signature + * @param psignatureLen The psignature length + * @param randomAttst The random attst + * @param[in] randomAttstLen The random attst length + * + * @return The sm status. + */ +smStatus_t Se05x_API_I2CM_ExecuteCommandSet(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t attestationID, + uint8_t attestationAlgo, + uint8_t *response, + size_t *presponseLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *freshness, + size_t *pfreshnessLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen, + uint8_t *randomAttst, + size_t randomAttstLen); + +/** Se05x_API_DigestInit + * + * Open a digest operation. The state of the digest operation is kept in the + * Crypto Object until the Crypto Object is finalized or deleted. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+---------------------------------+ + * | Field | Value | Description | + * +=======+============+=================================+ + * | CLA | 0x80 | | + * +-------+------------+---------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+---------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+---------------------------------+ + * | P2 | P2_INIT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+---------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+---------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +-------+------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_2] + */ +smStatus_t Se05x_API_DigestInit(pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID); + +/** Se05x_API_DigestUpdate + * + * + * # Command to Applet + * + * @rst + * +-------+------------+---------------------------------+ + * | Field | Value | Description | + * +=======+============+=================================+ + * | CLA | 0x80 | | + * +-------+------------+---------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+---------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+---------------------------------+ + * | P2 | P2_UPDATE | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+---------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+---------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +-------+------------+---------------------------------+ + * | | TLV[TAG_3] | Data to be hashed. | + * +-------+------------+---------------------------------+ + * | Le | | | + * +-------+------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------------+ + * | SW | Description | + * +=============+======================================+ + * | SW_NO_ERROR | The command is handled successfully. | + * +-------------+--------------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_2] + * @param[in] inputData inputData [2:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + */ +smStatus_t Se05x_API_DigestUpdate( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *inputData, size_t inputDataLen); + +/** Se05x_API_DigestFinal + * + * + * # Command to Applet + * + * @rst + * +-------+------------+------------------------------------+ + * | Field | Value | Description | + * +=======+============+====================================+ + * | CLA | 0x80 | | + * +-------+------------+------------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+------------------------------------+ + * | P2 | P2_FINAL | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+------------------------------------+ + * | | TLV[TAG_2] | 2-byte Crypto Object identifier | + * +-------+------------+------------------------------------+ + * | | TLV[TAG_3] | Data to be encrypted or decrypted. | + * +-------+------------+------------------------------------+ + * | Le | 0x00 | Expecting TLV with hash value. | + * +-------+------------+------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------+ + * | Value | Description | + * +============+=============+ + * | TLV[TAG_1] | CMAC value | + * +------------+-------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+-----------------------------------+ + * | SW | Description | + * +=============+===================================+ + * | SW_NO_ERROR | The hash is created successfully. | + * +-------------+-----------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] cryptoObjectID cryptoObjectID [1:kSE05x_TAG_2] + * @param[in] inputData inputData [2:kSE05x_TAG_3] + * @param[in] inputDataLen Length of inputData + * @param[out] cmacValue [0:kSE05x_TAG_1] + * @param[in,out] pcmacValueLen Length for cmacValue + */ +smStatus_t Se05x_API_DigestFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *cmacValue, + size_t *pcmacValueLen); + +/** Se05x_API_DigestOneShot + * + * Performs a hash operation in one shot (without context). + * + * + * # Command to Applet + * + * @rst + * +-------+------------+-------------------------------------------+ + * | Field | Value | Description | + * +=======+============+===========================================+ + * | CLA | 0x80 | | + * +-------+------------+-------------------------------------------+ + * | INS | INS_CRYPTO | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-------------------------------------------+ + * | P2 | P2_ONESHOT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-------------------------------------------+ + * | | TLV[TAG_1] | 1-byte DigestMode (except DIGEST_NO_HASH) | + * +-------+------------+-------------------------------------------+ + * | | TLV[TAG_2] | Data to hash. | + * +-------+------------+-------------------------------------------+ + * | Le | 0x00 | TLV expecting hash value | + * +-------+------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------+ + * | Value | Description | + * +============+=============+ + * | TLV[TAG_1] | Hash value. | + * +------------+-------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+-----------------------------------+ + * | SW | Description | + * +=============+===================================+ + * | SW_NO_ERROR | The hash is created successfully. | + * +-------------+-----------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + * @param[in] digestMode digestMode [1:kSE05x_TAG_1] + * @param[in] inputData inputData [2:kSE05x_TAG_2] + * @param[in] inputDataLen Length of inputData + * @param[out] hashValue [0:kSE05x_TAG_1] + * @param[in,out] phashValueLen Length for hashValue + */ +smStatus_t Se05x_API_DigestOneShot(pSe05xSession_t session_ctx, + uint8_t digestMode, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *hashValue, + size_t *phashValueLen); + +/** Se05x_API_GetVersion + * + * Gets the applet version information. + * + * This will return 7-byte VersionInfo (including major, minor and patch version + * of the applet, supported applet features and secure box version). + * + * # Command to Applet + * + * @rst + * +-------+------------------------------+----------------------------------------------+ + * | Field | Value | Description | + * +=======+==============================+==============================================+ + * | CLA | 0x80 | | + * +-------+------------------------------+----------------------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------------------------+----------------------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------------------------+----------------------------------------------+ + * | P2 | P2_VERSION or P2_VERSION_EXT | See :cpp:type:`SE05x_P2_t` | + * +-------+------------------------------+----------------------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------------------------+----------------------------------------------+ + * | Le | 0x00 | Expecting TLV with 7-byte data (when P2 = | + * | | | P2_VERSION) or a TLV with 37 byte data (when | + * | | | P2= P2_VERSION_EXT). | + * +-------+------------------------------+----------------------------------------------+ + * @endrst + * + * + * # R-APDU Body + * + * @rst + * +------------+------------------------------------------------+ + * | Value | Description | + * +============+================================================+ + * | TLV[TAG_1] | 7-byte :cpp:type:`VersionInfoRef` (if P2 = | + * | | P2_VERSION) or 7-byte VersionInfo followed by | + * | | 30 bytes extendedFeatureBits (if P2 = | + * | | P2_VERSION_EXT) | + * +------------+------------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * @param[in] session_ctx The session context + * @param pappletVersion The papplet version + * @param appletVersionLen The applet version length + * + * @return The sm status. + */ +smStatus_t Se05x_API_GetVersion(pSe05xSession_t session_ctx, uint8_t *pappletVersion, size_t *appletVersionLen); + +/** Se05x_API_GetTimestamp + * + * Gets a monotonic counter value (time stamp) from the operating system of the + * device (both persistent and transient part). See TimestampFunctionality for + * details on the timestamps. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+-------------------------------+ + * | Field | Value | Description | + * +=======+============+===============================+ + * | CLA | 0x80 | | + * +-------+------------+-------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-------------------------------+ + * | P2 | P2_TIME | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-------------------------------+ + * | Le | 0x2C | Expecting TLV with timestamp. | + * +-------+------------+-------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+-------------------------------------------+ + * | Value | Description | + * +============+===========================================+ + * | TLV[TAG_1] | TLV containing a 12-byte operating system | + * | | timestamp. | + * +------------+-------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx The session context + * @param ptimeStamp The ptime stamp + * + * @return The sm status. + */ +smStatus_t Se05x_API_GetTimestamp(pSe05xSession_t session_ctx, SE05x_TimeStamp_t *ptimeStamp); + +/** Se05x_API_GetFreeMemory + * + * Gets the amount of free memory. MemoryType indicates the type of memory. + * + * The result indicates the amount of free memory. Note that behavior of the + * function might not be fully linear and can have a granularity of 16 bytes + * where the applet will typically report the "worst case" amount. For example, + * when allocating 2 bytes a time, the first report will show 16 bytes being + * allocated, which remains the same for the next 7 allocations of 2 bytes. + * + * + * # Command to Applet + * + * @rst + * +-------+------------+---------------------------------+ + * | Field | Value | Description | + * +=======+============+=================================+ + * | CLA | 0x80 | | + * +-------+------------+---------------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+---------------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+---------------------------------+ + * | P2 | P2_MEMORY | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+---------------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+---------------------------------+ + * | | TLV[TAG_1] | :cpp:type:`SE05x_MemTyp_t` | + * +-------+------------+---------------------------------+ + * | Le | 0x04 | Expecting TLV with 2-byte data. | + * +-------+------------+---------------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+----------------------------------------------+ + * | Value | Description | + * +============+==============================================+ + * | TLV[TAG_1] | 2 bytes indicating the amount of free memory | + * | | of the requested memory type. 0x7FFF as | + * | | response means at least 32768 bytes are | + * | | available. | + * +------------+----------------------------------------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx The session context + * @param[in] memoryType The memory type + * @param pfreeMem The pfree memory + * + * @return The sm status. + */ +smStatus_t Se05x_API_GetFreeMemory(pSe05xSession_t session_ctx, SE05x_MemoryType_t memoryType, uint16_t *pfreeMem); + +/** Se05x_API_GetRandom + * + * Gets random data from the SE05X . + * + * + * # Command to Applet + * + * @rst + * +-------+------------+-----------------------------+ + * | Field | Value | Description | + * +=======+============+=============================+ + * | CLA | 0x80 | | + * +-------+------------+-----------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+------------+-----------------------------+ + * | P2 | P2_RANDOM | See :cpp:type:`SE05x_P2_t` | + * +-------+------------+-----------------------------+ + * | Lc | #(Payload) | | + * +-------+------------+-----------------------------+ + * | | TLV[TAG_1] | 2-byte requested size. | + * +-------+------------+-----------------------------+ + * | Le | 0x00 | Expecting random data | + * +-------+------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * @rst + * +------------+--------------+ + * | Value | Description | + * +============+==============+ + * | TLV[TAG_1] | Random data. | + * +------------+--------------+ + * @endrst + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx The session context + * @param[in] size The size + * @param randomData The random data + * @param prandomDataLen The prandom data length + * + * @return The sm status. + */ +smStatus_t Se05x_API_GetRandom(pSe05xSession_t session_ctx, uint16_t size, uint8_t *randomData, size_t *prandomDataLen); + +/** Se05x_API_DeleteAll + * + * Delete all Secure Objects, delete all curves and Crypto Objects. Secure + * Objects that are trust provisioned by NXP are not deleted (i.e., all objects + * that have Origin set to ORIGIN_PROVISIONED, including the objects with + * reserved object identifiers listed in Object attributes). + * + * This command can only be used from sessions that are authenticated using the + * credential with index RESERVED_ID_FACTORY_RESET. + * + * _Important_ : if a secure messaging session is up & running (e.g., AESKey or + * ECKey session) and the command is sent within this session, the response of + * the DeleteAll command will not be wrapped (i.e., not encrypted and no R-MAC), + * so this will also break down the secure channel protocol (as the session is + * closed by the DeleteAll command itself). + * + * # Command to Applet + * + * @rst + * +-------+---------------+-----------------------------+ + * | Field | Value | Description | + * +=======+===============+=============================+ + * | CLA | 0x80 | | + * +-------+---------------+-----------------------------+ + * | INS | INS_MGMT | See :cpp:type:`SE05x_INS_t` | + * +-------+---------------+-----------------------------+ + * | P1 | P1_DEFAULT | See :cpp:type:`SE05x_P1_t` | + * +-------+---------------+-----------------------------+ + * | P2 | P2_DELETE_ALL | See :cpp:type:`SE05x_P2_t` | + * +-------+---------------+-----------------------------+ + * | Lc | 0x00 | | + * +-------+---------------+-----------------------------+ + * @endrst + * + * # R-APDU Body + * + * NA + * + * # R-APDU Trailer + * + * @rst + * +-------------+--------------------------------+ + * | SW | Description | + * +=============+================================+ + * | SW_NO_ERROR | Data is returned successfully. | + * +-------------+--------------------------------+ + * @endrst + * + * + * + * @param[in] session_ctx Session Context [0:kSE05x_pSession] + */ +smStatus_t Se05x_API_DeleteAll(pSe05xSession_t session_ctx); + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#include "se05x_04_xx_APDU_apis.h" +#endif + +#endif /* SE050X_APDU_APIS_H_INC */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h new file mode 100644 index 00000000000..4717f19f7d7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h @@ -0,0 +1,3470 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(NONSECURE_WORLD) +#include "veneer_printf_table.h" +#endif + +#if defined(NONSECURE_WORLD) +#define NEWLINE() DbgConsole_Printf_NSE("\r\n") +#else +#define NEWLINE() printf("\r\n") +#endif + +smStatus_t Se05x_API_CreateSession( + pSe05xSession_t session_ctx, uint32_t authObjectID, uint8_t *sessionId, size_t *psessionIdLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SESSION_CREATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CreateSession []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("auth", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, authObjectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, sessionId, psessionIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ExchangeSessionData(pSe05xSession_t session_ctx, pSe05xPolicy_t policy) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SESSION_POLICY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + // uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ExchangeSessionData []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("Policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, policy); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_RefreshSession(pSe05xSession_t session_ctx, pSe05xPolicy_t policy) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SESSION_REFRESH}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "RefreshSession []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CloseSession(pSe05xSession_t session_ctx) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SESSION_CLOSE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t iCnt = 0; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CloseSession []"); +#endif /* VERBOSE_APDU_LOGS */ + if (((session_ctx->value[0] || session_ctx->value[1] || session_ctx->value[2] || session_ctx->value[3] || + session_ctx->value[4] || session_ctx->value[5] || session_ctx->value[6] || session_ctx->value[7])) && + (session_ctx->hasSession == 1)) { + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + if (retStatus == SM_OK) { + for (iCnt = 0; iCnt < 8; iCnt++) { + session_ctx->value[iCnt] = 0; + } + session_ctx->hasSession = 0; + } + } + else { + LOG_D("CloseSession command is sent only if valid Session exists!!!"); + } + return retStatus; +} + +smStatus_t Se05x_API_VerifySessionUserID(pSe05xSession_t session_ctx, const uint8_t *userId, size_t userIdLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SESSION_UserID}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "VerifySessionUserID []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("userId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, userId, userIdLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SetLockState(pSe05xSession_t session_ctx, uint8_t lockIndicator, uint8_t lockState) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_TRANSPORT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SetLockState []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U8("lock indicator", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, lockIndicator); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("lock state", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, lockState); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SetPlatformSCPRequest(pSe05xSession_t session_ctx, SE05x_PlatformSCPRequest_t platformSCPRequest) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_SCP}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SetPlatformSCPRequest []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_PlatformSCPRequest("platf scp req", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, platformSCPRequest); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SetAppletFeatures(pSe05xSession_t session_ctx, pSe05xAppletFeatures_t appletVariant) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_VARIANT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SetAppletFeatures []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Variant(&pCmdbuf, &cmdbufLen, kSE05x_TAG_1, appletVariant); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteECKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_EC | key_part, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WriteECKey []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECCurve("curveID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, curveID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("privKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, privKey, privKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("pubKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pubKey, pubKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteRSAKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_RSA | key_part, rsa_format}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WriteRSAKey []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("To be Checked(last 3 not pdf)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("size in bits", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, size); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("p", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, p, pLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("q", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, q, qLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, dp, dpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("dq", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, dq, dqLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("qnv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, qInv, qInvLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("public exp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_8, pubExp, pubExpLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("priv", &pCmdbuf, &cmdbufLen, kSE05x_TAG_9, priv, privLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional_ByteShift("public mod", &pCmdbuf, &cmdbufLen, kSE05x_TAG_10, pubMod, pubModLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteSymmKey(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, type, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WriteSymmKey []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_KeyID("KEK id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, kekID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("key value", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, keyValue, keyValueLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteBinary(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t offset, + uint16_t length, + const uint8_t *inputData, + size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_BINARY, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WriteBinary []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("input data", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_WriteUserID(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + const uint8_t *userId, + size_t userIdLen, + const SE05x_AttestationType_t attestation_type) +{ + smStatus_t retStatus = SM_NOT_OK; + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | attestation_type, kSE05x_P1_UserID, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WriteUserID []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_MaxAttemps("maxAttempt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_MAX_ATTEMPTS, maxAttempt); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("userId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, userId, userIdLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CreateCounter(pSe05xSession_t session_ctx, pSe05xPolicy_t policy, uint32_t objectID, uint16_t size) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_COUNTER, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "Se05x_API_CreateCounter []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + + if (size != 0) { + tlvRet = TLVSET_U16("size", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, size); + if (0 != tlvRet) { + goto cleanup; + } + } + + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SetCounterValue(pSe05xSession_t session_ctx, uint32_t objectID, uint16_t size, uint64_t value) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_COUNTER, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SetCounterValue []"); +#endif /* VERBOSE_APDU_LOGS */ + + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + + if ((size > 0) && (size <= 8)) { + if (value != 0) { + tlvRet = TLVSET_U64_SIZE("value", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, value, size); + if (0 != tlvRet) { + goto cleanup; + } + } + } + else { + LOG_E("Wrong size provided"); + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_IncCounter(pSe05xSession_t session_ctx, uint32_t objectID) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_COUNTER, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(objectID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "IncCounter []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +#if ENABLE_DEPRECATED_API_WritePCR +smStatus_t Se05x_API_WritePCR(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t pcrID, + const uint8_t *initialValue, + size_t initialValueLen, + const uint8_t *inputData, + size_t inputDataLen) +{ + return Se05x_API_WritePCR_WithType( + session_ctx, kSE05x_INS_NA, policy, pcrID, initialValue, initialValueLen, inputData, inputDataLen); +} +#endif // ENABLE_DEPRECATED_API_WritePCR + +smStatus_t Se05x_API_WritePCR_WithType(pSe05xSession_t session_ctx, + const SE05x_INS_t ins_type, + pSe05xPolicy_t policy, + uint32_t pcrID, + const uint8_t *initialValue, + size_t initialValueLen, + const uint8_t *inputData, + size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE | ins_type, kSE05x_P1_PCR, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + + if (Se05x_IsInValidRangeOfUID(pcrID)) + return SM_NOT_OK; + +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "WritePCR []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_Se05xPolicy("policy", &pCmdbuf, &cmdbufLen, kSE05x_TAG_POLICY, policy); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, pcrID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("initialValue", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, initialValue, initialValueLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ImportObject(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAKeyComponent_t rsaKeyComp, + const uint8_t *serializedObject, + size_t serializedObjectLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_DEFAULT, kSE05x_P2_IMPORT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ImportObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + if (rsaKeyComp != kSE05x_RSAKeyComponent_NA) { + tlvRet = TLVSET_RSAKeyComponent("rsaKeyComp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaKeyComp); + if (0 != tlvRet) { + goto cleanup; + } + } + tlvRet = TLVSET_u8bufOptional( + "serializedObject", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, serializedObject, serializedObjectLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ImportExternalObject(pSe05xSession_t session_ctx, + const uint8_t *ECKeydata, + size_t ECKeydataLen, + const uint8_t *ECAuthKeyID, + size_t ECAuthKeyIDLen, + const uint8_t *serializedObject, + size_t serializedObjectLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, 0x06, kSE05x_P1_DEFAULT, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ImportExternalObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8buf("AuthData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_IMPORT_AUTH_DATA, ECKeydata, ECKeydataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("AuthID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_IMPORT_AUTH_KEY_ID, ECAuthKeyID, ECAuthKeyIDLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional( + "serializedObject", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, serializedObject, serializedObjectLen); + + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadObject( + pSe05xSession_t session_ctx, uint32_t objectID, uint16_t offset, uint16_t length, uint8_t *data, size_t *pdataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + + if (retStatus == SM_ERR_ACCESS_DENIED_BASED_ON_POLICY) + LOG_W("Denied to read object %08X bases on policy.", objectID); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadObject_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + uint8_t *attribute, + size_t *pattributeLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ_With_Attestation, kSE05x_P1_DEFAULT, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadObject_W_Attst []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("attestID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, attestID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_AttestationAlgo("attestAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, attestAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, random, randomLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, data, pdataLen); /* */ + if (0 != tlvRet) { + /* Keys with no read policy will not return TAG1 */ + //goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, attribute, pattributeLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_4, outrandom, poutrandomLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_5, chipId, pchipIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_6, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadRSA(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + SE05x_RSAPubKeyComp_t rsa_key_comp, + uint8_t *data, + size_t *pdataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadRSA []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSAPubKeyComp("rsa_key_comp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, rsa_key_comp); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadRSA_W_Attst(pSe05xSession_t session_ctx, + uint32_t objectID, + uint16_t offset, + uint16_t length, + SE05x_RSAPubKeyComp_t rsa_key_comp, + uint32_t attestID, + SE05x_AttestationAlgo_t attestAlgo, + const uint8_t *random, + size_t randomLen, + uint8_t *data, + size_t *pdataLen, + uint8_t *attribute, + size_t *pattributeLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *outrandom, + size_t *poutrandomLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ_With_Attestation, kSE05x_P1_DEFAULT, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadRSA_W_Attst []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, offset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16Optional("length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, length); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSAPubKeyComp("rsa_key_comp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, rsa_key_comp); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("attestID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, attestID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_AttestationAlgo("attestAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, attestAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, random, randomLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, attribute, pattributeLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_4, outrandom, poutrandomLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_5, chipId, pchipIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_6, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ExportObject( + pSe05xSession_t session_ctx, uint32_t objectID, SE05x_RSAKeyComponent_t rsaKeyComp, uint8_t *data, size_t *pdataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_EXPORT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ExportObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSAKeyComponent("rsaKeyComp", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaKeyComp); + if (0 != tlvRet) { + goto cleanup; + } + + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, data, pdataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadType(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_SecureObjectType_t *ptype, + uint8_t *pisTransient, + const SE05x_AttestationType_t attestation_type) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ | attestation_type, kSE05x_P1_DEFAULT, kSE05x_P2_TYPE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadType []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_SecureObjectType(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, ptype); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, pisTransient); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadSize(pSe05xSession_t session_ctx, uint32_t objectID, uint16_t *psize) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_SIZE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadSize []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U16(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, psize); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadIDList(pSe05xSession_t session_ctx, + uint16_t outputOffset, + uint8_t filter, + uint8_t *pmore, + uint8_t *idlist, + size_t *pidlistLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_DEFAULT, kSE05x_P2_LIST}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadIDList []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U16("output offset", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, outputOffset); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("filter", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, filter); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pmore); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, + &rspIndex, + rspbufLen, + kSE05x_TAG_2, + idlist, + pidlistLen); /* Byte array containing 4-byte identifiers */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (smStatus_t)((pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1])); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CheckObjectExists(pSe05xSession_t session_ctx, uint32_t objectID, SE05x_Result_t *presult) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_EXIST}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CheckObjectExists []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, presult); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DeleteSecureObject(pSe05xSession_t session_ctx, uint32_t objectID) +{ + smStatus_t retStatus = SM_NOT_OK; + + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_DELETE_OBJECT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DeleteSecureObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CreateECCurve(pSe05xSession_t session_ctx, SE05x_ECCurve_t curveID) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_CURVE, kSE05x_P2_CREATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CreateECCurve []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_ECCurve("curve id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, curveID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_SetECCurveParam(pSe05xSession_t session_ctx, + SE05x_ECCurve_t curveID, + SE05x_ECCurveParam_t ecCurveParam, + const uint8_t *inputData, + size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_CURVE, kSE05x_P2_PARAM}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "SetECCurveParam []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_ECCurve("curve id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, curveID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECCurveParam("ecCurveParam", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, ecCurveParam); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetECCurveId(pSe05xSession_t session_ctx, uint32_t objectID, uint8_t *pcurveId) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_CURVE, kSE05x_P2_ID}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetECCurveId []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("object id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pcurveId); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadECCurveList(pSe05xSession_t session_ctx, uint8_t *curveList, size_t *pcurveListLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_CURVE, kSE05x_P2_LIST}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadECCurveList []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, curveList, pcurveListLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DeleteECCurve(pSe05xSession_t session_ctx, SE05x_ECCurve_t curveID) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_CURVE, kSE05x_P2_DELETE_OBJECT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DeleteECCurve []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_ECCurve("curve id", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, curveID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CreateCryptoObject(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + SE05x_CryptoContext_t cryptoContext, + SE05x_CryptoModeSubType_t subtype) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_WRITE, kSE05x_P1_CRYPTO_OBJ, kSE05x_P2_DEFAULT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CreateCryptoObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoContext("cryptoContext", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoContext); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoModeSubType( + "1-byte Crypto Object subtype, either from DigestMode, CipherMode or MACAlgo (depending on TAG_2).", + &pCmdbuf, + &cmdbufLen, + kSE05x_TAG_3, + subtype); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ReadCryptoObjectList(pSe05xSession_t session_ctx, uint8_t *idlist, size_t *pidlistLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_READ, kSE05x_P1_CRYPTO_OBJ, kSE05x_P2_LIST}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ReadCryptoObjectList []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = + tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, idlist, pidlistLen); /* If more ids are present */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DeleteCryptoObject(pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_CRYPTO_OBJ, kSE05x_P2_DELETE_OBJECT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DeleteCryptoObject []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ECDSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECSignatureAlgo_t ecSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_SIGN}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ECDSASign []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECSignatureAlgo("ecSignAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, ecSignAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_EdDSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_EDSignatureAlgo_t edSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_SIGN}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "EdDSASign []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_EDSignatureAlgo("edSignAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, edSignAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ECDAASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECDAASignatureAlgo_t ecdaaSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *randomData, + size_t randomDataLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_SIGN}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ECDAASign []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECDAASignatureAlgo("ecdaaSignAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, ecdaaSignAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("randomData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, randomData, randomDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ECDSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_ECSignatureAlgo_t ecSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_VERIFY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ECDSAVerify []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_ECSignatureAlgo("ecSignAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, ecSignAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("signature", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, signature, signatureLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, presult); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_EdDSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_EDSignatureAlgo_t edSignAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_VERIFY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "EdDSAVerify []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_EDSignatureAlgo("edSignAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, edSignAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("signature", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, signature, signatureLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, presult); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_ECDHGenerateSharedSecret(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *pubKey, + size_t pubKeyLen, + uint8_t *sharedSecret, + size_t *psharedSecretLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_EC, kSE05x_P2_DH}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "ECDHGenerateSharedSecret []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("pubKey", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, pubKey, pubKeyLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, sharedSecret, psharedSecretLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_RSASign(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSASignatureAlgo_t rsaSigningAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *signature, + size_t *psignatureLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_SIGN}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "RSASign []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSASignatureAlgo("rsaSigningAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaSigningAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_RSAVerify(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSASignatureAlgo_t rsaSigningAlgo, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *signature, + size_t signatureLen, + SE05x_Result_t *presult) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_SIGNATURE, kSE05x_P2_VERIFY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "RSAVerify []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSASignatureAlgo("rsaSigningAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaSigningAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("signature", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, signature, signatureLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, presult); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_RSAEncrypt(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *encryptedData, + size_t *pencryptedDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_RSA, kSE05x_P2_ENCRYPT_ONESHOT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "RSAEncrypt []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSAEncryptionAlgo("rsaEncryptionAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaEncryptionAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, encryptedData, pencryptedDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_RSADecrypt(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *decryptedData, + size_t *pdecryptedDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_RSA, kSE05x_P2_DECRYPT_ONESHOT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "RSADecrypt []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_RSAEncryptionAlgo("rsaEncryptionAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, rsaEncryptionAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, decryptedData, pdecryptedDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CipherInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *IV, + size_t IVLen, + const SE05x_Cipher_Oper_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_CIPHER, operation}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CipherInit []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, IV, IVLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CipherUpdate(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_CIPHER, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CipherUpdate []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CipherFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_CIPHER, kSE05x_P2_FINAL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CipherFinal []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_CipherOneShot(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CipherMode_t cipherMode, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *IV, + size_t IVLen, + uint8_t *outputData, + size_t *poutputDataLen, + const SE05x_Cipher_Oper_OneShot_t operation) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_CIPHER, operation}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "CipherOneShot []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CipherMode("cipherMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cipherMode); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, IV, IVLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_MACInit(pSe05xSession_t session_ctx, + uint32_t objectID, + SE05x_CryptoObjectID_t cryptoObjectID, + const SE05x_Mac_Oper_t mac_oper) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_MAC, mac_oper}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "MACInit []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_MACUpdate( + pSe05xSession_t session_ctx, const uint8_t *inputData, size_t inputDataLen, SE05x_CryptoObjectID_t cryptoObjectID) +{ + smStatus_t retStatus = SM_NOT_OK; + + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_MAC, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "MACUpdate []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_MACFinal(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *macValidateData, + size_t macValidateDataLen, + uint8_t *macValue, + size_t *pmacValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_MAC, kSE05x_P2_FINAL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "MACFinal []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8buf("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional( + "macValidateData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, macValidateData, macValidateDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, macValue, pmacValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_MACOneShot_G(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t macOperation, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *macValue, + size_t *pmacValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_MAC, kSE05x_P2_GENERATE_ONESHOT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "MACOneShot_G []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("macOperation", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, macOperation); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, macValue, pmacValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_MACOneShot_V(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t macOperation, + const uint8_t *inputData, + size_t inputDataLen, + const uint8_t *MAC, + size_t MACLen, + uint8_t *macValue, + size_t *pmacValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_MAC, kSE05x_P2_VALIDATE_ONESHOT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "MACOneShot_V []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("macOperation", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, macOperation); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional( + "MAC to verify (when P2=P2_VALIDATE_ONESHOT)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, MAC, MACLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, macValue, pmacValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_HKDF(pSe05xSession_t session_ctx, + uint32_t hmacID, + SE05x_DigestMode_t digestMode, + const uint8_t *salt, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + uint16_t deriveDataLen, + uint8_t *hkdfOuput, + size_t *phkdfOuputLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_HKDF}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "HKDF []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("hmacID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, hmacID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_DigestMode("digestMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, digestMode); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("salt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, salt, saltLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("info", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, info, infoLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("2-byte requested length (L)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, deriveDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, hkdfOuput, phkdfOuputLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_HKDF_Extended(pSe05xSession_t session_ctx, + uint32_t hmacID, + SE05x_DigestMode_t digestMode, + SE05x_HkdfMode_t hkdfMode, + const uint8_t *salt, + size_t saltLen, + uint32_t saltID, + const uint8_t *info, + size_t infoLen, + uint32_t derivedKeyID, + uint16_t deriveDataLen, + uint8_t *hkdfOuput, + size_t *phkdfOuputLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_HKDF}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + hdr.hdr[3] = (hkdfMode == kSE05x_HkdfMode_ExpandOnly ? kSE05x_P2_HKDF_EXPAND_ONLY : kSE05x_P2_HKDF); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "HKDF []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("hmacID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, hmacID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_DigestMode("digestMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, digestMode); + if (0 != tlvRet) { + goto cleanup; + } + if ((salt != NULL) && (hkdfMode != kSE05x_HkdfMode_ExpandOnly)) { + tlvRet = TLVSET_u8bufOptional("salt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, salt, saltLen); + if (0 != tlvRet) { + goto cleanup; + } + } + tlvRet = TLVSET_u8bufOptional("info", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, info, infoLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("2-byte requested length (L)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, deriveDataLen); + if (0 != tlvRet) { + goto cleanup; + } + // Warning: TAGS must be in numerical order, so this cannot be the else statement of (salt != null) + if ((salt == NULL) && (hkdfMode != kSE05x_HkdfMode_ExpandOnly)) { + tlvRet = TLVSET_U32("saltID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, saltID); + if (0 != tlvRet) { + goto cleanup; + } + } + if (hkdfOuput == NULL) { + tlvRet = TLVSET_U32("derivedKeyID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, derivedKeyID); + if (0 != tlvRet) { + goto cleanup; + } + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + if (hkdfOuput == NULL) { + retStatus = SM_NOT_OK; + if (2 == rspbufLen) { + retStatus = (rspbuf[0] << 8) | (rspbuf[1]); + } + } + else { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, hkdfOuput, phkdfOuputLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_PBKDF2(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *salt, + size_t saltLen, + uint16_t count, + uint16_t requestedLen, + uint8_t *derivedSessionKey, + size_t *pderivedSessionKeyLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_PBKDF}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "PBKDF2 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32( + "4-byte password identifier (object type must be HMACKey)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("salt", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, salt, saltLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("count", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, count); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("requestedLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, requestedLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = + tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, derivedSessionKey, pderivedSessionKeyLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFDiversifyKey(pSe05xSession_t session_ctx, + uint32_t masterKeyID, + uint32_t diversifiedKeyID, + const uint8_t *divInputData, + size_t divInputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_DIVERSIFY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFDiversifyKey []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("masterKeyID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, masterKeyID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("diversifiedKeyID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, diversifiedKeyID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("divInputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, divInputData, divInputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFAuthenticateFirstPart1(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_AUTH_FIRST_PART1}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFAuthenticateFirstPart1 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFAuthenticateNonFirstPart1(pSe05xSession_t session_ctx, + uint32_t objectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_AUTH_NONFIRST_PART1}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFAuthenticateFirstPart1 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFAuthenticateFirstPart2(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *outputData, + size_t *poutputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_AUTH_FIRST_PART2}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFAuthenticateFirstPart2 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFAuthenticateNonFirstPart2( + pSe05xSession_t session_ctx, const uint8_t *inputData, size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_AUTH_NONFIRST_PART2}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFAuthenticateNonFirstPart2 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFDumpSessionKeys(pSe05xSession_t session_ctx, uint8_t *sessionData, size_t *psessionDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_DUMP_KEY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFDumpSessionKeys []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, + &rspIndex, + rspbufLen, + kSE05x_TAG_1, + sessionData, + psessionDataLen); /* 38 bytes: KeyID.SesAuthENCKey || KeyID.SesAuthMACKey || TI || Cmd-Ctr */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFChangeKeyPart1(pSe05xSession_t session_ctx, + uint32_t oldObjectID, + uint32_t newObjectID, + uint8_t keySetNr, + uint8_t keyNoDESFire, + uint8_t keyVer, + uint8_t *KeyData, + size_t *pKeyDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_CHANGE_KEY_PART1}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFChangeKeyPart1 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_KeyID("oldObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, oldObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("newObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, newObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("keySetNr", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, keySetNr); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("keyNoDESFire", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, keyNoDESFire); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("keyVer", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, keyVer); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, KeyData, pKeyDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFChangeKeyPart2(pSe05xSession_t session_ctx, const uint8_t *MAC, size_t MACLen, uint8_t *presult) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_CHANGE_KEY_PART2}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFChangeKeyPart2 []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("MAC", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, MAC, MACLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U8(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, presult); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DFKillAuthentication(pSe05xSession_t session_ctx) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_KILL_AUTH}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DFKillAuthentication []"); +#endif /* VERBOSE_APDU_LOGS */ + + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + + return retStatus; +} + +smStatus_t Se05x_API_TLSGenerateRandom(pSe05xSession_t session_ctx, uint8_t *randomValue, size_t *prandomValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_TLS, kSE05x_P2_RANDOM}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TLSGenerateRandom []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, randomValue, prandomValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_TLSCalculatePreMasterSecret(pSe05xSession_t session_ctx, + uint32_t keyPairId, + uint32_t pskId, + uint32_t hmacKeyId, + const uint8_t *inputData, + size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_TLS, kSE05x_P2_TLS_PMS}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TLSCalculatePreMasterSecret []"); +#endif /* VERBOSE_APDU_LOGS */ + if (pskId != 0) { + tlvRet = TLVSET_U32("pskId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, pskId); + if (0 != tlvRet) { + goto cleanup; + } + } + tlvRet = TLVSET_U32("keyPairId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, keyPairId); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("hmacKeyId", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, hmacKeyId); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_TLSPerformPRF(pSe05xSession_t session_ctx, + uint32_t objectID, + uint8_t digestAlgo, + const uint8_t *label, + size_t labelLen, + const uint8_t *random, + size_t randomLen, + uint16_t reqLen, + uint8_t *outputData, + size_t *poutputDataLen, + const SE05x_TLSPerformPRFType_t tlsprf) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_TLS, tlsprf}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "TLSPerformPRF []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("digestAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, digestAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("Label (1 to 64 bytes)", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, label, labelLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("32-byte random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, random, randomLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U16("2-byte requested length", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, reqLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, outputData, poutputDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_I2CM_ExecuteCommandSet(pSe05xSession_t session_ctx, + const uint8_t *inputData, + size_t inputDataLen, + uint32_t attestationID, + uint8_t attestationAlgo, + uint8_t *response, + size_t *presponseLen, + SE05x_TimeStamp_t *ptimeStamp, + uint8_t *freshness, + size_t *pfreshnessLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen, + uint8_t *randomAttst, + size_t randomAttstLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_I2CM_Attestation, kSE05x_P1_DEFAULT, kSE05x_P2_I2CM}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "I2CM_ExecuteCommandSet []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U32("attestationID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, attestationID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_U8("attestationAlgo", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, attestationAlgo); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8bufOptional("freshness random", &pCmdbuf, &cmdbufLen, kSE05x_TAG_7, randomAttst, randomAttstLen); + if (0 != tlvRet) { + goto cleanup; + } + + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, response, presponseLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_4, freshness, pfreshnessLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_5, chipId, pchipIdLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_6, signature, psignatureLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DigestInit(pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_INIT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DigestInit []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DigestUpdate( + pSe05xSession_t session_ctx, SE05x_CryptoObjectID_t cryptoObjectID, const uint8_t *inputData, size_t inputDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_UPDATE}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DigestUpdate []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DigestFinal(pSe05xSession_t session_ctx, + SE05x_CryptoObjectID_t cryptoObjectID, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *cmacValue, + size_t *pcmacValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_FINAL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DigestFinal []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_CryptoObjectID("cryptoObjectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cryptoObjectID); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, cmacValue, pcmacValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DigestOneShot(pSe05xSession_t session_ctx, + uint8_t digestMode, + const uint8_t *inputData, + size_t inputDataLen, + uint8_t *hashValue, + size_t *phashValueLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_DEFAULT, kSE05x_P2_ONESHOT}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DigestOneShot []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U8("digestMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, digestMode); + if (0 != tlvRet) { + goto cleanup; + } + tlvRet = TLVSET_u8buf("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, inputData, inputDataLen); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, hashValue, phashValueLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetVersion(pSe05xSession_t session_ctx, uint8_t *pappletVersion, size_t *appletVersionLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_VERSION}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetVersion []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pappletVersion, appletVersionLen); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetTimestamp(pSe05xSession_t session_ctx, SE05x_TimeStamp_t *ptimeStamp) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_TIME}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetTimestamp []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTxRx_s_Case2(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_TimeStamp(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, ptimeStamp); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetFreeMemory(pSe05xSession_t session_ctx, SE05x_MemoryType_t memoryType, uint16_t *pfreeMem) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_MEMORY}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetFreeMemory []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_MemoryType("memoryType", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, memoryType); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_U16(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pfreeMem); /* - */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_GetRandom(pSe05xSession_t session_ctx, uint16_t size, uint8_t *randomData, size_t *prandomDataLen) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_RANDOM}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = &cmdbuf[0]; + int tlvRet = 0; + uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "GetRandom []"); +#endif /* VERBOSE_APDU_LOGS */ + tlvRet = TLVSET_U16("size", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, size); + if (0 != tlvRet) { + goto cleanup; + } + retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + if (retStatus == SM_OK) { + retStatus = SM_NOT_OK; + size_t rspIndex = 0; + tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, randomData, prandomDataLen); /* */ + if (0 != tlvRet) { + goto cleanup; + } + if ((rspIndex + 2) == rspbufLen) { + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + } + } + +cleanup: + return retStatus; +} + +smStatus_t Se05x_API_DeleteAll(pSe05xSession_t session_ctx) +{ + smStatus_t retStatus = SM_NOT_OK; + tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_MGMT, kSE05x_P1_DEFAULT, kSE05x_P2_DELETE_ALL}}; + uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; + size_t cmdbufLen = 0; +#if VERBOSE_APDU_LOGS + NEWLINE(); + nLog("APDU", NX_LEVEL_DEBUG, "DeleteAll []"); +#endif /* VERBOSE_APDU_LOGS */ + retStatus = DoAPDUTx_s_Case3(session_ctx, &hdr, cmdbuf, cmdbufLen); + return retStatus; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt new file mode 100644 index 00000000000..807fd387954 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt @@ -0,0 +1,207 @@ +CMAKE_MINIMUM_REQUIRED(VERSION 3.5.0) + +project (ssl2_client) + +FILE( + GLOB + MBEDTLS_SOURCES + ../ext/mbedtls/library/aes.c + ../ext/mbedtls/library/aesni.c + ../ext/mbedtls/library/arc4.c + ../ext/mbedtls/library/aria.c + ../ext/mbedtls/library/asn1parse.c + ../ext/mbedtls/library/asn1write.c + ../ext/mbedtls/library/base64.c + ../ext/mbedtls/library/bignum.c + ../ext/mbedtls/library/blowfish.c + ../ext/mbedtls/library/camellia.c + ../ext/mbedtls/library/ccm.c + ../ext/mbedtls/library/certs.c + ../ext/mbedtls/library/chacha20.c + ../ext/mbedtls/library/chachapoly.c + ../ext/mbedtls/library/cipher.c + ../ext/mbedtls/library/cipher_wrap.c + ../ext/mbedtls/library/cmac.c + ../ext/mbedtls/library/ctr_drbg.c + ../ext/mbedtls/library/debug.c + ../ext/mbedtls/library/des.c + ../ext/mbedtls/library/dhm.c + #../ext/mbedtls/library/ecdh.c + ../ext/mbedtls/library/ecdsa.c + ../ext/mbedtls/library/ecjpake.c + ../ext/mbedtls/library/ecp.c + ../ext/mbedtls/library/ecp_curves.c + ../ext/mbedtls/library/entropy.c + ../ext/mbedtls/library/entropy_poll.c + ../ext/mbedtls/library/error.c + ../ext/mbedtls/library/gcm.c + ../ext/mbedtls/library/havege.c + ../ext/mbedtls/library/hkdf.c + ../ext/mbedtls/library/hmac_drbg.c + ../ext/mbedtls/library/md.c + ../ext/mbedtls/library/md2.c + ../ext/mbedtls/library/md4.c + ../ext/mbedtls/library/md5.c + ../ext/mbedtls/library/md_wrap.c + ../ext/mbedtls/library/memory_buffer_alloc.c + ../ext/mbedtls/library/net_sockets.c + ../ext/mbedtls/library/nist_kw.c + ../ext/mbedtls/library/oid.c + ../ext/mbedtls/library/padlock.c + ../ext/mbedtls/library/pem.c + ../ext/mbedtls/library/pk.c + ../ext/mbedtls/library/pk_wrap.c + ../ext/mbedtls/library/pkcs11.c + ../ext/mbedtls/library/pkcs12.c + ../ext/mbedtls/library/pkcs5.c + ../ext/mbedtls/library/pkparse.c + ../ext/mbedtls/library/pkwrite.c + ../ext/mbedtls/library/platform.c + ../ext/mbedtls/library/platform_util.c + ../ext/mbedtls/library/poly1305.c + ../ext/mbedtls/library/ripemd160.c + ../ext/mbedtls/library/rsa.c + ../ext/mbedtls/library/rsa_internal.c + ../ext/mbedtls/library/sha1.c + ../ext/mbedtls/library/sha256.c + ../ext/mbedtls/library/sha512.c + ../ext/mbedtls/library/ssl_cache.c + ../ext/mbedtls/library/ssl_ciphersuites.c + ../ext/mbedtls/library/ssl_cli.c + ../ext/mbedtls/library/ssl_cookie.c + ../ext/mbedtls/library/ssl_srv.c + ../ext/mbedtls/library/ssl_ticket.c + ../ext/mbedtls/library/ssl_tls.c + ../ext/mbedtls/library/threading.c + ../ext/mbedtls/library/timing.c + ../ext/mbedtls/library/version.c + ../ext/mbedtls/library/version_features.c + ../ext/mbedtls/library/x509.c + ../ext/mbedtls/library/x509_create.c + ../ext/mbedtls/library/x509_crl.c + ../ext/mbedtls/library/x509_crt.c + ../ext/mbedtls/library/x509_csr.c + ../ext/mbedtls/library/x509write_crt.c + ../ext/mbedtls/library/x509write_csr.c + ../ext/mbedtls/library/xtea.c + ) + +FILE( + GLOB + SE_SOURCES + + ../sss/ex/src/ex_sss_boot.c + ../sss/ex/src/ex_sss_boot_connectstring.c + ../sss/ex/src/ex_sss_se05x.c + ../sss/ex/src/ex_sss_se05x_auth.c + ../sss/src/*.c + + ../sss/src/se05x/fsl_sss_se05x_apis.c + ../sss/src/se05x/fsl_sss_se05x_mw.c + ../sss/src/se05x/fsl_sss_se05x_policy.c + + ../hostlib/hostLib/libCommon/infra/*.c + + ../hostlib/hostLib/libCommon/log/nxLog.c + + ../hostlib/hostLib/libCommon/smCom/smCom.c + ../hostlib/hostLib/platform/rsp/se05x_reset.c + ../hostlib/hostLib/platform/generic/sm_timer.c + + ../hostlib/hostLib/se05x/src/se05x_ECC_curves.c + ../hostlib/hostLib/se05x/src/se05x_mw.c + ../hostlib/hostLib/se05x/src/se05x_tlv.c + ../hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c + + # T1oI2C files + ../hostlib/hostLib/libCommon/smCom/smComT1oI2C.c + ../hostlib/hostLib/libCommon/smCom/T1oI2C/*.c + ../hostlib/hostLib/platform/linux/i2c_a7.c + + ##### Mbedtls Host crypto support + ../sss/src/mbedtls/fsl_sss_mbedtls_apis.c + ../sss/src/keystore/keystore_pc.c + ../sss/src/keystore/keystore_cmn.c + + ##### Authenticated session to se05x + #../sss/ex/src/ex_sss_scp03_auth.c + #../sss/src/se05x/fsl_sss_se05x_eckey.c + #../sss/src/se05x/fsl_sss_se05x_scp03.c + #../hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c + + ../hostlib/hostLib/mbedtls/src/ecdh_alt.c + ../hostlib/hostLib/mbedtls/src/rsa_alt.c + ../sss/plugin/mbedtls/ecdh_alt_ax.c + ../sss/plugin/mbedtls/sss_mbedtls.c + ../sss/plugin/mbedtls/sss_mbedtls_rsa.c + + ../sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c + ../sss/plugin/mbedtls/port/ksdk/ecp_alt.c +) + +add_executable(${PROJECT_NAME} ../sss/ex/mbedtls/ex_sss_ssl2.c ${MBEDTLS_SOURCES} ${SE_SOURCES}) + +FILE( + GLOB + INC_DIR + ../sss/inc + ../sss/port/default + ../sss/ex/src + ../sss/ex/inc + ../hostlib/hostLib/inc + ../hostlib/hostLib/libCommon/infra + ../hostlib/hostLib/libCommon/smCom + ../hostlib/hostLib/libCommon/log + ../hostlib/hostLib/libCommon/smCom/T1oI2C + ../hostlib/hostLib/se05x_03_xx_xx + ../hostlib/hostLib/platform/inc + ../hostlib/hostLib/libCommon/smCom + ../sss/plugin/mbedtls + ../ext/mbedtls/include +) + +TARGET_INCLUDE_DIRECTORIES( + ${PROJECT_NAME} + PUBLIC + ../ + ${INC_DIR} + ) + + +TARGET_COMPILE_DEFINITIONS( + ${PROJECT_NAME} + PUBLIC + MBEDTLS_CONFIG_FILE=\"sss_mbedtls_x86_config.h\" +) + +ADD_DEFINITIONS(-DSSS_USE_FTR_FILE) +ADD_DEFINITIONS(-DSMCOM_T1oI2C) +ADD_DEFINITIONS(-DT1oI2C) +ADD_DEFINITIONS(-DT1oI2C_UM11225) + + + +######################################################################################### + + +project (ssl2_server) + +add_executable( ${PROJECT_NAME} + ../ext/mbedtls/programs/ssl/ssl_server2.c + ../ext/mbedtls/programs/ssl/query_config.c + ${SE_SOURCES} + ${MBEDTLS_SOURCES} + ) + +TARGET_INCLUDE_DIRECTORIES( + ${PROJECT_NAME} + PUBLIC + ../ + ${INC_DIR} + ) + +TARGET_COMPILE_DEFINITIONS( + ${PROJECT_NAME} + PUBLIC + MBEDTLS_CONFIG_FILE=\"sss_mbedtls_x86_config.h\" +) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c new file mode 100644 index 00000000000..97f9854fb7f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c @@ -0,0 +1,175 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#include +#include +#include +#include + +/* ************************************************************************** */ +/* Local Defines */ +/* ************************************************************************** */ +#define EC_KEY_BIT_LEN 256 +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* clang-format off */ +const uint8_t keyPairData[] = { 0x30, 0x81, 0x87, 0x02, 0x01, 0x00, 0x30, 0x13, + 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x02, + 0x01, 0x06, 0x08, 0x2A, 0x86, 0x48, 0xCE, 0x3D, + 0x03, 0x01, 0x07, 0x04, 0x6D, 0x30, 0x6B, 0x02, + 0x01, 0x01, 0x04, 0x20, 0x78, 0xE5, 0x20, 0x6A, + 0x08, 0xED, 0xD2, 0x52, 0x36, 0x33, 0x8A, 0x24, + 0x84, 0xE4, 0x2F, 0x1F, 0x7D, 0x1F, 0x6D, 0x94, + 0x37, 0xA9, 0x95, 0x86, 0xDA, 0xFC, 0xD2, 0x23, + 0x6F, 0xA2, 0x87, 0x35, 0xA1, 0x44, 0x03, 0x42, + 0x00, 0x04, 0xED, 0xA7, 0xE9, 0x0B, 0xF9, 0x20, + 0xCF, 0xFB, 0x9D, 0xF6, 0xDB, 0xCE, 0xF7, 0x20, + 0xE1, 0x23, 0x8B, 0x3C, 0xEE, 0x84, 0x86, 0xD2, + 0x50, 0xE4, 0xDF, 0x30, 0x11, 0x50, 0x1A, 0x15, + 0x08, 0xA6, 0x2E, 0xD7, 0x49, 0x52, 0x78, 0x63, + 0x6E, 0x61, 0xE8, 0x5F, 0xED, 0xB0, 0x6D, 0x87, + 0x92, 0x0A, 0x04, 0x19, 0x14, 0xFE, 0x76, 0x63, + 0x55, 0xDF, 0xBD, 0x68, 0x61, 0x59, 0x31, 0x8E, + 0x68, 0x7C }; + +const uint8_t extPubKeyData[] = { + 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x08, 0x2A, + 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07, 0x03, + 0x42, 0x00, 0x04, 0xED, 0xA7, 0xE9, 0x0B, 0xF9, + 0x20, 0xCF, 0xFB, 0x9D, 0xF6, 0xDB, 0xCE, 0xF7, + 0x20, 0xE1, 0x23, 0x8B, 0x3C, 0xEE, 0x84, 0x86, + 0xD2, 0x50, 0xE4, 0xDF, 0x30, 0x11, 0x50, 0x1A, + 0x15, 0x08, 0xA6, 0x2E, 0xD7, 0x49, 0x52, 0x78, + 0x63, 0x6E, 0x61, 0xE8, 0x5F, 0xED, 0xB0, 0x6D, + 0x87, 0x92, 0x0A, 0x04, 0x19, 0x14, 0xFE, 0x76, + 0x63, 0x55, 0xDF, 0xBD, 0x68, 0x61, 0x59, 0x31, + 0x8E, 0x68, 0x7C +}; + +/* clang-format on */ + +static ex_sss_boot_ctx_t gex_sss_ecc_boot_ctx; + +/* ************************************************************************** */ +/* Static function declarations */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Private Functions */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Public Functions */ +/* ************************************************************************** */ + +#define EX_SSS_BOOT_PCONTEXT (&gex_sss_ecc_boot_ctx) +#define EX_SSS_BOOT_DO_ERASE 1 +#define EX_SSS_BOOT_EXPOSE_ARGC_ARGV 0 + +#include + +sss_status_t ex_sss_entry(ex_sss_boot_ctx_t *pCtx) +{ + sss_status_t status = kStatus_SSS_Success; + uint8_t digest[32] = "Hello World"; + size_t digestLen; + uint8_t signature[256] = {0}; + size_t signatureLen; + sss_object_t keyPair; + sss_object_t key_pub; + sss_asymmetric_t ctx_asymm = {0}; + sss_asymmetric_t ctx_verify = {0}; + + LOG_I("Running Elliptic Curve Cryptography Example ex_sss_ecc.c"); + + digestLen = sizeof(digest); + + /* doc:start ex_sss_asymmetric-allocate-key */ + /* Pre-requisite for Signing Part*/ + status = sss_key_object_init(&keyPair, &pCtx->ks); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_key_object_allocate_handle(&keyPair, + MAKE_TEST_ID(__LINE__), + kSSS_KeyPart_Pair, + kSSS_CipherType_EC_NIST_P, + sizeof(keyPairData), + kKeyObject_Mode_Persistent); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_key_store_set_key(&pCtx->ks, &keyPair, keyPairData, sizeof(keyPairData), EC_KEY_BIT_LEN, NULL, 0); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + /* doc:end ex_sss_asymmetric-allocate-key */ + + /* doc:start ex_sss_asymmetric-asym-sign */ + status = sss_asymmetric_context_init(&ctx_asymm, &pCtx->session, &keyPair, kAlgorithm_SSS_SHA256, kMode_SSS_Sign); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + signatureLen = sizeof(signature); + /* Do Signing */ + LOG_I("Do Signing"); + LOG_MAU8_I("digest", digest, digestLen); + status = sss_asymmetric_sign_digest(&ctx_asymm, digest, digestLen, signature, &signatureLen); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + LOG_MAU8_I("signature", signature, signatureLen); + LOG_I("Signing Successful !!!"); + sss_asymmetric_context_free(&ctx_asymm); + /* doc:end ex_sss_asymmetric-asym-sign */ + + /* Pre requiste for Verifying Part*/ + status = sss_key_object_init(&key_pub, &pCtx->ks); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_key_object_allocate_handle(&key_pub, + MAKE_TEST_ID(__LINE__), + kSSS_KeyPart_Public, + kSSS_CipherType_EC_NIST_P, + sizeof(extPubKeyData), + kKeyObject_Mode_Persistent); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_key_store_set_key(&pCtx->ks, &key_pub, extPubKeyData, sizeof(extPubKeyData), EC_KEY_BIT_LEN, NULL, 0); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + /* doc:start ex_sss_asymmetric-asym-verify */ + status = + sss_asymmetric_context_init(&ctx_verify, &pCtx->session, &key_pub, kAlgorithm_SSS_SHA256, kMode_SSS_Verify); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + LOG_I("Do Verify"); + LOG_MAU8_I("digest", digest, digestLen); + LOG_MAU8_I("signature", signature, signatureLen); + status = sss_asymmetric_verify_digest(&ctx_verify, digest, digestLen, signature, signatureLen); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + LOG_I("Verification Successful !!!"); + /* doc:end ex_sss_asymmetric-asym-verify */ + +cleanup: + if (kStatus_SSS_Success == status) { + LOG_I("ex_sss_ecc Example Success !!!..."); + } + else { + LOG_E("ex_sss_ecc Example Failed !!!..."); + } + if (ctx_asymm.session != NULL) + sss_asymmetric_context_free(&ctx_asymm); + if (ctx_verify.session != NULL) + sss_asymmetric_context_free(&ctx_verify); + return status; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h new file mode 100644 index 00000000000..be9e9f1ce4d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h @@ -0,0 +1,124 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EX_SCP03_PUF_H__ +#define __EX_SCP03_PUF_H__ + +#if defined(SECURE_WORLD) + +/** + * Activation Code to start PUF. + * This is used only for testing purposes, actual + * activation code should be stored in PFR and always + * read from PFR before PUF_Start. + * + * AC is different for all PUFs, this code cannot be used + * on any other board. + */ + +#define ACTIVATION_CODE_TESTING_LOCAL \ + { \ + 0xA2, 0x7D, 0xF7, 0x38, 0x15, 0x8E, 0x1F, 0xE1, 0x8D, 0x9F, 0x45, 0x6F, 0x8A, 0x2C, 0xA5, 0x8D, 0xC2, 0x15, \ + 0xD1, 0x9A, 0x13, 0xFA, 0xD8, 0x5E, 0x36, 0x00, 0x9A, 0xDD, 0x42, 0xB6, 0x4F, 0x6D, 0x08, 0xFB, 0x89, \ + 0x37, 0x3C, 0x1D, 0xAF, 0xD5, 0x63, 0xE1, 0xE8, 0xC8, 0x93, 0x93, 0x5C, 0xD8, 0x49, 0xF3, 0x2D, 0xD1, \ + 0xF9, 0x3D, 0x74, 0x97, 0x37, 0xBD, 0xC5, 0xBE, 0x04, 0x6A, 0x5E, 0xBC, 0xF3, 0x7D, 0xBD, 0xE0, 0xC6, \ + 0x3E, 0x66, 0x5F, 0xC0, 0x5C, 0x57, 0x09, 0x57, 0x8C, 0x45, 0x30, 0x12, 0x6F, 0xFA, 0x3B, 0xDB, 0x40, \ + 0xCE, 0xB8, 0xF2, 0x6E, 0x9B, 0xF1, 0x16, 0x74, 0x2A, 0x34, 0x7A, 0x6F, 0xB6, 0xEF, 0xA3, 0xD3, 0x8C, \ + 0xF0, 0x03, 0xB8, 0xB8, 0x8B, 0x2F, 0x27, 0x16, 0xDD, 0xE0, 0x92, 0xC8, 0xD7, 0x4E, 0x4A, 0x44, 0xBC, \ + 0x4D, 0x7C, 0x7E, 0xA0, 0xE7, 0x8E, 0xA3, 0x5D, 0xFB, 0x53, 0x4D, 0x67, 0x74, 0x4B, 0x65, 0x1E, 0xC1, \ + 0x57, 0x7C, 0x67, 0xB3, 0x58, 0x42, 0x4F, 0x36, 0xF9, 0x0C, 0x77, 0x58, 0x6C, 0x9A, 0x04, 0x15, 0x0D, \ + 0x71, 0x55, 0x3F, 0x8E, 0x69, 0x12, 0x2C, 0xFC, 0xCA, 0x80, 0xD7, 0xC7, 0x27, 0xFE, 0xEA, 0x6E, 0x7D, \ + 0xFC, 0x84, 0x50, 0x0F, 0x00, 0x71, 0x09, 0x8F, 0x2C, 0x91, 0x57, 0xAF, 0xE7, 0xF3, 0x11, 0xA8, 0xA2, \ + 0x76, 0xF2, 0x1D, 0x88, 0xA5, 0x2F, 0x2E, 0x09, 0x02, 0xB3, 0xC4, 0xD5, 0x1D, 0x39, 0x20, 0x3C, 0x36, \ + 0x51, 0x19, 0x9C, 0xFB, 0xC9, 0x33, 0xD6, 0xBE, 0x93, 0xBD, 0x68, 0x6D, 0x51, 0x30, 0xA9, 0x11, 0x98, \ + 0xAD, 0x84, 0xC5, 0x50, 0x9A, 0x7E, 0x11, 0x8E, 0x43, 0x78, 0x79, 0x3A, 0xE2, 0xF0, 0x52, 0xB8, 0xDD, \ + 0x4E, 0xD3, 0xB8, 0xE0, 0xF9, 0xA6, 0x34, 0xF2, 0xE1, 0xA3, 0xEC, 0x92, 0x46, 0xE4, 0xAE, 0x09, 0xFB, \ + 0x2A, 0x1F, 0x6F, 0xD0, 0x23, 0x0F, 0xE8, 0x0D, 0x52, 0x98, 0x88, 0xA3, 0x15, 0xC9, 0x01, 0x94, 0x61, \ + 0x1D, 0xB7, 0x2F, 0x5F, 0xB2, 0x94, 0x5D, 0x01, 0x54, 0x61, 0xB1, 0xF2, 0xB6, 0xF3, 0x79, 0x22, 0x2F, \ + 0x9C, 0x44, 0xAB, 0xD5, 0x0D, 0xC8, 0x42, 0x06, 0x03, 0x33, 0x8E, 0x52, 0xDF, 0xC8, 0xDE, 0x18, 0xF6, \ + 0xD6, 0x73, 0x64, 0x70, 0x94, 0xC5, 0x0F, 0x64, 0x3E, 0x7E, 0x14, 0xE9, 0xF4, 0x4C, 0xF9, 0x5E, 0x5A, \ + 0xC6, 0x39, 0xF7, 0xA9, 0x72, 0xB5, 0x08, 0x51, 0x11, 0x7A, 0xDB, 0x8A, 0x72, 0xF9, 0xF7, 0x23, 0x59, \ + 0xAC, 0x9A, 0x61, 0x2F, 0xA6, 0xDB, 0x84, 0xBD, 0x7C, 0x7E, 0x1A, 0xEA, 0xFB, 0x6B, 0xC8, 0x5E, 0xE3, \ + 0x04, 0xBF, 0x13, 0x05, 0xFA, 0xDA, 0xF7, 0x96, 0x91, 0x6A, 0x40, 0xA8, 0xC7, 0x77, 0xC6, 0xCB, 0xAC, \ + 0x2C, 0xD9, 0xCD, 0x6C, 0x6D, 0xA4, 0x19, 0x50, 0x07, 0x8C, 0x72, 0xEE, 0x0F, 0x33, 0xA2, 0x48, 0x20, \ + 0x24, 0x5E, 0x93, 0xE7, 0xC2, 0x73, 0x02, 0x00, 0x87, 0xFD, 0x11, 0x2A, 0x8F, 0x9F, 0xD9, 0xFB, 0xF7, \ + 0xAC, 0x0D, 0x77, 0xBB, 0x1C, 0xF8, 0x55, 0xE7, 0x10, 0x05, 0x5C, 0x18, 0x23, 0x26, 0xDD, 0x60, 0xDD, \ + 0xFF, 0xAB, 0x8D, 0x68, 0xDE, 0x7E, 0xE8, 0xB3, 0xDE, 0xA2, 0x6D, 0x35, 0x7C, 0x9B, 0x31, 0x11, 0x5E, \ + 0xEC, 0xB5, 0x51, 0x00, 0x1C, 0x5C, 0x65, 0xA3, 0xC7, 0x35, 0xFA, 0x37, 0x1C, 0xDF, 0xD0, 0x26, 0xA0, \ + 0x44, 0x57, 0xD4, 0xC9, 0xCE, 0xE5, 0x2B, 0xB4, 0x06, 0xF6, 0x9B, 0xE9, 0xE5, 0x66, 0x6F, 0x24, 0x30, \ + 0xBF, 0x6D, 0x8E, 0x2E, 0xE7, 0x13, 0x94, 0x0B, 0x6F, 0x1A, 0x7A, 0x77, 0xAB, 0xD9, 0xB4, 0x2D, 0xFF, \ + 0x4F, 0xB4, 0xC7, 0x04, 0x2E, 0xF7, 0x1B, 0xF6, 0x66, 0x2D, 0xA7, 0x59, 0x99, 0x57, 0x5F, 0x2C, 0x1A, \ + 0x75, 0x81, 0xF3, 0xAC, 0x41, 0x7A, 0xFB, 0x47, 0xF3, 0x0E, 0xDC, 0x9E, 0xAB, 0xED, 0x18, 0xA4, 0x43, \ + 0xCC, 0x80, 0xFB, 0x6E, 0x53, 0xD6, 0x91, 0x9F, 0x30, 0x80, 0xEA, 0x04, 0x42, 0x7B, 0x94, 0x62, 0x34, \ + 0x25, 0xEA, 0xA4, 0x9A, 0x72, 0x9B, 0x81, 0x47, 0xA5, 0xA0, 0xE9, 0x07, 0xBB, 0x09, 0xDA, 0x4C, 0x51, \ + 0x61, 0x00, 0xC7, 0x1E, 0x0E, 0x37, 0x7F, 0xF2, 0x2B, 0x82, 0xD0, 0xF6, 0x18, 0xFA, 0x56, 0xC7, 0x2D, \ + 0xEB, 0x22, 0xFC, 0xDC, 0x97, 0xDF, 0x65, 0xBC, 0xB4, 0x2A, 0xB3, 0x10, 0xFF, 0xC5, 0x7A, 0x9F, 0xF8, \ + 0xCD, 0xB9, 0x84, 0x60, 0x9E, 0x92, 0xFD, 0xF9, 0x16, 0x90, 0xB2, 0x81, 0x52, 0x7E, 0x03, 0xBC, 0x91, \ + 0xD8, 0x9A, 0x0C, 0xC1, 0x99, 0x93, 0x42, 0x67, 0x96, 0x3C, 0x01, 0x55, 0x37, 0x86, 0xD2, 0x37, 0xE6, \ + 0x07, 0xC8, 0x74, 0x41, 0xCD, 0x88, 0x93, 0x51, 0xBA, 0x9B, 0xB0, 0x00, 0x6D, 0x14, 0x4F, 0xD8, 0x7F, \ + 0x77, 0x9F, 0x7E, 0x15, 0xE2, 0xA9, 0xA0, 0xC8, 0x7F, 0xD4, 0xFA, 0xCD, 0x60, 0x91, 0xA8, 0x9B, 0xB7, \ + 0x41, 0x6E, 0x07, 0xCB, 0x21, 0xE9, 0x42, 0xC1, 0xB7, 0x6E, 0x63, 0x68, 0x90, 0x0E, 0x29, 0xBB, 0x0D, \ + 0x83, 0x32, 0xD0, 0x71, 0x5A, 0xE1, 0xEC, 0x21, 0x0E, 0x78, 0xC6, 0x60, 0x3D, 0x78, 0xFA, 0x5C, 0xEE, \ + 0xAC, 0x29, 0xC4, 0xE4, 0x0F, 0x92, 0x27, 0xBE, 0xD0, 0xA5, 0x1E, 0xF4, 0xDD, 0xAB, 0xB9, 0x22, 0xA0, \ + 0x7E, 0xFE, 0x47, 0x1D, 0x62, 0x69, 0x9D, 0x8D, 0x01, 0xCF, 0x5D, 0xC1, 0xAD, 0x50, 0x61, 0x77, 0x91, \ + 0x39, 0x0A, 0x97, 0x92, 0x92, 0x66, 0x9F, 0xE5, 0x57, 0x26, 0xD7, 0x01, 0xC3, 0xEF, 0x23, 0xCC, 0x98, \ + 0xB9, 0x39, 0x20, 0x6D, 0xC8, 0x10, 0x2D, 0xB8, 0x18, 0x2E, 0xC2, 0x25, 0x83, 0x88, 0x2A, 0xDF, 0xC7, \ + 0xBF, 0xBC, 0xE8, 0xA9, 0x7B, 0xD4, 0x19, 0x0E, 0xEF, 0x4E, 0xE4, 0xBA, 0x8B, 0x7C, 0xDB, 0x6A, 0x2A, \ + 0xEA, 0xA3, 0xED, 0xDD, 0xCF, 0x00, 0x85, 0x4B, 0xA0, 0xC2, 0xBC, 0x72, 0x39, 0x3D, 0x6A, 0x5C, 0x9D, \ + 0xDA, 0x8C, 0x1C, 0x67, 0x9A, 0xDC, 0x73, 0xF3, 0x9E, 0x2E, 0xA2, 0x0C, 0x42, 0x86, 0xE4, 0xA6, 0x3F, \ + 0x05, 0x57, 0xD0, 0xE4, 0xA7, 0x75, 0x5B, 0xA8, 0xA4, 0xE3, 0x1A, 0x57, 0x02, 0xBD, 0xE7, 0xDA, 0x32, \ + 0xA2, 0x69, 0xAA, 0xEC, 0xEB, 0xAF, 0x42, 0x8C, 0x72, 0xE4, 0xB1, 0x15, 0x26, 0x25, 0x7B, 0x29, 0xF8, \ + 0x97, 0x3F, 0x12, 0x29, 0x4F, 0x0B, 0xA5, 0x2E, 0x74, 0x8F, 0xA9, 0xF4, 0xED, 0x00, 0x42, 0x73, 0x92, \ + 0x59, 0x0B, 0xA8, 0x98, 0xF7, 0x7E, 0xE7, 0x09, 0xEE, 0xA4, 0x91, 0x2F, 0x93, 0xB7, 0x91, 0x1A, 0xBF, \ + 0x94, 0x96, 0xF9, 0xCC, 0xA4, 0x16, 0xDA, 0x01, 0x7C, 0x1A, 0xF9, 0xC3, 0xE5, 0x8A, 0xCC, 0x96, 0x54, \ + 0xC2, 0xDE, 0x1E, 0x04, 0x98, 0xA3, 0x6B, 0x55, 0x61, 0xB8, 0x1C, 0x57, 0x70, 0x9E, 0xAB, 0x48, 0xEA, \ + 0xD7, 0x18, 0x0A, 0xC8, 0x45, 0xB1, 0xC8, 0x6A, 0x5A, 0xAA, 0xB6, 0xDE, 0x76, 0x76, 0x2B, 0x82, 0x45, \ + 0x7E, 0x17, 0x83, 0x51, 0xAA, 0x13, 0xC8, 0xBF, 0x30, 0x62, 0xB9, 0xAE, 0xB7, 0x74, 0x55, 0xC7, 0x24, \ + 0x94, 0x3C, 0x1C, 0xA5, 0x1E, 0x94, 0x70, 0x71, 0xAF, 0x29, 0x5B, 0x79, 0xF1, 0xAF, 0x31, 0x30, 0x82, \ + 0x0F, 0x3C, 0x5A, 0x05, 0x1D, 0x88, 0x7D, 0x63, 0x4C, 0xCE, 0x7D, 0xFD, 0x07, 0x17, 0xB0, 0xC8, 0x13, \ + 0xC4, 0x7B, 0x0F, 0xBD, 0xFC, 0x5E, 0x58, 0x14, 0xD6, 0x17, 0x10, 0x5D, 0xDB, 0x54, 0x60, 0x3C, 0x68, \ + 0x0B, 0x54, 0x84, 0xFA, 0xAB, 0xD0, 0x02, 0xFE, 0x66, 0xB3, 0xEC, 0xDF, 0x06, 0x97, 0xC4, 0x0C, 0xDC, \ + 0xEC, 0x4B, 0x9B, 0x6C, 0x3A, 0x04, 0x72, 0x84, 0xA0, 0x9D, 0xC2, 0x6A, 0xB5, 0x69, 0x81, 0x30, 0x57, \ + 0x5F, 0x40, 0x81, 0x4C, 0x57, 0xA8, 0x0B, 0x41, 0x24, 0x68, 0x36, 0x8E, 0xFD, 0x2A, 0xE0, 0x69, 0xF5, \ + 0x3E, 0x56, 0x52, 0xF4, 0x5A, 0xFF, 0xF6, 0x32, 0xC2, 0xAE, 0xF4, 0xCC, 0x88, 0xA6, 0x5F, 0xFB, 0xFB, \ + 0x6B, 0xD1, 0xFF, 0x65, 0x31, 0xE9, 0x38, 0x1B, 0xCC, 0xA0, 0x47, 0xC0, 0x0D, 0x3C, 0x10, 0x5D, 0xB3, \ + 0x46, 0x63, 0x2A, 0xC4, 0x74, 0xCA, 0xC4, 0x3E, 0x49, 0xEB, 0x0A, 0xE3, 0xD6, 0xF1, 0xE8, 0xF5, 0xC3, \ + 0x9C, 0xD2, 0xE6, 0xEF, 0xCB, 0x29, 0xAF, 0x5D, 0xEA, 0x27, 0x1D, 0x8B, 0x8F, 0xEB, 0x33, 0x9E, 0x57, \ + 0xD4, 0x55, 0xD8, 0xB0, 0x34, 0x43, 0xA4, 0xF6, 0x38, 0x8B, 0x66, 0x1E, 0x30, 0xA1, 0x7D, 0xAF, 0xC2, \ + 0x1E, 0x6B, 0xFD, 0x73, 0x05, 0x39, 0xB5, 0x06, 0xEF, 0x93, 0x1D, 0x7A, 0xF7, 0x15, 0x74, 0x3A, 0x72, \ + 0x06, 0x6F, 0x9F, 0xA8, 0xCF, 0x4D, 0x2A, 0x8C, 0xB4, 0x7F, 0xB9, 0x40, 0xE7, 0x2E, 0x8B, 0xC1, 0xD9, \ + 0x84, 0xFF, 0x5E, 0x78, 0x5D, 0x6C, 0x36, 0xDC, 0xD5, 0x92, 0x94, 0x17, 0x11, 0x0E, 0xE0, 0xE2, 0xFD, \ + 0xC0, \ + } + +#define KEY_CODE_ENC \ + { \ + 0x00, 0x00, 0x00, 0x02, 0xE2, 0x9B, 0x12, 0x4E, 0xF2, 0xDC, 0xA8, 0xE3, 0x2D, 0x7A, 0xB3, 0x98, 0x56, 0x3E, \ + 0x0A, 0x0F, 0x66, 0xCF, 0xB2, 0x37, 0x31, 0xBD, 0xD4, 0xD4, 0x42, 0x27, 0x73, 0x92, 0x23, 0xCC, 0xA7, \ + 0xE7, 0x51, 0xA4, 0x99, 0x91, 0x19, 0x68, 0x74, 0x92, 0xC9, 0x9D, 0xF2, 0x9F, 0x5B, 0x6E, 0x5E, 0x81 \ + } + +#define KEY_CODE_MAC \ + { \ + 0x00, 0x00, 0x00, 0x02, 0x81, 0x54, 0x3E, 0x5D, 0x47, 0xDE, 0x23, 0x7C, 0x00, 0x1B, 0x16, 0xBE, 0x1B, 0x05, \ + 0xED, 0xD2, 0xD5, 0xB2, 0x4D, 0x3C, 0xD3, 0xDD, 0xD5, 0xA9, 0x40, 0x5E, 0x7D, 0x90, 0x73, 0x74, 0xDE, \ + 0x05, 0xAC, 0x76, 0x7D, 0x87, 0xB6, 0x5E, 0x1F, 0x8E, 0xB5, 0x93, 0x53, 0x41, 0x51, 0x27, 0xE9, 0xF9 \ + } + +#define KEY_CODE_DEK \ + { \ + 0x00, 0x00, 0x00, 0x02, 0x88, 0xE0, 0x9A, 0x2B, 0x23, 0x77, 0xC3, 0xF5, 0xEE, 0x28, 0x4F, 0x7C, 0x5B, 0xD8, \ + 0x9C, 0xF5, 0xA8, 0xC9, 0xE4, 0xE3, 0xDC, 0x8D, 0x34, 0x3C, 0x00, 0x39, 0x7E, 0xA3, 0x35, 0x39, 0xFD, \ + 0xD1, 0xE4, 0x8D, 0xA9, 0x8C, 0x41, 0xAF, 0x8C, 0x8D, 0x50, 0xFE, 0x63, 0x96, 0x46, 0x2E, 0x4D, 0xEB \ + } + +#define EX_SSS_AUTH_SE05X_KEY_ENC KEY_CODE_ENC +#define EX_SSS_AUTH_SE05X_KEY_MAC KEY_CODE_MAC +#define EX_SSS_AUTH_SE05X_KEY_DEK KEY_CODE_DEK + +#endif // SECURE_WORLD + +#endif // __EX_SCP03_PUF_H__ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss.h new file mode 100644 index 00000000000..f967247a41b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss.h @@ -0,0 +1,96 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_EX_INC_EX_SSS_H_ +#define SSS_EX_INC_EX_SSS_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM +#include +#endif +#if SSS_HAVE_MBEDTLS +#include +#endif +#if SSS_HAVE_OPENSSL +#include +#endif + +#if SSS_HAVE_SSCP +#include +#endif + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +#ifndef MAKE_TEST_ID +#define MAKE_TEST_ID(ID) (0xEF000000u + ID) +#endif /* MAKE_TEST_ID */ + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +#if 0 +typedef struct +{ + sss_session_t currentSession; + + sss_key_store_t ks; + + sss_sscp_session_t *sscp_session; +#if (SSS_HAVE_A71CH) || (SSS_HAVE_A71CH_SIM) + sss_a71ch_key_store_t *a71ch_keystore; +#endif + + sscp_context_t sscp; + sss_asymmetric_t asymVerifyCtx; + sss_asymmetric_t asymm; + sss_object_t keyPair; + sss_object_t extPubkey; + + sss_object_t Device_Cert; + sss_object_t Pubkey; + sss_object_t interCaCert; + sss_object_t interkeyPair; + sss_object_t clientCert; +#if SSS_HAVE_APPLET_SE05X_IOT + sss_session_t hostSession; + sss_key_store_t hostKs; + sss_object_t hostKey; +#endif + sss_symmetric_t symm; + sss_rng_context_t rng; + sss_mac_t mac; + +} sss_ex_ctx_t; + +#endif + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ +// extern const char *gszA71COMPortDefault; +// extern const char *gszA71SocketPortDefault; + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/* Entry point for each individual SSS API Based example */ + +#endif /* SSS_EX_INC_EX_SSS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h new file mode 100644 index 00000000000..ffd5be8b328 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h @@ -0,0 +1,180 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_EX_INC_EX_SSS_AUTH_H_ +#define SSS_EX_INC_EX_SSS_AUTH_H_ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include "ex_sss_boot.h" +#include "ex_sss_objid.h" +#include "ex_sss_scp03_keys.h" +#if defined(SECURE_WORLD) +#include "ex_scp03_puf.h" +#endif /* SECURE_WORLD */ +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* clang-format off */ + +/* Used in examples and testing */ +/* doc:start:auth-key-user-id */ +#define EX_SSS_AUTH_SE05X_UserID_AUTH_ID kEX_SSS_ObjID_UserID_Auth + +#define EX_SSS_AUTH_SE05X_UserID_VALUE \ + { \ + 0xC0, 0x01, 0x02, 0x03, 0x04 \ + } /* COOL 234*/ + +#define EX_SSS_AUTH_SE05X_UserID_VALUE2 \ + { \ + 0xC0, 0x01, 0x02, 0x03, 0x04, 0x05 \ + } /* COOL 2345*/ +/* doc:end:auth-key-user-id */ + +#define EX_SSS_AUTH_SE05X_NONE_AUTH_ID 0x00000000 + +/* doc:start:auth-key-applet-scp */ +#define EX_SSS_AUTH_SE05X_APPLETSCP_AUTH_ID kEX_SSS_ObjID_APPLETSCP03_Auth + +#define EX_SSS_AUTH_SE05X_APPLETSCP_VALUE \ + { \ + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, \ + 0x4B, 0x4C, 0x4D, 0x4E, 0x4F \ + } + +#define EX_SSS_AUTH_SE05X_APPLETSCP_VALUE2 \ + { 0xea, 0x62, 0x04, 0x48, 0x0b, 0xf5, 0x19, 0xf6, 0xc2, 0xb7, 0x7f, \ + 0xba, 0x8b, 0x2d, 0x57, 0x30 \ + } +/* doc:end:auth-key-applet-scp */ + +/* Use the Platform SCP03 keys from required OEF + * See https://www.nxp.com/docs/en/application-note/AN12436.pdf + */ + +#if EXTERNAL_CUSTOMER_BUILD_CONFIGURATION + +#if SSS_HAVE_SE05X_VER_06_00 // Applet 6.0 + #ifndef EX_SSS_AUTH_SE05X_KEY_ENC + # define EX_SSS_AUTH_SE05X_KEY_ENC SSS_AUTH_SE051C2_KEY_ENC + #endif + #ifndef EX_SSS_AUTH_SE05X_KEY_MAC + # define EX_SSS_AUTH_SE05X_KEY_MAC SSS_AUTH_SE051C2_KEY_MAC + #endif + #ifndef EX_SSS_AUTH_SE05X_KEY_DEK + # define EX_SSS_AUTH_SE05X_KEY_DEK SSS_AUTH_SE051C2_KEY_DEK + #endif +#else + #ifndef EX_SSS_AUTH_SE05X_KEY_ENC + # define EX_SSS_AUTH_SE05X_KEY_ENC SSS_AUTH_SE050_DEVKIT_KEY_ENC + #endif + #ifndef EX_SSS_AUTH_SE05X_KEY_MAC + # define EX_SSS_AUTH_SE05X_KEY_MAC SSS_AUTH_SE050_DEVKIT_KEY_MAC + #endif + #ifndef EX_SSS_AUTH_SE05X_KEY_DEK + # define EX_SSS_AUTH_SE05X_KEY_DEK SSS_AUTH_SE050_DEVKIT_KEY_DEK + #endif +#endif + +#else +/* Test / dummy keys */ + +#ifndef EX_SSS_AUTH_SE05X_KEY_ENC +# define EX_SSS_AUTH_SE05X_KEY_ENC \ + { 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x01 } +#endif + +#ifndef EX_SSS_AUTH_SE05X_KEY_MAC +# define EX_SSS_AUTH_SE05X_KEY_MAC \ + { 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x02 } +#endif + +#ifndef EX_SSS_AUTH_SE05X_KEY_DEK +# define EX_SSS_AUTH_SE05X_KEY_DEK \ + { 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x03 } +#endif + +#endif + + +#define EX_SSS_AUTH_SE05X_KEY_VERSION_NO 0x0B + +/* doc:start:auth-key-fast-scp-ecdsa */ +#define EX_SSS_AUTH_SE05X_ECKEY_ECDSA_AUTH_ID kEX_SSS_objID_ECKEY_Auth + +#define EX_SSS_AUTH_SE05X_KEY_HOST_ECDSA_KEY \ + { \ + 0x30, 0x81, 0x87, 0x02, 0x01, 0x00, 0x30, 0x13, \ + 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x02, \ + 0x01, 0x06, 0x08, 0x2A, 0x86, 0x48, 0xCE, 0x3D, \ + 0x03, 0x01, 0x07, 0x04, 0x6D, 0x30, 0x6B, 0x02, \ + 0x01, 0x01, 0x04, 0x20, \ + 0x6D, 0x2F, 0x43, 0x2F, 0x8A, 0x2F, 0x45, 0xEC, \ + 0xD5, 0x82, 0x84, 0x7E, 0xC0, 0x83, 0xBB, 0xEB, \ + 0xC2, 0x3F, 0x1D, 0xF4, 0xF0, 0xDD, 0x2A, 0x6F, \ + 0xB8, 0x1A, 0x24, 0xE7, 0xB6, 0xD5, 0x4C, 0x7F, \ + 0xA1, 0x44, 0x03, 0x42, 0x00, \ + 0x04, 0x3C, 0x9E, 0x47, 0xED, 0xF0, 0x51, 0xA3, \ + 0x58, 0x9F, 0x67, 0x30, 0x2D, 0x22, 0x56, 0x7C, \ + 0x2E, 0x17, 0x22, 0x9E, 0x88, 0x83, 0x33, 0x8E, \ + 0xC3, 0xB7, 0xD5, 0x27, 0xF9, 0xEE, 0x71, 0xD0, \ + 0xA8, 0x1A, 0xAE, 0x7F, 0xE2, 0x1C, 0xAA, 0x66, \ + 0x77, 0x78, 0x3A, 0xA8, 0x8D, 0xA6, 0xD6, 0xA8, \ + 0xAD, 0x5E, 0xC5, 0x3B, 0x10, 0xBC, 0x0B, 0x11, \ + 0x09, 0x44, 0x82, 0xF0, 0x4D, 0x24, 0xB5, 0xBE, \ + 0xC4 \ + } + +#define EX_SSS_AUTH_SE05X_KEY_HOST_ECDSA_KEY2 \ + { \ + 0x30, 0x81, 0x87, 0x02, 0x01, 0x00, 0x30, 0x13, \ + 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x02, \ + 0x01, 0x06, 0x08, 0x2A, 0x86, 0x48, 0xCE, 0x3D, \ + 0x03, 0x01, 0x07, 0x04, 0x6D, 0x30, 0x6B, 0x02, \ + 0x01, 0x01, 0x04, 0x20, \ + 0x12, 0xe2, 0xd3, 0xc7, 0x31, 0xa6, 0x7c, 0x32, \ + 0xfb, 0xd7, 0x2f, 0xa9, 0xc4, 0xbb, 0xc2, 0xd0, \ + 0x64, 0xad, 0x50, 0x99, 0xd3, 0x3d, 0x01, 0x4b, \ + 0x4f, 0x36, 0x90, 0x9c, 0xba, 0xab, 0xbb, 0xda, \ + 0xA1, 0x44, 0x03, 0x42, 0x00, \ + 0x04, 0x0d, 0x0e, 0x03, 0xdd, 0x40, 0x1e, 0x77, \ + 0xff, 0xab, 0xa8, 0xb5, 0x79, 0xdb, 0x8a, 0xf4, \ + 0x09, 0x7b, 0x59, 0x4e, 0xe8, 0xa0, 0xb8, 0x1c, \ + 0xeb, 0xa8, 0x53, 0x96, 0xc6, 0x13, 0x96, 0x56, \ + 0x13, 0x5e, 0x68, 0x75, 0xb9, 0xe9, 0x79, 0x29, \ + 0x28, 0x8c, 0x7d, 0xa1, 0xf2, 0x78, 0x7b, 0x66, \ + 0x86, 0xcc, 0x9e, 0x6b, 0xf6, 0x03, 0xc2, 0xfe, \ + 0x59, 0x1b, 0xab, 0x4a, 0x40, 0x24, 0x70, 0xe4, \ + 0x8b \ + } + +/* doc:end:auth-key-fast-scp-ecdsa */ + +/* clang-format on */ + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +#endif /* SSS_EX_INC_EX_SSS_AUTH_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h new file mode 100644 index 00000000000..3d6ed1b123e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h @@ -0,0 +1,220 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_boot.h: *The purpose and scope of this file* + * + * Project: SecureIoTMW-Debug@appboot-top-eclipse_x86 + * + * $Date: Mar 10, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +#ifndef SSS_EX_INC_EX_SSS_BOOT_H_ +#define SSS_EX_INC_EX_SSS_BOOT_H_ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ex_sss.h" +#include "fsl_sss_api.h" + +#if SSS_HAVE_APPLET_SE05X_IOT +#include "fsl_sss_se05x_types.h" +#endif +#include "ex_sss_ports.h" +#include "nxScp03_Types.h" + +/* ***************************************************************************************************************** + * MACROS/Defines + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Types/Structure Declarations + * ***************************************************************************************************************** */ +#if SSS_HAVE_SE || SSS_HAVE_APPLET_SE05X_IOT + +typedef union ex_auth { + struct + { + NXSCP03_StaticCtx_t ex_static; //!< .static keys data + NXSCP03_DynCtx_t ex_dyn; //!< session keys data + } scp03; + struct + { + NXECKey03_StaticCtx_t ex_static; //!< .static keys data + NXSCP03_DynCtx_t ex_dyn; //!< session keys data + } eckey; + struct + { + sss_object_t ex_id; + } id; +} ex_SE05x_authCtx_t; +#endif + +typedef struct +{ + sss_session_t session; + sss_key_store_t ks; + +#if SSS_HAVE_HOSTCRYPTO_ANY || SSS_HAVE_SSCP + sss_session_t host_session; +#endif + +#if SSS_HAVE_HOSTCRYPTO_ANY + sss_key_store_t host_ks; +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT || SSS_HAVE_APPLET_LOOPBACK + SE_Connect_Ctx_t se05x_open_ctx; + sss_tunnel_t *pTunnel_ctx; + ex_SE05x_authCtx_t ex_se05x_auth; +#endif + +#if SSS_HAVE_SSCP + sscp_context_t sscp_ctx; +#endif + +} ex_sss_boot_ctx_t; + +#if SSS_HAVE_APPLET_SE05X_IOT +typedef struct +{ + sss_session_t platf_session; + SE_Connect_Ctx_t platf_open_ctx; + sss_session_t *phost_session; + sss_key_store_t *phost_ks; +#if 1 //SSS_HAVE_HOSTCRYPTO_ANY + /* Keeping this to be consistant on binary sizes */ + ex_SE05x_authCtx_t ex_se05x_auth; +#endif // SSS_HAVE_HOSTCRYPTO_ANY +} ex_sss_platf_ctx_t; +#endif + +typedef struct +{ + sss_object_t pub_obj; + sss_object_t obj; + sss_object_t dev_cert; + sss_object_t interCaCert; + sss_key_store_t *pHost_ks; + uint32_t client_keyPair_index; + uint32_t client_cert_index; +} ex_sss_cloud_ctx_t; + +/* ***************************************************************************************************************** + * Extern Variables + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Function Prototypes + * ***************************************************************************************************************** */ + +#if SSS_HAVE_APPLET_SE05X_IOT + +sss_status_t ex_sss_se05x_prepare_host(sss_session_t *host_session, + sss_key_store_t *host_ks, + SE05x_Connect_Ctx_t *se05x_open_ctx, + ex_SE05x_authCtx_t *ex_se05x_authctx, + SE_AuthType_t auth_type); + +/* Prepare host for multiple user sessions */ +sss_status_t ex_sss_se05x_prepare_host_keys(sss_session_t *pHostSession, + sss_key_store_t *pHostKs, + SE_Connect_Ctx_t *pConnectCtx, + ex_SE05x_authCtx_t *se05x_auth_ctx, + uint32_t offset); +#endif + +#if SSS_HAVE_SE +sss_status_t ex_sss_se_prepare_host(sss_session_t *host_session, + sss_key_store_t *host_ks, + SE_Connect_Ctx_t *se05x_open_ctx, + ex_SE05x_authCtx_t *ex_se05x_authctx, + SE_AuthType_t auth_type); +#endif + +/** The case where we connect to the cyrptogrpahic system directly. + * + * e.g. when running form an embedded sytem, without any choice of Port Numbers, etc. + */ +sss_status_t ex_sss_boot_direct(void); + +/** The case where we connect to the cyrptogrpahic system in-directly. + * + * This function is a similar to @ref ex_sss_boot_direct. + * + * This function expects that the last argument in argv is the + * expected/probable port name. + * + * e.g. when running form PC, where we are connected + * to secure element via a COM Port/Socket Port. In such cases, + * taking the Port number from a Command Line Argument, + * or Environment Variable would make sense and examples + * would become more portable. + * + * @param argc count of parameters, as received by main + * @param argv Array of argv, as received by main + * @param[out] pPortName Possible port name + * @return 0 if successful. + */ +sss_status_t ex_sss_boot_connectstring(int argc, const char *argv[], const char **pPortName); + +/** + * For the case where few activities have to be performed + * after RTOS initialization, this API would be executed + * as an RTOS Task. + * + * @return + */ +sss_status_t ex_sss_boot_rtos(void *); + +/** Is this a serail port */ +bool ex_sss_boot_isSerialPortName(const char *portName); + +/** Is this --help request */ +bool ex_sss_boot_isHelp(const char *argname); + +/** Is this a socket port */ +bool ex_sss_boot_isSocketPortName(const char *portName); + +/** Open an example session */ +sss_status_t ex_sss_boot_open(ex_sss_boot_ctx_t *pCtx, const char *portName); + +/** Open an example cc session */ +sss_status_t ex_sss_boot_open_on_id(ex_sss_boot_ctx_t *pCtx, const char *portName, const int32_t authId); + +/** Open an example session */ +sss_status_t ex_sss_boot_factory_reset(ex_sss_boot_ctx_t *pCtx); + +/** Close an example session */ +void ex_sss_session_close(ex_sss_boot_ctx_t *pCtx); + +/** Entry Point for each example */ +sss_status_t ex_sss_entry(ex_sss_boot_ctx_t *pCtx); + +#define ex_sss_kestore_and_object_init ex_sss_key_store_and_object_init + +sss_status_t ex_sss_key_store_and_object_init(ex_sss_boot_ctx_t *pCtx); + +int ex_sss_boot_rtos_init(void); + +#if SSS_HAVE_HOSTCRYPTO_ANY +sss_status_t ex_sss_boot_open_host_session(ex_sss_boot_ctx_t *pCtx); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* SSS_EX_INC_EX_SSS_BOOT_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h new file mode 100644 index 00000000000..9ce448dbb66 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h @@ -0,0 +1,382 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common, Re-Usable main implementation */ +/* Include this header file only once in the application */ + +/* + * Applications control the boot flow by defining these macros. + * + * + * - EX_SSS_BOOT_PCONTEXT : Pointer to ex_sss_boot_ctx_t + * This allows that boot framework do not blindly rely on + * global variables. + * + * - EX_SSS_BOOT_DO_ERASE : Delete all objects on boot up if 1 + * Few examples expect the IC is *empty*, and few examples + * expect to work with previously provisioned/persisted data. + * This variable allows to over-ride that behaviour. + * + * - EX_SSS_BOOT_EXPOSE_ARGC_ARGV : Expose ARGC & ARGV from Command + * line to Application. + * When running from PC/Linux/OSX, command line arguments allow + * to choose extra command line parameters, e.g. Input/Output + * certificate or signing/verifying data. + * But on embedded platforms, such feature is not possible to + * achieve. + * + * Optional variables: + * + * - EX_SSS_BOOT_RTOS_STACK_SIZE : For RTOS based system, + * this is over-ridden and passed to RTOS based example + * boot up. It sets value needed for new task. + * Please note, FREE RTOS will reserve + * EX_SSS_BOOT_RTOS_STACK_SIZE * sizeof(UBaseType_t) + * bytes. + * + * - EX_SSS_BOOT_OPEN_HOST_SESSION : For examples that do not + * need host side implementation, his allows to skip opening + * the host session. (Host session is needed to either re-verify + * test data at host, or for SCP03). + * By default this is enabled. + * + * + */ + +#if defined(FRDM_KW41Z) || defined(FRDM_K64F) || defined(IMX_RT) || defined(LPC_55x) || defined(QN9090DK6) +#define HAVE_KSDK +#endif + +#ifdef HAVE_KSDK +#include "ex_sss_main_inc_ksdk.h" +#endif + +#if defined(__linux__) && defined(T1oI2C) +#if SSS_HAVE_APPLET_SE05X_IOT +#include "ex_sss_main_inc_linux.h" +#endif +#endif +#include /* memset */ + +#include "PlugAndTrust_Pkg_Ver.h" +#include "string.h" /* memset */ + +#if defined(USE_RTOS) && USE_RTOS == 1 +#ifndef INC_FREERTOS_H /* Header guard of FreeRTOS */ +#include "FreeRTOS.h" +#include "FreeRTOSConfig.h" +#endif /* INC_FREERTOS_H */ +#include "task.h" +#include "iot_logging_task.h" +#define LOGGING_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define LOGGING_TASK_STACK_SIZE (200) +#define LOGGING_QUEUE_LENGTH (16) +#endif + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM +#include "ex_a71ch_scp03.h" +#endif + +#ifdef EX_SSS_BOOT_PCONTEXT +#define PCONTEXT EX_SSS_BOOT_PCONTEXT +#else +#define PCONTEXT (NULL) +#endif + +#if !defined(EX_SSS_BOOT_DO_ERASE) +#error EX_SSS_BOOT_DO_ERASE must be set to 0 or 1 +#endif + +#if !defined(EX_SSS_BOOT_EXPOSE_ARGC_ARGV) +#error EX_SSS_BOOT_EXPOSE_ARGC_ARGV must be set to 0 or 1 +#endif + +#if EX_SSS_BOOT_EXPOSE_ARGC_ARGV +static int gex_sss_argc; +static const char **gex_sss_argv; +#endif + +#if !defined(EX_SSS_BOOT_OPEN_HOST_SESSION) +#define EX_SSS_BOOT_OPEN_HOST_SESSION 1 +#endif + +#if !defined(EX_SSS_BOOT_RTOS_STACK_SIZE) +#define EX_SSS_BOOT_RTOS_STACK_SIZE 8500 +#endif + +#if defined(USE_RTOS) && USE_RTOS == 1 +static TaskHandle_t gSSSExRtosTaskHandle = NULL; +static void sss_ex_rtos_task(void *ctx); +#if INCLUDE_uxTaskGetStackHighWaterMark +void sss_ex_rtos_stack_size(const char *when); +#endif // INCLUDE_uxTaskGetStackHighWaterMark +#if (!AX_EMBEDDED) +extern void prvMiscInitialisation(void); +#endif +#endif /* RTOS */ + +#if defined(CPU_JN518X) +/* Allocate the memory for the heap. */ +uint8_t __attribute__((section(".bss.$SRAM1"))) ucHeap[configTOTAL_HEAP_SIZE]; +#endif + +int main(int argc, const char *argv[]) +{ + int ret; + sss_status_t status = kStatus_SSS_Fail; + const char *portName; + +#if EX_SSS_BOOT_EXPOSE_ARGC_ARGV + gex_sss_argc = argc; + gex_sss_argv = argv; +#endif // EX_SSS_BOOT_EXPOSE_ARGC_ARGV + +#ifdef HAVE_KSDK + ex_sss_main_ksdk_bm(); +#endif // HAVE_KSDK + +#if defined(__linux__) && defined(T1oI2C) && SSS_HAVE_APPLET_SE05X_IOT + ex_sss_main_linux_conf(); +#endif // defined(__linux__) && defined(T1oI2C) && SSS_HAVE_APPLET_SE05X_IOT + + LOG_I(PLUGANDTRUST_PROD_NAME_VER_FULL); + +#ifdef EX_SSS_BOOT_PCONTEXT + memset((EX_SSS_BOOT_PCONTEXT), 0, sizeof(*(EX_SSS_BOOT_PCONTEXT))); +#endif // EX_SSS_BOOT_PCONTEXT + +#if AX_EMBEDDED + portName = NULL; +#else + status = ex_sss_boot_connectstring(argc, argv, &portName); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_boot_connectstring Failed"); + goto cleanup; + } +#endif // AX_EMBEDDED + +#if defined(USE_RTOS) && USE_RTOS == 1 +#if (!AX_EMBEDDED) && ENABLE_CLOUD_DEMOS + prvMiscInitialisation(); +#endif +#endif + + /* Initialise Logging locks */ + if (nLog_Init() != 0) { + LOG_E("Lock initialisation failed"); + } +#if defined(EX_SSS_BOOT_SKIP_SELECT_APPLET) && (EX_SSS_BOOT_SKIP_SELECT_APPLET == 1) + (PCONTEXT)->se05x_open_ctx.skip_select_applet = 1; +#endif + +#if defined(USE_RTOS) && USE_RTOS == 1 + if (xTaskCreate(&sss_ex_rtos_task, + "sss_ex_rtos_task", + EX_SSS_BOOT_RTOS_STACK_SIZE, + (void *)portName, + (tskIDLE_PRIORITY), + &gSSSExRtosTaskHandle) != pdPASS) { + LOG_E("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Run RTOS */ + vTaskStartScheduler(); + +#else /* No RTOS, No Embedded */ + +#if !AX_EMBEDDED + if (ex_sss_boot_isHelp(portName)) { + memset(PCONTEXT, 0, sizeof(*PCONTEXT)); +#if EX_SSS_BOOT_EXPOSE_ARGC_ARGV + /* so that tool can fetchup last value */ + gex_sss_argc++; +#endif // EX_SSS_BOOT_EXPOSE_ARGC_ARGV + goto before_ex_sss_entry; + } +#endif + + status = ex_sss_boot_open(PCONTEXT, portName); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_session_open Failed"); + goto cleanup; + } + +#if EX_SSS_BOOT_DO_ERASE + status = ex_sss_boot_factory_reset((PCONTEXT)); +#endif + + if (kType_SSS_SubSystem_NONE == ((PCONTEXT)->session.subsystem)) { + /* Nothing to do. Device is not opened + * This is needed for the case when we open a generic communication + * channel, without being specific to SE05X + */ + } + else { + status = ex_sss_key_store_and_object_init((PCONTEXT)); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_key_store_and_object_init Failed"); + goto cleanup; + } + } + +#if EX_SSS_BOOT_OPEN_HOST_SESSION && SSS_HAVE_HOSTCRYPTO_ANY + ex_sss_boot_open_host_session((PCONTEXT)); +#endif + +#if (SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM) && SSS_HAVE_A71CH_AUTH_SCP03 + LOG_I("A71CH SCP03 add-on"); + { + // Variables used by calls to legacy API + U8 sCounter[3]; + U16 sCounterLen = sizeof(sCounter); + U16 sw = 0; + U8 scpKeyEncBase[SCP_KEY_SIZE]; + U8 scpKeyMacBase[SCP_KEY_SIZE]; + U8 scpKeyDekBase[SCP_KEY_SIZE]; + + LOG_I("** Establish SCP03 session: Start **"); + status = ex_a71ch_FetchRandomScp03Keys(scpKeyEncBase, scpKeyMacBase, scpKeyDekBase); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = ex_a71ch_SetSeScp03Keys(scpKeyEncBase, scpKeyMacBase, scpKeyDekBase); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + LOG_I("Clear host-side SCP03 channel state"); + DEV_ClearChannelState(); + + LOG_I("SCP_Authenticate()"); + sw = SCP_Authenticate(scpKeyEncBase, scpKeyMacBase, scpKeyDekBase, SCP_KEY_SIZE, sCounter, &sCounterLen); + status = (sw == SW_OK) ? kStatus_SSS_Success : kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(sw == SW_OK); + LOG_I("** Establish SCP03 session: End **"); + } +#endif // SSS_HAVE_A71CH && SSS_HAVE_A71CH_AUTH_SCP03 + +#if !AX_EMBEDDED +before_ex_sss_entry: +#endif + + status = ex_sss_entry((PCONTEXT)); + LOG_I("ex_sss Finished"); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_entry Failed"); + goto cleanup; + } +#endif /* No RTOS, No Embedded */ + // Delete locks for pthreads + nLog_DeInit(); + goto cleanup; + +cleanup: +#ifdef EX_SSS_BOOT_PCONTEXT + ex_sss_session_close((EX_SSS_BOOT_PCONTEXT)); +#endif + if (kStatus_SSS_Success == status) { + ret = 0; +#if defined(HAVE_KSDK) && HAVE_KSDK_LED_APIS == 1 + ex_sss_main_ksdk_success(); +#endif +#if defined(__linux__) && defined(T1oI2C) && SSS_HAVE_APPLET_SE05X_IOT + ex_sss_main_linux_unconf(); +#endif // defined(__linux__) && defined(T1oI2C) && SSS_HAVE_APPLET_SE05X_IOT + } + else { + LOG_E("!ERROR! ret != 0."); + ret = 1; +#if defined(HAVE_KSDK) && HAVE_KSDK_LED_APIS == 1 + ex_sss_main_ksdk_failure(); +#endif + } + return ret; +} + +#if defined(USE_RTOS) && USE_RTOS == 1 +static void sss_ex_rtos_task(void *ctx) +{ + sss_status_t status; + +#if INCLUDE_uxTaskGetStackHighWaterMark + sss_ex_rtos_stack_size("Boot"); +#endif // INCLUDE_uxTaskGetStackHighWaterMark + +#if AX_EMBEDDED + ex_sss_main_ksdk_boot_rtos_task(); +#endif + status = ex_sss_boot_open(PCONTEXT, (const char *)ctx); + + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_session_open Failed."); + goto exit; + } + + status = ex_sss_key_store_and_object_init((PCONTEXT)); + + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_key_store_and_object_init Failed"); + goto exit; + } + +#if INCLUDE_uxTaskGetStackHighWaterMark + sss_ex_rtos_stack_size("Before:ex_sss_entry"); +#endif // INCLUDE_uxTaskGetStackHighWaterMark + +#if EX_SSS_BOOT_DO_ERASE + status = ex_sss_boot_factory_reset((PCONTEXT)); + if (kStatus_SSS_Success != status) { + LOG_W("ex_sss_boot_factory_reset Failed"); + } +#if INCLUDE_uxTaskGetStackHighWaterMark + sss_ex_rtos_stack_size("after:erase"); +#endif // INCLUDE_uxTaskGetStackHighWaterMark +#endif + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM +#if EX_SSS_BOOT_OPEN_HOST_SESSION + ex_sss_boot_open_host_session((PCONTEXT)); +#endif +#endif + + xLoggingTaskInitialize(LOGGING_TASK_STACK_SIZE, LOGGING_TASK_PRIORITY, LOGGING_QUEUE_LENGTH); + status = ex_sss_entry((PCONTEXT)); + + LOG_I("ex_sss Finished"); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_entry Failed"); + } + + ex_sss_session_close(PCONTEXT); + /* Delete locks for FreeRtos*/ + nLog_DeInit(); +#if INCLUDE_uxTaskGetStackHighWaterMark + sss_ex_rtos_stack_size("After:ex_sss_entry"); +#endif // INCLUDE_uxTaskGetStackHighWaterMark +exit: +#if defined(_MSC_VER) || defined(__linux__) || defined(__MINGW32__) || defined(__MINGW64__) + if (kStatus_SSS_Success == status) { + exit(0); + } + else { + exit(1); + } +#else + vTaskDelete(NULL); +#endif +} + +#if INCLUDE_uxTaskGetStackHighWaterMark +void sss_ex_rtos_stack_size(const char *when) +{ +#if LOG_INFO_ENABLED + UBaseType_t stackused; + stackused = EX_SSS_BOOT_RTOS_STACK_SIZE - uxTaskGetStackHighWaterMark(gSSSExRtosTaskHandle); + LOG_I("STACK USED [%s] %d", when, sizeof(UBaseType_t) * stackused); +#endif +} +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ + +#endif /* No RTOS, No Embedded */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h new file mode 100644 index 00000000000..cd8b4002d70 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h @@ -0,0 +1,25 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "ax_reset.h" + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +void ex_sss_main_linux_conf() +{ + axReset_HostConfigure(); + axReset_PowerUp(); +} + +void ex_sss_main_linux_unconf() +{ + axReset_PowerDown(); + axReset_HostUnconfigure(); +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h new file mode 100644 index 00000000000..5e5beb1b47c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h @@ -0,0 +1,112 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_objid.h: Reserved Object Identifiers + * + * Project: SecureIoTMW-Debug@simw-top-eclipse_x86 + * + * $Date: Mar 27, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +#ifndef SSS_EX_INC_EX_SSS_OBJID_H_ +#define SSS_EX_INC_EX_SSS_OBJID_H_ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * MACROS/Defines + * ***************************************************************************************************************** */ + +/* clang-format off */ +#define EX_SSS_OBJID_CUST_START 0x00000001u +#define SE05X_OBJID_TP_MASK(X) (0xFFFFFFFC & (X)) +#define EX_SSS_OBJID_CUST_END 0x7BFFFFFFu + +#define EX_SSS_OBJID_AKM_START 0x7C000000u +#define EX_SSS_OBJID_AKM_END 0x7CFFFFFFu + +#define EX_SSS_OBJID_DEMO_START 0x7D000000u +#define EX_SSS_OBJID_DEMO_SA_START 0x7D500000u +#define EX_SSS_OBJID_DEMO_WIFI_START 0x7D51F000u +/* doc:start:mif-kdf-start-keyid */ +#define EX_SSS_OBJID_DEMO_MFDF_START 0x7D5DF000u +/* doc:end:mif-kdf-start-keyid */ +/////// EX_SSS_OBJID_DEMO_SA_END 0x7D5FFFFFu +#define EX_SSS_OBJID_DEMO_AUTH_START 0x7DA00000u +#define EX_SSS_OBJID_DEMO_AUTH_MASK(X) (0xFFFF0000u & (X)) +/////// EX_SSS_OBJID_DEMO_AUTH_END 0x7DA0FFFFu +#define EX_SSS_OBJID_DEMO_CLOUD_START 0x7DC00000u +#define EX_SSS_OBJID_DEMO_CLOUD_IBM_START 0x7DC1B000u +#define EX_SSS_OBJID_DEMO_CLOUD_GCP_START 0x7DC6C000u +#define EX_SSS_OBJID_DEMO_CLOUD_AWS_START 0x7DCA5000u +#define EX_SSS_OBJID_DEMO_CLOUD_AZURE_START 0x7DCAC000u +/////// EX_SSS_OBJID_DEMO_CLOUD_END 0x7DCFFFFFu +#define EX_SSS_OBJID_DEMO_END 0x7DFFFFFFu +#define SE05X_OBJID_SE05X_APPLET_RES_START 0x7FFF0000u +#define SE05X_OBJID_SE05X_APPLET_RES_MASK(X) \ + (0xFFFF0000u & (X)) +#define SE05X_OBJID_SE05X_APPLET_RES_END 0x7FFFFFFFu + +/* IoT Hub Managed */ +#define SE05X_OBJID_IOT_HUB_M_START 0x80000000u +#define SE05X_OBJID_IOT_HUB_M_END 0xEEFFFFFFu +#define EX_SSS_OBJID_TEST_START 0xEF000000u +#define EX_SSS_OBJID_TEST_END 0xEFFFFFFFu + +/* IoT Hub Access */ +#define EX_SSS_OBJID_IOT_HUB_A_START 0xF0000000u +#define EX_SSS_OBJID_IOT_HUB_A_MASK(X) (0xF0000000u & (X)) + +//Device Key and Certificate - ECC-256 +#define EX_SSS_OBJID_TP_KEY_EC_D 0xF0000100 +#define EX_SSS_OBJID_TP_CERT_EC_D 0xF0000101 +//Gateway Key and Certificate - ECC-256 +#define EX_SSS_OBJID_TP_KEY_EC_G 0xF0000102 +#define EX_SSS_OBJID_TP_CERT_EC_G 0xF0000103 + +//Device Key and Certificate - RSA-2K +#define EX_SSS_OBJID_TP_KEY_RSA2K_D 0xF0000110 +#define EX_SSS_OBJID_TP_CERT_RSA2K_D 0xF0000111 +//Gateway Key and Certificate - RSA-2K +#define EX_SSS_OBJID_TP_KEY_RSA2K_G 0xF0000112 +#define EX_SSS_OBJID_TP_CERT_RSA2K_G 0xF0000113 +//Device Key and Certificate - RSA-4K +#define EX_SSS_OBJID_TP_KEY_RSA4K_D 0xF0000120 +#define EX_SSS_OBJID_TP_CERT_RSA4K_D 0xF0000121 +//Gateway Key and Certificate - RSA-4K +#define EX_SSS_OBJID_TP_KEY_RSA4K_G 0xF0000122 +#define EX_SSS_OBJID_TP_CERT_RSA4K_G 0xF0000123 + +#define EX_SSS_OBJID_IOT_HUB_A_END 0xFFFFFFFFu + +/* clang-format on */ + +/* ***************************************************************************************************************** + * Types/Structure Declarations + * ***************************************************************************************************************** */ + +enum +{ + kEX_SSS_ObjID_UserID_Auth = EX_SSS_OBJID_DEMO_AUTH_START + 1, + kEX_SSS_ObjID_APPLETSCP03_Auth, + kEX_SSS_objID_ECKEY_Auth, +}; + +/* ***************************************************************************************************************** + * Extern Variables + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Function Prototypes + * ***************************************************************************************************************** */ + +#endif /* SSS_EX_INC_EX_SSS_OBJID_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h new file mode 100644 index 00000000000..ed238e7ef35 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h @@ -0,0 +1,53 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_ports.h: Default ports being used in Examples and test cases + * + * $Date: Mar 10, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +#ifndef SSS_EX_INC_EX_SSS_PORTS_H_ +#define SSS_EX_INC_EX_SSS_PORTS_H_ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * MACROS/Defines + * ***************************************************************************************************************** */ + +#define EX_SSS_BOOT_SSS_PORT "EX_SSS_BOOT_SSS_PORT" +#ifdef __linux__ +#define EX_SSS_BOOT_SSS_COMPORT_DEFAULT "/dev/ttyACM0" +#else +#define EX_SSS_BOOT_SSS_COMPORT_DEFAULT "\\\\.\\COM7" +#endif +#define EX_SSS_BOOT_SSS_SOCKET_HOSTNAME_DEFAULT "127.0.0.1" +#define EX_SSS_BOOT_SSS_SOCKET_PORTNUMBER_DEFAULT 8050 +#define EX_SSS_BOOT_SSS_SOCKET_PORTSZ_DEFAULT "8050" +#define EX_SSS_BOOT_SSS_PCSC_READER_DEFAULT "NXP SE050C v03.01.00 0" +#define EX_SSS_BOOT_SSS_SOCKETPORT_DEFAULT \ + EX_SSS_BOOT_SSS_SOCKET_HOSTNAME_DEFAULT \ + ":" EX_SSS_BOOT_SSS_SOCKET_PORTSZ_DEFAULT + +/* ***************************************************************************************************************** + * Types/Structure Declarations + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Extern Variables + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Function Prototypes + * ***************************************************************************************************************** */ + +#endif /* SSS_EX_INC_EX_SSS_PORTS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h new file mode 100644 index 00000000000..9e894babd7a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h @@ -0,0 +1,75 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_EX_INC_EX_SSS_SCP03_KEYS_H_ +#define SSS_EX_INC_EX_SSS_SCP03_KEYS_H_ + +#include "ex_sss_tp_scp03_keys.h" + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +#define EX_SSS_BOOT_SCP03_PATH_ENV "EX_SSS_BOOT_SCP03_PATH" + +/* Modify based on platform */ +#if defined(ANDROID) +/* Could be set to /data/vendor/secure_iot/ if sepolicies are in effect */ +/* doc:start:android-scp03-path */ +#define EX_SSS_SCP03_FILE_DIR "/data/vendor/SE05x/" +#define EX_SSS_SCP03_FILE_PATH EX_SSS_SCP03_FILE_DIR "plain_scp.txt" +/* doc:end:android-scp03-path */ +#elif defined(__linux__) +/* doc:start:linux-scp03-path */ +#define EX_SSS_SCP03_FILE_DIR "/tmp/SE05X/" +#define EX_SSS_SCP03_FILE_PATH EX_SSS_SCP03_FILE_DIR "plain_scp.txt" +/* doc:end:linux-scp03-path */ +#elif defined(_MSC_VER) +/* doc:start:windows-scp03-path */ +#define EX_SSS_SCP03_FILE_DIR "C:\\nxp\\SE05X\\" +#define EX_SSS_SCP03_FILE_PATH EX_SSS_SCP03_FILE_DIR "plain_scp.txt" +/* doc:end:windows-scp03-path */ +#else +/* Not defined / avialable */ +#endif + +#ifdef EX_SSS_SCP03_FILE_PATH +sss_status_t scp03_keys_from_path( + uint8_t *penc, size_t enc_len, uint8_t *pmac, size_t mac_len, uint8_t *pdek, size_t dek_len); +#endif + +#define SSS_AUTH_SE050_OEF_0004A2D0_KEY_ENC \ + { \ + 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x01 \ + } + +#define SSS_AUTH_SE050_OEF_0004A2D0_KEY_MAC \ + { \ + 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x02 \ + } + +#define SSS_AUTH_SE050_OEF_0004A2D0_KEY_DEK \ + { \ + 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0xAB, 0xCD, 0x00, 0x03 \ + } + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +#endif /* SSS_EX_INC_EX_SSS_SCP03_KEYS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h new file mode 100644 index 00000000000..24421b7cd84 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h @@ -0,0 +1,119 @@ +/* + * + * Copyright 2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_AUTH_SE050_OEF_20191211_1809_ +#define SSS_AUTH_SE050_OEF_20191211_1809_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* clang-format off */ + + + +/* See https://www.nxp.com/docs/en/application-note/AN12436.pdf */ + +// Variant ==> OEF ID +// SE050A1 ==> A204 +// SE050A2 ==> A205 +// SE050B1 ==> A202 +// SE050B2 ==> A203 +// SE050C1 ==> A200 +// SE050C2 ==> A201 +// Development Board ==> A1F4 (DEVKIT) + +// SE050A1 +#define SSS_AUTH_SE050A1_KEY_ENC \ + {0x34, 0xae, 0x09, 0x67, 0xe3, 0x29, 0xe9, 0x51, 0x8e, 0x72, 0x65, 0xd5, 0xad, 0xcc, 0x01, 0xc2 } +#define SSS_AUTH_SE050A1_KEY_MAC \ + {0x52, 0xb2, 0x53, 0xca, 0xdf, 0x47, 0x2b, 0xdb, 0x3d, 0x0f, 0xb3, 0x8e, 0x09, 0x77, 0x00, 0x99 } +#define SSS_AUTH_SE050A1_KEY_DEK \ + {0xac, 0xc9, 0x14, 0x31, 0xfe, 0x26, 0x81, 0x1b, 0x5e, 0xcb, 0xc8, 0x45, 0x62, 0x0d, 0x83, 0x44 } + +// SE050A2 +#define SSS_AUTH_SE050A2_KEY_ENC \ + {0x46, 0xa9, 0xc4, 0x8c, 0x34, 0xef, 0xe3, 0x44, 0xa5, 0x22, 0xe6, 0x67, 0x44, 0xf8, 0x99, 0x6a } +#define SSS_AUTH_SE050A2_KEY_MAC \ + {0x12, 0x03, 0xff, 0x61, 0xdf, 0xbc, 0x9c, 0x86, 0x19, 0x6a, 0x22, 0x74, 0xae, 0xf4, 0xed, 0x28 } +#define SSS_AUTH_SE050A2_KEY_DEK \ + {0xf7, 0x56, 0x1c, 0x6f, 0x48, 0x33, 0x61, 0x19, 0xee, 0x39, 0x43, 0x9a, 0xab, 0x34, 0x09, 0x8e } + +// SE050B1 +#define SSS_AUTH_SE050B1_KEY_ENC \ + {0xd4, 0x99, 0xbc, 0x90, 0xde, 0xa5, 0x42, 0xcf, 0x78, 0xd2, 0x5e, 0x13, 0xd6, 0x4c, 0xbb, 0x1f } +#define SSS_AUTH_SE050B1_KEY_MAC \ + {0x08, 0x15, 0x55, 0x96, 0x43, 0xfb, 0x79, 0xeb, 0x85, 0x01, 0xa0, 0xdc, 0x83, 0x3d, 0x90, 0x1f } +#define SSS_AUTH_SE050B1_KEY_DEK \ + {0xbe, 0x7d, 0xdf, 0xb4, 0x06, 0xe8, 0x1a, 0xe4, 0xe9, 0x66, 0x5a, 0x9f, 0xed, 0x64, 0x26, 0x7c } + +// SE050B2 +#define SSS_AUTH_SE050B2_KEY_ENC \ + {0x5f, 0xa4, 0x3d, 0x82, 0x02, 0xd2, 0x5e, 0x9a, 0x85, 0xb1, 0xfe, 0x7e, 0x2d, 0x26, 0x47, 0x8d } +#define SSS_AUTH_SE050B2_KEY_MAC \ + {0x10, 0x5c, 0xea, 0x22, 0x19, 0xf5, 0x2b, 0xd1, 0x67, 0xa0, 0x74, 0x63, 0xc6, 0x93, 0x79, 0xc3 } +#define SSS_AUTH_SE050B2_KEY_DEK \ + {0xd7, 0x02, 0x81, 0x57, 0xf2, 0xad, 0x37, 0x2c, 0x74, 0xbe, 0x96, 0x9b, 0xcc, 0x39, 0x06, 0x27 } + +// SE050C1 +#define SSS_AUTH_SE050C1_KEY_ENC \ + {0x85, 0x2b, 0x59, 0x62, 0xe9, 0xcc, 0xe5, 0xd0, 0xbe, 0x74, 0x6b, 0x83, 0x3b, 0xcc, 0x62, 0x87 } +#define SSS_AUTH_SE050C1_KEY_MAC \ + {0xdb, 0x0a, 0xa3, 0x19, 0xa4, 0x08, 0x69, 0x6c, 0x8e, 0x10, 0x7a, 0xb4, 0xe3, 0xc2, 0x6b, 0x47 } +#define SSS_AUTH_SE050C1_KEY_DEK \ + {0x4c, 0x2f, 0x75, 0xc6, 0xa2, 0x78, 0xa4, 0xae, 0xe5, 0xc9, 0xaf, 0x7c, 0x50, 0xee, 0xa8, 0x0c } + +// SE050C2 +#define SSS_AUTH_SE050C2_KEY_ENC \ + {0xbd, 0x1d, 0xe2, 0x0a, 0x81, 0xea, 0xb2, 0xbf, 0x3b, 0x70, 0x9a, 0x9d, 0x69, 0xa3, 0x12, 0x54 } +#define SSS_AUTH_SE050C2_KEY_MAC \ + {0x9a, 0x76, 0x1b, 0x8d, 0xba, 0x6b, 0xed, 0xf2, 0x27, 0x41, 0xe4, 0x5d, 0x8d, 0x42, 0x36, 0xf5 } +#define SSS_AUTH_SE050C2_KEY_DEK \ + {0x9b, 0x99, 0x3b, 0x60, 0x0f, 0x1c, 0x64, 0xf5, 0xad, 0xc0, 0x63, 0x19, 0x2a, 0x96, 0xc9, 0x47 } + +// SE050_DEVKIT +#define SSS_AUTH_SE050_DEVKIT_KEY_ENC \ + {0x35, 0xc2, 0x56, 0x45, 0x89, 0x58, 0xa3, 0x4f, 0x61, 0x36, 0x15, 0x5f, 0x82, 0x09, 0xd6, 0xcd } +#define SSS_AUTH_SE050_DEVKIT_KEY_MAC \ + {0xaf, 0x17, 0x7d, 0x5d, 0xbd, 0xf7, 0xc0, 0xd5, 0xc1, 0x0a, 0x05, 0xb9, 0xf1, 0x60, 0x7f, 0x78 } +#define SSS_AUTH_SE050_DEVKIT_KEY_DEK \ + {0xa1, 0xbc, 0x84, 0x38, 0xbf, 0x77, 0x93, 0x5b, 0x36, 0x1a, 0x44, 0x25, 0xfe, 0x79, 0xfa, 0x29 } + +// SE051A2 +#define SSS_AUTH_SE051A2_KEY_ENC \ + { 0x84, 0x0a, 0x5d, 0x51, 0x79, 0x55, 0x11, 0xc9, 0xce, 0xf0, 0xc9, 0x6f, 0xd2, 0xcb, 0xf0, 0x41 } +#define SSS_AUTH_SE051A2_KEY_MAC \ + { 0x64, 0x6b, 0xc2, 0xb8, 0xc3, 0xa4, 0xd9, 0xc1, 0xfa, 0x8d, 0x71, 0x16, 0xbe, 0x04, 0xfd, 0xfe } +#define SSS_AUTH_SE051A2_KEY_DEK \ + { 0x03, 0xe6, 0x69, 0x9a, 0xca, 0x94, 0x26, 0xd9, 0xc3, 0x89, 0x22, 0xf8, 0x91, 0x4c, 0xe5, 0xf7 } + +// SE051C2 +#define SSS_AUTH_SE051C2_KEY_ENC \ + { 0x88, 0xdb, 0xcd, 0x65, 0x82, 0x0d, 0x2a, 0xa0, 0x6f, 0xfa, 0xb9, 0x2a, 0xa8, 0xe7, 0x93, 0x64 } +#define SSS_AUTH_SE051C2_KEY_MAC \ + { 0xa8, 0x64, 0x4e, 0x2a, 0x04, 0xd9, 0xe9, 0xc8, 0xc0, 0xea, 0x60, 0x86, 0x68, 0x29, 0x99, 0xe5 } +#define SSS_AUTH_SE051C2_KEY_DEK \ + { 0x8a, 0x38, 0x72, 0x38, 0x99, 0x88, 0x18, 0x44, 0xe2, 0xc1, 0x51, 0x3d, 0xac, 0xd9, 0xf8, 0x0d } + +/* clang-format on */ + +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +#endif /* SSS_AUTH_SE050_OEF_20191211_1809_ */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c new file mode 100644 index 00000000000..c7f878a2dbb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c @@ -0,0 +1,2272 @@ +/* + * SSL client with certificate authentication + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2018-2019, NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* clang-format off */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_time time +#define mbedtls_time_t time_t +#define mbedtls_printf printf +#define mbedtls_fprintf fprintf +#define mbedtls_snprintf snprintf +#endif + +#include + +#if !defined(MBEDTLS_ENTROPY_C) || \ + !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_CLI_C) || \ + !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_CTR_DRBG_C) +int main(void) +{ + mbedtls_printf("MBEDTLS_ENTROPY_C and/or " + "MBEDTLS_SSL_TLS_C and/or MBEDTLS_SSL_CLI_C and/or " + "MBEDTLS_NET_C and/or MBEDTLS_CTR_DRBG_C and/or not defined.\n"); + return (0); +} +#else + +#include "mbedtls/certs.h" +#include "mbedtls/ctr_drbg.h" +#include "mbedtls/debug.h" +#include "mbedtls/entropy.h" +#include "mbedtls/error.h" +#include "mbedtls/net_sockets.h" +#include "mbedtls/ssl.h" +#include "mbedtls/timing.h" +#include "mbedtls/x509.h" + +#include +#include +#include + +/* +S */ + +#ifdef TGT_A71CH +# include "sm_printf.h" +#endif + +#if SSS_HAVE_ALT_SSS +#include "sss_mbedtls.h" +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) +#include "ecdsa_verify_alt.h" +#endif +#endif + +#include +#include +#include + +#if defined(SMCOM_JRCP_V2) && SSS_HAVE_SE05X_VER_GTE_06_00 +#include "smCom.h" +#include "smComJRCP.h" +#include "sm_types.h" +#endif + +static ex_sss_boot_ctx_t gex_sss_demo_boot_ctx; +ex_sss_boot_ctx_t *pex_sss_demo_boot_ctx = &gex_sss_demo_boot_ctx; +static ex_sss_cloud_ctx_t gex_sss_demo_tls_ctx; +ex_sss_cloud_ctx_t *pex_sss_demo_tls_ctx = &gex_sss_demo_tls_ctx; + +#define EX_SSS_BOOT_PCONTEXT (&gex_sss_demo_boot_ctx) +#define EX_SSS_BOOT_EXPOSE_ARGC_ARGV 1 +#define EX_SSS_BOOT_DO_ERASE 0 + +#include + +#define SSS_PUBKEY_INDEX_CA 0x7DCCBB22 //(1u) +#define SSS_KEYPAIR_INDEX_CLIENT_PRIVATE 0x20181001 //(2u) +#define SSS_CERTIFICATE_INDEX 0x20181002 //(3u) + +/*The size of the client certificate should be checked when script is used to store it in GP storage and updated here */ +#define SIZE_CLIENT_CERTIFICATE 2048 +/* -S */ + +#define MAX_REQUEST_SIZE 20000 +#define MAX_REQUEST_SIZE_STR "20000" + +#define DFL_SERVER_NAME "localhost" +#define DFL_SERVER_ADDR NULL +#define DFL_SERVER_PORT "4433" +#define DFL_REQUEST_PAGE "/" +#define DFL_REQUEST_SIZE -1 +#define DFL_DEBUG_LEVEL 0 +#define DFL_NBIO 0 +#define DFL_EVENT 0 +#define DFL_READ_TIMEOUT 0 +#define DFL_MAX_RESEND 0 +#define DFL_CA_FILE "" +#define DFL_CA_PATH "" +#define DFL_CRT_FILE "" +#define DFL_KEY_FILE "" +#define DFL_PSK "" +#define DFL_PSK_IDENTITY "Client_identity" +#define DFL_ECJPAKE_PW NULL +#define DFL_FORCE_CIPHER 0 +#define DFL_RENEGOTIATION MBEDTLS_SSL_RENEGOTIATION_DISABLED +#define DFL_ALLOW_LEGACY -2 +#define DFL_RENEGOTIATE 0 +#define DFL_EXCHANGES 1 +#define DFL_MIN_VERSION -1 +#define DFL_MAX_VERSION -1 +#define DFL_ARC4 -1 +#define DFL_SHA1 -1 +#define DFL_AUTH_MODE -1 +#define DFL_MFL_CODE MBEDTLS_SSL_MAX_FRAG_LEN_NONE +#define DFL_TRUNC_HMAC -1 +#define DFL_RECSPLIT -1 +#define DFL_DHMLEN -1 +#define DFL_RECONNECT 0 +#define DFL_RECO_DELAY 0 +#define DFL_RECONNECT_HARD 0 +#define DFL_TICKETS MBEDTLS_SSL_SESSION_TICKETS_ENABLED +#define DFL_ALPN_STRING NULL +#define DFL_CURVES NULL +#define DFL_TRANSPORT MBEDTLS_SSL_TRANSPORT_STREAM +#define DFL_HS_TO_MIN 0 +#define DFL_HS_TO_MAX 0 +#define DFL_FALLBACK -1 +#define DFL_EXTENDED_MS -1 +#define DFL_ETM -1 +#define DFL_CONNECT "" + +#define GET_REQUEST "GET %s HTTP/1.0\r\nExtra-header: " +#define GET_REQUEST_END "\r\n\r\n" + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +#if defined(MBEDTLS_FS_IO) +#define USAGE_IO \ + " ca_file=%%s The single file containing the top-level CA(s) you fully trust\n" \ + " default: \"\" (pre-loaded)\n" \ + " ca_path=%%s The path containing the top-level CA(s) you fully trust\n" \ + " default: \"\" (pre-loaded) (overrides ca_file)\n" \ + " crt_file=%%s Your own cert and chain (in bottom to top order, top may be omitted)\n" \ + " default: \"\" (pre-loaded)\n" \ + " key_file=%%s default: \"\" (pre-loaded)\n" \ + +#else +#define USAGE_IO \ + " No file operations available (MBEDTLS_FS_IO not defined)\n" +#endif /* MBEDTLS_FS_IO */ +#else +#define USAGE_IO "" +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) +#define USAGE_PSK \ + " psk=%%s default: \"\" (in hex, without 0x)\n" \ + " psk_identity=%%s default: \"Client_identity\"\n" +#else +#define USAGE_PSK "" +#endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */ + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) +#define USAGE_TICKETS \ + " tickets=%%d default: 1 (enabled)\n" +#else +#define USAGE_TICKETS "" +#endif /* MBEDTLS_SSL_SESSION_TICKETS */ + +#if defined(MBEDTLS_SSL_TRUNCATED_HMAC) +#define USAGE_TRUNC_HMAC \ + " trunc_hmac=%%d default: library default\n" +#else +#define USAGE_TRUNC_HMAC "" +#endif /* MBEDTLS_SSL_TRUNCATED_HMAC */ + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) +#define USAGE_MAX_FRAG_LEN \ + " max_frag_len=%%d default: 16384 (tls default)\n" \ + " options: 512, 1024, 2048, 4096\n" +#else +#define USAGE_MAX_FRAG_LEN "" +#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ + +#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) +#define USAGE_RECSPLIT \ + " recsplit=0/1 default: (library default: on)\n" +#else +#define USAGE_RECSPLIT +#endif + +#if defined(MBEDTLS_DHM_C) +#define USAGE_DHMLEN \ + " dhmlen=%%d default: (library default: 1024 bits)\n" +#else +#define USAGE_DHMLEN +#endif + +#if defined(MBEDTLS_SSL_ALPN) +#define USAGE_ALPN \ + " alpn=%%s default: \"\" (disabled)\n" \ + " example: spdy/1,http/1.1\n" +#else +#define USAGE_ALPN "" +#endif /* MBEDTLS_SSL_ALPN */ + +#if defined(MBEDTLS_ECP_C) +#define USAGE_CURVES \ + " curves=a,b,c,d default: \"default\" (library default)\n" \ + " example: \"secp521r1,brainpoolP512r1\"\n" \ + " - use \"none\" for empty list\n" \ + " - see mbedtls_ecp_curve_list()\n" \ + " for acceptable curve names\n" +#else +#define USAGE_CURVES "" +#endif + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +#define USAGE_DTLS \ + " dtls=%%d default: 0 (TLS)\n" \ + " hs_timeout=%%d-%%d default: (library default: 1000-60000)\n" \ + " range of DTLS handshake timeouts in millisecs\n" +#else +#define USAGE_DTLS "" +#endif + +#if defined(MBEDTLS_SSL_FALLBACK_SCSV) +#define USAGE_FALLBACK \ + " fallback=0/1 default: (library default: off)\n" +#else +#define USAGE_FALLBACK "" +#endif + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) +#define USAGE_EMS \ + " extended_ms=0/1 default: (library default: on)\n" +#else +#define USAGE_EMS "" +#endif + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) +#define USAGE_ETM \ + " etm=0/1 default: (library default: on)\n" +#else +#define USAGE_ETM "" +#endif + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +#define USAGE_RENEGO \ + " renegotiation=%%d default: 0 (disabled)\n" \ + " renegotiate=%%d default: 0 (disabled)\n" +#else +#define USAGE_RENEGO "" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) +#define USAGE_ECJPAKE \ + " ecjpake_pw=%%s default: none (disabled)\n" +#else +#define USAGE_ECJPAKE "" +#endif + +#define USAGE \ + "\n usage: ssl_client2 param=<>...\n" \ + "\n acceptable parameters:\n" \ + " server_name=%%s default: localhost\n" \ + " server_addr=%%s default: given by name\n" \ + " server_port=%%d default: 4433\n" \ + " request_page=%%s default: \".\"\n" \ + " request_size=%%d default: about 34 (basic request)\n" \ + " (minimum: 0, max: " MAX_REQUEST_SIZE_STR ")\n" \ + " If 0, in the first exchange only an empty\n" \ + " application data message is sent followed by\n" \ + " a second non-empty message before attempting\n" \ + " to read a response from the server\n" \ + " debug_level=%%d default: 0 (disabled)\n" \ + " nbio=%%d default: 0 (blocking I/O)\n" \ + " options: 1 (non-blocking), 2 (added delays)\n" \ + " event=%%d default: 0 (loop)\n" \ + " options: 1 (level-triggered, implies nbio=1),\n" \ + " read_timeout=%%d default: 0 ms (no timeout)\n" \ + " max_resend=%%d default: 0 (no resend on timeout)\n" \ + "\n" \ + USAGE_DTLS \ + "\n" \ + " auth_mode=%%s default: (library default: none)\n" \ + " options: none, optional, required\n" \ + USAGE_IO \ + "\n" \ + USAGE_PSK \ + USAGE_ECJPAKE \ + "\n" \ + " allow_legacy=%%d default: (library default: no)\n" \ + USAGE_RENEGO \ + " exchanges=%%d default: 1\n" \ + " reconnect=%%d default: 0 (disabled)\n" \ + " reco_delay=%%d default: 0 seconds\n" \ + " reconnect_hard=%%d default: 0 (disabled)\n" \ + USAGE_TICKETS \ + USAGE_MAX_FRAG_LEN \ + USAGE_TRUNC_HMAC \ + USAGE_ALPN \ + USAGE_FALLBACK \ + USAGE_EMS \ + USAGE_ETM \ + USAGE_CURVES \ + USAGE_RECSPLIT \ + USAGE_DHMLEN \ + "\n" \ + " arc4=%%d default: (library default: 0)\n" \ + " allow_sha1=%%d default: 0\n" \ + " min_version=%%s default: (library default: tls1)\n" \ + " max_version=%%s default: (library default: tls1_2)\n" \ + " force_version=%%s default: \"\" (none)\n" \ + " options: ssl3, tls1, tls1_1, tls1_2, dtls1, dtls1_2\n" \ + "\n" \ + " force_ciphersuite= default: all enabled\n" \ + " acceptable ciphersuite names:\n" + +#define ALPN_LIST_SIZE 10 +#define CURVE_LIST_SIZE 20 + +/* +* global options +*/ +struct options +{ + const char *server_name; /* hostname of the server (client only) */ + const char *server_addr; /* address of the server (client only) */ + const char *server_port; /* port on which the ssl service runs */ + int debug_level; /* level of debugging */ + int nbio; /* should I/O be blocking? */ + int event; /* loop or event-driven IO? level or edge triggered? */ + uint32_t read_timeout; /* timeout on mbedtls_ssl_read() in milliseconds */ + int max_resend; /* DTLS times to resend on read timeout */ + const char *request_page; /* page on server to request */ + int request_size; /* pad request with header to requested size */ + const char *ca_file; /* the file with the CA certificate(s) */ + const char *ca_path; /* the path with the CA certificate(s) reside */ + const char *crt_file; /* the file with the client certificate */ + const char *key_file; /* the file with the client key */ + const char *psk; /* the pre-shared key */ + const char *psk_identity; /* the pre-shared key identity */ + const char *ecjpake_pw; /* the EC J-PAKE password */ + int force_ciphersuite[2]; /* protocol/ciphersuite to use, or all */ + int renegotiation; /* enable / disable renegotiation */ + int allow_legacy; /* allow legacy renegotiation */ + int renegotiate; /* attempt renegotiation? */ + int renego_delay; /* delay before enforcing renegotiation */ + int exchanges; /* number of data exchanges */ + int min_version; /* minimum protocol version accepted */ + int max_version; /* maximum protocol version accepted */ + int arc4; /* flag for arc4 suites support */ + int allow_sha1; /* flag for SHA-1 support */ + int auth_mode; /* verify mode for connection */ + unsigned char mfl_code; /* code for maximum fragment length */ + int trunc_hmac; /* negotiate truncated hmac or not */ + int recsplit; /* enable record splitting? */ + int dhmlen; /* minimum DHM params len in bits */ + int reconnect; /* attempt to resume session */ + int reco_delay; /* delay in seconds before resuming session */ + int reconnect_hard; /* unexpectedly reconnect from the same port */ + int tickets; /* enable / disable session tickets */ + const char *curves; /* list of supported elliptic curves */ + const char *alpn_string; /* ALPN supported protocols */ + int transport; /* TLS or DTLS? */ + uint32_t hs_to_min; /* Initial value of DTLS handshake timer */ + uint32_t hs_to_max; /* Max value of DTLS handshake timer */ + int fallback; /* is this a fallback connection? */ + int extended_ms; /* negotiate extended master secret? */ + int etm; /* negotiate encrypt then mac? */ + +} opt; + +static void my_debug( void *ctx, int level, + const char *file, int line, + const char *str ) +{ + const char *p, *basename; + + /* Extract basename from file */ + for (p = basename = file; *p != '\0'; p++) + if (*p == '/' || *p == '\\') + basename = p + 1; + + mbedtls_fprintf( (FILE *) ctx, "%s:%04d: |%d| %s", + basename, line, level, str ); + fflush((FILE *)ctx); +} + +/* +* Test recv/send functions that make sure each try returns +* WANT_READ/WANT_WRITE at least once before sucesseding +*/ +static int my_recv(void *ctx, unsigned char *buf, size_t len) +{ + static int first_try = 1; + int ret; + + if( first_try ) + { + first_try = 0; + return (MBEDTLS_ERR_SSL_WANT_READ); + } + + ret = mbedtls_net_recv(ctx, buf, len); + if (ret != MBEDTLS_ERR_SSL_WANT_READ) + first_try = 1; /* Next call will be a new operation */ + return (ret); +} + + +#ifdef _MSC_VER +#pragma warning( disable: 4127) +#endif + +static int my_send(void *ctx, const unsigned char *buf, size_t len) +{ + static int first_try = 1; + int ret; + + if( first_try ) + { + first_try = 0; + return (MBEDTLS_ERR_SSL_WANT_WRITE); + } + + ret = mbedtls_net_send(ctx, buf, len); + if (ret != MBEDTLS_ERR_SSL_WANT_WRITE) + first_try = 1; /* Next call will be a new operation */ + return (ret); +} + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/* +* Enabled if debug_level > 1 in code below +*/ +static int my_verify( void *data, mbedtls_x509_crt *crt, + int depth, uint32_t *flags ) +{ + char buf[1024]; + ((void)data); + + mbedtls_printf("\nVerify requested for (Depth %d):\n", depth); + mbedtls_x509_crt_info(buf, sizeof(buf) - 1, "", crt); + mbedtls_printf("%s", buf); + + if ((*flags) == 0) + mbedtls_printf(" This certificate has no flags\n"); + else + { + mbedtls_x509_crt_verify_info(buf, sizeof(buf), " ! ", *flags); + mbedtls_printf("%s\n", buf); + } + + return (0); +} + +static int ssl_sig_hashes_for_test[] = { +#if defined(MBEDTLS_SHA512_C) + MBEDTLS_MD_SHA512, + MBEDTLS_MD_SHA384, +#endif +#if defined(MBEDTLS_SHA256_C) + MBEDTLS_MD_SHA256, + MBEDTLS_MD_SHA224, +#endif +#if defined(MBEDTLS_SHA1_C) + /* Allow SHA-1 as we use it extensively in tests. */ + MBEDTLS_MD_SHA1, +#endif + MBEDTLS_MD_NONE + +}; +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/* + * Wait for an event from the underlying transport or the timer + * (Used in event-driven IO mode). + */ +#if !defined(MBEDTLS_TIMING_C) +int idle( mbedtls_net_context *fd, + int idle_reason ) +#else +int idle( mbedtls_net_context *fd, + mbedtls_timing_delay_context *timer, + int idle_reason ) +#endif +{ + + int ret; + int poll_type = 0; + + if( idle_reason == MBEDTLS_ERR_SSL_WANT_WRITE ) + poll_type = MBEDTLS_NET_POLL_WRITE; + else if( idle_reason == MBEDTLS_ERR_SSL_WANT_READ ) + poll_type = MBEDTLS_NET_POLL_READ; +#if !defined(MBEDTLS_TIMING_C) + else + return( 0 ); +#endif + + while( 1 ) + { + /* Check if timer has expired */ +#if defined(MBEDTLS_TIMING_C) + if( timer != NULL && + mbedtls_timing_get_delay( timer ) == 2 ) + { + break; + } +#endif /* MBEDTLS_TIMING_C */ + + /* Check if underlying transport became available */ + if( poll_type != 0 ) + { + ret = mbedtls_net_poll( fd, poll_type, 0 ); + if( ret < 0 ) + return( ret ); + if( ret == poll_type ) + break; + } + } + + return( 0 ); +} + +sss_status_t ex_sss_entry(ex_sss_boot_ctx_t *pCtx) +{ + int ret = 0, len, tail_len, i, written, frags, retry_left; + bool useKeysFromSM = true; + int client_certificate_loaded = 0; + sss_status_t ret_code; + uint8_t aclient_cer[SIZE_CLIENT_CERTIFICATE] = {0}; + + mbedtls_net_context server_fd; + unsigned char buf[MAX_REQUEST_SIZE + 1]; +#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) + unsigned char psk[MBEDTLS_PSK_MAX_LEN]; + size_t psk_len = 0; +#endif +#if defined(MBEDTLS_SSL_ALPN) + const char *alpn_list[ALPN_LIST_SIZE]; +#endif +#if defined(MBEDTLS_ECP_C) + mbedtls_ecp_group_id curve_list[CURVE_LIST_SIZE]; + const mbedtls_ecp_curve_info *curve_cur; +#endif + + const char *pers = "ssl_client2"; + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + mbedtls_x509_crt_profile crt_profile_for_test = mbedtls_x509_crt_profile_default; +#endif + mbedtls_entropy_context entropy; + mbedtls_ctr_drbg_context ctr_drbg; + mbedtls_ssl_context ssl; + mbedtls_ssl_config conf; + mbedtls_ssl_session saved_session; +#if defined(MBEDTLS_TIMING_C) + mbedtls_timing_delay_context timer; +#endif +#if defined(MBEDTLS_X509_CRT_PARSE_C) + uint32_t flags; + mbedtls_x509_crt cacert; + mbedtls_x509_crt clicert; + mbedtls_pk_context pkey; +#endif + char *p, *q; + const int *list; + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) /* Set public key is causing NVM writes */ +#if defined(SMCOM_JRCP_V2) && SSS_HAVE_SE05X_VER_GTE_06_00 + uint32_t start_nvmCount = 0; + uint32_t end_nvmCount = 0; +#endif +#endif + + /* + * Make sure memory references are valid. + */ + mbedtls_net_init( &server_fd ); + mbedtls_ssl_init( &ssl ); + mbedtls_ssl_config_init( &conf ); + memset( &saved_session, 0, sizeof( mbedtls_ssl_session ) ); + mbedtls_ctr_drbg_init( &ctr_drbg ); +#if defined(MBEDTLS_X509_CRT_PARSE_C) + mbedtls_x509_crt_init( &cacert ); + mbedtls_x509_crt_init( &clicert ); + mbedtls_pk_init( &pkey ); +#endif +#if defined(MBEDTLS_SSL_ALPN) + memset( (void * ) alpn_list, 0, sizeof( alpn_list ) ); +#endif + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) /* Set public key is causing NVM writes */ +#if defined(SMCOM_JRCP_V2) && SSS_HAVE_SE05X_VER_GTE_06_00 + { + uint32_t status = kStatus_SSS_Fail; + sss_se05x_session_t *pSe05xSession = (sss_se05x_session_t *)&pCtx->session; + status = smComJRCP_NvmCount(pSe05xSession->s_ctx.conn_ctx, &start_nvmCount); + if (status == SMCOM_OK) { + mbedtls_printf("NVM count at start : %u \n", start_nvmCount); + } + } +#endif +#endif + if(gex_sss_argc == 0 ) + { + usage: + if (ret == 0) + ret = 1; + + mbedtls_printf(USAGE); + + list = mbedtls_ssl_list_ciphersuites(); + while( *list ) + { + mbedtls_printf(" %-42s", mbedtls_ssl_get_ciphersuite_name(*list)); + list++; + if (!*list) + break; + mbedtls_printf(" %s\n", mbedtls_ssl_get_ciphersuite_name(*list)); + list++; + } + mbedtls_printf("\n"); + goto exit; + } + + opt.server_name = DFL_SERVER_NAME; + opt.server_addr = DFL_SERVER_ADDR; + opt.server_port = DFL_SERVER_PORT; + opt.debug_level = DFL_DEBUG_LEVEL; + opt.nbio = DFL_NBIO; + opt.event = DFL_EVENT; + opt.read_timeout = DFL_READ_TIMEOUT; + opt.max_resend = DFL_MAX_RESEND; + opt.request_page = DFL_REQUEST_PAGE; + opt.request_size = DFL_REQUEST_SIZE; + opt.ca_file = DFL_CA_FILE; + opt.ca_path = DFL_CA_PATH; + opt.crt_file = DFL_CRT_FILE; + opt.key_file = DFL_KEY_FILE; + opt.psk = DFL_PSK; + opt.psk_identity = DFL_PSK_IDENTITY; + opt.ecjpake_pw = DFL_ECJPAKE_PW; + opt.force_ciphersuite[0] = DFL_FORCE_CIPHER; + opt.renegotiation = DFL_RENEGOTIATION; + opt.allow_legacy = DFL_ALLOW_LEGACY; + opt.renegotiate = DFL_RENEGOTIATE; + opt.exchanges = DFL_EXCHANGES; + opt.min_version = DFL_MIN_VERSION; + opt.max_version = DFL_MAX_VERSION; + opt.arc4 = DFL_ARC4; + opt.allow_sha1 = DFL_SHA1; + opt.auth_mode = DFL_AUTH_MODE; + opt.mfl_code = DFL_MFL_CODE; + opt.trunc_hmac = DFL_TRUNC_HMAC; + opt.recsplit = DFL_RECSPLIT; + opt.dhmlen = DFL_DHMLEN; + opt.reconnect = DFL_RECONNECT; + opt.reco_delay = DFL_RECO_DELAY; + opt.reconnect_hard = DFL_RECONNECT_HARD; + opt.tickets = DFL_TICKETS; + opt.alpn_string = DFL_ALPN_STRING; + opt.curves = DFL_CURVES; + opt.transport = DFL_TRANSPORT; + opt.hs_to_min = DFL_HS_TO_MIN; + opt.hs_to_max = DFL_HS_TO_MAX; + opt.fallback = DFL_FALLBACK; + opt.extended_ms = DFL_EXTENDED_MS; + opt.etm = DFL_ETM; + + /* Ignore the last command line argument (used in ex_sss_main_inc.h) */ + gex_sss_argc--; + for (i = 1; i < gex_sss_argc; i++) + { + p = (char *)gex_sss_argv[i]; + printf("%s \n", p); + if ((q = strchr(p, '=')) == NULL) + goto usage; + *q++ = '\0'; + + if (strcmp(p, "server_name") == 0) + opt.server_name = q; + else if (strcmp(p, "server_addr") == 0) + opt.server_addr = q; + else if (strcmp(p, "server_port") == 0) + opt.server_port = q; + else if( strcmp( p, "dtls" ) == 0 ) + { + int t = atoi(q); + if (t == 0) + opt.transport = MBEDTLS_SSL_TRANSPORT_STREAM; + else if (t == 1) + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + else + goto usage; + } + else if( strcmp( p, "debug_level" ) == 0 ) + { + opt.debug_level = atoi(q); + if (opt.debug_level < 0 || opt.debug_level > 65535) + goto usage; + } + else if( strcmp( p, "nbio" ) == 0 ) + { + opt.nbio = atoi(q); + if (opt.nbio < 0 || opt.nbio > 2) + goto usage; + } + else if( strcmp( p, "event" ) == 0 ) + { + opt.event = atoi( q ); + if( opt.event < 0 || opt.event > 2 ) + goto usage; + } + else if (strcmp(p, "read_timeout") == 0) + opt.read_timeout = atoi(q); + else if( strcmp( p, "max_resend" ) == 0 ) + { + opt.max_resend = atoi(q); + if (opt.max_resend < 0) + goto usage; + } + else if (strcmp(p, "request_page") == 0) + opt.request_page = q; + else if( strcmp( p, "request_size" ) == 0 ) + { + opt.request_size = atoi(q); + if( opt.request_size < 0 || + opt.request_size > MAX_REQUEST_SIZE ) + goto usage; + } + else if (strcmp(p, "ca_file") == 0) + opt.ca_file = q; + else if (strcmp(p, "ca_path") == 0) + opt.ca_path = q; + else if (strcmp(p, "crt_file") == 0) + opt.crt_file = q; + else if (strcmp(p, "key_file") == 0) + opt.key_file = q; + else if (strcmp(p, "psk") == 0) + opt.psk = q; + else if (strcmp(p, "psk_identity") == 0) + opt.psk_identity = q; + else if (strcmp(p, "ecjpake_pw") == 0) + opt.ecjpake_pw = q; + else if( strcmp( p, "force_ciphersuite" ) == 0 ) + { + opt.force_ciphersuite[0] = mbedtls_ssl_get_ciphersuite_id(q); + + if( opt.force_ciphersuite[0] == 0 ) + { + ret = 2; + goto usage; + } + opt.force_ciphersuite[1] = 0; + } + else if( strcmp( p, "renegotiation" ) == 0 ) + { + opt.renegotiation = (atoi( q )) ? + MBEDTLS_SSL_RENEGOTIATION_ENABLED : + MBEDTLS_SSL_RENEGOTIATION_DISABLED; + } + else if( strcmp( p, "allow_legacy" ) == 0 ) + { + switch( atoi( q ) ) + { + case -1: + opt.allow_legacy = MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE; + break; + case 0: + opt.allow_legacy = MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION; + break; + case 1: + opt.allow_legacy = MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION; + break; + default: goto usage; + } + } + else if( strcmp( p, "renegotiate" ) == 0 ) + { + opt.renegotiate = atoi(q); + if (opt.renegotiate < 0 || opt.renegotiate > 1) + goto usage; + } + else if( strcmp( p, "exchanges" ) == 0 ) + { + opt.exchanges = atoi(q); + if (opt.exchanges < 1) + goto usage; + } + else if( strcmp( p, "reconnect" ) == 0 ) + { + opt.reconnect = atoi(q); + if (opt.reconnect < 0 || opt.reconnect > 2) + goto usage; + } + else if( strcmp( p, "reco_delay" ) == 0 ) + { + opt.reco_delay = atoi(q); + if (opt.reco_delay < 0) + goto usage; + } + else if( strcmp( p, "reconnect_hard" ) == 0 ) + { + opt.reconnect_hard = atoi(q); + if (opt.reconnect_hard < 0 || opt.reconnect_hard > 1) + goto usage; + } + else if( strcmp( p, "tickets" ) == 0 ) + { + opt.tickets = atoi(q); + if (opt.tickets < 0 || opt.tickets > 2) + goto usage; + } + else if( strcmp( p, "alpn" ) == 0 ) + { + opt.alpn_string = q; + } + else if( strcmp( p, "fallback" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.fallback = MBEDTLS_SSL_IS_NOT_FALLBACK; break; + case 1: opt.fallback = MBEDTLS_SSL_IS_FALLBACK; break; + default: goto usage; + } + } + else if( strcmp( p, "extended_ms" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: + opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_DISABLED; + break; + case 1: + opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_ENABLED; + break; + default: goto usage; + } + } + else if (strcmp(p, "curves") == 0) + opt.curves = q; + else if( strcmp( p, "etm" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.etm = MBEDTLS_SSL_ETM_DISABLED; break; + case 1: opt.etm = MBEDTLS_SSL_ETM_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "min_version" ) == 0 ) + { + if (strcmp(q, "ssl3") == 0) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; + else if (strcmp(q, "tls1") == 0) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; + else if( strcmp( q, "tls1_1" ) == 0 || + strcmp( q, "dtls1" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + else if( strcmp( q, "tls1_2" ) == 0 || + strcmp( q, "dtls1_2" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + else + goto usage; + } + else if( strcmp( p, "max_version" ) == 0 ) + { + if (strcmp(q, "ssl3") == 0) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; + else if (strcmp(q, "tls1") == 0) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; + else if( strcmp( q, "tls1_1" ) == 0 || + strcmp( q, "dtls1" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + else if( strcmp( q, "tls1_2" ) == 0 || + strcmp( q, "dtls1_2" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + else + goto usage; + } + else if( strcmp( p, "arc4" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.arc4 = MBEDTLS_SSL_ARC4_DISABLED; break; + case 1: opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "allow_sha1" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.allow_sha1 = 0; break; + case 1: opt.allow_sha1 = 1; break; + default: goto usage; + } + } + else if( strcmp( p, "force_version" ) == 0 ) + { + if( strcmp( q, "ssl3" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; + } + else if( strcmp( q, "tls1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; + } + else if( strcmp( q, "tls1_1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + } + else if( strcmp( q, "tls1_2" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + } + else if( strcmp( q, "dtls1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + } + else if( strcmp( q, "dtls1_2" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + } + else + goto usage; + } + else if( strcmp( p, "auth_mode" ) == 0 ) + { + if (strcmp(q, "none") == 0) + opt.auth_mode = MBEDTLS_SSL_VERIFY_NONE; + else if (strcmp(q, "optional") == 0) + opt.auth_mode = MBEDTLS_SSL_VERIFY_OPTIONAL; + else if (strcmp(q, "required") == 0) + opt.auth_mode = MBEDTLS_SSL_VERIFY_REQUIRED; + else + goto usage; + } + else if( strcmp( p, "max_frag_len" ) == 0 ) + { + if (strcmp(q, "512") == 0) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_512; + else if (strcmp(q, "1024") == 0) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_1024; + else if (strcmp(q, "2048") == 0) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_2048; + else if (strcmp(q, "4096") == 0) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_4096; + else + goto usage; + } + else if( strcmp( p, "trunc_hmac" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_DISABLED; break; + case 1: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "hs_timeout" ) == 0 ) + { + if ((p = strchr(q, '-')) == NULL) + goto usage; + *p++ = '\0'; + opt.hs_to_min = atoi(q); + opt.hs_to_max = atoi(p); + if (opt.hs_to_min == 0 || opt.hs_to_max < opt.hs_to_min) + goto usage; + } + else if( strcmp( p, "recsplit" ) == 0 ) + { + opt.recsplit = atoi(q); + if (opt.recsplit < 0 || opt.recsplit > 1) + goto usage; + } + else if( strcmp( p, "dhmlen" ) == 0 ) + { + opt.dhmlen = atoi(q); + if (opt.dhmlen < 0) + goto usage; + } + else + goto usage; + } + + /* clang-format on */ + + if (strcmp(opt.key_file, "none") == 0) { + useKeysFromSM = true; + } + else { + useKeysFromSM = false; + } + + if (useKeysFromSM) { + sss_status_t status; + + /* doc+:initialize-key-objs */ + + /* pex_sss_demo_tls_ctx->obj will have the private key handle */ + status = sss_key_object_init(&pex_sss_demo_tls_ctx->obj, &pCtx->ks); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_init for keyPair Failed...\n"); + return kStatus_SSS_Fail; + } + + status = sss_key_object_get_handle(&pex_sss_demo_tls_ctx->obj, SSS_KEYPAIR_INDEX_CLIENT_PRIVATE); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_get_handle for keyPair Failed...\n"); + return kStatus_SSS_Fail; + } + + /* + * All ecdsa verification is done using the esdsa_alt file. No need to associate the root ca pub key. + */ +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) + /* pex_sss_demo_tls_ctx->pub_obj will have the root CA public key */ + status = sss_key_object_init(&pex_sss_demo_tls_ctx->pub_obj, &pCtx->ks); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_init for Pub key Failed...\n"); + return kStatus_SSS_Fail; + } + + status = sss_key_object_get_handle(&pex_sss_demo_tls_ctx->pub_obj, SSS_PUBKEY_INDEX_CA); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_get_handle for extPubkey Failed...\n"); + return kStatus_SSS_Fail; + } +#endif + + /* pex_sss_demo_tls_ctx->dev_cert will have the our device certificate */ + status = sss_key_object_init(&pex_sss_demo_tls_ctx->dev_cert, &pCtx->ks); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_init for Pub key Failed...\n"); + return kStatus_SSS_Fail; + } + status = sss_key_object_get_handle(&pex_sss_demo_tls_ctx->dev_cert, SSS_CERTIFICATE_INDEX); + if (status != kStatus_SSS_Success) { + printf(" sss_key_object_get_handle for client Cert Failed...\n"); + return kStatus_SSS_Fail; + } + /* doc-:initialize-key-objs */ + } + else { + printf("WARNING!!!!!!!!!!!! using keys from file system"); + } + + /* clang-format off */ + + /* Event-driven IO is incompatible with the above custom + * receive and send functions, as the polling builds on + * refers to the underlying net_context. */ + if( opt.event == 1 && opt.nbio != 1 ) + { + mbedtls_printf( "Warning: event-driven IO mandates nbio=1 - overwrite\n" ); + opt.nbio = 1; + } + +#if defined(MBEDTLS_DEBUG_C) + mbedtls_debug_set_threshold(opt.debug_level); +#endif + + if( opt.force_ciphersuite[0] > 0 ) + { + const mbedtls_ssl_ciphersuite_t *ciphersuite_info; + ciphersuite_info = + mbedtls_ssl_ciphersuite_from_id( opt.force_ciphersuite[0] ); + + if (opt.max_version != -1 && + ciphersuite_info->min_minor_ver > opt.max_version ) + { + mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); + ret = 2; + goto usage; + } + if (opt.min_version != -1 && + ciphersuite_info->max_minor_ver < opt.min_version ) + { + mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); + ret = 2; + goto usage; + } + + /* If the server selects a version that's not supported by + * this suite, then there will be no common ciphersuite... */ + if (opt.max_version == -1 || + opt.max_version > ciphersuite_info->max_minor_ver ) + { + opt.max_version = ciphersuite_info->max_minor_ver; + } + if( opt.min_version < ciphersuite_info->min_minor_ver ) + { + opt.min_version = ciphersuite_info->min_minor_ver; + /* DTLS starts with TLS 1.1 */ + if (opt.transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + opt.min_version < MBEDTLS_SSL_MINOR_VERSION_2) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + } + + /* Enable RC4 if needed and not explicitly disabled */ + if( ciphersuite_info->cipher == MBEDTLS_CIPHER_ARC4_128 ) + { + if( opt.arc4 == MBEDTLS_SSL_ARC4_DISABLED ) + { + mbedtls_printf("forced RC4 ciphersuite with RC4 disabled\n"); + ret = 2; + goto usage; + } + + opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; + } + } + +#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) + /* + * Unhexify the pre-shared key if any is given + */ + if( strlen( opt.psk ) ) + { + unsigned char c; + size_t j; + + if( strlen( opt.psk ) % 2 != 0 ) + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + + psk_len = strlen(opt.psk) / 2; + + for( j = 0; j < strlen( opt.psk ); j += 2 ) + { + c = opt.psk[j]; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c >= 'a' && c <= 'f') + c -= 'a' - 10; + else if (c >= 'A' && c <= 'F') + c -= 'A' - 10; + else + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + psk[j / 2] = c << 4; + + c = opt.psk[j + 1]; + if (c >= '0' && c <= '9') + c -= '0'; + else if (c >= 'a' && c <= 'f') + c -= 'a' - 10; + else if (c >= 'A' && c <= 'F') + c -= 'A' - 10; + else + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + psk[j / 2] |= c; + } + } +#endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */ + +#if defined(MBEDTLS_ECP_C) + if( opt.curves != NULL ) + { + p = (char *)opt.curves; + i = 0; + + if( strcmp( p, "none" ) == 0 ) + { + curve_list[0] = MBEDTLS_ECP_DP_NONE; + } + else if( strcmp( p, "default" ) != 0 ) + { + /* Leave room for a final NULL in curve list */ + while( i < CURVE_LIST_SIZE - 1 && *p != '\0' ) + { + q = p; + + /* Terminate the current string */ + while (*p != ',' && *p != '\0') + p++; + if (*p == ',') + *p++ = '\0'; + + if( ( curve_cur = mbedtls_ecp_curve_info_from_name( q ) ) != NULL ) + { + curve_list[i++] = curve_cur->grp_id; + } + else + { + mbedtls_printf("unknown curve %s\n", q); + mbedtls_printf("supported curves: "); + for (curve_cur = mbedtls_ecp_curve_list(); + curve_cur->grp_id != MBEDTLS_ECP_DP_NONE; + curve_cur++ ) + { + mbedtls_printf("%s ", curve_cur->name); + } + mbedtls_printf("\n"); + goto exit; + } + } + + mbedtls_printf("Number of curves: %d\n", i); + + if( i == CURVE_LIST_SIZE - 1 && *p != '\0' ) + { + mbedtls_printf( "curves list too long, maximum %d", + CURVE_LIST_SIZE - 1 ); + goto exit; + } + + curve_list[i] = MBEDTLS_ECP_DP_NONE; + } + } +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_SSL_ALPN) + if( opt.alpn_string != NULL ) + { + p = (char *)opt.alpn_string; + i = 0; + + /* Leave room for a final NULL in alpn_list */ + while( i < ALPN_LIST_SIZE - 1 && *p != '\0' ) + { + alpn_list[i++] = p; + + /* Terminate the current string and move on to next one */ + while (*p != ',' && *p != '\0') + p++; + if (*p == ',') + *p++ = '\0'; + } + } +#endif /* MBEDTLS_SSL_ALPN */ + + /* + * 0. Initialize the RNG and the session data + */ + mbedtls_printf("\n . Seeding the random number generator..."); + fflush(stdout); + + mbedtls_entropy_init(&entropy); + if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, + &entropy, (const unsigned char *) pers, + strlen( pers ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ctr_drbg_seed returned -0x%x\n", + -ret ); + goto exit; + } + + mbedtls_printf(" ok\n"); + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + /* + * 1.1. Load the trusted CA + */ + mbedtls_printf(" . Loading the CA root certificate ..."); + fflush(stdout); + +#if defined(MBEDTLS_FS_IO) + if (strlen(opt.ca_path)) + if (strcmp(opt.ca_path, "none") == 0) + ret = 0; + else + ret = mbedtls_x509_crt_parse_path(&cacert, opt.ca_path); + else if (strlen(opt.ca_file)) + if (strcmp(opt.ca_file, "none") == 0) + ret = 0; + else + ret = mbedtls_x509_crt_parse_file(&cacert, opt.ca_file); + else +#endif +#if defined(MBEDTLS_CERTS_C) + for( i = 0; mbedtls_test_cas[i] != NULL; i++ ) + { + ret = mbedtls_x509_crt_parse(&cacert, + (const unsigned char *)mbedtls_test_cas[i], + mbedtls_test_cas_len[i]); + if (ret != 0) + break; + } +#else + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } +#endif + if (useKeysFromSM) { + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) + /* doc+:use-public-key-from-se */ + mbedtls_pk_free(&cacert.pk); + ret = sss_mbedtls_associate_pubkey(&cacert.pk, &pex_sss_demo_tls_ctx->pub_obj); + /* doc-:use-public-key-from-se */ +#else + /* doc+:ecdsa-verify-alt-set-keystore */ + sss_mbedtls_set_sss_keystore(&pCtx->ks); + /* doc-:ecdsa-verify-alt-set-keystore */ +#endif + } + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", + -ret ); + goto exit; + } + + mbedtls_printf(" ok (%d skipped)\n", ret); + + /* + * 1.2. Load own certificate and private key + * + * (can be skipped if client authentication is not required) + */ + mbedtls_printf(" . Loading the client cert. and key..."); + fflush(stdout); + +#if defined(MBEDTLS_FS_IO) + if (strlen(opt.crt_file)) + if( strcmp( opt.crt_file, "none" ) == 0 ) + { + + /* doc+:load-certificate-from-se */ + size_t KeyBitLen = SIZE_CLIENT_CERTIFICATE * 8; + size_t KeyByteLen = SIZE_CLIENT_CERTIFICATE; + + ret_code = sss_key_store_get_key( + &pCtx->ks, &pex_sss_demo_tls_ctx->dev_cert, aclient_cer, &KeyByteLen, &KeyBitLen); + + ret = mbedtls_x509_crt_parse_der(&clicert, + (const unsigned char *)aclient_cer, + sizeof(aclient_cer)); + if ((ret_code == kStatus_SSS_Success) && (ret == 0)) { + client_certificate_loaded = 1; + } + /* doc-:load-certificate-from-se */ + } + else + + ret = mbedtls_x509_crt_parse_file(&clicert, opt.crt_file); + else +#endif +#if defined(MBEDTLS_CERTS_C) + ret = mbedtls_x509_crt_parse( &clicert, + (const unsigned char *) mbedtls_test_cli_crt, + mbedtls_test_cli_crt_len); +#else + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } +#endif + if (useKeysFromSM) { + // for private key, we use the KEY from SE. + mbedtls_pk_free(&clicert.pk); + } + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", + -ret ); + goto exit; + } + +#if defined(MBEDTLS_FS_IO) + if (useKeysFromSM) { + /* doc+:set-handle-to-use-private-key-from-se */ + sss_mbedtls_associate_keypair(&pkey, &pex_sss_demo_tls_ctx->obj); + /* doc-:set-handle-to-use-private-key-from-se */ + } + else if (strlen(opt.key_file)) + if (strcmp(opt.key_file, "none") == 0) + ret = 0; + else + ret = mbedtls_pk_parse_keyfile(&pkey, opt.key_file, ""); + else +#endif +#if defined(MBEDTLS_CERTS_C) + ret = mbedtls_pk_parse_key( &pkey, + (const unsigned char *) mbedtls_test_cli_key, + mbedtls_test_cli_key_len, NULL, 0 ); +#else + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } +#endif + + + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_pk_parse_key returned -0x%x\n\n", + -ret ); + goto exit; + } + + mbedtls_printf(" ok\n"); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + + /* + * 2. Start the connection + */ + if (opt.server_addr == NULL) + opt.server_addr = opt.server_name; + + mbedtls_printf(" . Connecting to %s/%s/%s...", + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? "tcp" : "udp", + opt.server_addr, opt.server_port ); + fflush(stdout); + + if( ( ret = mbedtls_net_connect( &server_fd, + opt.server_addr, opt.server_port, + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? + MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", + -ret ); + goto exit; + } + + if (opt.nbio > 0) + ret = mbedtls_net_set_nonblock(&server_fd); + else + ret = mbedtls_net_set_block(&server_fd); + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", + -ret ); + goto exit; + } + + mbedtls_printf(" ok\n"); + + /* + * 3. Setup stuff + */ + mbedtls_printf(" . Setting up the SSL/TLS structure..."); + fflush(stdout); + + if ((ret = mbedtls_ssl_config_defaults(&conf, + MBEDTLS_SSL_IS_CLIENT, + opt.transport, + MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned -0x%x\n\n", + -ret ); + goto exit; + } + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + /* The default algorithms profile disables SHA-1, but our tests still + rely on it heavily. */ + if( opt.allow_sha1 > 0 ) + { + crt_profile_for_test.allowed_mds |= MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA1 ); + mbedtls_ssl_conf_cert_profile(&conf, &crt_profile_for_test); + mbedtls_ssl_conf_sig_hashes(&conf, ssl_sig_hashes_for_test); + } + + if (opt.debug_level > 0) + mbedtls_ssl_conf_verify(&conf, my_verify, NULL); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + + if (opt.auth_mode != DFL_AUTH_MODE) + mbedtls_ssl_conf_authmode(&conf, opt.auth_mode); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if (opt.hs_to_min != DFL_HS_TO_MIN || opt.hs_to_max != DFL_HS_TO_MAX) + mbedtls_ssl_conf_handshake_timeout( &conf, opt.hs_to_min, + opt.hs_to_max ); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + if( ( ret = mbedtls_ssl_conf_max_frag_len( &conf, opt.mfl_code ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_max_frag_len returned %d\n\n", + ret ); + goto exit; + } +#endif + +#if defined(MBEDTLS_SSL_TRUNCATED_HMAC) + if (opt.trunc_hmac != DFL_TRUNC_HMAC) + mbedtls_ssl_conf_truncated_hmac(&conf, opt.trunc_hmac); +#endif + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) + if (opt.extended_ms != DFL_EXTENDED_MS) + mbedtls_ssl_conf_extended_master_secret(&conf, opt.extended_ms); +#endif + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + if (opt.etm != DFL_ETM) + mbedtls_ssl_conf_encrypt_then_mac(&conf, opt.etm); +#endif + +#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) + if (opt.recsplit != DFL_RECSPLIT) + mbedtls_ssl_conf_cbc_record_splitting( &conf, opt.recsplit + ? MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED + : MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED ); +#endif + +#if defined(MBEDTLS_DHM_C) + if (opt.dhmlen != DFL_DHMLEN) + mbedtls_ssl_conf_dhm_min_bitlen(&conf, opt.dhmlen); +#endif + +#if defined(MBEDTLS_SSL_ALPN) + if (opt.alpn_string != NULL) + if( ( ret = mbedtls_ssl_conf_alpn_protocols( &conf, alpn_list ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_alpn_protocols returned %d\n\n", + ret ); + goto exit; + } +#endif + + mbedtls_ssl_conf_rng(&conf, mbedtls_ctr_drbg_random, &ctr_drbg); + mbedtls_ssl_conf_dbg(&conf, my_debug, stdout); + + mbedtls_ssl_conf_read_timeout(&conf, opt.read_timeout); + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) + mbedtls_ssl_conf_session_tickets(&conf, opt.tickets); +#endif + + if (opt.force_ciphersuite[0] != DFL_FORCE_CIPHER) + mbedtls_ssl_conf_ciphersuites(&conf, opt.force_ciphersuite); + +#if defined(MBEDTLS_ARC4_C) + if (opt.arc4 != DFL_ARC4) + mbedtls_ssl_conf_arc4_support(&conf, opt.arc4); +#endif + + if (opt.allow_legacy != DFL_ALLOW_LEGACY) + mbedtls_ssl_conf_legacy_renegotiation(&conf, opt.allow_legacy); +#if defined(MBEDTLS_SSL_RENEGOTIATION) + mbedtls_ssl_conf_renegotiation(&conf, opt.renegotiation); +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + if( strcmp( opt.ca_path, "none" ) != 0 && + strcmp( opt.ca_file, "none" ) != 0 ) + { + mbedtls_ssl_conf_ca_chain(&conf, &cacert, NULL); + } + if( ( + (strcmp( opt.crt_file, "none" ) != 0) + || (client_certificate_loaded == 1))&& + ((strcmp( opt.key_file, "none" ) != 0) || (useKeysFromSM )) ) + { + if( ( ret = mbedtls_ssl_conf_own_cert( &conf, &clicert, &pkey ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", + ret ); + goto exit; + } + } +#endif + +#if defined(MBEDTLS_ECP_C) + if( opt.curves != NULL && + strcmp( opt.curves, "default" ) != 0 ) + { + mbedtls_ssl_conf_curves(&conf, curve_list); + } +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) + if( ( ret = mbedtls_ssl_conf_psk( &conf, psk, psk_len, + (const unsigned char *)opt.psk_identity, + strlen( opt.psk_identity ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_psk returned %d\n\n", + ret ); + goto exit; + } +#endif + + if (opt.min_version != DFL_MIN_VERSION) + mbedtls_ssl_conf_min_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, + opt.min_version ); + + if (opt.max_version != DFL_MAX_VERSION) + mbedtls_ssl_conf_max_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, + opt.max_version ); + +#if defined(MBEDTLS_SSL_FALLBACK_SCSV) + if (opt.fallback != DFL_FALLBACK) + mbedtls_ssl_conf_fallback(&conf, opt.fallback); +#endif + + if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_setup returned -0x%x\n\n", + -ret ); + goto exit; + } + + if (pex_sss_demo_tls_ctx->obj.cipherType == kSSS_CipherType_EC_NIST_P || + pex_sss_demo_tls_ctx->obj.cipherType == kSSS_CipherType_EC_NIST_K || + pex_sss_demo_tls_ctx->obj.cipherType == kSSS_CipherType_EC_BRAINPOOL || + pex_sss_demo_tls_ctx->obj.cipherType == kSSS_CipherType_EC_MONTGOMERY || + pex_sss_demo_tls_ctx->obj.cipherType == kSSS_CipherType_EC_TWISTED_ED) + { + if (useKeysFromSM) { + /* doc+:use-private-key-for-ecdh */ + sss_mbedtls_associate_ecdhctx(ssl.handshake, &pex_sss_demo_tls_ctx->obj, &pCtx->host_ks); + /* doc-:use-private-key-for-ecdh */ + } + } + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + if( ( ret = mbedtls_ssl_set_hostname( &ssl, opt.server_name ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", + ret ); + goto exit; + } +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) + if( opt.ecjpake_pw != DFL_ECJPAKE_PW ) + { + if ((ret = mbedtls_ssl_set_hs_ecjpake_password(&ssl, + (const unsigned char *)opt.ecjpake_pw, + strlen( opt.ecjpake_pw ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hs_ecjpake_password returned %d\n\n", + ret ); + goto exit; + } + } +#endif + + if (opt.nbio == 2) + mbedtls_ssl_set_bio(&ssl, &server_fd, my_send, my_recv, NULL); + else + mbedtls_ssl_set_bio( &ssl, &server_fd, + mbedtls_net_send, mbedtls_net_recv, + opt.nbio == 0 ? mbedtls_net_recv_timeout : NULL); + +#if defined(MBEDTLS_TIMING_C) + mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, + mbedtls_timing_get_delay ); +#endif + + mbedtls_printf(" ok\n"); + + /* + * 4. Handshake + */ + mbedtls_printf(" . Performing the SSL/TLS handshake..."); + fflush(stdout); + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n", + -ret ); + if (ret == MBEDTLS_ERR_X509_CERT_VERIFY_FAILED) + mbedtls_printf( + " Unable to verify the server's certificate. " + "Either it is invalid,\n" + " or you didn't set ca_file or ca_path " + "to an appropriate value.\n" + " Alternatively, you may want to use " + "auth_mode=optional for testing purposes.\n"); + mbedtls_printf("\n"); + goto exit; + } + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + ret = idle( &server_fd, &timer, ret ); +#else + ret = idle( &server_fd, ret ); +#endif + if( ret != 0 ) + goto exit; + } + } + + mbedtls_printf(" ok\n [ Protocol is %s ]\n [ Ciphersuite is %s ]\n", + mbedtls_ssl_get_version( &ssl ), + mbedtls_ssl_get_ciphersuite( &ssl ) ); + + if ((ret = mbedtls_ssl_get_record_expansion(&ssl)) >= 0) + mbedtls_printf(" [ Record expansion is %d ]\n", ret); + else + mbedtls_printf(" [ Record expansion is unknown (compression) ]\n"); + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + mbedtls_printf(" [ Maximum fragment length is %u ]\n", + (unsigned int)mbedtls_ssl_get_max_frag_len(&ssl)); +#endif + +#if defined(MBEDTLS_SSL_ALPN) + if( opt.alpn_string != NULL ) + { + const char *alp = mbedtls_ssl_get_alpn_protocol(&ssl); + mbedtls_printf( " [ Application Layer Protocol is %s ]\n", + alp ? alp : "(none)" ); + } +#endif + + if( opt.reconnect != 0 ) + { + mbedtls_printf(" . Saving session for reuse..."); + fflush(stdout); + + if( ( ret = mbedtls_ssl_get_session( &ssl, &saved_session ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_get_session returned -0x%x\n\n", + -ret ); + goto exit; + } + + mbedtls_printf(" ok\n"); + } + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + /* + * 5. Verify the server certificate + */ + mbedtls_printf(" . Verifying peer X.509 certificate..."); + + if( ( flags = mbedtls_ssl_get_verify_result( &ssl ) ) != 0 ) + { + char vrfy_buf[512]; + + mbedtls_printf(" failed\n"); + + mbedtls_x509_crt_verify_info( vrfy_buf, sizeof( vrfy_buf ), + " ! ", flags ); + + mbedtls_printf("%s\n", vrfy_buf); + } + else + mbedtls_printf(" ok\n"); + + if( mbedtls_ssl_get_peer_cert( &ssl ) != NULL ) + { + mbedtls_printf(" . Peer certificate information ...\n"); + mbedtls_x509_crt_info( (char *) buf, sizeof( buf ) - 1, " ", + mbedtls_ssl_get_peer_cert(&ssl)); + mbedtls_printf("%s\n", buf); + } +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_RENEGOTIATION) + if( opt.renegotiate ) + { + /* + * Perform renegotiation (this must be done when the server is waiting + * for input from our side). + */ + mbedtls_printf(" . Performing renegotiation..."); + fflush(stdout); + while( ( ret = mbedtls_ssl_renegotiate( &ssl ) ) != 0 ) + { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_renegotiate returned %d\n\n", + ret ); + goto exit; + } + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + + } + mbedtls_printf(" ok\n"); + } +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + + /* + * 6. Write the GET request + */ + retry_left = opt.max_resend; +send_request: + mbedtls_printf(" > Write to server:"); + fflush(stdout); + + len = mbedtls_snprintf( (char *) buf, sizeof(buf) - 1, GET_REQUEST, + opt.request_page ); + tail_len = (int)strlen(GET_REQUEST_END); + + /* Add padding to GET request to reach opt.request_size in length */ + if (opt.request_size != DFL_REQUEST_SIZE && + len + tail_len < opt.request_size ) + { + memset(buf + len, 'A', opt.request_size - len - tail_len); + for (i = 0; i < opt.request_size - len - tail_len; i++) + { + *(buf + len + i) = 'A' + (i % 26); + } + len += opt.request_size - len - tail_len; + } + + strncpy((char *)buf + len, GET_REQUEST_END, sizeof(buf) - len - 1); + len += tail_len; + + /* Truncate if request size is smaller than the "natural" size */ + if( opt.request_size != DFL_REQUEST_SIZE && + len > opt.request_size ) + { + len = opt.request_size; + + /* Still end with \r\n unless that's really not possible */ + if( len >= 2 ) buf[len - 2] = '\r'; + if( len >= 1 ) buf[len - 1] = '\n'; + } + + if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) + { + written = 0; + frags = 0; + + do + { + while( ( ret = mbedtls_ssl_write( &ssl, buf + written, + len - written ) ) < 0 ) + { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned -0x%x\n\n", + -ret ); + goto exit; + } + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + } + + frags++; + written += ret; + } + while( written < len ); + } + else /* Not stream, so datagram */ + { + while( 1 ) + { + ret = mbedtls_ssl_write( &ssl, buf, len ); + + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + break; + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + } + + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", + ret ); + goto exit; + } + + frags = 1; + written = ret; + + if( written < len ) + { + mbedtls_printf( " warning\n ! request didn't fit into single datagram and " + "was truncated to size %u", (unsigned) written ); + } + } + + buf[written] = '\0'; + mbedtls_printf( " %d bytes written in %d fragments\n\n%s\n", + written, frags, (char *) buf ); + + /* Send a non-empty request if request_size == 0 */ + if ( len == 0 ) + { + opt.request_size = DFL_REQUEST_SIZE; + goto send_request; + } + + /* + * 7. Read the HTTP response + */ + mbedtls_printf(" < Read from server:"); + fflush(stdout); + + /* + * TLS and DTLS need different reading styles (stream vs datagram) + */ + if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) + { + do + { + len = sizeof(buf) - 1; + memset(buf, 0, sizeof(buf)); + ret = mbedtls_ssl_read(&ssl, buf, len); + + if (ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE) + { + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + continue; + } + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf(" connection was closed gracefully\n"); + ret = 0; + goto close_notify; + + case 0: + case MBEDTLS_ERR_NET_CONN_RESET: + mbedtls_printf(" connection was reset by peer\n"); + ret = 0; + goto reconnect; + + default: + mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n", + -ret ); + goto exit; + } + } + + len = ret; + buf[len] = '\0'; + mbedtls_printf(" %d bytes read\n\n%s", len, (char *)buf); + + /* End of message should be detected according to the syntax of the + * application protocol (eg HTTP), just use a dummy test here. */ + if( ret > 0 && buf[len-1] == '\n' ) + { + ret = 0; + break; + } + } + while( 1 ); + } + else /* Not stream, so datagram */ + { + len = sizeof(buf) - 1; + memset(buf, 0, sizeof(buf)); + + while( 1 ) + { + ret = mbedtls_ssl_read( &ssl, buf, len ); + + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + break; + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + } + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_TIMEOUT: + mbedtls_printf(" timeout\n"); + if (retry_left-- > 0) + goto send_request; + goto exit; + + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf(" connection was closed gracefully\n"); + ret = 0; + goto close_notify; + + default: + mbedtls_printf(" mbedtls_ssl_read returned -0x%x\n", -ret); + goto exit; + } + } + + len = ret; + buf[len] = '\0'; + mbedtls_printf(" %d bytes read\n\n%s", len, (char *)buf); + ret = 0; + } + + /* + * 7b. Simulate hard reset and reconnect from same port? + */ + if( opt.reconnect_hard != 0 ) + { + opt.reconnect_hard = 0; + + mbedtls_printf(" . Restarting connection from same port..."); + fflush(stdout); + + if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", + -ret ); + goto exit; + } + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", + -ret ); + goto exit; + } + + /* For event-driven IO, wait for socket to become available */ + if( opt.event == 1 /* level triggered IO */ ) + { +#if defined(MBEDTLS_TIMING_C) + idle( &server_fd, &timer, ret ); +#else + idle( &server_fd, ret ); +#endif + } + } + + mbedtls_printf(" ok\n"); + + goto send_request; + } + + /* + * 7c. Continue doing data exchanges? + */ + if (--opt.exchanges > 0) + goto send_request; + + /* + * 8. Done, cleanly close the connection + */ +close_notify: + mbedtls_printf(" . Closing the connection..."); + fflush(stdout); + + /* No error checking, the connection might be closed already */ + do ret = mbedtls_ssl_close_notify( &ssl ); + while (ret == MBEDTLS_ERR_SSL_WANT_WRITE); + ret = 0; + + mbedtls_printf(" done\n"); + + /* + * 9. Reconnect? + */ +reconnect: + if( opt.reconnect != 0 ) + { + --opt.reconnect; + + mbedtls_net_free(&server_fd); + +#if defined(MBEDTLS_TIMING_C) + if (opt.reco_delay > 0) + mbedtls_net_usleep(1000000 * opt.reco_delay); +#endif + + mbedtls_printf(" . Reconnecting with saved session..."); + + if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", + -ret ); + goto exit; + } + + if( ( ret = mbedtls_ssl_set_session( &ssl, &saved_session ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_session returned %d\n\n", + ret ); + goto exit; + } + + if( ( ret = mbedtls_net_connect( &server_fd, + opt.server_addr, opt.server_port, + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? + MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", + -ret ); + goto exit; + } + + if (opt.nbio > 0) + ret = mbedtls_net_set_nonblock(&server_fd); + else + ret = mbedtls_net_set_block(&server_fd); + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", + -ret ); + goto exit; + } + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if (ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", + -ret ); + goto exit; + } + } + + mbedtls_printf(" ok\n"); + + goto send_request; + } + + /* + * Cleanup and exit + */ +exit: + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) /* Set public key is causing NVM writes */ +#if defined(SMCOM_JRCP_V2) && SSS_HAVE_SE05X_VER_GTE_06_00 + { + uint32_t status = kStatus_SSS_Fail; + sss_se05x_session_t *pSe05xSession = (sss_se05x_session_t *)&pCtx->session; + status = smComJRCP_NvmCount(pSe05xSession->s_ctx.conn_ctx, &end_nvmCount); + if (status == SMCOM_OK) { + mbedtls_printf("NVM count at end : %u \n", end_nvmCount); + } + + /* Ignore one nvm write for rsa sign for the first time */ + if (end_nvmCount > start_nvmCount + 1){ + mbedtls_printf("NVM write not expected\n"); + } + } +#endif +#endif + +#ifdef MBEDTLS_ERROR_C + if( ret != 0 ) + { + char error_buf[100]; + mbedtls_strerror(ret, error_buf, 100); + mbedtls_printf("Last error was: -0x%X - %s\n\n", -ret, error_buf); + } +#endif + + mbedtls_net_free(&server_fd); + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + mbedtls_x509_crt_free(&clicert); + mbedtls_x509_crt_free(&cacert); + mbedtls_pk_free(&pkey); +#endif + mbedtls_ssl_session_free(&saved_session); + mbedtls_ssl_free(&ssl); + mbedtls_ssl_config_free(&conf); + mbedtls_ctr_drbg_free(&ctr_drbg); + mbedtls_entropy_free(&entropy); + +//#if defined(_WIN32) +// mbedtls_printf(" + Press Enter to exit this program.\n"); +// fflush( stdout ); getchar(); +//#endif + + // Shell can not handle large exit numbers -> 1 for errors + if (ret < 0) + ret = kStatus_SSS_Fail; + + return kStatus_SSS_Success; +} +#endif /* MBEDTLS_BIGNUM_C && MBEDTLS_ENTROPY_C && MBEDTLS_SSL_TLS_C && +MBEDTLS_SSL_CLI_C && MBEDTLS_NET_C && MBEDTLS_RSA_C && +MBEDTLS_CTR_DRBG_C MBEDTLS_TIMING_C */ + +/* clang-format on */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c new file mode 100644 index 00000000000..8a36a800f31 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c @@ -0,0 +1,280 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_boot.c: *The purpose and scope of this file* + * + * Project: SecureIoTMW-Debug@appboot-top-eclipse_x86 + * + * $Date: Mar 10, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include "ex_sss_boot.h" + +#include +#include + +#include "ex_sss_boot_int.h" +#include "nxLog_App.h" +#include "stdio.h" +#if defined(SECURE_WORLD) +#include "fsl_sss_lpc55s_apis.h" +#endif +#if SSS_HAVE_APPLET_SE05X_IOT +#include "se05x_APDU.h" +#endif + +/* ***************************************************************************************************************** + * Internal Definitions + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Type Definitions + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Global and Static Variables + * Total Size: NNNbytes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Private Functions Prototypes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Public Functions + * ***************************************************************************************************************** */ + +sss_status_t ex_sss_boot_open(ex_sss_boot_ctx_t *pCtx, const char *portName) +{ + sss_status_t status = kStatus_SSS_Fail; + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM + status = ex_sss_boot_a71ch_open(pCtx, portName); +#elif SSS_HAVE_A71CL || SSS_HAVE_SE050_L + status = ex_sss_boot_a71cl_open(pCtx, portName); +#elif SSS_HAVE_APPLET_SE05X_IOT + status = ex_sss_boot_se05x_open(pCtx, portName); +#elif SSS_HAVE_SE + status = ex_sss_boot_se_open(pCtx, portName); +#elif SSS_HAVE_MBEDTLS + status = ex_sss_boot_mbedtls_open(pCtx, portName); +#elif SSS_HAVE_OPENSSL + status = ex_sss_boot_openssl_open(pCtx, portName); +#endif + return status; +} + +sss_status_t ex_sss_boot_open_on_id(ex_sss_boot_ctx_t *pCtx, const char *portName, const int32_t authId) +{ + sss_status_t status = kStatus_SSS_Fail; + +#if SSS_HAVE_APPLET_SE05X_IOT + status = ex_sss_boot_se05x_open_on_Id(pCtx, portName, authId); +#endif + return status; +} + +sss_status_t ex_sss_boot_factory_reset(ex_sss_boot_ctx_t *pCtx) +{ + sss_status_t status = kStatus_SSS_Fail; + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM + uint16_t ret; + ret = HLSE_DbgReset(); + if (ret == HLSE_SW_OK) + status = kStatus_SSS_Success; + +#elif SSS_HAVE_A71CL || SSS_HAVE_SE050_L + status = kStatus_SSS_Success; + +#elif SSS_HAVE_APPLET_SE05X_IOT + smStatus_t st; + sss_se05x_session_t *pSession = (sss_se05x_session_t *)&pCtx->session; + st = Se05x_API_DeleteAll_Iterative(&pSession->s_ctx); + if (st == SW_OK) + status = kStatus_SSS_Success; + +#elif SSS_HAVE_MBEDTLS + status = kStatus_SSS_Success; +#elif SSS_HAVE_OPENSSL + status = kStatus_SSS_Success; +#else + LOG_E("Select atleast one security subsystem"); +#endif + return status; +} + +sss_status_t ex_sss_key_store_and_object_init(ex_sss_boot_ctx_t *pCtx) +{ + sss_status_t status; + status = sss_key_store_context_init(&pCtx->ks, &pCtx->session); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_key_store_context_init Failed..."); + goto cleanup; + } + + status = sss_key_store_allocate(&pCtx->ks, __LINE__); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_key_store_allocate Failed..."); + goto cleanup; + } + +cleanup: + return status; +} + +#if ((SSS_HAVE_HOSTCRYPTO_ANY) && \ + ((SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03))) +static void free_auth_objects(SE_Connect_Ctx_t *pConnectCtx) +{ + if (pConnectCtx->auth.authType == kSSS_AuthType_ID) { + sss_host_key_object_free(pConnectCtx->auth.ctx.idobj.pObj); + } + + if (pConnectCtx->auth.authType == kSSS_AuthType_SCP03 || pConnectCtx->auth.authType == kSSS_AuthType_AESKey) { + NXSCP03_AuthCtx_t *pSC = &pConnectCtx->auth.ctx.scp03; + sss_host_key_object_free(&pSC->pStatic_ctx->Enc); + sss_host_key_object_free(&pSC->pStatic_ctx->Mac); + sss_host_key_object_free(&pSC->pStatic_ctx->Dek); + sss_host_key_object_free(&pSC->pDyn_ctx->Enc); + sss_host_key_object_free(&pSC->pDyn_ctx->Mac); + sss_host_key_object_free(&pSC->pDyn_ctx->Rmac); + } + + if (pConnectCtx->auth.authType == kSSS_AuthType_ECKey) { + SE05x_AuthCtx_ECKey_t *pEC = &pConnectCtx->auth.ctx.eckey; + sss_host_key_object_free(&pEC->pStatic_ctx->HostEcdsaObj); + sss_host_key_object_free(&pEC->pStatic_ctx->HostEcKeypair); + sss_host_key_object_free(&pEC->pStatic_ctx->masterSec); + sss_host_key_object_free(&pEC->pStatic_ctx->SeEcPubKey); + sss_host_key_object_free(&pEC->pDyn_ctx->Enc); + sss_host_key_object_free(&pEC->pDyn_ctx->Mac); + sss_host_key_object_free(&pEC->pDyn_ctx->Rmac); + } +} +#endif /* SSS_HAVE_HOSTCRYPTO_ANY */ + +void ex_sss_session_close(ex_sss_boot_ctx_t *pCtx) +{ +#if SSS_HAVE_APPLET_SE05X_IOT || SSS_HAVE_SSCP + if (pCtx->session.subsystem != kType_SSS_SubSystem_NONE) { + sss_session_close(&pCtx->session); + sss_session_delete(&pCtx->session); + } + +#if SSS_HAVE_APPLET_SE05X_IOT +#if ((SSS_HAVE_HOSTCRYPTO_ANY) && \ + ((SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03))) + SE_Connect_Ctx_t *pConnectCtx = &pCtx->se05x_open_ctx; + free_auth_objects(pConnectCtx); +#endif /* SSS_HAVE_HOSTCRYPTO_ANY */ + + if (pCtx->pTunnel_ctx && pCtx->pTunnel_ctx->session) { + if (pCtx->pTunnel_ctx->session->subsystem != kType_SSS_SubSystem_NONE) { + sss_session_close(pCtx->pTunnel_ctx->session); + sss_tunnel_context_free(pCtx->pTunnel_ctx); + } + } + +#if ((SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY)) + { + ex_SE05x_authCtx_t *pauth = &pCtx->ex_se05x_auth; + sss_host_key_object_free(&pauth->scp03.ex_static.Enc); + sss_host_key_object_free(&pauth->scp03.ex_static.Mac); + sss_host_key_object_free(&pauth->scp03.ex_static.Dek); + sss_host_key_object_free(&pauth->scp03.ex_dyn.Enc); + sss_host_key_object_free(&pauth->scp03.ex_dyn.Mac); + sss_host_key_object_free(&pauth->scp03.ex_dyn.Rmac); + } +#elif (SSS_HAVE_SE05X_AUTH_USERID) + sss_host_key_object_free(pCtx->se05x_open_ctx.auth.ctx.idobj.pObj); +#elif (SSS_HAVE_SE05X_AUTH_ECKEY) + { + ex_SE05x_authCtx_t *pauth = &pCtx->ex_se05x_auth; + sss_host_key_object_free(&pauth->eckey.ex_static.HostEcdsaObj); + sss_host_key_object_free(&pauth->eckey.ex_static.HostEcKeypair); + sss_host_key_object_free(&pauth->eckey.ex_static.masterSec); + sss_host_key_object_free(&pauth->eckey.ex_static.SeEcPubKey); + sss_host_key_object_free(&pauth->eckey.ex_dyn.Enc); + sss_host_key_object_free(&pauth->eckey.ex_dyn.Mac); + sss_host_key_object_free(&pauth->eckey.ex_dyn.Rmac); + } +#endif /* PF SCP */ + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ + +#if SSS_HAVE_HOSTCRYPTO_ANY + if (pCtx->host_ks.session != NULL) { + sss_host_key_store_context_free(&pCtx->host_ks); + } + if (pCtx->host_session.subsystem != kType_SSS_SubSystem_NONE) { + sss_host_session_close(&pCtx->host_session); + } +#endif // SSS_HAVE_HOSTCRYPTO_ANY +#endif + + if (pCtx->ks.session != NULL) { + sss_key_store_context_free(&pCtx->ks); + } +} + +#if SSS_HAVE_HOSTCRYPTO_ANY +sss_status_t ex_sss_boot_open_host_session(ex_sss_boot_ctx_t *pCtx) +{ + sss_status_t status = kStatus_SSS_Fail; + +#if SSS_HAVE_APPLET_SE05X_IOT || SSS_HAVE_SSCP + if (pCtx->host_ks.session == NULL) { + status = sss_session_open(&pCtx->host_session, kType_SSS_Software, 0, kSSS_ConnectionType_Plain, NULL); + if (kStatus_SSS_Success != status) { + LOG_E("Failed to open mbedtls Session"); + return status; + } + + status = sss_key_store_context_init(&pCtx->host_ks, &pCtx->host_session); + if (kStatus_SSS_Success != status) { + LOG_E("sss_key_store_context_init failed"); + return status; + } + status = sss_key_store_allocate(&pCtx->host_ks, __LINE__); + if (kStatus_SSS_Success != status) { + LOG_E("sss_key_store_allocate failed"); + return status; + } + } +#endif + return status; +} +#endif // SSS_HAVE_HOSTCRYPTO_ANY + +/* ***************************************************************************************************************** + * Private Functions + * ***************************************************************************************************************** */ + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c new file mode 100644 index 00000000000..777799e724b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c @@ -0,0 +1,178 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_boot_connectstring.c: *The purpose and scope of this file* + * + * Project: SecureIoTMW-Debug@appboot-top-eclipse_x86 + * + * $Date: Mar 10, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ +#include +#include +#include +#include +#include + +#if defined(_MSC_VER) +#include +#endif + +/* ***************************************************************************************************************** + * Internal Definitions + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Type Definitions + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Global and Static Variables + * Total Size: NNNbytes + * ***************************************************************************************************************** */ + +const char gszCOMPortDefault[] = EX_SSS_BOOT_SSS_COMPORT_DEFAULT; +const char gszSocketPortDefault[] = EX_SSS_BOOT_SSS_SOCKETPORT_DEFAULT; +const char gszReaderDefault[] = EX_SSS_BOOT_SSS_PCSC_READER_DEFAULT; + +/* ***************************************************************************************************************** + * Private Functions Prototypes + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Public Functions + * ***************************************************************************************************************** */ + +sss_status_t ex_sss_boot_connectstring(int argc, const char *argv[], const char **pPortName) +{ + const char *portName = NULL; + sss_status_t status = kStatus_SSS_Success; +#if defined(_WIN32) && defined(WIN32) && defined(DEBUG) + _CrtSetDbgFlag(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF); + _CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_DEBUG); +#endif + +#if !AX_EMBEDDED + bool last_is_help = FALSE; + if (argv != NULL) { + LOG_I("Running %s", argv[0]); + } + if (argc > 1 /* Alteast 1 cli argument */ + && argv != NULL /* argv not null */ + && argv[argc - 1] != NULL /* Last parameter exists */ + ) { + if (0 == strncmp("--help", argv[argc - 1], sizeof("--help"))) { + last_is_help = TRUE; + } + } + if (TRUE == last_is_help) { + *pPortName = argv[argc - 1]; /* --help */ + return kStatus_SSS_Success; + } + if (argc > 1 /* Alteast 1 cli argument */ + && argv != NULL /* argv not null */ + && argv[argc - 1] != NULL /* Last parameter exists */ + && argv[argc - 1][0] != '-' /* Not something like -h / --help */ + ) { + portName = argv[argc - 1]; /* last entry, deemed as port name */ + LOG_I("Using PortName='%s' (CLI)", portName); + } + else +#endif + { + const char *portName_env = getenv(EX_SSS_BOOT_SSS_PORT); + if (portName_env != NULL) { + portName = portName_env; + LOG_I("Using PortName='%s' (ENV: %s=%s)", portName, EX_SSS_BOOT_SSS_PORT, portName); + } + } + + if (portName == NULL) { +#if RJCT_VCOM + portName = gszCOMPortDefault; + LOG_I("Using PortName='%s' (gszCOMPortDefault)", portName); +#elif SMCOM_JRCP_V1 || SMCOM_JRCP_V2 + portName = gszSocketPortDefault; + LOG_I("Using PortName='%s' (gszSocketPortDefault)", portName); +#elif SMCOM_PCSC + portName = gszReaderDefault; +#else + status = kStatus_SSS_Success; +#endif + +#if AX_EMBEDDED + /* FINE. To be moved to boot direct */ +#else + LOG_I( + "If you want to over-ride the selection, use ENV=%s or pass in " + "command line arguments.", + EX_SSS_BOOT_SSS_PORT); +#endif + } + + if (status == kStatus_SSS_Success && pPortName != NULL) { + *pPortName = portName; + } + return status; +} + +bool ex_sss_boot_isSerialPortName(const char *portName) +{ + bool is_vcom = FALSE; +#if RJCT_VCOM + if (portName == NULL) { + is_vcom = FALSE; + } + else if (0 == strncmp("COM", portName, sizeof("COM") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("\\\\.\\COM", portName, sizeof("\\\\.\\COM") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("/tty/", portName, sizeof("/tty/") - 1)) { + is_vcom = TRUE; + } + else if (0 == strncmp("/dev/tty", portName, sizeof("/dev/tty") - 1)) { + is_vcom = TRUE; + } +#endif + return is_vcom; +} + +bool ex_sss_boot_isSocketPortName(const char *portName) +{ + bool is_socket = FALSE; +#if SMCOM_JRCP_V1 || SMCOM_JRCP_V2 + if (portName == NULL) { + is_socket = FALSE; + } + else if (NULL != strchr(portName, ':')) { + is_socket = TRUE; + } +#endif + return is_socket; +} + +bool ex_sss_boot_isHelp(const char *argname) +{ + bool last_is_help = FALSE; + + if (NULL != argname && (0 == strncmp("--help", argname, sizeof("--help")))) { + last_is_help = TRUE; + } + return last_is_help; +} + +/* ***************************************************************************************************************** + * Private Functions + * ***************************************************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h new file mode 100644 index 00000000000..f060e1244c6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h @@ -0,0 +1,70 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * + * ex_sss_boot_int.h: *The purpose and scope of this file* + * + * Project: SecureIoTMW-Debug@appboot-top-eclipse_x86 + * + * $Date: Mar 10, 2019 $ + * $Author: ing05193 $ + * $Revision$ + */ + +#ifndef SSS_EX_SRC_EX_SSS_BOOT_INT_H_ +#define SSS_EX_SRC_EX_SSS_BOOT_INT_H_ + +/* ***************************************************************************************************************** + * Includes + * ***************************************************************************************************************** */ +#include + +#include "fsl_sss_se05x_apis.h" + +/* ***************************************************************************************************************** + * MACROS/Defines + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Types/Structure Declarations + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Extern Variables + * ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** + * Function Prototypes + * ***************************************************************************************************************** */ +#if SSS_HAVE_SE +sss_status_t ex_sss_boot_se_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +#endif + +/** Entry Point for SE050 based build */ + +#if SSS_HAVE_APPLET_SE05X_IOT +sss_status_t ex_sss_boot_se05x_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +sss_status_t ex_sss_boot_se05x_open_on_Id(ex_sss_boot_ctx_t *pCtx, const char *portName, const int32_t authID); +#endif + +#if SSS_HAVE_MBEDTLS +sss_status_t ex_sss_boot_mbedtls_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +#endif + +#if SSS_HAVE_OPENSSL +sss_status_t ex_sss_boot_openssl_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +#endif + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM +sss_status_t ex_sss_boot_a71ch_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +#endif + +#if SSS_HAVE_A71CL || SSS_HAVE_SE050_L +sss_status_t ex_sss_boot_a71cl_open(ex_sss_boot_ctx_t *pCtx, const char *portName); +#endif + +#endif /* SSS_EX_SRC_EX_SSS_BOOT_INT_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c new file mode 100644 index 00000000000..7651608faae --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c @@ -0,0 +1,233 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file +* +* ex_sss_scp03_auth.c: *The purpose and scope of this file* +* +* Project: sss-doc-upstream +* +* $Date: Dec 12, 2019 $ +* $Author: nxf42670 $ +* $Revision$ +*/ + +/* ***************************************************************************************************************** +* Includes +* ***************************************************************************************************************** */ +#include +#include +#include +#include + +#include "ex_sss_auth.h" +#include "ex_sss_boot_int.h" +#include "ex_sss_scp03_keys.h" +#include "nxLog_App.h" +#include "nxScp03_Types.h" + +/* ***************************************************************************************************************** +* Internal Definitions +* ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** +* Type Definitions +* ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** +* Global and Static Variables +* Total Size: NNNbytes +* ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** +* Private Functions Prototypes +* ***************************************************************************************************************** */ + +#ifdef EX_SSS_SCP03_FILE_PATH + +static sss_status_t Scp03_KeyString_to_Keybuffer(bool hasAuthKey, char *inputKey, uint8_t *auth_key, size_t key_size); + +static sss_status_t read_platfscp03_keys_from_file(const char *scp03_file_path, + uint8_t *enc, + size_t enc_len, + uint8_t *mac, + size_t mac_len, + uint8_t *dek, + size_t dek_len); + +#define UNSECURE_LOGGING_OF_SCP_KEYS 0 + +/* ***************************************************************************************************************** +* Public Functions +* ***************************************************************************************************************** */ + +sss_status_t scp03_keys_from_path( + uint8_t *penc, size_t enc_len, uint8_t *pmac, size_t mac_len, uint8_t *pdek, size_t dek_len) +{ + sss_status_t status = kStatus_SSS_Fail; + const char *filename = EX_SSS_SCP03_FILE_PATH; + FILE *fp = NULL; + LOG_D("Using File: %s", filename); + fp = fopen(filename, "rb"); + if (fp != NULL) { + // File exists. Get keys from file + LOG_W("Using SCP03 keys from:'%s' (FILE=%s)", filename, EX_SSS_SCP03_FILE_PATH); + fclose(fp); + status = read_platfscp03_keys_from_file(filename, penc, enc_len, pmac, mac_len, pdek, dek_len); + } + else { + // File does not exist. Check env variable + const char *scp03_path_env = getenv(EX_SSS_BOOT_SCP03_PATH_ENV); + if (scp03_path_env != NULL) { + LOG_W("Using SCP03 keys from:'%s' (ENV=%s)", scp03_path_env, EX_SSS_BOOT_SCP03_PATH_ENV); + status = read_platfscp03_keys_from_file(scp03_path_env, penc, enc_len, pmac, mac_len, pdek, dek_len); + } + else { + LOG_I( + "Using default PlatfSCP03 keys. " + "You can use keys from file using ENV=%s", + EX_SSS_BOOT_SCP03_PATH_ENV); + } + } + + if (status != kStatus_SSS_Success) { + LOG_D("Using default keys"); + } + + return status; +} + +static sss_status_t read_platfscp03_keys_from_file(const char *scp03_file_path, + uint8_t *enc, + size_t enc_len, + uint8_t *mac, + size_t mac_len, + uint8_t *dek, + size_t dek_len) +{ + sss_status_t status = kStatus_SSS_Fail; + + FILE *scp_file = fopen(scp03_file_path, "r"); + if (scp_file == NULL) { + LOG_E("Cannot open SCP file"); + status = kStatus_SSS_Fail; + return status; + } + char file_data[1024]; + char *pdata = &file_data[0]; + bool hasEnc = false; + bool hasMac = false; + bool hasDek = false; + + while (fgets(pdata, sizeof(file_data), scp_file)) { + size_t i = 0, j = 0; + + /*Don't need leading spaces*/ + for (i = 0; i < strlen(pdata); i++) { + int charac = (int)pdata[i]; + if (!isspace(charac)) { + break; + } + } + + /*Lines beginning with '#' are comments*/ + if (pdata[i] == '#') { + continue; + } + + /*Remove trailing comments*/ + for (j = 0; j < strlen(pdata); j++) { + if (pdata[j] == '#') { + pdata[j] = '\0'; + break; + } + } + + if (strncmp(&pdata[i], "ENC ", strlen("ENC ")) == 0) { +#if UNSECURE_LOGGING_OF_SCP_KEYS + LOG_I("%s", &pdata[i]); +#endif + status = Scp03_KeyString_to_Keybuffer(hasEnc, &pdata[i], enc, enc_len); + if (status != kStatus_SSS_Success) { + fclose(scp_file); + return status; + } + hasEnc = true; + } + + else if (!strncmp(&pdata[i], "MAC ", strlen("MAC "))) { +#if UNSECURE_LOGGING_OF_SCP_KEYS + LOG_I("%s", &pdata[i]); +#endif + status = Scp03_KeyString_to_Keybuffer(hasMac, &pdata[i], mac, mac_len); + if (status != kStatus_SSS_Success) { + fclose(scp_file); + return status; + } + hasMac = true; + } + + else if (!strncmp(&pdata[i], "DEK ", strlen("DEK "))) { +#if UNSECURE_LOGGING_OF_SCP_KEYS + LOG_I("%s", &pdata[i]); +#endif + status = Scp03_KeyString_to_Keybuffer(hasDek, &pdata[i], dek, dek_len); + if (status != kStatus_SSS_Success) { + fclose(scp_file); + return status; + } + hasDek = true; + } + + else { + LOG_E("Unknown key type %s", &pdata[i]); + status = kStatus_SSS_Fail; + fclose(scp_file); + return status; + } + } + + fclose(scp_file); + + return kStatus_SSS_Success; +} + +static sss_status_t Scp03_KeyString_to_Keybuffer(bool hasAuthKey, char *inputKey, uint8_t *auth_key, size_t key_size) +{ + sss_status_t status = kStatus_SSS_Success; + size_t j = 0; + int charac = (int)inputKey[j]; + if (hasAuthKey) { + LOG_E("Duplicate Auth key value"); + status = kStatus_SSS_Fail; + return status; + } + while (!isspace(charac)) { + j++; + charac = (int)inputKey[j]; + } + while (isspace(charac)) { + j++; + charac = (int)inputKey[j]; + } + if (inputKey[j] == '\0') { + LOG_E("Invalid Key"); + status = kStatus_SSS_Fail; + return status; + } + for (size_t count = 0; count < key_size; count++) { + if (sscanf(&inputKey[j], "%2hhx", &auth_key[count]) != 1) { + LOG_E("Cannot copy data"); + status = kStatus_SSS_Fail; + return status; + } + j = j + 2; + } + + return status; +} + +#endif //EX_SSS_SCP03_FILE_PATH diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c new file mode 100644 index 00000000000..e7968d4697d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c @@ -0,0 +1,427 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#include +#include +#include +#include +#include + +#include "ex_sss_boot_int.h" +#if AX_EMBEDDED +#include +#endif + +#include "ex_sss_auth.h" + +/* ************************************************************************** */ +/* Local Defines */ +/* ************************************************************************** */ +/* clang-format off */ +#if SSS_HAVE_APPLET_SE05X_IOT +const uint8_t se050Authkey[] = EX_SSS_AUTH_SE05X_UserID_VALUE; +#endif +/* clang-format on */ +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ +#if SSS_HAVE_APPLET_SE05X_IOT + +#if (SSS_HAVE_SE05X_AUTH_USERID) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_ID +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_ObjID_UserID_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Password +#endif + +#if (SSS_HAVE_SE05X_AUTH_PLATFSCP03) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_SCP03 +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_SCP03 +#define SSS_EX_SE05x_TUNN_AUTH_MECH kSSS_AuthType_ID +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_ObjID_UserID_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_SCP03 +#define SSS_EX_SE05x_TUNN_AUTH_MECH kSSS_AuthType_AESKey +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_ObjID_APPLETSCP03_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_SCP03 +#define SSS_EX_SE05x_TUNN_AUTH_MECH kSSS_AuthType_ECKey +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_objID_ECKEY_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_AESKEY) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_AESKey +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_ObjID_APPLETSCP03_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_ECKEY) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_ECKey +#define SSS_EX_SE05x_AUTH_ID kEX_SSS_objID_ECKEY_Auth +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Encrypted +#endif + +#if (SSS_HAVE_SE05X_AUTH_NONE) +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_None +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Plain +#endif + +#ifndef SSS_EX_SE05x_AUTH_MECH +#define SSS_EX_SE05x_AUTH_MECH kSSS_AuthType_None +#endif + +#ifndef SSS_EX_CONNECTION_TYPE +#define SSS_EX_CONNECTION_TYPE kSSS_ConnectionType_Plain +#endif + +#ifndef SSS_EX_SE05x_TUNN_AUTH_MECH +#define SSS_EX_SE05x_TUNN_AUTH_MECH kSSS_AuthType_None +#else +/* Only define if using Tunnel*/ +sss_tunnel_t gTunnel_ctx; +ex_sss_platf_ctx_t gPlatfCtx; +#endif + +/* ************************************************************************** */ +/* Static function declarations */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Public Functions */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Private Functions */ +/* ************************************************************************** */ + +sss_status_t ex_sss_boot_se05x_open(ex_sss_boot_ctx_t *pCtx, const char *portName) +{ + sss_status_t status = kStatus_SSS_Fail; + SE_Connect_Ctx_t *pConnectCtx = NULL; + sss_session_t *pPfSession = NULL; +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + sss_connection_type_t connectType = kSSS_ConnectionType_Plain; +#endif + +#if defined SSS_EX_SE05x_AUTH_ID + const uint32_t auth_id = SSS_EX_SE05x_AUTH_ID; +#endif + +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + ex_sss_platf_ctx_t *pPlatfCtx = &gPlatfCtx; + + pCtx->pTunnel_ctx = &gTunnel_ctx; + pPlatfCtx->phost_session = &pCtx->host_session; + pPlatfCtx->phost_ks = &pCtx->host_ks; + pPfSession = &pPlatfCtx->platf_session; + pConnectCtx = &pPlatfCtx->platf_open_ctx; + pConnectCtx->auth.ctx.scp03.pStatic_ctx = &pPlatfCtx->ex_se05x_auth.scp03.ex_static; + pConnectCtx->auth.ctx.scp03.pDyn_ctx = &pPlatfCtx->ex_se05x_auth.scp03.ex_dyn; + +#else + pPfSession = &pCtx->session; + pConnectCtx = &pCtx->se05x_open_ctx; +#endif + +#if defined(SMCOM_JRCP_V1) + if (ex_sss_boot_isSocketPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_JRCP_V1; + pConnectCtx->portName = portName; + } +#endif + +#if defined(SMCOM_JRCP_V2) + if (ex_sss_boot_isSocketPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_JRCP_V2; + pConnectCtx->portName = portName; + } +#endif + +#if defined(RJCT_VCOM) + if (ex_sss_boot_isSerialPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_VCOM; + pConnectCtx->portName = portName; + } +#endif + +#if defined(SCI2C) +#error "Not a valid combination" +#endif + +#if defined(T1oI2C) + pConnectCtx->connType = kType_SE_Conn_Type_T1oI2C; + pConnectCtx->portName = portName; +#endif + +#if defined(SMCOM_PCSC) + pConnectCtx->connType = kType_SE_Conn_Type_PCSC; + pConnectCtx->portName = portName; +#endif + +#if defined(SMCOM_PN7150) + pConnectCtx->connType = kType_SE_Conn_Type_NFC; + pConnectCtx->portName = NULL; +#endif + +#if defined(SMCOM_RC663_VCOM) + if (portName == NULL) { + static const char *sszCOMPort = EX_SSS_BOOT_SSS_COMPORT_DEFAULT; + portName = sszCOMPort; + } + pConnectCtx->connType = kType_SE_Conn_Type_NFC; + pConnectCtx->portName = portName; +#endif + +#if SSS_HAVE_HOSTCRYPTO_ANY + status = ex_sss_se05x_prepare_host( + &pCtx->host_session, &pCtx->host_ks, pConnectCtx, &pCtx->ex_se05x_auth, SSS_EX_SE05x_AUTH_MECH); + + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_se05x_prepare_host failed"); + goto cleanup; + } +#endif // SSS_HAVE_HOSTCRYPTO_ANY + + if (SSS_EX_SE05x_AUTH_MECH == kSSS_AuthType_SCP03 || SSS_EX_SE05x_AUTH_MECH == kSSS_AuthType_None) { + status = sss_session_open(pPfSession, kType_SSS_SE_SE05x, 0, SSS_EX_CONNECTION_TYPE, pConnectCtx); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + goto cleanup; + } + } +#ifdef SSS_EX_SE05x_AUTH_ID + else { + status = sss_session_open(pPfSession, kType_SSS_SE_SE05x, auth_id, SSS_EX_CONNECTION_TYPE, pConnectCtx); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + } + } +#else + else { + LOG_E("Invalid combination for boot selection"); + status = kStatus_SSS_Fail; + } +#endif /* SSS_EX_SE05x_AUTH_ID */ + +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + SE05x_Connect_Ctx_t *pchannlCtxt = &pCtx->se05x_open_ctx; + pchannlCtxt->auth.authType = SSS_EX_SE05x_TUNN_AUTH_MECH; + + status = ex_sss_se05x_prepare_host( + &pCtx->host_session, &pCtx->host_ks, pchannlCtxt, &pPlatfCtx->ex_se05x_auth, SSS_EX_SE05x_TUNN_AUTH_MECH); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_se05x_prepare_host failed"); + goto cleanup; + } + + status = sss_tunnel_context_init(pCtx->pTunnel_ctx, pPfSession /* session */); + if (kStatus_SSS_Success != status) { + LOG_E("sss_tunnel_context_init failed"); + goto cleanup; + } + + pchannlCtxt->connType = kType_SE_Conn_Type_Channel; + pchannlCtxt->tunnelCtx = pCtx->pTunnel_ctx; + if (pchannlCtxt->auth.authType == kSSS_AuthType_ID) { + connectType = kSSS_ConnectionType_Password; + } + else { + connectType = kSSS_ConnectionType_Encrypted; + } + status = sss_session_open(&pCtx->session, kType_SSS_SE_SE05x, auth_id, connectType, pchannlCtxt); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + goto cleanup; + } + + ((sss_se05x_session_t *)&pCtx->session)->s_ctx.conn_ctx = ((sss_se05x_session_t *)pPfSession)->s_ctx.conn_ctx; + +#endif + +cleanup: + return status; +} + +sss_status_t ex_sss_boot_se05x_open_on_Id(ex_sss_boot_ctx_t *pCtx, const char *portName, const int32_t authID) +{ + sss_status_t status = kStatus_SSS_Fail; + SE_Connect_Ctx_t *pConnectCtx = NULL; + sss_session_t *pPfSession = NULL; +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + sss_connection_type_t connectType = kSSS_ConnectionType_Plain; +#endif + +#ifdef SSS_EX_SE05x_AUTH_ID + const uint32_t auth_id = authID; +#endif + +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + ex_sss_platf_ctx_t *pPlatfCtx = &gPlatfCtx; + + pCtx->pTunnel_ctx = &gTunnel_ctx; + pPlatfCtx->phost_session = &pCtx->host_session; + pPlatfCtx->phost_ks = &pCtx->host_ks; + pPfSession = &pPlatfCtx->platf_session; + pConnectCtx = &pPlatfCtx->platf_open_ctx; + pConnectCtx->auth.ctx.scp03.pStatic_ctx = &pPlatfCtx->ex_se05x_auth.scp03.ex_static; + pConnectCtx->auth.ctx.scp03.pDyn_ctx = &pPlatfCtx->ex_se05x_auth.scp03.ex_dyn; + +#else + pPfSession = &pCtx->session; + pConnectCtx = &pCtx->se05x_open_ctx; +#endif + +#if defined(SMCOM_JRCP_V1) + if (ex_sss_boot_isSocketPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_JRCP_V1; + pConnectCtx->portName = portName; + } +#endif + +#if defined(SMCOM_JRCP_V2) + if (ex_sss_boot_isSocketPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_JRCP_V2; + pConnectCtx->portName = portName; + } +#endif + +#if defined(RJCT_VCOM) + if (ex_sss_boot_isSerialPortName(portName)) { + pConnectCtx->connType = kType_SE_Conn_Type_VCOM; + pConnectCtx->portName = portName; + } +#endif + +#if defined(SCI2C) +#error "Not a valid combination" +#endif + +#if defined(T1oI2C) + pConnectCtx->connType = kType_SE_Conn_Type_T1oI2C; + pConnectCtx->portName = portName; +#endif + +#if defined(SMCOM_PCSC) + pConnectCtx->connType = kType_SE_Conn_Type_PCSC; + pConnectCtx->portName = portName; +#endif + +#if defined(SMCOM_PN7150) + pConnectCtx->connType = kType_SE_Conn_Type_NFC; + pConnectCtx->portName = NULL; +#endif + +#if defined(SMCOM_RC663_VCOM) + if (portName == NULL) { + static const char *sszCOMPort = EX_SSS_BOOT_SSS_COMPORT_DEFAULT; + portName = sszCOMPort; + } + pConnectCtx->connType = kType_SE_Conn_Type_NFC; + pConnectCtx->portName = portName; +#endif + + +#if SSS_HAVE_HOSTCRYPTO_ANY + pConnectCtx->auth.authType = SSS_EX_SE05x_AUTH_MECH; +#ifdef SSS_EX_SE05x_AUTH_ID + status = + ex_sss_se05x_prepare_host_keys(&pCtx->host_session, &pCtx->host_ks, pConnectCtx, &pCtx->ex_se05x_auth, auth_id); +#else + status = + ex_sss_se05x_prepare_host_keys(&pCtx->host_session, &pCtx->host_ks, pConnectCtx, &pCtx->ex_se05x_auth, 0); +#endif // SSS_EX_SE05x_AUTH_ID + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_se05x_prepare_host_keys failed"); + goto cleanup; + } +#endif // SSS_HAVE_HOSTCRYPTO_ANY + if (SSS_EX_SE05x_AUTH_MECH == kSSS_AuthType_SCP03 || SSS_EX_SE05x_AUTH_MECH == kSSS_AuthType_None) { + status = sss_session_open(pPfSession, kType_SSS_SE_SE05x, 0, SSS_EX_CONNECTION_TYPE, pConnectCtx); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + goto cleanup; + } + } +#ifdef SSS_EX_SE05x_AUTH_ID + else { + status = sss_session_open(pPfSession, kType_SSS_SE_SE05x, auth_id, SSS_EX_CONNECTION_TYPE, pConnectCtx); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + } + } +#else + else { + LOG_E("Invalid combination for boot selection"); + status = kStatus_SSS_Fail; + } +#endif /* SSS_EX_SE05x_AUTH_ID */ +#ifdef SSS_EX_SE05x_AUTH_ID +#if (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) || (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) || \ + (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + SE05x_Connect_Ctx_t *pchannlCtxt = &pCtx->se05x_open_ctx; + pchannlCtxt->auth.authType = SSS_EX_SE05x_TUNN_AUTH_MECH; + + status = ex_sss_se05x_prepare_host_keys( + &pCtx->host_session, &pCtx->host_ks, pchannlCtxt, &pPlatfCtx->ex_se05x_auth, auth_id); + if (kStatus_SSS_Success != status) { + LOG_E("ex_sss_se05x_prepare_host_keys failed"); + goto cleanup; + } + + status = sss_tunnel_context_init(pCtx->pTunnel_ctx, pPfSession /* session */); + if (kStatus_SSS_Success != status) { + LOG_E("sss_tunnel_context_init failed"); + goto cleanup; + } + + pchannlCtxt->connType = kType_SE_Conn_Type_Channel; + pchannlCtxt->tunnelCtx = pCtx->pTunnel_ctx; + if (pchannlCtxt->auth.authType == kSSS_AuthType_ID) { + connectType = kSSS_ConnectionType_Password; + } + else { + connectType = kSSS_ConnectionType_Encrypted; + } + status = sss_session_open(&pCtx->session, kType_SSS_SE_SE05x, auth_id, connectType, pchannlCtxt); + if (kStatus_SSS_Success != status) { + LOG_E("sss_session_open failed"); + goto cleanup; + } + + ((sss_se05x_session_t *)&pCtx->session)->s_ctx.conn_ctx = ((sss_se05x_session_t *)pPfSession)->s_ctx.conn_ctx; + +#endif +#endif //SSS_EX_SE05x_AUTH_ID + +cleanup: + return status; +} + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c new file mode 100644 index 00000000000..ea0d47f65c8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c @@ -0,0 +1,602 @@ +/* + * + * Copyright 2019-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file +* +* ex_sss_se050x_auth.c: *The purpose and scope of this file* +* +* Project: sss-doc-upstream +* +* $Date: Mar 10, 2019 $ +* $Author: ing05193 $ +* $Revision$ +*/ + +/* ***************************************************************************************************************** +* Includes +* ***************************************************************************************************************** */ +#include +#include +#include +#include + +#include "ex_sss_auth.h" +#include "ex_sss_boot_int.h" +#include "nxLog_App.h" +#include "nxScp03_Types.h" +#if defined(SECURE_WORLD) +#include "fsl_sss_lpc55s_apis.h" +#endif +/* ***************************************************************************************************************** +* Internal Definitions +* ***************************************************************************************************************** */ + +#define AUTH_KEY_SIZE 16 +#define SCP03_MAX_AUTH_KEY_SIZE 52 +/* ***************************************************************************************************************** +* Type Definitions +* ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** +* Global and Static Variables +* Total Size: NNNbytes +* ***************************************************************************************************************** */ + +/* ***************************************************************************************************************** +* Private Functions Prototypes +* ***************************************************************************************************************** */ + +#if SSSFTR_SE05X_AuthSession +static sss_status_t ex_sss_se05x_prepare_host_userid( + sss_object_t *pObj, sss_key_store_t *pKs, uint8_t *se050Authkey, size_t authKeyLen); +#endif + +#if SSS_HAVE_SCP_SCP03_SSS +static sss_status_t ex_sss_se05x_prepare_host_platformscp( + NXSCP03_AuthCtx_t *pCtx, ex_SE05x_authCtx_t *pauthctx, sss_key_store_t *pKs); + +#if SSSFTR_SE05X_AuthECKey +static sss_status_t ex_sss_se05x_prepare_host_eckey(SE05x_AuthCtx_ECKey_t *pCtx, + ex_SE05x_authCtx_t *pauthctx, + sss_key_store_t *pKs, + uint8_t *hostEcdsakey, + size_t keylen); + +static sss_status_t Alloc_ECKeykey_toSE05xAuthctx( + sss_object_t *keyObject, sss_key_store_t *pKs, uint32_t keyId, sss_key_part_t keypart); + +#endif // SSSFTR_SE05X_AuthECKey +#if SSSFTR_SE05X_AuthSession +static sss_status_t ex_sss_se05x_prepare_host_AppletScp03Keys( + NXSCP03_AuthCtx_t *pAuthCtx, ex_SE05x_authCtx_t *pauthctx, sss_key_store_t *host_k, uint8_t *authkey); +#endif +static sss_status_t Alloc_Scp03key_toSE05xAuthctx(sss_object_t *keyObject, sss_key_store_t *pKs, uint32_t keyId); + +#if SSSFTR_SE05X_AuthSession +static sss_status_t Alloc_AppletScp03key_toSE05xAuthctx( + sss_object_t *keyObject, uint32_t keyId, sss_key_store_t *host_ks); +#endif // SSSFTR_SE05X_AuthSession + +#endif + +/* ***************************************************************************************************************** +* Public Functions +* ***************************************************************************************************************** */ + +#if SSS_HAVE_HOSTCRYPTO_ANY +sss_status_t ex_sss_se05x_prepare_host(sss_session_t *host_session, + sss_key_store_t *host_ks, + SE_Connect_Ctx_t *se05x_open_ctx, + ex_SE05x_authCtx_t *se05x_auth_ctx, + SE_AuthType_t auth_type) +{ + sss_status_t status = kStatus_SSS_Fail; + + if (host_session->subsystem == kType_SSS_SubSystem_NONE) { + sss_type_t hostsubsystem = kType_SSS_SubSystem_NONE; + +#if SSS_HAVE_MBEDTLS + hostsubsystem = kType_SSS_mbedTLS; +#elif SSS_HAVE_OPENSSL + hostsubsystem = kType_SSS_OpenSSL; +#elif SSS_HAVE_HOSTCRYPTO_USER + hostsubsystem = kType_SSS_Software; +#endif + + status = sss_host_session_open(host_session, hostsubsystem, 0, kSSS_ConnectionType_Plain, NULL); + + if (kStatus_SSS_Success != status) { + LOG_E("Failed to open Host Session"); + goto cleanup; + } + status = sss_host_key_store_context_init(host_ks, host_session); + if (kStatus_SSS_Success != status) { + LOG_E("Host: sss_key_store_context_init failed"); + goto cleanup; + } + status = sss_host_key_store_allocate(host_ks, __LINE__); + if (kStatus_SSS_Success != status) { + LOG_E("Host: sss_key_store_allocate failed"); + goto cleanup; + } + } + switch (auth_type) { + case kSSS_AuthType_ID: { + se05x_open_ctx->auth.ctx.idobj.pObj = &se05x_auth_ctx->id.ex_id; +#if SSSFTR_SE05X_AuthSession + uint8_t se050Authkey[] = EX_SSS_AUTH_SE05X_UserID_VALUE; + size_t authKeyLen = sizeof(se050Authkey); + status = + ex_sss_se05x_prepare_host_userid(se05x_open_ctx->auth.ctx.idobj.pObj, host_ks, se050Authkey, authKeyLen); +#endif + } break; +#if SSS_HAVE_SCP_SCP03_SSS + case kSSS_AuthType_SCP03: + status = ex_sss_se05x_prepare_host_platformscp(&se05x_open_ctx->auth.ctx.scp03, se05x_auth_ctx, host_ks); + break; +#if SSSFTR_SE05X_AuthECKey + case kSSS_AuthType_ECKey: { + uint8_t hostEcdsakey[] = EX_SSS_AUTH_SE05X_KEY_HOST_ECDSA_KEY; + size_t keylen = sizeof(hostEcdsakey); + status = ex_sss_se05x_prepare_host_eckey( + &se05x_open_ctx->auth.ctx.eckey, se05x_auth_ctx, host_ks, hostEcdsakey, keylen); + } break; +#endif + case kSSS_AuthType_AESKey: { +#if SSSFTR_SE05X_AuthSession + uint8_t appletkey[] = EX_SSS_AUTH_SE05X_APPLETSCP_VALUE; + status = ex_sss_se05x_prepare_host_AppletScp03Keys( + &se05x_open_ctx->auth.ctx.scp03, se05x_auth_ctx, host_ks, appletkey); +#endif + } break; +#endif + case kSSS_AuthType_None: + /* Nothing to do */ + status = kStatus_SSS_Success; + break; + default: + status = kStatus_SSS_Fail; + LOG_E("Not handled"); + } + + if (kStatus_SSS_Success != status) { + LOG_E( + "Host: ex_sss_se05x_prepare_host_ " + "failed", + auth_type); + goto cleanup; + } + se05x_open_ctx->auth.authType = auth_type; + +cleanup: + return status; +} + +/* Use this host crypto set up multiple sessions */ +sss_status_t ex_sss_se05x_prepare_host_keys(sss_session_t *pHostSession, + sss_key_store_t *pHostKs, + SE_Connect_Ctx_t *pConnectCtx, + ex_SE05x_authCtx_t *se05x_auth_ctx, + uint32_t Id) +{ + sss_status_t status = kStatus_SSS_Fail; + sss_type_t hostsubsystem = kType_SSS_SubSystem_NONE; + +#if SSS_HAVE_MBEDTLS + hostsubsystem = kType_SSS_mbedTLS; +#elif SSS_HAVE_OPENSSL + hostsubsystem = kType_SSS_OpenSSL; +#elif SSS_HAVE_HOSTCRYPTO_USER + hostsubsystem = kType_SSS_Software; +#endif + + status = sss_host_session_open(pHostSession, hostsubsystem, 0, kSSS_ConnectionType_Plain, NULL); + + if (kStatus_SSS_Success != status) { + LOG_E("Failed to open Host Session"); + goto cleanup; + } + status = sss_host_key_store_context_init(pHostKs, pHostSession); + if (kStatus_SSS_Success != status) { + LOG_E("Host: sss_key_store_context_init failed"); + goto cleanup; + } + status = sss_host_key_store_allocate(pHostKs, __LINE__); + if (kStatus_SSS_Success != status) { + LOG_E("Host: sss_key_store_allocate failed"); + goto cleanup; + } + + switch (pConnectCtx->auth.authType) { + case kSSS_AuthType_ID: { + pConnectCtx->auth.ctx.idobj.pObj = &se05x_auth_ctx->id.ex_id; +#if SSSFTR_SE05X_AuthSession + uint8_t *se050Authkey = NULL; + size_t authKeyLen; + uint8_t Authkey1[] = EX_SSS_AUTH_SE05X_UserID_VALUE; + uint8_t Authkey2[] = EX_SSS_AUTH_SE05X_UserID_VALUE2; + if (Id == kEX_SSS_ObjID_UserID_Auth) { + authKeyLen = sizeof(Authkey1); + se050Authkey = &Authkey1[0]; + } + else if (Id == kEX_SSS_ObjID_UserID_Auth + 0x10) { + authKeyLen = sizeof(Authkey2); + se050Authkey = &Authkey2[0]; + } + else { + LOG_E("This authID is incorrect"); + break; + } + status = ex_sss_se05x_prepare_host_userid(pConnectCtx->auth.ctx.idobj.pObj, pHostKs, se050Authkey, authKeyLen); +#endif + } break; +#if SSS_HAVE_SCP_SCP03_SSS + case kSSS_AuthType_SCP03: + status = ex_sss_se05x_prepare_host_platformscp(&pConnectCtx->auth.ctx.scp03, se05x_auth_ctx, pHostKs); + break; +#if SSSFTR_SE05X_AuthECKey + case kSSS_AuthType_ECKey: { + uint8_t *hostEcdsakey = NULL; + size_t keylen; + uint8_t hostEcdsakey1[] = EX_SSS_AUTH_SE05X_KEY_HOST_ECDSA_KEY; + uint8_t hostEcdsakey2[] = EX_SSS_AUTH_SE05X_KEY_HOST_ECDSA_KEY2; + if (Id == kEX_SSS_objID_ECKEY_Auth) { + keylen = sizeof(hostEcdsakey1); + hostEcdsakey = &hostEcdsakey1[0]; + } + else if (Id == kEX_SSS_objID_ECKEY_Auth + 0x10) { + keylen = sizeof(hostEcdsakey2); + hostEcdsakey = &hostEcdsakey2[0]; + } + else { + LOG_E("This authID is incorrect"); + break; + } + status = ex_sss_se05x_prepare_host_eckey( + &pConnectCtx->auth.ctx.eckey, se05x_auth_ctx, pHostKs, hostEcdsakey, keylen); + } break; +#endif + case kSSS_AuthType_AESKey: { +#if SSSFTR_SE05X_AuthSession + uint8_t *appletkey = NULL; + uint8_t appletkey1[] = EX_SSS_AUTH_SE05X_APPLETSCP_VALUE; + uint8_t appletkey2[] = EX_SSS_AUTH_SE05X_APPLETSCP_VALUE2; + if (Id == kEX_SSS_ObjID_APPLETSCP03_Auth) { + appletkey = appletkey1; + } + else if (Id == kEX_SSS_ObjID_APPLETSCP03_Auth + 0x10) { + appletkey = appletkey2; + } + else { + LOG_E("This authID is incorrect"); + break; + } + status = + ex_sss_se05x_prepare_host_AppletScp03Keys(&pConnectCtx->auth.ctx.scp03, se05x_auth_ctx, pHostKs, appletkey); +#endif + } break; +#endif + case kSSS_AuthType_None: + /* Nothing to do */ + status = kStatus_SSS_Success; + break; + default: + status = kStatus_SSS_Fail; + LOG_E("Not handled"); + } + + if (kStatus_SSS_Success != status) { + goto cleanup; + } + +cleanup: + return status; +} + +#endif // SSS_HAVE_HOSTCRYPTO_ANY + +/* ***************************************************************************************************************** +* Private Functions +* ***************************************************************************************************************** */ +#if SSSFTR_SE05X_AuthSession +static sss_status_t ex_sss_se05x_prepare_host_userid( + sss_object_t *pObj, sss_key_store_t *pKs, uint8_t *se050Authkey, size_t authKeyLen) +{ + sss_status_t status = kStatus_SSS_Fail; + uint32_t keyId = __LINE__; + uint8_t data[32] = { + 0, + }; + size_t dataLen = sizeof(data); + size_t keyBitLen = sizeof(data) * 8; + + if (pObj->keyId != keyId) { + status = sss_host_key_object_init(pObj, pKs); + if (status != kStatus_SSS_Success) { + LOG_E("UserID: Key Object Init failed"); + goto cleanup; + } + + status = sss_host_key_object_allocate_handle( + pObj, keyId, kSSS_KeyPart_Default, kSSS_CipherType_UserID, authKeyLen + 1, kKeyObject_Mode_Persistent); + + if (status != kStatus_SSS_Success) { + LOG_E("UserID: Allocate failed"); + goto cleanup; + } + + status = sss_host_key_store_set_key(pObj->keyStore, pObj, se050Authkey, authKeyLen, authKeyLen * 8, NULL, 0); + + if (status != kStatus_SSS_Success) { + LOG_E("UserID: Set value failed"); + } + } + else { + status = sss_host_key_store_get_key(pObj->keyStore, pObj, data, &dataLen, &keyBitLen); + if (status == kStatus_SSS_Success) { + if (memcmp(data, se050Authkey, authKeyLen) != 0) { + status = kStatus_SSS_Fail; + LOG_E("UserID: Key Value is different"); + goto cleanup; + } + } + else { + LOG_E("UserID: Get value failed"); + } + } + +cleanup: + return status; +} +#endif // SSSFTR_SE05X_AuthSession + +#if SSS_HAVE_SCP_SCP03_SSS +/* Function to Set Init and Allocate static Scp03Keys and Init Allocate dynamic keys */ +static sss_status_t ex_sss_se05x_prepare_host_platformscp( + NXSCP03_AuthCtx_t *pAuthCtx, ex_SE05x_authCtx_t *pEx_auth, sss_key_store_t *pKs) +{ + sss_status_t status = kStatus_SSS_Fail; + uint8_t KEY_ENC[] = EX_SSS_AUTH_SE05X_KEY_ENC; + uint8_t KEY_MAC[] = EX_SSS_AUTH_SE05X_KEY_MAC; + uint8_t KEY_DEK[] = EX_SSS_AUTH_SE05X_KEY_DEK; + +#ifdef EX_SSS_SCP03_FILE_PATH + + uint8_t enc[AUTH_KEY_SIZE] = {0}; + uint8_t mac[AUTH_KEY_SIZE] = {0}; + uint8_t dek[AUTH_KEY_SIZE] = {0}; + + status = scp03_keys_from_path(&enc[0], sizeof(enc), &mac[0], sizeof(mac), &dek[0], sizeof(dek)); + + if (status == kStatus_SSS_Success) { + memcpy(KEY_ENC, enc, sizeof(KEY_ENC)); + memcpy(KEY_MAC, mac, sizeof(KEY_MAC)); + memcpy(KEY_DEK, dek, sizeof(KEY_DEK)); + } + +#endif // EX_SSS_SCP03_FILE_PATH + + pAuthCtx->pStatic_ctx = &pEx_auth->scp03.ex_static; + pAuthCtx->pDyn_ctx = &pEx_auth->scp03.ex_dyn; + NXSCP03_StaticCtx_t *pStatic_ctx = pAuthCtx->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthCtx->pDyn_ctx; + + pStatic_ctx->keyVerNo = EX_SSS_AUTH_SE05X_KEY_VERSION_NO; + + /* Init Allocate ENC Static Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pStatic_ctx->Enc, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set ENC Static Key */ + status = sss_host_key_store_set_key(pKs, &pStatic_ctx->Enc, KEY_ENC, sizeof(KEY_ENC), sizeof(KEY_ENC) * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate MAC Static Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pStatic_ctx->Mac, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set MAC Static Key */ + status = sss_host_key_store_set_key(pKs, &pStatic_ctx->Mac, KEY_MAC, sizeof(KEY_MAC), sizeof(KEY_MAC) * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate DEK Static Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pStatic_ctx->Dek, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set DEK Static Key */ + status = sss_host_key_store_set_key(pKs, &pStatic_ctx->Dek, KEY_DEK, sizeof(KEY_DEK), sizeof(KEY_DEK) * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate ENC Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Enc, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate MAC Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Mac, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate DEK Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Rmac, pKs, MAKE_TEST_ID(__LINE__)); + return status; +} +#endif + +#if SSS_HAVE_SCP_SCP03_SSS +static sss_status_t Alloc_Scp03key_toSE05xAuthctx(sss_object_t *keyObject, sss_key_store_t *pKs, uint32_t keyId) +{ + sss_status_t status = kStatus_SSS_Fail; + status = sss_host_key_object_init(keyObject, pKs); + if (status != kStatus_SSS_Success) { + return status; + } + + status = sss_host_key_object_allocate_handle(keyObject, + keyId, + kSSS_KeyPart_Default, + kSSS_CipherType_AES, + SCP03_MAX_AUTH_KEY_SIZE, + kKeyObject_Mode_Transient); + return status; +} + +#if SSSFTR_SE05X_AuthECKey +static sss_status_t Alloc_ECKeykey_toSE05xAuthctx( + sss_object_t *keyObject, sss_key_store_t *pKs, uint32_t keyId, sss_key_part_t keypart) +{ + sss_status_t status = kStatus_SSS_Fail; + status = sss_host_key_object_init(keyObject, pKs); + if (status != kStatus_SSS_Success) { + return status; + } + status = sss_host_key_object_allocate_handle( + keyObject, keyId, keypart, kSSS_CipherType_EC_NIST_P, 256, kKeyObject_Mode_Persistent); + return status; +} + +static sss_status_t ex_sss_se05x_prepare_host_eckey(SE05x_AuthCtx_ECKey_t *pAuthCtx, + ex_SE05x_authCtx_t *pEx_auth, + sss_key_store_t *pKs, + uint8_t *hostEcdsakey, + size_t keylen) +{ + sss_status_t status = kStatus_SSS_Fail; + pAuthCtx->pStatic_ctx = &pEx_auth->eckey.ex_static; + pAuthCtx->pDyn_ctx = &pEx_auth->eckey.ex_dyn; + + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthCtx->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthCtx->pDyn_ctx; + + /* Init allocate Host ECDSA Key pair */ + status = Alloc_ECKeykey_toSE05xAuthctx(&pStatic_ctx->HostEcdsaObj, pKs, MAKE_TEST_ID(__LINE__), kSSS_KeyPart_Pair); + /* Set Host ECDSA Key pair */ + status = sss_host_key_store_set_key(pKs, &pStatic_ctx->HostEcdsaObj, hostEcdsakey, keylen, 256, NULL, 0); + if (status == kStatus_SSS_Fail) { + return status; + } + + /* Init allocate Host ECKA Key pair */ + status = Alloc_ECKeykey_toSE05xAuthctx(&pStatic_ctx->HostEcKeypair, pKs, MAKE_TEST_ID(__LINE__), kSSS_KeyPart_Pair); + /* Generate Host EC Key pair */ + status = sss_host_key_store_generate_key(pKs, &pStatic_ctx->HostEcKeypair, 256, NULL); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init allocate SE ECKA Public Key */ + status = Alloc_ECKeykey_toSE05xAuthctx(&pStatic_ctx->SeEcPubKey, pKs, MAKE_TEST_ID(__LINE__), kSSS_KeyPart_Public); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate Master Secret */ + status = Alloc_Scp03key_toSE05xAuthctx(&pStatic_ctx->masterSec, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate ENC Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Enc, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate MAC Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Mac, pKs, MAKE_TEST_ID(__LINE__)); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate DEK Session Key */ + status = Alloc_Scp03key_toSE05xAuthctx(&pDyn_ctx->Rmac, pKs, MAKE_TEST_ID(__LINE__)); + + return status; +} +#endif // SSSFTR_SE05X_AuthECKey + +#if SSSFTR_SE05X_AuthSession +/* Function to Set Init and Allocate static Scp03Keys and Init Allocate dynamic keys */ +static sss_status_t ex_sss_se05x_prepare_host_AppletScp03Keys( + NXSCP03_AuthCtx_t *pAuthCtx, ex_SE05x_authCtx_t *pEx_auth, sss_key_store_t *host_k, uint8_t *authkey) +{ + sss_status_t status = kStatus_SSS_Fail; + pAuthCtx->pStatic_ctx = &pEx_auth->scp03.ex_static; + pAuthCtx->pDyn_ctx = &pEx_auth->scp03.ex_dyn; + NXSCP03_StaticCtx_t *pStatic_ctx = pAuthCtx->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthCtx->pDyn_ctx; + + /* Init Allocate ENC Static Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pStatic_ctx->Enc, MAKE_TEST_ID(__LINE__), host_k); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set ENC Static Key */ + status = sss_host_key_store_set_key(host_k, &pStatic_ctx->Enc, authkey, AUTH_KEY_SIZE, AUTH_KEY_SIZE * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate MAC Static Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pStatic_ctx->Mac, MAKE_TEST_ID(__LINE__), host_k); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set MAC Static Key */ + status = sss_host_key_store_set_key(host_k, &pStatic_ctx->Mac, authkey, AUTH_KEY_SIZE, AUTH_KEY_SIZE * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate DEK Static Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pStatic_ctx->Dek, MAKE_TEST_ID(__LINE__), host_k); + if (status != kStatus_SSS_Success) { + return status; + } + /* Set DEK Static Key */ + status = sss_host_key_store_set_key(host_k, &pStatic_ctx->Dek, authkey, AUTH_KEY_SIZE, AUTH_KEY_SIZE * 8, NULL, 0); + if (status != kStatus_SSS_Success) { + return status; + } + + /* Init Allocate ENC Session Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pDyn_ctx->Enc, MAKE_TEST_ID(__LINE__), host_k); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate MAC Session Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pDyn_ctx->Mac, MAKE_TEST_ID(__LINE__), host_k); + if (status != kStatus_SSS_Success) { + return status; + } + /* Init Allocate DEK Session Key */ + status = Alloc_AppletScp03key_toSE05xAuthctx(&pDyn_ctx->Rmac, MAKE_TEST_ID(__LINE__), host_k); + return status; +} + +static sss_status_t Alloc_AppletScp03key_toSE05xAuthctx( + sss_object_t *keyObject, uint32_t keyId, sss_key_store_t *host_ks) +{ + sss_status_t status = kStatus_SSS_Fail; + status = sss_host_key_object_init(keyObject, host_ks); + if (status != kStatus_SSS_Success) { + return status; + } + + status = sss_host_key_object_allocate_handle( + keyObject, keyId, kSSS_KeyPart_Default, kSSS_CipherType_AES, AUTH_KEY_SIZE, kKeyObject_Mode_Persistent); + return status; +} +#endif // SSSFTR_SE05X_AuthSession + +#endif //SSS_HAVE_SCP_SCP03_SSS diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h new file mode 100644 index 00000000000..bb4f10f6157 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h @@ -0,0 +1,428 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _FSL_SSCP_H_ +#define _FSL_SSCP_H_ + +#include +#include +#include + +#include "fsl_sscp_commands.h" + +/*! +@defgroup sscp Security Subsystem Communication Protocol (SSCP) + + # SSCP protocol description + + SSCP is very simple remote procedure call protocol. + Function parameters are described by one or multiple SSCP operation descriptor(s). + One parameter descriptor describes up to 7 function parameters as contexts, buffers, values or aggregates. + Multiple parameter descriptors can be linked by the aggregate parameter type (kSSCP_ParamType_Aggregate). + + Function arguments are described as a buffer (address and size), a value (a tuple of two words), + a context (pointer and type id) or an aggregate. + If the parameter is the aggregate (kSSCP_ParamType_Aggregate type), then it will contain a pointer to another + sscp_operation_t. This allows to link additional sscp_operation_t. + + The protocol allows for remote calling by a copy of all arguments (including buffer contents), + that is, to remote call to a sub-system having no physical access to Host CPU memory. + If a sub-system has access to Host CPU memory, the SSCP transport implementation can decide to transfer + only the buffer descriptor (pointer and size) without physically transmitting the buffer content, + as the buffer content can be accessed by the sub-system when the remote function executes. + The same holds for the context descriptor (pointer and type id). The actual SSCP implementation + can transfer only pointer to a sub-system, if the sub-system has the memory, where the context data + structure is located, and if it has an application level knowledge of the context data structure + layout (either based on the command id or the context type id). + + Byte length (for void* and uintptr_t) and endianess is inherited from the host CPU. + + # SSCP operation descriptors + + A remote function is invoked by transmitting a command id (unique identifier to specify a remote function), + followed by SSCP operation descriptors ::sscp_operation_t. There is always one descriptor and optionally + it can link another descriptor, if the number of ::sscp_operation_t params is not sufficient + to described all function parameters. In the example below, the last params[n-1] on the left side is an aggregate + that links secondary descriptor. + + @code + command + paramTypes + params[0] + ... + params[n-1] ------------- paramTypes + params[0] + ... + params[n-1] + @endcode + + where n = 1, 2, ..., 7. + + These operation descriptors serve as an input to ::sscp_invoke_command() function. + The serialization to the communication system is implementation specific. + For example, implementations may decide to transfer only pointers and values (without payloads), + because security sub-system has access to memory, so it can read and write payloads on its own during function + execution. Other implementations may need to serialize everything to a communication bus. + + This implementation specific data transfer is implemented by an invoke() function. + During implementation specific initialization of the SSCP transfer, sscp__init() function, + a pointer to implementation specific invoke() function is stored in the sscp__context_t. + + @code + sscp_mu_init(ctx, invoke = sscp_mu_invoke_command) + ... + ctx->invoke() + ... + ctx->invoke() + ... + sscp_deinit(ctx) + @endcode + + # Example for SSCP protocol implementation with S3MU + + The ::sscp_invoke_command() implementation for the S3MU (Sentinel), ::sscp_mu_invoke_command(), + builds up the serial message as follows: + + word 0 | word 1 | word 2 | word 3 | ... | word (n*2 + 1) + -------|-----------|-------------|-------------|-----|--------------- + CMD |paramTypes | params[0].a | params[0].b | ... | params[n-1].b + + where the n value is CMD specific and it is present in the CMD word. + Passing this message through S3MU to the Sentinel sub-system is done by simply moving the 16 words into S3MU Tx A + registers. + + # Example with the SSS API + + @code + sss_status_t sss_aead_one_go(sss_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t tagLen); + + uint32_t cmd = kSSCP_CMD_SSS_AeadOneGo(n=6); + + sscp_operation_t op = (0); + sscp_status_t status = kStatus_SSCP_Fail; + uint32_t ret = 0; + + if (context->mode == Encrypt) + { + op.paramTypes = SSCP_OP_SET_PARAM(kSSCP_ParamType_ContextReference, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefOutput, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefOutput, + kSSCP_ParamType_None); + } + else + { + op.paramTypes = SSCP_OP_SET_PARAM(kSSCP_ParamType_ContextReference, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefOutput, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_MemrefInput, + kSSCP_ParamType_None); + } + + ... context is an aggregate data type ... + ... implementation specific sscp_operation_t to serialize the context data ... + op.params[0].context.ptr = context; + op.params[0].context.type = kSSCP_ParamContextType_SSS_Aead; + + ... function parameters ... + op.params[1].memref.buffer = srcData; + op.params[1].memref.size = size; + + op.params[2].memref.buffer = destData; + op.params[2].memref.size = size; + + op.params[3].memref.buffer = nonce; + op.params[3].memref.size = nonceLen; + + op.params[4].memref.buffer = aad; + op.params[4].memref.size = aadLen; + + op.params[5].memref.buffer = tag; + op.params[5].memref.size = tagLen; + + ... Serialize to the link ... + status = context->session->sscp->invoke(context->sscpSession, cmd, &op, &ret); + if (status != kStatus_SSCP_Success) + { + return kStatus_SSS_Fail; + } + + return (sss_status_t)ret; + + @endcode + + # Example with the SSCP Client API + + @code + SSCP_Result SSCP_InvokeCommand(SSCP_Session *sessionSSCP, + uint32_t commandID, + SSCP_Operation *operation, + uint32_t *returnOrigin); + + + uint32_t cmd = kSSCP_CMD_SSCP_InvokeCommand; + + sscp_operation_t op = {0}; + sscp_status_t status = kStatus_SSCP_Fail; + uint32_t ret = 0; + + op.paramTypes = SSCP_OP_SET_PARAM(kSSCP_ParamType_ContextReference, + kSSCP_ParamType_ValueInput, + kSSCP_ParamType_ContextReference, + kSSCP_ParamType_MemrefOutput, + kSSCP_ParamType_None, + kSSCP_ParamType_None, + kSSCP_ParamType_None); + + op.params[0].context.ptr = sessionSSCP; + op.params[0].context.type = kSSCP_ParamContextType_SSCP_Session; + + op.params[1].value.a = commandID; + op.params[1].value.b = 0; + + op.params[2].context.ptr = operation; + op.params[2].context.type = kSSCP_ParamContextType_SSCP_Operation; + + op.params[3].memref.buffer = returnOrigin; + op.params[3].memref.size = sizeof(*returnOrigin); + + @endcode + */ + +/*! + * @addtogroup sscp + * @{ + */ + +/*! @brief Maximum number of parameters to be supported in one sscp_operation_t */ +#define SSCP_OPERATION_PARAM_COUNT (7) + +/*! @brief Default SSCP context is a pointer to memory. */ +#ifndef SSCP_MAX_CONTEXT_SIZE +#define SSCP_MAX_CONTEXT_SIZE (sizeof(void *)) +#endif + +/*! @brief Set parameter types for the SSCP operation. Each param type is encoded into 4-bits bit field. */ +#define SSCP_OP_SET_PARAM(p0, p1, p2, p3, p4, p5, p6) \ + (((uint32_t)p0 & 0xFu)) | (((uint32_t)p1 & 0xFu) << 4u) | (((uint32_t)p2 & 0xFu) << 8u) | \ + (((uint32_t)p3 & 0xFu) << 12u) | (((uint32_t)p4 & 0xFu) << 16u) | (((uint32_t)p5 & 0xFu) << 20u) | \ + (((uint32_t)p6 & 0xFu) << 24u); + +/*! @brief Decode i-th parameter as 4-bit unsigned integer. */ +#define SSCP_OP_GET_PARAM(i, paramTypes) ((uint32_t)((((uint32_t)paramTypes) >> i * 4) & 0xFu)) + +/*! @brief Data type for SSCP function return values */ +typedef uint32_t sscp_status_t; + +typedef struct _sscp_context sscp_context_t; + +/** + * @brief SSCP operation descriptor + * + */ +typedef struct _sscp_operation sscp_operation_t; + +/*! @brief Typedef for a function that sends a command and associated parameters to security sub-system + * + * The commandID and operation content is serialized and sent over to the selected security sub-system. + * This is implementation specific function. + * The function can invoke both blocking and non-blocking secure functions in the selected security sub-system. + * + * @param context Initialized SSCP context + * @param commandID Command - an id of a remote secure function to be invoked + * @param op Description of function arguments as a sequence of buffers, values, context references and aggregates + * @param ret Return code of the remote secure function (application layer return value) + * + * @returns Status of the operation + * @retval kStatus_SSCP_Success A blocking command has completed or a non-blocking command has been accepted. + * @retval kStatus_SSCP_Fail Operation failure, for example hardware fail. + * @retval kStatus_SSCP_InvalidArgument One of the arguments is invalid for the function to execute. + */ +typedef sscp_status_t (*fn_sscp_invoke_command_t)( + sscp_context_t *context, uint32_t commandID, sscp_operation_t *op, uint32_t *ret); + +/** + * struct _sscp_context - SSCP context struct + * + * This data type is used to keep context of the SSCP link. + * It has one mandatory member - pointer to invoke() function. + * Otherwise it is completely implementation specific. + * + * @param invoke Pointer to implementation specific invoke() function + * @param context Container for the implementation specific data. + */ +struct _sscp_context +{ + fn_sscp_invoke_command_t invoke; + // sscp_status_t (*sscp_invoke_command)(sscp_context_t *context, uint32_t commandID, sscp_operation_t *op); + + /*! Implementation specific part */ + struct + { + uint8_t data[SSCP_MAX_CONTEXT_SIZE]; + } context; +}; + +/** + * struct _sscp_memref - Buffer + * + * This data type is used to describe a function argument as a buffer. + * + * @param buffer Memory address + * @param size Length of the buffer in bytes + */ +typedef struct _sscp_memref +{ + void *buffer; + size_t size; +} sscp_memref_t; + +/** + * struct _sscp_value - Small raw data + * + * This data type is used to describe a function argument as a tuple of two 32-bit values. + * + * @param a First 32-bit data value. + * @param b Second 32-bit data value. + */ +typedef struct _sscp_value +{ + uint32_t a; + uint32_t b; +} sscp_value_t; + +/** + * @brief SSCP descriptor for an aggregate + * + * This data type is used to link additional SSCP operation. + * + * @param op Pointer to sscp_operation_t. + */ +typedef struct _sscp_aggregate_operation +{ + sscp_operation_t *op; +} sscp_aggregate_operation_t; + +/** + * @brief SSCP descriptor for a context struct + * + * This data type is used pass context struct to SSCP by reference + * + * @param ptr Pointer to a data structure + * @param type 32-bit identifier specifying context struct type + */ +typedef struct _sscp_context_operation +{ + void *ptr; + uint32_t type; +} sscp_context_reference_t; + +/** + * @brief Data structure representing a function argument. + * + * Either the client uses a shared memory reference, or a small raw + * data container. + * + * @param value Small raw data container + * @param memref Memory reference + * @param aggregate Reference to another SSCP descriptor + * @param context Pointer to a data struct to be passed to SSCP by reference + */ +typedef union _sscp_parameter { + sscp_value_t value; + sscp_memref_t memref; + sscp_aggregate_operation_t aggregate; + sscp_context_reference_t context; +} sscp_parameter_t; + +/** + * @brief Data structure describing function arguments. + * Function argument are described as a sequence of buffers, values, context references and aggregates. + * It serves as an input to ::sscp_invoke_command(), an implementation specific serialization function. + * + * @param paramTypes Type of data passed. + * @param params Array of parameters of type sscp_parameter_t. + * + */ +struct _sscp_operation +{ + uint32_t paramTypes; + sscp_parameter_t params[SSCP_OPERATION_PARAM_COUNT]; +}; + +/** + * @brief Enum with SSCP operation parameters. + */ +typedef enum _sscp_param_types +{ + kSSCP_ParamType_None = 0, /*! Parameter not in use */ + kSSCP_ParamType_Aggregate = 0x1u, /*! Link to another ::sscp_operation_t */ + kSSCP_ParamType_ContextReference, /*! Reference to a context structure - pointer and type */ + kSSCP_ParamType_MemrefInput, /*! Reference to a memory buffer - input to remote function or service */ + kSSCP_ParamType_MemrefOutput, /*! Reference to a memory buffer - output by remote function or service. + Implementations shall update the size member of the ::sscp_memref_t + with the actual number of bytes written. */ + kSSCP_ParamType_MemrefInOut, /*! Reference to a memory buffer - input to and ouput from remote function or service + */ + kSSCP_ParamType_ValueInput, /*! Tuple of two 32-bit integers - input to remote function or service */ + kSSCP_ParamType_ValueOutput, /*! Tuple of two 32-bit integers - output by remote function or service */ +} sscp_param_types_t; + +/** + * @brief Enum with return values from SSCP functions + */ +enum _sscp_return_values +{ + kStatus_SSCP_Success = 0x10203040u, + kStatus_SSCP_Fail = 0x40302010u, +}; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Sends a command and associated parameters to security sub-system + * + * The commandID and operation content is serialized and sent over to the selected security sub-system. + * This is implementation specific function. + * The function can invoke both blocking and non-blocking secure functions in the selected security sub-system. + * + * @param context Initialized SSCP context + * @param commandID Command - an id of a remote secure function to be invoked + * @param op Description of function arguments as a sequence of buffers and values + * @param ret Return code of the remote secure function (application layer return value) + * + * @returns Status of the operation + * @retval kStatus_SSCP_Success A blocking command has completed or a non-blocking command has been accepted. + * @retval kStatus_SSCP_Fail Operation failure, for example hardware fail. + * @retval kStatus_SSCP_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sscp_status_t sscp_invoke_command(sscp_context_t *context, uint32_t commandID, sscp_operation_t *op, uint32_t *ret); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ /* end of sscp */ + +#endif /* _FSL_SSCP_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h new file mode 100644 index 00000000000..f1b71c086d7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h @@ -0,0 +1,1892 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +/** @file */ +#ifndef _FSL_SSS_H_ +#define _FSL_SSS_H_ + +#if !defined(SSS_CONFIG_FILE) +#include "fsl_sss_config.h" +#else +#include SSS_CONFIG_FILE +#endif + +#include + +#include "fsl_sss_types.h" + +/** Version of the SSS API */ +#define SSS_API_VERSION (0x00000001u) + +/** Size of an AES Block, in bytes */ +#define SSS_AES_BLOCK_SIZE (16u) +/** Size of a DES Block, in bytes */ +#define SSS_DES_BLOCK_SIZE (8u) +/** Size of a DES Key, in bytes */ +#define SSS_DES_KEY_SIZE (8u) +/** Size of a DES IV, in bytes */ +#define SSS_DES_IV_SIZE (8u) + +/** Status of the SSS APIs */ +typedef enum +{ + /** Operation was successful */ + kStatus_SSS_Success = 0x5a5a5a5au, + /** Operation failed */ + kStatus_SSS_Fail = 0x3c3c0000u, + /** Operation not performed because some of the passed parameters + * were found inappropriate */ + kStatus_SSS_InvalidArgument = 0x3c3c0001u, + /** Where the underlying sub-system *supports* multi-threading, + * Internal status to handle simultaneous access. + * + * This status is not expected to be returned to higher layers. + * */ + kStatus_SSS_ResourceBusy = 0x3c3c0002u, +} sss_status_t; + +/** Helper macro to set enum value */ + +#define SSS_ENUM(GROUP, INDEX) ((GROUP) | (INDEX)) + +/** Cryptographic sub system */ +typedef enum +{ + kType_SSS_SubSystem_NONE, + /** Software based */ + kType_SSS_Software = SSS_ENUM(0x01 << 8, 0x00), + kType_SSS_mbedTLS = SSS_ENUM(kType_SSS_Software, 0x01), + kType_SSS_OpenSSL = SSS_ENUM(kType_SSS_Software, 0x02), + /** HOST HW Based */ + kType_SSS_HW = SSS_ENUM(0x02 << 8, 0x00), + kType_SSS_SECO = SSS_ENUM(kType_SSS_HW, 0x01), + /** Isolated HW */ + kType_SSS_Isolated_HW = SSS_ENUM(0x04 << 8, 0x00), + kType_SSS_Sentinel = SSS_ENUM(kType_SSS_Isolated_HW, 0x01), + kType_SSS_Sentinel200 = SSS_ENUM(kType_SSS_Isolated_HW, 0x02), + kType_SSS_Sentinel300 = SSS_ENUM(kType_SSS_Isolated_HW, 0x03), + kType_SSS_Sentinel400 = SSS_ENUM(kType_SSS_Isolated_HW, 0x04), + kType_SSS_Sentinel500 = SSS_ENUM(kType_SSS_Isolated_HW, 0x05), + /** Secure Element */ + kType_SSS_SecureElement = SSS_ENUM(0x08 << 8, 0x00), + /** To connect to https://www.nxp.com/products/:A71CH */ + kType_SSS_SE_A71CH = SSS_ENUM(kType_SSS_SecureElement, 0x01), + kType_SSS_SE_A71CL = SSS_ENUM(kType_SSS_SecureElement, 0x02), + /** To connect to https://www.nxp.com/products/:SE050 */ + kType_SSS_SE_SE05x = SSS_ENUM(kType_SSS_SecureElement, 0x03), + kType_SSS_SubSystem_LAST +} sss_type_t; + +/** Destintion connection type */ +typedef enum +{ + /* Plain => Lowest level of security requested. + * => Probably a system with no mechanism to *identify* who + * has opened the session from host + * => Probably a system with Easy for man in the middle attack. + * + */ + kSSS_ConnectionType_Plain, + /* Password: + * => Some level of user authentication/identification requested + * => Probably a system with "static" authentication/identification. + * => Probably same Password us always. + * => "Password" mostly gets sent in plain over the communication layer + * => Probably a system with replay attack possible + */ + kSSS_ConnectionType_Password, + /* Encrypted: + * Communication is guaranteed to be Encrypted. + * For SE => This would mean highest level of authentication + * For other system => channel would be encrypted + * + * In general, almost a level of security that is definitely higher than + * Plain/Password/PIN. + * + * Using *Dynamic* Sessions Keys for authenticated communication. + */ + kSSS_ConnectionType_Encrypted +} sss_connection_type_t; + +#ifndef __DOXYGEN__ + +#define SSS_ALGORITHM_START_AES (0x00) +#define SSS_ALGORITHM_START_CHACHA (0x01) +#define SSS_ALGORITHM_START_DES (0x02) +#define SSS_ALGORITHM_START_SHA (0x03) +#define SSS_ALGORITHM_START_MAC (0x04) +#define SSS_ALGORITHM_START_DH (0x05) +#define SSS_ALGORITHM_START_DSA (0x06) +#define SSS_ALGORITHM_START_RSASSA_PKCS1_V1_5 (0x07) +#define SSS_ALGORITHM_START_RSASSA_PKCS1_PSS_MGF1 (0x08) +#define SSS_ALGORITHM_START_RSAES_PKCS1_OAEP (0x09) +#define SSS_ALGORITHM_START_RSAES_PKCS1_V1_5 (0x0A) +#define SSS_ALGORITHM_START_RSASSA_NO_PADDING (0x0B) +#define SSS_ALGORITHM_START_ECDSA (0x0C) +#define SSS_ALGORITHM_START_ECDAA (0x0D) + +/* Not available outside this file */ +#define SSS_ENUM_ALGORITHM(GROUP, INDEX) (((SSS_ALGORITHM_START_##GROUP) << 8) | (INDEX)) + +#endif + +/** Cryptographic algorithm to be applied */ +typedef enum /* _sss_algorithm */ +{ + kAlgorithm_None, + /* AES */ + kAlgorithm_SSS_AES_ECB = SSS_ENUM_ALGORITHM(AES, 0x01), + kAlgorithm_SSS_AES_CBC = SSS_ENUM_ALGORITHM(AES, 0x02), + kAlgorithm_SSS_AES_CTR = SSS_ENUM_ALGORITHM(AES, 0x03), + kAlgorithm_SSS_AES_GCM = SSS_ENUM_ALGORITHM(AES, 0x04), + kAlgorithm_SSS_AES_CCM = SSS_ENUM_ALGORITHM(AES, 0x05), + kAlgorithm_SSS_AES_GCM_INT_IV = SSS_ENUM_ALGORITHM(AES, 0x06), + /* CHACHA_POLY */ + kAlgorithm_SSS_CHACHA_POLY = SSS_ENUM_ALGORITHM(CHACHA, 0x01), + /* DES */ + kAlgorithm_SSS_DES_ECB = SSS_ENUM_ALGORITHM(DES, 0x01), + kAlgorithm_SSS_DES_CBC = SSS_ENUM_ALGORITHM(DES, 0x02), + /* DES3 */ + kAlgorithm_SSS_DES3_ECB = SSS_ENUM_ALGORITHM(DES, 0x03), + kAlgorithm_SSS_DES3_CBC = SSS_ENUM_ALGORITHM(DES, 0x04), + /* digest */ + /* doc:start hash_algo */ + kAlgorithm_SSS_SHA1 = SSS_ENUM_ALGORITHM(SHA, 0x01), + kAlgorithm_SSS_SHA224 = SSS_ENUM_ALGORITHM(SHA, 0x02), + kAlgorithm_SSS_SHA256 = SSS_ENUM_ALGORITHM(SHA, 0x03), + kAlgorithm_SSS_SHA384 = SSS_ENUM_ALGORITHM(SHA, 0x04), + kAlgorithm_SSS_SHA512 = SSS_ENUM_ALGORITHM(SHA, 0x05), + /* doc:end hash_algo */ + /* MAC */ + kAlgorithm_SSS_CMAC_AES = SSS_ENUM_ALGORITHM(MAC, 0x01), + kAlgorithm_SSS_HMAC_SHA1 = SSS_ENUM_ALGORITHM(MAC, 0x02), + kAlgorithm_SSS_HMAC_SHA224 = SSS_ENUM_ALGORITHM(MAC, 0x03), + kAlgorithm_SSS_HMAC_SHA256 = SSS_ENUM_ALGORITHM(MAC, 0x04), + kAlgorithm_SSS_HMAC_SHA384 = SSS_ENUM_ALGORITHM(MAC, 0x05), + kAlgorithm_SSS_HMAC_SHA512 = SSS_ENUM_ALGORITHM(MAC, 0x06), + /* See above: + * kAlgorithm_SSS_HMAC_SHA224 = SSS_ENUM_ALGORITHM(CHACHA, 0x01) */ + + /* Diffie-Helmann */ + kAlgorithm_SSS_DH = SSS_ENUM_ALGORITHM(DH, 0x01), + kAlgorithm_SSS_ECDH = SSS_ENUM_ALGORITHM(DH, 0x02), + /* DSA */ + kAlgorithm_SSS_DSA_SHA1 = SSS_ENUM_ALGORITHM(DSA, 0x01), + kAlgorithm_SSS_DSA_SHA224 = SSS_ENUM_ALGORITHM(DSA, 0x02), + kAlgorithm_SSS_DSA_SHA256 = SSS_ENUM_ALGORITHM(DSA, 0x03), + + /* RSA */ + /* doc:start rsa_sign_algo */ + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x01), + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x02), + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x03), + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x04), + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x05), + kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_V1_5, 0x06), + kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_PSS_MGF1, 0x01), + kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_PSS_MGF1, 0x02), + kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_PSS_MGF1, 0x03), + kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_PSS_MGF1, 0x04), + kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512 = SSS_ENUM_ALGORITHM(RSASSA_PKCS1_PSS_MGF1, 0x05), + /* doc:end rsa_sign_algo */ + + /* doc:start rsa_enc_algo */ + kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_OAEP, 0x01), + kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_OAEP, 0x02), + kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_OAEP, 0x03), + kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_OAEP, 0x04), + kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_OAEP, 0x05), + kAlgorithm_SSS_RSAES_PKCS1_V1_5 = SSS_ENUM_ALGORITHM(RSAES_PKCS1_V1_5, 0x01), + /* doc:end rsa_enc_algo */ + + /* doc:start rsa_sign_algo_no_padding */ + kAlgorithm_SSS_RSASSA_NO_PADDING = SSS_ENUM_ALGORITHM(RSASSA_NO_PADDING, 0x01), + /* doc:end rsa_sign_algo_no_padding */ + + /* ECDSA */ + /* doc:start ecc_sign_algo */ + kAlgorithm_SSS_ECDSA_SHA1 = SSS_ENUM_ALGORITHM(ECDSA, 0x01), + kAlgorithm_SSS_ECDSA_SHA224 = SSS_ENUM_ALGORITHM(ECDSA, 0x02), + kAlgorithm_SSS_ECDSA_SHA256 = SSS_ENUM_ALGORITHM(ECDSA, 0x03), + kAlgorithm_SSS_ECDSA_SHA384 = SSS_ENUM_ALGORITHM(ECDSA, 0x04), + kAlgorithm_SSS_ECDSA_SHA512 = SSS_ENUM_ALGORITHM(ECDSA, 0x05), + /* doc:end ecc_sign_algo */ + + /* ECDAA */ + /* doc:start ecc_bn_sign_algo */ + kAlgorithm_SSS_ECDAA = SSS_ENUM_ALGORITHM(ECDAA, 0x01), + /* doc:end ecc_bn_sign_algo */ +} sss_algorithm_t; + +#undef SSS_ENUM_ALGORITHM + +#ifndef __DOXYGEN__ + +// Deprecated names for RSAES_PKCS1_OAEP algorithms +#define kAlgorithm_SSS_RSASSA_PKCS1_OEAP_SHA1 kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1 +#define kAlgorithm_SSS_RSASSA_PKCS1_OEAP_SHA224 kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224 +#define kAlgorithm_SSS_RSASSA_PKCS1_OEAP_SHA256 kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256 +#define kAlgorithm_SSS_RSASSA_PKCS1_OEAP_SHA384 kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384 +#define kAlgorithm_SSS_RSASSA_PKCS1_OEAP_SHA512 kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512 + +// Deprecated names for RSAES_PKCS1_V1_5 algorithms +#define kAlgorithm_SSS_RSAES_PKCS1_V1_5_SHA1 kAlgorithm_SSS_RSAES_PKCS1_V1_5 +#define kAlgorithm_SSS_RSAES_PKCS1_V1_5_SHA224 kAlgorithm_SSS_RSAES_PKCS1_V1_5 +#define kAlgorithm_SSS_RSAES_PKCS1_V1_5_SHA256 kAlgorithm_SSS_RSAES_PKCS1_V1_5 +#define kAlgorithm_SSS_RSAES_PKCS1_V1_5_SHA384 kAlgorithm_SSS_RSAES_PKCS1_V1_5 +#define kAlgorithm_SSS_RSAES_PKCS1_V1_5_SHA512 kAlgorithm_SSS_RSAES_PKCS1_V1_5 + +#endif /* __DOXYGEN__ */ + +/** High level algorihtmic operations. + * + * Augmented by @ref sss_algorithm_t + */ +typedef enum +{ + kMode_SSS_Encrypt = 1, //!< Encrypt + kMode_SSS_Decrypt = 2, //!< Decrypt + kMode_SSS_Sign = 3, //!< Sign + kMode_SSS_Verify = 4, //!< Verify + /* Compute Shared Secret. e.g. Diffie-Hellman */ + kMode_SSS_ComputeSharedSecret = 5, + kMode_SSS_Digest = 6, //!< Message Digest + kMode_SSS_Mac = 7, //!< Message Authentication Code + + // For now, use kMode_SSS_ComputeSharedSecret for HKDF Extract and Expand + // kMode_SSS_HKDF = 8, //!< HKDF Extract and Expand (RFC 5869) + kMode_SSS_HKDF_ExpandOnly = 9 //!< HKDF Expand Only (RFC 5869) +} sss_mode_t; + +/** + * Permissions of an object + */ +typedef enum +{ + /** Can read (applicable) contents of the key. + * + * @note This is not same as @ref kAccessPermission_SSS_Use. + * + * Without reading, the object, the key can be used. + */ + kAccessPermission_SSS_Read = (1u << 0), + /** Can change the value of an object */ + kAccessPermission_SSS_Write = (1u << 1), + /** Can use an object */ + kAccessPermission_SSS_Use = (1u << 2), + /** Can delete an object */ + kAccessPermission_SSS_Delete = (1u << 3), + /** Can change permissions applicable to an object */ + kAccessPermission_SSS_ChangeAttributes = (1u << 4), + /** Bitwise OR of all sss_access_permission. */ + kAccessPermission_SSS_All_Permission = 0x1F, +} sss_access_permission_t; + +/** + * Persistent / Non persistent mode of a key + */ +typedef enum +{ + kKeyObject_Mode_None = 0, //!< kKeyObject_Mode_None + /** Key object will be persisted in memory + * and will retain it's value after a closed session + */ + kKeyObject_Mode_Persistent = 1, + /** Key Object will be stored in RAM. + * It will lose it's contents after a session is closed + */ + kKeyObject_Mode_Transient = 2, +} sss_key_object_mode_t; + +/** Part of a key */ +typedef enum +{ + kSSS_KeyPart_NONE, + /** Applicable where we have UserID, Binary Files, + * Certificates, Symmetric Keys, PCR, HMAC-key, counter */ + kSSS_KeyPart_Default = 1, + /** Public part of asymmetric key */ + kSSS_KeyPart_Public = 2, + /** Private only part of asymmetric key */ + kSSS_KeyPart_Private = 3, + /** Both, public and private part of asymmetric key */ + kSSS_KeyPart_Pair = 4, +} sss_key_part_t; + +/** For all cipher types, key bit length is provides at the time key is inserted/generated */ +typedef enum +{ + kSSS_CipherType_NONE, + kSSS_CipherType_AES = 10, + kSSS_CipherType_DES = 12, + + kSSS_CipherType_CMAC = 20, + kSSS_CipherType_HMAC = 21, + + kSSS_CipherType_MAC = 30, + kSSS_CipherType_RSA = 31, /*! RSA RAW format */ + kSSS_CipherType_RSA_CRT = 32, /*! RSA CRT format */ + + /* The following keys can be identified + * solely by the *Family* and bit length + */ + kSSS_CipherType_EC_NIST_P = 40, /*! Keys Part of NIST-P Family */ + kSSS_CipherType_EC_NIST_K = 41, /*! Keys Part of NIST-K Family */ + + /* The following keys need their full curve parameters (p,a,b,x,y,n,h) + */ + /** Montgomery Key, */ + kSSS_CipherType_EC_MONTGOMERY = 50, + /** twisted Edwards form elliptic curve public key */ + kSSS_CipherType_EC_TWISTED_ED = 51, + /** Brainpool form elliptic curve public key */ + kSSS_CipherType_EC_BRAINPOOL = 52, + /** Barreto Naehrig curve */ + kSSS_CipherType_EC_BARRETO_NAEHRIG = 53, + + kSSS_CipherType_UserID = 70, + + /** Use kSSS_CipherType_Binary to store Certificate */ + kSSS_CipherType_Certificate = 71, + kSSS_CipherType_Binary = 72, + + kSSS_CipherType_Count = 73, + kSSS_CipherType_PCR = 74, + kSSS_CipherType_ReservedPin = 75, +} sss_cipher_type_t; + +/** XY Co-ordinates for ECC Curves */ +typedef struct +{ + /** X Point */ + uint8_t *X; + /** Y Point */ + uint8_t *Y; +} sss_ecc_point_t; + +/** ECC Curve Parameter */ +typedef struct +{ + uint8_t *p; /**< ECC parameter P */ + uint8_t *a; /**< ECC parameter a */ + uint8_t *b; /**< ECC parameter b */ + sss_ecc_point_t *G; /**< ECC parameter G */ + uint8_t *n; /**< ECC parameter n */ + uint8_t *h; /**< ECC parameter h */ +} sss_eccgfp_group_t; + +/** + * @addtogroup sss_session + * @{ + */ + +/** Properties of session that are U32 + * + * From 0 to kSSS_SessionProp_Optional_Prop_Start, + * around 2^24 = 16777215 Properties are + * possible. + * + * From 0 to kSSS_SessionProp_Optional_Prop_Start, + * around 2^24 = 16777215 Properties are + * possible. + * + */ +typedef enum +{ + /** Invalid */ + kSSS_SessionProp_u32_NA = 0, + /** Major version */ + kSSS_SessionProp_VerMaj, + /** Minor Version */ + kSSS_SessionProp_VerMin, + /** Development Version */ + kSSS_SessionProp_VerDev, + + /* Lenght of UID */ + kSSS_SessionProp_UIDLen, + + /** Optional Properties Start */ + kSSS_SessionProp_u32_Optional_Start = 0x00FFFFFFu, + + /** How much persistent memory is free */ + kSSS_KeyStoreProp_FreeMem_Persistant, + + /** How much transient memory is free */ + kSSS_KeyStoreProp_FreeMem_Transient, + + /** Proprietary Properties Start */ + kSSS_SessionProp_u32_Proprietary_Start = 0x01FFFFFFu, + +} sss_session_prop_u32_t; + +/** Properties of session that are S32 + * + * From 0 to kSSS_SessionProp_Optional_Prop_Start, + * around 2^24 = 16777215 Properties are + * possible. + * + * From 0 to kSSS_SessionProp_Optional_Prop_Start, + * around 2^24 = 16777215 Properties are + * possible. + * + */ +typedef enum +{ + /** Invalid */ + kSSS_SessionProp_au8_NA = 0, + /** Name of the product, string */ + kSSS_SessionProp_szName, + /** Unique Identifier */ + kSSS_SessionProp_UID, + + /** Optional Properties Start */ + kSSS_SessionProp_au8_Optional_Start = 0x00FFFFFFu, + + /** Proprietary Properties Start */ + kSSS_SessionProp_au8_Proprietary_Start = 0x01FFFFFFu, + +} sss_session_prop_au8_t; + +/** @} */ + +/** + * @addtogroup sss_session + * @{ + */ + +/** @brief Root session + * + * This is a *singleton* for each connection (physical/logical) + * to individual cryptographic system. + */ +typedef struct +{ + /** Indicates which security subsystem is selected. + * + * This is set when @ref sss_session_open is successful */ + sss_type_t subsystem; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_SESSION_MAX_CONTEXT_SIZE]; + } extension; +} sss_session_t; +/** @} */ + +/** + * @addtogroup sss_key_store + * @{ + */ + +/** @brief Store for secure and non secure key objects within a cryptographic system. + * + * - A cryptographic system may have more than partitions to store such keys. + * + */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_session_t *session; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_KEY_STORE_MAX_CONTEXT_SIZE]; + } extension; +} sss_key_store_t; + +/** properties of a Key Store that return array */ +typedef enum +{ + /** Optional Properties Start */ + kSSS_KeyStoreProp_au8_Optional_Start = 0x00FFFFFFu, + +} sss_key_store_prop_au8_t; + +/** Entity on the other side of the tunnel */ +typedef enum +{ + /** Default value */ + kSSS_TunnelDest_None = 0, + + /** SE05X IoT Applet */ + kSSS_TunnelType_Se05x_Iot_applet, +} sss_tunnel_dest_t; + +/** @} */ + +/** + * @addtogroup sss_key_object + * @{ + */ + +/** @brief An object (secure / non-secure) within a Key Store. + * + */ +typedef struct +{ + /** key store holding the data and other properties */ + sss_key_store_t *keyStore; + /** The type/part of object is referneced from @ref sss_key_part_t */ + uint32_t objectType; + /** cipherType type from @ref sss_cipher_type_t */ + uint32_t cipherType; + /** Application specific key identifier. The keyId is kept in the key store + * along with the key data and other properties. */ + uint32_t keyId; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_KEY_OBJECT_MAX_CONTEXT_SIZE]; + } extension; +} sss_object_t; + +/** @} */ + +/** + * @addtogroup sss_crypto_symmetric + * @{ + */ + +/** @brief Typedef for the symmetric crypto context */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_session_t *session; + /** Key to be used for the symmetric operation */ + sss_object_t *keyObject; + /** Algorithm to be applied, e.g AES_ECB / CBC */ + sss_algorithm_t algorithm; + /** Mode of operation, e.g Encryption/Decryption */ + sss_mode_t mode; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_SYMMETRIC_MAX_CONTEXT_SIZE]; + } extension; +} sss_symmetric_t; +/** @} */ + +/** @brief Authenticated Encryption with Additional Data + * + */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_session_t *session; + /** Key to be used for asymmetric */ + sss_object_t *keyObject; + /** Algorithm to be used */ + sss_algorithm_t algorithm; + /** High level operation (encrypt/decrypt) */ + sss_mode_t mode; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_AEAD_MAX_CONTEXT_SIZE]; + } extension; +} sss_aead_t; + +/** Message Digest operations */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_session_t *session; + /** Algorithm to be applied, e.g SHA1, SHA256 */ + sss_algorithm_t algorithm; + /** Mode of operation, e.g Sign/Verify */ + sss_mode_t mode; + /** Full digest length per algorithm definition. This field is initialized along with algorithm. */ + size_t digestFullLen; + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_DIGEST_MAX_CONTEXT_SIZE]; + } extension; +} sss_digest_t; + +/** @brief Message Authentication Code + * + */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_session_t *session; + /** Key to be used for ... */ + sss_object_t *keyObject; + /** Algorithm to be applied, e.g. MAC/CMAC */ + sss_algorithm_t algorithm; + /** Mode of operation for MAC (kMode_SSS_Mac) */ + sss_mode_t mode; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_MAC_MAX_CONTEXT_SIZE]; + } extension; +} sss_mac_t; + +/** @brief Asymmetric Cryptographic operations + * + * e.g. RSA/ECC. + */ + +typedef struct +{ + /** Pointer to root session */ + sss_session_t *session; + /** KeyObject used for Asymmetric operation */ + sss_object_t *keyObject; + /** Algorithm to be applied, e.g. ECDSA */ + sss_algorithm_t algorithm; + /** Mode of operation for the Asymmetric operation. + * e.g. Sign/Verify/Encrypt/Decrypt */ + sss_mode_t mode; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_ASYMMETRIC_MAX_CONTEXT_SIZE]; + } extension; +} sss_asymmetric_t; + +/** Header for a IS716 APDU */ + +typedef struct +{ + /** ISO 7816 APDU Header */ + uint8_t hdr[0 /* For Indentation */ + + 1 /* CLA */ + + 1 /* INS */ + + 1 /* P1 */ + + 1 /* P2 */ + ]; +} tlvHeader_t; + +/** Tunneling + * + * Used for communication via another system. + */ +typedef struct +{ + /** Pointer to the session */ + sss_session_t *session; + /** Tunnel to which Applet (Currently unused) */ + uint32_t tunnelType; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_TUNNEL_MAX_CONTEXT_SIZE]; + } extension; +} sss_tunnel_t; + +/** + * @addtogroup sss_crypto_derive_key + * @{ + */ + +/** Key derivation */ +typedef struct +{ + /** Pointer to the session */ + sss_session_t *session; + /** KeyObject used to derive key s*/ + sss_object_t *keyObject; + /** Algorithm to be applied, e.g. ... */ + sss_algorithm_t algorithm; + /** Mode of operation for .... e.g. ... */ + sss_mode_t mode; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_DERIVE_KEY_MAX_CONTEXT_SIZE]; + } extension; +} sss_derive_key_t; +/** @} */ + +/** Random number generator context */ +typedef struct +{ + /** Pointer to the session */ + sss_session_t *session; + + /** Reserved memory for implementation specific extension */ + struct + { + uint8_t data[SSS_RNG_MAX_CONTEXT_SIZE]; + } context; + +} sss_rng_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup sss_session + * @{ + */ + +/** + * Same as @ref sss_session_open but to support sub systems + * that explictily need a create before opening. + * + * For the sake of portabilty across various sub systems, + * the applicaiton has to call @ref sss_session_create + * before calling @ref sss_session_open. + * + * + * @param[in,out] session Pointer to session context + * @param[in] subsystem See @ref sss_session_open + * @param[in] application_id See @ref sss_session_open + * @param[in] connection_type See @ref sss_session_open + * @param[in] connectionData See @ref sss_session_open + */ +sss_status_t sss_session_create(sss_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** + * @brief Open session between application and a security subsystem. + * + * Open virtual session between application (user context) and a + * security subsystem and function thereof. Pointer to session + * shall be supplied to all SSS APIs as argument. Low level SSS + * functions can provide implementation specific behaviour based + * on the session argument. + * Note: sss_session_open() must not be called concurrently from + * multiple threads. The application must ensure this. + * + * @param[in,out] session Session context. + * @param[in] subsystem Indicates which security subsystem is + * selected to be used. + * @param[in] application_id ObjectId/AuthenticationID Connecting to: + * - ``application_id`` == 0 => Super use / Plaform user + * - Anything else => Authenticated user + * @param[in] connection_type How are we connecting to the system. + * @param[in,out] connectionData subsystem specific connection parameters. + * + * @return status + */ +sss_status_t sss_session_open(sss_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** + * @brief Get an underlying property of the crypto sub system + * + * This API is used to get values that are + * numeric in nature. + * + * Property can be either fixed value that is + * calculated at compile time and returned + * directly, or it may involve some access to the + * underlying system. + * + * For applicable properties see @ref sss_session_prop_u32_t + * + * @param[in] session Session context + * @param[in] property Value that is part of @ref sss_session_prop_u32_t + * @param[out] pValue + * + * @return + */ +sss_status_t sss_session_prop_get_u32(sss_session_t *session, uint32_t property, uint32_t *pValue); + +/** + * @brief Get an underlying property of the crypto sub system + * + * This API is used to get values that are + * numeric in nature. + * + * Property can be either fixed value that is + * calculated at compile time and returned + * directly, or it may involve some access to the + * underlying system. + * + * @param[in] session Session context + * @param[in] property Value that is part of @ref sss_session_prop_au8_t + * @param[out] pValue Output buffer array + * @param[in,out] pValueLen Count of values thare are/must br read + * @return + */ +sss_status_t sss_session_prop_get_au8(sss_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** + * @brief Close session between application and security subsystem. + * + * This function closes a session which has been opened with a security subsystem. + * All commands within the session must have completed before this function can be called. + * The implementation must do nothing if the input ``session`` parameter is NULL. + * + * + * @param session Session context. + */ +void sss_session_close(sss_session_t *session); + +/** Counterpart to @ref sss_session_create + * + * Similar to contraint on @ref sss_session_create, application + * may call @ref sss_session_delete to explicitly release all + * underlying/used session specific resoures of that implementation. + */ +void sss_session_delete(sss_session_t *session); + +/** + *@} + */ /* end of sss_session */ + +/** + * @addtogroup sss_key_store + * @{ + */ + +/** @brief Constructor for the key store context data structure. + * + * @param[out] keyStore Pointer to key store context. Key store context is updated on function return. + * @param session Session context. + */ +sss_status_t sss_key_store_context_init(sss_key_store_t *keyStore, sss_session_t *session); + +/** @brief Get handle to key store. + * If the key store already exists, nothing is allocated. + * If the key store does not exists, new empty key store is created and initialized. + * Key store context structure is updated with actual information. + * + * @param[out] keyStore Pointer to key store context. Key store context is updated on function return. + * @param keyStoreId Implementation specific ID, can be used in case security subsystem manages multiple different + * key stores. + */ +sss_status_t sss_key_store_allocate(sss_key_store_t *keyStore, uint32_t keyStoreId); + +/** @brief Save all cached persistent objects to persistent memory. + */ +sss_status_t sss_key_store_save(sss_key_store_t *keyStore); + +/** @brief Load from persistent memory to cached objects. + */ +sss_status_t sss_key_store_load(sss_key_store_t *keyStore); + +/** @brief This function moves data[] from memory to the destination key store. + * + * @param keyStore Key store context + * @param keyObject Reference to a key and it's properties + * @param data Data to be stored in Key. When setting ecc private key only, do not include key header. + * @param dataLen Length of the data + * @param keyBitLen Crypto algorithm key bit length + * @param options Pointer to implementation specific options + * @param optionsLen Length of the options in bytes + * + * @return + */ +sss_status_t sss_key_store_set_key(sss_key_store_t *keyStore, + sss_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @brief This function generates key[] in the destination key store. */ +sss_status_t sss_key_store_generate_key( + sss_key_store_t *keyStore, sss_object_t *keyObject, size_t keyBitLen, void *options); + +/** @brief This function exports plain key[] from key store (if constraints and user id allows reading) */ +sss_status_t sss_key_store_get_key( + sss_key_store_t *keyStore, sss_object_t *keyObject, uint8_t *data, size_t *dataLen, size_t *pKeyBitLen); + +/** + * @brief Access key store using one more level of encryption + * + * e.g. Access keys / encryption key during storage + * + * @param keyStore The key store + * @param keyObject The key object that is to be used as a KEK (Key Encryption Key) + * + * @return The sss status. + */ +sss_status_t sss_key_store_open_key(sss_key_store_t *keyStore, sss_object_t *keyObject); + +/** + * @brief The referenced key cannot be updated any more. + * + * @param keyStore The key store + * @param keyObject The key object to be locked / frozen. + * + * @return The sss status. + */ +sss_status_t sss_key_store_freeze_key(sss_key_store_t *keyStore, sss_object_t *keyObject); + +/** + * @brief Delete / destroy allocated keyObect . + * + * @param keyStore The key store + * @param keyObject The key object to be deleted + * + * @return The sss status. + */ +sss_status_t sss_key_store_erase_key(sss_key_store_t *keyStore, sss_object_t *keyObject); + +// sss_status_t sss_key_store_clear_all(sss_key_store_t *keyStore); + +/** @brief Destructor for the key store context. */ +void sss_key_store_context_free(sss_key_store_t *keyStore); + +/** + *@} + */ /* end of sss_key_store */ + +/** + * @addtogroup sss_key_object + * @{ + */ + +/** @brief Constructor for a key object data structure + * The function initializes keyObject data structure and associates it with a key store + * in which the plain key and other attributes are stored. + * + * @param keyObject + * @param keyStore + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_key_object_init(sss_object_t *keyObject, sss_key_store_t *keyStore); + +/** + * @brief Allocate / pre-provision memory for new key + * + * This API allows underlying cryptographic subsystems to perform + * preconditions of before creating any cryptographic key object. + * + * @param[in,out] keyObject The object If required, update implementation + * defined values inside the keyObject + * @param keyId External Key ID. Later on this may be used by + * @ref sss_key_object_get_handle + * @param keyPart See @ref sss_key_part_t + * @param cipherType See @ref sss_cipher_type_t + * @param keyByteLenMax Maximum storage this type of key may need. For + * systems that have their own internal allocation + * table this would help + * @param options 0 = Persistant Key (Default) or Transient Key. + * See sss_key_object_mode_t + * + * @return Status of object allocation. + */ +sss_status_t sss_key_object_allocate_handle(sss_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); /* Check if this can be made sss_key_object_mode_t */ + +/** + * @brief Get handle to an existing allocated/provisioned/created Object + * + * See @ref sss_key_object_allocate_handle. + * + * After calling this API, Ideally keyObject should become equivlant + * to as set after the calling of @ref + * sss_key_object_allocate_handle api. + * + * @param keyObject The key object + * @param[in] keyId The key identifier + * + * @return The sss status. + */ +sss_status_t sss_key_object_get_handle(sss_object_t *keyObject, uint32_t keyId); + +/** @brief Assign user to a key object. + * + * @param keyObject the object where permission restrictions are applied + * + * @param user Assign User id for a key object. The user is kept in the key + * store along with the key data and other properties. + * @param options Transient or persistent update. Allows for transient update + * of persistent attributes. + */ +sss_status_t sss_key_object_set_user(sss_object_t *keyObject, uint32_t user, uint32_t options); + +/** @brief Assign purpose to a key object. + * + * @param keyObject the object where permission restrictions are applied + * @param purpose Usage of the key. + * @param options Transient or persistent update. Allows for transient update of persistent attributes. + */ +sss_status_t sss_key_object_set_purpose(sss_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** @brief Assign access permissions to a key object. + * + * @param keyObject the object where permission restrictions are applied + * @param access Logical OR of read, write, delete, use, change attributes defined by enum _sss_access_permission. + * @param options Transient or persistent update. Allows for transient update of persistent attributes. + */ +sss_status_t sss_key_object_set_access(sss_object_t *keyObject, uint32_t access, uint32_t options); + +/** @brief Set elliptic curve domain parameters over Fp for a key object + * + * When the key object is a reference to one of ECC Private, ECC Public or ECC Pair key types, + * this function shall be used to specify the exact domain parameters prior to using the key object + * for ECDSA or ECDH algorithms. + * + * @param keyObject The destination key object + * @param group Pointer to elliptic curve domain parameters over Fp (sextuple p,a,b,G,n,h) + */ +sss_status_t sss_key_object_set_eccgfp_group(sss_object_t *keyObject, sss_eccgfp_group_t *group); + +/** @brief get attributes */ +sss_status_t sss_key_object_get_user(sss_object_t *keyObject, uint32_t *user); + +/** Check what is purpose restrictions on an object + * + * @param keyObject Object to be checked + * @param purpose Know what is permitted. + * @return + */ +sss_status_t sss_key_object_get_purpose(sss_object_t *keyObject, sss_mode_t *purpose); + +/** Check what are access restrictions on an object + * + * @param keyObject Object + * @param access What is permitted + * @return + */ +sss_status_t sss_key_object_get_access(sss_object_t *keyObject, uint32_t *access); + +/** @brief Destructor for the key object. + * The function frees key object context. + * + * @param keyObject Pointer to key object context. + */ +void sss_key_object_free(sss_object_t *keyObject); + +/** + *@} + */ /* end of sss_key_object */ + +/** + * @addtogroup sss_crypto_symmetric + * @{ + */ + +/** @brief Symmetric context init. + * The function initializes symmetric context with initial values. + * + * @param context Pointer to symmetric crypto context. + * @param session Associate SSS session with symmetric context. + * @param keyObject Associate SSS key object with symmetric context. + * @param algorithm One of the symmetric algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_symmetric_context_init(sss_symmetric_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @brief Symmetric cipher in one blocking function call. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to symmetric crypto context. + * @param iv Buffer containing the symmetric operation Initialization Vector. + * @param ivLen Length of the Initialization Vector in bytes. + * @param srcData Buffer containing the input data (block aligned). + * @param destData Buffer containing the output data. + * @param dataLen Size of input and output data buffer in bytes. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_cipher_one_go( + sss_symmetric_t *context, uint8_t *iv, size_t ivLen, const uint8_t *srcData, uint8_t *destData, size_t dataLen); + +/** @brief Symmetric cipher init. + * The function starts the symmetric cipher operation. + * + * @param context Pointer to symmetric crypto context. + * @param iv Buffer containing the symmetric operation Initialization Vector. + * @param ivLen Length of the Initialization Vector in bytes. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_cipher_init(sss_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @brief Symmetric cipher update. + * Input data does not have to be a multiple of block size. Subsequent calls to this function are possible. + * Unless one or more calls of this function have supplied sufficient input data, no output is generated. + * The cipher operation is finalized with a call to @ref sss_cipher_finish(). + * + * @param context Pointer to symmetric crypto context. + * @param srcData Buffer containing the input data. + * @param srcLen Length of the input data in bytes. + * @param destData Buffer containing the output data. + * @param[in,out] destLen Length of the output data in bytes. Buffer length on entry, reflects actual output size on + * return. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_cipher_update( + sss_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @brief Symmetric cipher finalize. + * + * @param context Pointer to symmetric crypto context. + * @param srcData Buffer containing final chunk of input data. + * @param srcLen Length of final chunk of input data in bytes. + * @param destData Buffer containing output data. + * @param[in,out] destLen Length of output data in bytes. Buffer length on entry, reflects actual output size on + * return. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_cipher_finish( + sss_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @brief Symmetric AES in Counter mode in one blocking function call. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to symmetric crypto context. + * @param srcData Buffer containing the input data. + * @param destData Buffer containing the output data. + * @param size Size of source and destination data buffers in bytes. + * @param[in,out] initialCounter Input counter (updates on return) + * @param[out] lastEncryptedCounter Output cipher of last counter, for chained CTR calls. NULL can be passed if + * chained calls are not used. + * @param[out] szLeft Output number of bytes in left unused in lastEncryptedCounter block. NULL can be passed if + * chained calls are not used. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_cipher_crypt_ctr(sss_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @brief Symmetric context release. + * The function frees symmetric context. + * + * @param context Pointer to symmetric crypto context. + */ +void sss_symmetric_context_free(sss_symmetric_t *context); +/** + *@} + */ /* end of sss_crypto_symmetric */ + +/** + * @addtogroup sss_crypto_aead + * @{ + */ + +/** @brief AEAD context init. + * The function initializes aead context with initial values. + * + * @param context Pointer to aead crypto context. + * @param session Associate SSS session with aead context. + * @param keyObject Associate SSS key object with aead context. + * @param algorithm One of the aead algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_aead_context_init( + sss_aead_t *context, sss_session_t *session, sss_object_t *keyObject, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @brief AEAD in one blocking function call. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to aead crypto context. + * @param srcData Buffer containing the input data. + * @param destData Buffer containing the output data. + * @param size Size of input and output data buffer in bytes. + * @param nonce The operation nonce or IV. + * @param nonceLen The length of nonce in bytes. For AES-GCM it must be >= 1. For AES-CCM it must be 7, 8, 9, 10, + * 11, 12, or 13. + * @param aad Input additional authentication data AAD + * @param aadLen Input size in bytes of AAD + * @param tag Encryption: Output buffer filled with computed tag + * Decryption: Input buffer filled with received tag + * @param tagLen Length of the tag in bytes. + * For AES-GCM it must be 4,8,12,13,14,15 or 16. + * For AES-CCM it must be 4,6,8,10,12,14 or 16. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_aead_one_go(sss_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +/** @brief AEAD init. + * The function starts the aead operation. + * + * @param context Pointer to aead crypto context. + * @param nonce The operation nonce or IV. + * @param nonceLen The length of nonce in bytes. For AES-GCM it must be >= 1. For AES-CCM it must be 7, 8, 9, 10, + * 11, 12, or 13. + * @param tagLen Length of the computed or received tag in bytes. + * For AES-GCM it must be 4,8,12,13,14,15 or 16. + * For AES-CCM it must be 4,6,8,10,12,14 or 16. + * @param aadLen Input size in bytes of AAD. Used only for AES-CCM. Ignored for AES-GCM. + * @param payloadLen Length in bytes of the payload. Used only for AES-CCM. Ignored for AES-GCM. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_aead_init( + sss_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); + +/** @brief Feeds a new chunk of the AAD. + * Subsequent calls of this function are possible. + * + * @param context Pointer to aead crypto context + * @param aadData Input buffer containing the chunk of AAD + * @param aadDataLen Length of the AAD data in bytes. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_aead_update_aad(sss_aead_t *context, const uint8_t *aadData, size_t aadDataLen); + +/** @brief AEAD data update. + * Feeds a new chunk of the data payload. + * Input data does not have to be a multiple of block size. Subsequent calls to this function are possible. + * Unless one or more calls of this function have supplied sufficient input data, no output is generated. + * The integration check is done by @ref sss_aead_finish(). Until then it is not sure if the decrypt data is + * authentic. + * + * @param context Pointer to aead crypto context. + * @param srcData Buffer containing the input data. + * @param srcLen Length of the input data in bytes. + * @param destData Buffer containing the output data. + * @param[in,out] destLen Length of the output data in bytes. Buffer length on entry, reflects actual output size on + * return. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_aead_update( + sss_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @brief Finalize AEAD. + * The functions processes data that has not been processed by previous calls to sss_aead_update() as well as + * srcData. It finalizes the AEAD operations and computes the tag (encryption) or compares the computed tag with the + * tag supplied in the parameter (decryption). + * + * @param context Pointer to aead crypto context. + * @param srcData Buffer containing final chunk of input data. + * @param srcLen Length of final chunk of input data in bytes. + * @param destData Buffer containing output data. + * @param[in,out] destLen Length of output data in bytes. Buffer length on entry, reflects actual output size on + * return. + * @param tag Encryption: Output buffer filled with computed tag + * Decryption: Input buffer filled with received tag + * @param tagLen Length of the computed or received tag in bytes. + * For AES-GCM it must be 4,8,12,13,14,15 or 16. + * For AES-CCM it must be 4,6,8,10,12,14 or 16. + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_aead_finish(sss_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); + +/** @brief AEAD context release. + * The function frees aead context. + * + * @param context Pointer to aead context. + */ +void sss_aead_context_free(sss_aead_t *context); +/** + *@} + */ /* end of sss_crypto_aead */ + +/** + * @addtogroup sss_crypto_digest + * @{ + */ + +/** @brief Digest context init. + * The function initializes digest context with initial values. + * + * @param context Pointer to digest context. + * @param session Associate SSS session with digest context. + * @param algorithm One of the digest algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_digest_context_init( + sss_digest_t *context, sss_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @brief Message digest in one blocking function call. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to digest context. + * @param message Input message + * @param messageLen Length of the input message in bytes + * @param digest Output message digest + * @param digestLen Message digest byte length + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_digest_one_go( + sss_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @brief Init digest for a message. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to digest context. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_digest_init(sss_digest_t *context); + +/** @brief Update digest for a message. + * + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to digest context. + * @param message Buffer with a message chunk. + * @param messageLen Length of the input buffer in bytes. + * @returns Status of the operation + * + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_digest_update(sss_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @brief Finish digest for a message. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to digest context. + * @param digest Output message digest + * @param digestLen Message digest byte length + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_digest_finish(sss_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @brief Digest context release. + * The function frees digest context. + * + * @param context Pointer to digest context. + */ +void sss_digest_context_free(sss_digest_t *context); + +/** + *@} + */ /* end of sss_crypto_digest */ + +/** + * @addtogroup sss_crypto_mac + * @{ + */ + +/** @brief MAC context init. + * The function initializes mac context with initial values. + * + * @param context Pointer to mac context. + * @param session Associate SSS session with mac context. + * @param keyObject Associate SSS key object with mac context. + * @param algorithm One of the mac algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_mac_context_init( + sss_mac_t *context, sss_session_t *session, sss_object_t *keyObject, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @brief Message MAC in one blocking function call. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to mac context. + * @param message Input message + * @param messageLen Length of the input message in bytes + * @param mac Output message MAC + * @param macLen Computed MAC byte length + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_mac_one_go( + sss_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @brief Init mac for a message. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to mac context. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_mac_init(sss_mac_t *context); + +/** @brief Update mac for a message. + * + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to mac context. + * @param message Buffer with a message chunk. + * @param messageLen Length of the input buffer in bytes. + * @returns Status of the operation + * + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_mac_update(sss_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @brief Finish mac for a message. + * The function blocks current thread until the operation completes or an error occurs. + * + * @param context Pointer to mac context. + * @param mac Output message MAC + * @param macLen Computed MAC byte length + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + */ +sss_status_t sss_mac_finish(sss_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @brief MAC context release. + * The function frees mac context. + * + * @param context Pointer to mac context. + */ +void sss_mac_context_free(sss_mac_t *context); +/** + *@} + */ /* end of sss_crypto_mac */ + +/** + * @addtogroup sss_crypto_asymmetric + * @{ + */ + +/** @brief Asymmetric context init. + * The function initializes asymmetric context with initial values. + * + * @param context Pointer to asymmetric crypto context. + * @param session Associate SSS session with asymmetric context. + * @param keyObject Associate SSS key object with asymmetric context. + * @param algorithm One of the asymmetric algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_asymmetric_context_init(sss_asymmetric_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @brief Asymmetric encryption + * The function uses asymmetric algorithm to encrypt data. Public key portion of a key pair is used for encryption. + * + * @param context Pointer to asymmetric context. + * @param srcData Input buffer + * @param srcLen Length of the input in bytes + * @param destData Output buffer + * @param destLen Length of the output in bytes + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_asymmetric_encrypt( + sss_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @brief Asymmetric decryption + * The function uses asymmetric algorithm to decrypt data. Private key portion of a key pair is used for + * decryption. + * + * @param context Pointer to asymmetric context. + * @param srcData Input buffer + * @param srcLen Length of the input in bytes + * @param destData Output buffer + * @param destLen Length of the output in bytes + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_asymmetric_decrypt( + sss_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @brief Asymmetric signature of a message digest + * The function signs a message digest. + * + * @param context Pointer to asymmetric context. + * @param digest Input buffer containing the input message digest + * @param digestLen Length of the digest in bytes + * @param signature Output buffer written with the signature of the digest + * @param signatureLen Length of the signature in bytes + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_asymmetric_sign_digest( + sss_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @brief Asymmetric verify of a message digest + * The function verifies a message digest. + * + * @param context Pointer to asymmetric context. + * @param digest Input buffer containing the input message digest + * @param digestLen Length of the digest in bytes + * @param signature Input buffer containing the signature to verify + * @param signatureLen Length of the signature in bytes + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_asymmetric_verify_digest( + sss_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @brief Asymmetric context release. + * The function frees asymmetric context. + * + * @param context Pointer to asymmetric context. + */ +void sss_asymmetric_context_free(sss_asymmetric_t *context); +/** + *@} + */ /* end of sss_crypto_asymmetric */ + +/** + * @addtogroup sss_crypto_derive_key + * @{ + */ + +/** @brief Derive key context init. + * The function initializes derive key context with initial values. + * + * @param context Pointer to derive key context. + * @param session Associate SSS session with the derive key context. + * @param keyObject Associate SSS key object with the derive key context. + * @param algorithm One of the derive key algorithms defined by @ref sss_algorithm_t. + * @param mode One of the modes defined by @ref sss_mode_t. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_derive_key_context_init(sss_derive_key_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @brief Symmetric key derivation + * The function cryptographically derives a key from another key. + * For example MIFARE key derivation, PRF, HKDF-Extract. + * + * @deprecated Please use ::sss_derive_key_one_go instead + * + * @param context Pointer to derive key context. + * @param saltData Input data buffer, typically with some random data. + * @param saltLen Length of saltData buffer in bytes. + * @param info Input data buffer, typically with some fixed info. + * @param infoLen Length of info buffer in bytes. + * @param[in,out] derivedKeyObject Reference to a derived key + * @param deriveDataLen Requested length of output + * @param hkdfOutput Output buffer containing key derivation output + * @param hkdfOutputLen Output containing length of hkdfOutput + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_derive_key_go(sss_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @brief Symmetric key derivation (replaces the deprecated function ::sss_derive_key_go) + * The function cryptographically derives a key from another key. + * For example MIFARE key derivation, PRF, HKDF-Extract-Expand, HKDF-Expand. + * Refer to ::sss_derive_key_sobj_one_go in case the Salt is available as a key object. + * + * @param context Pointer to derive key context. + * @param saltData Input data buffer, typically with some random data. + * @param saltLen Length of saltData buffer in bytes. + * @param info Input data buffer, typically with some fixed info. + * @param infoLen Length of info buffer in bytes. + * @param[in,out] derivedKeyObject Reference to a derived key + * @param[in] deriveDataLen Expected length of derived key. + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_derive_key_one_go(sss_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** + * @brief Symmetric key derivation (salt in key object) + * Refer to ::sss_derive_key_one_go in case the salt is not available as a key object. + * + * @param context Pointer to derive key context + * @param saltKeyObject Reference to salt. The salt key object must reside in the same keystore as the derive key context. + * @param[in] info Input data buffer, typically with some fixed info. + * @param[in] infoLen Length of info buffer in bytes. + * @param derivedKeyObject Reference to a derived key + * @param[in] deriveDataLen The derive data length + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_derive_key_sobj_one_go(sss_derive_key_t *context, + sss_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @brief Asymmetric key derivation Diffie-Helmann + * The function cryptographically derives a key from another key. + * For example Diffie-Helmann. + * + * @param context Pointer to derive key context. + * @param otherPartyKeyObject Public key of the other party in the Diffie-Helmann algorithm + * @param[in,out] derivedKeyObject Reference to a derived key + * + * @returns Status of the operation + * @retval #kStatus_SSS_Success The operation has completed successfully. + * @retval #kStatus_SSS_Fail The operation has failed. + * @retval #kStatus_SSS_InvalidArgument One of the arguments is invalid for the function to execute. + */ +sss_status_t sss_derive_key_dh( + sss_derive_key_t *context, sss_object_t *otherPartyKeyObject, sss_object_t *derivedKeyObject); + +/** @brief Derive key context release. + * The function frees derive key context. + * + * @param context Pointer to derive key context. + */ +void sss_derive_key_context_free(sss_derive_key_t *context); +/** + *@} + */ /* end of sss_crypto_derive_key */ + +/** + * @addtogroup sss_rng + * @{ + */ + +/** + * @brief Initialise random generator context between application and a security subsystem. + * + * + * @warning API Changed + * + * Earlier: + * sss_status_t sss_rng_context_init( + * sss_session_t *session, sss_rng_context_t *context); + * + * Now: Parameters are swapped + * sss_status_t sss_rng_context_init( + * sss_rng_context_t *context, sss_session_t *session); + * + * @param session Session context. + * @param context random generator context. + * @return status + */ +sss_status_t sss_rng_context_init(sss_rng_context_t *context, sss_session_t *session); + +/** + * @brief Generate random number. + * + * @param context random generator context. + * @param random_data buffer to hold random data. + * @param dataLen required random number length + * @return status + */ +sss_status_t sss_rng_get_random(sss_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** + * @brief free random genertor context. + * + * @param context generator context. + * @return status + */ +sss_status_t sss_rng_context_free(sss_rng_context_t *context); + +/** + *@} + */ /* end of sss_rng */ + +/** + * @addtogroup sss_crypto_tunnel + * @{ + */ + +/** @brief Constructor for the tunnelling service context. + * + * Earlier: + * sss_status_t sss_tunnel_context_init( + * sss_session_t *session, sss_tunnel_t *context); + * + * Now: Parameters are swapped + * sss_status_t sss_tunnel_context_init( + * sss_tunnel_t *context, sss_session_t *session); + * + * @param[out] context Pointer to tunnel context. Tunnel context is updated on function return. + * @param session Pointer to session this tunnelling service belongs to. + */ +sss_status_t sss_tunnel_context_init(sss_tunnel_t *context, sss_session_t *session); + +/** @brief Tunnelling service. + * + * @param[in,out] context Pointer to tunnel context. + * @param data Pointer to data to be send to subsystem. + * @param dataLen Length of the data in bytes. + * @param keyObjects Objects references used by the service. + * @param keyObjectCount Number of key references at ``keyObjects``. + * @param tunnelType Implementation specific id of the service. + */ +sss_status_t sss_tunnel(sss_tunnel_t *context, + uint8_t *data, + size_t dataLen, + sss_object_t *keyObjects, + uint32_t keyObjectCount, + uint32_t tunnelType); + +/** @brief Destructor for the tunnelling service context. + * + * @param[out] context Pointer to tunnel context. */ +void sss_tunnel_context_free(sss_tunnel_t *context); + +/** + *@} + */ /* end of sss_crypto_channel */ + +/** + * @addtogroup sss_str_log + * @{ + */ + +/** + * @brief Returns string error code for @ref sss_status_t + * + * @param[in] status See @ref sss_status_t + * + * @return String conversion of ``status`` to String. + */ + +const char *sss_status_sz(sss_status_t status); + +/** +* @brief Returns string error code for @ref sss_cipher_type_t +* +* @param[in] status See @ref sss_cipher_type_t +* +* @return String conversion of ``cipher_type`` to String. +*/ + +const char *sss_cipher_type_sz(sss_cipher_type_t cipher_type); + +/** + *@} + */ /* end of sss_str_log */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_SSS_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h new file mode 100644 index 00000000000..cdc223d1cf8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h @@ -0,0 +1,64 @@ +/* Copyright 2019-2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * + */ + +#ifndef SSS_APIS_VERSION_INFO_H_INCLUDED +#define SSS_APIS_VERSION_INFO_H_INCLUDED + + +/* clang-format off */ +#define SSS_APIS_PROD_NAME "SSS_APIs" +#define SSS_APIS_VER_STRING_NUM "v03.06.00_20210528" +#define SSS_APIS_PROD_NAME_VER_FULL "SSS_APIs_v03.06.00_20210528" +#define SSS_APIS_VER_MAJOR (3u) +#define SSS_APIS_VER_MINOR (6u) +#define SSS_APIS_VER_DEV (0u) + +/* v03.06 = 30006u */ +#define SSS_APIS_VER_MAJOR_MINOR ( 0 \ + | (SSS_APIS_VER_MAJOR * 10000u) \ + | (SSS_APIS_VER_MINOR)) + +/* v03.06.00 = 300060000ULL */ +#define SSS_APIS_VER_MAJOR_MINOR_DEV ( 0 \ + | (SSS_APIS_VER_MAJOR * 10000*10000u) \ + | (SSS_APIS_VER_MINOR * 10000u) \ + | (SSS_APIS_VER_DEV)) + +/* clang-format on */ + + +/* Version Information: + * Generated by: + * scripts\version_info.py (v2019.01.17_00) + * + * Do not edit this file. Update: + * sss/version_info.txt instead. + * + * prod_name = "SSS_APIs" + * + * prod_desc = "SSS APIs" + * + * lang_c_prefix = prod_name.upper() + * + * lang_namespace = "" + * + * v_major = "03" + * + * v_minor = "06" + * + * v_dev = "00" + * + * v_meta = "" + * + * maturity = "B" + * + * # + * # 03.00.00 : Changed Enums + * # + */ + +#endif /* SSS_APIS_VERSION_INFO_H_INCLUDED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h new file mode 100644 index 00000000000..6d2b9c36324 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h @@ -0,0 +1,84 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _FSL_SSS_CONFIG_H_ +#define _FSL_SSS_CONFIG_H_ + +/* clang-format off */ +#define SSS_SESSION_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (1 * sizeof(void *)) \ + + (8 * sizeof(void *)) \ + + 16) +#define SSS_KEY_STORE_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (4 * sizeof(void *)) \ + + 16) +#define SSS_KEY_OBJECT_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (2 * sizeof(int)) \ + + (4 * sizeof(void *)) \ + + 16) +#define SSS_SYMMETRIC_MAX_CONTEXT_SIZE ( 0 \ + + (2 * sizeof(void *)) \ + + (2 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 16 /* Buffer in case of unaligned block cipher operations */ \ + + 4 /* Buffer length in case of unaligned block cipher operations */ \ + + 16) +#define SSS_AEAD_MAX_CONTEXT_SIZE ( 0 \ + + (5 * sizeof(void *)) \ + + (6 * sizeof(int)) \ + + (5 * sizeof(void *)) \ + + 16) +#define SSS_DIGEST_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (3 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 16) +#define SSS_MAC_MAX_CONTEXT_SIZE ( 0 \ + + (2 * sizeof(void *)) \ + + (2 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 32) +#define SSS_ASYMMETRIC_MAX_CONTEXT_SIZE ( 0 \ + + (2 * sizeof(void *)) \ + + (3 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 16) +#define SSS_TUNNEL_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (2 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 16) +#define SSS_CHANNEL_MAX_CONTEXT_SIZE ( 0 \ + + (2 * sizeof(void *)) \ + + 16) +#define SSS_DERIVE_KEY_MAX_CONTEXT_SIZE ( 0 \ + + (2 * sizeof(void *)) \ + + (2 * sizeof(int)) \ + + (2 * sizeof(void *)) \ + + 16) +#define SSS_RNG_MAX_CONTEXT_SIZE ( 0 \ + + (1 * sizeof(void *)) \ + + (2 * sizeof(void *)) \ + + 16) + +#define SSS_CONNECT_MAX_CONTEXT_SIZE ( 0 \ + + (4 * sizeof(void *)) \ + + 8 \ + ) + +#define SSS_AUTH_MAX_CONTEXT_SIZE ( 0 \ + + (3 * sizeof(void *)) \ + + 8 \ + ) + +#define SSS_POLICY_COUNT_MAX (10) + +/* clang-format on */ + +#endif /* _FSL_SSS_CONFIG_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h new file mode 100644 index 00000000000..7ad9a873d25 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h @@ -0,0 +1,673 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_FTR_H_ +#define SSS_APIS_INC_FSL_SSS_FTR_H_ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* clang-format off */ + + +/* # CMake Features : Start */ + + +/** Applet : The Secure Element Applet + * + * You can compile host library for different Applets listed below. + * Please note, some of these Applets may be for NXP Internal use only. + */ + +/** Compiling without any Applet Support */ +#define SSS_HAVE_APPLET_NONE 0 + +/** A71CH (ECC) */ +#define SSS_HAVE_APPLET_A71CH 0 + +/** A71CL (RSA) */ +#define SSS_HAVE_APPLET_A71CL 0 + +/** Similar to A71CH */ +#define SSS_HAVE_APPLET_A71CH_SIM 0 + +/** SE050 Type A (ECC) */ +#define SSS_HAVE_APPLET_SE05X_A 0 + +/** SE050 Type B (RSA) */ +#define SSS_HAVE_APPLET_SE05X_B 0 + +/** SE050 (Super set of A + B) */ +#define SSS_HAVE_APPLET_SE05X_C 1 + +/** SE050 (Similar to A71CL) */ +#define SSS_HAVE_APPLET_SE05X_L 0 + +/** NXP Internal testing Applet */ +#define SSS_HAVE_APPLET_LOOPBACK 0 + +#if (( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) > 1) +# error "Enable only one of 'Applet'" +#endif + + +#if (( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) == 0) +# error "Enable at-least one of 'Applet'" +#endif + + + +/** SE05X_Ver : SE05X Applet version. + * + * Selection of Applet version 03_XX enables SE050 features. + * Selection of Applet version 06_00 enables SE051 features. + * + */ + +/** SE050 */ +#define SSS_HAVE_SE05X_VER_03_XX 1 + +/** SE051 */ +#define SSS_HAVE_SE05X_VER_06_00 0 + +#if (( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) > 1) +# error "Enable only one of 'SE05X_Ver'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) == 0) +# error "Enable at-least one of 'SE05X_Ver'" +#endif + + + +/** HostCrypto : Counterpart Crypto on Host + * + * What is being used as a cryptographic library on the host. + * As of now only OpenSSL / mbedTLS is supported + */ + +/** Use mbedTLS as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_MBEDTLS 1 + +/** Use mbed-crypto as host crypto + * Required for ARM-PSA / TF-M */ +#define SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO 0 + +/** Use OpenSSL as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_OPENSSL 0 + +/** User Implementation of Host Crypto + * e.g. Files at ``sss/src/user/crypto`` have low level AES/CMAC primitives. + * The files at ``sss/src/user`` use those primitives. + * This becomes an example for users with their own AES Implementation + * This then becomes integration without mbedTLS/OpenSSL for SCP03 / AESKey. + * + * .. note:: ECKey abstraction is not implemented/available yet. */ +#define SSS_HAVE_HOSTCRYPTO_USER 0 + +/** NO Host Crypto + * Note, this is unsecure and only provided for experimentation + * on platforms that do not have an mbedTLS PORT + * Many :ref:`sssftr-control` have to be disabled to have a valid build. */ +#define SSS_HAVE_HOSTCRYPTO_NONE 0 + +#if (( 0 \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_USER \ + + SSS_HAVE_HOSTCRYPTO_NONE \ + ) > 1) +# error "Enable only one of 'HostCrypto'" +#endif + + +#if (( 0 \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_USER \ + + SSS_HAVE_HOSTCRYPTO_NONE \ + ) == 0) +# error "Enable at-least one of 'HostCrypto'" +#endif + + + +/** mbedTLS_ALT : ALT Engine implementation for mbedTLS + * + * When set to None, mbedTLS would not use ALT Implementation to connect to / use Secure Element. + * This needs to be set to SSS for Cloud Demos over SSS APIs + */ + +/** Use SSS Layer ALT implementation */ +#define SSS_HAVE_MBEDTLS_ALT_SSS 0 + +/** Legacy implementation */ +#define SSS_HAVE_MBEDTLS_ALT_A71CH 0 + +/** Not using any mbedTLS_ALT + * + * When this is selected, cloud demos can not work with mbedTLS */ +#define SSS_HAVE_MBEDTLS_ALT_NONE 1 + +#if (( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) > 1) +# error "Enable only one of 'mbedTLS_ALT'" +#endif + + +#if (( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) == 0) +# error "Enable at-least one of 'mbedTLS_ALT'" +#endif + + + +/** SCP : Secure Channel Protocol + * + * In case we enable secure channel to Secure Element, which interface to be used. + */ + +/** */ +#define SSS_HAVE_SCP_NONE 0 + +/** Use SSS Layer for SCP. Used for SE050 family. */ +#define SSS_HAVE_SCP_SCP03_SSS 1 + +/** Use Host Crypto Layer for SCP03. Legacy implementation. Used for older demos of A71CH Family. */ +#define SSS_HAVE_SCP_SCP03_HOSTCRYPTO 0 + +#if (( 0 \ + + SSS_HAVE_SCP_NONE \ + + SSS_HAVE_SCP_SCP03_SSS \ + + SSS_HAVE_SCP_SCP03_HOSTCRYPTO \ + ) > 1) +# error "Enable only one of 'SCP'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SCP_NONE \ + + SSS_HAVE_SCP_SCP03_SSS \ + + SSS_HAVE_SCP_SCP03_HOSTCRYPTO \ + ) == 0) +# error "Enable at-least one of 'SCP'" +#endif + + + +/** FIPS : Enable or disable FIPS + * + * This selection mostly impacts tests, and generally not the actual Middleware + */ + +/** NO FIPS */ +#define SSS_HAVE_FIPS_NONE 1 + +/** SE050 IC FIPS */ +#define SSS_HAVE_FIPS_SE050 0 + +/** FIPS 140-2 */ +#define SSS_HAVE_FIPS_140_2 0 + +/** FIPS 140-3 */ +#define SSS_HAVE_FIPS_140_3 0 + +#if (( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) > 1) +# error "Enable only one of 'FIPS'" +#endif + + +#if (( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) == 0) +# error "Enable at-least one of 'FIPS'" +#endif + + + +/** SBL : Enable/Disable SBL Bootable support + * + * This option is to enable/disable boot from SBL by switching linker address + */ + +/** Not SBL bootable */ +#define SSS_HAVE_SBL_NONE 1 + +/** SE050 based LPC55S SBL bootable */ +#define SSS_HAVE_SBL_SBL_LPC55S 0 + +#if (( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) > 1) +# error "Enable only one of 'SBL'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) == 0) +# error "Enable at-least one of 'SBL'" +#endif + + + +/** SE05X_Auth : SE050 Authentication + * + * This settings is used by examples to connect using various options + * to authenticate with the Applet. + * The SE05X_Auth options can be changed for KSDK Demos and Examples. + * To change SE05X_Auth option follow below steps. + * Set flag ``SSS_HAVE_SCP_SCP03_SSS`` to 1 and Reset flag ``SSS_HAVE_SCP_NONE`` to 0. + * To change SE05X_Auth option other than ``None`` and ``PlatfSCP03``, + * execute se05x_Delete_and_test_provision.exe in order to provision the Authentication Key. + * To change SE05X_Auth option to ``ECKey`` or ``ECKey_PlatfSCP03``, + * Set additional flag ``SSS_HAVE_HOSTCRYPTO_ANY`` to 1. + */ + +/** Use the default session (i.e. session less) login */ +#define SSS_HAVE_SE05X_AUTH_NONE 1 + +/** Do User Authentication with UserID */ +#define SSS_HAVE_SE05X_AUTH_USERID 0 + +/** Use Platform SCP for connection to SE */ +#define SSS_HAVE_SE05X_AUTH_PLATFSCP03 0 + +/** Do User Authentication with AES Key + * Earlier this was called AppletSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY 0 + +/** Do User Authentication with EC Key + * Earlier this was called FastSCP */ +#define SSS_HAVE_SE05X_AUTH_ECKEY 0 + +/** UserID and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 0 + +/** AESKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 0 + +/** ECKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 0 + +#if (( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) > 1) +# error "Enable only one of 'SE05X_Auth'" +#endif + + +#if (( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) == 0) +# error "Enable at-least one of 'SE05X_Auth'" +#endif + + + +/** A71CH_AUTH : A71CH Authentication + * + * This settings is used by SSS-API based examples to connect using either plain or authenticated to the A71CH. + */ + +/** Plain communication, not authenticated or encrypted */ +#define SSS_HAVE_A71CH_AUTH_NONE 1 + +/** SCP03 enabled */ +#define SSS_HAVE_A71CH_AUTH_SCP03 0 + +#if (( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) > 1) +# error "Enable only one of 'A71CH_AUTH'" +#endif + + +#if (( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) == 0) +# error "Enable at-least one of 'A71CH_AUTH'" +#endif + + +/* ====================================================================== * + * == Feature selection/values ========================================== * + * ====================================================================== */ + + +/** SE05X Secure Element : Symmetric AES */ +#define SSSFTR_SE05X_AES 1 + +/** SE05X Secure Element : Elliptic Curve Cryptography */ +#define SSSFTR_SE05X_ECC 1 + +/** SE05X Secure Element : RSA */ +#define SSSFTR_SE05X_RSA 1 + +/** SE05X Secure Element : KEY operations : SET Key */ +#define SSSFTR_SE05X_KEY_SET 1 + +/** SE05X Secure Element : KEY operations : GET Key */ +#define SSSFTR_SE05X_KEY_GET 1 + +/** SE05X Secure Element : Authenticate via ECKey */ +#define SSSFTR_SE05X_AuthECKey 1 + +/** SE05X Secure Element : Allow creation of user/authenticated session. + * + * If the intended deployment only uses Platform SCP + * Or it is a pure session less integration, this can + * save some code size. */ +#define SSSFTR_SE05X_AuthSession 1 + +/** SE05X Secure Element : Allow creation/deletion of Crypto Objects + * + * If disabled, new Crytpo Objects are neither created and + * old/existing Crypto Objects are not deleted. + * It is assumed that during provisioning phase, the required + * Crypto Objects are pre-created or they are never going to + * be needed. */ +#define SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ 1 + +/** Software : Symmetric AES */ +#define SSSFTR_SW_AES 1 + +/** Software : Elliptic Curve Cryptography */ +#define SSSFTR_SW_ECC 1 + +/** Software : RSA */ +#define SSSFTR_SW_RSA 1 + +/** Software : KEY operations : SET Key */ +#define SSSFTR_SW_KEY_SET 1 + +/** Software : KEY operations : GET Key */ +#define SSSFTR_SW_KEY_GET 1 + +/** Software : Used as a test counterpart + * + * e.g. Major part of the mebdTLS SSS layer is purely used for + * testing of Secure Element implementation, and can be avoided + * fully during many production scenarios. */ +#define SSSFTR_SW_TESTCOUNTERPART 1 + +/* ====================================================================== * + * == Computed Options ================================================== * + * ====================================================================== */ + +/** Symmetric AES */ +#define SSSFTR_AES (SSSFTR_SE05X_AES + SSSFTR_SW_AES) +/** Elliptic Curve Cryptography */ +#define SSSFTR_ECC (SSSFTR_SE05X_ECC + SSSFTR_SW_ECC) +/** RSA */ +#define SSSFTR_RSA (SSSFTR_SE05X_RSA + SSSFTR_SW_RSA) +/** KEY operations : SET Key */ +#define SSSFTR_KEY_SET (SSSFTR_SE05X_KEY_SET + SSSFTR_SW_KEY_SET) +/** KEY operations : GET Key */ +#define SSSFTR_KEY_GET (SSSFTR_SE05X_KEY_GET + SSSFTR_SW_KEY_GET) +/** KEY operations */ +#define SSSFTR_KEY (SSSFTR_KEY_SET + SSSFTR_KEY_GET) +/** KEY operations */ +#define SSSFTR_SE05X_KEY (SSSFTR_SE05X_KEY_SET + SSSFTR_SE05X_KEY_GET) +/** KEY operations */ +#define SSSFTR_SW_KEY (SSSFTR_SW_KEY_SET + SSSFTR_SW_KEY_GET) + + +#define SSS_HAVE_APPLET \ + (SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CL | SSS_HAVE_APPLET_A71CH_SIM | SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C | SSS_HAVE_APPLET_SE05X_L | SSS_HAVE_APPLET_LOOPBACK) + +#define SSS_HAVE_APPLET_SE05X_IOT \ + (SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C) + +#define SSS_HAVE_MBEDTLS_ALT \ + (SSS_HAVE_MBEDTLS_ALT_SSS | SSS_HAVE_MBEDTLS_ALT_A71CH) + +#define SSS_HAVE_HOSTCRYPTO_ANY \ + (SSS_HAVE_HOSTCRYPTO_MBEDTLS | SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO | SSS_HAVE_HOSTCRYPTO_OPENSSL | SSS_HAVE_HOSTCRYPTO_USER) + +#define SSS_HAVE_FIPS \ + (SSS_HAVE_FIPS_SE050 | SSS_HAVE_FIPS_140_2 | SSS_HAVE_FIPS_140_3) + + +/* Version checks GTE - Greater Than Or Equal To */ +#if SSS_HAVE_APPLET_SE05X_IOT +# if SSS_HAVE_SE05X_VER_06_00 +# define SSS_HAVE_SE05X_VER_GTE_06_00 1 +# define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +# endif /* SSS_HAVE_SE05X_VER_06_00 */ +# if SSS_HAVE_SE05X_VER_03_XX +# define SSS_HAVE_SE05X_VER_GTE_06_00 0 +# define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +# endif /* SSS_HAVE_SE05X_VER_03_XX */ +#else //SSS_HAVE_APPLET_SE05X_IOT +# define SSS_HAVE_SE05X_VER_GTE_03_XX 0 +# define SSS_HAVE_SE05X_VER_GTE_06_00 0 +#endif // SSS_HAVE_APPLET_SE05X_IOT +/** Deprecated items. Used here for backwards compatibility. */ + +#define WithApplet_SE05X (SSS_HAVE_APPLET_SE05X_IOT) +#define WithApplet_SE050_A (SSS_HAVE_APPLET_SE05X_A) +#define WithApplet_SE050_B (SSS_HAVE_APPLET_SE05X_B) +#define WithApplet_SE050_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE050_A (SSS_HAVE_APPLET_SE05X_A) +#define SSS_HAVE_SE050_B (SSS_HAVE_APPLET_SE05X_B) +#define SSS_HAVE_SE050_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE05X (SSS_HAVE_APPLET_SE05X_IOT) +#define SSS_HAVE_SE (SSS_HAVE_APPLET) +#define SSS_HAVE_LOOPBACK (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_ALT (SSS_HAVE_MBEDTLS_ALT) +#define WithApplet_None (SSS_HAVE_APPLET_NONE) +#define SSS_HAVE_None (SSS_HAVE_APPLET_NONE) +#define WithApplet_A71CH (SSS_HAVE_APPLET_A71CH) +#define SSS_HAVE_A71CH (SSS_HAVE_APPLET_A71CH) +#define WithApplet_A71CL (SSS_HAVE_APPLET_A71CL) +#define SSS_HAVE_A71CL (SSS_HAVE_APPLET_A71CL) +#define WithApplet_A71CH_SIM (SSS_HAVE_APPLET_A71CH_SIM) +#define SSS_HAVE_A71CH_SIM (SSS_HAVE_APPLET_A71CH_SIM) +#define WithApplet_SE05X_A (SSS_HAVE_APPLET_SE05X_A) +#define SSS_HAVE_SE05X_A (SSS_HAVE_APPLET_SE05X_A) +#define WithApplet_SE05X_B (SSS_HAVE_APPLET_SE05X_B) +#define SSS_HAVE_SE05X_B (SSS_HAVE_APPLET_SE05X_B) +#define WithApplet_SE05X_C (SSS_HAVE_APPLET_SE05X_C) +#define SSS_HAVE_SE05X_C (SSS_HAVE_APPLET_SE05X_C) +#define WithApplet_SE05X_L (SSS_HAVE_APPLET_SE05X_L) +#define SSS_HAVE_SE05X_L (SSS_HAVE_APPLET_SE05X_L) +#define WithApplet_LoopBack (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_LoopBack (SSS_HAVE_APPLET_LOOPBACK) +#define SSS_HAVE_MBEDTLS (SSS_HAVE_HOSTCRYPTO_MBEDTLS) +#define SSS_HAVE_MBEDCRYPTO (SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO) +#define SSS_HAVE_OPENSSL (SSS_HAVE_HOSTCRYPTO_OPENSSL) +#define SSS_HAVE_USER (SSS_HAVE_HOSTCRYPTO_USER) +#define SSS_HAVE_NONE (SSS_HAVE_HOSTCRYPTO_NONE) +#define SSS_HAVE_ALT_SSS (SSS_HAVE_MBEDTLS_ALT_SSS) +#define SSS_HAVE_ALT_A71CH (SSS_HAVE_MBEDTLS_ALT_A71CH) +#define SSS_HAVE_ALT_NONE (SSS_HAVE_MBEDTLS_ALT_NONE) +#define SSS_HAVE_SE05X_Auth_None (SSS_HAVE_SE05X_AUTH_NONE) +#define SSS_HAVE_SE05X_Auth_UserID (SSS_HAVE_SE05X_AUTH_USERID) +#define SSS_HAVE_SE05X_Auth_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_AESKey (SSS_HAVE_SE05X_AUTH_AESKEY) +#define SSS_HAVE_SE05X_Auth_ECKey (SSS_HAVE_SE05X_AUTH_ECKEY) +#define SSS_HAVE_SE05X_Auth_UserID_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_AESKey_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03) +#define SSS_HAVE_SE05X_Auth_ECKey_PlatfSCP03 (SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03) + +/* # CMake Features : END */ + +/* ========= Miscellaneous values : START =================== */ + +/* ECC Mode is available */ +#define SSS_HAVE_ECC 1 + +/* RSA is available */ +#define SSS_HAVE_RSA 1 + +/* TPM BARRETO_NAEHRIG Curve is enabled */ +#define SSS_HAVE_TPM_BN 1 + +/* Edwards Curve is enabled */ +#define SSS_HAVE_EC_ED 1 + +/* Montgomery Curve is enabled */ +#define SSS_HAVE_EC_MONT 1 + +/* MIFARE DESFire is enabled */ +#define SSS_HAVE_MIFARE_DESFIRE 1 + +/* PBKDF2 is enabled */ +#define SSS_HAVE_PBKDF2 1 + +/* TLS handshake support on SE is enabled */ +#define SSS_HAVE_TLS_HANDSHAKE 1 + +/* Import Export Key is enabled */ +#define SSS_HAVE_IMPORT 1 + +/* With NXP NFC Reader Library */ +#define SSS_HAVE_NXPNFCRDLIB 0 + +#define SSS_HAVE_A71XX \ + (SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CH_SIM) + +#define SSS_HAVE_SSCP (SSS_HAVE_A71XX) + +/* For backwards compatibility */ +#define SSS_HAVE_TESTCOUNTERPART (SSSFTR_SW_TESTCOUNTERPART) + +/* ========= Miscellaneous values : END ===================== */ + +/* ========= Calculated values : START ====================== */ + +/* Should we expose, SSS APIs */ +#define SSS_HAVE_SSS ( 0 \ + + SSS_HAVE_SSCP \ + + SSS_HAVE_APPLET_SE05X_IOT \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_USER \ + ) + +/* MBEDCRYPTO is superset of MBEDTLS and exposing that way */ +#if SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO +# undef SSS_HAVE_MBEDTLS +# undef SSS_HAVE_HOSTCRYPTO_MBEDTLS + +# define SSS_HAVE_MBEDTLS 1 +# define SSS_HAVE_HOSTCRYPTO_MBEDTLS 1 +#endif // SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO + +#if SSS_HAVE_HOSTCRYPTO_NONE +# undef SSSFTR_SE05X_AuthSession +# define SSSFTR_SE05X_AuthSession 0 +#endif + +/* Montgomery curves is not supported in SE05X_A*/ +#if SSS_HAVE_APPLET_SE05X_A +# undef SSS_HAVE_EC_MONT +# define SSS_HAVE_EC_MONT 0 +/* ED is not supported in SE050_A */ +#if SSS_HAVE_SE05X_VER_03_XX +# undef SSS_HAVE_EC_ED +# define SSS_HAVE_EC_ED 0 +#endif +#endif + +#if SSS_HAVE_RSA +# define SSS_HAVE_RSA_4K 1 +#endif + +#if SSS_HAVE_ECC +# define SSS_HAVE_EC_NIST_192 1 +# define SSS_HAVE_EC_NIST_224 1 +# define SSS_HAVE_EC_NIST_256 1 +# define SSS_HAVE_EC_NIST_384 1 +# define SSS_HAVE_EC_NIST_521 1 +# define SSS_HAVE_EC_BP 1 +# define SSS_HAVE_EC_NIST_K 1 +# define SSS_HAVE_ECDAA 1 +# define SSS_HAVE_EDDSA 1 +#if SSS_HAVE_APPLET_SE05X_A +# undef SSS_HAVE_ECDAA +# undef SSS_HAVE_EDDSA +# define SSS_HAVE_ECDAA 0 +# define SSS_HAVE_EDDSA 0 +#endif +#endif + +#if SSS_HAVE_APPLET +#define SSS_HAVE_HASH_1 1 +#define SSS_HAVE_HASH_224 1 +#define SSS_HAVE_HASH_512 1 +#endif + + +/* ========= Calculated values : END ======================== */ + +/* clang-format on */ + +#endif /* SSS_APIS_INC_FSL_SSS_FTR_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h new file mode 100644 index 00000000000..2b9b58a1c81 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h @@ -0,0 +1,182 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Mapping between key id and physical key store */ + +#ifndef SSS_INC_KEYID_MAP_H_ +#define SSS_INC_KEYID_MAP_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* Physical index */ +/* clang-format off */ +#define K_INDEX_MASK (0xFFFFu << 0u) +#define K_TYPE_MASK (0xFFu << 24u) +#define K_TYPE_ECC_KP (0x01u << 24u) +#define K_TYPE_ECC_PUB (0x02u << 24u) +#define K_TYPE_AES (0x03u << 24u) +#define K_TYPE_CERT (0x04u << 24u) + +/* Key store N Count */ +#define KS_N_ECC_KEY_PAIRS 4 +#define KS_N_ECC_PUB_KEYS 3 +#define KS_N_AES_KEYS 8 +#define KS_N_CERTIFCATES 4 +#define KS_N_RSA_KEY_PAIRS 1 +#define KS_N_SYM_KEYS 1 + +/* clang-format on */ + +#define KS_N_ENTIRES_CL (0 + KS_N_RSA_KEY_PAIRS + KS_N_SYM_KEYS) + +#define KS_N_ENTIRES (0 + KS_N_ECC_KEY_PAIRS + KS_N_ECC_PUB_KEYS + KS_N_AES_KEYS + KS_N_CERTIFCATES) + +#define KEYSTORE_MAGIC (0xA71C401L) +#define KEYSTORE_VERSION (0x0004) +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +/* Generic entry of a Key ID Mapping inside the secure element */ +typedef struct +{ + /** External index */ + uint32_t extKeyId; + + /* Of type sss_key_part_t + * + * B0,B1,B2,B3 -> Key part and B4,B5,B6,B7 -> (No of slots taken - 1) */ + uint8_t keyPart; + uint8_t accessPermission; + uint8_t cipherType; /* Of type sss_cipher_type_t */ + /** Internal index */ + uint8_t keyIntIndex; +} keyIdAndTypeIndexLookup_t; + +typedef struct _keyStoreTable_t +{ + /** Fixed - Unique 32bit magic number. + * + * In case some one over-writes we can know. */ + uint32_t magic; + /** Fixed - constant based on version number */ + uint16_t version; + /** + * maxEntries Fixed - constant in the Layout. Should be equal to + * KS_N_ENTIRES This will help in porting between A71CH with less memory and + * SE050 with more memory + */ + uint16_t maxEntries; + /** Dynamic entries */ + keyIdAndTypeIndexLookup_t *entries; +} keyStoreTable_t; + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** + * Initialize the File allocation table entry + * + * @param keystore_shadow Shadow structure (to be persisted later to EEPROM or + * File System) + * @param lookup_entires Mapping table + * @param max_entries Maximum entries that the Key Store can have + */ +void ks_common_init_fat( + keyStoreTable_t *keystore_shadow, keyIdAndTypeIndexLookup_t *lookup_entires, size_t max_entries); + +/** + * Update the File Allocation Table for the key. + * + * @param[out] keystore_shadow + * @param[in] sss_key The key object. + * @param[in] intIndex internal index. + * @param extId External 32bit id of the key + * @param object_type Type of the object + * @param intIndex Internal index of the key. + * @param accessPermission Access (Read/write/etc.) + * + * @note accessPermission is not used for A71CH + * + * @return Fail if not able to add the entry. + + */ +sss_status_t ks_common_update_fat(keyStoreTable_t *keystore_shadow, + uint32_t extId, + sss_key_part_t object_part, + sss_cipher_type_t cipher_type, + uint8_t intIndex, + uint32_t accessPermission, + uint16_t keyLen); + +/** + * check if the internal slot is availble for the key type. + * + * @param[in] keystore_shadow + * @param[in] object_type type of key Object + * @param[out] next_free_index avialable internal index for a particular key + * type + * + * @return Fail if internal index is not available. + */ +sss_status_t ks_common_check_available_int_index(keyStoreTable_t *keystore_shadow, + uint8_t object_type, + uint8_t cipher_type, + uint16_t *next_free_index, + uint16_t keyLen); + +sss_status_t ks_common_extId_to_int_index(keyStoreTable_t *keystore_shadow, uint32_t extId, uint16_t *intIndex); +/** + * check if the key store is valid. + * + * @param[in] keystore_shadow The shadow of keystore + * @param[out] status + * + * @return Fail if key store is not valid + */ +sss_status_t isValidKeyStoreShadow(keyStoreTable_t *keystore_shadow); +/** +* check if the internal slot is availble for the key type. +* +* @param[in] keystore_shadow +* @param[in] keyId key id for getting key object +* @param[out] keyType type of keyobject retrieved from keyId* type +* +* @return Fail if keyId not found +*/ +sss_status_t ks_common_get_keyType_from_keyid( + keyStoreTable_t *keystore_shadow, uint32_t keyId, uint32_t *keyType, uint32_t *cipherType); +/** + * remove entry from shadow keystore. + * + * @param[in] keystore_shadow + * @param[in] extId key id for getting key object + * + * @return Fail if keyId not found + */ +sss_status_t ks_common_remove_fat(keyStoreTable_t *keystore_shadow, uint32_t extId); + +void ks_sw_fat_remove(const char *szRootPath); +void ks_sw_fat_free(keyStoreTable_t *keystore_shadow); +void ks_sw_fat_allocate(keyStoreTable_t **keystore_shadow); +void ks_sw_getKeyFileName( + char *const file_name, const size_t size, const sss_object_t *sss_key, const char *root_folder); +sss_status_t ks_sw_fat_load(const char *szRootPath, keyStoreTable_t *pKeystore_shadow); + +#endif /* SSS_INC_KEYID_MAP_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h new file mode 100644 index 00000000000..d9e1a05f4f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h @@ -0,0 +1,115 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __FSL_SSS_LPC55S_APIS_H__ +#define __FSL_SSS_LPC55S_APIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if defined(SECURE_WORLD) +#if SSS_HAVE_HOSTCRYPTO_MBEDTLS +#include +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** @copydoc sss_session_open + * + */ +sss_status_t sss_lpc55s_impl_session_open(sss_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_close + * + */ +void sss_lpc55s_impl_session_close(sss_session_t *session); + +/** + * @addtogroup sss_lpc55s_impl_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_lpc55s_impl_mac_context_init( + sss_mac_t *context, sss_session_t *session, sss_object_t *keyObject, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_lpc55s_impl_mac_one_go( + sss_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_lpc55s_impl_mac_context_free(sss_mac_t *context); + +/** Re-define sss_host_session_open to be redirected + * from HashCrypt session open + */ +#ifdef sss_host_session_open +#undef sss_host_session_open +#define sss_host_session_open(session, subsystem, application_id, connection_type, connectionData) \ + sss_lpc55s_impl_session_open((session), (subsystem), (application_id), (connection_type), (connectionData)) +#endif + +/** Re-define sss_host_session_close to be redirected + * from HashCrypt session open + */ +#ifdef sss_host_session_close +#undef sss_host_session_close +#define sss_host_session_close(session) sss_lpc55s_impl_session_close((session)) +#endif + +/** Re-define sss_host_mac_context_init to be redirected + * from HashCrypt MAC operations + */ +#ifdef sss_host_mac_context_init +#undef sss_host_mac_context_init +#define sss_host_mac_context_init(context, session, keyObject, algorithm, mode) \ + sss_lpc55s_impl_mac_context_init((context), (session), (keyObject), (algorithm), (mode)) +#endif + +/** Re-define sss_host_mac_one_go to be redirected + * from HashCrypt MAC operations + */ +#ifdef sss_host_mac_one_go +#undef sss_host_mac_one_go +#define sss_host_mac_one_go(context, message, messageLen, mac, macLen) \ + sss_lpc55s_impl_mac_one_go((context), (message), (messageLen), (mac), (macLen)) +#endif + +/** Re-define sss_host_mac_context_free to be redirected + * from HashCrypt MAC operations + */ +#ifdef sss_host_mac_context_free +#undef sss_host_mac_context_free +#define sss_host_mac_context_free(context) sss_lpc55s_impl_mac_context_free((context)) +#endif + +/* clang-format on */ +#endif /* SSS_HAVE_HOSTCRYPTO_MBEDTLS */ +#endif /* SECURE_WORLD */ + +#ifdef __cplusplus +} // extern "C" +#endif /* __cplusplus */ + +#endif /* __FSL_SSS_LPC55S_APIS_H__ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h new file mode 100644 index 00000000000..d077f63088a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h @@ -0,0 +1,837 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FSL_SSS_MBEDTLS_APIS_H +#define FSL_SSS_MBEDTLS_APIS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_MBEDTLS +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** + * @addtogroup sss_mbedtls_session + * @{ + */ +/** @copydoc sss_session_create + * + */ +sss_status_t sss_mbedtls_session_create(sss_mbedtls_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_open + * + */ +sss_status_t sss_mbedtls_session_open(sss_mbedtls_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_prop_get_u32 + * + */ +sss_status_t sss_mbedtls_session_prop_get_u32(sss_mbedtls_session_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_session_prop_get_au8 + * + */ +sss_status_t sss_mbedtls_session_prop_get_au8( + sss_mbedtls_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_session_close + * + */ +void sss_mbedtls_session_close(sss_mbedtls_session_t *session); + +/** @copydoc sss_session_delete + * + */ +void sss_mbedtls_session_delete(sss_mbedtls_session_t *session); + +/*! @} */ /* end of : sss_mbedtls_session */ + +/** + * @addtogroup sss_mbedtls_keyobj + * @{ + */ +/** @copydoc sss_key_object_init + * + */ +sss_status_t sss_mbedtls_key_object_init(sss_mbedtls_object_t *keyObject, sss_mbedtls_key_store_t *keyStore); + +/** @copydoc sss_key_object_allocate_handle + * + */ +sss_status_t sss_mbedtls_key_object_allocate_handle(sss_mbedtls_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); + +/** @copydoc sss_key_object_get_handle + * + */ +sss_status_t sss_mbedtls_key_object_get_handle(sss_mbedtls_object_t *keyObject, uint32_t keyId); + +/** @copydoc sss_key_object_set_user + * + */ +sss_status_t sss_mbedtls_key_object_set_user(sss_mbedtls_object_t *keyObject, uint32_t user, uint32_t options); + +/** @copydoc sss_key_object_set_purpose + * + */ +sss_status_t sss_mbedtls_key_object_set_purpose(sss_mbedtls_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** @copydoc sss_key_object_set_access + * + */ +sss_status_t sss_mbedtls_key_object_set_access(sss_mbedtls_object_t *keyObject, uint32_t access, uint32_t options); + +/** @copydoc sss_key_object_set_eccgfp_group + * + */ +sss_status_t sss_mbedtls_key_object_set_eccgfp_group(sss_mbedtls_object_t *keyObject, sss_eccgfp_group_t *group); + +/** @copydoc sss_key_object_get_user + * + */ +sss_status_t sss_mbedtls_key_object_get_user(sss_mbedtls_object_t *keyObject, uint32_t *user); + +/** @copydoc sss_key_object_get_purpose + * + */ +sss_status_t sss_mbedtls_key_object_get_purpose(sss_mbedtls_object_t *keyObject, sss_mode_t *purpose); + +/** @copydoc sss_key_object_get_access + * + */ +sss_status_t sss_mbedtls_key_object_get_access(sss_mbedtls_object_t *keyObject, uint32_t *access); + +/** @copydoc sss_key_object_free + * + */ +void sss_mbedtls_key_object_free(sss_mbedtls_object_t *keyObject); + +/*! @} */ /* end of : sss_mbedtls_keyobj */ + +/** + * @addtogroup sss_mbedtls_keyderive + * @{ + */ +/** @copydoc sss_derive_key_context_init + * + */ +sss_status_t sss_mbedtls_derive_key_context_init(sss_mbedtls_derive_key_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_derive_key_go + * + */ +sss_status_t sss_mbedtls_derive_key_go(sss_mbedtls_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @copydoc sss_derive_key_one_go +* +*/ +sss_status_t sss_mbedtls_derive_key_one_go(sss_mbedtls_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_sobj_one_go +* +*/ +sss_status_t sss_mbedtls_derive_key_sobj_one_go(sss_mbedtls_derive_key_t *context, + sss_mbedtls_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_dh + * + */ +sss_status_t sss_mbedtls_derive_key_dh(sss_mbedtls_derive_key_t *context, + sss_mbedtls_object_t *otherPartyKeyObject, + sss_mbedtls_object_t *derivedKeyObject); + +/** @copydoc sss_derive_key_context_free + * + */ +void sss_mbedtls_derive_key_context_free(sss_mbedtls_derive_key_t *context); + +/*! @} */ /* end of : sss_mbedtls_keyderive */ + +/** + * @addtogroup sss_mbedtls_keystore + * @{ + */ +/** @copydoc sss_key_store_context_init + * + */ +sss_status_t sss_mbedtls_key_store_context_init(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_session_t *session); + +/** @copydoc sss_key_store_allocate + * + */ +sss_status_t sss_mbedtls_key_store_allocate(sss_mbedtls_key_store_t *keyStore, uint32_t keyStoreId); + +/** @copydoc sss_key_store_save + * + */ +sss_status_t sss_mbedtls_key_store_save(sss_mbedtls_key_store_t *keyStore); + +/** @copydoc sss_key_store_load + * + */ +sss_status_t sss_mbedtls_key_store_load(sss_mbedtls_key_store_t *keyStore); + +/** @copydoc sss_key_store_set_key + * + */ +sss_status_t sss_mbedtls_key_store_set_key(sss_mbedtls_key_store_t *keyStore, + sss_mbedtls_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @copydoc sss_key_store_generate_key + * + */ +sss_status_t sss_mbedtls_key_store_generate_key( + sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject, size_t keyBitLen, void *options); + +/** @copydoc sss_key_store_get_key + * + */ +sss_status_t sss_mbedtls_key_store_get_key(sss_mbedtls_key_store_t *keyStore, + sss_mbedtls_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen); + +/** @copydoc sss_key_store_open_key + * + */ +sss_status_t sss_mbedtls_key_store_open_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject); + +/** @copydoc sss_key_store_freeze_key + * + */ +sss_status_t sss_mbedtls_key_store_freeze_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject); + +/** @copydoc sss_key_store_erase_key + * + */ +sss_status_t sss_mbedtls_key_store_erase_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject); + +/** @copydoc sss_key_store_context_free + * + */ +void sss_mbedtls_key_store_context_free(sss_mbedtls_key_store_t *keyStore); + +/*! @} */ /* end of : sss_mbedtls_keystore */ + +/** + * @addtogroup sss_mbedtls_asym + * @{ + */ +/** @copydoc sss_asymmetric_context_init + * + */ +sss_status_t sss_mbedtls_asymmetric_context_init(sss_mbedtls_asymmetric_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_asymmetric_encrypt + * + */ +sss_status_t sss_mbedtls_asymmetric_encrypt( + sss_mbedtls_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_decrypt + * + */ +sss_status_t sss_mbedtls_asymmetric_decrypt( + sss_mbedtls_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_sign_digest + * + */ +sss_status_t sss_mbedtls_asymmetric_sign_digest( + sss_mbedtls_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @copydoc sss_asymmetric_verify_digest + * + */ +sss_status_t sss_mbedtls_asymmetric_verify_digest( + sss_mbedtls_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @copydoc sss_asymmetric_context_free + * + */ +void sss_mbedtls_asymmetric_context_free(sss_mbedtls_asymmetric_t *context); + +/*! @} */ /* end of : sss_mbedtls_asym */ + +/** + * @addtogroup sss_mbedtls_symm + * @{ + */ +/** @copydoc sss_symmetric_context_init + * + */ +sss_status_t sss_mbedtls_symmetric_context_init(sss_mbedtls_symmetric_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_cipher_one_go + * + */ +sss_status_t sss_mbedtls_cipher_one_go(sss_mbedtls_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen); + +/** @copydoc sss_cipher_init + * + */ +sss_status_t sss_mbedtls_cipher_init(sss_mbedtls_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @copydoc sss_cipher_update + * + */ +sss_status_t sss_mbedtls_cipher_update( + sss_mbedtls_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_finish + * + */ +sss_status_t sss_mbedtls_cipher_finish( + sss_mbedtls_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_crypt_ctr + * + */ +sss_status_t sss_mbedtls_cipher_crypt_ctr(sss_mbedtls_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @copydoc sss_symmetric_context_free + * + */ +void sss_mbedtls_symmetric_context_free(sss_mbedtls_symmetric_t *context); + +/*! @} */ /* end of : sss_mbedtls_symm */ + +/** + * @addtogroup sss_mbedtls_aead + * @{ + */ +/** @copydoc sss_aead_context_init + * + */ +sss_status_t sss_mbedtls_aead_context_init(sss_mbedtls_aead_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_aead_one_go + * + */ +sss_status_t sss_mbedtls_aead_one_go(sss_mbedtls_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_init + * + */ +sss_status_t sss_mbedtls_aead_init( + sss_mbedtls_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); + +/** @copydoc sss_aead_update_aad + * + */ +sss_status_t sss_mbedtls_aead_update_aad(sss_mbedtls_aead_t *context, const uint8_t *aadData, size_t aadDataLen); + +/** @copydoc sss_aead_update + * + */ +sss_status_t sss_mbedtls_aead_update( + sss_mbedtls_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_aead_finish + * + */ +sss_status_t sss_mbedtls_aead_finish(sss_mbedtls_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_context_free + * + */ +void sss_mbedtls_aead_context_free(sss_mbedtls_aead_t *context); + +/*! @} */ /* end of : sss_mbedtls_aead */ + +/** + * @addtogroup sss_mbedtls_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_mbedtls_mac_context_init(sss_mbedtls_mac_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_mbedtls_mac_one_go( + sss_mbedtls_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_init + * + */ +sss_status_t sss_mbedtls_mac_init(sss_mbedtls_mac_t *context); + +/** @copydoc sss_mac_update + * + */ +sss_status_t sss_mbedtls_mac_update(sss_mbedtls_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_mac_finish + * + */ +sss_status_t sss_mbedtls_mac_finish(sss_mbedtls_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_mbedtls_mac_context_free(sss_mbedtls_mac_t *context); + +/*! @} */ /* end of : sss_mbedtls_mac */ + +/** + * @addtogroup sss_mbedtls_md + * @{ + */ +/** @copydoc sss_digest_context_init + * + */ +sss_status_t sss_mbedtls_digest_context_init( + sss_mbedtls_digest_t *context, sss_mbedtls_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_digest_one_go + * + */ +sss_status_t sss_mbedtls_digest_one_go( + sss_mbedtls_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_init + * + */ +sss_status_t sss_mbedtls_digest_init(sss_mbedtls_digest_t *context); + +/** @copydoc sss_digest_update + * + */ +sss_status_t sss_mbedtls_digest_update(sss_mbedtls_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_digest_finish + * + */ +sss_status_t sss_mbedtls_digest_finish(sss_mbedtls_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_context_free + * + */ +void sss_mbedtls_digest_context_free(sss_mbedtls_digest_t *context); + +/*! @} */ /* end of : sss_mbedtls_md */ + +/** + * @addtogroup sss_mbedtls_rng + * @{ + */ +/** @copydoc sss_rng_context_init + * + */ +sss_status_t sss_mbedtls_rng_context_init(sss_mbedtls_rng_context_t *context, sss_mbedtls_session_t *session); + +/** @copydoc sss_rng_get_random + * + */ +sss_status_t sss_mbedtls_rng_get_random(sss_mbedtls_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** @copydoc sss_rng_context_free + * + */ +sss_status_t sss_mbedtls_rng_context_free(sss_mbedtls_rng_context_t *context); + +/*! @} */ /* end of : sss_mbedtls_rng */ + +/* clang-format off */ +# if (SSS_HAVE_SSS == 1) + /* Direct Call : session */ +# define sss_session_create(session,subsystem,application_id,connection_type,connectionData) \ + sss_mbedtls_session_create(((sss_mbedtls_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_open(session,subsystem,application_id,connection_type,connectionData) \ + sss_mbedtls_session_open(((sss_mbedtls_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_prop_get_u32(session,property,pValue) \ + sss_mbedtls_session_prop_get_u32(((sss_mbedtls_session_t * ) session),(property),(pValue)) +# define sss_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_mbedtls_session_prop_get_au8(((sss_mbedtls_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_session_close(session) \ + sss_mbedtls_session_close(((sss_mbedtls_session_t * ) session)) +# define sss_session_delete(session) \ + sss_mbedtls_session_delete(((sss_mbedtls_session_t * ) session)) + /* Direct Call : keyobj */ +# define sss_key_object_init(keyObject,keyStore) \ + sss_mbedtls_key_object_init(((sss_mbedtls_object_t * ) keyObject),((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_mbedtls_key_object_allocate_handle(((sss_mbedtls_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_key_object_get_handle(keyObject,keyId) \ + sss_mbedtls_key_object_get_handle(((sss_mbedtls_object_t * ) keyObject),(keyId)) +# define sss_key_object_set_user(keyObject,user,options) \ + sss_mbedtls_key_object_set_user(((sss_mbedtls_object_t * ) keyObject),(user),(options)) +# define sss_key_object_set_purpose(keyObject,purpose,options) \ + sss_mbedtls_key_object_set_purpose(((sss_mbedtls_object_t * ) keyObject),(purpose),(options)) +# define sss_key_object_set_access(keyObject,access,options) \ + sss_mbedtls_key_object_set_access(((sss_mbedtls_object_t * ) keyObject),(access),(options)) +# define sss_key_object_set_eccgfp_group(keyObject,group) \ + sss_mbedtls_key_object_set_eccgfp_group(((sss_mbedtls_object_t * ) keyObject),(group)) +# define sss_key_object_get_user(keyObject,user) \ + sss_mbedtls_key_object_get_user(((sss_mbedtls_object_t * ) keyObject),(user)) +# define sss_key_object_get_purpose(keyObject,purpose) \ + sss_mbedtls_key_object_get_purpose(((sss_mbedtls_object_t * ) keyObject),(purpose)) +# define sss_key_object_get_access(keyObject,access) \ + sss_mbedtls_key_object_get_access(((sss_mbedtls_object_t * ) keyObject),(access)) +# define sss_key_object_free(keyObject) \ + sss_mbedtls_key_object_free(((sss_mbedtls_object_t * ) keyObject)) + /* Direct Call : keyderive */ +# define sss_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_derive_key_context_init(((sss_mbedtls_derive_key_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_mbedtls_derive_key_go(((sss_mbedtls_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_mbedtls_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_derive_key_one_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen) \ + sss_mbedtls_derive_key_one_go(((sss_mbedtls_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_mbedtls_object_t * ) derivedKeyObject),(deriveDataLen)) +# define sss_derive_key_sobj_one_go(context,saltKeyObject,info,infoLen,derivedKeyObject,deriveDataLen) \ + sss_mbedtls_derive_key_sobj_one_go(((sss_mbedtls_derive_key_t * ) context),((sss_mbedtls_object_t * )saltKeyObject),(info),(infoLen),((sss_mbedtls_object_t * ) derivedKeyObject),(deriveDataLen)) +# define sss_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_mbedtls_derive_key_dh(((sss_mbedtls_derive_key_t * ) context),((sss_mbedtls_object_t * ) otherPartyKeyObject),((sss_mbedtls_object_t * ) derivedKeyObject)) +# define sss_derive_key_context_free(context) \ + sss_mbedtls_derive_key_context_free(((sss_mbedtls_derive_key_t * ) context)) + /* Direct Call : keystore */ +# define sss_key_store_context_init(keyStore,session) \ + sss_mbedtls_key_store_context_init(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_session_t * ) session)) +# define sss_key_store_allocate(keyStore,keyStoreId) \ + sss_mbedtls_key_store_allocate(((sss_mbedtls_key_store_t * ) keyStore),(keyStoreId)) +# define sss_key_store_save(keyStore) \ + sss_mbedtls_key_store_save(((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_key_store_load(keyStore) \ + sss_mbedtls_key_store_load(((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_mbedtls_key_store_set_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_mbedtls_key_store_generate_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_mbedtls_key_store_get_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_key_store_open_key(keyStore,keyObject) \ + sss_mbedtls_key_store_open_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_key_store_freeze_key(keyStore,keyObject) \ + sss_mbedtls_key_store_freeze_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_key_store_erase_key(keyStore,keyObject) \ + sss_mbedtls_key_store_erase_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_key_store_context_free(keyStore) \ + sss_mbedtls_key_store_context_free(((sss_mbedtls_key_store_t * ) keyStore)) + /* Direct Call : asym */ +# define sss_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_asymmetric_context_init(((sss_mbedtls_asymmetric_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_asymmetric_encrypt(((sss_mbedtls_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_asymmetric_decrypt(((sss_mbedtls_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_mbedtls_asymmetric_sign_digest(((sss_mbedtls_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_mbedtls_asymmetric_verify_digest(((sss_mbedtls_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_context_free(context) \ + sss_mbedtls_asymmetric_context_free(((sss_mbedtls_asymmetric_t * ) context)) + /* Direct Call : symm */ +# define sss_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_symmetric_context_init(((sss_mbedtls_symmetric_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_mbedtls_cipher_one_go(((sss_mbedtls_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_cipher_init(context,iv,ivLen) \ + sss_mbedtls_cipher_init(((sss_mbedtls_symmetric_t * ) context),(iv),(ivLen)) +# define sss_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_cipher_update(((sss_mbedtls_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_cipher_finish(((sss_mbedtls_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_mbedtls_cipher_crypt_ctr(((sss_mbedtls_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_symmetric_context_free(context) \ + sss_mbedtls_symmetric_context_free(((sss_mbedtls_symmetric_t * ) context)) + /* Direct Call : aead */ +# define sss_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_aead_context_init(((sss_mbedtls_aead_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_mbedtls_aead_one_go(((sss_mbedtls_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_mbedtls_aead_init(((sss_mbedtls_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_aead_update_aad(context,aadData,aadDataLen) \ + sss_mbedtls_aead_update_aad(((sss_mbedtls_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_aead_update(((sss_mbedtls_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_mbedtls_aead_finish(((sss_mbedtls_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_aead_context_free(context) \ + sss_mbedtls_aead_context_free(((sss_mbedtls_aead_t * ) context)) + /* Direct Call : mac */ +# define sss_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_mac_context_init(((sss_mbedtls_mac_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_mbedtls_mac_one_go(((sss_mbedtls_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_mac_init(context) \ + sss_mbedtls_mac_init(((sss_mbedtls_mac_t * ) context)) +# define sss_mac_update(context,message,messageLen) \ + sss_mbedtls_mac_update(((sss_mbedtls_mac_t * ) context),(message),(messageLen)) +# define sss_mac_finish(context,mac,macLen) \ + sss_mbedtls_mac_finish(((sss_mbedtls_mac_t * ) context),(mac),(macLen)) +# define sss_mac_context_free(context) \ + sss_mbedtls_mac_context_free(((sss_mbedtls_mac_t * ) context)) + /* Direct Call : md */ +# define sss_digest_context_init(context,session,algorithm,mode) \ + sss_mbedtls_digest_context_init(((sss_mbedtls_digest_t * ) context),((sss_mbedtls_session_t * ) session),(algorithm),(mode)) +# define sss_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_mbedtls_digest_one_go(((sss_mbedtls_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_digest_init(context) \ + sss_mbedtls_digest_init(((sss_mbedtls_digest_t * ) context)) +# define sss_digest_update(context,message,messageLen) \ + sss_mbedtls_digest_update(((sss_mbedtls_digest_t * ) context),(message),(messageLen)) +# define sss_digest_finish(context,digest,digestLen) \ + sss_mbedtls_digest_finish(((sss_mbedtls_digest_t * ) context),(digest),(digestLen)) +# define sss_digest_context_free(context) \ + sss_mbedtls_digest_context_free(((sss_mbedtls_digest_t * ) context)) + /* Direct Call : rng */ +# define sss_rng_context_init(context,session) \ + sss_mbedtls_rng_context_init(((sss_mbedtls_rng_context_t * ) context),((sss_mbedtls_session_t * ) session)) +# define sss_rng_get_random(context,random_data,dataLen) \ + sss_mbedtls_rng_get_random(((sss_mbedtls_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_rng_context_free(context) \ + sss_mbedtls_rng_context_free(((sss_mbedtls_rng_context_t * ) context)) +# endif /* (SSS_HAVE_SSS == 1) */ +# if (SSS_HAVE_OPENSSL == 0) + /* Host Call : session */ +# define sss_host_session_create(session,subsystem,application_id,connection_type,connectionData) \ + sss_mbedtls_session_create(((sss_mbedtls_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_host_session_open(session,subsystem,application_id,connection_type,connectionData) \ + sss_mbedtls_session_open(((sss_mbedtls_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_host_session_prop_get_u32(session,property,pValue) \ + sss_mbedtls_session_prop_get_u32(((sss_mbedtls_session_t * ) session),(property),(pValue)) +# define sss_host_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_mbedtls_session_prop_get_au8(((sss_mbedtls_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_host_session_close(session) \ + sss_mbedtls_session_close(((sss_mbedtls_session_t * ) session)) +# define sss_host_session_delete(session) \ + sss_mbedtls_session_delete(((sss_mbedtls_session_t * ) session)) + /* Host Call : keyobj */ +# define sss_host_key_object_init(keyObject,keyStore) \ + sss_mbedtls_key_object_init(((sss_mbedtls_object_t * ) keyObject),((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_host_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_mbedtls_key_object_allocate_handle(((sss_mbedtls_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_host_key_object_get_handle(keyObject,keyId) \ + sss_mbedtls_key_object_get_handle(((sss_mbedtls_object_t * ) keyObject),(keyId)) +# define sss_host_key_object_set_user(keyObject,user,options) \ + sss_mbedtls_key_object_set_user(((sss_mbedtls_object_t * ) keyObject),(user),(options)) +# define sss_host_key_object_set_purpose(keyObject,purpose,options) \ + sss_mbedtls_key_object_set_purpose(((sss_mbedtls_object_t * ) keyObject),(purpose),(options)) +# define sss_host_key_object_set_access(keyObject,access,options) \ + sss_mbedtls_key_object_set_access(((sss_mbedtls_object_t * ) keyObject),(access),(options)) +# define sss_host_key_object_set_eccgfp_group(keyObject,group) \ + sss_mbedtls_key_object_set_eccgfp_group(((sss_mbedtls_object_t * ) keyObject),(group)) +# define sss_host_key_object_get_user(keyObject,user) \ + sss_mbedtls_key_object_get_user(((sss_mbedtls_object_t * ) keyObject),(user)) +# define sss_host_key_object_get_purpose(keyObject,purpose) \ + sss_mbedtls_key_object_get_purpose(((sss_mbedtls_object_t * ) keyObject),(purpose)) +# define sss_host_key_object_get_access(keyObject,access) \ + sss_mbedtls_key_object_get_access(((sss_mbedtls_object_t * ) keyObject),(access)) +# define sss_host_key_object_free(keyObject) \ + sss_mbedtls_key_object_free(((sss_mbedtls_object_t * ) keyObject)) + /* Host Call : keyderive */ +# define sss_host_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_derive_key_context_init(((sss_mbedtls_derive_key_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_mbedtls_derive_key_go(((sss_mbedtls_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_mbedtls_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_host_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_mbedtls_derive_key_dh(((sss_mbedtls_derive_key_t * ) context),((sss_mbedtls_object_t * ) otherPartyKeyObject),((sss_mbedtls_object_t * ) derivedKeyObject)) +# define sss_host_derive_key_context_free(context) \ + sss_mbedtls_derive_key_context_free(((sss_mbedtls_derive_key_t * ) context)) + /* Host Call : keystore */ +# define sss_host_key_store_context_init(keyStore,session) \ + sss_mbedtls_key_store_context_init(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_session_t * ) session)) +# define sss_host_key_store_allocate(keyStore,keyStoreId) \ + sss_mbedtls_key_store_allocate(((sss_mbedtls_key_store_t * ) keyStore),(keyStoreId)) +# define sss_host_key_store_save(keyStore) \ + sss_mbedtls_key_store_save(((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_host_key_store_load(keyStore) \ + sss_mbedtls_key_store_load(((sss_mbedtls_key_store_t * ) keyStore)) +# define sss_host_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_mbedtls_key_store_set_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_host_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_mbedtls_key_store_generate_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_host_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_mbedtls_key_store_get_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_host_key_store_open_key(keyStore,keyObject) \ + sss_mbedtls_key_store_open_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_host_key_store_freeze_key(keyStore,keyObject) \ + sss_mbedtls_key_store_freeze_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_host_key_store_erase_key(keyStore,keyObject) \ + sss_mbedtls_key_store_erase_key(((sss_mbedtls_key_store_t * ) keyStore),((sss_mbedtls_object_t * ) keyObject)) +# define sss_host_key_store_context_free(keyStore) \ + sss_mbedtls_key_store_context_free(((sss_mbedtls_key_store_t * ) keyStore)) + /* Host Call : asym */ +# define sss_host_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_asymmetric_context_init(((sss_mbedtls_asymmetric_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_asymmetric_encrypt(((sss_mbedtls_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_asymmetric_decrypt(((sss_mbedtls_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_mbedtls_asymmetric_sign_digest(((sss_mbedtls_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_mbedtls_asymmetric_verify_digest(((sss_mbedtls_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_context_free(context) \ + sss_mbedtls_asymmetric_context_free(((sss_mbedtls_asymmetric_t * ) context)) + /* Host Call : symm */ +# define sss_host_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_symmetric_context_init(((sss_mbedtls_symmetric_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_mbedtls_cipher_one_go(((sss_mbedtls_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_host_cipher_init(context,iv,ivLen) \ + sss_mbedtls_cipher_init(((sss_mbedtls_symmetric_t * ) context),(iv),(ivLen)) +# define sss_host_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_cipher_update(((sss_mbedtls_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_cipher_finish(((sss_mbedtls_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_mbedtls_cipher_crypt_ctr(((sss_mbedtls_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_host_symmetric_context_free(context) \ + sss_mbedtls_symmetric_context_free(((sss_mbedtls_symmetric_t * ) context)) + /* Host Call : aead */ +# define sss_host_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_aead_context_init(((sss_mbedtls_aead_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_mbedtls_aead_one_go(((sss_mbedtls_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_host_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_mbedtls_aead_init(((sss_mbedtls_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_host_aead_update_aad(context,aadData,aadDataLen) \ + sss_mbedtls_aead_update_aad(((sss_mbedtls_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_host_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_mbedtls_aead_update(((sss_mbedtls_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_mbedtls_aead_finish(((sss_mbedtls_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_host_aead_context_free(context) \ + sss_mbedtls_aead_context_free(((sss_mbedtls_aead_t * ) context)) + /* Host Call : mac */ +# define sss_host_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_mbedtls_mac_context_init(((sss_mbedtls_mac_t * ) context),((sss_mbedtls_session_t * ) session),((sss_mbedtls_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_mbedtls_mac_one_go(((sss_mbedtls_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_host_mac_init(context) \ + sss_mbedtls_mac_init(((sss_mbedtls_mac_t * ) context)) +# define sss_host_mac_update(context,message,messageLen) \ + sss_mbedtls_mac_update(((sss_mbedtls_mac_t * ) context),(message),(messageLen)) +# define sss_host_mac_finish(context,mac,macLen) \ + sss_mbedtls_mac_finish(((sss_mbedtls_mac_t * ) context),(mac),(macLen)) +# define sss_host_mac_context_free(context) \ + sss_mbedtls_mac_context_free(((sss_mbedtls_mac_t * ) context)) + /* Host Call : md */ +# define sss_host_digest_context_init(context,session,algorithm,mode) \ + sss_mbedtls_digest_context_init(((sss_mbedtls_digest_t * ) context),((sss_mbedtls_session_t * ) session),(algorithm),(mode)) +# define sss_host_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_mbedtls_digest_one_go(((sss_mbedtls_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_host_digest_init(context) \ + sss_mbedtls_digest_init(((sss_mbedtls_digest_t * ) context)) +# define sss_host_digest_update(context,message,messageLen) \ + sss_mbedtls_digest_update(((sss_mbedtls_digest_t * ) context),(message),(messageLen)) +# define sss_host_digest_finish(context,digest,digestLen) \ + sss_mbedtls_digest_finish(((sss_mbedtls_digest_t * ) context),(digest),(digestLen)) +# define sss_host_digest_context_free(context) \ + sss_mbedtls_digest_context_free(((sss_mbedtls_digest_t * ) context)) + /* Host Call : rng */ +# define sss_host_rng_context_init(context,session) \ + sss_mbedtls_rng_context_init(((sss_mbedtls_rng_context_t * ) context),((sss_mbedtls_session_t * ) session)) +# define sss_host_rng_get_random(context,random_data,dataLen) \ + sss_mbedtls_rng_get_random(((sss_mbedtls_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_host_rng_context_free(context) \ + sss_mbedtls_rng_context_free(((sss_mbedtls_rng_context_t * ) context)) +# endif /* (SSS_HAVE_SSS == 1) */ +/* clang-format on */ +#endif /* SSS_HAVE_MBEDTLS */ +#ifdef __cplusplus +} // extern "C" +#endif /* __cplusplus */ + +#endif /* FSL_SSS_MBEDTLS_APIS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h new file mode 100644 index 00000000000..1d090753a04 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h @@ -0,0 +1,253 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_MBEDTLS_TYPES_H_ +#define SSS_APIS_INC_FSL_SSS_MBEDTLS_TYPES_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_MBEDTLS + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * @addtogroup sss_sw_mbedtls + * @{ + */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +#define SSS_SUBSYSTEM_TYPE_IS_MBEDTLS(subsystem) (subsystem == kType_SSS_mbedTLS) + +#define SSS_SESSION_TYPE_IS_MBEDTLS(session) (session && SSS_SUBSYSTEM_TYPE_IS_MBEDTLS(session->subsystem)) + +#define SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore) (keyStore && SSS_SESSION_TYPE_IS_MBEDTLS(keyStore->session)) + +#define SSS_OBJECT_TYPE_IS_MBEDTLS(pObject) (pObject && SSS_KEY_STORE_TYPE_IS_MBEDTLS(pObject->keyStore)) + +#define SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_MAC_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_RNG_CONTEXT_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_DIGEST_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +#define SSS_AEAD_TYPE_IS_MBEDTLS(context) (context && SSS_SESSION_TYPE_IS_MBEDTLS(context->session)) + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +struct _sss_mbedtls_session; + +typedef struct _sss_mbedtls_session +{ + /*! Indicates which security subsystem is selected to be used. */ + sss_type_t subsystem; + + mbedtls_entropy_context *entropy; + mbedtls_ctr_drbg_context *ctr_drbg; + +#ifdef MBEDTLS_FS_IO + /* Root Path for persitant key store */ + const char *szRootPath; +#endif +} sss_mbedtls_session_t; + +struct _sss_mbedtls_object; + +typedef struct _sss_mbedtls_key_store +{ + sss_mbedtls_session_t *session; + +#ifdef MBEDTLS_FS_IO + /*! Implementation specific part */ + struct _sss_mbedtls_object **objects; + uint32_t max_object_count; + + keyStoreTable_t *keystore_shadow; +#endif +} sss_mbedtls_key_store_t; + +typedef struct _sss_mbedtls_object +{ + /*! key store holding the data and other properties */ + sss_mbedtls_key_store_t *keyStore; + /*! Object types */ + uint32_t objectType; + uint32_t cipherType; + /*! Application specific key identifier. The keyId is kept in the key store + * along with the key data and other properties. */ + uint32_t keyId; + + /*! Implementation specific part */ + /** Contents are malloced, so must be freed */ + uint32_t contents_must_free : 1; + /** Type of key. Persistnet/trainsient @ref sss_key_object_mode_t */ + uint32_t keyMode : 3; + /** Max size allocated */ + size_t contents_max_size; + size_t contents_size; + size_t keyBitLen; + uint32_t user_id; + sss_mode_t purpose; + sss_access_permission_t accessRights; + /* malloced / referenced contents */ + void *contents; +} sss_mbedtls_object_t; + +typedef struct _sss_mbedtls_derive_key +{ + sss_mbedtls_session_t *session; + sss_mbedtls_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + +} sss_mbedtls_derive_key_t; + +typedef struct _sss_mbedtls_asymmetric +{ + sss_mbedtls_session_t *session; + sss_mbedtls_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + +} sss_mbedtls_asymmetric_t; + +typedef struct _sss_mbedtls_symmetric +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_mbedtls_session_t *session; + sss_mbedtls_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + mbedtls_cipher_context_t *cipher_ctx; + uint8_t cache_data[16]; + size_t cache_data_len; + +} sss_mbedtls_symmetric_t; + +typedef struct _sss_mbedtls_mac +{ + sss_mbedtls_session_t *session; + sss_mbedtls_object_t *keyObject; /*! Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + + /*! Implementation specific part */ + mbedtls_cipher_context_t *cipher_ctx; /*For init- update -finish*/ + mbedtls_md_context_t *HmacCtx; +} sss_mbedtls_mac_t; + +typedef struct _sss_mbedtls_aead +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_mbedtls_session_t *session; + sss_mbedtls_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + + /*! Implementation specific part */ + mbedtls_gcm_context *gcm_ctx; /*!< Reference to gcm context. */ + mbedtls_ccm_context *ccm_ctx; /*!< Reference to ccm context. */ + uint8_t *pNonce; /*!< Reference to IV. */ + size_t nonceLen; /*!< Store IV len. */ + const uint8_t *pCcm_aad; /*!< Reference to AAD */ + size_t ccm_aadLen; /*!< Store AAD len. */ + uint8_t *pCcm_data; /*!< Ref to CCM data dynamic allocated.. */ + size_t ccm_dataTotalLen; /*!< Store CCM data total len. */ + size_t ccm_dataoffset; /*!< Store CCM data offset. */ + uint8_t cache_data[16]; /*!< Cache for GCM data */ + size_t cache_data_len; /*!< Store GCM Cache len*/ +} sss_mbedtls_aead_t; + +typedef struct _sss_mbedtls_digest +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_mbedtls_session_t *session; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + /*! Full digest length per algorithm definition. This field is initialized along with algorithm. */ + size_t digestFullLen; + /*! Implementation specific part */ + mbedtls_md_context_t md_ctx; +} sss_mbedtls_digest_t; + +typedef struct +{ + sss_mbedtls_session_t *session; + +} sss_mbedtls_rng_context_t; + +#define sss_mbedtls_tunnel_t sss_tunnel_t + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +#ifdef MBEDTLS_FS_IO + +/** Store key inside persistant key store */ +sss_status_t ks_mbedtls_store_key(const sss_mbedtls_object_t *sss_key); + +sss_status_t ks_mbedtls_load_key(sss_mbedtls_object_t *sss_key, keyStoreTable_t *keystore_shadow, uint32_t extKeyId); + +sss_status_t ks_mbedtls_remove_key(const sss_mbedtls_object_t *sss_key); + +sss_status_t ks_mbedtls_fat_update(sss_mbedtls_key_store_t *keyStore); + +#endif /* MBEDTLS_FS_IO */ + +/* Low Level API Key object create */ +sss_status_t ks_mbedtls_key_object_create(sss_mbedtls_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t keyMode); + +/** @} */ + +#endif /* SSS_HAVE_MBEDTLS */ + +#endif /* SSS_APIS_INC_FSL_SSS_MBEDTLS_TYPES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h new file mode 100644 index 00000000000..b4e02131d2a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h @@ -0,0 +1,839 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FSL_SSS_OPENSSL_APIS_H +#define FSL_SSS_OPENSSL_APIS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_OPENSSL +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** + * @addtogroup sss_openssl_session + * @{ + */ +/** @copydoc sss_session_create + * + */ +sss_status_t sss_openssl_session_create(sss_openssl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_open + * + */ +sss_status_t sss_openssl_session_open(sss_openssl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_prop_get_u32 + * + */ +sss_status_t sss_openssl_session_prop_get_u32(sss_openssl_session_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_session_prop_get_au8 + * + */ +sss_status_t sss_openssl_session_prop_get_au8( + sss_openssl_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_session_close + * + */ +void sss_openssl_session_close(sss_openssl_session_t *session); + +/** @copydoc sss_session_delete + * + */ +void sss_openssl_session_delete(sss_openssl_session_t *session); + +/*! @} */ /* end of : sss_openssl_session */ + +/** + * @addtogroup sss_openssl_keyobj + * @{ + */ +/** @copydoc sss_key_object_init + * + */ +sss_status_t sss_openssl_key_object_init(sss_openssl_object_t *keyObject, sss_openssl_key_store_t *keyStore); + +/** @copydoc sss_key_object_allocate_handle + * + */ +sss_status_t sss_openssl_key_object_allocate_handle(sss_openssl_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); + +/** @copydoc sss_key_object_get_handle + * + */ +sss_status_t sss_openssl_key_object_get_handle(sss_openssl_object_t *keyObject, uint32_t keyId); + +/** @copydoc sss_key_object_set_user + * + */ +sss_status_t sss_openssl_key_object_set_user(sss_openssl_object_t *keyObject, uint32_t user, uint32_t options); + +/** @copydoc sss_key_object_set_purpose + * + */ +sss_status_t sss_openssl_key_object_set_purpose(sss_openssl_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** @copydoc sss_key_object_set_access + * + */ +sss_status_t sss_openssl_key_object_set_access(sss_openssl_object_t *keyObject, uint32_t access, uint32_t options); + +/** @copydoc sss_key_object_set_eccgfp_group + * + */ +sss_status_t sss_openssl_key_object_set_eccgfp_group(sss_openssl_object_t *keyObject, sss_eccgfp_group_t *group); + +/** @copydoc sss_key_object_get_user + * + */ +sss_status_t sss_openssl_key_object_get_user(sss_openssl_object_t *keyObject, uint32_t *user); + +/** @copydoc sss_key_object_get_purpose + * + */ +sss_status_t sss_openssl_key_object_get_purpose(sss_openssl_object_t *keyObject, sss_mode_t *purpose); + +/** @copydoc sss_key_object_get_access + * + */ +sss_status_t sss_openssl_key_object_get_access(sss_openssl_object_t *keyObject, uint32_t *access); + +/** @copydoc sss_key_object_free + * + */ +void sss_openssl_key_object_free(sss_openssl_object_t *keyObject); + +/*! @} */ /* end of : sss_openssl_keyobj */ + +/** + * @addtogroup sss_openssl_keyderive + * @{ + */ +/** @copydoc sss_derive_key_context_init + * + */ +sss_status_t sss_openssl_derive_key_context_init(sss_openssl_derive_key_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_derive_key_one_go +* +*/ +sss_status_t sss_openssl_derive_key_one_go(sss_openssl_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_sobj_one_go +* +*/ +sss_status_t sss_openssl_derive_key_sobj_one_go(sss_openssl_derive_key_t *context, + sss_openssl_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_go + * + */ +sss_status_t sss_openssl_derive_key_go(sss_openssl_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @copydoc sss_derive_key_dh + * + */ +sss_status_t sss_openssl_derive_key_dh(sss_openssl_derive_key_t *context, + sss_openssl_object_t *otherPartyKeyObject, + sss_openssl_object_t *derivedKeyObject); + +/** @copydoc sss_derive_key_context_free + * + */ +void sss_openssl_derive_key_context_free(sss_openssl_derive_key_t *context); + +/*! @} */ /* end of : sss_openssl_keyderive */ + +/** + * @addtogroup sss_openssl_keystore + * @{ + */ +/** @copydoc sss_key_store_context_init + * + */ +sss_status_t sss_openssl_key_store_context_init(sss_openssl_key_store_t *keyStore, sss_openssl_session_t *session); + +/** @copydoc sss_key_store_allocate + * + */ +sss_status_t sss_openssl_key_store_allocate(sss_openssl_key_store_t *keyStore, uint32_t keyStoreId); + +/** @copydoc sss_key_store_save + * + */ +sss_status_t sss_openssl_key_store_save(sss_openssl_key_store_t *keyStore); + +/** @copydoc sss_key_store_load + * + */ +sss_status_t sss_openssl_key_store_load(sss_openssl_key_store_t *keyStore); + +/** @copydoc sss_key_store_set_key + * + */ +sss_status_t sss_openssl_key_store_set_key(sss_openssl_key_store_t *keyStore, + sss_openssl_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @copydoc sss_key_store_generate_key + * + */ +sss_status_t sss_openssl_key_store_generate_key( + sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject, size_t keyBitLen, void *options); + +/** @copydoc sss_key_store_get_key + * + */ +sss_status_t sss_openssl_key_store_get_key(sss_openssl_key_store_t *keyStore, + sss_openssl_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen); + +/** @copydoc sss_key_store_open_key + * + */ +sss_status_t sss_openssl_key_store_open_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject); + +/** @copydoc sss_key_store_freeze_key + * + */ +sss_status_t sss_openssl_key_store_freeze_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject); + +/** @copydoc sss_key_store_erase_key + * + */ +sss_status_t sss_openssl_key_store_erase_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject); + +/** @copydoc sss_key_store_context_free + * + */ +void sss_openssl_key_store_context_free(sss_openssl_key_store_t *keyStore); + +/*! @} */ /* end of : sss_openssl_keystore */ + +/** + * @addtogroup sss_openssl_asym + * @{ + */ +/** @copydoc sss_asymmetric_context_init + * + */ +sss_status_t sss_openssl_asymmetric_context_init(sss_openssl_asymmetric_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_asymmetric_encrypt + * + */ +sss_status_t sss_openssl_asymmetric_encrypt( + sss_openssl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_decrypt + * + */ +sss_status_t sss_openssl_asymmetric_decrypt( + sss_openssl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_sign_digest + * + */ +sss_status_t sss_openssl_asymmetric_sign_digest( + sss_openssl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @copydoc sss_asymmetric_verify_digest + * + */ +sss_status_t sss_openssl_asymmetric_verify_digest( + sss_openssl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @copydoc sss_asymmetric_context_free + * + */ +void sss_openssl_asymmetric_context_free(sss_openssl_asymmetric_t *context); + +/*! @} */ /* end of : sss_openssl_asym */ + +/** + * @addtogroup sss_openssl_symm + * @{ + */ +/** @copydoc sss_symmetric_context_init + * + */ +sss_status_t sss_openssl_symmetric_context_init(sss_openssl_symmetric_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_cipher_one_go + * + */ +sss_status_t sss_openssl_cipher_one_go(sss_openssl_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen); + +/** @copydoc sss_cipher_init + * + */ +sss_status_t sss_openssl_cipher_init(sss_openssl_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @copydoc sss_cipher_update + * + */ +sss_status_t sss_openssl_cipher_update( + sss_openssl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_finish + * + */ +sss_status_t sss_openssl_cipher_finish( + sss_openssl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_crypt_ctr + * + */ +sss_status_t sss_openssl_cipher_crypt_ctr(sss_openssl_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @copydoc sss_symmetric_context_free + * + */ +void sss_openssl_symmetric_context_free(sss_openssl_symmetric_t *context); + +/*! @} */ /* end of : sss_openssl_symm */ + +/** + * @addtogroup sss_openssl_aead + * @{ + */ +/** @copydoc sss_aead_context_init + * + */ +sss_status_t sss_openssl_aead_context_init(sss_openssl_aead_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_aead_one_go + * + */ +sss_status_t sss_openssl_aead_one_go(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_init + * + */ +sss_status_t sss_openssl_aead_init( + sss_openssl_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); + +/** @copydoc sss_aead_update_aad + * + */ +sss_status_t sss_openssl_aead_update_aad(sss_openssl_aead_t *context, const uint8_t *aadData, size_t aadDataLen); + +/** @copydoc sss_aead_update + * + */ +sss_status_t sss_openssl_aead_update( + sss_openssl_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_aead_finish + * + */ +sss_status_t sss_openssl_aead_finish(sss_openssl_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_context_free + * + */ +void sss_openssl_aead_context_free(sss_openssl_aead_t *context); + +/*! @} */ /* end of : sss_openssl_aead */ + +/** + * @addtogroup sss_openssl_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_openssl_mac_context_init(sss_openssl_mac_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_openssl_mac_one_go( + sss_openssl_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_init + * + */ +sss_status_t sss_openssl_mac_init(sss_openssl_mac_t *context); + +/** @copydoc sss_mac_update + * + */ +sss_status_t sss_openssl_mac_update(sss_openssl_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_mac_finish + * + */ +sss_status_t sss_openssl_mac_finish(sss_openssl_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_openssl_mac_context_free(sss_openssl_mac_t *context); + +/*! @} */ /* end of : sss_openssl_mac */ + +/** + * @addtogroup sss_openssl_md + * @{ + */ +/** @copydoc sss_digest_context_init + * + */ +sss_status_t sss_openssl_digest_context_init( + sss_openssl_digest_t *context, sss_openssl_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_digest_one_go + * + */ +sss_status_t sss_openssl_digest_one_go( + sss_openssl_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_init + * + */ +sss_status_t sss_openssl_digest_init(sss_openssl_digest_t *context); + +/** @copydoc sss_digest_update + * + */ +sss_status_t sss_openssl_digest_update(sss_openssl_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_digest_finish + * + */ +sss_status_t sss_openssl_digest_finish(sss_openssl_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_context_free + * + */ +void sss_openssl_digest_context_free(sss_openssl_digest_t *context); + +/*! @} */ /* end of : sss_openssl_md */ + +/** + * @addtogroup sss_openssl_rng + * @{ + */ +/** @copydoc sss_rng_context_init + * + */ +sss_status_t sss_openssl_rng_context_init(sss_openssl_rng_context_t *context, sss_openssl_session_t *session); + +/** @copydoc sss_rng_get_random + * + */ +sss_status_t sss_openssl_rng_get_random(sss_openssl_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** @copydoc sss_rng_context_free + * + */ +sss_status_t sss_openssl_rng_context_free(sss_openssl_rng_context_t *context); + +/*! @} */ /* end of : sss_openssl_rng */ + +/* clang-format off */ +# if (SSS_HAVE_SSS == 1) + /* Direct Call : session */ +# define sss_session_create(session,subsystem,application_id,connection_type,connectionData) \ + sss_openssl_session_create(((sss_openssl_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_open(session,subsystem,application_id,connection_type,connectionData) \ + sss_openssl_session_open(((sss_openssl_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_prop_get_u32(session,property,pValue) \ + sss_openssl_session_prop_get_u32(((sss_openssl_session_t * ) session),(property),(pValue)) +# define sss_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_openssl_session_prop_get_au8(((sss_openssl_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_session_close(session) \ + sss_openssl_session_close(((sss_openssl_session_t * ) session)) +# define sss_session_delete(session) \ + sss_openssl_session_delete(((sss_openssl_session_t * ) session)) + /* Direct Call : keyobj */ +# define sss_key_object_init(keyObject,keyStore) \ + sss_openssl_key_object_init(((sss_openssl_object_t * ) keyObject),((sss_openssl_key_store_t * ) keyStore)) +# define sss_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_openssl_key_object_allocate_handle(((sss_openssl_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_key_object_get_handle(keyObject,keyId) \ + sss_openssl_key_object_get_handle(((sss_openssl_object_t * ) keyObject),(keyId)) +# define sss_key_object_set_user(keyObject,user,options) \ + sss_openssl_key_object_set_user(((sss_openssl_object_t * ) keyObject),(user),(options)) +# define sss_key_object_set_purpose(keyObject,purpose,options) \ + sss_openssl_key_object_set_purpose(((sss_openssl_object_t * ) keyObject),(purpose),(options)) +# define sss_key_object_set_access(keyObject,access,options) \ + sss_openssl_key_object_set_access(((sss_openssl_object_t * ) keyObject),(access),(options)) +# define sss_key_object_set_eccgfp_group(keyObject,group) \ + sss_openssl_key_object_set_eccgfp_group(((sss_openssl_object_t * ) keyObject),(group)) +# define sss_key_object_get_user(keyObject,user) \ + sss_openssl_key_object_get_user(((sss_openssl_object_t * ) keyObject),(user)) +# define sss_key_object_get_purpose(keyObject,purpose) \ + sss_openssl_key_object_get_purpose(((sss_openssl_object_t * ) keyObject),(purpose)) +# define sss_key_object_get_access(keyObject,access) \ + sss_openssl_key_object_get_access(((sss_openssl_object_t * ) keyObject),(access)) +# define sss_key_object_free(keyObject) \ + sss_openssl_key_object_free(((sss_openssl_object_t * ) keyObject)) + /* Direct Call : keyderive */ +# define sss_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_derive_key_context_init(((sss_openssl_derive_key_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_derive_key_one_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen) \ + sss_openssl_derive_key_one_go(((sss_openssl_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_openssl_object_t * ) derivedKeyObject),(deriveDataLen)) +# define sss_derive_key_sobj_one_go(context,saltKeyObject,info,infoLen,derivedKeyObject,deriveDataLen) \ + sss_openssl_derive_key_sobj_one_go(((sss_openssl_derive_key_t * ) context),((sss_openssl_object_t *)saltKeyObject),(info),(infoLen),((sss_openssl_object_t * ) derivedKeyObject),(deriveDataLen)) +# define sss_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_openssl_derive_key_go(((sss_openssl_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_openssl_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_openssl_derive_key_dh(((sss_openssl_derive_key_t * ) context),((sss_openssl_object_t * ) otherPartyKeyObject),((sss_openssl_object_t * ) derivedKeyObject)) +# define sss_derive_key_context_free(context) \ + sss_openssl_derive_key_context_free(((sss_openssl_derive_key_t * ) context)) + /* Direct Call : keystore */ +# define sss_key_store_context_init(keyStore,session) \ + sss_openssl_key_store_context_init(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_session_t * ) session)) +# define sss_key_store_allocate(keyStore,keyStoreId) \ + sss_openssl_key_store_allocate(((sss_openssl_key_store_t * ) keyStore),(keyStoreId)) +# define sss_key_store_save(keyStore) \ + sss_openssl_key_store_save(((sss_openssl_key_store_t * ) keyStore)) +# define sss_key_store_load(keyStore) \ + sss_openssl_key_store_load(((sss_openssl_key_store_t * ) keyStore)) +# define sss_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_openssl_key_store_set_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_openssl_key_store_generate_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_openssl_key_store_get_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_key_store_open_key(keyStore,keyObject) \ + sss_openssl_key_store_open_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_key_store_freeze_key(keyStore,keyObject) \ + sss_openssl_key_store_freeze_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_key_store_erase_key(keyStore,keyObject) \ + sss_openssl_key_store_erase_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_key_store_context_free(keyStore) \ + sss_openssl_key_store_context_free(((sss_openssl_key_store_t * ) keyStore)) + /* Direct Call : asym */ +# define sss_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_asymmetric_context_init(((sss_openssl_asymmetric_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_openssl_asymmetric_encrypt(((sss_openssl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_openssl_asymmetric_decrypt(((sss_openssl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_openssl_asymmetric_sign_digest(((sss_openssl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_openssl_asymmetric_verify_digest(((sss_openssl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_context_free(context) \ + sss_openssl_asymmetric_context_free(((sss_openssl_asymmetric_t * ) context)) + /* Direct Call : symm */ +# define sss_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_symmetric_context_init(((sss_openssl_symmetric_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_openssl_cipher_one_go(((sss_openssl_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_cipher_init(context,iv,ivLen) \ + sss_openssl_cipher_init(((sss_openssl_symmetric_t * ) context),(iv),(ivLen)) +# define sss_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_openssl_cipher_update(((sss_openssl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_openssl_cipher_finish(((sss_openssl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_openssl_cipher_crypt_ctr(((sss_openssl_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_symmetric_context_free(context) \ + sss_openssl_symmetric_context_free(((sss_openssl_symmetric_t * ) context)) + /* Direct Call : aead */ +# define sss_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_aead_context_init(((sss_openssl_aead_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_openssl_aead_one_go(((sss_openssl_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_openssl_aead_init(((sss_openssl_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_aead_update_aad(context,aadData,aadDataLen) \ + sss_openssl_aead_update_aad(((sss_openssl_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_openssl_aead_update(((sss_openssl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_openssl_aead_finish(((sss_openssl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_aead_context_free(context) \ + sss_openssl_aead_context_free(((sss_openssl_aead_t * ) context)) + /* Direct Call : mac */ +# define sss_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_mac_context_init(((sss_openssl_mac_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_openssl_mac_one_go(((sss_openssl_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_mac_init(context) \ + sss_openssl_mac_init(((sss_openssl_mac_t * ) context)) +# define sss_mac_update(context,message,messageLen) \ + sss_openssl_mac_update(((sss_openssl_mac_t * ) context),(message),(messageLen)) +# define sss_mac_finish(context,mac,macLen) \ + sss_openssl_mac_finish(((sss_openssl_mac_t * ) context),(mac),(macLen)) +# define sss_mac_context_free(context) \ + sss_openssl_mac_context_free(((sss_openssl_mac_t * ) context)) + /* Direct Call : md */ +# define sss_digest_context_init(context,session,algorithm,mode) \ + sss_openssl_digest_context_init(((sss_openssl_digest_t * ) context),((sss_openssl_session_t * ) session),(algorithm),(mode)) +# define sss_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_openssl_digest_one_go(((sss_openssl_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_digest_init(context) \ + sss_openssl_digest_init(((sss_openssl_digest_t * ) context)) +# define sss_digest_update(context,message,messageLen) \ + sss_openssl_digest_update(((sss_openssl_digest_t * ) context),(message),(messageLen)) +# define sss_digest_finish(context,digest,digestLen) \ + sss_openssl_digest_finish(((sss_openssl_digest_t * ) context),(digest),(digestLen)) +# define sss_digest_context_free(context) \ + sss_openssl_digest_context_free(((sss_openssl_digest_t * ) context)) + /* Direct Call : rng */ +# define sss_rng_context_init(context,session) \ + sss_openssl_rng_context_init(((sss_openssl_rng_context_t * ) context),((sss_openssl_session_t * ) session)) +# define sss_rng_get_random(context,random_data,dataLen) \ + sss_openssl_rng_get_random(((sss_openssl_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_rng_context_free(context) \ + sss_openssl_rng_context_free(((sss_openssl_rng_context_t * ) context)) +# endif /* (SSS_HAVE_SSS == 1) */ +# if (SSS_HAVE_MBEDTLS == 0) + /* Host Call : session */ +# define sss_host_session_create(session,subsystem,application_id,connection_type,connectionData) \ + sss_openssl_session_create(((sss_openssl_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_host_session_open(session,subsystem,application_id,connection_type,connectionData) \ + sss_openssl_session_open(((sss_openssl_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_host_session_prop_get_u32(session,property,pValue) \ + sss_openssl_session_prop_get_u32(((sss_openssl_session_t * ) session),(property),(pValue)) +# define sss_host_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_openssl_session_prop_get_au8(((sss_openssl_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_host_session_close(session) \ + sss_openssl_session_close(((sss_openssl_session_t * ) session)) +# define sss_host_session_delete(session) \ + sss_openssl_session_delete(((sss_openssl_session_t * ) session)) + /* Host Call : keyobj */ +# define sss_host_key_object_init(keyObject,keyStore) \ + sss_openssl_key_object_init(((sss_openssl_object_t * ) keyObject),((sss_openssl_key_store_t * ) keyStore)) +# define sss_host_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_openssl_key_object_allocate_handle(((sss_openssl_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_host_key_object_get_handle(keyObject,keyId) \ + sss_openssl_key_object_get_handle(((sss_openssl_object_t * ) keyObject),(keyId)) +# define sss_host_key_object_set_user(keyObject,user,options) \ + sss_openssl_key_object_set_user(((sss_openssl_object_t * ) keyObject),(user),(options)) +# define sss_host_key_object_set_purpose(keyObject,purpose,options) \ + sss_openssl_key_object_set_purpose(((sss_openssl_object_t * ) keyObject),(purpose),(options)) +# define sss_host_key_object_set_access(keyObject,access,options) \ + sss_openssl_key_object_set_access(((sss_openssl_object_t * ) keyObject),(access),(options)) +# define sss_host_key_object_set_eccgfp_group(keyObject,group) \ + sss_openssl_key_object_set_eccgfp_group(((sss_openssl_object_t * ) keyObject),(group)) +# define sss_host_key_object_get_user(keyObject,user) \ + sss_openssl_key_object_get_user(((sss_openssl_object_t * ) keyObject),(user)) +# define sss_host_key_object_get_purpose(keyObject,purpose) \ + sss_openssl_key_object_get_purpose(((sss_openssl_object_t * ) keyObject),(purpose)) +# define sss_host_key_object_get_access(keyObject,access) \ + sss_openssl_key_object_get_access(((sss_openssl_object_t * ) keyObject),(access)) +# define sss_host_key_object_free(keyObject) \ + sss_openssl_key_object_free(((sss_openssl_object_t * ) keyObject)) + /* Host Call : keyderive */ +# define sss_host_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_derive_key_context_init(((sss_openssl_derive_key_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_derive_key_one_go(context,saltData,saltLen,saltKeyObject,info,infoLen,derivedKeyObject,deriveDataLen) \ + sss_openssl_derive_key_go(((sss_openssl_derive_key_t * ) context),(saltData),(saltLen),((sss_openssl_object_t *)saltKeyObject),(info),(infoLen),((sss_openssl_object_t * ) derivedKeyObject),(deriveDataLen)) +# define sss_host_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_openssl_derive_key_go(((sss_openssl_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_openssl_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_host_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_openssl_derive_key_dh(((sss_openssl_derive_key_t * ) context),((sss_openssl_object_t * ) otherPartyKeyObject),((sss_openssl_object_t * ) derivedKeyObject)) +# define sss_host_derive_key_context_free(context) \ + sss_openssl_derive_key_context_free(((sss_openssl_derive_key_t * ) context)) + /* Host Call : keystore */ +# define sss_host_key_store_context_init(keyStore,session) \ + sss_openssl_key_store_context_init(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_session_t * ) session)) +# define sss_host_key_store_allocate(keyStore,keyStoreId) \ + sss_openssl_key_store_allocate(((sss_openssl_key_store_t * ) keyStore),(keyStoreId)) +# define sss_host_key_store_save(keyStore) \ + sss_openssl_key_store_save(((sss_openssl_key_store_t * ) keyStore)) +# define sss_host_key_store_load(keyStore) \ + sss_openssl_key_store_load(((sss_openssl_key_store_t * ) keyStore)) +# define sss_host_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_openssl_key_store_set_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_host_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_openssl_key_store_generate_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_host_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_openssl_key_store_get_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_host_key_store_open_key(keyStore,keyObject) \ + sss_openssl_key_store_open_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_host_key_store_freeze_key(keyStore,keyObject) \ + sss_openssl_key_store_freeze_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_host_key_store_erase_key(keyStore,keyObject) \ + sss_openssl_key_store_erase_key(((sss_openssl_key_store_t * ) keyStore),((sss_openssl_object_t * ) keyObject)) +# define sss_host_key_store_context_free(keyStore) \ + sss_openssl_key_store_context_free(((sss_openssl_key_store_t * ) keyStore)) + /* Host Call : asym */ +# define sss_host_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_asymmetric_context_init(((sss_openssl_asymmetric_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_openssl_asymmetric_encrypt(((sss_openssl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_openssl_asymmetric_decrypt(((sss_openssl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_openssl_asymmetric_sign_digest(((sss_openssl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_openssl_asymmetric_verify_digest(((sss_openssl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_context_free(context) \ + sss_openssl_asymmetric_context_free(((sss_openssl_asymmetric_t * ) context)) + /* Host Call : symm */ +# define sss_host_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_symmetric_context_init(((sss_openssl_symmetric_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_openssl_cipher_one_go(((sss_openssl_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_host_cipher_init(context,iv,ivLen) \ + sss_openssl_cipher_init(((sss_openssl_symmetric_t * ) context),(iv),(ivLen)) +# define sss_host_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_openssl_cipher_update(((sss_openssl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_openssl_cipher_finish(((sss_openssl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_openssl_cipher_crypt_ctr(((sss_openssl_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_host_symmetric_context_free(context) \ + sss_openssl_symmetric_context_free(((sss_openssl_symmetric_t * ) context)) + /* Host Call : aead */ +# define sss_host_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_aead_context_init(((sss_openssl_aead_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_openssl_aead_one_go(((sss_openssl_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_host_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_openssl_aead_init(((sss_openssl_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_host_aead_update_aad(context,aadData,aadDataLen) \ + sss_openssl_aead_update_aad(((sss_openssl_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_host_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_openssl_aead_update(((sss_openssl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_openssl_aead_finish(((sss_openssl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_host_aead_context_free(context) \ + sss_openssl_aead_context_free(((sss_openssl_aead_t * ) context)) + /* Host Call : mac */ +# define sss_host_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_openssl_mac_context_init(((sss_openssl_mac_t * ) context),((sss_openssl_session_t * ) session),((sss_openssl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_openssl_mac_one_go(((sss_openssl_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_host_mac_init(context) \ + sss_openssl_mac_init(((sss_openssl_mac_t * ) context)) +# define sss_host_mac_update(context,message,messageLen) \ + sss_openssl_mac_update(((sss_openssl_mac_t * ) context),(message),(messageLen)) +# define sss_host_mac_finish(context,mac,macLen) \ + sss_openssl_mac_finish(((sss_openssl_mac_t * ) context),(mac),(macLen)) +# define sss_host_mac_context_free(context) \ + sss_openssl_mac_context_free(((sss_openssl_mac_t * ) context)) + /* Host Call : md */ +# define sss_host_digest_context_init(context,session,algorithm,mode) \ + sss_openssl_digest_context_init(((sss_openssl_digest_t * ) context),((sss_openssl_session_t * ) session),(algorithm),(mode)) +# define sss_host_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_openssl_digest_one_go(((sss_openssl_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_host_digest_init(context) \ + sss_openssl_digest_init(((sss_openssl_digest_t * ) context)) +# define sss_host_digest_update(context,message,messageLen) \ + sss_openssl_digest_update(((sss_openssl_digest_t * ) context),(message),(messageLen)) +# define sss_host_digest_finish(context,digest,digestLen) \ + sss_openssl_digest_finish(((sss_openssl_digest_t * ) context),(digest),(digestLen)) +# define sss_host_digest_context_free(context) \ + sss_openssl_digest_context_free(((sss_openssl_digest_t * ) context)) + /* Host Call : rng */ +# define sss_host_rng_context_init(context,session) \ + sss_openssl_rng_context_init(((sss_openssl_rng_context_t * ) context),((sss_openssl_session_t * ) session)) +# define sss_host_rng_get_random(context,random_data,dataLen) \ + sss_openssl_rng_get_random(((sss_openssl_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_host_rng_context_free(context) \ + sss_openssl_rng_context_free(((sss_openssl_rng_context_t * ) context)) +# endif /* (SSS_HAVE_SSS == 1) */ +/* clang-format on */ +#endif /* SSS_HAVE_OPENSSL */ +#ifdef __cplusplus +} // extern "C" +#endif /* __cplusplus */ + +#endif /* FSL_SSS_OPENSSL_APIS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h new file mode 100644 index 00000000000..f76bf5b39c0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h @@ -0,0 +1,239 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_OPENSSL_TYPES_H_ +#define SSS_APIS_INC_FSL_SSS_OPENSSL_TYPES_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_OPENSSL + +#include +#include +#include +#include +/** + * @addtogroup sss_sw_openssl + * @{ + */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +#define SSS_SUBSYSTEM_TYPE_IS_OPENSSL(subsystem) (subsystem == kType_SSS_OpenSSL) + +#define SSS_SESSION_TYPE_IS_OPENSSL(session) (session && SSS_SUBSYSTEM_TYPE_IS_OPENSSL(session->subsystem)) + +#define SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore) (keyStore && SSS_SESSION_TYPE_IS_OPENSSL(keyStore->session)) + +#define SSS_OBJECT_TYPE_IS_OPENSSL(pObject) (pObject && SSS_KEY_STORE_TYPE_IS_OPENSSL(pObject->keyStore)) + +#define SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_SYMMETRIC_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_MAC_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_RNG_CONTEXT_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_DIGEST_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +#define SSS_AEAD_TYPE_IS_OPENSSL(context) (context && SSS_SESSION_TYPE_IS_OPENSSL(context->session)) + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +struct _sss_openssl_session; + +typedef struct _sss_openssl_session +{ + /*! Indicates which security subsystem is selected to be used. */ + sss_type_t subsystem; + + /* Root Path for persitant key store */ + const char *szRootPath; +} sss_openssl_session_t; + +struct _sss_openssl_object; + +typedef struct _sss_openssl_key_store +{ + sss_openssl_session_t *session; + + /*! Implementation specific part */ + struct _sss_openssl_object **objects; + uint32_t max_object_count; + + keyStoreTable_t *keystore_shadow; + +} sss_openssl_key_store_t; + +typedef struct _sss_openssl_object +{ + /*! key store holding the data and other properties */ + sss_openssl_key_store_t *keyStore; + /*! Object types */ + uint32_t objectType; + uint32_t cipherType; + /*! Application specific key identifier. The keyId is kept in the key store + * along with the key data and other properties. */ + uint32_t keyId; + + /*! Implementation specific part */ + /** Contents are malloced, so must be freed */ + uint32_t contents_must_free : 1; + /** Type of key. Persistnet/trainsient @ref sss_key_object_mode_t */ + uint32_t keyMode : 3; + /** Max size allocated */ + size_t contents_max_size; + size_t contents_size; + size_t keyBitLen; + uint32_t user_id; + sss_mode_t purpose; + sss_access_permission_t accessRights; + /* malloced / referenced contents */ + void *contents; +} sss_openssl_object_t; + +typedef struct _sss_openssl_derive_key +{ + sss_openssl_session_t *session; + sss_openssl_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + +} sss_openssl_derive_key_t; + +typedef struct _sss_openssl_asymmetric +{ + sss_openssl_session_t *session; + sss_openssl_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + +} sss_openssl_asymmetric_t; + +typedef struct _sss_openssl_symmetric +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_openssl_session_t *session; + sss_openssl_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + EVP_CIPHER_CTX *cipher_ctx; + uint8_t cache_data[16]; + size_t cache_data_len; +} sss_openssl_symmetric_t; + +typedef struct +{ + sss_openssl_session_t *session; + sss_openssl_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ + CMAC_CTX *cmac_ctx; + HMAC_CTX *hmac_ctx; +} sss_openssl_mac_t; + +typedef struct _sss_openssl_aead +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_openssl_session_t *session; + sss_openssl_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + + /*! Implementation specific part */ + EVP_CIPHER_CTX *aead_ctx; /*!< Reference to aead context. */ + uint8_t cache_data[16]; /*!< Cache for GCM data */ + size_t cache_data_len; /*!< Store GCM Cache len*/ + uint8_t *pCcm_data; /*!< Ref to CCM data dynamic allocated.. */ + size_t ccm_dataTotalLen; /*!< Store CCM data total len. */ + size_t ccm_dataoffset; /*!< Store CCM data offset. */ + uint8_t *pCcm_tag; /*!< Reference to tag. */ + size_t ccm_tagLen; /*!< Store tag len. */ + const uint8_t *pCcm_aad; /*!< Reference to AAD */ + size_t ccm_aadLen; /*!< Store AAD len. */ + const uint8_t *pCcm_iv; /*!< Reference to IV. */ + size_t ccm_ivLen; /*!< Store IV len. */ +} sss_openssl_aead_t; + +typedef struct _sss_openssl_digest +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_openssl_session_t *session; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + /*! Full digest length per algorithm definition. This field is initialized along with algorithm. */ + size_t digestFullLen; + /*! Implementation specific part */ + EVP_MD_CTX *mdctx; +} sss_openssl_digest_t; + +typedef struct +{ + sss_openssl_session_t *session; +} sss_openssl_rng_context_t; + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** Similar to @ref sss_openssl_asymmetric_sign_digest, +* +* but hashing/digest done by openssl +*/ +sss_status_t sss_openssl_asymmetric_sign( + sss_openssl_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t *signatureLen); + +/** Similar to @ref sss_openssl_asymmetric_verify_digest, +* but hashing/digest done by openssl +* +*/ +sss_status_t sss_openssl_asymmetric_verify( + sss_openssl_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t signatureLen); + +/** Store key inside persistant key store */ +sss_status_t ks_openssl_store_key(const sss_openssl_object_t *sss_key); + +sss_status_t ks_openssl_load_key(sss_openssl_object_t *sss_key, keyStoreTable_t *keystore_shadow, uint32_t extKeyId); + +sss_status_t ks_openssl_fat_update(sss_openssl_key_store_t *keyStore); + +sss_status_t ks_openssl_remove_key(const sss_openssl_object_t *sss_key); + +sss_status_t sss_openssl_key_object_allocate(sss_openssl_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t keyMode); + +/** @} */ + +#endif /* SSS_HAVE_OPENSSL */ + +#endif /* SSS_APIS_INC_FSL_SSS_OPENSSL_TYPES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h new file mode 100644 index 00000000000..5edff48590e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h @@ -0,0 +1,221 @@ +/* + * + * Copyright 2019,2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +/** @file */ + +#ifndef _FSL_SSS_POLICY_H_ +#define _FSL_SSS_POLICY_H_ + +#if !defined(SSS_CONFIG_FILE) +#include "fsl_sss_config.h" +#else +#include SSS_CONFIG_FILE +#endif + +#include "fsl_sss_types.h" +//#include + +/** @defgroup sss_policy Policy + * + * Policies to restrict and control sessions and objects. + */ + +/** @addtogroup sss_policy + * @{ */ + +/** Type of policy */ +typedef enum +{ + /** No policy applied */ + KPolicy_None, + /** Policy related to session. @see sss_policy_session_u */ + KPolicy_Session, + /** Policy related to key. @see sss_policy_key_u */ + KPolicy_Sym_Key, + KPolicy_Asym_Key, + KPolicy_UserID, + KPolicy_File, + KPolicy_Counter, + KPolicy_PCR, + KPolicy_Common, + KPolicy_Common_PCR_Value, +} sss_policy_type_u; + +/** Policy applicable to a session */ +typedef struct +{ + /** Number of operations permitted in a session */ + uint16_t maxOperationsInSession; + /** Session can be used for this much time, in seconds */ + uint16_t maxDurationOfSession_sec; + /** Whether maxOperationsInSession is set. + * This is to ensure '0 == maxOperationsInSession' does not get set + * by middleware. */ + uint8_t has_MaxOperationsInSession : 1; + /** Whether maxOperationsInSession is set. + * This is to ensure '0 == maxDurationOfSession_sec' does not get set + * by middleware. */ + uint8_t has_MaxDurationOfSession_sec : 1; + /** Whether this session can be refreshed without losing context. + * And also reset maxDurationOfSession_sec / maxOperationsInSession */ + uint8_t allowRefresh : 1; +} sss_policy_session_u; + +/** Policies applicable to Symmetric KEY */ +typedef struct +{ + /** Allow signature generation */ + uint8_t can_Sign : 1; + /** Allow signature verification */ + uint8_t can_Verify : 1; + /** Allow encryption */ + uint8_t can_Encrypt : 1; + /** Allow decryption */ + uint8_t can_Decrypt : 1; + /** Allow key derivation */ + uint8_t can_KD : 1; + /** Allow key wrapping */ + uint8_t can_Wrap : 1; + /** Allow to write the object */ + uint8_t can_Write : 1; + /** Allow to (re)generate the object */ + uint8_t can_Gen : 1; + /** Allow to perform DESFire authentication */ + uint8_t can_Desfire_Auth : 1; + /** Allow to dump DESFire session keys */ + uint8_t can_Desfire_Dump : 1; + /** Allow to imported or exported */ + uint8_t can_Import_Export : 1; +#if 1 // SSS_HAVE_SE05X_VER_GTE_06_00 + /** Forbid derived output */ + uint8_t forbid_Derived_Output : 1; +#endif + /** Allow kdf(prf) external random */ + uint8_t allow_kdf_ext_rnd : 1; +} sss_policy_sym_key_u; + +/** Policies applicable to Asymmetric KEY */ +typedef struct +{ + /** Allow signature generation */ + uint8_t can_Sign : 1; + /** Allow signature verification */ + uint8_t can_Verify : 1; + /** Allow encryption */ + uint8_t can_Encrypt : 1; + /** Allow decryption */ + uint8_t can_Decrypt : 1; + /** Allow key derivation */ + uint8_t can_KD : 1; + /** Allow key wrapping */ + uint8_t can_Wrap : 1; + /** Allow to write the object */ + uint8_t can_Write : 1; + /** Allow to (re)generate the object */ + uint8_t can_Gen : 1; + /** Allow to imported or exported */ + uint8_t can_Import_Export : 1; + /** Allow key agreement */ + uint8_t can_KA : 1; + /** Allow to read the object */ + uint8_t can_Read : 1; + /** Allow to attest an object */ + uint8_t can_Attest : 1; +#if 1 // SSS_HAVE_SE05X_VER_GTE_06_00 + /** Forbid derived output */ + uint8_t forbid_Derived_Output : 1; +#endif +} sss_policy_asym_key_u; + +/** All policies related to secure object type File */ +typedef struct +{ + /** Allow to write the object */ + uint8_t can_Write : 1; + /** Allow to read the object */ + uint8_t can_Read : 1; +} sss_policy_file_u; + +/** All policies related to secure object type Counter */ +typedef struct +{ + /** Allow to write the object */ + uint8_t can_Write : 1; + /** Allow to read the object */ + uint8_t can_Read : 1; +} sss_policy_counter_u; + +/** All policies related to secure object type PCR */ +typedef struct +{ + /** Allow to write the object */ + uint8_t can_Write : 1; + /** Allow to read the object */ + uint8_t can_Read : 1; +} sss_policy_pcr_u; + +/** All policies related to secure object type UserID */ +typedef struct +{ + /** Allow to write the object */ + uint8_t can_Write : 1; +} sss_policy_userid_u; + +/** Common Policies for all object types */ +typedef struct +{ + /** Forbid all operations */ + uint8_t forbid_All : 1; + /** Allow to delete the object */ + uint8_t can_Delete : 1; + /** Require having secure messaging enabled with encryption and integrity on the command */ + uint8_t req_Sm : 1; +} sss_policy_common_u; + +/** Common PCR Value Policies for all object types */ +typedef struct +{ + /** PCR object ID */ + uint32_t pcrObjId; + /** Expected value of the PCR */ + uint8_t pcrExpectedValue[32]; +} sss_policy_common_pcr_value_u; + +/** Unique/individual policy. + * For any operation, you need array of sss_policy_u. + */ +typedef struct +{ + /** Secure Object Type */ + sss_policy_type_u type; + /** Auth ID for each Object Policy, invalid for session policy type == KPolicy_Session*/ + uint32_t auth_obj_id; + /** Union of applicable policies based on the type of object + */ + union { + sss_policy_file_u file; + sss_policy_counter_u counter; + sss_policy_pcr_u pcr; + sss_policy_sym_key_u symmkey; + sss_policy_asym_key_u asymmkey; + sss_policy_userid_u pin; + sss_policy_common_u common; + sss_policy_common_pcr_value_u common_pcr_value; + sss_policy_session_u session; + } policy; +} sss_policy_u; + +/** An array of policies @ref sss_policy_u */ +typedef struct +{ + /** Array of unique policies, this needs to be allocated based nPolicies */ + const sss_policy_u *policies[SSS_POLICY_COUNT_MAX]; + /** Number of policies */ + size_t nPolicies; +} sss_policy_t; + +/** @} */ + +#endif /* _FSL_SSS_POLICY_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h new file mode 100644 index 00000000000..b0937f8f542 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h @@ -0,0 +1,781 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ + +#ifndef FSL_SSS_SE05X_APIS_H +#define FSL_SSS_SE05X_APIS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** + * @addtogroup sss_se05x_session + * @{ + */ +/** @copydoc sss_session_create + * + */ +sss_status_t sss_se05x_session_create(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_open + * + */ +sss_status_t sss_se05x_session_open(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_prop_get_u32 + * + */ +sss_status_t sss_se05x_session_prop_get_u32(sss_se05x_session_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_session_prop_get_au8 + * + */ +sss_status_t sss_se05x_session_prop_get_au8( + sss_se05x_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_session_close + * + */ +void sss_se05x_session_close(sss_se05x_session_t *session); + +/** @copydoc sss_session_delete + * + */ +void sss_se05x_session_delete(sss_se05x_session_t *session); + +/*! @} */ /* end of : sss_se05x_session */ + +/** + * @addtogroup sss_se05x_keyobj + * @{ + */ +/** @copydoc sss_key_object_init + * + */ +sss_status_t sss_se05x_key_object_init(sss_se05x_object_t *keyObject, sss_se05x_key_store_t *keyStore); + +/** @copydoc sss_key_object_allocate_handle + * + * On SE050, the memory get reserved only when the actual object is created and + * hence there is no memory reservation happening in this API call. but + * internally it checks if the object already exists or not . if the object is + * already existing it returns a failure. + * + */ +sss_status_t sss_se05x_key_object_allocate_handle(sss_se05x_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); + +/** @copydoc sss_key_object_get_handle + * + * On SE05X, this API uses @ref Se05x_API_ReadType and fetches + * parameters of the API. + * + */ +sss_status_t sss_se05x_key_object_get_handle(sss_se05x_object_t *keyObject, uint32_t keyId); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_set_user(sss_se05x_object_t *keyObject, uint32_t user, uint32_t options); + +/** @copydoc sss_key_object_set_purpose + * + */ +sss_status_t sss_se05x_key_object_set_purpose(sss_se05x_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_set_access(sss_se05x_object_t *keyObject, uint32_t access, uint32_t options); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_set_eccgfp_group(sss_se05x_object_t *keyObject, sss_eccgfp_group_t *group); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_get_user(sss_se05x_object_t *keyObject, uint32_t *user); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_get_purpose(sss_se05x_object_t *keyObject, sss_mode_t *purpose); + +/** Not Available for SE05X + * + */ +sss_status_t sss_se05x_key_object_get_access(sss_se05x_object_t *keyObject, uint32_t *access); + +/** @copydoc sss_key_object_free + * + * On SE050, this has no impact on physical Key Object. + */ +void sss_se05x_key_object_free(sss_se05x_object_t *keyObject); + +/*! @} */ /* end of : sss_se05x_keyobj */ + +/** + * @addtogroup sss_se05x_keyderive + * @{ + */ +/** @copydoc sss_derive_key_context_init + * + */ +sss_status_t sss_se05x_derive_key_context_init(sss_se05x_derive_key_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_derive_key_go + * + */ +sss_status_t sss_se05x_derive_key_go(sss_se05x_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @copydoc sss_derive_key_one_go + * + */ +sss_status_t sss_se05x_derive_key_one_go(sss_se05x_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_sobj_one_go +* +*/ +sss_status_t sss_se05x_derive_key_sobj_one_go(sss_se05x_derive_key_t *context, + sss_se05x_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_dh + * + */ +sss_status_t sss_se05x_derive_key_dh( + sss_se05x_derive_key_t *context, sss_se05x_object_t *otherPartyKeyObject, sss_se05x_object_t *derivedKeyObject); + +/** @copydoc sss_derive_key_context_free + * + */ +void sss_se05x_derive_key_context_free(sss_se05x_derive_key_t *context); + +/*! @} */ /* end of : sss_se05x_keyderive */ + +/** + * @addtogroup sss_se05x_keystore + * @{ + */ +/** @copydoc sss_key_store_context_init + * + */ +sss_status_t sss_se05x_key_store_context_init(sss_se05x_key_store_t *keyStore, sss_se05x_session_t *session); + +/** @copydoc sss_key_store_allocate + * + * This API does not do anything special on SE05X. + */ +sss_status_t sss_se05x_key_store_allocate(sss_se05x_key_store_t *keyStore, uint32_t keyStoreId); + +/** @copydoc sss_key_store_save + * + * This API does not do anything special on SE05X. + */ +sss_status_t sss_se05x_key_store_save(sss_se05x_key_store_t *keyStore); + +/** @copydoc sss_key_store_load + * + * This API does not do anything special on SE05X. + */ +sss_status_t sss_se05x_key_store_load(sss_se05x_key_store_t *keyStore); + +/** @copydoc sss_key_store_set_key + * + */ +sss_status_t sss_se05x_key_store_set_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @copydoc sss_key_store_generate_key + * + */ +sss_status_t sss_se05x_key_store_generate_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, size_t keyBitLen, void *options); + +/** @copydoc sss_key_store_get_key + * + */ +sss_status_t sss_se05x_key_store_get_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *data, size_t *dataLen, size_t *pKeyBitLen); + +/** @copydoc sss_key_store_open_key + * + * In SE05X, these keys can be used as KEK encryption key + * + * If ``keyObject`` == NULL, then subsequent key injection does not use any KEK. + * + * @return The sss status. + */ +sss_status_t sss_se05x_key_store_open_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject); + +/** Not available for SE05X + * + */ +sss_status_t sss_se05x_key_store_freeze_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject); + +/** @copydoc sss_key_store_erase_key + * + */ +sss_status_t sss_se05x_key_store_erase_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject); + +/** @copydoc sss_key_store_context_free + * + */ +void sss_se05x_key_store_context_free(sss_se05x_key_store_t *keyStore); + +/** Export Key from SE050 to host + * + * Only Transient keys can be exported. + */ +sss_status_t sss_se05x_key_store_export_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *key, size_t *keylen); + +/** Re Import previously exported SE05X key from host to the SE05X + * + * Only Transient keys can be imported. + */ +sss_status_t sss_se05x_key_store_import_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *key, size_t keylen); + +/*! @} */ /* end of : sss_se05x_keystore */ + +/** + * @addtogroup sss_se05x_asym + * @{ + */ +/** @copydoc sss_asymmetric_context_init + * + */ +sss_status_t sss_se05x_asymmetric_context_init(sss_se05x_asymmetric_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_asymmetric_encrypt + * + */ +sss_status_t sss_se05x_asymmetric_encrypt( + sss_se05x_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_decrypt + * + */ +sss_status_t sss_se05x_asymmetric_decrypt( + sss_se05x_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_sign_digest + * + */ +sss_status_t sss_se05x_asymmetric_sign_digest( + sss_se05x_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @copydoc sss_asymmetric_verify_digest + * + */ +sss_status_t sss_se05x_asymmetric_verify_digest( + sss_se05x_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @copydoc sss_asymmetric_context_free + * + */ +void sss_se05x_asymmetric_context_free(sss_se05x_asymmetric_t *context); + +/*! @} */ /* end of : sss_se05x_asym */ + +/** + * @addtogroup sss_se05x_symm + * @{ + */ +/** @copydoc sss_symmetric_context_init + * + */ +sss_status_t sss_se05x_symmetric_context_init(sss_se05x_symmetric_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_cipher_one_go + * + */ +sss_status_t sss_se05x_cipher_one_go(sss_se05x_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen); + +/** @copydoc sss_cipher_init + * + */ +sss_status_t sss_se05x_cipher_init(sss_se05x_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @copydoc sss_cipher_update + * + */ +sss_status_t sss_se05x_cipher_update( + sss_se05x_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_finish + * + */ +sss_status_t sss_se05x_cipher_finish( + sss_se05x_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_crypt_ctr + * + */ +sss_status_t sss_se05x_cipher_crypt_ctr(sss_se05x_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @copydoc sss_symmetric_context_free + * + */ +void sss_se05x_symmetric_context_free(sss_se05x_symmetric_t *context); + +/*! @} */ /* end of : sss_se05x_symm */ + +/** + * @addtogroup sss_se05x_aead + * @{ + */ +/** @copydoc sss_aead_context_init + * + */ +sss_status_t sss_se05x_aead_context_init(sss_se05x_aead_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_aead_one_go + * + */ +sss_status_t sss_se05x_aead_one_go(sss_se05x_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_init + * + */ +sss_status_t sss_se05x_aead_init( + sss_se05x_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); + +/** @copydoc sss_aead_update_aad + * + */ +sss_status_t sss_se05x_aead_update_aad(sss_se05x_aead_t *context, const uint8_t *aadData, size_t aadDataLen); + +/** @copydoc sss_aead_update + * + */ +sss_status_t sss_se05x_aead_update( + sss_se05x_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_aead_finish + * + */ +sss_status_t sss_se05x_aead_finish(sss_se05x_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_context_free + * + */ +void sss_se05x_aead_context_free(sss_se05x_aead_t *context); + +/*! @} */ /* end of : sss_se05x_aead */ + +/** + * @addtogroup sss_se05x_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_se05x_mac_context_init(sss_se05x_mac_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_se05x_mac_one_go( + sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_init + * + */ +sss_status_t sss_se05x_mac_init(sss_se05x_mac_t *context); + +/** @copydoc sss_mac_update + * + */ +sss_status_t sss_se05x_mac_update(sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_mac_finish + * + */ +sss_status_t sss_se05x_mac_finish(sss_se05x_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_se05x_mac_context_free(sss_se05x_mac_t *context); + +/*! @} */ /* end of : sss_se05x_mac */ + +/** + * @addtogroup sss_se05x_md + * @{ + */ +/** @copydoc sss_digest_context_init + * + */ +sss_status_t sss_se05x_digest_context_init( + sss_se05x_digest_t *context, sss_se05x_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_digest_one_go + * + */ +sss_status_t sss_se05x_digest_one_go( + sss_se05x_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_init + * + */ +sss_status_t sss_se05x_digest_init(sss_se05x_digest_t *context); + +/** @copydoc sss_digest_update + * + */ +sss_status_t sss_se05x_digest_update(sss_se05x_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_digest_finish + * + */ +sss_status_t sss_se05x_digest_finish(sss_se05x_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_context_free + * + */ +void sss_se05x_digest_context_free(sss_se05x_digest_t *context); + +/*! @} */ /* end of : sss_se05x_md */ + +/** + * @addtogroup sss_se05x_rng + * @{ + */ +/** @copydoc sss_rng_context_init + * + */ +sss_status_t sss_se05x_rng_context_init(sss_se05x_rng_context_t *context, sss_se05x_session_t *session); + +/** @copydoc sss_rng_get_random + * + */ +sss_status_t sss_se05x_rng_get_random(sss_se05x_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** @copydoc sss_rng_context_free + * + */ +sss_status_t sss_se05x_rng_context_free(sss_se05x_rng_context_t *context); + +/*! @} */ /* end of : sss_se05x_rng */ + +/** +* @addtogroup sss_se05x_tunnel +* @{ +*/ +/** @copydoc sss_tunnel_context_init + * + */ +sss_status_t sss_se05x_tunnel_context_init(sss_se05x_tunnel_context_t *context, sss_se05x_session_t *session); + +/** @copydoc sss_tunnel_context_free +* +*/ +void sss_se05x_tunnel_context_free(sss_se05x_tunnel_context_t *context); + +/*! @} */ /* end of : sss_se05x_tunnel */ + +sss_status_t sss_se05x_refresh_session(sss_se05x_session_t *session, void *connectionData); + +/** + * @addtogroup sss_se05x_tunnel + * @{ + */ + +/** @copydoc sss_tunnel_context_init + * + */ +sss_status_t sss_se05x_tunnel_context_init(sss_se05x_tunnel_context_t *context, sss_se05x_session_t *session); + +/** @copydoc sss_tunnel_t + * + */ +sss_status_t sss_se05x_tunnel(sss_se05x_tunnel_context_t *context, + uint8_t *data, + size_t dataLen, + sss_se05x_object_t *keyObjects, + uint32_t keyObjectCount, + uint32_t tunnelType); + +/** @copydoc sss_tunnel_context_free + * + */ +void sss_se05x_tunnel_context_free(sss_se05x_tunnel_context_t *context); + +/*! @} */ /* end of : sss_se05x_tunnel */ + +/** Set features of the Applet. + * + * See @ref Se05x_API_SetAppletFeatures + */ +sss_status_t sss_se05x_set_feature( + sss_se05x_session_t *session, SE05x_Applet_Feature_t feature, SE05x_Applet_Feature_Disable_t disable_features); + +SE05x_DigestMode_t se05x_get_sha_algo(sss_algorithm_t algorithm); + +#if SSSFTR_SE05X_ECC +sss_status_t sss_se05x_key_store_create_curve(Se05xSession_t *pSession, uint32_t curve_id); +#endif + +/* clang-format off */ +# if (SSS_HAVE_SSS == 1) + /* Direct Call : session */ +# define sss_session_create(session,subsystem,application_id,connection_type,connectionData) \ + sss_se05x_session_create(((sss_se05x_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_open(session,subsystem,application_id,connection_type,connectionData) \ + sss_se05x_session_open(((sss_se05x_session_t * ) session),(subsystem),(application_id),(connection_type),(connectionData)) +# define sss_session_prop_get_u32(session,property,pValue) \ + sss_se05x_session_prop_get_u32(((sss_se05x_session_t * ) session),(property),(pValue)) +# define sss_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_se05x_session_prop_get_au8(((sss_se05x_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_session_close(session) \ + sss_se05x_session_close(((sss_se05x_session_t * ) session)) +# define sss_session_delete(session) \ + sss_se05x_session_delete(((sss_se05x_session_t * ) session)) + /* Direct Call : keyobj */ +# define sss_key_object_init(keyObject,keyStore) \ + sss_se05x_key_object_init(((sss_se05x_object_t * ) keyObject),((sss_se05x_key_store_t * ) keyStore)) +# define sss_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_se05x_key_object_allocate_handle(((sss_se05x_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_key_object_get_handle(keyObject,keyId) \ + sss_se05x_key_object_get_handle(((sss_se05x_object_t * ) keyObject),(keyId)) +# define sss_key_object_set_user(keyObject,user,options) \ + sss_se05x_key_object_set_user(((sss_se05x_object_t * ) keyObject),(user),(options)) +# define sss_key_object_set_purpose(keyObject,purpose,options) \ + sss_se05x_key_object_set_purpose(((sss_se05x_object_t * ) keyObject),(purpose),(options)) +# define sss_key_object_set_access(keyObject,access,options) \ + sss_se05x_key_object_set_access(((sss_se05x_object_t * ) keyObject),(access),(options)) +# define sss_key_object_set_eccgfp_group(keyObject,group) \ + sss_se05x_key_object_set_eccgfp_group(((sss_se05x_object_t * ) keyObject),(group)) +# define sss_key_object_get_user(keyObject,user) \ + sss_se05x_key_object_get_user(((sss_se05x_object_t * ) keyObject),(user)) +# define sss_key_object_get_purpose(keyObject,purpose) \ + sss_se05x_key_object_get_purpose(((sss_se05x_object_t * ) keyObject),(purpose)) +# define sss_key_object_get_access(keyObject,access) \ + sss_se05x_key_object_get_access(((sss_se05x_object_t * ) keyObject),(access)) +# define sss_key_object_free(keyObject) \ + sss_se05x_key_object_free(((sss_se05x_object_t * ) keyObject)) + /* Direct Call : keyderive */ +# define sss_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_se05x_derive_key_context_init(((sss_se05x_derive_key_t * ) context),((sss_se05x_session_t * ) session),((sss_se05x_object_t * ) keyObject),(algorithm),(mode)) +# define sss_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_se05x_derive_key_go(((sss_se05x_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_se05x_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_se05x_derive_key_dh(((sss_se05x_derive_key_t * ) context),((sss_se05x_object_t * ) otherPartyKeyObject),((sss_se05x_object_t * ) derivedKeyObject)) +# define sss_derive_key_context_free(context) \ + sss_se05x_derive_key_context_free(((sss_se05x_derive_key_t * ) context)) + /* Direct Call : keystore */ +# define sss_key_store_context_init(keyStore,session) \ + sss_se05x_key_store_context_init(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_session_t * ) session)) +# define sss_key_store_allocate(keyStore,keyStoreId) \ + sss_se05x_key_store_allocate(((sss_se05x_key_store_t * ) keyStore),(keyStoreId)) +# define sss_key_store_save(keyStore) \ + sss_se05x_key_store_save(((sss_se05x_key_store_t * ) keyStore)) +# define sss_key_store_load(keyStore) \ + sss_se05x_key_store_load(((sss_se05x_key_store_t * ) keyStore)) +# define sss_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_se05x_key_store_set_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_se05x_key_store_generate_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_se05x_key_store_get_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_key_store_open_key(keyStore,keyObject) \ + sss_se05x_key_store_open_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject)) +# define sss_key_store_freeze_key(keyStore,keyObject) \ + sss_se05x_key_store_freeze_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject)) +# define sss_key_store_erase_key(keyStore,keyObject) \ + sss_se05x_key_store_erase_key(((sss_se05x_key_store_t * ) keyStore),((sss_se05x_object_t * ) keyObject)) +# define sss_key_store_context_free(keyStore) \ + sss_se05x_key_store_context_free(((sss_se05x_key_store_t * ) keyStore)) + /* Direct Call : asym */ +# define sss_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_se05x_asymmetric_context_init(((sss_se05x_asymmetric_t * ) context),((sss_se05x_session_t * ) session),((sss_se05x_object_t * ) keyObject),(algorithm),(mode)) +# define sss_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_se05x_asymmetric_encrypt(((sss_se05x_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_se05x_asymmetric_decrypt(((sss_se05x_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_se05x_asymmetric_sign_digest(((sss_se05x_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_se05x_asymmetric_verify_digest(((sss_se05x_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_asymmetric_context_free(context) \ + sss_se05x_asymmetric_context_free(((sss_se05x_asymmetric_t * ) context)) + /* Direct Call : symm */ +# define sss_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_se05x_symmetric_context_init(((sss_se05x_symmetric_t * ) context),((sss_se05x_session_t * ) session),((sss_se05x_object_t * ) keyObject),(algorithm),(mode)) +# define sss_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_se05x_cipher_one_go(((sss_se05x_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_cipher_init(context,iv,ivLen) \ + sss_se05x_cipher_init(((sss_se05x_symmetric_t * ) context),(iv),(ivLen)) +# define sss_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_se05x_cipher_update(((sss_se05x_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_se05x_cipher_finish(((sss_se05x_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_se05x_cipher_crypt_ctr(((sss_se05x_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_symmetric_context_free(context) \ + sss_se05x_symmetric_context_free(((sss_se05x_symmetric_t * ) context)) + /* Direct Call : aead */ +# define sss_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_se05x_aead_context_init(((sss_se05x_aead_t * ) context),((sss_se05x_session_t * ) session),((sss_se05x_object_t * ) keyObject),(algorithm),(mode)) +# define sss_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_se05x_aead_one_go(((sss_se05x_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_se05x_aead_init(((sss_se05x_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_aead_update_aad(context,aadData,aadDataLen) \ + sss_se05x_aead_update_aad(((sss_se05x_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_se05x_aead_update(((sss_se05x_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_se05x_aead_finish(((sss_se05x_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_aead_context_free(context) \ + sss_se05x_aead_context_free(((sss_se05x_aead_t * ) context)) + /* Direct Call : mac */ +# define sss_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_se05x_mac_context_init(((sss_se05x_mac_t * ) context),((sss_se05x_session_t * ) session),((sss_se05x_object_t * ) keyObject),(algorithm),(mode)) +# define sss_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_se05x_mac_one_go(((sss_se05x_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_mac_init(context) \ + sss_se05x_mac_init(((sss_se05x_mac_t * ) context)) +# define sss_mac_update(context,message,messageLen) \ + sss_se05x_mac_update(((sss_se05x_mac_t * ) context),(message),(messageLen)) +# define sss_mac_finish(context,mac,macLen) \ + sss_se05x_mac_finish(((sss_se05x_mac_t * ) context),(mac),(macLen)) +# define sss_mac_context_free(context) \ + sss_se05x_mac_context_free(((sss_se05x_mac_t * ) context)) + /* Direct Call : md */ +# define sss_digest_context_init(context,session,algorithm,mode) \ + sss_se05x_digest_context_init(((sss_se05x_digest_t * ) context),((sss_se05x_session_t * ) session),(algorithm),(mode)) +# define sss_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_se05x_digest_one_go(((sss_se05x_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_digest_init(context) \ + sss_se05x_digest_init(((sss_se05x_digest_t * ) context)) +# define sss_digest_update(context,message,messageLen) \ + sss_se05x_digest_update(((sss_se05x_digest_t * ) context),(message),(messageLen)) +# define sss_digest_finish(context,digest,digestLen) \ + sss_se05x_digest_finish(((sss_se05x_digest_t * ) context),(digest),(digestLen)) +# define sss_digest_context_free(context) \ + sss_se05x_digest_context_free(((sss_se05x_digest_t * ) context)) + /* Direct Call : rng */ +# define sss_rng_context_init(context,session) \ + sss_se05x_rng_context_init(((sss_se05x_rng_context_t * ) context),((sss_se05x_session_t * ) session)) +# define sss_rng_get_random(context,random_data,dataLen) \ + sss_se05x_rng_get_random(((sss_se05x_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_rng_context_free(context) \ + sss_se05x_rng_context_free(((sss_se05x_rng_context_t * ) context)) + /* Direct Call : tunnel */ +# define sss_tunnel_context_init(context,session) \ + sss_se05x_tunnel_context_init(((sss_se05x_tunnel_context_t * ) context),((sss_se05x_session_t * ) session)) +# define sss_tunnel(context,data,dataLen,keyObjects,keyObjectCount,tunnelType) \ + sss_se05x_tunnel(((sss_se05x_tunnel_context_t * ) context),(data),(dataLen),((sss_se05x_object_t * ) keyObjects),(keyObjectCount),(tunnelType)) +# define sss_tunnel_context_free(context) \ + sss_se05x_tunnel_context_free(((sss_se05x_tunnel_context_t * ) context)) +# endif /* (SSS_HAVE_SSS == 1) */ +/* clang-format on */ +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#ifdef __cplusplus +} // extern "C" +#endif /* __cplusplus */ + +#endif /* FSL_SSS_SE05X_APIS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h new file mode 100644 index 00000000000..bab222bf0e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h @@ -0,0 +1,51 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FSL_SSS_SE05X_POLICY_H +#define FSL_SSS_SE05X_POLICY_H + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT +#include +#include +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** @brief + * The function serializes input passed by user (array of sss_policy_t) in to + * uin8[] policy buffer + * + * @param[in] Array of policies passed by user. + * @param[out] buffer passed by user where serialized policy data is copied. + * @param[out] buf_len passed by user where serialized policy data length is copied. + * + * @warning Please ensure pbuff is atleast of size MAX_POLICY_BUFFER_SIZE + * + */ +sss_status_t sss_se05x_create_object_policy_buffer(sss_policy_t *policies, uint8_t *pbuff, size_t *buf_len); +/*! @brief + * The function serializes input passed by user (sss_policy_session_u) in to + * uin8[] policy buffer + * + * @param[in] pointer to sss_policy_session_u passed by user. + * @param[out] buffer passed by user where serialized policy data is copied. + * @param[out] buf_len passed by user where serialized policy data length is copied. + * + * @warning Please ensure session_pol_buff is atleast of size MAX_POLICY_BUFFER_SIZE + * + */ +sss_status_t sss_se05x_create_session_policy_buffer( + sss_policy_session_u *session_policy, uint8_t *session_pol_buff, size_t *buf_len); +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#endif /* FSL_SSS_SE05X_POLICY_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h new file mode 100644 index 00000000000..d15a4bdd924 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h @@ -0,0 +1,56 @@ +/* +* +* Copyright 2018-2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef FSL_SSS_SE05X_SCP03_H +#define FSL_SSS_SE05X_SCP03_H + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nxScp03_Const.h" +#include "nxScp03_Types.h" +#include "se05x_tlv.h" +#if SSS_HAVE_MBEDTLS +#include +#endif +#if SSS_HAVE_OPENSSL +#include +#endif + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** +* To send and receive encrypted communication using SCP03 +*/ +sss_status_t nxScp03_AuthenticateChannel(pSe05xSession_t se05xSession, NXSCP03_AuthCtx_t *authScp03); + +/** +* To send and receive encrypted communication using Fast SCP +*/ +sss_status_t nxECKey_AuthenticateChannel(pSe05xSession_t se05xSession, SE05x_AuthCtx_ECKey_t *pAuthFScp); + +#ifdef __cplusplus +} /* extern "c"*/ +#endif + +#endif /* FSL_SSS_SE05X_SCP03_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h new file mode 100644 index 00000000000..26a8e0d3fef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h @@ -0,0 +1,613 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_SE05X_TYPES_H_ +#define SSS_APIS_INC_FSL_SSS_SE05X_TYPES_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT +#include "nxScp03_Types.h" +#include "se05x_const.h" +#include "se05x_tlv.h" +#include "sm_api.h" +#if (__GNUC__ && !AX_EMBEDDED) +#include +/* Only for base session with os */ +#endif +/* FreeRTOS includes. */ +#if USE_RTOS +#include "FreeRTOS.h" +#include "FreeRTOSIPConfig.h" +#include "semphr.h" +#include "task.h" +#endif + +/*! + * @addtogroup sss_sw_se05x + * @{ + */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_SUBSYSTEM_TYPE_IS_SE05X(subsystem) (subsystem == kType_SSS_SE_SE05x) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_SESSION_TYPE_IS_SE05X(session) (session && SSS_SUBSYSTEM_TYPE_IS_SE05X(session->subsystem)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_KEY_STORE_TYPE_IS_SE05X(keyStore) (keyStore && SSS_SESSION_TYPE_IS_SE05X(keyStore->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_OBJECT_TYPE_IS_SE05X(pObject) (pObject && SSS_KEY_STORE_TYPE_IS_SE05X(pObject->keyStore)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_ASYMMETRIC_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_DERIVE_KEY_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_SYMMETRIC_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_MAC_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_RNG_CONTEXT_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_DIGEST_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_AEAD_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_TUNNEL_CONTEXT_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/** Are we using SE05X as crypto subsystem? */ +#define SSS_TUNNEL_TYPE_IS_SE05X(context) (context && SSS_SESSION_TYPE_IS_SE05X(context->session)) + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +struct _sss_se05x_session; + +/** @copydoc sss_tunnel_t */ +typedef struct _sss_se05x_tunnel_context +{ + /** Pointer to the base SE050 SEssion */ + struct _sss_se05x_session *se05x_session; + /** Where exactly this tunnel terminates to */ + sss_tunnel_dest_t tunnelDest; +/** For systems where we potentially have multi-threaded operations, have a lock */ +#if USE_RTOS + SemaphoreHandle_t channelLock; +#elif (__GNUC__ && !AX_EMBEDDED) + pthread_mutex_t channelLock; +#endif +} sss_se05x_tunnel_context_t; + +/** @copydoc sss_session_t */ +typedef struct _sss_se05x_session +{ + /** Indicates which security subsystem is selected to be used. */ + sss_type_t subsystem; + + /** Connection context to SE050 */ + + Se05xSession_t s_ctx; + + /** In case connection is tunneled, context to the tunnel */ + + sss_se05x_tunnel_context_t *ptun_ctx; +} sss_se05x_session_t; + +struct _sss_se05x_object; + +/** @copydoc sss_key_store_t */ +typedef struct +{ + /** Pointer to the session */ + sss_se05x_session_t *session; + /** In case the we are using Key Wrapping while injecting the keys, pointer to key used for wrapping */ + struct _sss_se05x_object *kekKey; + +} sss_se05x_key_store_t; + +/** @copydoc sss_object_t */ +typedef struct _sss_se05x_object +{ + /** key store holding the data and other properties */ + sss_se05x_key_store_t *keyStore; + /** @copydoc sss_object_t::objectType */ + uint32_t objectType; + /** @copydoc sss_object_t::cipherType */ + uint32_t cipherType; + /** Application specific key identifier. The keyId is kept in the key store + * along with the key data and other properties. */ + uint32_t keyId; + + /** If this is an ECC Key, the Curve ID of the key */ + SE05x_ECCurve_t curve_id; + + /** Whether this is a persistant or tansient object */ + uint8_t isPersistant : 1; + +} sss_se05x_object_t; + +/** @copydoc sss_derive_key_t */ +typedef struct +{ + /** @copydoc sss_derive_key_t::session */ + sss_se05x_session_t *session; + /** @copydoc sss_derive_key_t::keyObject */ + sss_se05x_object_t *keyObject; + /** @copydoc sss_derive_key_t::algorithm */ + sss_algorithm_t algorithm; + /** @copydoc sss_derive_key_t::mode */ + sss_mode_t mode; + +} sss_se05x_derive_key_t; + +/** @copydoc sss_asymmetric_t */ +typedef struct +{ + /** @copydoc sss_asymmetric_t::session */ + sss_se05x_session_t *session; + /** @copydoc sss_asymmetric_t::keyObject */ + sss_se05x_object_t *keyObject; + /** @copydoc sss_asymmetric_t::algorithm */ + sss_algorithm_t algorithm; + /** @copydoc sss_asymmetric_t::mode */ + sss_mode_t mode; + +} sss_se05x_asymmetric_t; + +/** @copydoc sss_symmetric_t */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_se05x_session_t *session; + /** Reference to key and it's properties. */ + sss_se05x_object_t *keyObject; + /** @copydoc sss_symmetric_t::algorithm */ + sss_algorithm_t algorithm; + /** @copydoc sss_symmetric_t::mode */ + sss_mode_t mode; + + /* Implementation specific part */ + + /** Used crypto object ID for this operation */ + SE05x_CryptoObjectID_t cryptoObjectId; + /** Since underlying system conly only process in fixed chunks, chache them on host + * to complete the operation sanely */ + uint8_t cache_data[16]; + /** Length of bytes cached on host */ + size_t cache_data_len; +} sss_se05x_symmetric_t; + +/** @copydoc sss_mac_t */ +typedef struct +{ + /** copydoc sss_mac_t::session */ + sss_se05x_session_t *session; + /** copydoc sss_mac_t::keyObject */ + sss_se05x_object_t *keyObject; + + /** copydoc sss_mac_t::algorithm */ + sss_algorithm_t algorithm; + /** copydoc sss_mac_t::mode */ + sss_mode_t mode; + /* Implementation specific part */ + + /** Used crypto object ID for this operation */ + SE05x_CryptoObjectID_t cryptoObjectId; +} sss_se05x_mac_t; + +/** @copydoc sss_aead_t */ +typedef struct +{ + /** @copydoc sss_aead_t::session */ + sss_se05x_session_t *session; + /** @copydoc sss_aead_t::keyObject */ + sss_se05x_object_t *keyObject; + /** @copydoc sss_aead_t::algorithm */ + sss_algorithm_t algorithm; + /** @copydoc sss_aead_t::mode */ + sss_mode_t mode; + + /** Implementation specific part */ + SE05x_CryptoObjectID_t cryptoObjectId; + /** Cache in case of un-alined inputs */ + uint8_t cache_data[16]; + /** How much we have cached */ + size_t cache_data_len; +} sss_se05x_aead_t; + +/** @copydoc sss_digest_t */ +typedef struct +{ + /** Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_se05x_session_t *session; + /** @copydoc sss_digest_t::algorithm */ + sss_algorithm_t algorithm; + /** @copydoc sss_digest_t::mode */ + sss_mode_t mode; + /** @copydoc sss_digest_t::digestFullLen */ + size_t digestFullLen; + /** Implementation specific part */ + + SE05x_CryptoObjectID_t cryptoObjectId; +} sss_se05x_digest_t; + +/** @copydoc sss_rng_context_t */ +typedef struct +{ + /** @copydoc sss_rng_context_t::session */ + sss_se05x_session_t *session; +} sss_se05x_rng_context_t; + +/** SE050 Properties that can be represented as an array */ +typedef enum +{ + kSSS_SE05x_SessionProp_CertUID = kSSS_SessionProp_au8_Proprietary_Start + 1, +} sss_s05x_sesion_prop_au8_t; + +/** SE050 Properties that can be represented as 32bit numbers */ +typedef enum +{ + kSSS_SE05x_SessionProp_CertUIDLen = kSSS_SessionProp_u32_Optional_Start + 1, +} sss_s05x_sesion_prop_u32_t; + +/** deprecated : Used only for backwards compatibility */ +#define SE05x_Connect_Ctx_t SE_Connect_Ctx_t +/** deprecated : Used only for backwards compatibility */ +#define se05x_auth_context_t SE_Connect_Ctx_t + +/** Used to enable Applet Features via ``sss_se05x_set_feature`` */ +typedef struct +{ + /** Use of curve TPM_ECC_BN_P256 */ + uint8_t AppletConfig_ECDAA : 1; + /** EC DSA and DH support */ + uint8_t AppletConfig_ECDSA_ECDH_ECDHE : 1; + /** Use of curve RESERVED_ID_ECC_ED_25519 */ + uint8_t AppletConfig_EDDSA : 1; + /** Use of curve RESERVED_ID_ECC_MONT_DH_25519 */ + uint8_t AppletConfig_DH_MONT : 1; + /** Writing HMACKey objects */ + uint8_t AppletConfig_HMAC : 1; + /** Writing RSAKey objects */ + uint8_t AppletConfig_RSA_PLAIN : 1; + /** Writing RSAKey objects */ + uint8_t AppletConfig_RSA_CRT : 1; + /** Writing AESKey objects */ + uint8_t AppletConfig_AES : 1; + /** Writing DESKey objects */ + uint8_t AppletConfig_DES : 1; + /** PBKDF2 */ + uint8_t AppletConfig_PBKDF : 1; + /** TLS Handshake support commands (see 4.16) in APDU Spec*/ + uint8_t AppletConfig_TLS : 1; + /** Mifare DESFire support (see 4.15) in APDU Spec*/ + uint8_t AppletConfig_MIFARE : 1; + /** Allocated value undefined and reserved for future use */ + uint8_t AppletConfig_RFU1 : 1; + /** I2C Master support (see 4.17) in APDU Spec*/ + uint8_t AppletConfig_I2CM : 1; + /** RFU */ + uint8_t AppletConfig_RFU21 : 1; +} SE05x_Applet_Feature_t; + +/** Used to disable Applet Features via ``sss_se05x_set_feature`` */ +typedef struct +{ + /** Disable feature ECDH B2b8 */ + uint8_t EXTCFG_FORBID_ECDH : 1; + /** Disable feature ECDAA B2b7 */ + uint8_t EXTCFG_FORBID_ECDAA : 1; + /** Disable feature RSA_LT_2K B6b8 */ + uint8_t EXTCFG_FORBID_RSA_LT_2K : 1; + /** Disable feature RSA_SHA1 B6b7 */ + uint8_t EXTCFG_FORBID_RSA_SHA1 : 1; + /** Disable feature AES_GCM B8b8 */ + uint8_t EXTCFG_FORBID_AES_GCM : 1; + /** Disable feature AES_GCM_EXT_IV B8b7 */ + uint8_t EXTCFG_FORBID_AES_GCM_EXT_IV : 1; + /** Disable feature HKDF_EXTRACT B10b7 */ + uint8_t EXTCFG_FORBID_HKDF_EXTRACT : 1; +} SE05x_Applet_Feature_Disable_t; + +/** Attestation data */ +typedef struct +{ + /** Random used during attestation */ + uint8_t outrandom[16]; + /** length of outrandom */ + size_t outrandomLen; + /** time stamp */ + SE05x_TimeStamp_t timeStamp; + /** Length of timeStamp */ + size_t timeStampLen; + /** Uinquie ID of SE050 */ + uint8_t chipId[SE050_MODULE_UNIQUE_ID_LEN]; + /** Lenght of the Unique ID */ + size_t chipIdLen; + /** Attributes */ + uint8_t attribute[MAX_POLICY_BUFFER_SIZE + 15]; + /** Length of Attribute */ + size_t attributeLen; + /** Signature for attestation */ + uint8_t signature[512]; + /** Lenght of signature */ + size_t signatureLen; +} sss_se05x_attst_comp_data_t; + +/** Data to be read with attestation */ +typedef struct +{ + /** Whle reading RSA Objects, modulus and public exporent get attested separately, */ + sss_se05x_attst_comp_data_t data[SE05X_MAX_ATTST_DATA]; + /** How many entries to attest */ + uint8_t valid_number; +} sss_se05x_attst_data_t; + +/** @} */ + +/** @addtogroup se050_i2cm + * + * @{ */ + +/** Types of entries in an I2CM Transaction */ +typedef enum +{ + /** Do nothing */ + kSE05x_I2CM_None = 0, + /** Configure the address, baudrate */ + kSE05x_I2CM_Configure, + /** Write to I2C Slave */ + kSE05x_I2CM_Write = 3, + /** Read from I2C Slave */ + kSE05x_I2CM_Read, + + /** Response from SE05x that there is something wrong */ + kSE05x_I2CM_StructuralIssue = 0xFF +} SE05x_I2CM_TLV_type_t; + +/** Status of I2CM Transaction */ +typedef enum +{ + kSE05x_I2CM_Success = 0x5A, + kSE05x_I2CM_I2C_Nack_Fail = 0x01, + kSE05x_I2CM_I2C_Write_Error = 0x02, + kSE05x_I2CM_I2C_Read_Error = 0x03, + kSE05x_I2CM_I2C_Time_Out_Error = 0x05, + kSE05x_I2CM_Invalid_Tag = 0x11, + kSE05x_I2CM_Invalid_Length = 0x12, + kSE05x_I2CM_Invalid_Length_Encode = 0x13, + kSE05x_I2CM_I2C_Config = 0x21 +} SE05x_I2CM_status_t; + +/** Additional operation on data read by I2C */ +typedef enum +{ + kSE05x_Security_None = 0, + kSE05x_Sign_Request, + kSE05x_Sign_Enc_Request, +} SE05x_I2CM_securityReq_t; + +/** Configuration for I2CM */ +typedef enum +{ + kSE05x_I2CM_Baud_Rate_100Khz = 0, + kSE05x_I2CM_Baud_Rate_400Khz, +} SE05x_I2CM_Baud_Rate_t; + +/** Data Configuration for I2CM */ +typedef struct +{ + /** 7 Bit address of I2C slave */ + uint8_t I2C_addr; + /** What baud rate */ + SE05x_I2CM_Baud_Rate_t I2C_baudRate; + /** return status of the config operation */ + SE05x_I2CM_status_t status; +} SE05x_I2CM_configData_t; + +/** @brief Security Configuration for I2CM */ +typedef struct +{ + /** @copydoc SE05x_I2CM_securityReq_t */ + SE05x_I2CM_securityReq_t operation; + /** object used for the operation */ + uint32_t keyObject; +} SE05x_I2CM_securityData_t; + +/** @brief Write From I2CM to I2C Slave */ +typedef struct +{ + /** How many bytes to write */ + uint8_t writeLength; + /** [Out] status of the operation */ + SE05x_I2CM_status_t wrStatus; + /** Buffer to be written */ + uint8_t *writebuf; /* Input */ +} SE05x_I2CM_writeData_t; + +/** Read to I2CM from I2C Slave */ +typedef struct +{ + /** How many bytes to read */ + uint16_t readLength; + /** [Out] status of the operation */ + SE05x_I2CM_status_t rdStatus; + /** Output. rdBuf will point to Host buffer. */ + uint8_t *rdBuf; +} SE05x_I2CM_readData_t; + +/** Used to report error response, not for outgoing command */ +typedef struct +{ + /** [Out] In case there is any structural issue */ + SE05x_I2CM_status_t issueStatus; +} SE05x_I2CM_structuralIssue_t; + +/** @brief Individual entry in array of TLV commands */ +typedef union { + /** @copydoc SE05x_I2CM_configData_t */ + SE05x_I2CM_configData_t cfg; + /** @copydoc SE05x_I2CM_securityData_t */ + SE05x_I2CM_securityData_t sec; + /** @copydoc SE05x_I2CM_writeData_t */ + SE05x_I2CM_writeData_t w; + /** @copydoc SE05x_I2CM_readData_t */ + SE05x_I2CM_readData_t rd; + /** @copydoc SE05x_I2CM_structuralIssue_t */ + SE05x_I2CM_structuralIssue_t issue; +} SE05x_I2CM_INS_type_t; + +/** Individual entry in array of TLV commands, with type + * + * @ref Se05x_i2c_master_txn would expect an array of these. + */ +typedef struct _SE05x_I2CM_cmd +{ + /** @copybrief SE05x_I2CM_TLV_type_t */ + SE05x_I2CM_TLV_type_t type; + /** @copybrief SE05x_I2CM_INS_type_t */ + SE05x_I2CM_INS_type_t cmd; +} SE05x_I2CM_cmd_t; + +/*! + *@} + */ /* end of se050_i2cm */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** MAC Validate + * + */ +sss_status_t sss_se05x_mac_validate_one_go( + sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t macLen); + +/** Similar to @ref sss_se05x_asymmetric_sign_digest, + * + * but hashing/digest done by SE + */ +sss_status_t sss_se05x_asymmetric_sign( + sss_se05x_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t *signatureLen); + +/** Similar to @ref sss_se05x_asymmetric_verify_digest, + * but hashing/digest done by SE + * + */ +sss_status_t sss_se05x_asymmetric_verify( + sss_se05x_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t signatureLen); + +/** Read with attestation + * + */ +sss_status_t sss_se05x_key_store_get_key_attst(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + uint8_t *key, + size_t *keylen, + size_t *pKeyBitLen, + sss_se05x_object_t *keyObject_attst, + sss_algorithm_t algorithm_attst, + uint8_t *random_attst, + size_t randomLen_attst, + sss_se05x_attst_data_t *attst_data); + +uint32_t se05x_sssKeyTypeLenToCurveId(sss_cipher_type_t keyType, size_t keyBits); + +/** @addtogroup se050_i2cm + * + * @{ +*/ + +/** @brief Se05x_i2c_master_txn +* +* I2CM Transaction +* +* @param[in] sess session identifier +* @param[in,out] cmds Array of structure type capturing a sequence of i2c master cmd/rsp transactions. +* @param[in] cmdLen Amount of structures contained in cmds +* +* @pre p describes I2C master commands. +* @post p contains execution state of I2C master commands, the I2C master commands can be overwritten to report on execution failure. +*/ +smStatus_t Se05x_i2c_master_txn(sss_session_t *sess, SE05x_I2CM_cmd_t *cmds, uint8_t cmdLen); + +/** @brief Se05x_i2c_master_attst_txn + * + * I2CM Read With Attestation + * + * @param[in] sess session identifier + * @param[in] keyObject Keyobject which contains 4 byte attestaion KeyId + * @param[in,out] p Array of structure type capturing a sequence of i2c master cmd/rsp transactions. + * @param[in] random_attst 16-byte freshness random + * @param[in] random_attstLen length of freshness random + * @param[in] attst_algo 1 byte attestationAlgo + * @param[out] ptimeStamp timestamp + * @param[out] timeStampLen Length for timestamp + * @param[out] freshness freshness (random) + * @param[out] pfreshnessLen Length for freshness + * @param[out] chipId unique chip Id + * @param[out] pchipIdLen Length for chipId + * @param[out] signature signature + * @param[out] psignatureLen Length for signature + * @param[in] noOftags Amount of structures contained in ``p`` + * + * @pre p describes I2C master commands. + * @post p contains execution state of I2C master commands, the I2C master commands can be overwritten to report on execution failure. + */ +smStatus_t Se05x_i2c_master_attst_txn(sss_session_t *sess, + sss_object_t *keyObject, + SE05x_I2CM_cmd_t *p, + uint8_t *random_attst, + size_t random_attstLen, + SE05x_AttestationAlgo_t attst_algo, + SE05x_TimeStamp_t *ptimeStamp, + size_t *timeStampLen, + uint8_t *freshness, + size_t *pfreshnessLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen, + uint8_t noOftags); + +/*! + *@} + */ /* end of se050_i2cm */ + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ + +#endif /* SSS_APIS_INC_FSL_SSS_SE05X_TYPES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h new file mode 100644 index 00000000000..b80f0c3e6d6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h @@ -0,0 +1,717 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _FSL_SSS_SSCP_H_ +#define _FSL_SSS_SSCP_H_ + +#include "fsl_sscp.h" +#include "fsl_sss_api.h" + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if !defined(SSS_SSCP_CONFIG_FILE) +#include "fsl_sss_sscp_config.h" +#else +#include SSS_SSCP_CONFIG_FILE +#endif + +#define SSS_SUBSYSTEM_TYPE_IS_SSCP(subsystem) ((subsystem == kType_SSS_SE_A71CH) || (subsystem == kType_SSS_SE_A71CL)) + +#define SSS_SESSION_TYPE_IS_SSCP(session) (session && SSS_SUBSYSTEM_TYPE_IS_SSCP(session->subsystem)) + +#define SSS_KEY_STORE_TYPE_IS_SSCP(keyStore) (keyStore && SSS_SESSION_TYPE_IS_SSCP(keyStore->session)) + +#define SSS_OBJECT_TYPE_IS_SSCP(pObject) (pObject && SSS_KEY_STORE_TYPE_IS_SSCP(pObject->keyStore)) + +#define SSS_DERIVE_KEY_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_ASYMMETRIC_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_SYMMETRIC_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_MAC_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_RNG_CONTEXT_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_DIGEST_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +#define SSS_AEAD_TYPE_IS_SSCP(context) (context && SSS_SESSION_TYPE_IS_SSCP(context->session)) + +typedef enum +{ + kSSS_SSCP_SessionProp_CertUID = kSSS_SessionProp_au8_Proprietary_Start + 1, +} sss_sscp_sesion_prop_au8_t; + +typedef enum +{ + kSSS_SSCP_SessionProp_CertUIDLen = kSSS_SessionProp_u32_Optional_Start + 1, +} sss_sscp_sesion_prop_u32_t; + +typedef void (*fn_sscp_close_t)(void); + +typedef struct _sss_sscp_session +{ + /*! Indicates which security subsystem is selected to be used. */ + sss_type_t subsystem; + + /*! Implementation specific part + * This will be NULL unitl and unless we are not ready to use the sscp_context. + */ + sscp_context_t *sscp_context; + /** + * Allocated structure, not to be used directly... + * Use only sscp_context */ + sscp_context_t mem_sscp_ctx; + /** session identifier */ + uint32_t sessionId; + /** Function pointer that can be used to close the last active session. */ + fn_sscp_close_t fp_closeConnection; +} sss_sscp_session_t; + +typedef struct _sss_sscp_key_store +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_sscp_session_t *session; + /*! Implementation specific part */ + uint32_t keyStoreId; +} sss_sscp_key_store_t; + +typedef struct _sss_sscp_object +{ + /*! key store holding the data and other properties */ + sss_sscp_key_store_t *keyStore; + + uint32_t objectType; /*!< Object types */ + uint32_t cipherType; /*!< Cipher types */ + /*! Application specific key identifier. The keyId is kept in the key store along with the key data and other + * properties. */ + uint32_t keyId; + + void *transientObject; + size_t transientObjectLen; + size_t transientObjectBitLen; + uint8_t slotId; +} sss_sscp_object_t; + +/*! @brief ::sss_symmetric_t with SSCP specific information */ +typedef struct _sss_sscp_symmetric +{ + /*! Virtual connection between application (user context) and + specific security subsystem and function thereof. */ + sss_sscp_session_t *session; + sss_sscp_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*!< What eventual operation algorithm be performed */ + sss_mode_t mode; /*!< High level operation, encrypt/decrypt/etc. */ + uint32_t sessionId; /*!< Session identifier in case of parallel contexts */ + /*! Implementation specific part */ + struct + { + uint8_t data[SSS_SSCP_SYMMETRIC_CONTEXT_SIZE]; + } context; +} sss_sscp_symmetric_t; + +typedef struct _sss_sscp_aead +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_sscp_session_t *session; + sss_sscp_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + + /*! Implementation specific part */ +} sss_sscp_aead_t; + +typedef struct _sss_sscp_digest +{ + /*! Virtual connection between application (user context) and specific security subsystem and function thereof. */ + sss_sscp_session_t *session; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + /*! Full digest length per algorithm definition. This field is initialized along with algorithm. */ + size_t digestFullLen; + + /*! Implementation specific part */ + struct + { + uint8_t data[SSS_SSCP_DIGEST_CONTEXT_SIZE]; + } context; +} sss_sscp_digest_t; + +typedef struct _sss_sscp_mac +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_sscp_session_t *session; + sss_sscp_object_t *keyObject; /*!< Reference to key and it's properties. */ + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + + /*! Implementation specific part */ + uint32_t macFullLen; + struct + { + uint8_t data[SSS_SSCP_MAC_CONTEXT_SIZE]; + } context; +} sss_sscp_mac_t; + +typedef struct _sss_sscp_asymmetric +{ + sss_sscp_session_t *session; + sss_sscp_object_t *keyObject; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + size_t signatureFullLen; + uint32_t sessionId; /*!< */ + /*! Implementation specific part */ +} sss_sscp_asymmetric_t; + +typedef struct _sss_sscp_tunnel +{ + sss_sscp_session_t *session; + uint32_t tunnelType; + uint32_t sessionId; /*!< */ + /*! Implementation specific part */ +} sss_sscp_tunnel_t; + +typedef struct _sss_sscp_derive_key +{ + sss_sscp_session_t *session; + sss_sscp_object_t *keyObject; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + uint32_t sessionId; /*!< */ + /*! Implementation specific part */ +} sss_sscp_derive_key_t; + +typedef struct +{ + /** Context holder of session */ + sss_sscp_session_t *session; +} sss_sscp_rng_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** + * @addtogroup sss_sscp_session + * @{ + */ +/** @copydoc sss_session_open + * + */ +sss_status_t sss_sscp_session_open(sss_sscp_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData); + +/** @copydoc sss_session_prop_get_u32 + * + */ +sss_status_t sss_sscp_session_prop_get_u32(sss_sscp_session_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_session_prop_get_au8 + * + */ +sss_status_t sss_sscp_session_prop_get_au8( + sss_sscp_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_session_close + * + */ +void sss_sscp_session_close(sss_sscp_session_t *session); + +/*! @} */ /* end of : sss_sscp_session */ + +/** + * @addtogroup sss_sscp_keyobj + * @{ + */ +/** @copydoc sss_key_object_init + * + */ +sss_status_t sss_sscp_key_object_init(sss_sscp_object_t *keyObject, sss_sscp_key_store_t *keyStore); + +/** @copydoc sss_key_object_allocate_handle + * + */ +sss_status_t sss_sscp_key_object_allocate_handle(sss_sscp_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); + +/** @copydoc sss_key_object_get_handle + * + */ +sss_status_t sss_sscp_key_object_get_handle(sss_sscp_object_t *keyObject, uint32_t keyId); + +/** @copydoc sss_key_object_set_user + * + */ +sss_status_t sss_sscp_key_object_set_user(sss_sscp_object_t *keyObject, uint32_t user, uint32_t options); + +/** @copydoc sss_key_object_set_purpose + * + */ +sss_status_t sss_sscp_key_object_set_purpose(sss_sscp_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** @copydoc sss_key_object_set_access + * + */ +sss_status_t sss_sscp_key_object_set_access(sss_sscp_object_t *keyObject, uint32_t access, uint32_t options); + +/** @copydoc sss_key_object_set_eccgfp_group + * + */ +sss_status_t sss_sscp_key_object_set_eccgfp_group(sss_sscp_object_t *keyObject, sss_eccgfp_group_t *group); + +/** @copydoc sss_key_object_get_user + * + */ +sss_status_t sss_sscp_key_object_get_user(sss_sscp_object_t *keyObject, uint32_t *user); + +/** @copydoc sss_key_object_get_purpose + * + */ +sss_status_t sss_sscp_key_object_get_purpose(sss_sscp_object_t *keyObject, sss_mode_t *purpose); + +/** @copydoc sss_key_object_get_access + * + */ +sss_status_t sss_sscp_key_object_get_access(sss_sscp_object_t *keyObject, uint32_t *access); + +/** @copydoc sss_key_object_free + * + */ +void sss_sscp_key_object_free(sss_sscp_object_t *keyObject); + +/*! @} */ /* end of : sss_sscp_keyobj */ + +/** + * @addtogroup sss_sscp_keyderive + * @{ + */ +/** @copydoc sss_derive_key_context_init + * + */ +sss_status_t sss_sscp_derive_key_context_init(sss_sscp_derive_key_t *context, + sss_sscp_session_t *session, + sss_sscp_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_derive_key_one_go +* +*/ +sss_status_t sss_sscp_derive_key_one_go(sss_sscp_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_sscp_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_sobj_one_go +* +*/ +sss_status_t sss_sscp_derive_key_sobj_one_go(sss_sscp_derive_key_t *context, + sss_sscp_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_sscp_object_t *derivedKeyObject, + uint16_t deriveDataLen); + +/** @copydoc sss_derive_key_go + * + */ +sss_status_t sss_sscp_derive_key_go(sss_sscp_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_sscp_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @copydoc sss_derive_key_dh + * + */ +sss_status_t sss_sscp_derive_key_dh( + sss_sscp_derive_key_t *context, sss_sscp_object_t *otherPartyKeyObject, sss_sscp_object_t *derivedKeyObject); + +/** @copydoc sss_derive_key_context_free + * + */ +void sss_sscp_derive_key_context_free(sss_sscp_derive_key_t *context); + +/*! @} */ /* end of : sss_sscp_keyderive */ + +/** + * @addtogroup sss_sscp_keystore + * @{ + */ +/** @copydoc sss_key_store_context_init + * + */ +sss_status_t sss_sscp_key_store_context_init(sss_sscp_key_store_t *keyStore, sss_sscp_session_t *session); + +/** @copydoc sss_key_store_allocate + * + */ +sss_status_t sss_sscp_key_store_allocate(sss_sscp_key_store_t *keyStore, uint32_t keyStoreId); + +/** @copydoc sss_key_store_save + * + */ +sss_status_t sss_sscp_key_store_save(sss_sscp_key_store_t *keyStore); + +/** @copydoc sss_key_store_load + * + */ +sss_status_t sss_sscp_key_store_load(sss_sscp_key_store_t *keyStore); + +/** @copydoc sss_key_store_set_key + * + */ +sss_status_t sss_sscp_key_store_set_key(sss_sscp_key_store_t *keyStore, + sss_sscp_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @copydoc sss_key_store_generate_key + * + */ +sss_status_t sss_sscp_key_store_generate_key( + sss_sscp_key_store_t *keyStore, sss_sscp_object_t *keyObject, size_t keyBitLen, void *options); + +/** @copydoc sss_key_store_get_key + * + */ +sss_status_t sss_sscp_key_store_get_key( + sss_sscp_key_store_t *keyStore, sss_sscp_object_t *keyObject, uint8_t *data, size_t *dataLen, size_t *pKeyBitLen); + +#if 0 +/* To be reviewed: Purnank */ +/** @copydoc sss_sscp_key_store_get_key_fromoffset + * + */ +sss_status_t sss_sscp_key_store_get_key_fromoffset(sss_sscp_key_store_t *keyStore, + sss_sscp_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen, + uint16_t offset); +#endif +/** @copydoc sss_key_store_open_key + * + */ +sss_status_t sss_sscp_key_store_open_key(sss_sscp_key_store_t *keyStore, sss_sscp_object_t *keyObject); + +/** @copydoc sss_key_store_freeze_key + * + */ +sss_status_t sss_sscp_key_store_freeze_key(sss_sscp_key_store_t *keyStore, sss_sscp_object_t *keyObject); + +/** @copydoc sss_key_store_erase_key + * + */ +sss_status_t sss_sscp_key_store_erase_key(sss_sscp_key_store_t *keyStore, sss_sscp_object_t *keyObject); + +/** @copydoc sss_key_store_context_free + * + */ +void sss_sscp_key_store_context_free(sss_sscp_key_store_t *keyStore); + +/*! @} */ /* end of : sss_sscp_keystore */ + +/** + * @addtogroup sss_sscp_asym + * @{ + */ +/** @copydoc sss_asymmetric_context_init + * + */ +sss_status_t sss_sscp_asymmetric_context_init(sss_sscp_asymmetric_t *context, + sss_sscp_session_t *session, + sss_sscp_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_asymmetric_encrypt + * + */ +sss_status_t sss_sscp_asymmetric_encrypt( + sss_sscp_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_decrypt + * + */ +sss_status_t sss_sscp_asymmetric_decrypt( + sss_sscp_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_sign_digest + * + */ +sss_status_t sss_sscp_asymmetric_sign_digest( + sss_sscp_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @copydoc sss_asymmetric_verify_digest + * + */ +sss_status_t sss_sscp_asymmetric_verify_digest( + sss_sscp_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @copydoc sss_asymmetric_context_free + * + */ +void sss_sscp_asymmetric_context_free(sss_sscp_asymmetric_t *context); + +/*! @} */ /* end of : sss_sscp_asym */ + +/** + * @addtogroup sss_sscp_symm + * @{ + */ +/** @copydoc sss_symmetric_context_init + * + */ +sss_status_t sss_sscp_symmetric_context_init(sss_sscp_symmetric_t *context, + sss_sscp_session_t *session, + sss_sscp_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_cipher_one_go + * + */ +sss_status_t sss_sscp_cipher_one_go(sss_sscp_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen); + +/** @copydoc sss_cipher_init + * + */ +sss_status_t sss_sscp_cipher_init(sss_sscp_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @copydoc sss_cipher_update + * + */ +sss_status_t sss_sscp_cipher_update( + sss_sscp_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_finish + * + */ +sss_status_t sss_sscp_cipher_finish( + sss_sscp_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_crypt_ctr + * + */ +sss_status_t sss_sscp_cipher_crypt_ctr(sss_sscp_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @copydoc sss_symmetric_context_free + * + */ +void sss_sscp_symmetric_context_free(sss_sscp_symmetric_t *context); + +/*! @} */ /* end of : sss_sscp_symm */ + +/** + * @addtogroup sss_sscp_aead + * @{ + */ +/** @copydoc sss_aead_context_init + * + */ +sss_status_t sss_sscp_aead_context_init(sss_sscp_aead_t *context, + sss_sscp_session_t *session, + sss_sscp_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_aead_one_go + * + */ +sss_status_t sss_sscp_aead_one_go(sss_sscp_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_init + * + */ +sss_status_t sss_sscp_aead_init( + sss_sscp_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); + +/** @copydoc sss_aead_update_aad + * + */ +sss_status_t sss_sscp_aead_update_aad(sss_sscp_aead_t *context, const uint8_t *aadData, size_t aadDataLen); + +/** @copydoc sss_aead_update + * + */ +sss_status_t sss_sscp_aead_update( + sss_sscp_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_aead_finish + * + */ +sss_status_t sss_sscp_aead_finish(sss_sscp_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); + +/** @copydoc sss_aead_context_free + * + */ +void sss_sscp_aead_context_free(sss_sscp_aead_t *context); + +/*! @} */ /* end of : sss_sscp_aead */ + +/** + * @addtogroup sss_sscp_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_sscp_mac_context_init(sss_sscp_mac_t *context, + sss_sscp_session_t *session, + sss_sscp_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_sscp_mac_one_go( + sss_sscp_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_init + * + */ +sss_status_t sss_sscp_mac_init(sss_sscp_mac_t *context); + +/** @copydoc sss_mac_update + * + */ +sss_status_t sss_sscp_mac_update(sss_sscp_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_mac_finish + * + */ +sss_status_t sss_sscp_mac_finish(sss_sscp_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_sscp_mac_context_free(sss_sscp_mac_t *context); + +/*! @} */ /* end of : sss_sscp_mac */ + +/** + * @addtogroup sss_sscp_md + * @{ + */ +/** @copydoc sss_digest_context_init + * + */ +sss_status_t sss_sscp_digest_context_init( + sss_sscp_digest_t *context, sss_sscp_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_digest_one_go + * + */ +sss_status_t sss_sscp_digest_one_go( + sss_sscp_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_init + * + */ +sss_status_t sss_sscp_digest_init(sss_sscp_digest_t *context); + +/** @copydoc sss_digest_update + * + */ +sss_status_t sss_sscp_digest_update(sss_sscp_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_digest_finish + * + */ +sss_status_t sss_sscp_digest_finish(sss_sscp_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_context_free + * + */ +void sss_sscp_digest_context_free(sss_sscp_digest_t *context); + +/*! @} */ /* end of : sss_sscp_md */ + +/** + * @addtogroup sss_sscp_rng + * @{ + */ +/** @copydoc sss_rng_context_init + * + */ +sss_status_t sss_sscp_rng_context_init(sss_sscp_rng_context_t *context, sss_sscp_session_t *session); + +/** @copydoc sss_rng_get_random + * + */ +sss_status_t sss_sscp_rng_get_random(sss_sscp_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** @copydoc sss_rng_context_free + * + */ +sss_status_t sss_sscp_rng_context_free(sss_sscp_rng_context_t *context); + +/*! @} */ /* end of : sss_sscp_rng */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_SSS_SSCP_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h new file mode 100644 index 00000000000..65900ab508a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h @@ -0,0 +1,627 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef fsl_sss_user_apis_H +#define fsl_sss_user_apis_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_HOSTCRYPTO_USER +#include + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/** + * @addtogroup sss_user_impl_session + * @{ + */ +/** @copydoc sss_session_create + * + */ +sss_status_t sss_user_impl_session_create(sss_user_impl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connetion_type, + void *connectionData); + +/** @copydoc sss_session_open + * + */ +sss_status_t sss_user_impl_session_open(sss_user_impl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connetion_type, + void *connectionData); + +/** @copydoc sss_session_prop_get_u32 + * + */ +sss_status_t sss_user_impl_session_prop_get_u32(sss_user_impl_session_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_session_prop_get_au8 + * + */ +sss_status_t sss_user_impl_session_prop_get_au8( + sss_user_impl_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_session_close + * + */ +void sss_user_impl_session_close(sss_user_impl_session_t *session); + +/** @copydoc sss_session_delete + * + */ +void sss_user_impl_session_delete(sss_user_impl_session_t *session); + +/*! @} */ /* end of : sss_user_impl_session */ + +/** + * @addtogroup sss_user_impl_keyobj + * @{ + */ +/** @copydoc sss_key_object_init + * + */ +sss_status_t sss_user_impl_key_object_init(sss_user_impl_object_t *keyObject, sss_user_impl_key_store_t *keyStore); + +/** @copydoc sss_key_object_allocate_handle + * + */ +sss_status_t sss_user_impl_key_object_allocate_handle(sss_user_impl_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options); + +/** @copydoc sss_key_object_get_handle + * + */ +sss_status_t sss_user_impl_key_object_get_handle(sss_user_impl_object_t *keyObject, uint32_t keyId); + +/** @copydoc sss_key_object_set_user + * + */ +sss_status_t sss_user_impl_key_object_set_user(sss_user_impl_object_t *keyObject, uint32_t user, uint32_t options); + +/** @copydoc sss_key_object_set_purpose + * + */ +sss_status_t sss_user_impl_key_object_set_purpose( + sss_user_impl_object_t *keyObject, sss_mode_t purpose, uint32_t options); + +/** @copydoc sss_key_object_set_access + * + */ +sss_status_t sss_user_impl_key_object_set_access(sss_user_impl_object_t *keyObject, uint32_t access, uint32_t options); + +/** @copydoc sss_key_object_set_eccgfp_group + * + */ +sss_status_t sss_user_impl_key_object_set_eccgfp_group(sss_user_impl_object_t *keyObject, sss_eccgfp_group_t *group); + +/** @copydoc sss_key_object_get_user + * + */ +sss_status_t sss_user_impl_key_object_get_user(sss_user_impl_object_t *keyObject, uint32_t *user); + +/** @copydoc sss_key_object_get_purpose + * + */ +sss_status_t sss_user_impl_key_object_get_purpose(sss_user_impl_object_t *keyObject, sss_mode_t *purpose); + +/** @copydoc sss_key_object_get_access + * + */ +sss_status_t sss_user_impl_key_object_get_access(sss_user_impl_object_t *keyObject, uint32_t *access); + +/** @copydoc sss_key_object_free + * + */ +void sss_user_impl_key_object_free(sss_user_impl_object_t *keyObject); + +/*! @} */ /* end of : sss_user_impl_keyobj */ + +/** + * @addtogroup sss_user_impl_keyderive + * @{ + */ +/** @copydoc sss_derive_key_context_init + * + */ +sss_status_t sss_user_impl_derive_key_context_init(sss_user_impl_derive_key_t *context, + sss_user_impl_session_t *session, + sss_user_impl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_derive_key_go + * + */ +sss_status_t sss_user_impl_derive_key_go(sss_user_impl_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_user_impl_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen); + +/** @copydoc sss_derive_key_dh + * + */ +sss_status_t sss_user_impl_derive_key_dh(sss_user_impl_derive_key_t *context, + sss_user_impl_object_t *otherPartyKeyObject, + sss_user_impl_object_t *derivedKeyObject); + +/** @copydoc sss_derive_key_context_free + * + */ +void sss_user_impl_derive_key_context_free(sss_user_impl_derive_key_t *context); + +/*! @} */ /* end of : sss_user_impl_keyderive */ + +/** + * @addtogroup sss_user_impl_keystore + * @{ + */ +/** @copydoc sss_key_store_context_init + * + */ +sss_status_t sss_user_impl_key_store_context_init( + sss_user_impl_key_store_t *keyStore, sss_user_impl_session_t *session); + +/** @copydoc sss_key_store_allocate + * + */ +sss_status_t sss_user_impl_key_store_allocate(sss_user_impl_key_store_t *keyStore, uint32_t keyStoreId); + +/** @copydoc sss_key_store_save + * + */ +sss_status_t sss_user_impl_key_store_save(sss_user_impl_key_store_t *keyStore); + +/** @copydoc sss_key_store_load + * + */ +sss_status_t sss_user_impl_key_store_load(sss_user_impl_key_store_t *keyStore); + +/** @copydoc sss_key_store_set_key + * + */ +sss_status_t sss_user_impl_key_store_set_key(sss_user_impl_key_store_t *keyStore, + sss_user_impl_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen); + +/** @copydoc sss_key_store_generate_key + * + */ +sss_status_t sss_user_impl_key_store_generate_key( + sss_user_impl_key_store_t *keyStore, sss_user_impl_object_t *keyObject, size_t keyBitLen, void *options); + +/** @copydoc sss_key_store_get_key + * + */ +sss_status_t sss_user_impl_key_store_get_key(sss_user_impl_key_store_t *keyStore, + sss_user_impl_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen); + +/** @copydoc sss_key_store_open_key + * + */ +sss_status_t sss_user_impl_key_store_open_key(sss_user_impl_key_store_t *keyStore, sss_user_impl_object_t *keyObject); + +/** @copydoc sss_key_store_freeze_key + * + */ +sss_status_t sss_user_impl_key_store_freeze_key(sss_user_impl_key_store_t *keyStore, sss_user_impl_object_t *keyObject); + +/** @copydoc sss_key_store_erase_key + * + */ +sss_status_t sss_user_impl_key_store_erase_key(sss_user_impl_key_store_t *keyStore, sss_user_impl_object_t *keyObject); + +/** @copydoc sss_key_store_prop_get_u32 + * + */ +sss_status_t sss_user_impl_key_store_prop_get_u32( + sss_user_impl_key_store_t *session, uint32_t property, uint32_t *pValue); + +/** @copydoc sss_key_store_prop_get_au8 + * + */ +sss_status_t sss_user_impl_key_store_prop_get_au8( + sss_user_impl_key_store_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen); + +/** @copydoc sss_key_store_context_free + * + */ +void sss_user_impl_key_store_context_free(sss_user_impl_key_store_t *keyStore); + +/*! @} */ /* end of : sss_user_impl_keystore */ + +/** + * @addtogroup sss_user_impl_asym + * @{ + */ +/** @copydoc sss_asymmetric_context_init + * + */ +sss_status_t sss_user_impl_asymmetric_context_init(sss_user_impl_asymmetric_t *context, + sss_user_impl_session_t *session, + sss_user_impl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_asymmetric_encrypt + * + */ +sss_status_t sss_user_impl_asymmetric_encrypt( + sss_user_impl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_decrypt + * + */ +sss_status_t sss_user_impl_asymmetric_decrypt( + sss_user_impl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_asymmetric_sign_digest + * + */ +sss_status_t sss_user_impl_asymmetric_sign_digest( + sss_user_impl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen); + +/** @copydoc sss_asymmetric_verify_digest + * + */ +sss_status_t sss_user_impl_asymmetric_verify_digest( + sss_user_impl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen); + +/** @copydoc sss_asymmetric_context_free + * + */ +void sss_user_impl_asymmetric_context_free(sss_user_impl_asymmetric_t *context); + +/*! @} */ /* end of : sss_user_impl_asym */ + +/** + * @addtogroup sss_user_impl_symm + * @{ + */ +/** @copydoc sss_symmetric_context_init + * + */ +sss_status_t sss_user_impl_symmetric_context_init(sss_user_impl_symmetric_t *context, + sss_user_impl_session_t *session, + sss_user_impl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_cipher_one_go + * + */ +sss_status_t sss_user_impl_cipher_one_go(sss_user_impl_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen); + +/** @copydoc sss_cipher_init + * + */ +sss_status_t sss_user_impl_cipher_init(sss_user_impl_symmetric_t *context, uint8_t *iv, size_t ivLen); + +/** @copydoc sss_cipher_update + * + */ +sss_status_t sss_user_impl_cipher_update( + sss_user_impl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_finish + * + */ +sss_status_t sss_user_impl_cipher_finish( + sss_user_impl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen); + +/** @copydoc sss_cipher_crypt_ctr + * + */ +sss_status_t sss_user_impl_cipher_crypt_ctr(sss_user_impl_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft); + +/** @copydoc sss_symmetric_context_free + * + */ +void sss_user_impl_symmetric_context_free(sss_user_impl_symmetric_t *context); + +/*! @} */ /* end of : sss_user_impl_symm */ + +/** + * @addtogroup sss_user_impl_aead + * @{ + */ + +/** + * @addtogroup sss_user_impl_mac + * @{ + */ +/** @copydoc sss_mac_context_init + * + */ +sss_status_t sss_user_impl_mac_context_init(sss_user_impl_mac_t *context, + sss_user_impl_session_t *session, + sss_user_impl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode); + +/** @copydoc sss_mac_one_go + * + */ +sss_status_t sss_user_impl_mac_one_go( + sss_user_impl_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_init + * + */ +sss_status_t sss_user_impl_mac_init(sss_user_impl_mac_t *context); + +/** @copydoc sss_mac_update + * + */ +sss_status_t sss_user_impl_mac_update(sss_user_impl_mac_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_mac_finish + * + */ +sss_status_t sss_user_impl_mac_finish(sss_user_impl_mac_t *context, uint8_t *mac, size_t *macLen); + +/** @copydoc sss_mac_context_free + * + */ +void sss_user_impl_mac_context_free(sss_user_impl_mac_t *context); + +/*! @} */ /* end of : sss_user_impl_mac */ + +/** + * @addtogroup sss_user_impl_md + * @{ + */ +/** @copydoc sss_digest_context_init + * + */ +sss_status_t sss_user_impl_digest_context_init( + sss_user_impl_digest_t *context, sss_user_impl_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode); + +/** @copydoc sss_digest_one_go + * + */ +sss_status_t sss_user_impl_digest_one_go( + sss_user_impl_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_init + * + */ +sss_status_t sss_user_impl_digest_init(sss_user_impl_digest_t *context); + +/** @copydoc sss_digest_update + * + */ +sss_status_t sss_user_impl_digest_update(sss_user_impl_digest_t *context, const uint8_t *message, size_t messageLen); + +/** @copydoc sss_digest_finish + * + */ +sss_status_t sss_user_impl_digest_finish(sss_user_impl_digest_t *context, uint8_t *digest, size_t *digestLen); + +/** @copydoc sss_digest_context_free + * + */ +void sss_user_impl_digest_context_free(sss_user_impl_digest_t *context); + +/*! @} */ /* end of : sss_user_impl_md */ + +/** + * @addtogroup sss_user_impl_rng + * @{ + */ +/** @copydoc sss_rng_context_init + * + */ +sss_status_t sss_user_impl_rng_context_init(sss_user_impl_rng_context_t *context, sss_user_impl_session_t *session); + +/** @copydoc sss_rng_get_random + * + */ +sss_status_t sss_user_impl_rng_get_random(sss_user_impl_rng_context_t *context, uint8_t *random_data, size_t dataLen); + +/** @copydoc sss_rng_context_free + * + */ +sss_status_t sss_user_impl_rng_context_free(sss_user_impl_rng_context_t *context); + +/*! @} */ /* end of : sss_user_impl_rng */ + +/* clang-format off */ + + /* Host Call : session */ +# define sss_host_session_create(session,subsystem,application_id,connetion_type,connectionData) \ + sss_user_impl_session_create(((sss_user_impl_session_t * ) session),(subsystem),(application_id),(connetion_type),(connectionData)) +# define sss_host_session_open(session,subsystem,application_id,connetion_type,connectionData) \ + sss_user_impl_session_open(((sss_user_impl_session_t * ) session),(subsystem),(application_id),(connetion_type),(connectionData)) +# define sss_host_session_prop_get_u32(session,property,pValue) \ + sss_user_impl_session_prop_get_u32(((sss_user_impl_session_t * ) session),(property),(pValue)) +# define sss_host_session_prop_get_au8(session,property,pValue,pValueLen) \ + sss_user_impl_session_prop_get_au8(((sss_user_impl_session_t * ) session),(property),(pValue),(pValueLen)) +# define sss_host_session_close(session) \ + sss_user_impl_session_close(((sss_user_impl_session_t * ) session)) +# define sss_host_session_delete(session) \ + sss_user_impl_session_delete(((sss_user_impl_session_t * ) session)) + /* Host Call : keyobj */ +# define sss_host_key_object_init(keyObject,keyStore) \ + sss_user_impl_key_object_init(((sss_user_impl_object_t * ) keyObject),((sss_user_impl_key_store_t * ) keyStore)) +# define sss_host_key_object_allocate_handle(keyObject,keyId,keyPart,cipherType,keyByteLenMax,options) \ + sss_user_impl_key_object_allocate_handle(((sss_user_impl_object_t * ) keyObject),(keyId),(keyPart),(cipherType),(keyByteLenMax),(options)) +# define sss_host_key_object_get_handle(keyObject,keyId) \ + sss_user_impl_key_object_get_handle(((sss_user_impl_object_t * ) keyObject),(keyId)) +# define sss_host_key_object_set_user(keyObject,user,options) \ + sss_user_impl_key_object_set_user(((sss_user_impl_object_t * ) keyObject),(user),(options)) +# define sss_host_key_object_set_purpose(keyObject,purpose,options) \ + sss_user_impl_key_object_set_purpose(((sss_user_impl_object_t * ) keyObject),(purpose),(options)) +# define sss_host_key_object_set_access(keyObject,access,options) \ + sss_user_impl_key_object_set_access(((sss_user_impl_object_t * ) keyObject),(access),(options)) +# define sss_host_key_object_set_eccgfp_group(keyObject,group) \ + sss_user_impl_key_object_set_eccgfp_group(((sss_user_impl_object_t * ) keyObject),(group)) +# define sss_host_key_object_get_user(keyObject,user) \ + sss_user_impl_key_object_get_user(((sss_user_impl_object_t * ) keyObject),(user)) +# define sss_host_key_object_get_purpose(keyObject,purpose) \ + sss_user_impl_key_object_get_purpose(((sss_user_impl_object_t * ) keyObject),(purpose)) +# define sss_host_key_object_get_access(keyObject,access) \ + sss_user_impl_key_object_get_access(((sss_user_impl_object_t * ) keyObject),(access)) +# define sss_host_key_object_free(keyObject) \ + sss_user_impl_key_object_free(((sss_user_impl_object_t * ) keyObject)) + /* Host Call : keyderive */ +# define sss_host_derive_key_context_init(context,session,keyObject,algorithm,mode) \ + sss_user_impl_derive_key_context_init(((sss_user_impl_derive_key_t * ) context),((sss_user_impl_session_t * ) session),((sss_user_impl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_derive_key_go(context,saltData,saltLen,info,infoLen,derivedKeyObject,deriveDataLen,hkdfOutput,hkdfOutputLen) \ + sss_user_impl_derive_key_go(((sss_user_impl_derive_key_t * ) context),(saltData),(saltLen),(info),(infoLen),((sss_user_impl_object_t * ) derivedKeyObject),(deriveDataLen),(hkdfOutput),(hkdfOutputLen)) +# define sss_host_derive_key_dh(context,otherPartyKeyObject,derivedKeyObject) \ + sss_user_impl_derive_key_dh(((sss_user_impl_derive_key_t * ) context),((sss_user_impl_object_t * ) otherPartyKeyObject),((sss_user_impl_object_t * ) derivedKeyObject)) +# define sss_host_derive_key_context_free(context) \ + sss_user_impl_derive_key_context_free(((sss_user_impl_derive_key_t * ) context)) + /* Host Call : keystore */ +# define sss_host_key_store_context_init(keyStore,session) \ + sss_user_impl_key_store_context_init(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_session_t * ) session)) +# define sss_host_key_store_allocate(keyStore,keyStoreId) \ + sss_user_impl_key_store_allocate(((sss_user_impl_key_store_t * ) keyStore),(keyStoreId)) +# define sss_host_key_store_save(keyStore) \ + sss_user_impl_key_store_save(((sss_user_impl_key_store_t * ) keyStore)) +# define sss_host_key_store_load(keyStore) \ + sss_user_impl_key_store_load(((sss_user_impl_key_store_t * ) keyStore)) +# define sss_host_key_store_set_key(keyStore,keyObject,data,dataLen,keyBitLen,options,optionsLen) \ + sss_user_impl_key_store_set_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject),(data),(dataLen),(keyBitLen),(options),(optionsLen)) +# define sss_host_key_store_generate_key(keyStore,keyObject,keyBitLen,options) \ + sss_user_impl_key_store_generate_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject),(keyBitLen),(options)) +# define sss_host_key_store_get_key(keyStore,keyObject,data,dataLen,pKeyBitLen) \ + sss_user_impl_key_store_get_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject),(data),(dataLen),(pKeyBitLen)) +# define sss_host_key_store_open_key(keyStore,keyObject) \ + sss_user_impl_key_store_open_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject)) +# define sss_host_key_store_freeze_key(keyStore,keyObject) \ + sss_user_impl_key_store_freeze_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject)) +# define sss_host_key_store_erase_key(keyStore,keyObject) \ + sss_user_impl_key_store_erase_key(((sss_user_impl_key_store_t * ) keyStore),((sss_user_impl_object_t * ) keyObject)) +# define sss_host_key_store_prop_get_u32(session,property,pValue) \ + sss_user_impl_key_store_prop_get_u32(((sss_user_impl_key_store_t * ) session),(property),(pValue)) +# define sss_host_key_store_prop_get_au8(session,property,pValue,pValueLen) \ + sss_user_impl_key_store_prop_get_au8(((sss_user_impl_key_store_t * ) session),(property),(pValue),(pValueLen)) +# define sss_host_key_store_context_free(keyStore) \ + sss_user_impl_key_store_context_free(((sss_user_impl_key_store_t * ) keyStore)) + /* Host Call : asym */ +# define sss_host_asymmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_user_impl_asymmetric_context_init(((sss_user_impl_asymmetric_t * ) context),((sss_user_impl_session_t * ) session),((sss_user_impl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_asymmetric_encrypt(context,srcData,srcLen,destData,destLen) \ + sss_user_impl_asymmetric_encrypt(((sss_user_impl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_decrypt(context,srcData,srcLen,destData,destLen) \ + sss_user_impl_asymmetric_decrypt(((sss_user_impl_asymmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_asymmetric_sign_digest(context,digest,digestLen,signature,signatureLen) \ + sss_user_impl_asymmetric_sign_digest(((sss_user_impl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_verify_digest(context,digest,digestLen,signature,signatureLen) \ + sss_user_impl_asymmetric_verify_digest(((sss_user_impl_asymmetric_t * ) context),(digest),(digestLen),(signature),(signatureLen)) +# define sss_host_asymmetric_context_free(context) \ + sss_user_impl_asymmetric_context_free(((sss_user_impl_asymmetric_t * ) context)) + /* Host Call : symm */ +# define sss_host_symmetric_context_init(context,session,keyObject,algorithm,mode) \ + sss_user_impl_symmetric_context_init(((sss_user_impl_symmetric_t * ) context),((sss_user_impl_session_t * ) session),((sss_user_impl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_cipher_one_go(context,iv,ivLen,srcData,destData,dataLen) \ + sss_user_impl_cipher_one_go(((sss_user_impl_symmetric_t * ) context),(iv),(ivLen),(srcData),(destData),(dataLen)) +# define sss_host_cipher_init(context,iv,ivLen) \ + sss_user_impl_cipher_init(((sss_user_impl_symmetric_t * ) context),(iv),(ivLen)) +# define sss_host_cipher_update(context,srcData,srcLen,destData,destLen) \ + sss_user_impl_cipher_update(((sss_user_impl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_finish(context,srcData,srcLen,destData,destLen) \ + sss_user_impl_cipher_finish(((sss_user_impl_symmetric_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_cipher_crypt_ctr(context,srcData,destData,size,initialCounter,lastEncryptedCounter,szLeft) \ + sss_user_impl_cipher_crypt_ctr(((sss_user_impl_symmetric_t * ) context),(srcData),(destData),(size),(initialCounter),(lastEncryptedCounter),(szLeft)) +# define sss_host_symmetric_context_free(context) \ + sss_user_impl_symmetric_context_free(((sss_user_impl_symmetric_t * ) context)) + /* Host Call : aead */ +# define sss_host_aead_context_init(context,session,keyObject,algorithm,mode) \ + sss_user_impl_aead_context_init(((sss_user_impl_aead_t * ) context),((sss_user_impl_session_t * ) session),((sss_user_impl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_aead_one_go(context,srcData,destData,size,nonce,nonceLen,aad,aadLen,tag,tagLen) \ + sss_user_impl_aead_one_go(((sss_user_impl_aead_t * ) context),(srcData),(destData),(size),(nonce),(nonceLen),(aad),(aadLen),(tag),(tagLen)) +# define sss_host_aead_init(context,nonce,nonceLen,tagLen,aadLen,payloadLen) \ + sss_user_impl_aead_init(((sss_user_impl_aead_t * ) context),(nonce),(nonceLen),(tagLen),(aadLen),(payloadLen)) +# define sss_host_aead_update_aad(context,aadData,aadDataLen) \ + sss_user_impl_aead_update_aad(((sss_user_impl_aead_t * ) context),(aadData),(aadDataLen)) +# define sss_host_aead_update(context,srcData,srcLen,destData,destLen) \ + sss_user_impl_aead_update(((sss_user_impl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen)) +# define sss_host_aead_finish(context,srcData,srcLen,destData,destLen,tag,tagLen) \ + sss_user_impl_aead_finish(((sss_user_impl_aead_t * ) context),(srcData),(srcLen),(destData),(destLen),(tag),(tagLen)) +# define sss_host_aead_context_free(context) \ + sss_user_impl_aead_context_free(((sss_user_impl_aead_t * ) context)) + /* Host Call : mac */ +# define sss_host_mac_context_init(context,session,keyObject,algorithm,mode) \ + sss_user_impl_mac_context_init(((sss_user_impl_mac_t * ) context),((sss_user_impl_session_t * ) session),((sss_user_impl_object_t * ) keyObject),(algorithm),(mode)) +# define sss_host_mac_one_go(context,message,messageLen,mac,macLen) \ + sss_user_impl_mac_one_go(((sss_user_impl_mac_t * ) context),(message),(messageLen),(mac),(macLen)) +# define sss_host_mac_init(context) \ + sss_user_impl_mac_init(((sss_user_impl_mac_t * ) context)) +# define sss_host_mac_update(context,message,messageLen) \ + sss_user_impl_mac_update(((sss_user_impl_mac_t * ) context),(message),(messageLen)) +# define sss_host_mac_finish(context,mac,macLen) \ + sss_user_impl_mac_finish(((sss_user_impl_mac_t * ) context),(mac),(macLen)) +# define sss_host_mac_context_free(context) \ + sss_user_impl_mac_context_free(((sss_user_impl_mac_t * ) context)) + /* Host Call : md */ +# define sss_host_digest_context_init(context,session,algorithm,mode) \ + sss_user_impl_digest_context_init(((sss_user_impl_digest_t * ) context),((sss_user_impl_session_t * ) session),(algorithm),(mode)) +# define sss_host_digest_one_go(context,message,messageLen,digest,digestLen) \ + sss_user_impl_digest_one_go(((sss_user_impl_digest_t * ) context),(message),(messageLen),(digest),(digestLen)) +# define sss_host_digest_init(context) \ + sss_user_impl_digest_init(((sss_user_impl_digest_t * ) context)) +# define sss_host_digest_update(context,message,messageLen) \ + sss_user_impl_digest_update(((sss_user_impl_digest_t * ) context),(message),(messageLen)) +# define sss_host_digest_finish(context,digest,digestLen) \ + sss_user_impl_digest_finish(((sss_user_impl_digest_t * ) context),(digest),(digestLen)) +# define sss_host_digest_context_free(context) \ + sss_user_impl_digest_context_free(((sss_user_impl_digest_t * ) context)) + /* Host Call : rng */ +# define sss_host_rng_context_init(context,session) \ + sss_user_impl_rng_context_init(((sss_user_impl_rng_context_t * ) context),((sss_user_impl_session_t * ) session)) +# define sss_host_rng_get_random(context,random_data,dataLen) \ + sss_user_impl_rng_get_random(((sss_user_impl_rng_context_t * ) context),(random_data),(dataLen)) +# define sss_host_rng_context_free(context) \ + sss_user_impl_rng_context_free(((sss_user_impl_rng_context_t * ) context)) + +/* clang-format on */ +#endif /* SSS_HAVE_HOSTCRYPTO_USER */ +#ifdef __cplusplus +} // extern "C" +#endif /* __cplusplus */ + +#endif /* fsl_sss_user_apis_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h new file mode 100644 index 00000000000..302c34e9023 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h @@ -0,0 +1,144 @@ +/* + * + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_fsl_sss_user_types_H_ +#define SSS_APIS_INC_fsl_sss_user_types_H_ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_HOSTCRYPTO_USER + +/** + * @addtogroup sss_sw_host_impl + * @{ + */ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +#define SSS_SUBSYSTEM_TYPE_IS_HOST(subsystem) (subsystem == kType_SSS_mbedTLS) + +#define SSS_SESSION_TYPE_IS_HOST(session) (session && SSS_SUBSYSTEM_TYPE_IS_HOST(session->subsystem)) + +#define SSS_KEY_STORE_TYPE_IS_HOST(keyStore) (keyStore && SSS_SESSION_TYPE_IS_HOST(keyStore->session)) + +#define SSS_OBJECT_TYPE_IS_HOST(pObject) (pObject && SSS_KEY_STORE_TYPE_IS_HOST(pObject->keyStore)) + +#define SSS_SYMMETRIC_TYPE_IS_HOST(context) (context && SSS_SESSION_TYPE_IS_HOST(context->session)) + +#define SSS_RNG_CONTEXT_TYPE_IS_HOST(context) (context && SSS_SESSION_TYPE_IS_HOST(context->session)) + +/* ************************************************************************** */ +/* Structrues and Typedefs */ +/* ************************************************************************** */ + +struct _sss_user_impl_session; + +typedef struct _sss_user_impl_session +{ + /*! Indicates which security subsystem is selected to be used. */ + sss_type_t subsystem; + +} sss_user_impl_session_t; + +struct _sss_user_impl_object; + +typedef struct _sss_user_impl_key_store +{ + sss_user_impl_session_t *session; + +} sss_user_impl_key_store_t; + +typedef struct _sss_user_impl_object +{ + /*! key store holding the data and other properties */ + sss_user_impl_key_store_t *keyStore; + /*! Object types */ + uint32_t objectType; + uint32_t cipherType; + /*! Application specific key identifier. The keyId is kept in the key store + * along with the key data and other properties. */ + uint32_t keyId; +} sss_user_impl_object_t; + +typedef struct _sss_user_impl_derive_key +{ + sss_user_impl_session_t *session; + sss_user_impl_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ +} sss_user_impl_derive_key_t; + +typedef struct _sss_user_impl_asymmetric +{ + sss_user_impl_session_t *session; + sss_user_impl_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ +} sss_user_impl_asymmetric_t; + +typedef struct _sss_user_impl_symmetric +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_user_impl_session_t *session; + /*** Reference to key and it's properties. */ + sss_user_impl_object_t *keyObject; + sss_algorithm_t algorithm; + sss_mode_t mode; +} sss_user_impl_symmetric_t; + +typedef struct _sss_user_impl_mac +{ + sss_user_impl_session_t *session; + /*! Reference to key and it's properties. */ + sss_user_impl_object_t *keyObject; + sss_algorithm_t algorithm; /*! */ + sss_mode_t mode; /*! */ +} sss_user_impl_mac_t; + +typedef struct _sss_user_impl_digest +{ + /*! Virtual connection between application (user context) and specific + * security subsystem and function thereof. */ + sss_user_impl_session_t *session; + sss_algorithm_t algorithm; /*!< */ + sss_mode_t mode; /*!< */ + /*! Full digest length per algorithm definition. This field is initialized along with algorithm. */ + size_t digestFullLen; + /*! Implementation specific part */ +} sss_user_impl_digest_t; + +typedef struct +{ + sss_user_impl_session_t *session; + +} sss_user_impl_rng_context_t; + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ + +/** @} */ + +#endif /* SSS_HAVE_HOSTCRYPTO_USER */ + +#endif /* SSS_APIS_INC_fsl_sss_user_types_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h new file mode 100644 index 00000000000..ae83a08ca91 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h @@ -0,0 +1,175 @@ +/* +* +* Copyright 2018-2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#ifndef FSL_SSS_UTIL_ASN1_DER_H +#define FSL_SSS_UTIL_ASN1_DER_H + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ +#define ASN_TAG_INT 0x02 +#define ASN_TAG_SEQUENCE 0x30 +#define ASN_TAG_BITSTRING 0x03 +#define ASN_TAG_OCTETSTRING 0x04 +#define ASN_TAG_OBJ_IDF 0x06 +#define ASN_TAG_CNT_SPECIFIC 0xA1 +#define ASN_TAG_CNT_SPECIFIC_PRIMITIVE 0x80 +#define ASN_TAG_CRL_EXTENSIONS 0xA0 + +extern const uint8_t grsa1kPubHeader[]; +extern const uint8_t grsa1152PubHeader[]; +extern const uint8_t grsa2kPubHeader[]; +extern const uint8_t grsa3kPubHeader[]; +extern const uint8_t grsa4kPubHeader[]; +extern const uint8_t gecc_der_header_nist192[]; +extern const uint8_t gecc_der_header_nist224[]; +extern const uint8_t gecc_der_header_nist256[]; +extern const uint8_t gecc_der_header_nist384[]; +extern const uint8_t gecc_der_header_nist521[]; +extern const uint8_t gecc_der_header_160k[]; +extern const uint8_t gecc_der_header_192k[]; +extern const uint8_t gecc_der_header_224k[]; +extern const uint8_t gecc_der_header_256k[]; +extern const uint8_t gecc_der_header_bp160[]; +extern const uint8_t gecc_der_header_bp192[]; +extern const uint8_t gecc_der_header_bp224[]; +extern const uint8_t gecc_der_header_bp256[]; +extern const uint8_t gecc_der_header_bp320[]; +extern const uint8_t gecc_der_header_bp384[]; +extern const uint8_t gecc_der_header_bp512[]; +extern const uint8_t gecc_der_header_mont_dh_448[]; +extern const uint8_t gecc_der_header_mont_dh_25519[]; +extern const uint8_t gecc_der_header_twisted_ed_25519[]; + +extern const size_t der_ecc_nistp192_header_len; +extern const size_t der_ecc_nistp224_header_len; +extern const size_t der_ecc_nistp256_header_len; +extern const size_t der_ecc_nistp384_header_len; +extern const size_t der_ecc_nistp521_header_len; +extern const size_t der_ecc_160k_header_len; +extern const size_t der_ecc_192k_header_len; +extern const size_t der_ecc_224k_header_len; +extern const size_t der_ecc_256k_header_len; +extern const size_t der_ecc_bp160_header_len; +extern const size_t der_ecc_bp192_header_len; +extern const size_t der_ecc_bp224_header_len; +extern const size_t der_ecc_bp256_header_len; +extern const size_t der_ecc_bp320_header_len; +extern const size_t der_ecc_bp384_header_len; +extern const size_t der_ecc_bp512_header_len; +extern const size_t der_ecc_mont_dh_448_header_len; +extern const size_t der_ecc_mont_dh_25519_header_len; +extern const size_t der_ecc_twisted_ed_25519_header_len; + +/* ************************************************************************** */ +/* Functions */ +/* ************************************************************************** */ +/**/ +sss_status_t sss_util_asn1_rsa_parse_private(const uint8_t *key, + size_t keylen, + sss_cipher_type_t cipher_type, + uint8_t **modulus, + size_t *modlen, + uint8_t **pubExp, + size_t *pubExplen, + uint8_t **priExp, + size_t *priExplen, + uint8_t **prime1, + size_t *prime1len, + uint8_t **prime2, + size_t *prime2len, + uint8_t **exponent1, + size_t *exponent1len, + uint8_t **exponent2, + size_t *exponent2len, + uint8_t **coefficient, + size_t *coefficientlen); + +sss_status_t sss_util_asn1_rsa_parse_private_allow_invalid_key(const uint8_t *key, + size_t keylen, + sss_cipher_type_t cipher_type, + uint8_t **modulus, + size_t *modlen, + uint8_t **pubExp, + size_t *pubExplen, + uint8_t **priExp, + size_t *priExplen, + uint8_t **prime1, + size_t *prime1len, + uint8_t **prime2, + size_t *prime2len, + uint8_t **exponent1, + size_t *exponent1len, + uint8_t **exponent2, + size_t *exponent2len, + uint8_t **coefficient, + size_t *coefficientlen); + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen); + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc_complete_modulus( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen); + +sss_status_t sss_util_asn1_rsa_parse_public( + const uint8_t *key, size_t keylen, uint8_t **modulus, size_t *modlen, uint8_t **pubExp, size_t *pubExplen); + +sss_status_t sss_util_asn1_rsa_get_public( + uint8_t *key, size_t *keylen, uint8_t *modulus, size_t modlen, uint8_t *pubExp, size_t pubExplen); + +#if SSS_HAVE_ECDAA +sss_status_t sss_util_asn1_ecdaa_get_signature( + uint8_t *signature, size_t *signatureLen, uint8_t *rawSignature, size_t rawSignatureLen); +#endif + +sss_status_t sss_util_asn1_get_oid_from_header(uint8_t *input, size_t inLen, uint32_t *output, uint8_t *outLen); + +sss_status_t sss_util_asn1_get_oid_from_sssObj(sss_object_t *pkeyObject, uint32_t *output, uint8_t *outLen); + +sss_status_t sss_util_pkcs8_asn1_get_ec_public_key_index( + const uint8_t *input, size_t inLen, uint16_t *outkeyIndex, size_t *publicKeyLen); + +sss_status_t sss_util_pkcs8_asn1_get_ec_pair_key_index(const uint8_t *input, + size_t inLen, + uint16_t *pubkeyIndex, + size_t *publicKeyLen, + uint16_t *prvkeyIndex, + size_t *privateKeyLen); + +sss_status_t sss_util_rfc8410_asn1_get_ec_pair_key_index(const uint8_t *input, + size_t inLen, + uint16_t *pubkeyIndex, + size_t *publicKeyLen, + uint16_t *prvkeyIndex, + size_t *privateKeyLen); + +int asn_1_parse_tlv(uint8_t *pbuf, size_t *taglen, size_t *bufindex); + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen); + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc_complete_modulus( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen); + +sss_status_t sss_util_openssl_read_pkcs12( + const char *pkcs12_cert, const char *password, uint8_t *private_key, uint8_t *cert); + +sss_status_t sss_util_openssl_write_pkcs12(const char *pkcs12_cert, + const char *password, + const char *ref_key, + long ref_key_length, + const char *cert, + long cert_length); + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h new file mode 100644 index 00000000000..c78fd34b092 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h @@ -0,0 +1,28 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FSL_SSS_UTIL_RSA_SIGN_H +#define FSL_SSS_UTIL_RSA_SIGN_H + +uint8_t pkcs1_v15_encode( + sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen); + +uint8_t pkcs1_v15_encode_no_hash( + sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen); + +uint8_t sss_mgf_mask_func(uint8_t *dst, + size_t dlen, + uint8_t *src, + size_t slen, + sss_algorithm_t sha_algorithm, + sss_se05x_asymmetric_t *context); + +uint8_t emsa_encode(sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen); + +uint8_t emsa_decode_and_compare( + sss_se05x_asymmetric_t *context, uint8_t *sig, size_t siglen, uint8_t *hash, size_t hashlen); + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c new file mode 100644 index 00000000000..9bcb1795f9c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c @@ -0,0 +1,417 @@ +/* + * + * Copyright 2017-2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * Implementation of key association between NXP Secure Element and mbedtls. + * + *****************************************************************************/ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDH_C) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS + +#include +#include +#include +#include + +#include "mbedtls/ecdh.h" +#include "mbedtls/version.h" + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if defined(FLOW_VERBOSE) && FLOW_VERBOSE == 1 +#include "sm_printf.h" +#include "sm_types.h" +#endif /* FLOW_VERBOSE */ + +extern int mbedtls_ecdh_gen_public_o(mbedtls_ecp_group *grp, + mbedtls_mpi *d, + mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +extern int mbedtls_ecdh_compute_shared_o(mbedtls_ecp_group *grp, + mbedtls_mpi *z, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +extern int mbedtls_ecdh_get_params_o(mbedtls_ecdh_context *ctx, const mbedtls_ecp_keypair *key, mbedtls_ecdh_side side); + +int get_header_and_bit_Length(int groupid, int *headerLen, int *bitLen) +{ + switch (groupid) { + case MBEDTLS_ECP_DP_SECP192R1: + if (headerLen != NULL) + *headerLen = der_ecc_nistp192_header_len; + if (bitLen != NULL) + *bitLen = 192; + break; + case MBEDTLS_ECP_DP_SECP224R1: + if (headerLen != NULL) + *headerLen = der_ecc_nistp224_header_len; + if (bitLen != NULL) + *bitLen = 224; + break; + case MBEDTLS_ECP_DP_SECP256R1: + if (headerLen != NULL) + *headerLen = der_ecc_nistp256_header_len; + if (bitLen != NULL) + *bitLen = 256; + break; + case MBEDTLS_ECP_DP_SECP384R1: + if (headerLen != NULL) + *headerLen = der_ecc_nistp384_header_len; + if (bitLen != NULL) + *bitLen = 384; + break; + case MBEDTLS_ECP_DP_SECP521R1: + if (headerLen != NULL) + *headerLen = der_ecc_nistp521_header_len; + if (bitLen != NULL) + *bitLen = 521; + break; + case MBEDTLS_ECP_DP_BP256R1: + if (headerLen != NULL) + *headerLen = der_ecc_bp256_header_len; + if (bitLen != NULL) + *bitLen = 256; + break; + case MBEDTLS_ECP_DP_BP384R1: + if (headerLen != NULL) + *headerLen = der_ecc_bp384_header_len; + if (bitLen != NULL) + *bitLen = 384; + break; + case MBEDTLS_ECP_DP_BP512R1: + if (headerLen != NULL) + *headerLen = der_ecc_bp512_header_len; + if (bitLen != NULL) + *bitLen = 512; + break; + case MBEDTLS_ECP_DP_SECP192K1: + if (headerLen != NULL) + *headerLen = der_ecc_192k_header_len; + if (bitLen != NULL) + *bitLen = 192; + break; + case MBEDTLS_ECP_DP_SECP224K1: + if (headerLen != NULL) + *headerLen = der_ecc_224k_header_len; + if (bitLen != NULL) + *bitLen = 224; + break; + case MBEDTLS_ECP_DP_SECP256K1: + if (headerLen != NULL) + *headerLen = der_ecc_256k_header_len; + if (bitLen != NULL) + *bitLen = 256; + break; + case MBEDTLS_ECP_DP_CURVE25519: + if (headerLen != NULL) + *headerLen = 0; + if (bitLen != NULL) + *bitLen = 256; + break; + case MBEDTLS_ECP_DP_CURVE448: + if (headerLen != NULL) + *headerLen = 0; + if (bitLen != NULL) + *bitLen = 448; + break; + default: + LOG_E("get_header_and_bit_Length: Group id not supported"); + return 1; + } + + return 0; +} + +/* + * Generate public key: simple wrapper around mbedtls_ecp_gen_keypair + */ +int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, + mbedtls_mpi *d, + mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + sss_status_t status = kStatus_SSS_Fail; + uint8_t publickey[256] = { + 0, + }; + int headerLen = 0; + size_t publickeylen = sizeof(publickey); + size_t publickeyBitLen = publickeylen * 8; + + if (grp->pSSSObject == NULL) { + return mbedtls_ecdh_gen_public_o(grp, d, Q, f_rng, p_rng); + } + else if (grp->pSSSObject->objectType == kSSS_KeyPart_Pair && + (grp->pSSSObject->cipherType == kSSS_CipherType_EC_NIST_P || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_NIST_K || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_MONTGOMERY || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_TWISTED_ED)) { + if (get_header_and_bit_Length(grp->id, &headerLen, NULL)) { + return 1; + } + + mbedtls_mpi_free(d); + status = sss_key_store_get_key( + grp->pSSSObject->keyStore, grp->pSSSObject, publickey, &publickeylen, &publickeyBitLen); + if (kStatus_SSS_Success == status) { + publickeylen -= headerLen; + return mbedtls_ecp_point_read_binary(grp, Q, &publickey[headerLen], publickeylen); + } + else { + return 1; + } + } + return 1; +} + +/* + * Compute shared secret (SEC1 3.3.1) + */ +int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, + mbedtls_mpi *z, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + int ret = 1; + sss_key_part_t keyType = kSSS_KeyPart_NONE; + sss_cipher_type_t cipherType = kSSS_CipherType_NONE; + int headerLen = 0; + uint8_t OtherPublicKey[256]; + size_t OtherPublickeylen = sizeof(OtherPublicKey); + int keyBitLen = 0; + sss_status_t status; + sss_object_t otherPartyKeyObject; + sss_object_t derivedKeyObject; + sss_derive_key_t context; + uint8_t SharedSecret[128]; + uint16_t SharedSecretlen = sizeof(SharedSecret); + uint8_t buf[256]; + size_t bitLen = 500; + size_t bufByteLen = sizeof(buf); + sss_cipher_type_t OtherPublickeycipherType = kSSS_CipherType_NONE; + + if (get_header_and_bit_Length(grp->id, &headerLen, &keyBitLen)) { + return 1; + } + + if (grp->pSSSObject == NULL) { + ret = mbedtls_ecdh_compute_shared_o(grp, z, Q, d, f_rng, p_rng); + } + else if (grp->pSSSObject->cipherType == kSSS_CipherType_EC_NIST_P || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_NIST_K || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + grp->pSSSObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + if (0 == mbedtls_ecp_point_write_binary(grp, + Q, + MBEDTLS_ECP_PF_UNCOMPRESSED, + &OtherPublickeylen, + (OtherPublicKey + headerLen), + sizeof(OtherPublicKey))) { + switch (grp->id) { + case MBEDTLS_ECP_DP_SECP192R1: + memcpy(OtherPublicKey, gecc_der_header_nist192, der_ecc_nistp192_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_nistp192_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_P; + break; + case MBEDTLS_ECP_DP_SECP224R1: + memcpy(OtherPublicKey, gecc_der_header_nist224, der_ecc_nistp224_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_nistp224_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_P; + break; + case MBEDTLS_ECP_DP_SECP256R1: + memcpy(OtherPublicKey, gecc_der_header_nist256, der_ecc_nistp256_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_nistp256_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_P; + break; + case MBEDTLS_ECP_DP_SECP384R1: + memcpy(OtherPublicKey, gecc_der_header_nist384, der_ecc_nistp384_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_nistp384_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_P; + break; + case MBEDTLS_ECP_DP_SECP521R1: + memcpy(OtherPublicKey, gecc_der_header_nist521, der_ecc_nistp521_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_nistp521_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_P; + break; + case MBEDTLS_ECP_DP_BP256R1: + memcpy(OtherPublicKey, gecc_der_header_bp256, der_ecc_bp256_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_bp256_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_BRAINPOOL; + break; + case MBEDTLS_ECP_DP_BP384R1: + memcpy(OtherPublicKey, gecc_der_header_bp384, der_ecc_bp384_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_bp384_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_BRAINPOOL; + break; + case MBEDTLS_ECP_DP_BP512R1: + memcpy(OtherPublicKey, gecc_der_header_bp512, der_ecc_bp512_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_bp512_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_BRAINPOOL; + break; + case MBEDTLS_ECP_DP_SECP192K1: + memcpy(OtherPublicKey, gecc_der_header_192k, der_ecc_192k_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_192k_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_K; + break; + case MBEDTLS_ECP_DP_SECP224K1: + memcpy(OtherPublicKey, gecc_der_header_224k, der_ecc_224k_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_224k_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_K; + break; + case MBEDTLS_ECP_DP_SECP256K1: + memcpy(OtherPublicKey, gecc_der_header_256k, der_ecc_256k_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_256k_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_NIST_K; + break; + case MBEDTLS_ECP_DP_CURVE25519: + memcpy(OtherPublicKey, gecc_der_header_mont_dh_25519, der_ecc_mont_dh_25519_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_mont_dh_25519_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_MONTGOMERY; + break; + case MBEDTLS_ECP_DP_CURVE448: + memcpy(OtherPublicKey, gecc_der_header_mont_dh_448, der_ecc_mont_dh_448_header_len); + OtherPublickeylen = OtherPublickeylen + der_ecc_mont_dh_448_header_len; + OtherPublickeycipherType = kSSS_CipherType_EC_MONTGOMERY; + break; + default: + return 1; + } + + do { + //For The derived shared secret init and allocate + status = sss_key_object_init(&derivedKeyObject, grp->hostKs); + if (status != kStatus_SSS_Success) { + printf( + " sss_key_object_init for derivedKeyObject " + "Failed...\n"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + + keyType = kSSS_KeyPart_Default; + cipherType = kSSS_CipherType_AES; + + status = sss_key_object_allocate_handle( + &derivedKeyObject, (__LINE__), keyType, cipherType, SharedSecretlen, kKeyObject_Mode_Transient); + if (status != kStatus_SSS_Success) { + LOG_E( + " sss_key_object_allocate_handle for derivedKeyObject " + "Failed"); + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + break; + } + + // SSCP Transient Object for the othe party public key init and allocate + status = sss_key_object_init(&otherPartyKeyObject, grp->hostKs); + if (status != kStatus_SSS_Success) { + LOG_E( + " sss_key_object_init for otherPartyKeyObject " + "Failed"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + + status = sss_key_object_allocate_handle(&otherPartyKeyObject, + (__LINE__), + kSSS_KeyPart_Public, + OtherPublickeycipherType, + (sizeof(OtherPublicKey)), + kKeyObject_Mode_Transient); + if (status != kStatus_SSS_Success) { + LOG_E( + " sss_key_object_allocate_handle for " + "otherPartyKeyObject Failed"); + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + break; + } + + //setting the other party public key + status = sss_key_store_set_key( + grp->hostKs, &otherPartyKeyObject, OtherPublicKey, OtherPublickeylen, keyBitLen, NULL, 0); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_key_store_set_key for keyPair Failed"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + + status = sss_derive_key_context_init(&context, + grp->pSSSObject->keyStore->session, + grp->pSSSObject, + kAlgorithm_SSS_ECDH, + kMode_SSS_ComputeSharedSecret); + if (status != kStatus_SSS_Success) { + printf(" sss_derive_key_context_init Failed...\n"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + + status = sss_derive_key_dh(&context, &otherPartyKeyObject, &derivedKeyObject); + if (status != kStatus_SSS_Success) { + printf(" sss_derive_key_dh Failed...\n"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + + status = sss_key_store_get_key(grp->hostKs, &derivedKeyObject, buf, &bufByteLen, &bitLen); + if (status != kStatus_SSS_Success) { + printf(" sss_key_store_get_key Failed...\n"); + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + break; + } + ret = mbedtls_mpi_read_binary(z, buf, bufByteLen); + } while (0); + sss_key_object_free(&otherPartyKeyObject); + sss_key_object_free(&derivedKeyObject); + } + } + else { + ret = 1; //Failed + } + return (ret); +} + +/* + * Get parameters from a keypair + */ +int mbedtls_ecdh_get_params(mbedtls_ecdh_context *ctx, const mbedtls_ecp_keypair *key, mbedtls_ecdh_side side) +{ + int ret; + sss_object_t *backup_type_SSS_Object = ctx->grp.pSSSObject; + sss_key_store_t *backup_type_hostKs = ctx->grp.hostKs; + ret = mbedtls_ecdh_get_params_o(ctx, key, side); + ctx->grp.pSSSObject = backup_type_SSS_Object; + ctx->grp.hostKs = backup_type_hostKs; + return (ret); +} + +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) +typedef mbedtls_ecdh_context mbedtls_ecdh_context_mbed; + +int ecdh_get_params_internal(mbedtls_ecdh_context_mbed *ctx, const mbedtls_ecp_keypair *key, mbedtls_ecdh_side side) +{ + return mbedtls_ecdh_get_params(ctx, key, side); +} + +#endif + +#endif /* defined(MBEDTLS_ECDH_C) && defined(MBEDTLS_ECDH_ALT) */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c new file mode 100644 index 00000000000..e0653b97ba8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c @@ -0,0 +1,632 @@ +/* + * Elliptic curve DSA + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDSA_C) + +#include +#include "fsl_sss_util_asn1_der.h" + +#include "mbedtls/ecdsa.h" +#include "mbedtls/asn1write.h" + +#include + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#include "mbedtls/hmac_drbg.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +/* Parameter validation macros based on platform_util.h */ +#define ECDSA_VALIDATE_RET(cond) MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) +#define ECDSA_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE(cond) + +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) + +/* Used for SSS object init */ +static sss_key_store_t *ecdsa_verify_ssskeystore = NULL; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/* +* Sub-context for ecdsa_verify() +*/ +struct mbedtls_ecdsa_restart_ver +{ + mbedtls_mpi u1, u2; /* intermediate values */ + enum + { /* what to do next? */ + ecdsa_ver_init = 0, /* getting started */ + ecdsa_ver_muladd, /* muladd step */ + } state; +}; + +/* +* Init verify restart sub-context +*/ +static void ecdsa_restart_ver_init(mbedtls_ecdsa_restart_ver_ctx *ctx) +{ + mbedtls_mpi_init(&ctx->u1); + mbedtls_mpi_init(&ctx->u2); + ctx->state = ecdsa_ver_init; +} + +/* +* Free the components of a verify restart sub-context +*/ +static void ecdsa_restart_ver_free(mbedtls_ecdsa_restart_ver_ctx *ctx) +{ + if (ctx == NULL) + return; + + mbedtls_mpi_free(&ctx->u1); + mbedtls_mpi_free(&ctx->u2); + + ecdsa_restart_ver_init(ctx); +} + +/* +* Sub-context for ecdsa_sign() +*/ +struct mbedtls_ecdsa_restart_sig +{ + int sign_tries; + int key_tries; + mbedtls_mpi k; /* per-signature random */ + mbedtls_mpi r; /* r value */ + enum + { /* what to do next? */ + ecdsa_sig_init = 0, /* getting started */ + ecdsa_sig_mul, /* doing ecp_mul() */ + ecdsa_sig_modn, /* mod N computations */ + } state; +}; + +/* +* Init verify sign sub-context +*/ +static void ecdsa_restart_sig_init(mbedtls_ecdsa_restart_sig_ctx *ctx) +{ + ctx->sign_tries = 0; + ctx->key_tries = 0; + mbedtls_mpi_init(&ctx->k); + mbedtls_mpi_init(&ctx->r); + ctx->state = ecdsa_sig_init; +} + +/* +* Free the components of a sign restart sub-context +*/ +static void ecdsa_restart_sig_free(mbedtls_ecdsa_restart_sig_ctx *ctx) +{ + if (ctx == NULL) + return; + + mbedtls_mpi_free(&ctx->k); + mbedtls_mpi_free(&ctx->r); +} + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/* +* Sub-context for ecdsa_sign_det() +*/ +struct mbedtls_ecdsa_restart_det +{ + mbedtls_hmac_drbg_context rng_ctx; /* DRBG state */ + enum + { /* what to do next? */ + ecdsa_det_init = 0, /* getting started */ + ecdsa_det_sign, /* make signature */ + } state; +}; + +/* +* Init verify sign_det sub-context +*/ +static void ecdsa_restart_det_init(mbedtls_ecdsa_restart_det_ctx *ctx) +{ + mbedtls_hmac_drbg_init(&ctx->rng_ctx); + ctx->state = ecdsa_det_init; +} + +/* +* Free the components of a sign_det restart sub-context +*/ +static void ecdsa_restart_det_free(mbedtls_ecdsa_restart_det_ctx *ctx) +{ + if (ctx == NULL) + return; + + mbedtls_hmac_drbg_free(&ctx->rng_ctx); + + ecdsa_restart_det_init(ctx); +} +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#define ECDSA_RS_ECP &rs_ctx->ecp + +/* Utility macro for checking and updating ops budget */ +#define ECDSA_BUDGET(ops) MBEDTLS_MPI_CHK(mbedtls_ecp_check_budget(grp, &rs_ctx->ecp, ops)); + +/* Call this when entering a function that needs its own sub-context */ +#define ECDSA_RS_ENTER(SUB) \ + do { \ + /* reset ops count for this call if top-level */ \ + if (rs_ctx != NULL && rs_ctx->ecp.depth++ == 0) \ + rs_ctx->ecp.ops_done = 0; \ + \ + /* set up our own sub-context if needed */ \ + if (mbedtls_ecp_restart_is_enabled() && rs_ctx != NULL && rs_ctx->SUB == NULL) { \ + rs_ctx->SUB = mbedtls_calloc(1, sizeof(*rs_ctx->SUB)); \ + if (rs_ctx->SUB == NULL) \ + return (MBEDTLS_ERR_ECP_ALLOC_FAILED); \ + \ + ecdsa_restart_##SUB##_init(rs_ctx->SUB); \ + } \ + } while (0) + +/* Call this when leaving a function that needs its own sub-context */ +#define ECDSA_RS_LEAVE(SUB) \ + do { \ + /* clear our sub-context when not in progress (done or error) */ \ + if (rs_ctx != NULL && rs_ctx->SUB != NULL && ret != MBEDTLS_ERR_ECP_IN_PROGRESS) { \ + ecdsa_restart_##SUB##_free(rs_ctx->SUB); \ + mbedtls_free(rs_ctx->SUB); \ + rs_ctx->SUB = NULL; \ + } \ + \ + if (rs_ctx != NULL) \ + rs_ctx->ecp.depth--; \ + } while (0) + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define ECDSA_RS_ECP NULL + +#define ECDSA_BUDGET(ops) /* no-op; for compatibility */ + +#define ECDSA_RS_ENTER(SUB) (void)rs_ctx +#define ECDSA_RS_LEAVE(SUB) (void)rs_ctx + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/* +* Derive a suitable integer for group grp from a buffer of length len +* SEC1 4.1.3 step 5 aka SEC1 4.1.4 step 3 +*/ +static int derive_mpi(const mbedtls_ecp_group *grp, mbedtls_mpi *x, const unsigned char *buf, size_t blen) +{ + int ret; + size_t n_size = (grp->nbits + 7) / 8; + size_t use_size = blen > n_size ? n_size : blen; + + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(x, buf, use_size)); + if (use_size * 8 > grp->nbits) + MBEDTLS_MPI_CHK(mbedtls_mpi_shift_r(x, use_size * 8 - grp->nbits)); + + /* While at it, reduce modulo N */ + if (mbedtls_mpi_cmp_mpi(x, &grp->N) >= 0) + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_mpi(x, x, &grp->N)); + +cleanup: + return (ret); +} + +/* +* For software rollback +*/ +/* +* Verify ECDSA signature of hashed message (SEC1 4.1.4) +* Obviously, compared to SEC1 4.1.3, we skip step 2 (hash message) +*/ +static int ecdsa_verify_restartable_o(mbedtls_ecp_group *grp, + const unsigned char *buf, + size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, + const mbedtls_mpi *s, + mbedtls_ecdsa_restart_ctx *rs_ctx) +{ + int ret; + mbedtls_mpi e, s_inv, u1, u2; + mbedtls_ecp_point R; + mbedtls_mpi *pu1 = &u1, *pu2 = &u2; + + mbedtls_ecp_point_init(&R); + mbedtls_mpi_init(&e); + mbedtls_mpi_init(&s_inv); + mbedtls_mpi_init(&u1); + mbedtls_mpi_init(&u2); + + /* Fail cleanly on curves such as Curve25519 that can't be used for ECDSA */ + if (grp->N.p == NULL) + return (MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + + ECDSA_RS_ENTER(ver); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if (rs_ctx != NULL && rs_ctx->ver != NULL) { + /* redirect to our context */ + pu1 = &rs_ctx->ver->u1; + pu2 = &rs_ctx->ver->u2; + + /* jump to current step */ + if (rs_ctx->ver->state == ecdsa_ver_muladd) + goto muladd; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + /* + * Step 1: make sure r and s are in range 1..n-1 + */ + if (mbedtls_mpi_cmp_int(r, 1) < 0 || mbedtls_mpi_cmp_mpi(r, &grp->N) >= 0 || mbedtls_mpi_cmp_int(s, 1) < 0 || + mbedtls_mpi_cmp_mpi(s, &grp->N) >= 0) { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + + /* + * Step 3: derive MPI from hashed message + */ + MBEDTLS_MPI_CHK(derive_mpi(grp, &e, buf, blen)); + + /* + * Step 4: u1 = e / s mod n, u2 = r / s mod n + */ + ECDSA_BUDGET(MBEDTLS_ECP_OPS_CHK + MBEDTLS_ECP_OPS_INV + 2); + + MBEDTLS_MPI_CHK(mbedtls_mpi_inv_mod(&s_inv, s, &grp->N)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(pu1, &e, &s_inv)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(pu1, pu1, &grp->N)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(pu2, r, &s_inv)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(pu2, pu2, &grp->N)); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if (rs_ctx != NULL && rs_ctx->ver != NULL) + rs_ctx->ver->state = ecdsa_ver_muladd; + +muladd: +#endif + /* + * Step 5: R = u1 G + u2 Q + */ + MBEDTLS_MPI_CHK(mbedtls_ecp_muladd_restartable(grp, &R, pu1, &grp->G, pu2, Q, ECDSA_RS_ECP)); + + if (mbedtls_ecp_is_zero(&R)) { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + + /* + * Step 6: convert xR to an integer (no-op) + * Step 7: reduce xR mod n (gives v) + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&R.X, &R.X, &grp->N)); + + /* + * Step 8: check if v (that is, R.X) is equal to r + */ + if (mbedtls_mpi_cmp_mpi(&R.X, r) != 0) { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free(&R); + mbedtls_mpi_free(&e); + mbedtls_mpi_free(&s_inv); + mbedtls_mpi_free(&u1); + mbedtls_mpi_free(&u2); + + ECDSA_RS_LEAVE(ver); + + return (ret); +} + +/* +* Verify ECDSA signature of hashed message +*/ +int mbedtls_ecdsa_verify_o(mbedtls_ecp_group *grp, + const unsigned char *buf, + size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, + const mbedtls_mpi *s) +{ + ECDSA_VALIDATE_RET(grp != NULL); + ECDSA_VALIDATE_RET(Q != NULL); + ECDSA_VALIDATE_RET(r != NULL); + ECDSA_VALIDATE_RET(s != NULL); + ECDSA_VALIDATE_RET(buf != NULL || blen == 0); + + return (ecdsa_verify_restartable_o(grp, buf, blen, Q, r, s, NULL)); +} + +void sss_mbedtls_set_sss_keystore(sss_key_store_t *ssskeystore) +{ + ecdsa_verify_ssskeystore = ssskeystore; +} + +/* + * Verify ECDSA signature of hashed message + */ +int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, + const unsigned char *buf, + size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, + const mbedtls_mpi *s) +{ + int ret = 1; + ECDSA_VALIDATE_RET(grp != NULL); + ECDSA_VALIDATE_RET(Q != NULL); + ECDSA_VALIDATE_RET(r != NULL); + ECDSA_VALIDATE_RET(s != NULL); + ECDSA_VALIDATE_RET(buf != NULL || blen == 0); + + if (ecdsa_verify_ssskeystore != NULL) { + sss_cipher_type_t cipherType = kSSS_CipherType_NONE; + sss_object_t sssKeyObject = { + 0, + }; + sss_status_t status; + size_t keyBitLen = 0; + uint8_t publickey[170] = { + 0, + }; + size_t publickeylen = 0; + size_t rawPublickeylen = 0; + unsigned char signature[150] = { + 0, + }; + size_t sigLen = 0; + unsigned char rs_buf[80] = { + 0, + }; + size_t rs_buf_len = 0; + sss_algorithm_t algorithm; + sss_asymmetric_t asymVerifyCtx; + + /* + * Create the signature + * Signature = { + * 0x30, Remaining Length, Tag, R_length, R, Tag, S_length, S } + */ + + /* Set totoal length */ + signature[sigLen++] = 0x30; + signature[sigLen++] = (unsigned char)(4 + mbedtls_mpi_size(r) + mbedtls_mpi_size(s)); + /* 4 ==> Tag + Lengthn + Tag + Length */ + + /* Set R */ + rs_buf_len = mbedtls_mpi_size(r); + ret = mbedtls_mpi_write_binary(r, rs_buf, rs_buf_len); + if (ret != 0) { + return ret; + } + + signature[sigLen++] = 0x02; + if ((rs_buf[0] & 0x80)) { + signature[sigLen++] = (unsigned char)(rs_buf_len + 1); + signature[sigLen++] = 0x00; + /* Increment total length */ + signature[1] += 1; + } + else { + signature[sigLen++] = (unsigned char)rs_buf_len; + } + + if ((sizeof(signature) - sigLen) < rs_buf_len) { + return -1; + } + memcpy(&signature[sigLen], rs_buf, rs_buf_len); + sigLen += rs_buf_len; + + /* Set S */ + rs_buf_len = mbedtls_mpi_size(s); + ret = mbedtls_mpi_write_binary(s, rs_buf, rs_buf_len); + if (ret != 0) { + return ret; + } + + signature[sigLen++] = 0x02; + if ((rs_buf[0] & 0x80)) { + signature[sigLen++] = (unsigned char)(rs_buf_len + 1); + signature[sigLen++] = 0x00; + /* Increment total length */ + signature[1] += 1; + } + else { + signature[sigLen++] = (unsigned char)rs_buf_len; + } + + if ((sizeof(signature) - sigLen) < rs_buf_len) { + return -1; + } + memcpy(&signature[sigLen], rs_buf, rs_buf_len); + sigLen += rs_buf_len; + + switch (grp->id) { + case MBEDTLS_ECP_DP_SECP192R1: + memcpy(publickey, gecc_der_header_nist192, der_ecc_nistp192_header_len); + publickeylen = der_ecc_nistp192_header_len; + cipherType = kSSS_CipherType_EC_NIST_P; + keyBitLen = 192; + break; + case MBEDTLS_ECP_DP_SECP224R1: + memcpy(publickey, gecc_der_header_nist224, der_ecc_nistp224_header_len); + publickeylen = der_ecc_nistp224_header_len; + cipherType = kSSS_CipherType_EC_NIST_P; + keyBitLen = 224; + break; + case MBEDTLS_ECP_DP_SECP256R1: + memcpy(publickey, gecc_der_header_nist256, der_ecc_nistp256_header_len); + publickeylen = der_ecc_nistp256_header_len; + cipherType = kSSS_CipherType_EC_NIST_P; + keyBitLen = 256; + break; + case MBEDTLS_ECP_DP_SECP384R1: + memcpy(publickey, gecc_der_header_nist384, der_ecc_nistp384_header_len); + publickeylen = der_ecc_nistp384_header_len; + cipherType = kSSS_CipherType_EC_NIST_P; + keyBitLen = 384; + break; + case MBEDTLS_ECP_DP_SECP521R1: + memcpy(publickey, gecc_der_header_nist521, der_ecc_nistp521_header_len); + publickeylen = der_ecc_nistp521_header_len; + cipherType = kSSS_CipherType_EC_NIST_P; + keyBitLen = 521; + break; + case MBEDTLS_ECP_DP_BP256R1: + memcpy(publickey, gecc_der_header_bp256, der_ecc_bp256_header_len); + publickeylen = der_ecc_bp256_header_len; + cipherType = kSSS_CipherType_EC_BRAINPOOL; + keyBitLen = 256; + break; + case MBEDTLS_ECP_DP_BP384R1: + memcpy(publickey, gecc_der_header_bp384, der_ecc_bp384_header_len); + publickeylen = der_ecc_bp384_header_len; + cipherType = kSSS_CipherType_EC_BRAINPOOL; + keyBitLen = 384; + break; + case MBEDTLS_ECP_DP_BP512R1: + memcpy(publickey, gecc_der_header_bp512, der_ecc_bp512_header_len); + publickeylen = der_ecc_bp512_header_len; + cipherType = kSSS_CipherType_EC_BRAINPOOL; + keyBitLen = 512; + break; + case MBEDTLS_ECP_DP_SECP192K1: + memcpy(publickey, gecc_der_header_192k, der_ecc_192k_header_len); + publickeylen = der_ecc_192k_header_len; + cipherType = kSSS_CipherType_EC_NIST_K; + keyBitLen = 192; + break; + case MBEDTLS_ECP_DP_SECP224K1: + memcpy(publickey, gecc_der_header_224k, der_ecc_224k_header_len); + publickeylen = der_ecc_224k_header_len; + cipherType = kSSS_CipherType_EC_NIST_K; + keyBitLen = 224; + break; + case MBEDTLS_ECP_DP_SECP256K1: + memcpy(publickey, gecc_der_header_256k, der_ecc_256k_header_len); + publickeylen = der_ecc_256k_header_len; + cipherType = kSSS_CipherType_EC_NIST_K; + keyBitLen = 256; + break; + default: + /* Rollback to verification on host if SE is not initialised */ + return mbedtls_ecdsa_verify_o(grp, buf, blen, Q, r, s); + } + + ret = mbedtls_ecp_point_write_binary( + grp, Q, 0, &rawPublickeylen, &publickey[publickeylen], (sizeof(publickey) - publickeylen)); + if (ret != 0) { + return ret; + } + publickeylen += rawPublickeylen; + + status = sss_key_object_init(&sssKeyObject, ecdsa_verify_ssskeystore); + if (status != kStatus_SSS_Success) { + return 1; + } + + status = sss_key_object_allocate_handle( + &sssKeyObject, (__LINE__), kSSS_KeyPart_Public, cipherType, publickeylen, kKeyObject_Mode_Transient); + if (status != kStatus_SSS_Success) { + return 1; + } + + status = + sss_key_store_set_key(ecdsa_verify_ssskeystore, &sssKeyObject, publickey, publickeylen, keyBitLen, NULL, 0); + if (status != kStatus_SSS_Success) { + return 1; + } + + switch (blen) { + case 20: + algorithm = kAlgorithm_SSS_SHA1; + break; + case 28: + algorithm = kAlgorithm_SSS_SHA224; + break; + case 32: + algorithm = kAlgorithm_SSS_SHA256; + break; + case 48: + algorithm = kAlgorithm_SSS_SHA384; + break; + case 64: + algorithm = kAlgorithm_SSS_SHA512; + break; + default: + return 1; + } + + status = sss_asymmetric_context_init( + &asymVerifyCtx, ecdsa_verify_ssskeystore->session, &sssKeyObject, algorithm, kMode_SSS_Verify); + if (status != kStatus_SSS_Success) { + return 1; + } + + LOG_D("Verify using sss_asymmetric_verify_digest \n"); + status = sss_asymmetric_verify_digest(&asymVerifyCtx, (uint8_t *)buf, blen, (uint8_t *)signature, sigLen); + if (status != kStatus_SSS_Success) { + return 1; + } + + status = sss_key_store_erase_key(ecdsa_verify_ssskeystore, &sssKeyObject); + if (status != kStatus_SSS_Success) { + return 1; + } + + return 0; + } + else { + /* Rollback to verification on host if SE is not initialised */ + return mbedtls_ecdsa_verify_o(grp, buf, blen, Q, r, s); + } +} +#endif /* !MBEDTLS_ECDSA_VERIFY_ALT */ + +#endif /* MBEDTLS_ECDSA_C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h new file mode 100644 index 00000000000..69a324a2d0d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h @@ -0,0 +1,12 @@ +/* + * Copyright 2018-2020 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "fsl_sss_api.h" + +/* + * Set sss keystore for ecdsa verify + */ +void sss_mbedtls_set_sss_keystore(sss_key_store_t *ssskeystore); \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h new file mode 100644 index 00000000000..88dcf2349d8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h @@ -0,0 +1,191 @@ +/** + * \file ecp_alt.h + * + * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). + * + * The use of ECP in cryptography and TLS is defined in + * Standards for Efficient Cryptography Group (SECG): SEC1 + * Elliptic Curve Cryptography and + * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites + * for Transport Layer Security (TLS). + * + * RFC-2409: The Internet Key Exchange (IKE) defines ECP + * group types. + * + */ + +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +#ifndef SSS_ECP_ALT_H_INCLUDED +#define SSS_ECP_ALT_H_INCLUDED + +/* clang-format off */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ECP_ALT) + +#if SSS_HAVE_ALT_SSS +#include +#endif +#if SSS_HAVE_ALT_A71CH +#include "HLSETypes.h" +#endif + +/* + * default mbed TLS elliptic curve arithmetic implementation + * + * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an + * alternative implementation for the whole module and it will replace this + * one.) + */ + +/** + * \brief The ECP group structure. + * + * We consider two types of curve equations: + *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P + * (SEC1 + RFC-4492)
    • + *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, + * Curve448)
+ * In both cases, the generator (\p G) for a prime-order subgroup is fixed. + * + * For Short Weierstrass, this subgroup is the whole curve, and its + * cardinality is denoted by \p N. Our code requires that \p N is an + * odd prime as mbedtls_ecp_mul() requires an odd number, and + * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. + * + * For Montgomery curves, we do not store \p A, but (A + 2) / 4, + * which is the quantity used in the formulas. Additionally, \p nbits is + * not the size of \p N but the required size for private keys. + * + * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. + * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the + * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer + * which is congruent mod \p P to the given MPI, and is close enough to \p pbits + * in size, so that it may be efficiently brought in the 0..P-1 range by a few + * additions or subtractions. Therefore, it is only an approximative modular + * reduction. It must return 0 on success and non-zero on failure. + * + */ +typedef struct +{ + mbedtls_ecp_group_id id; /*!< An internal group identifier. */ + mbedtls_mpi P; /*!< The prime modulus of the base field. */ + mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. For + Montgomery curves: (A + 2) / 4. */ + mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. + For Montgomery curves: unused. */ + mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ + mbedtls_mpi N; /*!< The order of \p G. */ + size_t pbits; /*!< The number of bits in \p P.*/ + size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. + For Montgomery curves: the number of bits in the + private keys. */ + unsigned int h; /*!< \internal 1 if the constants are static. */ + int (*modp)(mbedtls_mpi *); /*!< The function for fast pseudo-reduction + mod \p P (see above).*/ + int (*t_pre)(mbedtls_ecp_point *, void *); /*!< Unused. */ + int (*t_post)(mbedtls_ecp_point *, void *); /*!< Unused. */ + void *t_data; /*!< Unused. */ + mbedtls_ecp_point *T; /*!< Pre-computed points for ecp_mul_comb(). */ + size_t T_size; /*!< The number of pre-computed points. */ + +#if SSS_HAVE_ALT_A71CH + /** Reference to object mapped between HLSE Layer of A71CH Host library */ + HLSE_OBJECT_HANDLE hlse_handle; +#endif +#if SSS_HAVE_ALT_SSS + /** Reference to object mapped between SSS Layer */ + sss_object_t* pSSSObject; + sss_key_store_t* hostKs; +#endif +} +mbedtls_ecp_group; + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h, or define them using the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ECP_MAX_BITS) +/** + * The maximum size of the groups, that is, of \c N and \c P. + */ +#define MBEDTLS_ECP_MAX_BITS 521 /**< The maximum size of groups, in bits. */ +#endif + +#define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) +#define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) + +#if !defined(MBEDTLS_ECP_WINDOW_SIZE) +/* + * Maximum "window" size used for point multiplication. + * Default: 6. + * Minimum value: 2. Maximum value: 7. + * + * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + * points used for point multiplication. This value is directly tied to EC + * peak memory usage, so decreasing it by one should roughly cut memory usage + * by two (if large curves are in use). + * + * Reduction in size may reduce speed, but larger curves are impacted first. + * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): + * w-size: 6 5 4 3 2 + * 521 145 141 135 120 97 + * 384 214 209 198 177 146 + * 256 320 320 303 262 226 + * 224 475 475 453 398 342 + * 192 640 640 633 587 476 + */ +#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< The maximum window size used. */ +#endif /* MBEDTLS_ECP_WINDOW_SIZE */ + +#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) +/* + * Trade memory for speed on fixed-point multiplication. + * + * This speeds up repeated multiplication of the generator (that is, the + * multiplication in ECDSA signatures, and half of the multiplications in + * ECDSA verification and ECDHE) by a factor roughly 3 to 4. + * + * The cost is increasing EC peak memory usage by a factor roughly 2. + * + * Change this value to 0 to reduce peak memory usage. + */ +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ +#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ + +/* \} name SECTION: Module settings */ + +#endif /* MBEDTLS_ECP_ALT */ + +#ifdef __cplusplus +} +#endif + +/* clang-format on */ + +#endif /* SSS_ECP_ALT_H_INCLUDED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c new file mode 100644 index 00000000000..f8351b63fa4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c @@ -0,0 +1,3115 @@ +/* + * Elliptic curves over GF(p): generic functions + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone + * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf + * RFC 4492 for the related TLS structures and constants + * RFC 7748 for the Curve448 and Curve25519 curve definitions + * + * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +/** + * \brief Function level alternative implementation. + * + * The MBEDTLS_ECP_INTERNAL_ALT macro enables alternative implementations to + * replace certain functions in this module. The alternative implementations are + * typically hardware accelerators and need to activate the hardware before the + * computation starts and deactivate it after it finishes. The + * mbedtls_internal_ecp_init() and mbedtls_internal_ecp_free() functions serve + * this purpose. + * + * To preserve the correct functionality the following conditions must hold: + * + * - The alternative implementation must be activated by + * mbedtls_internal_ecp_init() before any of the replaceable functions is + * called. + * - mbedtls_internal_ecp_free() must \b only be called when the alternative + * implementation is activated. + * - mbedtls_internal_ecp_init() must \b not be called when the alternative + * implementation is activated. + * - Public functions must not return while the alternative implementation is + * activated. + * - Replaceable functions are guarded by \c MBEDTLS_ECP_XXX_ALT macros and + * before calling them an \code if( mbedtls_internal_ecp_grp_capable( grp ) ) + * \endcode ensures that the alternative implementation supports the current + * group. + */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) +#endif +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/threading.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_ECP_ALT) + +#if SSS_HAVE_ALT_SSS +# include "sss_mbedtls.h" +#else +//# include "ax_mbedtls.h" +#endif + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/ecp_internal.h" + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#if defined(MBEDTLS_SELF_TEST) +/* + * Counts of point addition and doubling, and field multiplications. + * Used to test resistance of point multiplication to simple timing attacks. + */ +static unsigned long add_count, dbl_count, mul_count; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Maximum number of "basic operations" to be done in a row. + * + * Default value 0 means that ECC operations will not yield. + * Note that regardless of the value of ecp_max_ops, always at + * least one step is performed before yielding. + * + * Setting ecp_max_ops=1 can be suitable for testing purposes + * as it will interrupt computation at all possible points. + */ +static unsigned ecp_max_ops = 0; + +/* + * Set ecp_max_ops + */ +void mbedtls_ecp_set_max_ops( unsigned max_ops ) +{ + ecp_max_ops = max_ops; +} + +/* + * Check if restart is enabled + */ +int mbedtls_ecp_restart_is_enabled( void ) +{ + return( ecp_max_ops != 0 ); +} + +/* + * Restart sub-context for ecp_mul_comb() + */ +struct mbedtls_ecp_restart_mul +{ + mbedtls_ecp_point R; /* current intermediate result */ + size_t i; /* current index in various loops, 0 outside */ + mbedtls_ecp_point *T; /* table for precomputed points */ + unsigned char T_size; /* number of points in table T */ + enum { /* what were we doing last time we returned? */ + ecp_rsm_init = 0, /* nothing so far, dummy initial state */ + ecp_rsm_pre_dbl, /* precompute 2^n multiples */ + ecp_rsm_pre_norm_dbl, /* normalize precomputed 2^n multiples */ + ecp_rsm_pre_add, /* precompute remaining points by adding */ + ecp_rsm_pre_norm_add, /* normalize all precomputed points */ + ecp_rsm_comb_core, /* ecp_mul_comb_core() */ + ecp_rsm_final_norm, /* do the final normalization */ + } state; +}; + +/* + * Init restart_mul sub-context + */ +static void ecp_restart_rsm_init( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->R ); + ctx->i = 0; + ctx->T = NULL; + ctx->T_size = 0; + ctx->state = ecp_rsm_init; +} + +/* + * Free the components of a restart_mul sub-context + */ +static void ecp_restart_rsm_free( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + unsigned char i; + + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->R ); + + if( ctx->T != NULL ) + { + for( i = 0; i < ctx->T_size; i++ ) + mbedtls_ecp_point_free( ctx->T + i ); + mbedtls_free( ctx->T ); + } + + ecp_restart_rsm_init( ctx ); +} + +/* + * Restart context for ecp_muladd() + */ +struct mbedtls_ecp_restart_muladd +{ + mbedtls_ecp_point mP; /* mP value */ + mbedtls_ecp_point R; /* R intermediate result */ + enum { /* what should we do next? */ + ecp_rsma_mul1 = 0, /* first multiplication */ + ecp_rsma_mul2, /* second multiplication */ + ecp_rsma_add, /* addition */ + ecp_rsma_norm, /* normalization */ + } state; +}; + +/* + * Init restart_muladd sub-context + */ +static void ecp_restart_ma_init( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->mP ); + mbedtls_ecp_point_init( &ctx->R ); + ctx->state = ecp_rsma_mul1; +} + +/* + * Free the components of a restart_muladd sub-context + */ +static void ecp_restart_ma_free( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->mP ); + mbedtls_ecp_point_free( &ctx->R ); + + ecp_restart_ma_init( ctx ); +} + +/* + * Initialize a restart context + */ +void mbedtls_ecp_restart_init( mbedtls_ecp_restart_ctx *ctx ) +{ + ECP_VALIDATE( ctx != NULL ); + ctx->ops_done = 0; + ctx->depth = 0; + ctx->rsm = NULL; + ctx->ma = NULL; +} + +/* + * Free the components of a restart context + */ +void mbedtls_ecp_restart_free( mbedtls_ecp_restart_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + ecp_restart_rsm_free( ctx->rsm ); + mbedtls_free( ctx->rsm ); + + ecp_restart_ma_free( ctx->ma ); + mbedtls_free( ctx->ma ); + + mbedtls_ecp_restart_init( ctx ); +} + +/* + * Check if we can do the next step + */ +int mbedtls_ecp_check_budget( const mbedtls_ecp_group *grp, + mbedtls_ecp_restart_ctx *rs_ctx, + unsigned ops ) +{ + ECP_VALIDATE_RET( grp != NULL ); + + if( rs_ctx != NULL && ecp_max_ops != 0 ) + { + /* scale depending on curve size: the chosen reference is 256-bit, + * and multiplication is quadratic. Round to the closest integer. */ + if( grp->pbits >= 512 ) + ops *= 4; + else if( grp->pbits >= 384 ) + ops *= 2; + + /* Avoid infinite loops: always allow first step. + * Because of that, however, it's not generally true + * that ops_done <= ecp_max_ops, so the check + * ops_done > ecp_max_ops below is mandatory. */ + if( ( rs_ctx->ops_done != 0 ) && + ( rs_ctx->ops_done > ecp_max_ops || + ops > ecp_max_ops - rs_ctx->ops_done ) ) + { + return( MBEDTLS_ERR_ECP_IN_PROGRESS ); + } + + /* update running count */ + rs_ctx->ops_done += ops; + } + + return( 0 ); +} + +/* Call this when entering a function that needs its own sub-context */ +#define ECP_RS_ENTER( SUB ) do { \ + /* reset ops count for this call if top-level */ \ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) \ + rs_ctx->ops_done = 0; \ + \ + /* set up our own sub-context if needed */ \ + if( mbedtls_ecp_restart_is_enabled() && \ + rs_ctx != NULL && rs_ctx->SUB == NULL ) \ + { \ + rs_ctx->SUB = mbedtls_calloc( 1, sizeof( *rs_ctx->SUB ) ); \ + if( rs_ctx->SUB == NULL ) \ + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); \ + \ + ecp_restart_## SUB ##_init( rs_ctx->SUB ); \ + } \ +} while( 0 ) + +/* Call this when leaving a function that needs its own sub-context */ +#define ECP_RS_LEAVE( SUB ) do { \ + /* clear our sub-context when not in progress (done or error) */ \ + if( rs_ctx != NULL && rs_ctx->SUB != NULL && \ + ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) \ + { \ + ecp_restart_## SUB ##_free( rs_ctx->SUB ); \ + mbedtls_free( rs_ctx->SUB ); \ + rs_ctx->SUB = NULL; \ + } \ + \ + if( rs_ctx != NULL ) \ + rs_ctx->depth--; \ +} while( 0 ) + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define ECP_RS_ENTER( sub ) (void) rs_ctx; +#define ECP_RS_LEAVE( sub ) (void) rs_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define ECP_SHORTWEIERSTRASS +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || \ + defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define ECP_MONTGOMERY +#endif + +/* + * Curve types: internal for now, might be exposed later + */ +typedef enum +{ + ECP_TYPE_NONE = 0, + ECP_TYPE_SHORT_WEIERSTRASS, /* y^2 = x^3 + a x + b */ + ECP_TYPE_MONTGOMERY, /* y^2 = x^3 + a x^2 + x */ +} ecp_curve_type; + +/* + * List of supported curves: + * - internal ID + * - TLS NamedCurve ID (RFC 4492 sec. 5.1.1, RFC 7071 sec. 2) + * - size in bits + * - readable name + * + * Curves are listed in order: largest curves first, and for a given size, + * fastest curves first. This provides the default order for the SSL module. + * + * Reminder: update profiles in x509_crt.c when adding a new curves! + */ +static const mbedtls_ecp_curve_info ecp_supported_curves[] = +{ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + { MBEDTLS_ECP_DP_SECP521R1, 25, 521, "secp521r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + { MBEDTLS_ECP_DP_BP512R1, 28, 512, "brainpoolP512r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + { MBEDTLS_ECP_DP_SECP384R1, 24, 384, "secp384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + { MBEDTLS_ECP_DP_BP384R1, 27, 384, "brainpoolP384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + { MBEDTLS_ECP_DP_SECP256R1, 23, 256, "secp256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + { MBEDTLS_ECP_DP_SECP256K1, 22, 256, "secp256k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + { MBEDTLS_ECP_DP_BP256R1, 26, 256, "brainpoolP256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + { MBEDTLS_ECP_DP_SECP224R1, 21, 224, "secp224r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + { MBEDTLS_ECP_DP_SECP224K1, 20, 224, "secp224k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + { MBEDTLS_ECP_DP_SECP192R1, 19, 192, "secp192r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + { MBEDTLS_ECP_DP_SECP192K1, 18, 192, "secp192k1" }, +#endif + { MBEDTLS_ECP_DP_NONE, 0, 0, NULL }, +}; + +#define ECP_NB_CURVES sizeof( ecp_supported_curves ) / \ + sizeof( ecp_supported_curves[0] ) + +static mbedtls_ecp_group_id ecp_supported_grp_id[ECP_NB_CURVES]; + +/* + * List of supported curves and associated info + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void ) +{ + return( ecp_supported_curves ); +} + +/* + * List of supported curves, group ID only + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void ) +{ + static int init_done = 0; + + if( ! init_done ) + { + size_t i = 0; + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + ecp_supported_grp_id[i++] = curve_info->grp_id; + } + ecp_supported_grp_id[i] = MBEDTLS_ECP_DP_NONE; + + init_done = 1; + } + + return( ecp_supported_grp_id ); +} + +/* + * Get the curve info for the internal identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->grp_id == grp_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the TLS identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->tls_id == tls_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the name + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name ) +{ + const mbedtls_ecp_curve_info *curve_info; + + if( name == NULL ) + return( NULL ); + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( strcmp( curve_info->name, name ) == 0 ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the type of a curve + */ +static inline ecp_curve_type ecp_get_type( const mbedtls_ecp_group *grp ) +{ + if( grp->G.X.p == NULL ) + return( ECP_TYPE_NONE ); + + if( grp->G.Y.p == NULL ) + return( ECP_TYPE_MONTGOMERY ); + else + return( ECP_TYPE_SHORT_WEIERSTRASS ); +} + +/* + * Initialize (the components of) a point + */ +void mbedtls_ecp_point_init( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE( pt != NULL ); + + mbedtls_mpi_init( &pt->X ); + mbedtls_mpi_init( &pt->Y ); + mbedtls_mpi_init( &pt->Z ); +} + +/* + * Initialize (the components of) a group + */ +void mbedtls_ecp_group_init( mbedtls_ecp_group *grp ) +{ + ECP_VALIDATE( grp != NULL ); + + grp->id = MBEDTLS_ECP_DP_NONE; + mbedtls_mpi_init( &grp->P ); + mbedtls_mpi_init( &grp->A ); + mbedtls_mpi_init( &grp->B ); + mbedtls_ecp_point_init( &grp->G ); + mbedtls_mpi_init( &grp->N ); + grp->pbits = 0; + grp->nbits = 0; + grp->h = 0; + grp->modp = NULL; + grp->t_pre = NULL; + grp->t_post = NULL; + grp->t_data = NULL; + grp->T = NULL; + grp->T_size = 0; +} + +/* + * Initialize (the components of) a key pair + */ +void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key ) +{ + ECP_VALIDATE( key != NULL ); + + mbedtls_ecp_group_init( &key->grp ); + mbedtls_mpi_init( &key->d ); + mbedtls_ecp_point_init( &key->Q ); +} + +/* + * Unallocate (the components of) a point + */ +void mbedtls_ecp_point_free( mbedtls_ecp_point *pt ) +{ + if( pt == NULL ) + return; + + mbedtls_mpi_free( &( pt->X ) ); + mbedtls_mpi_free( &( pt->Y ) ); + mbedtls_mpi_free( &( pt->Z ) ); +} + +/* + * Unallocate (the components of) a group + */ +void mbedtls_ecp_group_free( mbedtls_ecp_group *grp ) +{ + size_t i; + + if( grp == NULL ) + return; + + if( grp->h != 1 ) + { + mbedtls_mpi_free( &grp->P ); + mbedtls_mpi_free( &grp->A ); + mbedtls_mpi_free( &grp->B ); + mbedtls_ecp_point_free( &grp->G ); + mbedtls_mpi_free( &grp->N ); + } + + if( grp->T != NULL ) + { + for( i = 0; i < grp->T_size; i++ ) + mbedtls_ecp_point_free( &grp->T[i] ); + mbedtls_free( grp->T ); + } + + mbedtls_platform_zeroize( grp, sizeof( mbedtls_ecp_group ) ); +} + +/* + * Unallocate (the components of) a key pair + */ +void mbedtls_ecp_keypair_free_o( mbedtls_ecp_keypair *key ) +{ + if( key == NULL ) + return; + + mbedtls_ecp_group_free( &key->grp ); + mbedtls_mpi_free( &key->d ); + mbedtls_ecp_point_free( &key->Q ); +} + +/* + * Secure element hostlib handling + */ + +void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ) +{ + if( key == NULL ) + return; +#if SSS_HAVE_ALT_A71CH + if ( key->grp.hlse_handle != 0 ) + { + key->grp.hlse_handle = 0; + } +#endif + mbedtls_ecp_keypair_free_o(key); +} + +/* + * Copy the contents of a point + */ +int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->X, &Q->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Y, &Q->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Z, &Q->Z ) ); + +cleanup: + return( ret ); +} + +/* + * Copy the contents of a group object + */ +int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src ) +{ + ECP_VALIDATE_RET( dst != NULL ); + ECP_VALIDATE_RET( src != NULL ); + + return( mbedtls_ecp_group_load( dst, src->id ) ); +} + +/* + * Set point to zero + */ +int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ) +{ + int ret; + ECP_VALIDATE_RET( pt != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->X , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Y , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z , 0 ) ); + +cleanup: + return( ret ); +} + +/* + * Tell if a point is zero + */ +int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( pt != NULL ); + + return( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ); +} + +/* + * Compare two points lazily + */ +int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_mpi_cmp_mpi( &P->X, &Q->X ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Y, &Q->Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Z, &Q->Z ) == 0 ) + { + return( 0 ); + } + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Import a non-zero point from ASCII strings + */ +int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, + const char *x, const char *y ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( x != NULL ); + ECP_VALIDATE_RET( y != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->X, radix, x ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->Y, radix, y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Export a point into unsigned binary data (SEC1 2.3.3) + */ +int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen ) +{ + int ret = 0; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * Common case: P == 0 + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + { + if( buflen < 1 ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x00; + *olen = 1; + + return( 0 ); + } + + plen = mbedtls_mpi_size( &grp->P ); + + if( format == MBEDTLS_ECP_PF_UNCOMPRESSED ) + { + *olen = 2 * plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x04; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->Y, buf + 1 + plen, plen ) ); + } + else if( format == MBEDTLS_ECP_PF_COMPRESSED ) + { + *olen = plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x02 + mbedtls_mpi_get_bit( &P->Y, 0 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + } + +cleanup: + return( ret ); +} + +/* + * Import a point from unsigned binary data (SEC1 2.3.4) + */ +int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char *buf, size_t ilen ) +{ + int ret; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ilen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( buf[0] == 0x00 ) + { + if( ilen == 1 ) + return( mbedtls_ecp_set_zero( pt ) ); + else + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + plen = mbedtls_mpi_size( &grp->P ); + + if( buf[0] != 0x04 ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + if( ilen != 2 * plen + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->Y, buf + 1 + plen, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Import a point from a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t buf_len ) +{ + unsigned char data_len; + const unsigned char *buf_start; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We must have at least two bytes (1 for length, at least one for data) + */ + if( buf_len < 2 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + data_len = *(*buf)++; + if( data_len < 1 || data_len > buf_len - 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Save buffer start for read_binary and update buf + */ + buf_start = *buf; + *buf += data_len; + + return( mbedtls_ecp_point_read_binary( grp, pt, buf_start, data_len ) ); +} + +/* + * Export a point as a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * buffer length must be at least one, for our length byte + */ + if( blen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_point_write_binary( grp, pt, format, + olen, buf + 1, blen - 1) ) != 0 ) + return( ret ); + + /* + * write length to the first byte and update total length + */ + buf[0] = (unsigned char) *olen; + ++*olen; + + return( 0 ); +} + +/* + * Set a group from an ECParameters record (RFC 4492) + */ +int mbedtls_ecp_tls_read_group_o( mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, len ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_group_load( grp, grp_id ) ); +} + +/* + * Use modified handling for secure element hostlib + */ +#if SSS_HAVE_ALT_A71CH +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, const unsigned char **buf, size_t len ) +{ + int ret; + HLSE_OBJECT_HANDLE backup_type_ax_index; + backup_type_ax_index = grp->hlse_handle; + ret = mbedtls_ecp_tls_read_group_o(grp, buf, len); + grp->hlse_handle = backup_type_ax_index; + return ret; +} +#elif SSS_HAVE_ALT_SSS +int mbedtls_ecp_tls_read_group( + mbedtls_ecp_group *grp, const unsigned char **buf, size_t len) +{ + int ret; + sss_object_t *backup_type_SSS_Object = grp->pSSSObject; + sss_key_store_t *backup_type_hostKs = grp->hostKs; + ret = mbedtls_ecp_tls_read_group_o(grp, buf, len); + grp->pSSSObject = backup_type_SSS_Object; + grp->hostKs = backup_type_hostKs; + + return ret; +} +#else +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, const unsigned char **buf, size_t len ) +{ + int ret = mbedtls_ecp_tls_read_group_o(grp, buf, len); + return ret; +} +#endif + +/* + * Read a group id from an ECParameters record (RFC 4492) and convert it to + * mbedtls_ecp_group_id. + */ +int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp, + const unsigned char **buf, size_t len ) +{ + uint16_t tls_id; + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We expect at least three bytes (see below) + */ + if( len < 3 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * First byte is curve_type; only named_curve is handled + */ + if( *(*buf)++ != MBEDTLS_ECP_TLS_NAMED_CURVE ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Next two bytes are the namedcurve value + */ + tls_id = *(*buf)++; + tls_id <<= 8; + tls_id |= *(*buf)++; + + if( ( curve_info = mbedtls_ecp_curve_info_from_tls_id( tls_id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + *grp = curve_info->grp_id; + + return( 0 ); +} + +/* + * Write the ECParameters record corresponding to a group (RFC 4492) + */ +int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen, + unsigned char *buf, size_t blen ) +{ + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + + if( ( curve_info = mbedtls_ecp_curve_info_from_grp_id( grp->id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * We are going to write 3 bytes (see below) + */ + *olen = 3; + if( blen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + /* + * First byte is curve_type, always named_curve + */ + *buf++ = MBEDTLS_ECP_TLS_NAMED_CURVE; + + /* + * Next two bytes are the namedcurve value + */ + buf[0] = curve_info->tls_id >> 8; + buf[1] = curve_info->tls_id & 0xFF; + + return( 0 ); +} + +/* + * Wrapper around fast quasi-modp functions, with fall-back to mbedtls_mpi_mod_mpi. + * See the documentation of struct mbedtls_ecp_group. + * + * This function is in the critial loop for mbedtls_ecp_mul, so pay attention to perf. + */ +static int ecp_modp( mbedtls_mpi *N, const mbedtls_ecp_group *grp ) +{ + int ret; + + if( grp->modp == NULL ) + return( mbedtls_mpi_mod_mpi( N, N, &grp->P ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + if( ( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) || + mbedtls_mpi_bitlen( N ) > 2 * grp->pbits ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + MBEDTLS_MPI_CHK( grp->modp( N ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + while( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &grp->P ) ); + + while( mbedtls_mpi_cmp_mpi( N, &grp->P ) >= 0 ) + /* we known P, N and the result are positive */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, N, &grp->P ) ); + +cleanup: + return( ret ); +} + +/* + * Fast mod-p functions expect their argument to be in the 0..p^2 range. + * + * In order to guarantee that, we need to ensure that operands of + * mbedtls_mpi_mul_mpi are in the 0..p range. So, after each operation we will + * bring the result back to this range. + * + * The following macros are shortcuts for doing that. + */ + +/* + * Reduce a mbedtls_mpi mod p in-place, general case, to use after mbedtls_mpi_mul_mpi + */ +#if defined(MBEDTLS_SELF_TEST) +#define INC_MUL_COUNT mul_count++; +#else +#define INC_MUL_COUNT +#endif + +#define MOD_MUL( N ) \ + do \ + { \ + MBEDTLS_MPI_CHK( ecp_modp( &(N), grp ) ); \ + INC_MUL_COUNT \ + } while( 0 ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_sub_mpi + * N->s < 0 is a very fast test, which fails only if N is 0 + */ +#define MOD_SUB( N ) \ + while( (N).s < 0 && mbedtls_mpi_cmp_int( &(N), 0 ) != 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &(N), &(N), &grp->P ) ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_add_mpi and mbedtls_mpi_mul_int. + * We known P, N and the result are positive, so sub_abs is correct, and + * a bit faster. + */ +#define MOD_ADD( N ) \ + while( mbedtls_mpi_cmp_mpi( &(N), &grp->P ) >= 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &(N), &(N), &grp->P ) ) + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * For curves in short Weierstrass form, we do all the internal operations in + * Jacobian coordinates. + * + * For multiplication, we'll use a comb method with coutermeasueres against + * SPA, hence timing attacks. + */ + +/* + * Normalize jacobian coordinates so that Z == 0 || Z == 1 (GECC 3.2.1) + * Cost: 1N := 1I + 3M + 1S + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) || !defined(MBEDTLS_ECP_ADD_ALT) +static int ecp_normalize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi Zi, ZZi; + + if( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ) + return( 0 ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac( grp, pt ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_ALT */ + + mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * X = X / Z^2 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &Zi, &pt->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ZZi ) ); MOD_MUL( pt->X ); + + /* + * Y = Y / Z^3 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ZZi ) ); MOD_MUL( pt->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &Zi ) ); MOD_MUL( pt->Y ); + + /* + * Z = 1 + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + + mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT || !MBEDTLS_ECP_ADD_ALT */ + +/* + * Normalize jacobian coordinates of an array of (pointers to) points, + * using Montgomery's trick to perform only one inversion mod P. + * (See for example Cohen's "A Course in Computational Algebraic Number + * Theory", Algorithm 10.3.4.) + * + * Warning: fails (returning an error) if one of the points is zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * Cost: 1N(t) := 1I + (6t - 3)M + 1S + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t T_size ) +{ + int ret; + size_t i; + mbedtls_mpi *c, u, Zi, ZZi; + + if( T_size < 2 ) + return( ecp_normalize_jac( grp, *T ) ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac_many( grp, T, T_size ) ); +#endif + + if( ( c = mbedtls_calloc( T_size, sizeof( mbedtls_mpi ) ) ) == NULL ) + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); + + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_init( &c[i] ); + + mbedtls_mpi_init( &u ); mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * c[i] = Z_0 * ... * Z_i + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &c[0], &T[0]->Z ) ); + for( i = 1; i < T_size; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &c[i], &c[i-1], &T[i]->Z ) ); + MOD_MUL( c[i] ); + } + + /* + * u = 1 / (Z_0 * ... * Z_n) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &u, &c[T_size-1], &grp->P ) ); + + for( i = T_size - 1; ; i-- ) + { + /* + * Zi = 1 / Z_i mod p + * u = 1 / (Z_0 * ... * Z_i) mod P + */ + if( i == 0 ) { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Zi, &u ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Zi, &u, &c[i-1] ) ); MOD_MUL( Zi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &u, &u, &T[i]->Z ) ); MOD_MUL( u ); + } + + /* + * proceed as in normalize() + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->X, &T[i]->X, &ZZi ) ); MOD_MUL( T[i]->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &ZZi ) ); MOD_MUL( T[i]->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &Zi ) ); MOD_MUL( T[i]->Y ); + + /* + * Post-precessing: reclaim some memory by shrinking coordinates + * - not storing Z (always 1) + * - shrinking other coordinates, but still keeping the same number of + * limbs as P, as otherwise it will too likely be regrown too fast. + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) ); + mbedtls_mpi_free( &T[i]->Z ); + + if( i == 0 ) + break; + } + +cleanup: + + mbedtls_mpi_free( &u ); mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_free( &c[i] ); + mbedtls_free( c ); + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Conditional point inversion: Q -> -Q = (Q.X, -Q.Y, Q.Z) without leak. + * "inv" must be 0 (don't invert) or 1 (invert) or the result will be invalid + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_safe_invert_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *Q, + unsigned char inv ) +{ + int ret; + unsigned char nonzero; + mbedtls_mpi mQY; + + mbedtls_mpi_init( &mQY ); + + /* Use the fact that -Q.Y mod P = P - Q.Y unless Q.Y == 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mQY, &grp->P, &Q->Y ) ); + nonzero = mbedtls_mpi_cmp_int( &Q->Y, 0 ) != 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &Q->Y, &mQY, inv & nonzero ) ); + +cleanup: + mbedtls_mpi_free( &mQY ); + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Point doubling R = 2 P, Jacobian coordinates + * + * Based on http://www.hyperelliptic.org/EFD/g1p/auto-shortw-jacobian.html#doubling-dbl-1998-cmo-2 . + * + * We follow the variable naming fairly closely. The formula variations that trade a MUL for a SQR + * (plus a few ADDs) aren't useful as our bignum implementation doesn't distinguish squaring. + * + * Standard optimizations are applied when curve parameter A is one of { 0, -3 }. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) || !defined(MBEDTLS_ECP_ADD_ALT) +static int ecp_double_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P ) +{ + int ret; + mbedtls_mpi M, S, T, U; + +#if defined(MBEDTLS_SELF_TEST) + dbl_count++; +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_jac( grp, R, P ) ); +#endif /* MBEDTLS_ECP_DOUBLE_JAC_ALT */ + + mbedtls_mpi_init( &M ); mbedtls_mpi_init( &S ); mbedtls_mpi_init( &T ); mbedtls_mpi_init( &U ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + /* M = 3(X + Z^2)(X - Z^2) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &T, &P->X, &S ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U, &P->X, &S ) ); MOD_SUB( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &U ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + } + else + { + /* M = 3.X^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &P->X ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + + /* Optimize away for "koblitz" curves with A = 0 */ + if( mbedtls_mpi_cmp_int( &grp->A, 0 ) != 0 ) + { + /* M += A.Z^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &S, &S ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &grp->A ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &S ) ); MOD_ADD( M ); + } + } + + /* S = 4.X.Y^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &P->Y, &P->Y ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T, 1 ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &T ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &S, 1 ) ); MOD_ADD( S ); + + /* U = 8.Y^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &T, &T ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + /* T = M^2 - 2.S */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &M, &M ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + + /* S = M(S - T) - U */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &T ) ); MOD_SUB( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &S, &M ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &U ) ); MOD_SUB( S ); + + /* U = 2.Y.Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &P->Y, &P->Z ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &U ) ); + +cleanup: + mbedtls_mpi_free( &M ); mbedtls_mpi_free( &S ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &U ); + + return( ret ); +} +#endif + +/* + * Addition: R = P + Q, mixed affine-Jacobian coordinates (GECC 3.22) + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * Special cases: (1) P or Q is zero, (2) R is zero, (3) P == Q. + * None of these cases can happen as intermediate step in ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base point, the factor + * being less than its order, so none of them is zero; + * - Q is an odd multiple of the base point, P an even multiple, + * due to the choice of precomputed points in the modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as meaning 1. + * + * Cost: 1A := 8M + 3S + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) || !defined(MBEDTLS_ECP_ADD_ALT) +static int ecp_add_mixed( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + mbedtls_mpi T1, T2, T3, T4, X, Y, Z; + +#if defined(MBEDTLS_SELF_TEST) + add_count++; +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_add_mixed( grp, R, P, Q ) ); +#endif /* MBEDTLS_ECP_ADD_MIXED_ALT */ + + /* + * Trivial cases: P == 0 or Q == 0 (case 1) + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, Q ) ); + + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, P ) ); + + /* + * Make sure Q coordinates are normalized + */ + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); mbedtls_mpi_init( &T3 ); mbedtls_mpi_init( &T4 ); + mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &P->Z, &P->Z ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T1, &P->Z ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &T1, &Q->X ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T2, &Q->Y ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T1, &T1, &P->X ) ); MOD_SUB( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T2, &T2, &P->Y ) ); MOD_SUB( T2 ); + + /* Special cases (2) and (3) */ + if( mbedtls_mpi_cmp_int( &T1, 0 ) == 0 ) + { + if( mbedtls_mpi_cmp_int( &T2, 0 ) == 0 ) + { + ret = ecp_double_jac( grp, R, P ); + goto cleanup; + } + else + { + ret = mbedtls_ecp_set_zero( R ); + goto cleanup; + } + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Z, &P->Z, &T1 ) ); MOD_MUL( Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T1, &T1 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T3, &T1 ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &P->X ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T3, 2 ) ); MOD_ADD( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &X, &T2, &T2 ) ); MOD_MUL( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T1 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T4 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T3, &T3, &X ) ); MOD_SUB( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &T2 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T4, &P->Y ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &Y, &T3, &T4 ) ); MOD_SUB( Y ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &Z ) ); + +cleanup: + + mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); mbedtls_mpi_free( &T3 ); mbedtls_mpi_free( &T4 ); + mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_MUL_COMB_ALT */ + +/* + * Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_jac(). + * + * This countermeasure was first suggested in [2]. + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l, ll; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_jac( grp, pt, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); mbedtls_mpi_init( &ll ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Z, &pt->Z, &l ) ); MOD_MUL( pt->Z ); + + /* X = l^2 * X */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &l, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ll ) ); MOD_MUL( pt->X ); + + /* Y = l^3 * Y */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &ll, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ll ) ); MOD_MUL( pt->Y ); + +cleanup: + mbedtls_mpi_free( &l ); mbedtls_mpi_free( &ll ); + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Check and define parameters used by the comb method (see below for details) + */ +#if MBEDTLS_ECP_WINDOW_SIZE < 2 || MBEDTLS_ECP_WINDOW_SIZE > 7 +#error "MBEDTLS_ECP_WINDOW_SIZE out of bounds" +#endif + +/* d = ceil( n / w ) */ +#define COMB_MAX_D ( MBEDTLS_ECP_MAX_BITS + 1 ) / 2 + +/* number of precomputed points */ +#define COMB_MAX_PRE ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + +/* + * Compute the representation of m that will be used with our comb method. + * + * The basic comb method is described in GECC 3.44 for example. We use a + * modified version that provides resistance to SPA by avoiding zero + * digits in the representation as in [3]. We modify the method further by + * requiring that all K_i be odd, which has the small cost that our + * representation uses one more K_i, due to carries, but saves on the size of + * the precomputed table. + * + * Summary of the comb method and its modifications: + * + * - The goal is to compute m*P for some w*d-bit integer m. + * + * - The basic comb method splits m into the w-bit integers + * x[0] .. x[d-1] where x[i] consists of the bits in m whose + * index has residue i modulo d, and computes m * P as + * S[x[0]] + 2 * S[x[1]] + .. + 2^(d-1) S[x[d-1]], where + * S[i_{w-1} .. i_0] := i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + i_0 P. + * + * - If it happens that, say, x[i+1]=0 (=> S[x[i+1]]=0), one can replace the sum by + * .. + 2^{i-1} S[x[i-1]] - 2^i S[x[i]] + 2^{i+1} S[x[i]] + 2^{i+2} S[x[i+2]] .., + * thereby successively converting it into a form where all summands + * are nonzero, at the cost of negative summands. This is the basic idea of [3]. + * + * - More generally, even if x[i+1] != 0, we can first transform the sum as + * .. - 2^i S[x[i]] + 2^{i+1} ( S[x[i]] + S[x[i+1]] ) + 2^{i+2} S[x[i+2]] .., + * and then replace S[x[i]] + S[x[i+1]] = S[x[i] ^ x[i+1]] + 2 S[x[i] & x[i+1]]. + * Performing and iterating this procedure for those x[i] that are even + * (keeping track of carry), we can transform the original sum into one of the form + * S[x'[0]] +- 2 S[x'[1]] +- .. +- 2^{d-1} S[x'[d-1]] + 2^d S[x'[d]] + * with all x'[i] odd. It is therefore only necessary to know S at odd indices, + * which is why we are only computing half of it in the first place in + * ecp_precompute_comb and accessing it with index abs(i) / 2 in ecp_select_comb. + * + * - For the sake of compactness, only the seven low-order bits of x[i] + * are used to represent its absolute value (K_i in the paper), and the msb + * of x[i] encodes the sign (s_i in the paper): it is set if and only if + * if s_i == -1; + * + * Calling conventions: + * - x is an array of size d + 1 + * - w is the size, ie number of teeth, of the comb, and must be between + * 2 and 7 (in practice, between 2 and MBEDTLS_ECP_WINDOW_SIZE) + * - m is the MPI, expected to be odd and such that bitlength(m) <= w * d + * (the result will be incorrect if these assumptions are not satisfied) + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static void ecp_comb_recode_core( unsigned char x[], size_t d, + unsigned char w, const mbedtls_mpi *m ) +{ + size_t i, j; + unsigned char c, cc, adjust; + + memset( x, 0, d+1 ); + + /* First get the classical comb values (except for x_d = 0) */ + for( i = 0; i < d; i++ ) + for( j = 0; j < w; j++ ) + x[i] |= mbedtls_mpi_get_bit( m, i + d * j ) << j; + + /* Now make sure x_1 .. x_d are odd */ + c = 0; + for( i = 1; i <= d; i++ ) + { + /* Add carry and update it */ + cc = x[i] & c; + x[i] = x[i] ^ c; + c = cc; + + /* Adjust if needed, avoiding branches */ + adjust = 1 - ( x[i] & 0x01 ); + c |= x[i] & ( x[i-1] * adjust ); + x[i] = x[i] ^ ( x[i-1] * adjust ); + x[i-1] |= adjust << 7; + } +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Precompute points for the adapted comb method + * + * Assumption: T must be able to hold 2^{w - 1} elements. + * + * Operation: If i = i_{w-1} ... i_1 is the binary representation of i, + * sets T[i] = i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + P. + * + * Cost: d(w-1) D + (2^{w-1} - 1) A + 1 N(w-1) + 1 N(2^{w-1} - 1) + * + * Note: Even comb values (those where P would be omitted from the + * sum defining T[i] above) are not needed in our adaption + * the comb method. See ecp_comb_recode_core(). + * + * This function currently works in four steps: + * (1) [dbl] Computation of intermediate T[i] for 2-power values of i + * (2) [norm_dbl] Normalization of coordinates of these T[i] + * (3) [add] Computation of all T[i] + * (4) [norm_add] Normalization of all T[i] + * + * Step 1 can be interrupted but not the others; together with the final + * coordinate normalization they are the largest steps done at once, depending + * on the window size. Here are operation counts for P-256: + * + * step (2) (3) (4) + * w = 5 142 165 208 + * w = 4 136 77 160 + * w = 3 130 33 136 + * w = 2 124 11 124 + * + * So if ECC operations are blocking for too long even with a low max_ops + * value, it's useful to set MBEDTLS_ECP_WINDOW_SIZE to a lower value in order + * to minimize maximum blocking time. + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_precompute_comb( const mbedtls_ecp_group *grp, + mbedtls_ecp_point T[], const mbedtls_ecp_point *P, + unsigned char w, size_t d, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char i; + size_t j = 0; + const unsigned char T_size = 1U << ( w - 1 ); + mbedtls_ecp_point *cur, *TT[COMB_MAX_PRE - 1]; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + goto dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_dbl ) + goto norm_dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_add ) + goto add; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_add ) + goto norm_add; + } +#else + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + rs_ctx->rsm->state = ecp_rsm_pre_dbl; + + /* initial state for the loop */ + rs_ctx->rsm->i = 0; + } + +dbl: +#endif + /* + * Set T[0] = P and + * T[2^{l-1}] = 2^{dl} P for l = 1 .. w-1 (this is not the final value) + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &T[0], P ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + j = rs_ctx->rsm->i; + else +#endif + j = 0; + + for( ; j < d * ( w - 1 ); j++ ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL ); + + i = 1U << ( j / d ); + cur = T + i; + + if( j % d == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( cur, T + ( i >> 1 ) ) ); + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, cur, cur ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_dbl; + +norm_dbl: +#endif + /* + * Normalize current elements in T. As T has holes, + * use an auxiliary array of pointers to elements in T. + */ + j = 0; + for( i = 1; i < T_size; i <<= 1 ) + TT[j++] = T + i; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_add; + +add: +#endif + /* + * Compute the remaining ones using the minimal number of additions + * Be careful to update T[2^l] only after using it! + */ + MBEDTLS_ECP_BUDGET( ( T_size - 1 ) * MBEDTLS_ECP_OPS_ADD ); + + for( i = 1; i < T_size; i <<= 1 ) + { + j = i; + while( j-- ) + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, &T[i + j], &T[j], &T[i] ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_add; + +norm_add: +#endif + /* + * Normalize final elements in T. Even though there are no holes now, we + * still need the auxiliary array for homogeneity with the previous + * call. Also, skip T[0] which is already normalised, being a copy of P. + */ + for( j = 0; j + 1 < T_size; j++ ) + TT[j] = T + j + 1; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +cleanup: +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + rs_ctx->rsm->i = j; + } +#endif + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Select precomputed point: R = sign(i) * T[ abs(i) / 2 ] + * + * See ecp_comb_recode_core() for background + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_select_comb( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + unsigned char i ) +{ + int ret; + unsigned char ii, j; + + /* Ignore the "sign" bit and scale down */ + ii = ( i & 0x7Fu ) >> 1; + + /* Read the whole table to thwart cache-based timing attacks */ + for( j = 0; j < T_size; j++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->X, &T[j].X, j == ii ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->Y, &T[j].Y, j == ii ) ); + } + + /* Safely invert result if i is "negative" */ + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, R, i >> 7 ) ); + +cleanup: + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +/* + * Core multiplication algorithm for the (modified) comb method. + * This part is actually common with the basic comb method (GECC 3.44) + * + * Cost: d A + d D + 1 R + */ +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +static int ecp_mul_comb_core( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + const unsigned char x[], size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point Txi; + size_t i; + + mbedtls_ecp_point_init( &Txi ); + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + rs_ctx->rsm->state != ecp_rsm_comb_core ) + { + rs_ctx->rsm->i = 0; + rs_ctx->rsm->state = ecp_rsm_comb_core; + } + + /* new 'if' instead of nested for the sake of the 'else' branch */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + { + /* restore current index (R already pointing to rs_ctx->rsm->R) */ + i = rs_ctx->rsm->i; + } + else +#endif + { + /* Start with a non-zero point and randomize its coordinates */ + i = d; + MBEDTLS_MPI_CHK( ecp_select_comb( grp, R, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); + if( f_rng != 0 ) + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, R, f_rng, p_rng ) ); + } + + while( i != 0 ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL + MBEDTLS_ECP_OPS_ADD ); + --i; + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, R, R ) ); + MBEDTLS_MPI_CHK( ecp_select_comb( grp, &Txi, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, R, R, &Txi ) ); + } + +cleanup: + + mbedtls_ecp_point_free( &Txi ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + rs_ctx->rsm->i = i; + /* no need to save R, already pointing to rs_ctx->rsm->R */ + } +#endif + + return( ret ); +} +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +#if !defined(MBEDTLS_ECP_MUL_COMB_ALT) +/* + * Recode the scalar to get constant-time comb multiplication + * + * As the actual scalar recoding needs an odd scalar as a starting point, + * this wrapper ensures that by replacing m by N - m if necessary, and + * informs the caller that the result of multiplication will be negated. + * + * This works because we only support large prime order for Short Weierstrass + * curves, so N is always odd hence either m or N - m is. + * + * See ecp_comb_recode_core() for background. + */ +static int ecp_comb_recode_scalar( const mbedtls_ecp_group *grp, + const mbedtls_mpi *m, + unsigned char k[COMB_MAX_D + 1], + size_t d, + unsigned char w, + unsigned char *parity_trick ) +{ + int ret; + mbedtls_mpi M, mm; + + mbedtls_mpi_init( &M ); + mbedtls_mpi_init( &mm ); + + /* N is always odd (see above), just make extra sure */ + if( mbedtls_mpi_get_bit( &grp->N, 0 ) != 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* do we need the parity trick? */ + *parity_trick = ( mbedtls_mpi_get_bit( m, 0 ) == 0 ); + + /* execute parity fix in constant time */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &M, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mm, &grp->N, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &M, &mm, *parity_trick ) ); + + /* actual scalar recoding */ + ecp_comb_recode_core( k, d, w, &M ); + +cleanup: + mbedtls_mpi_free( &mm ); + mbedtls_mpi_free( &M ); + + return( ret ); +} + +/* + * Perform comb multiplication (for short Weierstrass curves) + * once the auxiliary table has been pre-computed. + * + * Scalar recoding may use a parity trick that makes us compute -m * P, + * if that is the case we'll need to recover m * P at the end. + */ +static int ecp_mul_comb_after_precomp( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *T, + unsigned char T_size, + unsigned char w, + size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char parity_trick; + unsigned char k[COMB_MAX_D + 1]; + mbedtls_ecp_point *RR = R; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + RR = &rs_ctx->rsm->R; + + if( rs_ctx->rsm->state == ecp_rsm_final_norm ) + goto final_norm; + } +#endif + + MBEDTLS_MPI_CHK( ecp_comb_recode_scalar( grp, m, k, d, w, + &parity_trick ) ); + MBEDTLS_MPI_CHK( ecp_mul_comb_core( grp, RR, T, T_size, k, d, + f_rng, p_rng, rs_ctx ) ); + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, RR, parity_trick ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_final_norm; + +final_norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, RR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, RR ) ); +#endif + +cleanup: + return( ret ); +} + +/* + * Pick window size based on curve size and whether we optimize for base point + */ +static unsigned char ecp_pick_window_size( const mbedtls_ecp_group *grp, + unsigned char p_eq_g ) +{ + unsigned char w; + + /* + * Minimize the number of multiplications, that is minimize + * 10 * d * w + 18 * 2^(w-1) + 11 * d + 7 * w, with d = ceil( nbits / w ) + * (see costs of the various parts, with 1S = 1M) + */ + w = grp->nbits >= 384 ? 5 : 4; + + /* + * If P == G, pre-compute a bit more, since this may be re-used later. + * Just adding one avoids upping the cost of the first mul too much, + * and the memory cost too. + */ + if( p_eq_g ) + w++; + + /* + * Make sure w is within bounds. + * (The last test is useful only for very small curves in the test suite.) + */ + if( w > MBEDTLS_ECP_WINDOW_SIZE ) + w = MBEDTLS_ECP_WINDOW_SIZE; + if( w >= grp->nbits ) + w = 2; + + return( w ); +} + +/* + * Multiplication using the comb method - for curves in short Weierstrass form + * + * This function is mainly responsible for administrative work: + * - managing the restart context if enabled + * - managing the table of precomputed points (passed between the below two + * functions): allocation, computation, ownership tranfer, freeing. + * + * It delegates the actual arithmetic work to: + * ecp_precompute_comb() and ecp_mul_comb_with_precomp() + * + * See comments on ecp_comb_recode_core() regarding the computation strategy. + */ +static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char w, p_eq_g, i; + size_t d; + unsigned char T_size, T_ok; + mbedtls_ecp_point *T; + + ECP_RS_ENTER( rsm ); + + /* Is P the base point ? */ +#if MBEDTLS_ECP_FIXED_POINT_OPTIM == 1 + p_eq_g = ( mbedtls_mpi_cmp_mpi( &P->Y, &grp->G.Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->X, &grp->G.X ) == 0 ); +#else + p_eq_g = 0; +#endif + + /* Pick window size and deduce related sizes */ + w = ecp_pick_window_size( grp, p_eq_g ); + T_size = 1U << ( w - 1 ); + d = ( grp->nbits + w - 1 ) / w; + + /* Pre-computed table: do we have it already for the base point? */ + if( p_eq_g && grp->T != NULL ) + { + /* second pointer to the same table, will be deleted on exit */ + T = grp->T; + T_ok = 1; + } + else +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* Pre-computed table: do we have one in progress? complete? */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->T != NULL ) + { + /* transfer ownership of T from rsm to local function */ + T = rs_ctx->rsm->T; + rs_ctx->rsm->T = NULL; + rs_ctx->rsm->T_size = 0; + + /* This effectively jumps to the call to mul_comb_after_precomp() */ + T_ok = rs_ctx->rsm->state >= ecp_rsm_comb_core; + } + else +#endif + /* Allocate table if we didn't have any */ + { + T = mbedtls_calloc( T_size, sizeof( mbedtls_ecp_point ) ); + if( T == NULL ) + { + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + goto cleanup; + } + + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_init( &T[i] ); + + T_ok = 0; + } + + /* Compute table (or finish computing it) if not done already */ + if( !T_ok ) + { + MBEDTLS_MPI_CHK( ecp_precompute_comb( grp, T, P, w, d, rs_ctx ) ); + + if( p_eq_g ) + { + /* almost transfer ownership of T to the group, but keep a copy of + * the pointer to use for calling the next function more easily */ + grp->T = T; + grp->T_size = T_size; + } + } + + /* Actual comb multiplication using precomputed points */ + MBEDTLS_MPI_CHK( ecp_mul_comb_after_precomp( grp, R, m, + T, T_size, w, d, + f_rng, p_rng, rs_ctx ) ); + +cleanup: + + /* does T belong to the group? */ + if( T == grp->T ) + T = NULL; + + /* does T belong to the restart context? */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS && T != NULL ) + { + /* transfer ownership of T from local function to rsm */ + rs_ctx->rsm->T_size = T_size; + rs_ctx->rsm->T = T; + T = NULL; + } +#endif + + /* did T belong to us? then let's destroy it! */ + if( T != NULL ) + { + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_free( &T[i] ); + mbedtls_free( T ); + } + + /* don't free R while in progress in case R == P */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) +#endif + /* prevent caller from using invalid value */ + if( ret != 0 ) + mbedtls_ecp_point_free( R ); + + ECP_RS_LEAVE( rsm ); + + return( ret ); +} +#else +int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ); +#endif /*!MBEDTLS_ECP_MUL_COMB_ALT*/ + +#endif /* ECP_SHORTWEIERSTRASS */ + +#if defined(ECP_MONTGOMERY) +/* + * For Montgomery curves, we do all the internal arithmetic in projective + * coordinates. Import/export of points uses only the x coordinates, which is + * internaly represented as X / Z. + * + * For scalar multiplication, we'll use a Montgomery ladder. + */ + +/* + * Normalize Montgomery x/z coordinates: X = X/Z, Z = 1 + * Cost: 1M + 1I + */ +static int ecp_normalize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P ) +{ + int ret; + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_mxz( grp, P ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &P->Z, &P->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &P->Z ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_mxz(). + * + * This countermeasure was first suggested in [2]. + * Cost: 2M + */ +static int ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_mxz( grp, P, f_rng, p_rng ); +#endif /* MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &l ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->Z, &P->Z, &l ) ); MOD_MUL( P->Z ); + +cleanup: + mbedtls_mpi_free( &l ); + + return( ret ); +} + +/* + * Double-and-add: R = 2P, S = P + Q, with d = X(P - Q), + * for Montgomery curves in x/z coordinates. + * + * http://www.hyperelliptic.org/EFD/g1p/auto-code/montgom/xz/ladder/mladd-1987-m.op3 + * with + * d = X1 + * P = (X2, Z2) + * Q = (X3, Z3) + * R = (X4, Z4) + * S = (X5, Z5) + * and eliminating temporary variables tO, ..., t4. + * + * Cost: 5M + 4S + */ +static int ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q, + const mbedtls_mpi *d ) +{ + int ret; + mbedtls_mpi A, AA, B, BB, E, C, D, DA, CB; + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_add_mxz( grp, R, S, P, Q, d ) ); +#endif /* MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ + + mbedtls_mpi_init( &A ); mbedtls_mpi_init( &AA ); mbedtls_mpi_init( &B ); + mbedtls_mpi_init( &BB ); mbedtls_mpi_init( &E ); mbedtls_mpi_init( &C ); + mbedtls_mpi_init( &D ); mbedtls_mpi_init( &DA ); mbedtls_mpi_init( &CB ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &A, &P->X, &P->Z ) ); MOD_ADD( A ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &AA, &A, &A ) ); MOD_MUL( AA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &B, &P->X, &P->Z ) ); MOD_SUB( B ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &BB, &B, &B ) ); MOD_MUL( BB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &E, &AA, &BB ) ); MOD_SUB( E ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &C, &Q->X, &Q->Z ) ); MOD_ADD( C ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &D, &Q->X, &Q->Z ) ); MOD_SUB( D ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DA, &D, &A ) ); MOD_MUL( DA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &CB, &C, &B ) ); MOD_MUL( CB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &S->X, &DA, &CB ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->X, &S->X, &S->X ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S->Z, &DA, &CB ) ); MOD_SUB( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, &S->Z, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, d, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->X, &AA, &BB ) ); MOD_MUL( R->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &grp->A, &E ) ); MOD_MUL( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &R->Z, &BB, &R->Z ) ); MOD_ADD( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &E, &R->Z ) ); MOD_MUL( R->Z ); + +cleanup: + mbedtls_mpi_free( &A ); mbedtls_mpi_free( &AA ); mbedtls_mpi_free( &B ); + mbedtls_mpi_free( &BB ); mbedtls_mpi_free( &E ); mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &D ); mbedtls_mpi_free( &DA ); mbedtls_mpi_free( &CB ); + + return( ret ); +} + +/* + * Multiplication with Montgomery ladder in x/z coordinates, + * for curves in Montgomery form + */ +#if !defined(MBEDTLS_ECP_MUL_MXZ_ALT) +static int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + size_t i; + unsigned char b; + mbedtls_ecp_point RP; + mbedtls_mpi PX; + + mbedtls_ecp_point_init( &RP ); mbedtls_mpi_init( &PX ); + + /* Save PX and read from P before writing to R, in case P == R */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &PX, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &RP, P ) ); + + /* Set R to zero in modified x/z coordinates */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->X, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 0 ) ); + mbedtls_mpi_free( &R->Y ); + + /* RP.X might be sligtly larger than P, so reduce it */ + MOD_ADD( RP.X ); + + /* Randomize coordinates of the starting point */ + if( f_rng != NULL ) + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, &RP, f_rng, p_rng ) ); + + /* Loop invariant: R = result so far, RP = R + P */ + i = mbedtls_mpi_bitlen( m ); /* one past the (zero-based) most significant bit */ + while( i-- > 0 ) + { + b = mbedtls_mpi_get_bit( m, i ); + /* + * if (b) R = 2R + P else R = 2R, + * which is: + * if (b) double_add( RP, R, RP, R ) + * else double_add( R, RP, R, RP ) + * but using safe conditional swaps to avoid leaks + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + MBEDTLS_MPI_CHK( ecp_double_add_mxz( grp, R, &RP, R, &RP, &PX ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + } + + MBEDTLS_MPI_CHK( ecp_normalize_mxz( grp, R ) ); + +cleanup: + mbedtls_ecp_point_free( &RP ); mbedtls_mpi_free( &PX ); + + return( ret ); +} + +#else +int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif /* MBEDTLS_ECP_MUL_MXZ_ALT */ +#endif /* ECP_MONTGOMERY */ + +/* + * Restartable multiplication R = m * P + */ +int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* reset ops count for this call if top-level */ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) + rs_ctx->ops_done = 0; +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* skip argument check when restarting */ + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + { + /* check_privkey is free */ + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_CHK ); + + /* Common sanity checks */ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) ); + } + + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + MBEDTLS_MPI_CHK( ecp_mul_mxz( grp, R, m, P, f_rng, p_rng ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + MBEDTLS_MPI_CHK( ecp_mul_comb( grp, R, m, P, f_rng, p_rng, rs_ctx ) ); +#endif + +cleanup: + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL ) + rs_ctx->depth--; +#endif + + return( ret ); +} + +/* + * Multiplication R = m * P + */ +int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + return( mbedtls_ecp_mul_restartable( grp, R, m, P, f_rng, p_rng, NULL ) ); +} + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * Check that an affine point is valid as a public key, + * short weierstrass curves (SEC1 3.2.3.1) + */ +static int ecp_check_pubkey_sw( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi YY, RHS; + + /* pt coordinates must be normalized for our checks */ + if( mbedtls_mpi_cmp_int( &pt->X, 0 ) < 0 || + mbedtls_mpi_cmp_int( &pt->Y, 0 ) < 0 || + mbedtls_mpi_cmp_mpi( &pt->X, &grp->P ) >= 0 || + mbedtls_mpi_cmp_mpi( &pt->Y, &grp->P ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + mbedtls_mpi_init( &YY ); mbedtls_mpi_init( &RHS ); + + /* + * YY = Y^2 + * RHS = X (X^2 + A) + B = X^3 + A X + B + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &YY, &pt->Y, &pt->Y ) ); MOD_MUL( YY ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &pt->X, &pt->X ) ); MOD_MUL( RHS ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &RHS, &RHS, 3 ) ); MOD_SUB( RHS ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->A ) ); MOD_ADD( RHS ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &RHS, &pt->X ) ); MOD_MUL( RHS ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->B ) ); MOD_ADD( RHS ); + + if( mbedtls_mpi_cmp_mpi( &YY, &RHS ) != 0 ) + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + +cleanup: + + mbedtls_mpi_free( &YY ); mbedtls_mpi_free( &RHS ); + + return( ret ); +} +#endif /* ECP_SHORTWEIERSTRASS */ + +/* + * R = m * P with shortcuts for m == 1 and m == -1 + * NOT constant-time - ONLY for short Weierstrass! + */ +#if !defined(MBEDTLS_ECP_MULADD_ALT) +static int mbedtls_ecp_mul_shortcuts( mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + + if( mbedtls_mpi_cmp_int( m, 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + } + else if( mbedtls_mpi_cmp_int( m, -1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + if( mbedtls_mpi_cmp_int( &R->Y, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &R->Y, &grp->P, &R->Y ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, R, m, P, + NULL, NULL, rs_ctx ) ); + } + +cleanup: + return( ret ); +} +#endif /* !MBEDTLS_ECP_MULADD_ALT */ + +/* + * Addition: R = P + Q, result's coordinates normalized + */ +#if !defined(MBEDTLS_ECP_ADD_ALT) +int ecp_add( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + + if( ecp_get_type( grp ) != ECP_TYPE_SHORT_WEIERSTRASS ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, R, P, Q ) ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, R ) ); + +cleanup: + return( ret ); +} +#else +int ecp_add( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ); +#endif /* !MBEDTLS_ECP_ADD_ALT */ + +#if !defined(MBEDTLS_ECP_MULADD_ALT) +/* + * Restartable linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point mP; + mbedtls_ecp_point *pmP = &mP; + mbedtls_ecp_point *pR = R; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( ecp_get_type( grp ) != ECP_TYPE_SHORT_WEIERSTRASS ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + mbedtls_ecp_point_init( &mP ); + + ECP_RS_ENTER( ma ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + { + /* redirect intermediate results to restart context */ + pmP = &rs_ctx->ma->mP; + pR = &rs_ctx->ma->R; + + /* jump to next operation */ + if( rs_ctx->ma->state == ecp_rsma_mul2 ) + goto mul2; + if( rs_ctx->ma->state == ecp_rsma_add ) + goto add; + if( rs_ctx->ma->state == ecp_rsma_norm ) + goto norm; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pmP, m, P, rs_ctx ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_mul2; + +mul2: +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pR, n, Q, rs_ctx ) ); + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ +#if !defined(MBEDTLS_ECP_ADD_ALT) +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_add; + +add: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_ADD ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, pR, pmP, pR ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_norm; + +norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, pR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, pR ) ); +#endif + +#else + MBEDTLS_MPI_CHK(ecp_add(grp, R, &mP, R )); +#endif + +cleanup: +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + + mbedtls_ecp_point_free( &mP ); + + ECP_RS_LEAVE( ma ); + + return( ret ); +} + +/* + * Linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + return( mbedtls_ecp_muladd_restartable( grp, R, m, P, n, Q, NULL ) ); +} +#endif /* MBEDTLS_ECP_MULADD_ALT */ + +#if defined(ECP_MONTGOMERY) +/* + * Check validity of a public key for Montgomery curves with x-only schemes + */ +static int ecp_check_pubkey_mx( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + /* [Curve25519 p. 5] Just check X is the correct number of bytes */ + /* Allow any public value, if it's too big then we'll just reduce it mod p + * (RFC 7748 sec. 5 para. 3). */ + if( mbedtls_mpi_size( &pt->X ) > ( grp->nbits + 7 ) / 8 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); +} +#endif /* ECP_MONTGOMERY */ + +/* + * Check that a point is valid as a public key + */ +int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + + /* Must use affine coordinates */ + if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + return( ecp_check_pubkey_mx( grp, pt ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + return( ecp_check_pubkey_sw( grp, pt ) ); +#endif + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Check that an mbedtls_mpi is valid as a private key + */ +int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, + const mbedtls_mpi *d ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + { + /* see RFC 7748 sec. 5 para. 5 */ + if( mbedtls_mpi_get_bit( d, 0 ) != 0 || + mbedtls_mpi_get_bit( d, 1 ) != 0 || + mbedtls_mpi_bitlen( d ) - 1 != grp->nbits ) /* mbedtls_mpi_bitlen is one-based! */ + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + else + + /* see [Curve25519] page 5 */ + if( grp->nbits == 254 && mbedtls_mpi_get_bit( d, 2 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); + } +#endif /* ECP_MONTGOMERY */ +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* see SEC1 3.2 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + else + return( 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Generate a private key + */ +int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + size_t n_size; + + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + n_size = ( grp->nbits + 7 ) / 8; + +#if defined(ECP_MONTGOMERY) + if( ecp_get_type( grp ) == ECP_TYPE_MONTGOMERY ) + { + /* [M225] page 5 */ + size_t b; + + do { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + } while( mbedtls_mpi_bitlen( d ) == 0); + + /* Make sure the most significant bit is nbits */ + b = mbedtls_mpi_bitlen( d ) - 1; /* mbedtls_mpi_bitlen is one-based */ + if( b > grp->nbits ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, b - grp->nbits ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, grp->nbits, 1 ) ); + + /* Make sure the last two bits are unset for Curve448, three bits for + Curve25519 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 1, 0 ) ); + if( grp->nbits == 254 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 2, 0 ) ); + } + } + else +#endif /* ECP_MONTGOMERY */ + +#if defined(ECP_SHORTWEIERSTRASS) + if( ecp_get_type( grp ) == ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* SEC1 3.2.1: Generate d such that 1 <= n < N */ + int count = 0; + + /* + * Match the procedure given in RFC 6979 (deterministic ECDSA): + * - use the same byte ordering; + * - keep the leftmost nbits bits of the generated octet string; + * - try until result is in the desired range. + * This also avoids any biais, which is especially important for ECDSA. + */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, 8 * n_size - grp->nbits ) ); + + /* + * Each try has at worst a probability 1/2 of failing (the msb has + * a probability 1/2 of being 0, and then the result will be < N), + * so after 30 tries failure probability is a most 2**(-30). + * + * For most curves, 1 try is enough with overwhelming probability, + * since N starts with a lot of 1s in binary, but some curves + * such as secp224k1 are actually very close to the worst case. + */ + if( ++count > 30 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + +cleanup: + return( ret ); +} + +/* + * Generate a keypair with configurable base point + */ +int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( G != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, Q, d, G, f_rng, p_rng ) ); + +cleanup: + return( ret ); +} + +/* + * Generate key pair, wrapper for conventional base point + */ +int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + return( mbedtls_ecp_gen_keypair_base( grp, &grp->G, d, Q, f_rng, p_rng ) ); +} + +/* + * Generate a keypair, prettier wrapper + */ +int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_gen_keypair( &key->grp, &key->d, &key->Q, f_rng, p_rng ) ); +} + +/* + * Check a public-private key pair + */ +int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv ) +{ + int ret; + mbedtls_ecp_point Q; + mbedtls_ecp_group grp; + ECP_VALIDATE_RET( pub != NULL ); + ECP_VALIDATE_RET( prv != NULL ); + + if( pub->grp.id == MBEDTLS_ECP_DP_NONE || + pub->grp.id != prv->grp.id || + mbedtls_mpi_cmp_mpi( &pub->Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Z, &prv->Q.Z ) ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + mbedtls_ecp_point_init( &Q ); + mbedtls_ecp_group_init( &grp ); + + /* mbedtls_ecp_mul() needs a non-const group... */ + mbedtls_ecp_group_copy( &grp, &prv->grp ); + + /* Also checks d is valid */ + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &Q, &prv->d, &prv->grp.G, NULL, NULL ) ); + + if( mbedtls_mpi_cmp_mpi( &Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &Q.Z, &prv->Q.Z ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free( &Q ); + mbedtls_ecp_group_free( &grp ); + + return( ret ); +} + +#if defined(MBEDTLS_SELF_TEST) + +/* + * Checkup routine + */ +int mbedtls_ecp_self_test( int verbose ) +{ + int ret; + size_t i; + mbedtls_ecp_group grp; + mbedtls_ecp_point R, P; + mbedtls_mpi m; + unsigned long add_c_prev, dbl_c_prev, mul_c_prev; + /* exponents especially adapted for secp192r1 */ + const char *exponents[] = + { + "000000000000000000000000000000000000000000000001", /* one */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22830", /* N - 1 */ + "5EA6F389A38B8BC81E767753B15AA5569E1782E30ABE7D25", /* random */ + "400000000000000000000000000000000000000000000000", /* one and zeros */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* all ones */ + "555555555555555555555555555555555555555555555555", /* 101010... */ + }; + + mbedtls_ecp_group_init( &grp ); + mbedtls_ecp_point_init( &R ); + mbedtls_ecp_point_init( &P ); + mbedtls_mpi_init( &m ); + + /* Use secp192r1 if available, or any available curve */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_SECP192R1 ) ); +#else + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, mbedtls_ecp_curve_list()->grp_id ) ); +#endif + + if( verbose != 0 ) + mbedtls_printf( " ECP test #1 (constant op_count, base point G): " ); + + /* Do a dummy multiplication first to trigger precomputation */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &m, 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &P, &m, &grp.G, NULL, NULL ) ); + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + if( verbose != 0 ) + mbedtls_printf( " ECP test #2 (constant op_count, other point): " ); + /* We computed P = 2G last time, use it */ + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + +cleanup: + + if( ret < 0 && verbose != 0 ) + mbedtls_printf( "Unexpected error, return code = %08X\n", ret ); + + mbedtls_ecp_group_free( &grp ); + mbedtls_ecp_point_free( &R ); + mbedtls_ecp_point_free( &P ); + mbedtls_mpi_free( &m ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* !MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c new file mode 100644 index 00000000000..440b326551e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c @@ -0,0 +1,1485 @@ +/* + * Elliptic curves over GF(p): curve-specific data and functions + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" + +#include + +#if defined(MBEDTLS_ECP_ALT) + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + ( (mbedtls_mpi_uint) a << 0 ) | \ + ( (mbedtls_mpi_uint) b << 8 ) | \ + ( (mbedtls_mpi_uint) c << 16 ) | \ + ( (mbedtls_mpi_uint) d << 24 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_4( a, b, 0, 0 ) + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + BYTES_TO_T_UINT_4( a, b, c, d ), \ + BYTES_TO_T_UINT_4( e, f, g, h ) + +#else /* 64-bits */ + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + ( (mbedtls_mpi_uint) a << 0 ) | \ + ( (mbedtls_mpi_uint) b << 8 ) | \ + ( (mbedtls_mpi_uint) c << 16 ) | \ + ( (mbedtls_mpi_uint) d << 24 ) | \ + ( (mbedtls_mpi_uint) e << 32 ) | \ + ( (mbedtls_mpi_uint) f << 40 ) | \ + ( (mbedtls_mpi_uint) g << 48 ) | \ + ( (mbedtls_mpi_uint) h << 56 ) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) + +#endif /* bits in mbedtls_mpi_uint */ + +/* + * Note: the constants are in little-endian order + * to be directly usable in MPIs + */ + +/* + * Domain parameters for secp192r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static const mbedtls_mpi_uint secp192r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192r1_a[] = { + BYTES_TO_T_UINT_8( 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192r1_b[] = { + BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), + BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), + BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), +}; +static const mbedtls_mpi_uint secp192r1_gx[] = { + BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), + BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), + BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), +}; +static const mbedtls_mpi_uint secp192r1_gy[] = { + BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), + BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), + BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), +}; +static const mbedtls_mpi_uint secp192r1_n[] = { + BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), + BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +/* + * Domain parameters for secp224r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static const mbedtls_mpi_uint secp224r1_p[] = { + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224r1_a[] = { + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp224r1_b[] = { + BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), + BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), + BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), + BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), +}; +static const mbedtls_mpi_uint secp224r1_gx[] = { + BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), + BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), + BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), + BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), +}; +static const mbedtls_mpi_uint secp224r1_gy[] = { + BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), + BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), + BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), + BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), +}; +static const mbedtls_mpi_uint secp224r1_n[] = { + BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), + BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +/* + * Domain parameters for secp256r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static const mbedtls_mpi_uint secp256r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256r1_a[] = { + BYTES_TO_T_UINT_8( 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256r1_b[] = { + BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), + BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), + BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), + BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), +}; +static const mbedtls_mpi_uint secp256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), + BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), + BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), + BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), +}; +static const mbedtls_mpi_uint secp256r1_gy[] = { + BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), + BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), + BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), + BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), +}; +static const mbedtls_mpi_uint secp256r1_n[] = { + BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), + BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +/* + * Domain parameters for secp384r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static const mbedtls_mpi_uint secp384r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp384r1_a[] = { + BYTES_TO_T_UINT_8( 0xFC, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp384r1_b[] = { + BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), + BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), + BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), + BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), + BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), + BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), +}; +static const mbedtls_mpi_uint secp384r1_gx[] = { + BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), + BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), + BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), + BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), + BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), + BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), +}; +static const mbedtls_mpi_uint secp384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), + BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), + BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), + BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), + BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), + BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), +}; +static const mbedtls_mpi_uint secp384r1_n[] = { + BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), + BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), + BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +/* + * Domain parameters for secp521r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static const mbedtls_mpi_uint secp521r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_b[] = { + BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), + BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), + BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), + BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), + BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), + BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), + BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), + BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), + BYTES_TO_T_UINT_2( 0x51, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gx[] = { + BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), + BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), + BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), + BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), + BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), + BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), + BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), + BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), + BYTES_TO_T_UINT_2( 0xC6, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gy[] = { + BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), + BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), + BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), + BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), + BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), + BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), + BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), + BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), + BYTES_TO_T_UINT_2( 0x18, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_n[] = { + BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), + BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), + BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), + BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), + BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static const mbedtls_mpi_uint secp192k1_p[] = { + BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_b[] = { + BYTES_TO_T_UINT_2( 0x03, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_gx[] = { + BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), + BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), + BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), +}; +static const mbedtls_mpi_uint secp192k1_gy[] = { + BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), + BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), + BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), +}; +static const mbedtls_mpi_uint secp192k1_n[] = { + BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), + BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static const mbedtls_mpi_uint secp224k1_p[] = { + BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp224k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_b[] = { + BYTES_TO_T_UINT_2( 0x05, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_gx[] = { + BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), + BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), + BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), + BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), +}; +static const mbedtls_mpi_uint secp224k1_gy[] = { + BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), + BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), + BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), + BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), +}; +static const mbedtls_mpi_uint secp224k1_n[] = { + BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), + BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static const mbedtls_mpi_uint secp256k1_p[] = { + BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_b[] = { + BYTES_TO_T_UINT_2( 0x07, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_gx[] = { + BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), + BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), + BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), + BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), +}; +static const mbedtls_mpi_uint secp256k1_gy[] = { + BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), + BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), + BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), + BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), +}; +static const mbedtls_mpi_uint secp256k1_n[] = { + BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), + BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +/* + * Domain parameters for brainpoolP256r1 (RFC 5639 3.4) + */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP256r1_p[] = { + BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), + BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), + BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_a[] = { + BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), + BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), + BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), + BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_b[] = { + BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), + BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), + BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), + BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), + BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), + BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), + BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gy[] = { + BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), + BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), + BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), + BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_n[] = { + BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), + BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), + BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +/* + * Domain parameters for brainpoolP384r1 (RFC 5639 3.6) + */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP384r1_p[] = { + BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), + BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), + BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), + BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_a[] = { + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), + BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), + BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), + BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), + BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_b[] = { + BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), + BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), + BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), + BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), + BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gx[] = { + BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), + BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), + BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), + BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), + BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), + BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), + BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), + BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), + BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), + BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_n[] = { + BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), + BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), + BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), + BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +/* + * Domain parameters for brainpoolP512r1 (RFC 5639 3.7) + */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP512r1_p[] = { + BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), + BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), + BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), + BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), + BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_a[] = { + BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), + BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), + BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), + BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), + BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), + BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), + BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), + BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_b[] = { + BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), + BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), + BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), + BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), + BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), + BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), + BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), + BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gx[] = { + BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), + BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), + BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), + BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), + BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), + BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), + BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), + BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gy[] = { + BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), + BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), + BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), + BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), + BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), + BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), + BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_n[] = { + BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), + BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), + BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), + BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), + BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +/* + * Create an MPI from embedded constants + * (assumes len is an exact multiple of sizeof mbedtls_mpi_uint) + */ +static inline void ecp_mpi_load( mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_t len ) +{ + X->s = 1; + X->n = len / sizeof( mbedtls_mpi_uint ); + X->p = (mbedtls_mpi_uint *) p; +} + +/* + * Set an MPI to static value 1 + */ +static inline void ecp_mpi_set1( mbedtls_mpi *X ) +{ + static mbedtls_mpi_uint one[] = { 1 }; + X->s = 1; + X->n = 1; + X->p = one; +} + +/* + * Make group available from embedded constants + */ +static int ecp_group_load( mbedtls_ecp_group *grp, + const mbedtls_mpi_uint *p, size_t plen, + const mbedtls_mpi_uint *a, size_t alen, + const mbedtls_mpi_uint *b, size_t blen, + const mbedtls_mpi_uint *gx, size_t gxlen, + const mbedtls_mpi_uint *gy, size_t gylen, + const mbedtls_mpi_uint *n, size_t nlen) +{ + ecp_mpi_load( &grp->P, p, plen ); + if( a != NULL ) + ecp_mpi_load( &grp->A, a, alen ); + ecp_mpi_load( &grp->B, b, blen ); + ecp_mpi_load( &grp->N, n, nlen ); + + ecp_mpi_load( &grp->G.X, gx, gxlen ); + ecp_mpi_load( &grp->G.Y, gy, gylen ); + ecp_mpi_set1( &grp->G.Z ); + + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + grp->nbits = mbedtls_mpi_bitlen( &grp->N ); + + grp->h = 1; + + return( 0 ); +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* Forward declarations */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static int ecp_mod_p192( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static int ecp_mod_p224( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static int ecp_mod_p256( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static int ecp_mod_p384( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static int ecp_mod_p521( mbedtls_mpi * ); +#endif + +#define NIST_MODP( P ) grp->modp = ecp_mod_ ## P; +#else +#define NIST_MODP( P ) +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +/* Additional forward declarations */ +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +static int ecp_mod_p255( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +static int ecp_mod_p448( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static int ecp_mod_p192k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static int ecp_mod_p224k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static int ecp_mod_p256k1( mbedtls_mpi * ); +#endif + +#define LOAD_GROUP_A( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + G ## _a, sizeof( G ## _a ), \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#define LOAD_GROUP( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + NULL, 0, \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +/* + * Specialized function for creating the Curve25519 group + */ +static int ecp_use_curve25519( mbedtls_ecp_group *grp ) +{ + int ret; + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "01DB42" ) ); + + /* P = 2^255 - 19 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 255 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 19 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* N = 2^252 + 27742317777372353535851937790883648493 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->N, 16, + "14DEF9DEA2F79CD65812631A5CF5D3ED" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 252, 1 ) ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 9 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* Actually, the required msb for private keys */ + grp->nbits = 254; + +cleanup: + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +/* + * Specialized function for creating the Curve448 group + */ +static int ecp_use_curve448( mbedtls_ecp_group *grp ) +{ + mbedtls_mpi Ns; + int ret; + + mbedtls_mpi_init( &Ns ); + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "98AA" ) ); + + /* P = 2^448 - 2^224 - 1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 5 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* N = 2^446 - 13818066809895115352007386748515426880336692474882178609894547503885 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 446, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &Ns, 16, + "8335DC163BB124B65129C96FDE933D8D723A70AADC873D6D54A7BB0D" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &grp->N, &grp->N, &Ns ) ); + + /* Actually, the required msb for private keys */ + grp->nbits = 447; + +cleanup: + mbedtls_mpi_free( &Ns ); + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +/* + * Set a group using well-known domain parameters + */ +int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id ) +{ + mbedtls_ecp_group_free( grp ); + + grp->id = id; + + switch( id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + NIST_MODP( p192 ); + return( LOAD_GROUP_A( secp192r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + NIST_MODP( p224 ); + return( LOAD_GROUP_A( secp224r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + NIST_MODP( p256 ); + return( LOAD_GROUP_A( secp256r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + case MBEDTLS_ECP_DP_SECP384R1: + NIST_MODP( p384 ); + return( LOAD_GROUP_A( secp384r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + case MBEDTLS_ECP_DP_SECP521R1: + NIST_MODP( p521 ); + return( LOAD_GROUP( secp521r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + case MBEDTLS_ECP_DP_SECP192K1: + grp->modp = ecp_mod_p192k1; + return( LOAD_GROUP_A( secp192k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + case MBEDTLS_ECP_DP_SECP224K1: + grp->modp = ecp_mod_p224k1; + return( LOAD_GROUP_A( secp224k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + case MBEDTLS_ECP_DP_SECP256K1: + grp->modp = ecp_mod_p256k1; + return( LOAD_GROUP_A( secp256k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + case MBEDTLS_ECP_DP_BP256R1: + return( LOAD_GROUP_A( brainpoolP256r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + case MBEDTLS_ECP_DP_BP384R1: + return( LOAD_GROUP_A( brainpoolP384r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + case MBEDTLS_ECP_DP_BP512R1: + return( LOAD_GROUP_A( brainpoolP512r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + case MBEDTLS_ECP_DP_CURVE25519: + grp->modp = ecp_mod_p255; + return( ecp_use_curve25519( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + case MBEDTLS_ECP_DP_CURVE448: + grp->modp = ecp_mod_p448; + return( ecp_use_curve448( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + + default: + mbedtls_ecp_group_free( grp ); + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* + * Fast reduction modulo the primes used by the NIST curves. + * + * These functions are critical for speed, but not needed for correct + * operations. So, we make the choice to heavily rely on the internals of our + * bignum library, which creates a tight coupling between these functions and + * our MPI implementation. However, the coupling between the ECP module and + * MPI remains loose, since these functions can be deactivated at will. + */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +/* + * Compared to the way things are presented in FIPS 186-3 D.2, + * we proceed in columns, from right (least significant chunk) to left, + * adding chunks to N in place, and keeping a carry for the next chunk. + * This avoids moving things around in memory, and uselessly adding zeros, + * compared to the more straightforward, line-oriented approach. + * + * For this prime we need to handle data in chunks of 64 bits. + * Since this is always a multiple of our basic mbedtls_mpi_uint, we can + * use a mbedtls_mpi_uint * to designate such a chunk, and small loops to handle it. + */ + +/* Add 64-bit chunks (dst += src) and update carry */ +static inline void add64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *src, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + mbedtls_mpi_uint c = 0; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++, src++ ) + { + *dst += c; c = ( *dst < c ); + *dst += *src; c += ( *dst < *src ); + } + *carry += c; +} + +/* Add carry to a 64-bit chunk and update carry */ +static inline void carry64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++ ) + { + *dst += *carry; + *carry = ( *dst < *carry ); + } +} + +#define WIDTH 8 / sizeof( mbedtls_mpi_uint ) +#define A( i ) N->p + i * WIDTH +#define ADD( i ) add64( p, A( i ), &c ) +#define NEXT p += WIDTH; carry64( p, &c ) +#define LAST p += WIDTH; *p = c; while( ++p < end ) *p = 0 + +/* + * Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) + */ +static int ecp_mod_p192( mbedtls_mpi *N ) +{ + int ret; + mbedtls_mpi_uint c = 0; + mbedtls_mpi_uint *p, *end; + + /* Make sure we have enough blocks so that A(5) is legal */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, 6 * WIDTH ) ); + + p = N->p; + end = p + N->n; + + ADD( 3 ); ADD( 5 ); NEXT; // A0 += A3 + A5 + ADD( 3 ); ADD( 4 ); ADD( 5 ); NEXT; // A1 += A3 + A4 + A5 + ADD( 4 ); ADD( 5 ); LAST; // A2 += A4 + A5 + +cleanup: + return( ret ); +} + +#undef WIDTH +#undef A +#undef ADD +#undef NEXT +#undef LAST +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * The reader is advised to first understand ecp_mod_p192() since the same + * general structure is used here, but with additional complications: + * (1) chunks of 32 bits, and (2) subtractions. + */ + +/* + * For these primes, we need to handle data in chunks of 32 bits. + * This makes it more complicated if we use 64 bits limbs in MPI, + * which prevents us from using a uniform access method as for p192. + * + * So, we define a mini abstraction layer to access 32 bit chunks, + * load them in 'cur' for work, and store them back from 'cur' when done. + * + * While at it, also define the size of N in terms of 32-bit chunks. + */ +#define LOAD32 cur = A( i ); + +#if defined(MBEDTLS_HAVE_INT32) /* 32 bit */ + +#define MAX32 N->n +#define A( j ) N->p[j] +#define STORE32 N->p[i] = cur; + +#else /* 64-bit */ + +#define MAX32 N->n * 2 +#define A( j ) j % 2 ? (uint32_t)( N->p[j/2] >> 32 ) : (uint32_t)( N->p[j/2] ) +#define STORE32 \ + if( i % 2 ) { \ + N->p[i/2] &= 0x00000000FFFFFFFF; \ + N->p[i/2] |= ((mbedtls_mpi_uint) cur) << 32; \ + } else { \ + N->p[i/2] &= 0xFFFFFFFF00000000; \ + N->p[i/2] |= (mbedtls_mpi_uint) cur; \ + } + +#endif /* sizeof( mbedtls_mpi_uint ) */ + +/* + * Helpers for addition and subtraction of chunks, with signed carry. + */ +static inline void add32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *dst += src; + *carry += ( *dst < src ); +} + +static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *carry -= ( *dst < src ); + *dst -= src; +} + +#define ADD( j ) add32( &cur, A( j ), &c ); +#define SUB( j ) sub32( &cur, A( j ), &c ); + +/* + * Helpers for the main 'loop' + * (see fix_negative for the motivation of C) + */ +#define INIT( b ) \ + int ret; \ + signed char c = 0, cc; \ + uint32_t cur; \ + size_t i = 0, bits = b; \ + mbedtls_mpi C; \ + mbedtls_mpi_uint Cp[ b / 8 / sizeof( mbedtls_mpi_uint) + 1 ]; \ + \ + C.s = 1; \ + C.n = b / 8 / sizeof( mbedtls_mpi_uint) + 1; \ + C.p = Cp; \ + memset( Cp, 0, C.n * sizeof( mbedtls_mpi_uint ) ); \ + \ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, b * 2 / 8 / sizeof( mbedtls_mpi_uint ) ) ); \ + LOAD32; + +#define NEXT \ + STORE32; i++; LOAD32; \ + cc = c; c = 0; \ + if( cc < 0 ) \ + sub32( &cur, -cc, &c ); \ + else \ + add32( &cur, cc, &c ); \ + +#define LAST \ + STORE32; i++; \ + cur = c > 0 ? c : 0; STORE32; \ + cur = 0; while( ++i < MAX32 ) { STORE32; } \ + if( c < 0 ) fix_negative( N, c, &C, bits ); + +/* + * If the result is negative, we get it in the form + * c * 2^(bits + 32) + N, with c negative and N positive shorter than 'bits' + */ +static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, size_t bits ) +{ + int ret; + + /* C = - c * 2^(bits + 32) */ +#if !defined(MBEDTLS_HAVE_INT64) + ((void) bits); +#else + if( bits == 224 ) + C->p[ C->n - 1 ] = ((mbedtls_mpi_uint) -c) << 32; + else +#endif + C->p[ C->n - 1 ] = (mbedtls_mpi_uint) -c; + + /* N = - ( C - N ) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, C, N ) ); + N->s = -1; + +cleanup: + + return( ret ); +} + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +/* + * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + */ +static int ecp_mod_p224( mbedtls_mpi *N ) +{ + INIT( 224 ); + + SUB( 7 ); SUB( 11 ); NEXT; // A0 += -A7 - A11 + SUB( 8 ); SUB( 12 ); NEXT; // A1 += -A8 - A12 + SUB( 9 ); SUB( 13 ); NEXT; // A2 += -A9 - A13 + SUB( 10 ); ADD( 7 ); ADD( 11 ); NEXT; // A3 += -A10 + A7 + A11 + SUB( 11 ); ADD( 8 ); ADD( 12 ); NEXT; // A4 += -A11 + A8 + A12 + SUB( 12 ); ADD( 9 ); ADD( 13 ); NEXT; // A5 += -A12 + A9 + A13 + SUB( 13 ); ADD( 10 ); LAST; // A6 += -A13 + A10 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +/* + * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + */ +static int ecp_mod_p256( mbedtls_mpi *N ) +{ + INIT( 256 ); + + ADD( 8 ); ADD( 9 ); + SUB( 11 ); SUB( 12 ); SUB( 13 ); SUB( 14 ); NEXT; // A0 + + ADD( 9 ); ADD( 10 ); + SUB( 12 ); SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A1 + + ADD( 10 ); ADD( 11 ); + SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A2 + + ADD( 11 ); ADD( 11 ); ADD( 12 ); ADD( 12 ); ADD( 13 ); + SUB( 15 ); SUB( 8 ); SUB( 9 ); NEXT; // A3 + + ADD( 12 ); ADD( 12 ); ADD( 13 ); ADD( 13 ); ADD( 14 ); + SUB( 9 ); SUB( 10 ); NEXT; // A4 + + ADD( 13 ); ADD( 13 ); ADD( 14 ); ADD( 14 ); ADD( 15 ); + SUB( 10 ); SUB( 11 ); NEXT; // A5 + + ADD( 14 ); ADD( 14 ); ADD( 15 ); ADD( 15 ); ADD( 14 ); ADD( 13 ); + SUB( 8 ); SUB( 9 ); NEXT; // A6 + + ADD( 15 ); ADD( 15 ); ADD( 15 ); ADD( 8 ); + SUB( 10 ); SUB( 11 ); SUB( 12 ); SUB( 13 ); LAST; // A7 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) + */ +static int ecp_mod_p384( mbedtls_mpi *N ) +{ + INIT( 384 ); + + ADD( 12 ); ADD( 21 ); ADD( 20 ); + SUB( 23 ); NEXT; // A0 + + ADD( 13 ); ADD( 22 ); ADD( 23 ); + SUB( 12 ); SUB( 20 ); NEXT; // A2 + + ADD( 14 ); ADD( 23 ); + SUB( 13 ); SUB( 21 ); NEXT; // A2 + + ADD( 15 ); ADD( 12 ); ADD( 20 ); ADD( 21 ); + SUB( 14 ); SUB( 22 ); SUB( 23 ); NEXT; // A3 + + ADD( 21 ); ADD( 21 ); ADD( 16 ); ADD( 13 ); ADD( 12 ); ADD( 20 ); ADD( 22 ); + SUB( 15 ); SUB( 23 ); SUB( 23 ); NEXT; // A4 + + ADD( 22 ); ADD( 22 ); ADD( 17 ); ADD( 14 ); ADD( 13 ); ADD( 21 ); ADD( 23 ); + SUB( 16 ); NEXT; // A5 + + ADD( 23 ); ADD( 23 ); ADD( 18 ); ADD( 15 ); ADD( 14 ); ADD( 22 ); + SUB( 17 ); NEXT; // A6 + + ADD( 19 ); ADD( 16 ); ADD( 15 ); ADD( 23 ); + SUB( 18 ); NEXT; // A7 + + ADD( 20 ); ADD( 17 ); ADD( 16 ); + SUB( 19 ); NEXT; // A8 + + ADD( 21 ); ADD( 18 ); ADD( 17 ); + SUB( 20 ); NEXT; // A9 + + ADD( 22 ); ADD( 19 ); ADD( 18 ); + SUB( 21 ); NEXT; // A10 + + ADD( 23 ); ADD( 20 ); ADD( 19 ); + SUB( 22 ); LAST; // A11 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#undef A +#undef LOAD32 +#undef STORE32 +#undef MAX32 +#undef INIT +#undef NEXT +#undef LAST + +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || + MBEDTLS_ECP_DP_SECP256R1_ENABLED || + MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +/* + * Here we have an actual Mersenne prime, so things are more straightforward. + * However, chunks are aligned on a 'weird' boundary (521 bits). + */ + +/* Size of p521 in terms of mbedtls_mpi_uint */ +#define P521_WIDTH ( 521 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* Bits to keep in the most significant mbedtls_mpi_uint */ +#define P521_MASK 0x01FF + +/* + * Fast quasi-reduction modulo p521 (FIPS 186-3 D.2.5) + * Write N as A1 + 2^521 A0, return A0 + A1 + */ +static int ecp_mod_p521( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P521_WIDTH + 1]; + /* Worst case for the size of M is when mbedtls_mpi_uint is 16 bits: + * we need to hold bits 513 to 1056, which is 34 limbs, that is + * P521_WIDTH + 1. Otherwise P521_WIDTH is enough. */ + + if( N->n < P521_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P521_WIDTH - 1 ); + if( M.n > P521_WIDTH + 1 ) + M.n = P521_WIDTH + 1; + M.p = Mp; + memcpy( Mp, N->p + P521_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 521 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + + /* N = A0 */ + N->p[P521_WIDTH - 1] &= P521_MASK; + for( i = P521_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} + +#undef P521_WIDTH +#undef P521_MASK +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +/* Size of p255 in terms of mbedtls_mpi_uint */ +#define P255_WIDTH ( 255 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* + * Fast quasi-reduction modulo p255 = 2^255 - 19 + * Write N as A0 + 2^255 A1, return A0 + 19 * A1 + */ +static int ecp_mod_p255( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P255_WIDTH + 2]; + + if( N->n < P255_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P255_WIDTH - 1 ); + if( M.n > P255_WIDTH + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + P255_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 255 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + M.n++; /* Make room for multiplication by 19 */ + + /* N = A0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( N, 255, 0 ) ); + for( i = P255_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + 19 * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &M, 19 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Size of p448 in terms of mbedtls_mpi_uint */ +#define P448_WIDTH ( 448 / 8 / sizeof( mbedtls_mpi_uint ) ) + +/* Number of limbs fully occupied by 2^224 (max), and limbs used by it (min) */ +#define DIV_ROUND_UP( X, Y ) ( ( ( X ) + ( Y ) - 1 ) / ( Y ) ) +#define P224_WIDTH_MIN ( 28 / sizeof( mbedtls_mpi_uint ) ) +#define P224_WIDTH_MAX DIV_ROUND_UP( 28, sizeof( mbedtls_mpi_uint ) ) +#define P224_UNUSED_BITS ( ( P224_WIDTH_MAX * sizeof( mbedtls_mpi_uint ) * 8 ) - 224 ) + +/* + * Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 + * Write N as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return + * A0 + A1 + B1 + (B0 + B1) * 2^224. This is different to the reference + * implementation of Curve448, which uses its own special 56-bit limbs rather + * than a generic bignum library. We could squeeze some extra speed out on + * 32-bit machines by splitting N up into 32-bit limbs and doing the + * arithmetic using the limbs directly as we do for the NIST primes above, + * but for 64-bit targets it should use half the number of operations if we do + * the reduction with 224-bit limbs, since mpi_add_mpi will then use 64-bit adds. + */ +static int ecp_mod_p448( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M, Q; + mbedtls_mpi_uint Mp[P448_WIDTH + 1], Qp[P448_WIDTH]; + + if( N->n <= P448_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P448_WIDTH ); + if( M.n > P448_WIDTH ) + /* Shouldn't be called with N larger than 2^896! */ + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof( Mp ) ); + memcpy( Mp, N->p + P448_WIDTH, M.n * sizeof( mbedtls_mpi_uint ) ); + + /* N = A0 */ + for( i = P448_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N += A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + + /* Q = B1, N += B1 */ + Q = M; + Q.p = Qp; + memcpy( Qp, Mp, sizeof( Qp ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Q, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &Q ) ); + + /* M = (B0 + B1) * 2^224, N += M */ + if( sizeof( mbedtls_mpi_uint ) > 4 ) + Mp[P224_WIDTH_MIN] &= ( (mbedtls_mpi_uint)-1 ) >> ( P224_UNUSED_BITS ); + for( i = P224_WIDTH_MAX; i < M.n; ++i ) + Mp[i] = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &Q ) ); + M.n = P448_WIDTH + 1; /* Make room for shifted carry bit from the addition */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &M, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo P = 2^s - R, + * with R about 33 bits, used by the Koblitz curves. + * + * Write N as A0 + 2^224 A1, return A0 + R * A1. + * Actually do two passes, since R is big. + */ +#define P_KOBLITZ_MAX ( 256 / 8 / sizeof( mbedtls_mpi_uint ) ) // Max limbs in P +#define P_KOBLITZ_R ( 8 / sizeof( mbedtls_mpi_uint ) ) // Limbs in R +static inline int ecp_mod_koblitz( mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, + size_t adjust, size_t shift, mbedtls_mpi_uint mask ) +{ + int ret; + size_t i; + mbedtls_mpi M, R; + mbedtls_mpi_uint Mp[P_KOBLITZ_MAX + P_KOBLITZ_R + 1]; + + if( N->n < p_limbs ) + return( 0 ); + + /* Init R */ + R.s = 1; + R.p = Rp; + R.n = P_KOBLITZ_R; + + /* Common setup for M */ + M.s = 1; + M.p = Mp; + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + + /* Second pass */ + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED) || + MBEDTLS_ECP_DP_SECP224K1_ENABLED) || + MBEDTLS_ECP_DP_SECP256K1_ENABLED) */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +/* + * Fast quasi-reduction modulo p192k1 = 2^192 - R, + * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x0100001119 + */ +static int ecp_mod_p192k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + + return( ecp_mod_koblitz( N, Rp, 192 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +/* + * Fast quasi-reduction modulo p224k1 = 2^224 - R, + * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 + */ +static int ecp_mod_p224k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + +#if defined(MBEDTLS_HAVE_INT64) + return( ecp_mod_koblitz( N, Rp, 4, 1, 32, 0xFFFFFFFF ) ); +#else + return( ecp_mod_koblitz( N, Rp, 224 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +#endif +} + +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo p256k1 = 2^256 - R, + * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 + */ +static int ecp_mod_p256k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + return( ecp_mod_koblitz( N, Rp, 256 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#endif /* !MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h new file mode 100644 index 00000000000..e7ba8da2b7d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h @@ -0,0 +1,86 @@ +/** + * \file rsa.h + * + * \brief This file provides an API for the RSA public-key cryptosystem. + * + * The RSA public-key cryptosystem is defined in Public-Key + * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption + * and Public-Key Cryptography Standards (PKCS) #1 v2.1: + * RSA Cryptography Specifications. + * + */ +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright (C) 2019, NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_RSA_ALT) +#include + +typedef struct +{ + int ver; /*!< Always 0.*/ + size_t len; /*!< The size of \p N in Bytes. */ + + mbedtls_mpi N; /*!< The public modulus. */ + mbedtls_mpi E; /*!< The public exponent. */ + + mbedtls_mpi D; /*!< The private exponent. */ + mbedtls_mpi P; /*!< The first prime factor. */ + mbedtls_mpi Q; /*!< The second prime factor. */ + + mbedtls_mpi DP; /*!< D % (P - 1). */ + mbedtls_mpi DQ; /*!< D % (Q - 1). */ + mbedtls_mpi QP; /*!< 1 / (Q % P). */ + + mbedtls_mpi RN; /*!< cached R^2 mod N. */ + + mbedtls_mpi RP; /*!< cached R^2 mod P. */ + mbedtls_mpi RQ; /*!< cached R^2 mod Q. */ + + mbedtls_mpi Vi; /*!< The cached blinding value. */ + mbedtls_mpi Vf; /*!< The cached un-blinding value. */ + + int padding; /*!< Selects padding mode: + #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and + #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */ + int hash_id; /*!< Hash identifier of mbedtls_md_type_t type, + as specified in md.h for use in the MGF + mask generating function used in the + EME-OAEP and EMSA-PSS encodings. */ +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t mutex; /*!< Thread-safety mutex. */ +#endif + + /** Reference to object mapped between SSS Layer */ + sss_object_t *pSSSObject; +} mbedtls_rsa_context; + +#endif /* MBEDTLS_RSA_ALT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c new file mode 100644 index 00000000000..eb223c24c77 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c @@ -0,0 +1,508 @@ +/* + * + * Copyright 2018-2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * Implementation of key association between NXP Secure Element and mbedtls. + * @par History + * 1.0 30-jan-2018 : Initial version + * + *****************************************************************************/ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_ALT) && SSS_HAVE_ALT_SSS + +/** @ingroup ax_mbed_tls */ +/** @{ */ + +#include +#include +#include + +#include "fsl_sss_api.h" +#include "mbedtls/pk_internal.h" +#include "mbedtls/platform.h" +#include "mbedtls/rsa.h" +#include "mbedtls/ssl.h" +#include "mbedtls/ssl_internal.h" +#include "mbedtls/version.h" +#include "sss_mbedtls.h" +#if defined(FLOW_VERBOSE) && (FLOW_VERBOSE == 1) +#define LOG_API_CALLS 1 +#else +#define LOG_API_CALLS 0 +#endif /* FLOW_VERBOSE */ + +#ifndef LOG_API_CALLS +#define LOG_API_CALLS 1 /* Log by default */ +#endif + +extern mbedtls_pk_info_t ax_mbedtls_rsakeypair_info; +extern mbedtls_pk_info_t ax_mbedtls_rsapubkey_info; + +static size_t sss_eckey_get_bitlen(const void *ctx); +static int sss_eckey_sign(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + unsigned char *sig, + size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +static int sss_eckey_verify(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + const unsigned char *sig, + size_t sig_len); +static int sss_eckey_check_pair(const void *pub, const void *prv); +static int sss_eckeypair_can_do(mbedtls_pk_type_t type); +static int sss_ecpubkey_can_do(mbedtls_pk_type_t type); +static void sss_eckeypair_free_func(void *ctx); +static void sss_ecpubkey_free_func(void *ctx); + +static const mbedtls_pk_info_t ax_mbedtls_eckeypair_info = { + MBEDTLS_PK_ECKEY, + "AxEC_Keypair", + &sss_eckey_get_bitlen, + &sss_eckeypair_can_do, + NULL, + &sss_eckey_sign, + NULL, // decrypt_func, + NULL, // encrypt_func, + &sss_eckey_check_pair, + NULL, //&ax_eckey_alloc, + &sss_eckeypair_free_func, + NULL, //&ax_eckey_debug, +}; + +static const mbedtls_pk_info_t ax_mbedtls_ecpubkey_info = { + MBEDTLS_PK_ECKEY, + "AxEC_pubkey", + &sss_eckey_get_bitlen, + &sss_ecpubkey_can_do, + &sss_eckey_verify, + NULL, + NULL, + NULL, + NULL, + NULL, + &sss_ecpubkey_free_func, + NULL, +}; + +/* clang-format off */ +typedef struct _object_identifiers +{ + uint32_t identifier[16]; + size_t indentifier_len; + int groupId; + char* name; +} object_identifiers_t; +object_identifiers_t object_identifiers_gvar[] = { + + { { 1, 2, 840, 10045, 3, 1, 1 }, 7, MBEDTLS_ECP_DP_SECP192R1, "MBEDTLS_ECP_DP_SECP192R1" }, + { { 1, 3, 132, 0, 33 }, 5, MBEDTLS_ECP_DP_SECP224R1, "MBEDTLS_ECP_DP_SECP224R1" }, + { { 1, 2, 840, 10045, 3, 1, 7 }, 7, MBEDTLS_ECP_DP_SECP256R1, "MBEDTLS_ECP_DP_SECP256R1" }, + { { 1, 3, 132, 0, 34 }, 5, MBEDTLS_ECP_DP_SECP384R1, "MBEDTLS_ECP_DP_SECP384R1" }, + { { 1, 3, 132, 0, 35 }, 5, MBEDTLS_ECP_DP_SECP521R1, "MBEDTLS_ECP_DP_SECP521R1" }, + + { { 1, 3, 36, 3, 3, 2, 8, 1, 1, 7 }, 10, MBEDTLS_ECP_DP_BP256R1, "MBEDTLS_ECP_DP_BP256R1" }, + { { 1, 3, 24, 3, 3, 2, 8, 1, 1, 7 }, 10, MBEDTLS_ECP_DP_BP256R1, "MBEDTLS_ECP_DP_BP256R1" }, + { { 1, 3, 36, 3, 3, 2, 8, 1, 1, 11}, 10, MBEDTLS_ECP_DP_BP384R1, "MBEDTLS_ECP_DP_BP384R1" }, + { { 1, 3, 36, 3, 3, 2, 8, 1, 1, 13}, 10, MBEDTLS_ECP_DP_BP512R1, "MBEDTLS_ECP_DP_BP512R1" }, + + { { 1, 3, 132, 0, 31 }, 5, MBEDTLS_ECP_DP_SECP192K1, "MBEDTLS_ECP_DP_SECP192K1" }, + { { 1, 3, 132, 0, 32 }, 5, MBEDTLS_ECP_DP_SECP224K1, "MBEDTLS_ECP_DP_SECP224K1" }, + { { 1, 3, 132, 0, 10 }, 5, MBEDTLS_ECP_DP_SECP256K1, "MBEDTLS_ECP_DP_SECP256K1" }, + {{0,}, 0, 0}, +}; +/* clang-format on */ + +#ifdef _MSC_VER +#pragma warning(disable : 4127) +#endif + +int get_group_id(uint32_t *objectid, uint8_t objectIdLen) +{ + size_t i = 0, j = 0; + int groupId = -1; + + while (1) { + if (object_identifiers_gvar[i].indentifier_len == 0) { + break; + } + + if (object_identifiers_gvar[i].indentifier_len != objectIdLen) { + i++; + continue; + } + + for (j = 0; j < object_identifiers_gvar[i].indentifier_len; j++) { + if (object_identifiers_gvar[i].identifier[j] != objectid[j]) { + i++; + goto skip_oid; + } + } + + groupId = object_identifiers_gvar[i].groupId; + LOG_I("Group id found - %s \n", object_identifiers_gvar[i].name); + break; + skip_oid: + continue; + } + + return groupId; +} + +int sss_mbedtls_associate_keypair(mbedtls_pk_context *pkey, sss_object_t *pkeyObject) +{ + void *pax_ctx = NULL; + uint32_t objectId[16] = { + 0, + }; + uint8_t objectIdLen = sizeof(objectId); + sss_status_t status = kStatus_SSS_Fail; + + memset(pkey, 0, sizeof(*pkey)); + + if (pkeyObject->cipherType == kSSS_CipherType_EC_NIST_P || pkeyObject->cipherType == kSSS_CipherType_EC_NIST_K || + pkeyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + pkeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY || + pkeyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + LOG_D("Associating ECC key-pair '0x%08X'", pkeyObject->keyId); + + pkey->pk_info = &ax_mbedtls_eckeypair_info; + pax_ctx = (mbedtls_ecp_keypair *)mbedtls_calloc(1, sizeof(mbedtls_ecp_keypair)); + ((mbedtls_ecp_keypair *)pax_ctx)->grp.pSSSObject = pkeyObject; + status = sss_util_asn1_get_oid_from_sssObj(pkeyObject, objectId, &objectIdLen); + if (status != kStatus_SSS_Success) { + if (pax_ctx != NULL) { + mbedtls_free(pax_ctx); + } + return 1; + } + + ((mbedtls_ecp_keypair *)pax_ctx)->grp.id = get_group_id(objectId, objectIdLen); + if (((mbedtls_ecp_keypair *)pax_ctx)->grp.id == MBEDTLS_ECP_DP_NONE) { + LOG_E(" sss_mbedtls_associate_keypair: Group id not found...\n"); + if (pax_ctx != NULL) { + mbedtls_free(pax_ctx); + } + return 1; + } + pkey->pk_ctx = pax_ctx; + } +#ifdef MBEDTLS_RSA_ALT + else if (pkeyObject->cipherType == kSSS_CipherType_RSA || pkeyObject->cipherType == kSSS_CipherType_RSA_CRT) { + uint8_t pbKey[1024]; + size_t pbKeyBitLen = 0; + size_t pbKeyBytetLen = sizeof(pbKey); + uint8_t *modulus = NULL; + size_t modlen = 0; + uint8_t *pubExp = NULL; + size_t pubExplen = 0; + + LOG_D("Associating RSA key-pair '0x%08X'", pkeyObject->keyId); + + pkey->pk_info = &ax_mbedtls_rsakeypair_info; + pax_ctx = (mbedtls_rsa_context *)mbedtls_calloc(1, sizeof(mbedtls_rsa_context)); + ((mbedtls_rsa_context *)pax_ctx)->pSSSObject = pkeyObject; + + status = sss_key_store_get_key(pkeyObject->keyStore, pkeyObject, pbKey, &pbKeyBytetLen, &pbKeyBitLen); + if (status != kStatus_SSS_Success) { + return 1; + } + + status = sss_util_asn1_rsa_parse_public(pbKey, pbKeyBytetLen, &modulus, &modlen, &pubExp, &pubExplen); + if (modulus != NULL) { + SSS_FREE(modulus); + modulus = NULL; + } + if (pubExp != NULL) { + SSS_FREE(pubExp); + pubExp = NULL; + } + if (status != kStatus_SSS_Success) { + return 1; + } + + ((mbedtls_rsa_context *)pax_ctx)->len = (modlen * 8); + } +#endif /* MBEDTLS_RSA_ALT */ + else { + return 1; + } + + pkey->pk_ctx = pax_ctx; + return 0; +} + +int sss_mbedtls_associate_pubkey(mbedtls_pk_context *pkey, sss_object_t *pkeyObject) +{ + void *pax_ctx = NULL; + uint32_t objectId[16] = { + 0, + }; + uint8_t objectIdLen = sizeof(objectId); + sss_status_t status = kStatus_SSS_Fail; + + memset(pkey, 0, sizeof(*pkey)); + + if (pkeyObject->cipherType == kSSS_CipherType_EC_NIST_P || pkeyObject->cipherType == kSSS_CipherType_EC_NIST_K || + pkeyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + pkeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY || + pkeyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + LOG_D("Associating ECC public key '0x%08X'", pkeyObject->keyId); + + pkey->pk_info = &ax_mbedtls_ecpubkey_info; + pax_ctx = (mbedtls_ecp_keypair *)mbedtls_calloc(1, sizeof(mbedtls_ecp_keypair)); + ((mbedtls_ecp_keypair *)pax_ctx)->grp.pSSSObject = pkeyObject; + + status = sss_util_asn1_get_oid_from_sssObj(pkeyObject, objectId, &objectIdLen); + if (status != kStatus_SSS_Success) { + if (pax_ctx != NULL) { + mbedtls_free(pax_ctx); + } + return 1; + } + + ((mbedtls_ecp_keypair *)pax_ctx)->grp.id = get_group_id(objectId, objectIdLen); + if (((mbedtls_ecp_keypair *)pax_ctx)->grp.id == MBEDTLS_ECP_DP_NONE) { + LOG_E(" sss_mbedtls_associate_pubkey: Group id not found...\n"); + if (pax_ctx != NULL) { + mbedtls_free(pax_ctx); + } + return 1; + } + } +#ifdef MBEDTLS_RSA_ALT + else if (pkeyObject->cipherType == kSSS_CipherType_RSA || pkeyObject->cipherType == kSSS_CipherType_RSA_CRT) { + uint8_t pbKey[1400]; + size_t pbKeyBitLen = 0; + size_t pbKeyBytetLen = sizeof(pbKey); + uint8_t *modulus = NULL; + size_t modlen = 0; + uint8_t *pubExp = NULL; + size_t pubExplen = 0; + + LOG_D("Associating RSA public key '0x%08X'", pkeyObject->keyId); + + pax_ctx = (mbedtls_rsa_context *)mbedtls_calloc(1, sizeof(mbedtls_rsa_context)); + pkey->pk_ctx = pax_ctx; + pkey->pk_info = &ax_mbedtls_rsapubkey_info; + ((mbedtls_rsa_context *)pax_ctx)->pSSSObject = pkeyObject; + + status = sss_key_store_get_key(pkeyObject->keyStore, pkeyObject, pbKey, &pbKeyBytetLen, &pbKeyBitLen); + if (status != kStatus_SSS_Success) { + return 1; + } + + status = sss_util_asn1_rsa_parse_public(pbKey, pbKeyBytetLen, &modulus, &modlen, &pubExp, &pubExplen); + if (modulus != NULL) { + SSS_FREE(modulus); + modulus = NULL; + } + if (pubExp != NULL) { + SSS_FREE(pubExp); + pubExp = NULL; + } + if (status != kStatus_SSS_Success) { + return 1; + } + + ((mbedtls_rsa_context *)pax_ctx)->len = (modlen * 8); + } +#endif /* MBEDTLS_RSA_ALT */ + else { + return 1; + } + + pkey->pk_ctx = pax_ctx; + return 0; +} + +int sss_mbedtls_associate_ecdhctx( + mbedtls_ssl_handshake_params *handshake, sss_object_t *pSSSObject, sss_key_store_t *hostKs) +{ + sss_status_t status = kStatus_SSS_Fail; + uint32_t objectId[16] = { + 0, + }; + uint8_t objectIdLen = sizeof(objectId); + + status = sss_util_asn1_get_oid_from_sssObj(pSSSObject, objectId, &objectIdLen); + if (status != kStatus_SSS_Success) { + return 1; + } + + handshake->ecdh_ctx.grp.id = get_group_id(objectId, objectIdLen); + + handshake->ecdh_ctx.grp.pSSSObject = pSSSObject; + handshake->ecdh_ctx.grp.hostKs = hostKs; +#if LOG_API_CALLS > 1 + LOG_I("Associating ECC key-pair '%d' for handshake.\r\n", key_index); +#endif + return 0; +} + +static size_t sss_eckey_get_bitlen(const void *ctx) +{ + return ((64 << 1) + 1); +} + +static int sss_eckey_verify(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + const unsigned char *sig, + size_t sig_len) +{ + sss_status_t status = kStatus_SSS_Success; + sss_asymmetric_t asymVerifyCtx; + sss_object_t *sssObject = NULL; + sss_algorithm_t algorithm; + mbedtls_ecp_keypair *pax_ctx = (mbedtls_ecp_keypair *)ctx; + + sssObject = pax_ctx->grp.pSSSObject; + + switch (md_alg) { + case MBEDTLS_MD_SHA1: + algorithm = kAlgorithm_SSS_SHA1; + break; + case MBEDTLS_MD_SHA224: + algorithm = kAlgorithm_SSS_SHA224; + break; + case MBEDTLS_MD_SHA256: + algorithm = kAlgorithm_SSS_SHA256; + break; + case MBEDTLS_MD_SHA384: + algorithm = kAlgorithm_SSS_SHA384; + break; + case MBEDTLS_MD_SHA512: + algorithm = kAlgorithm_SSS_SHA512; + break; + default: + return 1; + } + + LOG_D("%s: Verify using key '0x%08X'", __FUNCTION__, pax_ctx->grp.pSSSObject->keyId); + + status = sss_asymmetric_context_init( + &asymVerifyCtx, sssObject->keyStore->session, sssObject, algorithm, kMode_SSS_Verify); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_context_init verify context Failed...\n"); + return 1; + } + + status = sss_asymmetric_verify_digest(&asymVerifyCtx, (uint8_t *)hash, hash_len, (uint8_t *)sig, sig_len); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_verify_digest Failed...\n"); + return 1; + } + + return (0); +} + +static int sss_eckey_sign(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + unsigned char *sig, + size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + int ret = 0; + size_t u16_sig_len = 1024; + sss_asymmetric_t asymVerifyCtx; + sss_status_t status = kStatus_SSS_Success; + sss_object_t *sssObject = NULL; + mbedtls_ecp_keypair *pax_ctx = (mbedtls_ecp_keypair *)ctx; + sss_algorithm_t algorithm; + + sssObject = pax_ctx->grp.pSSSObject; + switch (md_alg) { + case MBEDTLS_MD_SHA1: + algorithm = kAlgorithm_SSS_SHA1; + break; + case MBEDTLS_MD_SHA224: + algorithm = kAlgorithm_SSS_SHA224; + break; + case MBEDTLS_MD_SHA256: + algorithm = kAlgorithm_SSS_SHA256; + break; + case MBEDTLS_MD_SHA384: + algorithm = kAlgorithm_SSS_SHA384; + break; + case MBEDTLS_MD_SHA512: + algorithm = kAlgorithm_SSS_SHA512; + break; + default: + return 1; + } + + status = + sss_asymmetric_context_init(&asymVerifyCtx, sssObject->keyStore->session, sssObject, algorithm, kMode_SSS_Sign); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_context_init verify context Failed...\n"); + return 1; + } + + LOG_D("%s: Signing using key '0x%08lX'", __FUNCTION__, pax_ctx->grp.pSSSObject->keyId); + + status = sss_asymmetric_sign_digest(&asymVerifyCtx, (uint8_t *)hash, hash_len, sig, &u16_sig_len); + if (status != kStatus_SSS_Success) { + LOG_W(" sss_asymmetric_sign_digest Failed...\n"); + return 1; + } + + *sig_len = u16_sig_len; + + return (ret); +} + +static int sss_eckey_check_pair(const void *pub, const void *prv) +{ + return 0; +} + +static int sss_eckeypair_can_do(mbedtls_pk_type_t type) +{ + return (type == MBEDTLS_PK_ECKEY || type == MBEDTLS_PK_ECKEY_DH || type == MBEDTLS_PK_ECDSA); +} + +static int sss_ecpubkey_can_do(mbedtls_pk_type_t type) +{ + return (type == MBEDTLS_PK_ECKEY || type == MBEDTLS_PK_ECKEY_DH || type == MBEDTLS_PK_ECDSA); +} + +static void sss_eckeypair_free_func(void *ctx) +{ + mbedtls_ecp_keypair *pax_ctx = (mbedtls_ecp_keypair *)ctx; + if (pax_ctx != NULL) { + mbedtls_free(ctx); + } + return; +} + +static void sss_ecpubkey_free_func(void *ctx) +{ + mbedtls_ecp_keypair *pax_ctx = (mbedtls_ecp_keypair *)ctx; + if (pax_ctx != NULL) { + mbedtls_free(ctx); + } + return; +} + +/** @} */ + +#endif /* MBEDTLS_ECP_ALT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h new file mode 100644 index 00000000000..a559e19005a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h @@ -0,0 +1,102 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @par Description + * Implementation of key association between NXP Secure Element and mbedtls. + * @par History + * 1.0 30-jan-2018 : Initial version + * + *****************************************************************************/ + +#ifndef AX_MBEDTLS_H +#define AX_MBEDTLS_H + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_ALT_SSS +#include "sss_mbedtls.h" +#else +#include "ax_mbedtls.h" +#endif + +#include + +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM +#include +#endif +#if SSS_HAVE_MBEDTLS +#include +#endif + +/** @ingroup ax_mbed_tls */ +/** @{ */ + +#include "fsl_sss_api.h" +#include "mbedtls/pk.h" +#include "mbedtls/ssl.h" + +/** + * @brief Associate a keypair provisioned in the secure element for + * subsequent operations. + * + * @param[out] pkey Pointer to the mbedtls_pk_context which will be + * associated with data corresponding to the key_index + * + * @param[in] pkeyObject The object that we are going to be use. + * + * @return 0 if successful, or 1 if unsuccessful + */ +int sss_mbedtls_associate_keypair(mbedtls_pk_context *pkey, sss_object_t *pkeyObject); + +/** + * @brief Associate a pubkey provisioned in the secure element for + * subsequent operations. + * + * @param[out] pkey Pointer to the mbedtls_pk_context which will be + * associated with data corresponding to the key index + * + * @param[in] pkeyObject The object that we are going to be use. + * + * @return 0 if successful, or 1 if unsuccessful + */ +int sss_mbedtls_associate_pubkey(mbedtls_pk_context *pkey, sss_object_t *pkeyObject); + +/** + * @brief Update ECDSA HandShake key with given inded. + * + * @param[in,out] handshake Pointer to the mbedtls_ssl_handshake_params which + * will be associated with data corresponding to the + * key index + * + * @param[in] pkeyObject The object that we are going to be use. + * + * @param[in] hostKs Keystore to host for session key. + * + * @return 0 if successful, or 1 if unsuccessful + */ + +int sss_mbedtls_associate_ecdhctx( + mbedtls_ssl_handshake_params *handshake, sss_object_t *pkeyObject, sss_key_store_t *hostKs); + +/** @} */ + +/** + * \brief This function frees the components of a key pair. Original implementation + * \param key The key pair to free. + */ +void mbedtls_ecp_keypair_free_o(mbedtls_ecp_keypair *key); + +/** + * same as ``mbedtls_ecp_tls_read_group`` + */ +int mbedtls_ecp_tls_read_group_o(mbedtls_ecp_group *grp, const unsigned char **buf, size_t len); + +#endif /* AX_MBEDTLS_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c new file mode 100644 index 00000000000..989aa0eab31 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c @@ -0,0 +1,251 @@ +/* + * + * Copyright 2018-2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file sss_mbedtls_rsa.c + * + * @par Description + * Implementation of key association between SSS and mbedtls. + * + *****************************************************************************/ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +/** @ingroup ax_mbed_tls */ +/** @{ */ + +#if defined(MBEDTLS_RSA_ALT) + +#include +#include +#include + +#include "fsl_sss_api.h" +#include "mbedtls/pk_internal.h" +#include "mbedtls/platform.h" +#include "mbedtls/rsa.h" +#include "mbedtls/ssl.h" +#include "mbedtls/ssl_internal.h" +#include "mbedtls/version.h" +#include "sss_mbedtls.h" +#if defined(FLOW_VERBOSE) && (FLOW_VERBOSE == 1) +#define LOG_API_CALLS 1 +#else +#define LOG_API_CALLS 0 +#endif /* FLOW_VERBOSE */ + +#ifndef LOG_API_CALLS +#define LOG_API_CALLS 1 /* Log by default */ +#endif + +static size_t sss_rsakey_get_bitlen(const void *ctx); +static int sss_rsakey_sign(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + unsigned char *sig, + size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +static int sss_rsakey_verify(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + const unsigned char *sig, + size_t sig_len); +static int sss_rsakey_check_pair(const void *pub, const void *prv); +static int sss_rsakeypair_can_do(mbedtls_pk_type_t type); +static int sss_rsapubkey_can_do(mbedtls_pk_type_t type); +static void sss_rsakeypair_free_func(void *ctx); +static void sss_rsapubkey_free_func(void *ctx); + +const mbedtls_pk_info_t ax_mbedtls_rsakeypair_info = { + MBEDTLS_PK_RSA, + "AxRSA_Keypair", + &sss_rsakey_get_bitlen, + &sss_rsakeypair_can_do, + NULL, + &sss_rsakey_sign, + NULL, // decrypt_func, + NULL, // encrypt_func, + &sss_rsakey_check_pair, + NULL, //&ax_rsakey_alloc, + &sss_rsakeypair_free_func, + NULL, //&ax_rsakey_debug, +}; + +const mbedtls_pk_info_t ax_mbedtls_rsapubkey_info = { + MBEDTLS_PK_RSA, + "AxRSA_pubkey", + &sss_rsakey_get_bitlen, + &sss_rsapubkey_can_do, + &sss_rsakey_verify, + NULL, + NULL, + NULL, + NULL, + NULL, + &sss_rsapubkey_free_func, + NULL, +}; + +static size_t sss_rsakey_get_bitlen(const void *ctx) +{ + mbedtls_rsa_context *pax_ctx = (mbedtls_rsa_context *)ctx; + return pax_ctx->len; +} + +static int sss_rsakey_verify(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + const unsigned char *sig, + size_t sig_len) +{ + sss_status_t status = kStatus_SSS_Success; + sss_asymmetric_t asymVerifyCtx; + sss_object_t *sssObject = NULL; + sss_algorithm_t algorithm; + mbedtls_rsa_context *pax_ctx = (mbedtls_rsa_context *)ctx; + + switch (md_alg) { + case MBEDTLS_MD_SHA1: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1; + break; + case MBEDTLS_MD_SHA224: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224; + break; + case MBEDTLS_MD_SHA256: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256; + break; + case MBEDTLS_MD_SHA384: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384; + break; + case MBEDTLS_MD_SHA512: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512; + break; + default: + return 1; + } + sssObject = (sss_object_t *)pax_ctx->pSSSObject; + + LOG_D("%s: Verify using key '0x%08lX'", __FUNCTION__, pax_ctx->pSSSObject->keyId); + + status = sss_asymmetric_context_init( + &asymVerifyCtx, sssObject->keyStore->session, sssObject, algorithm, kMode_SSS_Verify); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_context_init verify context Failed."); + return 1; + } + status = sss_asymmetric_verify_digest(&asymVerifyCtx, (uint8_t *)hash, hash_len, (uint8_t *)sig, sig_len); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_verify_digest Failed."); + return 1; + } + + return (0); +} + +static int sss_rsakey_sign(void *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len, + unsigned char *sig, + size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + int ret = 0; + size_t u16_sig_len = 1024; + sss_asymmetric_t asymVerifyCtx; + sss_status_t status = kStatus_SSS_Success; + sss_object_t *sssObject = NULL; + mbedtls_rsa_context *pax_ctx = NULL; + sss_algorithm_t algorithm; + + pax_ctx = (mbedtls_rsa_context *)ctx; + sssObject = (sss_object_t *)pax_ctx->pSSSObject; + + switch (md_alg) { + case MBEDTLS_MD_SHA1: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1; + break; + case MBEDTLS_MD_SHA224: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224; + break; + case MBEDTLS_MD_SHA256: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256; + break; + case MBEDTLS_MD_SHA384: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384; + break; + case MBEDTLS_MD_SHA512: + algorithm = kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512; + break; + default: + return 1; + } + + status = + sss_asymmetric_context_init(&asymVerifyCtx, sssObject->keyStore->session, sssObject, algorithm, kMode_SSS_Sign); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_context_init verify context Failed."); + return 1; + } + + LOG_D("%s: Signing using key '0x%08lX'", __FUNCTION__, pax_ctx->pSSSObject->keyId); + + status = sss_asymmetric_sign_digest(&asymVerifyCtx, (uint8_t *)hash, hash_len, sig, &u16_sig_len); + if (status != kStatus_SSS_Success) { + LOG_E(" sss_asymmetric_sign_digest failed."); + return 1; + } + + *sig_len = u16_sig_len; + + return (ret); +} + +static int sss_rsakey_check_pair(const void *pub, const void *prv) +{ + return 0; +} + +static int sss_rsakeypair_can_do(mbedtls_pk_type_t type) +{ + return (type == MBEDTLS_PK_RSA || type == MBEDTLS_PK_RSASSA_PSS); +} + +static int sss_rsapubkey_can_do(mbedtls_pk_type_t type) +{ + return (type == MBEDTLS_PK_RSA || type == MBEDTLS_PK_RSASSA_PSS); +} + +static void sss_rsakeypair_free_func(void *ctx) +{ + mbedtls_rsa_context *pax_ctx = (mbedtls_rsa_context *)ctx; + if (pax_ctx != NULL) { + mbedtls_free(ctx); + } + return; +} + +static void sss_rsapubkey_free_func(void *ctx) +{ + mbedtls_rsa_context *pax_ctx = (mbedtls_rsa_context *)ctx; + if (pax_ctx != NULL) { + mbedtls_free(ctx); + } + return; +} + +#endif /* MBEDTLS_RSA_ALT */ + +/** @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h new file mode 100644 index 00000000000..a312a7970eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h @@ -0,0 +1,3368 @@ +/** + * \file sss_mbedtls_x86_config.h + * + * \brief Configuration options (set of defines) + * + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ +/* + * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +#ifndef MBEDTLS_CONFIG_X86_H +#define MBEDTLS_CONFIG_X86_H + +/* clang-format off */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#ifdef CHECK_MEMORY + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE) +#define _CRT_SECURE_NO_DEPRECATE 1 +#endif + +#define MBEDTLS_PLATFORM_MEMORY + +void tstDoTraceAndFree( + const char * szWhat, + const char * szFunction, const unsigned int line, + void * pWhat ); + +void * tstDoTraceAndCalloc( + const char * szNUM, const char * szSize, + const char * szFunction, const unsigned int line, + const unsigned int num, const unsigned int size ); + +#define MBEDTLS_PLATFORM_FREE_MACRO(WHAT) \ + tstDoTraceAndFree(#WHAT, __FUNCTION__, __LINE__, WHAT ) +#define MBEDTLS_PLATFORM_CALLOC_MACRO(NUM, SIZE) \ + tstDoTraceAndCalloc(#NUM, #SIZE, __FUNCTION__, __LINE__, NUM, SIZE ) + +#define MBEDTLS_MEMORY_DEBUG +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +#endif /* CHECK_MEMORY */ + +/** + * \name SECTION: System support + * + * This section sets system specific settings. + * \{ + */ + +/** + * \def MBEDTLS_HAVE_ASM + * + * The compiler has support for asm(). + * + * Requires support for asm() in compiler. + * + * Used in: + * library/aria.c + * library/timing.c + * include/mbedtls/bn_mul.h + * + * Required by: + * MBEDTLS_AESNI_C + * MBEDTLS_PADLOCK_C + * + * Comment to disable the use of assembly code. + */ +#define MBEDTLS_HAVE_ASM + +/** + * \def MBEDTLS_NO_UDBL_DIVISION + * + * The platform lacks support for double-width integer division (64-bit + * division on a 32-bit platform, 128-bit division on a 64-bit platform). + * + * Used in: + * include/mbedtls/bignum.h + * library/bignum.c + * + * The bignum code uses double-width division to speed up some operations. + * Double-width division is often implemented in software that needs to + * be linked with the program. The presence of a double-width integer + * type is usually detected automatically through preprocessor macros, + * but the automatic detection cannot know whether the code needs to + * and can be linked with an implementation of division for that type. + * By default division is assumed to be usable if the type is present. + * Uncomment this option to prevent the use of double-width division. + * + * Note that division for the native integer type is always required. + * Furthermore, a 64-bit type is always required even on a 32-bit + * platform, but it need not support multiplication or division. In some + * cases it is also desirable to disable some double-width operations. For + * example, if double-width division is implemented in software, disabling + * it can reduce code size in some embedded targets. + */ +//#define MBEDTLS_NO_UDBL_DIVISION + +/** + * \def MBEDTLS_NO_64BIT_MULTIPLICATION + * + * The platform lacks support for 32x32 -> 64-bit multiplication. + * + * Used in: + * library/poly1305.c + * + * Some parts of the library may use multiplication of two unsigned 32-bit + * operands with a 64-bit result in order to speed up computations. On some + * platforms, this is not available in hardware and has to be implemented in + * software, usually in a library provided by the toolchain. + * + * Sometimes it is not desirable to have to link to that library. This option + * removes the dependency of that library on platforms that lack a hardware + * 64-bit multiplier by embedding a software implementation in Mbed TLS. + * + * Note that depending on the compiler, this may decrease performance compared + * to using the library function provided by the toolchain. + */ +//#define MBEDTLS_NO_64BIT_MULTIPLICATION + +/** + * \def MBEDTLS_HAVE_SSE2 + * + * CPU supports SSE2 instruction set. + * + * Uncomment if the CPU supports SSE2 (IA-32 specific). + */ +//#define MBEDTLS_HAVE_SSE2 + +/** + * \def MBEDTLS_HAVE_TIME + * + * System has time.h and time(). + * The time does not need to be correct, only time differences are used, + * by contrast with MBEDTLS_HAVE_TIME_DATE + * + * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, + * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and + * MBEDTLS_PLATFORM_STD_TIME. + * + * Comment if your system does not support time functions + */ +#define MBEDTLS_HAVE_TIME + +/** + * \def MBEDTLS_HAVE_TIME_DATE + * + * System has time.h, time(), and an implementation for + * mbedtls_platform_gmtime_r() (see below). + * The time needs to be correct (not necesarily very accurate, but at least + * the date should be correct). This is used to verify the validity period of + * X.509 certificates. + * + * Comment if your system does not have a correct clock. + * + * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that + * behaves similarly to the gmtime_r() function from the C standard. Refer to + * the documentation for mbedtls_platform_gmtime_r() for more information. + * + * \note It is possible to configure an implementation for + * mbedtls_platform_gmtime_r() at compile-time by using the macro + * MBEDTLS_PLATFORM_GMTIME_R_ALT. + */ +#define MBEDTLS_HAVE_TIME_DATE + +/** + * \def MBEDTLS_PLATFORM_MEMORY + * + * Enable the memory allocation layer. + * + * By default mbed TLS uses the system-provided calloc() and free(). + * This allows different allocators (self-implemented or provided) to be + * provided to the platform abstraction layer. + * + * Enabling MBEDTLS_PLATFORM_MEMORY without the + * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide + * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and + * free() function pointer at runtime. + * + * Enabling MBEDTLS_PLATFORM_MEMORY and specifying + * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the + * alternate function at compile time. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Enable this layer to allow use of alternative memory allocators. + */ +//#define MBEDTLS_PLATFORM_MEMORY + +/** + * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + * + * Do not assign standard functions in the platform layer (e.g. calloc() to + * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) + * + * This makes sure there are no linking errors on platforms that do not support + * these functions. You will HAVE to provide alternatives, either at runtime + * via the platform_set_xxx() functions or at compile time by setting + * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a + * MBEDTLS_PLATFORM_XXX_MACRO. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Uncomment to prevent default assignment of standard functions in the + * platform layer. + */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +/** + * \def MBEDTLS_PLATFORM_EXIT_ALT + * + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the + * function in the platform abstraction layer. + * + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will + * provide a function "mbedtls_platform_set_printf()" that allows you to set an + * alternative printf function pointer. + * + * All these define require MBEDTLS_PLATFORM_C to be defined! + * + * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; + * it will be enabled automatically by check_config.h + * + * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as + * MBEDTLS_PLATFORM_XXX_MACRO! + * + * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME + * + * Uncomment a macro to enable alternate implementation of specific base + * platform function + */ +//#define MBEDTLS_PLATFORM_EXIT_ALT +//#define MBEDTLS_PLATFORM_TIME_ALT +//#define MBEDTLS_PLATFORM_FPRINTF_ALT +//#define MBEDTLS_PLATFORM_PRINTF_ALT +//#define MBEDTLS_PLATFORM_SNPRINTF_ALT +//#define MBEDTLS_PLATFORM_NV_SEED_ALT +//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT + +/** + * \def MBEDTLS_DEPRECATED_WARNING + * + * Mark deprecated functions so that they generate a warning if used. + * Functions deprecated in one version will usually be removed in the next + * version. You can enable this to help you prepare the transition to a new + * major version by making sure your code is not using these functions. + * + * This only works with GCC and Clang. With other compilers, you may want to + * use MBEDTLS_DEPRECATED_REMOVED + * + * Uncomment to get warnings on using deprecated functions. + */ +//#define MBEDTLS_DEPRECATED_WARNING + +/** + * \def MBEDTLS_DEPRECATED_REMOVED + * + * Remove deprecated functions so that they generate an error if used. + * Functions deprecated in one version will usually be removed in the next + * version. You can enable this to help you prepare the transition to a new + * major version by making sure your code is not using these functions. + * + * Uncomment to get errors on using deprecated functions. + */ +//#define MBEDTLS_DEPRECATED_REMOVED + +/** + * \def MBEDTLS_CHECK_PARAMS + * + * This configuration option controls whether the library validates more of + * the parameters passed to it. + * + * When this flag is not defined, the library only attempts to validate an + * input parameter if: (1) they may come from the outside world (such as the + * network, the filesystem, etc.) or (2) not validating them could result in + * internal memory errors such as overflowing a buffer controlled by the + * library. On the other hand, it doesn't attempt to validate parameters whose + * values are fully controlled by the application (such as pointers). + * + * When this flag is defined, the library additionally attempts to validate + * parameters that are fully controlled by the application, and should always + * be valid if the application code is fully correct and trusted. + * + * For example, when a function accepts as input a pointer to a buffer that may + * contain untrusted data, and its documentation mentions that this pointer + * must not be NULL: + * - the pointer is checked to be non-NULL only if this option is enabled + * - the content of the buffer is always validated + * + * When this flag is defined, if a library function receives a parameter that + * is invalid, it will: + * - invoke the macro MBEDTLS_PARAM_FAILED() which by default expands to a + * call to the function mbedtls_param_failed() + * - immediately return (with a specific error code unless the function + * returns void and can't communicate an error). + * + * When defining this flag, you also need to: + * - either provide a definition of the function mbedtls_param_failed() in + * your application (see platform_util.h for its prototype) as the library + * calls that function, but does not provide a default definition for it, + * - or provide a different definition of the macro MBEDTLS_PARAM_FAILED() + * below if the above mechanism is not flexible enough to suit your needs. + * See the documentation of this macro later in this file. + * + * Uncomment to enable validation of application-controlled parameters. + */ +//#define MBEDTLS_CHECK_PARAMS + +/* \} name SECTION: System support */ + +/** + * \name SECTION: mbed TLS feature support + * + * This section sets support for features that are or are not needed + * within the modules that are enabled. + * \{ + */ + +/** + * \def MBEDTLS_TIMING_ALT + * + * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(), + * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() + * + * Only works if you have MBEDTLS_TIMING_C enabled. + * + * You will need to provide a header "timing_alt.h" and an implementation at + * compile time. + */ +//#define MBEDTLS_TIMING_ALT + +/** + * \def MBEDTLS_AES_ALT + * + * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternate core implementation of a symmetric crypto, an arithmetic or hash + * module (e.g. platform specific assembly optimized implementations). Keep + * in mind that the function prototypes should remain the same. + * + * This replaces the whole module. If you only want to replace one of the + * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer + * provide the "struct mbedtls_aes_context" definition and omit the base + * function declarations and implementations. "aes_alt.h" will be included from + * "aes.h" to include the new function definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * module. + * + * \warning MD2, MD4, MD5, ARC4, DES and SHA-1 are considered weak and their + * use constitutes a security risk. If possible, we recommend + * avoiding dependencies on them, and considering stronger message + * digests and ciphers instead. + * + */ +//#define MBEDTLS_AES_ALT +//#define MBEDTLS_ARC4_ALT +//#define MBEDTLS_ARIA_ALT +//#define MBEDTLS_BLOWFISH_ALT +//#define MBEDTLS_CAMELLIA_ALT +//#define MBEDTLS_CCM_ALT +//#define MBEDTLS_CHACHA20_ALT +//#define MBEDTLS_CHACHAPOLY_ALT +//#define MBEDTLS_CMAC_ALT +//#define MBEDTLS_DES_ALT +//#define MBEDTLS_DHM_ALT +//#define MBEDTLS_ECJPAKE_ALT +//#define MBEDTLS_GCM_ALT +//#define MBEDTLS_NIST_KW_ALT +//#define MBEDTLS_MD2_ALT +//#define MBEDTLS_MD4_ALT +//#define MBEDTLS_MD5_ALT +//#define MBEDTLS_POLY1305_ALT +//#define MBEDTLS_RIPEMD160_ALT +//#define MBEDTLS_RSA_ALT +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT +//#define MBEDTLS_XTEA_ALT + +/* + * When replacing the elliptic curve module, pleace consider, that it is + * implemented with two .c files: + * - ecp.c + * - ecp_curves.c + * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT + * macros as described above. The only difference is that you have to make sure + * that you provide functionality for both .c files. + */ + +#if defined(SSS_HAVE_ALT) && (SSS_HAVE_ALT) +# define MBEDTLS_ECP_ALT +# define MBEDTLS_RSA_ALT +#endif /* SSS_HAVE_ALT */ +//#define MBEDTLS_ECP_ALT + + +/** + * - MBEDTLS_ECDSA_VERIFY_ALT + * To use SE for all public key ecdsa verify operation, enable MBEDTLS_ECDSA_VERIFY_ALT + */ + +#if defined(SSS_HAVE_ALT) && (SSS_HAVE_ALT) +# define MBEDTLS_ECDH_ALT +# define MBEDTLS_ECDH_GEN_PUBLIC_ALT +# define MBEDTLS_ECDH_COMPUTE_SHARED_ALT +//# define MBEDTLS_ECDSA_VERIFY_ALT +#endif /* SSS_HAVE_ALT */ +//#define MBEDTLS_ECDH_ALT + +/** + * \def MBEDTLS_MD2_PROCESS_ALT + * + * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you + * alternate core implementation of symmetric crypto or hash function. Keep in + * mind that function prototypes should remain the same. + * + * This replaces only one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will + * no longer provide the mbedtls_sha1_process() function, but it will still provide + * the other function (using your mbedtls_sha1_process() function) and the definition + * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible + * with this definition. + * + * \note Because of a signature change, the core AES encryption and decryption routines are + * currently named mbedtls_aes_internal_encrypt and mbedtls_aes_internal_decrypt, + * respectively. When setting up alternative implementations, these functions should + * be overriden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt + * must stay untouched. + * + * \note If you use the AES_xxx_ALT macros, then is is recommended to also set + * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES + * tables. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + * + * \warning MD2, MD4, MD5, DES and SHA-1 are considered weak and their use + * constitutes a security risk. If possible, we recommend avoiding + * dependencies on them, and considering stronger message digests + * and ciphers instead. + * + */ +//#define MBEDTLS_MD2_PROCESS_ALT +//#define MBEDTLS_MD4_PROCESS_ALT +//#define MBEDTLS_MD5_PROCESS_ALT +//#define MBEDTLS_RIPEMD160_PROCESS_ALT +//#define MBEDTLS_SHA1_PROCESS_ALT +//#define MBEDTLS_SHA256_PROCESS_ALT +//#define MBEDTLS_SHA512_PROCESS_ALT +//#define MBEDTLS_DES_SETKEY_ALT +//#define MBEDTLS_DES_CRYPT_ECB_ALT +//#define MBEDTLS_DES3_CRYPT_ECB_ALT +//#define MBEDTLS_AES_SETKEY_ENC_ALT +//#define MBEDTLS_AES_SETKEY_DEC_ALT +//#define MBEDTLS_AES_ENCRYPT_ALT +//#define MBEDTLS_AES_DECRYPT_ALT +//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT +//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT +//#define MBEDTLS_ECDSA_VERIFY_ALT +//#define MBEDTLS_ECDSA_SIGN_ALT +//#define MBEDTLS_ECDSA_GENKEY_ALT + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * + * Expose a part of the internal interface of the Elliptic Curve Point module. + * + * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternative core implementation of elliptic curve arithmetic. Keep in mind + * that function prototypes should remain the same. + * + * This partially replaces one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation + * is still present and it is used for group structures not supported by the + * alternative. + * + * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT + * and implementing the following functions: + * unsigned char mbedtls_internal_ecp_grp_capable( + * const mbedtls_ecp_group *grp ) + * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) + * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) + * The mbedtls_internal_ecp_grp_capable function should return 1 if the + * replacement functions implement arithmetic for the given group and 0 + * otherwise. + * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are + * called before and after each point operation and provide an opportunity to + * implement optimized set up and tear down instructions. + * + * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and + * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac + * function, but will use your mbedtls_internal_ecp_double_jac if the group is + * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when + * receives it as an argument). If the group is not supported then the original + * implementation is used. The other functions and the definition of + * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your + * implementation of mbedtls_internal_ecp_double_jac and + * mbedtls_internal_ecp_grp_capable must be compatible with this definition. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + */ +/* Required for all the functions in this section */ +//#define MBEDTLS_ECP_INTERNAL_ALT +/* Support for Weierstrass curves with Jacobi representation */ +//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +//#define MBEDTLS_ECP_ADD_MIXED_ALT +//#define MBEDTLS_ECP_DOUBLE_JAC_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +/* Support for curves with Montgomery arithmetic */ +//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT +//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT +//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT + +/** + * \def MBEDTLS_TEST_NULL_ENTROPY + * + * Enables testing and use of mbed TLS without any configured entropy sources. + * This permits use of the library on platforms before an entropy source has + * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the + * MBEDTLS_ENTROPY_NV_SEED switches). + * + * WARNING! This switch MUST be disabled in production builds, and is suitable + * only for development. + * Enabling the switch negates any security provided by the library. + * + * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + */ +//#define MBEDTLS_TEST_NULL_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_HARDWARE_ALT + * + * Uncomment this macro to let mbed TLS use your own implementation of a + * hardware entropy collector. + * + * Your function must be called \c mbedtls_hardware_poll(), have the same + * prototype as declared in entropy_poll.h, and accept NULL as first argument. + * + * Uncomment to use your own hardware entropy collector. + */ +//#define MBEDTLS_ENTROPY_HARDWARE_ALT + +/** + * \def MBEDTLS_AES_ROM_TABLES + * + * Use precomputed AES tables stored in ROM. + * + * Uncomment this macro to use precomputed AES tables stored in ROM. + * Comment this macro to generate AES tables in RAM at runtime. + * + * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb + * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the + * initialization time before the first AES operation can be performed. + * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c + * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded + * performance if ROM access is slower than RAM access. + * + * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. + * + */ +//#define MBEDTLS_AES_ROM_TABLES + +/** + * \def MBEDTLS_AES_FEWER_TABLES + * + * Use less ROM/RAM for AES tables. + * + * Uncommenting this macro omits 75% of the AES tables from + * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) + * by computing their values on the fly during operations + * (the tables are entry-wise rotations of one another). + * + * Tradeoff: Uncommenting this reduces the RAM / ROM footprint + * by ~6kb but at the cost of more arithmetic operations during + * runtime. Specifically, one has to compare 4 accesses within + * different tables to 4 accesses with additional arithmetic + * operations within the same table. The performance gain/loss + * depends on the system and memory details. + * + * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + * + */ +//#define MBEDTLS_AES_FEWER_TABLES + +/** + * \def MBEDTLS_CAMELLIA_SMALL_MEMORY + * + * Use less ROM for the Camellia implementation (saves about 768 bytes). + * + * Uncomment this macro to use less memory for Camellia. + */ +//#define MBEDTLS_CAMELLIA_SMALL_MEMORY + +/** + * \def MBEDTLS_CIPHER_MODE_CBC + * + * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CBC + +/** + * \def MBEDTLS_CIPHER_MODE_CFB + * + * Enable Cipher Feedback mode (CFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CFB + +/** + * \def MBEDTLS_CIPHER_MODE_CTR + * + * Enable Counter Block Cipher mode (CTR) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CTR + +/** + * \def MBEDTLS_CIPHER_MODE_OFB + * + * Enable Output Feedback mode (OFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_OFB + +/** + * \def MBEDTLS_CIPHER_MODE_XTS + * + * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES. + */ +#define MBEDTLS_CIPHER_MODE_XTS + +/** + * \def MBEDTLS_CIPHER_NULL_CIPHER + * + * Enable NULL cipher. + * Warning: Only do so when you know what you are doing. This allows for + * encryption or channels without any security! + * + * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable + * the following ciphersuites: + * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA + * + * Uncomment this macro to enable the NULL cipher and ciphersuites + */ +//#define MBEDTLS_CIPHER_NULL_CIPHER + +/** + * \def MBEDTLS_CIPHER_PADDING_PKCS7 + * + * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for + * specific padding modes in the cipher layer with cipher modes that support + * padding (e.g. CBC) + * + * If you disable all padding modes, only full blocks can be used with CBC. + * + * Enable padding modes in the cipher layer. + */ +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS + +/** + * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES + * + * Enable weak ciphersuites in SSL / TLS. + * Warning: Only do so when you know what you are doing. This allows for + * channels with virtually no security at all! + * + * This enables the following ciphersuites: + * MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA + * + * Uncomment this macro to enable weak ciphersuites + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES + +/** + * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES + * + * Remove RC4 ciphersuites by default in SSL / TLS. + * This flag removes the ciphersuites based on RC4 from the default list as + * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to + * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them + * explicitly. + * + * Uncomment this macro to remove RC4 ciphersuites by default. + */ +#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES + +/** + * \def MBEDTLS_REMOVE_3DES_CIPHERSUITES + * + * Remove 3DES ciphersuites by default in SSL / TLS. + * This flag removes the ciphersuites based on 3DES from the default list as + * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible + * to enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including + * them explicitly. + * + * A man-in-the-browser attacker can recover authentication tokens sent through + * a TLS connection using a 3DES based cipher suite (see "On the Practical + * (In-)Security of 64-bit Block Ciphers" by Karthikeyan Bhargavan and Gaëtan + * Leurent, see https://sweet32.info/SWEET32_CCS16.pdf). If this attack falls + * in your threat model or you are unsure, then you should keep this option + * enabled to remove 3DES based cipher suites. + * + * Comment this macro to keep 3DES in the default ciphersuite list. + */ +#define MBEDTLS_REMOVE_3DES_CIPHERSUITES + +/** + * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED + * + * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve + * module. By default all supported curves are enabled. + * + * Comment macros to disable the curve and functions for it + */ +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_CURVE448_ENABLED + +#ifdef TGT_A71CH +# undef MBEDTLS_ECP_DP_SECP192R1_ENABLED +# undef MBEDTLS_ECP_DP_SECP224R1_ENABLED +# undef MBEDTLS_ECP_DP_SECP384R1_ENABLED +# undef MBEDTLS_ECP_DP_SECP521R1_ENABLED +# undef MBEDTLS_ECP_DP_SECP192K1_ENABLED +# undef MBEDTLS_ECP_DP_SECP224K1_ENABLED +# undef MBEDTLS_ECP_DP_SECP256K1_ENABLED +# undef MBEDTLS_ECP_DP_BP256R1_ENABLED +# undef MBEDTLS_ECP_DP_BP384R1_ENABLED +# undef MBEDTLS_ECP_DP_BP512R1_ENABLED +# undef MBEDTLS_ECP_DP_CURVE25519_ENABLED +# undef MBEDTLS_ECP_DP_CURVE448_ENABLED +#endif + + +/** + * \def MBEDTLS_ECP_NIST_OPTIM + * + * Enable specific 'modulo p' routines for each NIST prime. + * Depending on the prime and architecture, makes operations 4 to 8 times + * faster on the corresponding curve. + * + * Comment this macro to disable NIST curves optimisation. + */ +#define MBEDTLS_ECP_NIST_OPTIM + +/** + * \def MBEDTLS_ECP_RESTARTABLE + * + * Enable "non-blocking" ECC operations that can return early and be resumed. + * + * This allows various functions to pause by returning + * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module, + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in + * order to further progress and eventually complete their operation. This is + * controlled through mbedtls_ecp_set_max_ops() which limits the maximum + * number of ECC operations a function may perform before pausing; see + * mbedtls_ecp_set_max_ops() for more information. + * + * This is useful in non-threaded environments if you want to avoid blocking + * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. + * + * Uncomment this macro to enable restartable ECC computations. + * + * \note This option only works with the default software implementation of + * elliptic curve functionality. It is incompatible with + * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT and MBEDTLS_ECDSA_XXX_ALT. + */ +//#define MBEDTLS_ECP_RESTARTABLE + +/** + * \def MBEDTLS_ECDSA_DETERMINISTIC + * + * Enable deterministic ECDSA (RFC 6979). + * Standard ECDSA is "fragile" in the sense that lack of entropy when signing + * may result in a compromise of the long-term signing key. This is avoided by + * the deterministic variant. + * + * Requires: MBEDTLS_HMAC_DRBG_C + * + * Comment this macro to disable deterministic ECDSA. + */ +#define MBEDTLS_ECDSA_DETERMINISTIC + +/** + * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + * + * Enable the PSK based ciphersuite modes in SSL / TLS. + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + * + * Enable the DHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + * + * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + * + * Enable the RSA-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + * + * Enable the RSA-only based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5 + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + * + * Enable the DHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + * + * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + * + * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C, + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + * + * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + * + * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + * + * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Requires: MBEDTLS_ECJPAKE_C + * MBEDTLS_SHA256_C + * MBEDTLS_ECP_DP_SECP256R1_ENABLED + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + */ +//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + +/** + * \def MBEDTLS_PK_PARSE_EC_EXTENDED + * + * Enhance support for reading EC keys using variants of SEC1 not allowed by + * RFC 5915 and RFC 5480. + * + * Currently this means parsing the SpecifiedECDomain choice of EC + * parameters (only known groups are supported, not arbitrary domains, to + * avoid validation issues). + * + * Disable if you only need to support RFC 5915 + 5480 key formats. + */ +#define MBEDTLS_PK_PARSE_EC_EXTENDED + +/** + * \def MBEDTLS_ERROR_STRERROR_DUMMY + * + * Enable a dummy error function to make use of mbedtls_strerror() in + * third party libraries easier when MBEDTLS_ERROR_C is disabled + * (no effect when MBEDTLS_ERROR_C is enabled). + * + * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're + * not using mbedtls_strerror() or error_strerror() in your application. + * + * Disable if you run into name conflicts and want to really remove the + * mbedtls_strerror() + */ +#define MBEDTLS_ERROR_STRERROR_DUMMY + +/** + * \def MBEDTLS_GENPRIME + * + * Enable the prime-number generation code. + * + * Requires: MBEDTLS_BIGNUM_C + */ +#define MBEDTLS_GENPRIME + +/** + * \def MBEDTLS_FS_IO + * + * Enable functions that use the filesystem. + */ +#define MBEDTLS_FS_IO + +/** + * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + * Do not add default entropy sources. These are the platform specific, + * mbedtls_timing_hardclock and HAVEGE based poll functions. + * + * This is useful to have more control over the added entropy sources in an + * application. + * + * Uncomment this macro to prevent loading of default entropy functions. + */ +//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + +/** + * \def MBEDTLS_NO_PLATFORM_ENTROPY + * + * Do not use built-in platform entropy functions. + * This is useful if your platform does not support + * standards like the /dev/urandom or Windows CryptoAPI. + * + * Uncomment this macro to disable the built-in platform entropy functions. + */ +//#define MBEDTLS_NO_PLATFORM_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_FORCE_SHA256 + * + * Force the entropy accumulator to use a SHA-256 accumulator instead of the + * default SHA-512 based one (if both are available). + * + * Requires: MBEDTLS_SHA256_C + * + * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option + * if you have performance concerns. + * + * This option is only useful if both MBEDTLS_SHA256_C and + * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. + */ +//#define MBEDTLS_ENTROPY_FORCE_SHA256 + +/** + * \def MBEDTLS_ENTROPY_NV_SEED + * + * Enable the non-volatile (NV) seed file-based entropy source. + * (Also enables the NV seed read/write functions in the platform layer) + * + * This is crucial (if not required) on systems that do not have a + * cryptographic entropy source (in hardware or kernel) available. + * + * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C + * + * \note The read/write functions that are used by the entropy source are + * determined in the platform layer, and can be modified at runtime and/or + * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. + * + * \note If you use the default implementation functions that read a seedfile + * with regular fopen(), please make sure you make a seedfile with the + * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at + * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from + * and written to or you will get an entropy source error! The default + * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE + * bytes from the file. + * + * \note The entropy collector will write to the seed file before entropy is + * given to an external source, to update it. + */ +//#define MBEDTLS_ENTROPY_NV_SEED + +/** + * \def MBEDTLS_MEMORY_DEBUG + * + * Enable debugging of buffer allocator memory issues. Automatically prints + * (to stderr) all (fatal) messages on memory allocation issues. Enables + * function for 'debug output' of allocated memory. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Uncomment this macro to let the buffer allocator print out error messages. + */ +//#define MBEDTLS_MEMORY_DEBUG + +/** + * \def MBEDTLS_MEMORY_BACKTRACE + * + * Include backtrace information with each allocated block. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * GLIBC-compatible backtrace() an backtrace_symbols() support + * + * Uncomment this macro to include backtrace information + */ +//#define MBEDTLS_MEMORY_BACKTRACE + +/** + * \def MBEDTLS_PK_RSA_ALT_SUPPORT + * + * Support external private RSA keys (eg from a HSM) in the PK layer. + * + * Comment this macro to disable support for external private RSA keys. + */ +#define MBEDTLS_PK_RSA_ALT_SUPPORT + +/** + * \def MBEDTLS_PKCS1_V15 + * + * Enable support for PKCS#1 v1.5 encoding. + * + * Requires: MBEDTLS_RSA_C + * + * This enables support for PKCS#1 v1.5 operations. + */ +#define MBEDTLS_PKCS1_V15 + +/** + * \def MBEDTLS_PKCS1_V21 + * + * Enable support for PKCS#1 v2.1 encoding. + * + * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C + * + * This enables support for RSAES-OAEP and RSASSA-PSS operations. + */ +#define MBEDTLS_PKCS1_V21 + +/** + * \def MBEDTLS_RSA_NO_CRT + * + * Do not use the Chinese Remainder Theorem + * for the RSA private operation. + * + * Uncomment this macro to disable the use of CRT in RSA. + * + */ +//#define MBEDTLS_RSA_NO_CRT + +/** + * \def MBEDTLS_SELF_TEST + * + * Enable the checkup functions (*_self_test). + */ +//#define MBEDTLS_SELF_TEST + +/** + * \def MBEDTLS_SHA256_SMALLER + * + * Enable an implementation of SHA-256 that has lower ROM footprint but also + * lower performance. + * + * The default implementation is meant to be a reasonnable compromise between + * performance and size. This version optimizes more aggressively for size at + * the expense of performance. Eg on Cortex-M4 it reduces the size of + * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about + * 30%. + * + * Uncomment to enable the smaller implementation of SHA256. + */ +//#define MBEDTLS_SHA256_SMALLER + +/** + * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES + * + * Enable sending of alert messages in case of encountered errors as per RFC. + * If you choose not to send the alert messages, mbed TLS can still communicate + * with other servers, only debugging of failures is harder. + * + * The advantage of not sending alert messages, is that no information is given + * about reasons for failures thus preventing adversaries of gaining intel. + * + * Enable sending of all alert messages + */ +#define MBEDTLS_SSL_ALL_ALERT_MESSAGES + +/** + * \def MBEDTLS_SSL_ASYNC_PRIVATE + * + * Enable asynchronous external private key operations in SSL. This allows + * you to configure an SSL connection to call an external cryptographic + * module to perform private key operations instead of performing the + * operation inside the library. + * + */ +//#define MBEDTLS_SSL_ASYNC_PRIVATE + +/** + * \def MBEDTLS_SSL_DEBUG_ALL + * + * Enable the debug messages in SSL module for all issues. + * Debug messages have been disabled in some places to prevent timing + * attacks due to (unbalanced) debugging function calls. + * + * If you need all error reporting you should enable this during debugging, + * but remove this for production servers that should log as well. + * + * Uncomment this macro to report all debug messages on errors introducing + * a timing side-channel. + * + */ +//#define MBEDTLS_SSL_DEBUG_ALL + +/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC + * + * Enable support for Encrypt-then-MAC, RFC 7366. + * + * This allows peers that both support it to use a more robust protection for + * ciphersuites using CBC, providing deep resistance against timing attacks + * on the padding or underlying cipher. + * + * This only affects CBC ciphersuites, and is useless if none is defined. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1 or + * MBEDTLS_SSL_PROTO_TLS1_1 or + * MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Encrypt-then-MAC + */ +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC + +/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET + * + * Enable support for Extended Master Secret, aka Session Hash + * (draft-ietf-tls-session-hash-02). + * + * This was introduced as "the proper fix" to the Triple Handshake familiy of + * attacks, but it is recommended to always use it (even if you disable + * renegotiation), since it actually fixes a more fundamental issue in the + * original SSL/TLS design, and has implications beyond Triple Handshake. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1 or + * MBEDTLS_SSL_PROTO_TLS1_1 or + * MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Extended Master Secret. + */ +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET + +/** + * \def MBEDTLS_SSL_FALLBACK_SCSV + * + * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00). + * + * For servers, it is recommended to always enable this, unless you support + * only one version of TLS, or know for sure that none of your clients + * implements a fallback strategy. + * + * For clients, you only need this if you're using a fallback strategy, which + * is not recommended in the first place, unless you absolutely need it to + * interoperate with buggy (version-intolerant) servers. + * + * Comment this macro to disable support for FALLBACK_SCSV + */ +#define MBEDTLS_SSL_FALLBACK_SCSV + +/** + * \def MBEDTLS_SSL_HW_RECORD_ACCEL + * + * Enable hooking functions in SSL module for hardware acceleration of + * individual records. + * + * Uncomment this macro to enable hooking functions. + */ +//#define MBEDTLS_SSL_HW_RECORD_ACCEL + +/** + * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING + * + * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0. + * + * This is a countermeasure to the BEAST attack, which also minimizes the risk + * of interoperability issues compared to sending 0-length records. + * + * Comment this macro to disable 1/n-1 record splitting. + */ +#define MBEDTLS_SSL_CBC_RECORD_SPLITTING + +/** + * \def MBEDTLS_SSL_RENEGOTIATION + * + * Enable support for TLS renegotiation. + * + * The two main uses of renegotiation are (1) refresh keys on long-lived + * connections and (2) client authentication after the initial handshake. + * If you don't need renegotiation, it's probably better to disable it, since + * it has been associated with security issues in the past and is easy to + * misuse/misunderstand. + * + * Comment this to disable support for renegotiation. + * + * \note Even if this option is disabled, both client and server are aware + * of the Renegotiation Indication Extension (RFC 5746) used to + * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). + * (See \c mbedtls_ssl_conf_legacy_renegotiation for the + * configuration of this extension). + * + */ +#define MBEDTLS_SSL_RENEGOTIATION + +/** + * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO + * + * Enable support for receiving and parsing SSLv2 Client Hello messages for the + * SSL Server module (MBEDTLS_SSL_SRV_C). + * + * Uncomment this macro to enable support for SSLv2 Client Hello messages. + */ +//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO + +/** + * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE + * + * Pick the ciphersuite according to the client's preferences rather than ours + * in the SSL Server module (MBEDTLS_SSL_SRV_C). + * + * Uncomment this macro to respect client's ciphersuite order + */ +//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE + +/** + * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + * + * Enable support for RFC 6066 max_fragment_length extension in SSL. + * + * Comment this macro to disable support for the max_fragment_length extension + */ +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/** + * \def MBEDTLS_SSL_PROTO_SSL3 + * + * Enable support for SSL 3.0. + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for SSL 3.0 + */ +//#define MBEDTLS_SSL_PROTO_SSL3 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1 + * + * Enable support for TLS 1.0. + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for TLS 1.0 + */ +#define MBEDTLS_SSL_PROTO_TLS1 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_1 + * + * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled). + * + * Requires: MBEDTLS_MD5_C + * MBEDTLS_SHA1_C + * + * Comment this macro to disable support for TLS 1.1 / DTLS 1.0 + */ +#define MBEDTLS_SSL_PROTO_TLS1_1 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_2 + * + * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). + * + * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C + * (Depends on ciphersuites) + * + * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 + */ +#define MBEDTLS_SSL_PROTO_TLS1_2 + +/** + * \def MBEDTLS_SSL_PROTO_DTLS + * + * Enable support for DTLS (all available versions). + * + * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0, + * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_1 + * or MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for DTLS + */ +#define MBEDTLS_SSL_PROTO_DTLS + +/** + * \def MBEDTLS_SSL_ALPN + * + * Enable support for RFC 7301 Application Layer Protocol Negotiation. + * + * Comment this macro to disable support for ALPN. + */ +#define MBEDTLS_SSL_ALPN + +/** + * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY + * + * Enable support for the anti-replay mechanism in DTLS. + * + * Requires: MBEDTLS_SSL_TLS_C + * MBEDTLS_SSL_PROTO_DTLS + * + * \warning Disabling this is often a security risk! + * See mbedtls_ssl_conf_dtls_anti_replay() for details. + * + * Comment this to disable anti-replay in DTLS. + */ +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY + +/** + * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Enable support for HelloVerifyRequest on DTLS servers. + * + * This feature is highly recommended to prevent DTLS servers being used as + * amplifiers in DoS attacks against other hosts. It should always be enabled + * unless you know for sure amplification cannot be a problem in the + * environment in which your server operates. + * + * \warning Disabling this can ba a security risk! (see above) + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Comment this to disable support for HelloVerifyRequest. + */ +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY + +/** + * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + * + * Enable server-side support for clients that reconnect from the same port. + * + * Some clients unexpectedly close the connection and try to reconnect using the + * same source port. This needs special support from the server to handle the + * new connection securely, as described in section 4.2.8 of RFC 6347. This + * flag enables that support. + * + * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Comment this to disable support for clients reusing the source port. + */ +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + +/** + * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT + * + * Enable support for a limit of records with bad MAC. + * + * See mbedtls_ssl_conf_dtls_badmac_limit(). + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + */ +#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT + +/** + * \def MBEDTLS_SSL_SESSION_TICKETS + * + * Enable support for RFC 5077 session tickets in SSL. + * Client-side, provides full support for session tickets (maintainance of a + * session store remains the responsibility of the application, though). + * Server-side, you also need to provide callbacks for writing and parsing + * tickets, including authenticated encryption and key management. Example + * callbacks are provided by MBEDTLS_SSL_TICKET_C. + * + * Comment this macro to disable support for SSL session tickets + */ +#define MBEDTLS_SSL_SESSION_TICKETS + +/** + * \def MBEDTLS_SSL_EXPORT_KEYS + * + * Enable support for exporting key block and master secret. + * This is required for certain users of TLS, e.g. EAP-TLS. + * + * Comment this macro to disable support for key export + */ +#define MBEDTLS_SSL_EXPORT_KEYS + +/** + * \def MBEDTLS_SSL_SERVER_NAME_INDICATION + * + * Enable support for RFC 6066 server name indication (SNI) in SSL. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Comment this macro to disable support for server name indication in SSL + */ +#define MBEDTLS_SSL_SERVER_NAME_INDICATION + +/** + * \def MBEDTLS_SSL_TRUNCATED_HMAC + * + * Enable support for RFC 6066 truncated HMAC in SSL. + * + * Comment this macro to disable support for truncated HMAC in SSL + */ +#define MBEDTLS_SSL_TRUNCATED_HMAC + +/** + * \def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT + * + * Fallback to old (pre-2.7), non-conforming implementation of the truncated + * HMAC extension which also truncates the HMAC key. Note that this option is + * only meant for a transitory upgrade period and is likely to be removed in + * a future version of the library. + * + * \warning The old implementation is non-compliant and has a security weakness + * (2^80 brute force attack on the HMAC key used for a single, + * uninterrupted connection). This should only be enabled temporarily + * when (1) the use of truncated HMAC is essential in order to save + * bandwidth, and (2) the peer is an Mbed TLS stack that doesn't use + * the fixed implementation yet (pre-2.7). + * + * \deprecated This option is deprecated and will likely be removed in a + * future version of Mbed TLS. + * + * Uncomment to fallback to old, non-compliant truncated HMAC implementation. + * + * Requires: MBEDTLS_SSL_TRUNCATED_HMAC + */ +//#define MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT + +/** + * \def MBEDTLS_THREADING_ALT + * + * Provide your own alternate threading implementation. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to allow your own alternate threading implementation. + */ +//#define MBEDTLS_THREADING_ALT + +/** + * \def MBEDTLS_THREADING_PTHREAD + * + * Enable the pthread wrapper layer for the threading layer. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to enable pthread mutexes. + */ +//#define MBEDTLS_THREADING_PTHREAD + +/** + * \def MBEDTLS_VERSION_FEATURES + * + * Allow run-time checking of compile-time enabled features. Thus allowing users + * to check at run-time if the library is for instance compiled with threading + * support via mbedtls_version_check_feature(). + * + * Requires: MBEDTLS_VERSION_C + * + * Comment this to disable run-time checking and save ROM space + */ +#define MBEDTLS_VERSION_FEATURES + +/** + * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 + * + * If set, the X509 parser will not break-off when parsing an X509 certificate + * and encountering an extension in a v1 or v2 certificate. + * + * Uncomment to prevent an error. + */ +//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 + +/** + * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION + * + * If set, the X509 parser will not break-off when parsing an X509 certificate + * and encountering an unknown critical extension. + * + * \warning Depending on your PKI use, enabling this can be a security risk! + * + * Uncomment to prevent an error. + */ +//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION + +/** + * \def MBEDTLS_X509_CHECK_KEY_USAGE + * + * Enable verification of the keyUsage extension (CA and leaf certificates). + * + * Disabling this avoids problems with mis-issued and/or misused + * (intermediate) CA and leaf certificates. + * + * \warning Depending on your PKI use, disabling this can be a security risk! + * + * Comment to skip keyUsage checking for both CA and leaf certificates. + */ +#define MBEDTLS_X509_CHECK_KEY_USAGE + +/** + * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + * + * Enable verification of the extendedKeyUsage extension (leaf certificates). + * + * Disabling this avoids problems with mis-issued and/or misused certificates. + * + * \warning Depending on your PKI use, disabling this can be a security risk! + * + * Comment to skip extendedKeyUsage checking for certificates. + */ +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + +/** + * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT + * + * Enable parsing and verification of X.509 certificates, CRLs and CSRS + * signed with RSASSA-PSS (aka PKCS#1 v2.1). + * + * Comment this macro to disallow using RSASSA-PSS in certificates. + */ +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT + +/** + * \def MBEDTLS_ZLIB_SUPPORT + * + * If set, the SSL/TLS module uses ZLIB to support compression and + * decompression of packet data. + * + * \warning TLS-level compression MAY REDUCE SECURITY! See for example the + * CRIME attack. Before enabling this option, you should examine with care if + * CRIME or similar exploits may be a applicable to your use case. + * + * \note Currently compression can't be used with DTLS. + * + * \deprecated This feature is deprecated and will be removed + * in the next major revision of the library. + * + * Used in: library/ssl_tls.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * This feature requires zlib library and headers to be present. + * + * Uncomment to enable use of ZLIB + */ +//#define MBEDTLS_ZLIB_SUPPORT +/* \} name SECTION: mbed TLS feature support */ + +/** + * \name SECTION: mbed TLS modules + * + * This section enables or disables entire modules in mbed TLS + * \{ + */ + +/** + * \def MBEDTLS_AESNI_C + * + * Enable AES-NI support on x86-64. + * + * Module: library/aesni.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the AES-NI instructions on x86-64 + */ +#define MBEDTLS_AESNI_C + +/** + * \def MBEDTLS_AES_C + * + * Enable the AES block cipher. + * + * Module: library/aes.c + * Caller: library/cipher.c + * library/pem.c + * library/ctr_drbg.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * + * PEM_PARSE uses AES for decrypting encrypted keys. + */ +#define MBEDTLS_AES_C + +/** + * \def MBEDTLS_ARC4_C + * + * Enable the ARCFOUR stream cipher. + * + * Module: library/arc4.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_SHA + * MBEDTLS_TLS_RSA_WITH_RC4_128_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA + * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA + * + * \warning ARC4 is considered a weak cipher and its use constitutes a + * security risk. If possible, we recommend avoidng dependencies on + * it, and considering stronger ciphers instead. + * + */ +#define MBEDTLS_ARC4_C + +/** + * \def MBEDTLS_ASN1_PARSE_C + * + * Enable the generic ASN1 parser. + * + * Module: library/asn1.c + * Caller: library/x509.c + * library/dhm.c + * library/pkcs12.c + * library/pkcs5.c + * library/pkparse.c + */ +#define MBEDTLS_ASN1_PARSE_C + +/** + * \def MBEDTLS_ASN1_WRITE_C + * + * Enable the generic ASN1 writer. + * + * Module: library/asn1write.c + * Caller: library/ecdsa.c + * library/pkwrite.c + * library/x509_create.c + * library/x509write_crt.c + * library/x509write_csr.c + */ +#define MBEDTLS_ASN1_WRITE_C + +/** + * \def MBEDTLS_BASE64_C + * + * Enable the Base64 module. + * + * Module: library/base64.c + * Caller: library/pem.c + * + * This module is required for PEM support (required by X.509). + */ +#define MBEDTLS_BASE64_C + +/** + * \def MBEDTLS_BIGNUM_C + * + * Enable the multi-precision integer library. + * + * Module: library/bignum.c + * Caller: library/dhm.c + * library/ecp.c + * library/ecdsa.c + * library/rsa.c + * library/rsa_internal.c + * library/ssl_tls.c + * + * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support. + */ +#define MBEDTLS_BIGNUM_C + +/** + * \def MBEDTLS_BLOWFISH_C + * + * Enable the Blowfish block cipher. + * + * Module: library/blowfish.c + */ +#define MBEDTLS_BLOWFISH_C + +/** + * \def MBEDTLS_CAMELLIA_C + * + * Enable the Camellia block cipher. + * + * Module: library/camellia.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_CAMELLIA_C + +/** + * \def MBEDTLS_ARIA_C + * + * Enable the ARIA block cipher. + * + * Module: library/aria.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * + * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 + */ +//#define MBEDTLS_ARIA_C + +/** + * \def MBEDTLS_CCM_C + * + * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher. + * + * Module: library/ccm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C + * + * This module enables the AES-CCM ciphersuites, if other requisites are + * enabled as well. + */ +#define MBEDTLS_CCM_C + +/** + * \def MBEDTLS_CERTS_C + * + * Enable the test certificates. + * + * Module: library/certs.c + * Caller: + * + * This module is used for testing (ssl_client/server). + */ +#define MBEDTLS_CERTS_C + +/** + * \def MBEDTLS_CHACHA20_C + * + * Enable the ChaCha20 stream cipher. + * + * Module: library/chacha20.c + */ +#define MBEDTLS_CHACHA20_C + +/** + * \def MBEDTLS_CHACHAPOLY_C + * + * Enable the ChaCha20-Poly1305 AEAD algorithm. + * + * Module: library/chachapoly.c + * + * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C + */ +#define MBEDTLS_CHACHAPOLY_C + +/** + * \def MBEDTLS_CIPHER_C + * + * Enable the generic cipher layer. + * + * Module: library/cipher.c + * Caller: library/ssl_tls.c + * + * Uncomment to enable generic cipher wrappers. + */ +#define MBEDTLS_CIPHER_C + +/** + * \def MBEDTLS_CMAC_C + * + * Enable the CMAC (Cipher-based Message Authentication Code) mode for block + * ciphers. + * + * Module: library/cmac.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C + * + */ +#define MBEDTLS_CMAC_C + +/** + * \def MBEDTLS_CTR_DRBG_C + * + * Enable the CTR_DRBG AES-based random generator. + * The CTR_DRBG generator uses AES-256 by default. + * To use AES-128 instead, enable MBEDTLS_CTR_DRBG_USE_128_BIT_KEY below. + * + * Module: library/ctr_drbg.c + * Caller: + * + * Requires: MBEDTLS_AES_C + * + * This module provides the CTR_DRBG AES random number generator. + */ +#define MBEDTLS_CTR_DRBG_C + +/** + * \def MBEDTLS_DEBUG_C + * + * Enable the debug functions. + * + * Module: library/debug.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module provides debugging functions. + */ +#define MBEDTLS_DEBUG_C + +/** + * \def MBEDTLS_DES_C + * + * Enable the DES block cipher. + * + * Module: library/des.c + * Caller: library/pem.c + * library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA + * + * PEM_PARSE uses DES/3DES for decrypting encrypted keys. + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +#define MBEDTLS_DES_C + +/** + * \def MBEDTLS_DHM_C + * + * Enable the Diffie-Hellman-Merkle module. + * + * Module: library/dhm.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * DHE-RSA, DHE-PSK + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_DHM_C + +/** + * \def MBEDTLS_ECDH_C + * + * Enable the elliptic curve Diffie-Hellman library. + * + * Module: library/ecdh.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK + * + * Requires: MBEDTLS_ECP_C + */ +#define MBEDTLS_ECDH_C + +/** + * \def MBEDTLS_ECDSA_C + * + * Enable the elliptic curve DSA library. + * + * Module: library/ecdsa.c + * Caller: + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C + */ +#define MBEDTLS_ECDSA_C + +/** + * \def MBEDTLS_ECJPAKE_C + * + * Enable the elliptic curve J-PAKE library. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Module: library/ecjpake.c + * Caller: + * + * This module is used by the following key exchanges: + * ECJPAKE + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C + */ +//#define MBEDTLS_ECJPAKE_C + +/** + * \def MBEDTLS_ECP_C + * + * Enable the elliptic curve over GF(p) library. + * + * Module: library/ecp.c + * Caller: library/ecdh.c + * library/ecdsa.c + * library/ecjpake.c + * + * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED + */ +#define MBEDTLS_ECP_C + +/** + * \def MBEDTLS_ENTROPY_C + * + * Enable the platform-specific entropy code. + * + * Module: library/entropy.c + * Caller: + * + * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C + * + * This module provides a generic entropy pool + */ +#define MBEDTLS_ENTROPY_C + +/** + * \def MBEDTLS_ERROR_C + * + * Enable error code to error string conversion. + * + * Module: library/error.c + * Caller: + * + * This module enables mbedtls_strerror(). + */ +#define MBEDTLS_ERROR_C + +/** + * \def MBEDTLS_GCM_C + * + * Enable the Galois/Counter Mode (GCM) for AES. + * + * Module: library/gcm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C + * + * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other + * requisites are enabled as well. + */ +#define MBEDTLS_GCM_C + +/** + * \def MBEDTLS_HAVEGE_C + * + * Enable the HAVEGE random generator. + * + * Warning: the HAVEGE random generator is not suitable for virtualized + * environments + * + * Warning: the HAVEGE random generator is dependent on timing and specific + * processor traits. It is therefore not advised to use HAVEGE as + * your applications primary random generator or primary entropy pool + * input. As a secondary input to your entropy pool, it IS able add + * the (limited) extra entropy it provides. + * + * Module: library/havege.c + * Caller: + * + * Requires: MBEDTLS_TIMING_C + * + * Uncomment to enable the HAVEGE random generator. + */ +//#define MBEDTLS_HAVEGE_C + +/** + * \def MBEDTLS_HKDF_C + * + * Enable the HKDF algorithm (RFC 5869). + * + * Module: library/hkdf.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the Hashed Message Authentication Code + * (HMAC)-based key derivation function (HKDF). + */ +#define MBEDTLS_HKDF_C + +/** + * \def MBEDTLS_HMAC_DRBG_C + * + * Enable the HMAC_DRBG random generator. + * + * Module: library/hmac_drbg.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * Uncomment to enable the HMAC_DRBG random number geerator. + */ +#define MBEDTLS_HMAC_DRBG_C + +/** + * \def MBEDTLS_NIST_KW_C + * + * Enable the Key Wrapping mode for 128-bit block ciphers, + * as defined in NIST SP 800-38F. Only KW and KWP modes + * are supported. At the moment, only AES is approved by NIST. + * + * Module: library/nist_kw.c + * + * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C + */ +//#define MBEDTLS_NIST_KW_C + +/** + * \def MBEDTLS_MD_C + * + * Enable the generic message digest layer. + * + * Module: library/md.c + * Caller: + * + * Uncomment to enable generic message digest wrappers. + */ +#define MBEDTLS_MD_C + +/** + * \def MBEDTLS_MD2_C + * + * Enable the MD2 hash algorithm. + * + * Module: library/md2.c + * Caller: + * + * Uncomment to enable support for (rare) MD2-signed X.509 certs. + * + * \warning MD2 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +//#define MBEDTLS_MD2_C + +/** + * \def MBEDTLS_MD4_C + * + * Enable the MD4 hash algorithm. + * + * Module: library/md4.c + * Caller: + * + * Uncomment to enable support for (rare) MD4-signed X.509 certs. + * + * \warning MD4 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +//#define MBEDTLS_MD4_C + +/** + * \def MBEDTLS_MD5_C + * + * Enable the MD5 hash algorithm. + * + * Module: library/md5.c + * Caller: library/md.c + * library/pem.c + * library/ssl_tls.c + * + * This module is required for SSL/TLS up to version 1.1, and for TLS 1.2 + * depending on the handshake parameters. Further, it is used for checking + * MD5-signed certificates, and for PBKDF1 when decrypting PEM-encoded + * encrypted keys. + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_MD5_C + +/** + * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Enable the buffer allocator implementation that makes use of a (stack) + * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() + * calls) + * + * Module: library/memory_buffer_alloc.c + * + * Requires: MBEDTLS_PLATFORM_C + * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS) + * + * Enable this module to enable the buffer memory allocator. + */ +//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +/** + * \def MBEDTLS_NET_C + * + * Enable the TCP and UDP over IPv6/IPv4 networking routines. + * + * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) + * and Windows. For other platforms, you'll want to disable it, and write your + * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/net_sockets.c + * + * This module provides networking routines. + */ +#define MBEDTLS_NET_C + +/** + * \def MBEDTLS_OID_C + * + * Enable the OID database. + * + * Module: library/oid.c + * Caller: library/asn1write.c + * library/pkcs5.c + * library/pkparse.c + * library/pkwrite.c + * library/rsa.c + * library/x509.c + * library/x509_create.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * This modules translates between OIDs and internal values. + */ +#define MBEDTLS_OID_C + +/** + * \def MBEDTLS_PADLOCK_C + * + * Enable VIA Padlock support on x86. + * + * Module: library/padlock.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the VIA PadLock on x86. + */ +#define MBEDTLS_PADLOCK_C + +/** + * \def MBEDTLS_PEM_PARSE_C + * + * Enable PEM decoding / parsing. + * + * Module: library/pem.c + * Caller: library/dhm.c + * library/pkparse.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for decoding / parsing PEM files. + */ +#define MBEDTLS_PEM_PARSE_C + +/** + * \def MBEDTLS_PEM_WRITE_C + * + * Enable PEM encoding / writing. + * + * Module: library/pem.c + * Caller: library/pkwrite.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for encoding / writing PEM files. + */ +#define MBEDTLS_PEM_WRITE_C + +/** + * \def MBEDTLS_PK_C + * + * Enable the generic public (asymetric) key layer. + * + * Module: library/pk.c + * Caller: library/ssl_tls.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C + * + * Uncomment to enable generic public key wrappers. + */ +#define MBEDTLS_PK_C + +/** + * \def MBEDTLS_PK_PARSE_C + * + * Enable the generic public (asymetric) key parser. + * + * Module: library/pkparse.c + * Caller: library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key parse functions. + */ +#define MBEDTLS_PK_PARSE_C + +/** + * \def MBEDTLS_PK_WRITE_C + * + * Enable the generic public (asymetric) key writer. + * + * Module: library/pkwrite.c + * Caller: library/x509write.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key write functions. + */ +#define MBEDTLS_PK_WRITE_C + +/** + * \def MBEDTLS_PKCS5_C + * + * Enable PKCS#5 functions. + * + * Module: library/pkcs5.c + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the PKCS#5 functions. + */ +#define MBEDTLS_PKCS5_C + +/** + * \def MBEDTLS_PKCS11_C + * + * Enable wrapper for PKCS#11 smartcard support. + * + * Module: library/pkcs11.c + * Caller: library/pk.c + * + * Requires: MBEDTLS_PK_C + * + * This module enables SSL/TLS PKCS #11 smartcard support. + * Requires the presence of the PKCS#11 helper library (libpkcs11-helper) + */ +//#define MBEDTLS_PKCS11_C + +/** + * \def MBEDTLS_PKCS12_C + * + * Enable PKCS#12 PBE functions. + * Adds algorithms for parsing PKCS#8 encrypted private keys + * + * Module: library/pkcs12.c + * Caller: library/pkparse.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * Can use: MBEDTLS_ARC4_C + * + * This module enables PKCS#12 functions. + */ +#define MBEDTLS_PKCS12_C + +/** + * \def MBEDTLS_PLATFORM_C + * + * Enable the platform abstraction layer that allows you to re-assign + * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). + * + * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT + * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned + * above to be specified at runtime or compile time respectively. + * + * \note This abstraction layer must be enabled on Windows (including MSYS2) + * as other module rely on it for a fixed snprintf implementation. + * + * Module: library/platform.c + * Caller: Most other .c files + * + * This module enables abstraction of common (libc) functions. + */ +#define MBEDTLS_PLATFORM_C + +/** + * \def MBEDTLS_POLY1305_C + * + * Enable the Poly1305 MAC algorithm. + * + * Module: library/poly1305.c + * Caller: library/chachapoly.c + */ +#define MBEDTLS_POLY1305_C + +/** + * \def MBEDTLS_RIPEMD160_C + * + * Enable the RIPEMD-160 hash algorithm. + * + * Module: library/ripemd160.c + * Caller: library/md.c + * + */ +#define MBEDTLS_RIPEMD160_C + +/** + * \def MBEDTLS_RSA_C + * + * Enable the RSA public-key cryptosystem. + * + * Module: library/rsa.c + * library/rsa_internal.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509.c + * + * This module is used by the following key exchanges: + * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C + */ +#define MBEDTLS_RSA_C + +/** + * \def MBEDTLS_SHA1_C + * + * Enable the SHA1 cryptographic hash algorithm. + * + * Module: library/sha1.c + * Caller: library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509write_crt.c + * + * This module is required for SSL/TLS up to version 1.1, for TLS 1.2 + * depending on the handshake parameters, and for SHA1-signed certificates. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_SHA1_C + +/** + * \def MBEDTLS_SHA256_C + * + * Enable the SHA-224 and SHA-256 cryptographic hash algorithms. + * + * Module: library/sha256.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module adds support for SHA-224 and SHA-256. + * This module is required for the SSL/TLS 1.2 PRF function. + */ +#define MBEDTLS_SHA256_C + +/** + * \def MBEDTLS_SHA512_C + * + * Enable the SHA-384 and SHA-512 cryptographic hash algorithms. + * + * Module: library/sha512.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * This module adds support for SHA-384 and SHA-512. + */ +#define MBEDTLS_SHA512_C + +#if (SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM) +#undef MBEDTLS_SHA512_C +#endif + +/** + * \def MBEDTLS_SSL_CACHE_C + * + * Enable simple SSL cache implementation. + * + * Module: library/ssl_cache.c + * Caller: + * + * Requires: MBEDTLS_SSL_CACHE_C + */ +#define MBEDTLS_SSL_CACHE_C + +/** + * \def MBEDTLS_SSL_COOKIE_C + * + * Enable basic implementation of DTLS cookies for hello verification. + * + * Module: library/ssl_cookie.c + * Caller: + */ +#define MBEDTLS_SSL_COOKIE_C + +/** + * \def MBEDTLS_SSL_TICKET_C + * + * Enable an implementation of TLS server-side callbacks for session tickets. + * + * Module: library/ssl_ticket.c + * Caller: + * + * Requires: MBEDTLS_CIPHER_C + */ +#define MBEDTLS_SSL_TICKET_C + +/** + * \def MBEDTLS_SSL_CLI_C + * + * Enable the SSL/TLS client code. + * + * Module: library/ssl_cli.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS client support. + */ +#define MBEDTLS_SSL_CLI_C + +/** + * \def MBEDTLS_SSL_SRV_C + * + * Enable the SSL/TLS server code. + * + * Module: library/ssl_srv.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS server support. + */ +#define MBEDTLS_SSL_SRV_C + +/** + * \def MBEDTLS_SSL_TLS_C + * + * Enable the generic SSL/TLS code. + * + * Module: library/ssl_tls.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * and at least one of the MBEDTLS_SSL_PROTO_XXX defines + * + * This module is required for SSL/TLS. + */ +#define MBEDTLS_SSL_TLS_C + +/** + * \def MBEDTLS_THREADING_C + * + * Enable the threading abstraction layer. + * By default mbed TLS assumes it is used in a non-threaded environment or that + * contexts are not shared between threads. If you do intend to use contexts + * between threads, you will need to enable this layer to prevent race + * conditions. See also our Knowledge Base article about threading: + * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading + * + * Module: library/threading.c + * + * This allows different threading implementations (self-implemented or + * provided). + * + * You will have to enable either MBEDTLS_THREADING_ALT or + * MBEDTLS_THREADING_PTHREAD. + * + * Enable this layer to allow use of mutexes within mbed TLS + */ +//#define MBEDTLS_THREADING_C + +/** + * \def MBEDTLS_TIMING_C + * + * Enable the semi-portable timing interface. + * + * \note The provided implementation only works on POSIX/Unix (including Linux, + * BSD and OS X) and Windows. On other platforms, you can either disable that + * module and provide your own implementations of the callbacks needed by + * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide + * your own implementation of the whole module by setting + * \c MBEDTLS_TIMING_ALT in the current file. + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/timing.c + * Caller: library/havege.c + * + * This module is used by the HAVEGE random number generator. + */ +#define MBEDTLS_TIMING_C + +/** + * \def MBEDTLS_VERSION_C + * + * Enable run-time version information. + * + * Module: library/version.c + * + * This module provides run-time version information. + */ +#define MBEDTLS_VERSION_C + +/** + * \def MBEDTLS_X509_USE_C + * + * Enable X.509 core for using certificates. + * + * Module: library/x509.c + * Caller: library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, + * MBEDTLS_PK_PARSE_C + * + * This module is required for the X.509 parsing modules. + */ +#define MBEDTLS_X509_USE_C + +/** + * \def MBEDTLS_X509_CRT_PARSE_C + * + * Enable X.509 certificate parsing. + * + * Module: library/x509_crt.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 certificate parsing. + */ +#define MBEDTLS_X509_CRT_PARSE_C + +/** + * \def MBEDTLS_X509_CRL_PARSE_C + * + * Enable X.509 CRL parsing. + * + * Module: library/x509_crl.c + * Caller: library/x509_crt.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 CRL parsing. + */ +#define MBEDTLS_X509_CRL_PARSE_C + +/** + * \def MBEDTLS_X509_CSR_PARSE_C + * + * Enable X.509 Certificate Signing Request (CSR) parsing. + * + * Module: library/x509_csr.c + * Caller: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is used for reading X.509 certificate request. + */ +#define MBEDTLS_X509_CSR_PARSE_C + +/** + * \def MBEDTLS_X509_CREATE_C + * + * Enable X.509 core for creating certificates. + * + * Module: library/x509_create.c + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C + * + * This module is the basis for creating X.509 certificates and CSRs. + */ +#define MBEDTLS_X509_CREATE_C + +/** + * \def MBEDTLS_X509_CRT_WRITE_C + * + * Enable creating X.509 certificates. + * + * Module: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate creation. + */ +#define MBEDTLS_X509_CRT_WRITE_C + +/** + * \def MBEDTLS_X509_CSR_WRITE_C + * + * Enable creating X.509 Certificate Signing Requests (CSR). + * + * Module: library/x509_csr_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate request writing. + */ +#define MBEDTLS_X509_CSR_WRITE_C + +/** + * \def MBEDTLS_XTEA_C + * + * Enable the XTEA block cipher. + * + * Module: library/xtea.c + * Caller: + */ +#define MBEDTLS_XTEA_C + +/* \} name SECTION: mbed TLS modules */ + +/** + * \name SECTION: Module configuration options + * + * This section allows for the setting of module specific sizes and + * configuration options. The default values are already present in the + * relevant header files and should suffice for the regular use cases. + * + * Our advice is to enable options and change their values here + * only if you have a good reason and know the consequences. + * + * Please check the respective header file for documentation on these + * parameters (to prevent duplicate documentation). + * \{ + */ + +/* MPI / BIGNUM options */ +//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ + +/* CTR_DRBG options */ +//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ +//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ +//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY /**< Use 128-bit key for CTR_DRBG - may reduce security (see ctr_drbg.h) */ + +/* HMAC_DRBG options */ +//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* ECP options */ +//#define MBEDTLS_ECP_MAX_BITS 521 /**< Maximum bit size of groups */ +//#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< Maximum window size used */ +//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ + +/* Entropy options */ +//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ + +/* Memory buffer allocator options */ +//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ + +/* Platform options */ +//#define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ +//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +/* Note: your snprintf must correclty zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ + +/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */ +/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ +//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ +/* Note: your snprintf must correclty zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ + +/** + * \brief This macro is invoked by the library when an invalid parameter + * is detected that is only checked with MBEDTLS_CHECK_PARAMS + * (see the documentation of that option for context). + * + * When you leave this undefined here, a default definition is + * provided that invokes the function mbedtls_param_failed(), + * which is declared in platform_util.h for the benefit of the + * library, but that you need to define in your application. + * + * When you define this here, this replaces the default + * definition in platform_util.h (which no longer declares the + * function mbedtls_param_failed()) and it is your responsibility + * to make sure this macro expands to something suitable (in + * particular, that all the necessary declarations are visible + * from within the library - you can ensure that by providing + * them in this file next to the macro definition). + * + * Note that you may define this macro to expand to nothing, in + * which case you don't have to worry about declarations or + * definitions. However, you will then be notified about invalid + * parameters only in non-void functions, and void function will + * just silently return early on invalid parameters, which + * partially negates the benefits of enabling + * #MBEDTLS_CHECK_PARAMS in the first place, so is discouraged. + * + * \param cond The expression that should evaluate to true, but doesn't. + */ +//#define MBEDTLS_PARAM_FAILED( cond ) assert( cond ) + +/* SSL Cache options */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ + +/* SSL options */ + +/** \def MBEDTLS_SSL_MAX_CONTENT_LEN + * + * Maximum length (in bytes) of incoming and outgoing plaintext fragments. + * + * This determines the size of both the incoming and outgoing TLS I/O buffers + * in such a way that both are capable of holding the specified amount of + * plaintext data, regardless of the protection mechanism used. + * + * To configure incoming and outgoing I/O buffers separately, use + * #MBEDTLS_SSL_IN_CONTENT_LEN and #MBEDTLS_SSL_OUT_CONTENT_LEN, + * which overwrite the value set by this option. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of both + * incoming and outgoing I/O buffers. + */ +//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_IN_CONTENT_LEN + * + * Maximum length (in bytes) of incoming plaintext fragments. + * + * This determines the size of the incoming TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * If this option is undefined, it inherits its value from + * #MBEDTLS_SSL_MAX_CONTENT_LEN. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of the incoming I/O buffer + * independently of the outgoing I/O buffer. + */ +//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_OUT_CONTENT_LEN + * + * Maximum length (in bytes) of outgoing plaintext fragments. + * + * This determines the size of the outgoing TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * If this option undefined, it inherits its value from + * #MBEDTLS_SSL_MAX_CONTENT_LEN. + * + * It is possible to save RAM by setting a smaller outward buffer, while keeping + * the default inward 16384 byte buffer to conform to the TLS specification. + * + * The minimum required outward buffer size is determined by the handshake + * protocol's usage. Handshaking will fail if the outward buffer is too small. + * The specific size requirement depends on the configured ciphers and any + * certificate data which is sent during the handshake. + * + * Uncomment to set the maximum plaintext size of the outgoing I/O buffer + * independently of the incoming I/O buffer. + */ +//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING + * + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + * + * This should be at least 9/8 * MBEDTLSSL_IN_CONTENT_LEN + * to account for a reassembled handshake message of maximum size, + * together with its reassembly bitmap. + * + * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) + * should be sufficient for all practical situations as it allows + * to reassembly a large handshake message (such as a certificate) + * while buffering multiple smaller handshake messages. + * + */ +//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 + +//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */ +//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ +//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ + +/** + * Complete list of ciphersuites to use, in order of preference. + * + * \warning No dependency checking is done on that field! This option can only + * be used to restrict the set of available ciphersuites. It is your + * responsibility to make sure the needed modules are active. + * + * Use this to save a few hundred bytes of ROM (default ordering of all + * available ciphersuites) and a few to a few hundred bytes of RAM. + * + * The value below is only an example, not the default. + */ +//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +/* X509 options */ +//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ +//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ + +/** + * Allow SHA-1 in the default TLS configuration for certificate signing. + * Without this build-time option, SHA-1 support must be activated explicitly + * through mbedtls_ssl_conf_cert_profile. Turning on this option is not + * recommended because of it is possible to generate SHA-1 collisions, however + * this may be safe for legacy infrastructure where additional controls apply. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +// #define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES + +/** + * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake + * signature and ciphersuite selection. Without this build-time option, SHA-1 + * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes. + * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by + * default. At the time of writing, there is no practical attack on the use + * of SHA-1 in handshake signatures, hence this option is turned on by default + * to preserve compatibility with existing peers, but the general + * warning applies nonetheless: + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE + +/** + * Uncomment the macro to let mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(). This replaces the default implementation in + * platform_util.c. + * + * mbedtls_platform_zeroize() is a widely used function across the library to + * zero a block of memory. The implementation is expected to be secure in the + * sense that it has been written to prevent the compiler from removing calls + * to mbedtls_platform_zeroize() as part of redundant code elimination + * optimizations. However, it is difficult to guarantee that calls to + * mbedtls_platform_zeroize() will not be optimized by the compiler as older + * versions of the C language standards do not provide a secure implementation + * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to + * configure their own implementation of mbedtls_platform_zeroize(), for + * example by using directives specific to their compiler, features from newer + * C standards (e.g using memset_s() in C11) or calling a secure memset() from + * their system (e.g explicit_bzero() in BSD). + */ +//#define MBEDTLS_PLATFORM_ZEROIZE_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +//#define MBEDTLS_PLATFORM_GMTIME_R_ALT + +/* \} name SECTION: Customisation configuration options */ + +/* Target and application specific configurations + * + * Allow user to override any previous default. + * + */ +#if defined(MBEDTLS_USER_CONFIG_FILE) +#include MBEDTLS_USER_CONFIG_FILE +#endif + +#include "mbedtls/check_config.h" + +/* clang-format on */ + +#endif /* MBEDTLS_CONFIG_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h new file mode 100644 index 00000000000..0fff01ab17e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h @@ -0,0 +1,62 @@ +/* + * Copyright 2018,2019 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef FSL_SSS_TYPES_H +#define FSL_SSS_TYPES_H + +#include +#include +#include + +#ifdef __STDC__ +#include +#endif + +#ifndef FALSE +#define FALSE false +#endif + +#ifndef TRUE +#define TRUE true +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / (sizeof(array[0]))) +#endif + +#define assert_static(e) \ + { \ + char assert_static__[(e) ? 1 : -1]; \ + assert_static__; \ + } + +/** Compile time assert */ +#define SSS_ASSERT(condition) assert_static(condition) + +/*! @brief Compile time sizeof() check */ +#define SSCP_BUILD_ASSURE(condition, msg) assert_static(condition) + +/* snprintf definition for MSVisualC */ +#ifdef _MSC_VER +#define SNPRINTF _snprintf +#define STRNICMP _strnicmp +#else /* _MSC_VER*/ +#define SNPRINTF snprintf +#define STRNICMP strncasecmp +#endif /*_MSC_VER*/ + +#ifndef SSS_MALLOC +#define SSS_MALLOC malloc +#endif // SSS_MALLOC + +#ifndef SSS_FREE +#define SSS_FREE free +#endif // SSS_FREE + +#ifndef SSS_CALLOC +#define SSS_CALLOC calloc +#endif // SSS_CALLOC + +#endif /* FSL_SSS_TYPES_H */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c new file mode 100644 index 00000000000..083005b1426 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c @@ -0,0 +1,2601 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_SSCP +#include +#endif /* SSS_HAVE_SSCP */ + +#if SSS_HAVE_APPLET_SE05X_IOT +#include +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ + +#if SSS_HAVE_MBEDTLS +#include +#endif /* SSS_HAVE_MBEDTLS */ + +#if SSS_HAVE_OPENSSL +#include +#endif /* SSS_HAVE_OPENSSL */ + +#if defined(FLOW_VERBOSE) +#define NX_LOG_ENABLE_SSS_DEBUG 1 +#endif +#include "nxLog_sss.h" + +#if (SSS_HAVE_SSS > 1) + +sss_status_t sss_session_create(sss_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + if (kType_SSS_Software == subsystem) { +#if SSS_HAVE_OPENSSL + /* if I have openSSL */ + subsystem = kType_SSS_OpenSSL; +#endif +#if SSS_HAVE_MBEDTLS + /* if I have mbed TLS */ + subsystem = kType_SSS_mbedTLS; +#endif + } + else if (kType_SSS_SecureElement == subsystem) { +#if SSS_HAVE_APPLET_SE05X_IOT + subsystem = kType_SSS_SE_SE05x; +#endif +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM + subsystem = kType_SSS_SE_A71CH; +#endif + } + +#if SSS_HAVE_SSCP + if (SSS_SUBSYSTEM_TYPE_IS_SSCP(subsystem)) { + return kStatus_SSS_Success; /* Nothing special to be handled yet */ + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SUBSYSTEM_TYPE_IS_SE05X(subsystem)) { + return kStatus_SSS_Success; /* Nothing special to be handled yet */ + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SUBSYSTEM_TYPE_IS_MBEDTLS(subsystem)) { + return kStatus_SSS_Success; /* Nothing special to be handled yet */ + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SUBSYSTEM_TYPE_IS_OPENSSL(subsystem)) { + return kStatus_SSS_Success; /* Nothing special to be handled yet */ + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_session_open(sss_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + if (kType_SSS_Software == subsystem) { +#if SSS_HAVE_OPENSSL + /* if I have openSSL */ + subsystem = kType_SSS_OpenSSL; +#endif +#if SSS_HAVE_MBEDTLS + /* if I have mbed TLS */ + subsystem = kType_SSS_mbedTLS; +#endif + } + else if (kType_SSS_SecureElement == subsystem) { +#if SSS_HAVE_SE + + subsystem = kType_SSS_SE_SE05x; +#endif +#if SSS_HAVE_A71CH || SSS_HAVE_A71CH_SIM + subsystem = kType_SSS_SE_A71CH; +#endif + } + +#if SSS_HAVE_SSCP + if (SSS_SUBSYSTEM_TYPE_IS_SSCP(subsystem)) { + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + return sss_sscp_session_open(sscp_session, subsystem, application_id, connection_type, connectionData); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SUBSYSTEM_TYPE_IS_SE05X(subsystem)) { + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + return sss_se05x_session_open(se05x_session, subsystem, application_id, connection_type, connectionData); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SUBSYSTEM_TYPE_IS_MBEDTLS(subsystem)) { + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + return sss_mbedtls_session_open(mbedtls_session, subsystem, application_id, connection_type, connectionData); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SUBSYSTEM_TYPE_IS_OPENSSL(subsystem)) { + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + return sss_openssl_session_open(openssl_session, subsystem, application_id, connection_type, connectionData); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_session_prop_get_u32(sss_session_t *session, uint32_t property, uint32_t *pValue) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + return sss_sscp_session_prop_get_u32(sscp_session, property, pValue); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + return sss_se05x_session_prop_get_u32(se05x_session, property, pValue); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + return sss_mbedtls_session_prop_get_u32(mbedtls_session, property, pValue); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + return sss_openssl_session_prop_get_u32(openssl_session, property, pValue); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_session_prop_get_au8(sss_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + return sss_sscp_session_prop_get_au8(sscp_session, property, pValue, pValueLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + return sss_se05x_session_prop_get_au8(se05x_session, property, pValue, pValueLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + return sss_mbedtls_session_prop_get_au8(mbedtls_session, property, pValue, pValueLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + return sss_openssl_session_prop_get_au8(openssl_session, property, pValue, pValueLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_session_close(sss_session_t *session) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_session_close(sscp_session); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_session_close(se05x_session); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_session_close(mbedtls_session); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_session_close(openssl_session); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +void sss_session_delete(sss_session_t *session) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + /* Nothing special to be handled */ + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + /* Nothing special to be handled */ + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + /* Nothing special to be handled */ + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + /* Nothing special to be handled */ + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_key_object_init(sss_object_t *keyObject, sss_key_store_t *keyStore) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + SSS_ASSERT(sizeof(*sscp_keyStore) <= sizeof(*keyStore)); + return sss_sscp_key_object_init(sscp_keyObject, sscp_keyStore); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + SSS_ASSERT(sizeof(*se05x_keyStore) <= sizeof(*keyStore)); + return sss_se05x_key_object_init(se05x_keyObject, se05x_keyStore); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + SSS_ASSERT(sizeof(*mbedtls_keyStore) <= sizeof(*keyStore)); + return sss_mbedtls_key_object_init(mbedtls_keyObject, mbedtls_keyStore); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + SSS_ASSERT(sizeof(*openssl_keyStore) <= sizeof(*keyStore)); + return sss_openssl_key_object_init(openssl_keyObject, openssl_keyStore); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_allocate_handle(sss_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_allocate_handle(sscp_keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_KEY_SET + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_allocate_handle( + se05x_keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_allocate_handle( + mbedtls_keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_allocate_handle( + openssl_keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_get_handle(sss_object_t *keyObject, uint32_t keyId) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_get_handle(sscp_keyObject, keyId); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_KEY_GET + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_get_handle(se05x_keyObject, keyId); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_get_handle(mbedtls_keyObject, keyId); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_get_handle(openssl_keyObject, keyId); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_set_user(sss_object_t *keyObject, uint32_t user, uint32_t options) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_set_user(sscp_keyObject, user, options); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_set_user(se05x_keyObject, user, options); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_set_user(mbedtls_keyObject, user, options); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_set_user(openssl_keyObject, user, options); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_set_purpose(sss_object_t *keyObject, sss_mode_t purpose, uint32_t options) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_set_purpose(sscp_keyObject, purpose, options); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_set_purpose(se05x_keyObject, purpose, options); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_set_purpose(mbedtls_keyObject, purpose, options); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_set_purpose(openssl_keyObject, purpose, options); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_set_access(sss_object_t *keyObject, uint32_t access, uint32_t options) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_set_access(sscp_keyObject, access, options); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_set_access(se05x_keyObject, access, options); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_set_access(mbedtls_keyObject, access, options); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_set_access(openssl_keyObject, access, options); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_set_eccgfp_group(sss_object_t *keyObject, sss_eccgfp_group_t *group) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_set_eccgfp_group(sscp_keyObject, group); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_set_eccgfp_group(se05x_keyObject, group); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_set_eccgfp_group(mbedtls_keyObject, group); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_set_eccgfp_group(openssl_keyObject, group); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_get_user(sss_object_t *keyObject, uint32_t *user) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_get_user(sscp_keyObject, user); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_get_user(se05x_keyObject, user); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_get_user(mbedtls_keyObject, user); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_get_user(openssl_keyObject, user); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_get_purpose(sss_object_t *keyObject, sss_mode_t *purpose) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_get_purpose(sscp_keyObject, purpose); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_get_purpose(se05x_keyObject, purpose); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_get_purpose(mbedtls_keyObject, purpose); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_get_purpose(openssl_keyObject, purpose); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_object_get_access(sss_object_t *keyObject, uint32_t *access) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_object_get_access(sscp_keyObject, access); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_object_get_access(se05x_keyObject, access); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_object_get_access(mbedtls_keyObject, access); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_object_get_access(openssl_keyObject, access); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_key_object_free(sss_object_t *keyObject) +{ +#if SSS_HAVE_SSCP + if (SSS_OBJECT_TYPE_IS_SSCP(keyObject)) { + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + sss_sscp_key_object_free(sscp_keyObject); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_OBJECT_TYPE_IS_SE05X(keyObject)) { + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + sss_se05x_key_object_free(se05x_keyObject); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_OBJECT_TYPE_IS_MBEDTLS(keyObject)) { + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + sss_mbedtls_key_object_free(mbedtls_keyObject); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_OBJECT_TYPE_IS_OPENSSL(keyObject)) { + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + sss_openssl_key_object_free(openssl_keyObject); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_derive_key_context_init(sss_derive_key_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + return sss_sscp_derive_key_context_init(sscp_context, sscp_session, sscp_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + return sss_se05x_derive_key_context_init(se05x_context, se05x_session, se05x_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + return sss_mbedtls_derive_key_context_init( + mbedtls_context, mbedtls_session, mbedtls_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + return sss_openssl_derive_key_context_init( + openssl_context, openssl_session, openssl_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_derive_key_go(sss_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DERIVE_KEY_TYPE_IS_SSCP(context)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_object_t *sscp_derivedKeyObject = (sss_sscp_object_t *)derivedKeyObject; + return sss_sscp_derive_key_go(sscp_context, + saltData, + saltLen, + info, + infoLen, + sscp_derivedKeyObject, + deriveDataLen, + hkdfOutput, + hkdfOutputLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DERIVE_KEY_TYPE_IS_SE05X(context)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_object_t *se05x_derivedKeyObject = (sss_se05x_object_t *)derivedKeyObject; + return sss_se05x_derive_key_go(se05x_context, + saltData, + saltLen, + info, + infoLen, + se05x_derivedKeyObject, + deriveDataLen, + hkdfOutput, + hkdfOutputLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_object_t *mbedtls_derivedKeyObject = (sss_mbedtls_object_t *)derivedKeyObject; + return sss_mbedtls_derive_key_go(mbedtls_context, + saltData, + saltLen, + info, + infoLen, + mbedtls_derivedKeyObject, + deriveDataLen, + hkdfOutput, + hkdfOutputLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_object_t *openssl_derivedKeyObject = (sss_openssl_object_t *)derivedKeyObject; + return sss_openssl_derive_key_go(openssl_context, + saltData, + saltLen, + info, + infoLen, + openssl_derivedKeyObject, + deriveDataLen, + hkdfOutput, + hkdfOutputLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +/* + Salt is public information and is passed as an array. +*/ +sss_status_t sss_derive_key_one_go(sss_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DERIVE_KEY_TYPE_IS_SSCP(context)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_object_t *sscp_derivedKeyObject = (sss_sscp_object_t *)derivedKeyObject; + return sss_sscp_derive_key_one_go( + sscp_context, saltData, saltLen, info, infoLen, sscp_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DERIVE_KEY_TYPE_IS_SE05X(context)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_object_t *se05x_derivedKeyObject = (sss_se05x_object_t *)derivedKeyObject; + return sss_se05x_derive_key_one_go( + se05x_context, saltData, saltLen, info, infoLen, se05x_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_object_t *mbedtls_derivedKeyObject = (sss_mbedtls_object_t *)derivedKeyObject; + return sss_mbedtls_derive_key_one_go( + mbedtls_context, saltData, saltLen, info, infoLen, mbedtls_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_object_t *openssl_derivedKeyObject = (sss_openssl_object_t *)derivedKeyObject; + return sss_openssl_derive_key_one_go( + openssl_context, saltData, saltLen, info, infoLen, openssl_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_derive_key_sobj_one_go(sss_derive_key_t *context, + sss_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DERIVE_KEY_TYPE_IS_SSCP(context)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_object_t *sscp_derivedKeyObject = (sss_sscp_object_t *)derivedKeyObject; + sss_sscp_object_t *sscp_saltKeyObject = (sss_sscp_object_t *)saltKeyObject; + return sss_sscp_derive_key_sobj_one_go( + sscp_context, sscp_saltKeyObject, info, infoLen, sscp_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DERIVE_KEY_TYPE_IS_SE05X(context)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_object_t *se05x_derivedKeyObject = (sss_se05x_object_t *)derivedKeyObject; + sss_se05x_object_t *se05x_saltKeyObject = (sss_se05x_object_t *)saltKeyObject; + return sss_se05x_derive_key_sobj_one_go( + se05x_context, se05x_saltKeyObject, info, infoLen, se05x_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_object_t *mbedtls_derivedKeyObject = (sss_mbedtls_object_t *)derivedKeyObject; + sss_mbedtls_object_t *mbedtls_saltKeyObject = (sss_mbedtls_object_t *)saltKeyObject; + return sss_mbedtls_derive_key_sobj_one_go( + mbedtls_context, mbedtls_saltKeyObject, info, infoLen, mbedtls_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_object_t *openssl_derivedKeyObject = (sss_openssl_object_t *)derivedKeyObject; + sss_openssl_object_t *openssl_saltKeyObject = (sss_openssl_object_t *)saltKeyObject; + return sss_openssl_derive_key_sobj_one_go( + openssl_context, openssl_saltKeyObject, info, infoLen, openssl_derivedKeyObject, deriveDataLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_derive_key_dh( + sss_derive_key_t *context, sss_object_t *otherPartyKeyObject, sss_object_t *derivedKeyObject) +{ +#if SSS_HAVE_SSCP + if (SSS_DERIVE_KEY_TYPE_IS_SSCP(context)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_object_t *sscp_otherPartyKeyObject = (sss_sscp_object_t *)otherPartyKeyObject; + sss_sscp_object_t *sscp_derivedKeyObject = (sss_sscp_object_t *)derivedKeyObject; + return sss_sscp_derive_key_dh(sscp_context, sscp_otherPartyKeyObject, sscp_derivedKeyObject); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DERIVE_KEY_TYPE_IS_SE05X(context)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_object_t *se05x_otherPartyKeyObject = (sss_se05x_object_t *)otherPartyKeyObject; + sss_se05x_object_t *se05x_derivedKeyObject = (sss_se05x_object_t *)derivedKeyObject; + return sss_se05x_derive_key_dh(se05x_context, se05x_otherPartyKeyObject, se05x_derivedKeyObject); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_object_t *mbedtls_otherPartyKeyObject = (sss_mbedtls_object_t *)otherPartyKeyObject; + sss_mbedtls_object_t *mbedtls_derivedKeyObject = (sss_mbedtls_object_t *)derivedKeyObject; + return sss_mbedtls_derive_key_dh(mbedtls_context, mbedtls_otherPartyKeyObject, mbedtls_derivedKeyObject); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_object_t *openssl_otherPartyKeyObject = (sss_openssl_object_t *)otherPartyKeyObject; + sss_openssl_object_t *openssl_derivedKeyObject = (sss_openssl_object_t *)derivedKeyObject; + return sss_openssl_derive_key_dh(openssl_context, openssl_otherPartyKeyObject, openssl_derivedKeyObject); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_derive_key_context_free(sss_derive_key_t *context) +{ +#if SSS_HAVE_SSCP + if (SSS_DERIVE_KEY_TYPE_IS_SSCP(context)) { + sss_sscp_derive_key_t *sscp_context = (sss_sscp_derive_key_t *)context; + sss_sscp_derive_key_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DERIVE_KEY_TYPE_IS_SE05X(context)) { + sss_se05x_derive_key_t *se05x_context = (sss_se05x_derive_key_t *)context; + sss_se05x_derive_key_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DERIVE_KEY_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_derive_key_t *mbedtls_context = (sss_mbedtls_derive_key_t *)context; + sss_mbedtls_derive_key_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DERIVE_KEY_TYPE_IS_OPENSSL(context)) { + sss_openssl_derive_key_t *openssl_context = (sss_openssl_derive_key_t *)context; + sss_openssl_derive_key_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_key_store_context_init(sss_key_store_t *keyStore, sss_session_t *session) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + SSS_ASSERT(sizeof(*sscp_keyStore) <= sizeof(*keyStore)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + return sss_sscp_key_store_context_init(sscp_keyStore, sscp_session); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + SSS_ASSERT(sizeof(*se05x_keyStore) <= sizeof(*keyStore)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + return sss_se05x_key_store_context_init(se05x_keyStore, se05x_session); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + SSS_ASSERT(sizeof(*mbedtls_keyStore) <= sizeof(*keyStore)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + return sss_mbedtls_key_store_context_init(mbedtls_keyStore, mbedtls_session); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + SSS_ASSERT(sizeof(*openssl_keyStore) <= sizeof(*keyStore)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + return sss_openssl_key_store_context_init(openssl_keyStore, openssl_session); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_allocate(sss_key_store_t *keyStore, uint32_t keyStoreId) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + return sss_sscp_key_store_allocate(sscp_keyStore, keyStoreId); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + return sss_se05x_key_store_allocate(se05x_keyStore, keyStoreId); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + return sss_mbedtls_key_store_allocate(mbedtls_keyStore, keyStoreId); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + return sss_openssl_key_store_allocate(openssl_keyStore, keyStoreId); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_save(sss_key_store_t *keyStore) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + return sss_sscp_key_store_save(sscp_keyStore); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + return sss_se05x_key_store_save(se05x_keyStore); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + return sss_mbedtls_key_store_save(mbedtls_keyStore); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + return sss_openssl_key_store_save(openssl_keyStore); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_load(sss_key_store_t *keyStore) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + return sss_sscp_key_store_load(sscp_keyStore); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + return sss_se05x_key_store_load(se05x_keyStore); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + return sss_mbedtls_key_store_load(mbedtls_keyStore); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + return sss_openssl_key_store_load(openssl_keyStore); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_set_key(sss_key_store_t *keyStore, + sss_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen) +{ + LOG_D("sss_key_store_set_key(@%08X, cipherType=%s, keyBitLen=%d)", + keyObject->keyId, + sss_cipher_type_sz(keyObject->cipherType), + keyBitLen); +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_set_key(sscp_keyStore, sscp_keyObject, data, dataLen, keyBitLen, options, optionsLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_KEY_SET + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_set_key( + se05x_keyStore, se05x_keyObject, data, dataLen, keyBitLen, options, optionsLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_set_key( + mbedtls_keyStore, mbedtls_keyObject, data, dataLen, keyBitLen, options, optionsLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_set_key( + openssl_keyStore, openssl_keyObject, data, dataLen, keyBitLen, options, optionsLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_generate_key( + sss_key_store_t *keyStore, sss_object_t *keyObject, size_t keyBitLen, void *options) +{ + LOG_D("sss_key_store_generate_key(@%08X, cipherType=%s, keyBitLen=%d)", + keyObject->keyId, + sss_cipher_type_sz(keyObject->cipherType), + keyBitLen); +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_generate_key(sscp_keyStore, sscp_keyObject, keyBitLen, options); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_generate_key(se05x_keyStore, se05x_keyObject, keyBitLen, options); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_generate_key(mbedtls_keyStore, mbedtls_keyObject, keyBitLen, options); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_generate_key(openssl_keyStore, openssl_keyObject, keyBitLen, options); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_get_key( + sss_key_store_t *keyStore, sss_object_t *keyObject, uint8_t *data, size_t *dataLen, size_t *pKeyBitLen) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_get_key(sscp_keyStore, sscp_keyObject, data, dataLen, pKeyBitLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_KEY_GET + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_get_key(se05x_keyStore, se05x_keyObject, data, dataLen, pKeyBitLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_get_key(mbedtls_keyStore, mbedtls_keyObject, data, dataLen, pKeyBitLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_get_key(openssl_keyStore, openssl_keyObject, data, dataLen, pKeyBitLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_open_key(sss_key_store_t *keyStore, sss_object_t *keyObject) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_open_key(sscp_keyStore, sscp_keyObject); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_open_key(se05x_keyStore, se05x_keyObject); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_open_key(mbedtls_keyStore, mbedtls_keyObject); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_open_key(openssl_keyStore, openssl_keyObject); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_freeze_key(sss_key_store_t *keyStore, sss_object_t *keyObject) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_freeze_key(sscp_keyStore, sscp_keyObject); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_freeze_key(se05x_keyStore, se05x_keyObject); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_freeze_key(mbedtls_keyStore, mbedtls_keyObject); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_freeze_key(openssl_keyStore, openssl_keyObject); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_key_store_erase_key(sss_key_store_t *keyStore, sss_object_t *keyObject) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + return sss_sscp_key_store_erase_key(sscp_keyStore, sscp_keyObject); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + return sss_se05x_key_store_erase_key(se05x_keyStore, se05x_keyObject); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + return sss_mbedtls_key_store_erase_key(mbedtls_keyStore, mbedtls_keyObject); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + return sss_openssl_key_store_erase_key(openssl_keyStore, openssl_keyObject); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_key_store_context_free(sss_key_store_t *keyStore) +{ +#if SSS_HAVE_SSCP + if (SSS_KEY_STORE_TYPE_IS_SSCP(keyStore)) { + sss_sscp_key_store_t *sscp_keyStore = (sss_sscp_key_store_t *)keyStore; + sss_sscp_key_store_context_free(sscp_keyStore); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_KEY_STORE_TYPE_IS_SE05X(keyStore)) { + sss_se05x_key_store_t *se05x_keyStore = (sss_se05x_key_store_t *)keyStore; + sss_se05x_key_store_context_free(se05x_keyStore); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_KEY_STORE_TYPE_IS_MBEDTLS(keyStore)) { + sss_mbedtls_key_store_t *mbedtls_keyStore = (sss_mbedtls_key_store_t *)keyStore; + sss_mbedtls_key_store_context_free(mbedtls_keyStore); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_KEY_STORE_TYPE_IS_OPENSSL(keyStore)) { + sss_openssl_key_store_t *openssl_keyStore = (sss_openssl_key_store_t *)keyStore; + sss_openssl_key_store_context_free(openssl_keyStore); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_asymmetric_context_init(sss_asymmetric_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + return sss_sscp_asymmetric_context_init(sscp_context, sscp_session, sscp_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + return sss_se05x_asymmetric_context_init(se05x_context, se05x_session, se05x_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + return sss_mbedtls_asymmetric_context_init( + mbedtls_context, mbedtls_session, mbedtls_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + return sss_openssl_asymmetric_context_init( + openssl_context, openssl_session, openssl_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_asymmetric_encrypt( + sss_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ +#if SSS_HAVE_SSCP + if (SSS_ASYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + return sss_sscp_asymmetric_encrypt(sscp_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_ASYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + return sss_se05x_asymmetric_encrypt(se05x_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + return sss_mbedtls_asymmetric_encrypt(mbedtls_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + return sss_openssl_asymmetric_encrypt(openssl_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_asymmetric_decrypt( + sss_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ +#if SSS_HAVE_SSCP + if (SSS_ASYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + return sss_sscp_asymmetric_decrypt(sscp_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_ASYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + return sss_se05x_asymmetric_decrypt(se05x_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + return sss_mbedtls_asymmetric_decrypt(mbedtls_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + return sss_openssl_asymmetric_decrypt(openssl_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_asymmetric_sign_digest( + sss_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen) +{ +#if SSS_HAVE_SSCP + if (SSS_ASYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + return sss_sscp_asymmetric_sign_digest(sscp_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_ASYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + return sss_se05x_asymmetric_sign_digest(se05x_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + return sss_mbedtls_asymmetric_sign_digest(mbedtls_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + return sss_openssl_asymmetric_sign_digest(openssl_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_asymmetric_verify_digest( + sss_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen) +{ +#if SSS_HAVE_SSCP + if (SSS_ASYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + return sss_sscp_asymmetric_verify_digest(sscp_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_ASYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + return sss_se05x_asymmetric_verify_digest(se05x_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + return sss_mbedtls_asymmetric_verify_digest(mbedtls_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + return sss_openssl_asymmetric_verify_digest(openssl_context, digest, digestLen, signature, signatureLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_asymmetric_context_free(sss_asymmetric_t *context) +{ +#if SSS_HAVE_SSCP + if (SSS_ASYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_asymmetric_t *sscp_context = (sss_sscp_asymmetric_t *)context; + sss_sscp_asymmetric_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_ASYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_asymmetric_t *se05x_context = (sss_se05x_asymmetric_t *)context; + sss_se05x_asymmetric_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_ASYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_asymmetric_t *mbedtls_context = (sss_mbedtls_asymmetric_t *)context; + sss_mbedtls_asymmetric_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_ASYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_asymmetric_t *openssl_context = (sss_openssl_asymmetric_t *)context; + sss_openssl_asymmetric_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_symmetric_context_init(sss_symmetric_t *context, + sss_session_t *session, + sss_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_D("Input:algorithm %02x", algorithm); + LOG_D("Input:mode %02x", mode); + +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + return sss_sscp_symmetric_context_init(sscp_context, sscp_session, sscp_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_AES + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + return sss_se05x_symmetric_context_init(se05x_context, se05x_session, se05x_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + return sss_mbedtls_symmetric_context_init(mbedtls_context, mbedtls_session, mbedtls_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + return sss_openssl_symmetric_context_init(openssl_context, openssl_session, openssl_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_cipher_one_go( + sss_symmetric_t *context, uint8_t *iv, size_t ivLen, const uint8_t *srcData, uint8_t *destData, size_t dataLen) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input: IV", iv, ivLen); + LOG_MAU8_D(" Input: srcData", srcData, dataLen); +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + return sss_sscp_cipher_one_go(sscp_context, iv, ivLen, srcData, destData, dataLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_AES + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + return sss_se05x_cipher_one_go(se05x_context, iv, ivLen, srcData, destData, dataLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + return sss_mbedtls_cipher_one_go(mbedtls_context, iv, ivLen, srcData, destData, dataLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + return sss_openssl_cipher_one_go(openssl_context, iv, ivLen, srcData, destData, dataLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_cipher_init(sss_symmetric_t *context, uint8_t *iv, size_t ivLen) +{ +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + return sss_sscp_cipher_init(sscp_context, iv, ivLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + return sss_se05x_cipher_init(se05x_context, iv, ivLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + return sss_mbedtls_cipher_init(mbedtls_context, iv, ivLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + return sss_openssl_cipher_init(openssl_context, iv, ivLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_cipher_update( + sss_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + return sss_sscp_cipher_update(sscp_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + return sss_se05x_cipher_update(se05x_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + return sss_mbedtls_cipher_update(mbedtls_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + return sss_openssl_cipher_update(openssl_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_cipher_finish( + sss_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + return sss_sscp_cipher_finish(sscp_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + return sss_se05x_cipher_finish(se05x_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + return sss_mbedtls_cipher_finish(mbedtls_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + return sss_openssl_cipher_finish(openssl_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_cipher_crypt_ctr(sss_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft) +{ +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + return sss_sscp_cipher_crypt_ctr( + sscp_context, srcData, destData, size, initialCounter, lastEncryptedCounter, szLeft); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + return sss_se05x_cipher_crypt_ctr( + se05x_context, srcData, destData, size, initialCounter, lastEncryptedCounter, szLeft); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + return sss_mbedtls_cipher_crypt_ctr( + mbedtls_context, srcData, destData, size, initialCounter, lastEncryptedCounter, szLeft); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + return sss_openssl_cipher_crypt_ctr( + openssl_context, srcData, destData, size, initialCounter, lastEncryptedCounter, szLeft); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_symmetric_context_free(sss_symmetric_t *context) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_SYMMETRIC_TYPE_IS_SSCP(context)) { + sss_sscp_symmetric_t *sscp_context = (sss_sscp_symmetric_t *)context; + sss_sscp_symmetric_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SYMMETRIC_TYPE_IS_SE05X(context)) { + sss_se05x_symmetric_t *se05x_context = (sss_se05x_symmetric_t *)context; + sss_se05x_symmetric_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SYMMETRIC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_symmetric_t *mbedtls_context = (sss_mbedtls_symmetric_t *)context; + sss_mbedtls_symmetric_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SYMMETRIC_TYPE_IS_OPENSSL(context)) { + sss_openssl_symmetric_t *openssl_context = (sss_openssl_symmetric_t *)context; + sss_openssl_symmetric_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_aead_context_init( + sss_aead_t *context, sss_session_t *session, sss_object_t *keyObject, sss_algorithm_t algorithm, sss_mode_t mode) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + return sss_sscp_aead_context_init(sscp_context, sscp_session, sscp_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + return sss_se05x_aead_context_init(se05x_context, se05x_session, se05x_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + return sss_mbedtls_aead_context_init(mbedtls_context, mbedtls_session, mbedtls_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + return sss_openssl_aead_context_init(openssl_context, openssl_session, openssl_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_aead_one_go(sss_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + return sss_sscp_aead_one_go(sscp_context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + return sss_se05x_aead_one_go(se05x_context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + return sss_mbedtls_aead_one_go( + mbedtls_context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + return sss_openssl_aead_one_go( + openssl_context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_aead_init( + sss_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + return sss_sscp_aead_init(sscp_context, nonce, nonceLen, tagLen, aadLen, payloadLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + return sss_se05x_aead_init(se05x_context, nonce, nonceLen, tagLen, aadLen, payloadLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + return sss_mbedtls_aead_init(mbedtls_context, nonce, nonceLen, tagLen, aadLen, payloadLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + return sss_openssl_aead_init(openssl_context, nonce, nonceLen, tagLen, aadLen, payloadLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_aead_update_aad(sss_aead_t *context, const uint8_t *aadData, size_t aadDataLen) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + return sss_sscp_aead_update_aad(sscp_context, aadData, aadDataLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + return sss_se05x_aead_update_aad(se05x_context, aadData, aadDataLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + return sss_mbedtls_aead_update_aad(mbedtls_context, aadData, aadDataLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + return sss_openssl_aead_update_aad(openssl_context, aadData, aadDataLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_aead_update( + sss_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + return sss_sscp_aead_update(sscp_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + return sss_se05x_aead_update(se05x_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + return sss_mbedtls_aead_update(mbedtls_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + return sss_openssl_aead_update(openssl_context, srcData, srcLen, destData, destLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_aead_finish(sss_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + return sss_sscp_aead_finish(sscp_context, srcData, srcLen, destData, destLen, tag, tagLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + return sss_se05x_aead_finish(se05x_context, srcData, srcLen, destData, destLen, tag, tagLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + return sss_mbedtls_aead_finish(mbedtls_context, srcData, srcLen, destData, destLen, tag, tagLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + return sss_openssl_aead_finish(openssl_context, srcData, srcLen, destData, destLen, tag, tagLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_aead_context_free(sss_aead_t *context) +{ +#if SSS_HAVE_SSCP + if (SSS_AEAD_TYPE_IS_SSCP(context)) { + sss_sscp_aead_t *sscp_context = (sss_sscp_aead_t *)context; + sss_sscp_aead_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_AEAD_TYPE_IS_SE05X(context)) { + sss_se05x_aead_t *se05x_context = (sss_se05x_aead_t *)context; + sss_se05x_aead_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_AEAD_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_aead_t *mbedtls_context = (sss_mbedtls_aead_t *)context; + sss_mbedtls_aead_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_AEAD_TYPE_IS_OPENSSL(context)) { + sss_openssl_aead_t *openssl_context = (sss_openssl_aead_t *)context; + sss_openssl_aead_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_mac_context_init( + sss_mac_t *context, sss_session_t *session, sss_object_t *keyObject, sss_algorithm_t algorithm, sss_mode_t mode) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_D("Input:algorithm %02x", algorithm); + LOG_D("Input:mode %02x", mode); +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + sss_sscp_object_t *sscp_keyObject = (sss_sscp_object_t *)keyObject; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*sscp_keyObject) <= sizeof(*keyObject)); + return sss_sscp_mac_context_init(sscp_context, sscp_session, sscp_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + sss_se05x_object_t *se05x_keyObject = (sss_se05x_object_t *)keyObject; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*se05x_keyObject) <= sizeof(*keyObject)); + return sss_se05x_mac_context_init(se05x_context, se05x_session, se05x_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + sss_mbedtls_object_t *mbedtls_keyObject = (sss_mbedtls_object_t *)keyObject; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*mbedtls_keyObject) <= sizeof(*keyObject)); + return sss_mbedtls_mac_context_init(mbedtls_context, mbedtls_session, mbedtls_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + sss_openssl_object_t *openssl_keyObject = (sss_openssl_object_t *)keyObject; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + SSS_ASSERT(sizeof(*openssl_keyObject) <= sizeof(*keyObject)); + return sss_openssl_mac_context_init(openssl_context, openssl_session, openssl_keyObject, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_mac_one_go(sss_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input: message", message, messageLen); + //LOG_MAU8_D(" Output: mac", context, *macLen); +#if SSS_HAVE_SSCP + if (SSS_MAC_TYPE_IS_SSCP(context)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + return sss_sscp_mac_one_go(sscp_context, message, messageLen, mac, macLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_MAC_TYPE_IS_SE05X(context)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + return sss_se05x_mac_one_go(se05x_context, message, messageLen, mac, macLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_MAC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + return sss_mbedtls_mac_one_go(mbedtls_context, message, messageLen, mac, macLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_MAC_TYPE_IS_OPENSSL(context)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + return sss_openssl_mac_one_go(openssl_context, message, messageLen, mac, macLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_mac_init(sss_mac_t *context) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_MAC_TYPE_IS_SSCP(context)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + return sss_sscp_mac_init(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_SE05X_AES + if (SSS_MAC_TYPE_IS_SE05X(context)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + return sss_se05x_mac_init(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_MAC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + return sss_mbedtls_mac_init(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_MAC_TYPE_IS_OPENSSL(context)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + return sss_openssl_mac_init(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_mac_update(sss_mac_t *context, const uint8_t *message, size_t messageLen) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input: message", message, messageLen); + +#if SSS_HAVE_SSCP + if (SSS_MAC_TYPE_IS_SSCP(context)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + return sss_sscp_mac_update(sscp_context, message, messageLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_MAC_TYPE_IS_SE05X(context)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + return sss_se05x_mac_update(se05x_context, message, messageLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_MAC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + return sss_mbedtls_mac_update(mbedtls_context, message, messageLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_MAC_TYPE_IS_OPENSSL(context)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + return sss_openssl_mac_update(openssl_context, message, messageLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_mac_finish(sss_mac_t *context, uint8_t *mac, size_t *macLen) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_MAC_TYPE_IS_SSCP(context)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + return sss_sscp_mac_finish(sscp_context, mac, macLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_MAC_TYPE_IS_SE05X(context)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + return sss_se05x_mac_finish(se05x_context, mac, macLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_MAC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + return sss_mbedtls_mac_finish(mbedtls_context, mac, macLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_MAC_TYPE_IS_OPENSSL(context)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + return sss_openssl_mac_finish(openssl_context, mac, macLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_mac_context_free(sss_mac_t *context) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_MAC_TYPE_IS_SSCP(context)) { + sss_sscp_mac_t *sscp_context = (sss_sscp_mac_t *)context; + sss_sscp_mac_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_MAC_TYPE_IS_SE05X(context)) { + sss_se05x_mac_t *se05x_context = (sss_se05x_mac_t *)context; + sss_se05x_mac_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_MAC_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_mac_t *mbedtls_context = (sss_mbedtls_mac_t *)context; + sss_mbedtls_mac_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_MAC_TYPE_IS_OPENSSL(context)) { + sss_openssl_mac_t *openssl_context = (sss_openssl_mac_t *)context; + sss_openssl_mac_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_digest_context_init( + sss_digest_t *context, sss_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode) +{ +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + return sss_sscp_digest_context_init(sscp_context, sscp_session, algorithm, mode); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + return sss_se05x_digest_context_init(se05x_context, se05x_session, algorithm, mode); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + return sss_mbedtls_digest_context_init(mbedtls_context, mbedtls_session, algorithm, mode); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + return sss_openssl_digest_context_init(openssl_context, openssl_session, algorithm, mode); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_digest_one_go( + sss_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DIGEST_TYPE_IS_SSCP(context)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + return sss_sscp_digest_one_go(sscp_context, message, messageLen, digest, digestLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DIGEST_TYPE_IS_SE05X(context)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + return sss_se05x_digest_one_go(se05x_context, message, messageLen, digest, digestLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DIGEST_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + return sss_mbedtls_digest_one_go(mbedtls_context, message, messageLen, digest, digestLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DIGEST_TYPE_IS_OPENSSL(context)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + return sss_openssl_digest_one_go(openssl_context, message, messageLen, digest, digestLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_digest_init(sss_digest_t *context) +{ +#if SSS_HAVE_SSCP + if (SSS_DIGEST_TYPE_IS_SSCP(context)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + return sss_sscp_digest_init(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DIGEST_TYPE_IS_SE05X(context)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + return sss_se05x_digest_init(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DIGEST_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + return sss_mbedtls_digest_init(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DIGEST_TYPE_IS_OPENSSL(context)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + return sss_openssl_digest_init(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_digest_update(sss_digest_t *context, const uint8_t *message, size_t messageLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DIGEST_TYPE_IS_SSCP(context)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + return sss_sscp_digest_update(sscp_context, message, messageLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DIGEST_TYPE_IS_SE05X(context)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + return sss_se05x_digest_update(se05x_context, message, messageLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DIGEST_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + return sss_mbedtls_digest_update(mbedtls_context, message, messageLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DIGEST_TYPE_IS_OPENSSL(context)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + return sss_openssl_digest_update(openssl_context, message, messageLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_digest_finish(sss_digest_t *context, uint8_t *digest, size_t *digestLen) +{ +#if SSS_HAVE_SSCP + if (SSS_DIGEST_TYPE_IS_SSCP(context)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + return sss_sscp_digest_finish(sscp_context, digest, digestLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DIGEST_TYPE_IS_SE05X(context)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + return sss_se05x_digest_finish(se05x_context, digest, digestLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DIGEST_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + return sss_mbedtls_digest_finish(mbedtls_context, digest, digestLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DIGEST_TYPE_IS_OPENSSL(context)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + return sss_openssl_digest_finish(openssl_context, digest, digestLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_digest_context_free(sss_digest_t *context) +{ +#if SSS_HAVE_SSCP + if (SSS_DIGEST_TYPE_IS_SSCP(context)) { + sss_sscp_digest_t *sscp_context = (sss_sscp_digest_t *)context; + sss_sscp_digest_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_DIGEST_TYPE_IS_SE05X(context)) { + sss_se05x_digest_t *se05x_context = (sss_se05x_digest_t *)context; + sss_se05x_digest_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_DIGEST_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_digest_t *mbedtls_context = (sss_mbedtls_digest_t *)context; + sss_mbedtls_digest_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_DIGEST_TYPE_IS_OPENSSL(context)) { + sss_openssl_digest_t *openssl_context = (sss_openssl_digest_t *)context; + sss_openssl_digest_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ +} + +sss_status_t sss_rng_context_init(sss_rng_context_t *context, sss_session_t *session) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_rng_context_t *sscp_context = (sss_sscp_rng_context_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + SSS_ASSERT(sizeof(*sscp_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*sscp_session) <= sizeof(*session)); + return sss_sscp_rng_context_init(sscp_context, sscp_session); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_rng_context_t *se05x_context = (sss_se05x_rng_context_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + SSS_ASSERT(sizeof(*se05x_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*se05x_session) <= sizeof(*session)); + return sss_se05x_rng_context_init(se05x_context, se05x_session); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_SESSION_TYPE_IS_MBEDTLS(session)) { + sss_mbedtls_rng_context_t *mbedtls_context = (sss_mbedtls_rng_context_t *)context; + sss_mbedtls_session_t *mbedtls_session = (sss_mbedtls_session_t *)session; + SSS_ASSERT(sizeof(*mbedtls_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*mbedtls_session) <= sizeof(*session)); + return sss_mbedtls_rng_context_init(mbedtls_context, mbedtls_session); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_SESSION_TYPE_IS_OPENSSL(session)) { + sss_openssl_rng_context_t *openssl_context = (sss_openssl_rng_context_t *)context; + sss_openssl_session_t *openssl_session = (sss_openssl_session_t *)session; + SSS_ASSERT(sizeof(*openssl_context) <= sizeof(*context)); + SSS_ASSERT(sizeof(*openssl_session) <= sizeof(*session)); + return sss_openssl_rng_context_init(openssl_context, openssl_session); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_rng_get_random(sss_rng_context_t *context, uint8_t *random_data, size_t dataLen) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_RNG_CONTEXT_TYPE_IS_SSCP(context)) { + sss_sscp_rng_context_t *sscp_context = (sss_sscp_rng_context_t *)context; + return sss_sscp_rng_get_random(sscp_context, random_data, dataLen); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_RNG_CONTEXT_TYPE_IS_SE05X(context)) { + sss_se05x_rng_context_t *se05x_context = (sss_se05x_rng_context_t *)context; + return sss_se05x_rng_get_random(se05x_context, random_data, dataLen); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_RNG_CONTEXT_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_rng_context_t *mbedtls_context = (sss_mbedtls_rng_context_t *)context; + return sss_mbedtls_rng_get_random(mbedtls_context, random_data, dataLen); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_RNG_CONTEXT_TYPE_IS_OPENSSL(context)) { + sss_openssl_rng_context_t *openssl_context = (sss_openssl_rng_context_t *)context; + return sss_openssl_rng_get_random(openssl_context, random_data, dataLen); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_rng_context_free(sss_rng_context_t *context) +{ + LOG_D("FN: %s", __FUNCTION__); +#if SSS_HAVE_SSCP + if (SSS_RNG_CONTEXT_TYPE_IS_SSCP(context)) { + sss_sscp_rng_context_t *sscp_context = (sss_sscp_rng_context_t *)context; + return sss_sscp_rng_context_free(sscp_context); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_RNG_CONTEXT_TYPE_IS_SE05X(context)) { + sss_se05x_rng_context_t *se05x_context = (sss_se05x_rng_context_t *)context; + return sss_se05x_rng_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + if (SSS_RNG_CONTEXT_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_rng_context_t *mbedtls_context = (sss_mbedtls_rng_context_t *)context; + return sss_mbedtls_rng_context_free(mbedtls_context); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + if (SSS_RNG_CONTEXT_TYPE_IS_OPENSSL(context)) { + sss_openssl_rng_context_t *openssl_context = (sss_openssl_rng_context_t *)context; + return sss_openssl_rng_context_free(openssl_context); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_tunnel_context_init(sss_tunnel_t *context, sss_session_t *session) +{ +#if 0 && SSS_HAVE_SSCP + if (SSS_SESSION_TYPE_IS_SSCP(session)) { + sss_sscp_tunnel_t *sscp_context = (sss_sscp_tunnel_t *)context; + sss_sscp_session_t *sscp_session = (sss_sscp_session_t *)session; + return sss_sscp_tunnel_context_init(sscp_context, sscp_session); + } +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (SSS_SESSION_TYPE_IS_SE05X(session)) { + sss_se05x_tunnel_context_t *se05x_context = (sss_se05x_tunnel_context_t *)context; + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)session; + return sss_se05x_tunnel_context_init(se05x_context, se05x_session); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + /* NA */ +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + /* NA */ +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +sss_status_t sss_tunnel(sss_tunnel_t *context, + uint8_t *data, + size_t dataLen, + sss_object_t *keyObjects, + uint32_t keyObjectCount, + uint32_t tunnelType) +{ +#if 0 && SSS_HAVE_SSCP + if (SSS_TUNNEL_TYPE_IS_SSCP(context)) { + sss_sscp_tunnel_t *sscp_context = (sss_sscp_tunnel_t *)context; + sss_sscp_object_t *sscp_keyObjects = (sss_sscp_object_t *)keyObjects; + return sss_sscp_tunnel(sscp_context, + data, + dataLen, + sscp_keyObjects, + keyObjectCount, + tunnelType); + } +#endif /* SSS_HAVE_SSCP */ +#if 0 && SSS_HAVE_APPLET_SE05X_IOT + if (SSS_TUNNEL_TYPE_IS_SE05X(context)) { + sss_se05x_tunnel_context_t *se05x_context = (sss_se05x_tunnel_context_t *)context; + sss_se05x_object_t *se05x_keyObjects = (sss_se05x_object_t *)keyObjects; + return sss_se05x_tunnel(se05x_context, + data, + dataLen, + se05x_keyObjects, + keyObjectCount, + tunnelType); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if 0 && SSS_HAVE_MBEDTLS + if (SSS_TUNNEL_TYPE_IS_MBEDTLS(context)) { + sss_mbedtls_tunnel_t *mbedtls_context = (sss_mbedtls_tunnel_t *)context; + sss_mbedtls_object_t *mbedtls_keyObjects = + (sss_mbedtls_object_t *)keyObjects; + return sss_mbedtls_tunnel(mbedtls_context, + data, + dataLen, + mbedtls_keyObjects, + keyObjectCount, + tunnelType); + } +#endif /* SSS_HAVE_MBEDTLS */ +#if 0 && SSS_HAVE_OPENSSL + if (SSS_TUNNEL_TYPE_IS_OPENSSL(context)) { + sss_openssl_tunnel_t *openssl_context = (sss_openssl_tunnel_t *)context; + sss_openssl_object_t *openssl_keyObjects = + (sss_openssl_object_t *)keyObjects; + return sss_openssl_tunnel(openssl_context, + data, + dataLen, + openssl_keyObjects, + keyObjectCount, + tunnelType); + } +#endif /* SSS_HAVE_OPENSSL */ + return kStatus_SSS_InvalidArgument; +} + +void sss_tunnel_context_free(sss_tunnel_t *context) +{ +#if SSS_HAVE_SSCP + /* NA */ +#endif /* SSS_HAVE_SSCP */ +#if SSS_HAVE_APPLET_SE05X_IOT + if (/*SSS_TUNNEL_TYPE_IS_SE05X*/ (context)) { + sss_se05x_tunnel_context_t *se05x_context = (sss_se05x_tunnel_context_t *)context; + sss_se05x_tunnel_context_free(se05x_context); + } +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ +#if SSS_HAVE_MBEDTLS + /* NA */ +#endif /* SSS_HAVE_MBEDTLS */ +#if SSS_HAVE_OPENSSL + /* NA */ +#endif /* SSS_HAVE_OPENSSL */ +} + +#define CASE_X_RETRUN_STR_kStatus_SSS(SUFFIX) \ + case kStatus_SSS_##SUFFIX: \ + return "kStatus_SSS_" #SUFFIX + +const char *sss_status_sz(sss_status_t status) +{ + switch (status) { + CASE_X_RETRUN_STR_kStatus_SSS(Success); + CASE_X_RETRUN_STR_kStatus_SSS(Fail); + CASE_X_RETRUN_STR_kStatus_SSS(InvalidArgument); + CASE_X_RETRUN_STR_kStatus_SSS(ResourceBusy); + default: + LOG_W("sss_status_sz status=0x%X Unknown", status); + return "Unknown sss_status_t"; + } +} + +#define CASE_X_RETRUN_STR_kSSS_CipherType(SUFFIX) \ + case kSSS_CipherType_##SUFFIX: \ + return "kSSS_CipherType_" #SUFFIX + +const char *sss_cipher_type_sz(sss_cipher_type_t cipher_type) +{ + switch (cipher_type) { + CASE_X_RETRUN_STR_kSSS_CipherType(AES); + CASE_X_RETRUN_STR_kSSS_CipherType(DES); + CASE_X_RETRUN_STR_kSSS_CipherType(CMAC); + CASE_X_RETRUN_STR_kSSS_CipherType(HMAC); + CASE_X_RETRUN_STR_kSSS_CipherType(MAC); + CASE_X_RETRUN_STR_kSSS_CipherType(RSA); + CASE_X_RETRUN_STR_kSSS_CipherType(RSA_CRT); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_NIST_P); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_NIST_K); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_MONTGOMERY); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_TWISTED_ED); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_BRAINPOOL); + CASE_X_RETRUN_STR_kSSS_CipherType(EC_BARRETO_NAEHRIG); + CASE_X_RETRUN_STR_kSSS_CipherType(UserID); + CASE_X_RETRUN_STR_kSSS_CipherType(Certificate); + CASE_X_RETRUN_STR_kSSS_CipherType(Binary); + CASE_X_RETRUN_STR_kSSS_CipherType(Count); + CASE_X_RETRUN_STR_kSSS_CipherType(PCR); + CASE_X_RETRUN_STR_kSSS_CipherType(ReservedPin); + default: + LOG_W("sss_cipher_type_sz status=0x%X Unknown", cipher_type); + return "Unknown sss_cipher_type_t"; + } +} + +#endif /* SSS_HAVE_SSS > 1 */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c new file mode 100644 index 00000000000..5c513d85515 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c @@ -0,0 +1,1751 @@ +/* +* +* Copyright 2018-2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +#include +#include +#include +#include +#include + +#if SSS_HAVE_APPLET_SE05X_IOT +#include +#endif + +#if SSS_HAVE_MBEDTLS +#include +#endif + +#if SSS_HAVE_OPENSSL +#include +#include +#include +#include +#include +#endif + +#define IS_VALID_TAG(x) \ + (x == ASN_TAG_SEQUENCE || x == ASN_TAG_OBJ_IDF || x == ASN_TAG_BITSTRING || x == ASN_TAG_INT || \ + x == ASN_TAG_OCTETSTRING || x == ASN_TAG_CNT_SPECIFIC || x == ASN_TAG_CRL_EXTENSIONS) ? \ + 1 : \ + 0 + +#define IS_VALID_RFC8410_TAG(x) \ + (x == ASN_TAG_SEQUENCE || x == ASN_TAG_OBJ_IDF || x == ASN_TAG_BITSTRING || x == ASN_TAG_INT || \ + x == ASN_TAG_OCTETSTRING || x == ASN_TAG_CNT_SPECIFIC || x == ASN_TAG_CRL_EXTENSIONS || \ + x == (ASN_TAG_CNT_SPECIFIC_PRIMITIVE | 0x01)) ? \ + 1 : \ + 0 + +/* clang-format off */ + +/* RSA Header */ +const uint8_t grsa512PubHeader[] = { + 0x30, 0x5C, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, \ + 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 0x05, \ + 0x00, 0x03, 0x4B, 0x00, 0x30, 0x48, 0x02 }; + +const uint8_t grsa1kPubHeader[] = { + 0x30, 0x81, 0x9F, 0x30, 0x0D, 0x06, 0x09, 0x2A, \ + 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, \ + 0x05, 0x00, 0x03, 0x81, 0x8D, 0x00, 0x30, 0x81, \ + 0x89, 0x02 }; + +const uint8_t grsa1152PubHeader[] = { + 0x30, 0x81, 0xAF, 0x30, 0x0D, 0x06, 0x09, 0x2A, \ + 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, \ + 0x05, 0x00, 0x03, 0x81, 0x9D, 0x00, 0x30, 0x81, \ + 0x99, 0x02 }; + +const uint8_t grsa2kPubHeader[] = { + 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, \ + 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, \ + 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, \ + 0x30, 0x82, 0x01, 0x0A, 0x02 }; + +const uint8_t grsa3kPubHeader[] = { + 0x30, 0x82, 0x01, 0xA2, 0x30, 0x0D, 0x06, 0x09, \ + 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, \ + 0x01, 0x05, 0x00, 0x03, 0x82, 0x01, 0x8F, 0x00, \ + 0x30, 0x82, 0x01, 0x8A, 0x02 }; + +const uint8_t grsa4kPubHeader[] = { + 0x30, 0x82, 0x02, 0x22, 0x30, 0x0D, 0x06, 0x09, \ + 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, \ + 0x01, 0x05, 0x00, 0x03, 0x82, 0x02, 0x0F, 0x00, \ + 0x30, 0x82, 0x02, 0x0A, 0x02 }; + +/* ECC Header */ +const uint8_t gecc_der_header_nist192[] = { + 0x30, 0x49, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x08, 0x2A, + 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x01, 0x03, + 0x32, 0x00, }; + +const uint8_t gecc_der_header_nist224[] = { + 0x30, 0x4E, 0x30, 0x10, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x05, 0x2B, + 0x81, 0x04, 0x00, 0x21, 0x03, 0x3A, 0x00, }; + +const uint8_t gecc_der_header_nist256[] = { + 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x08, 0x2A, + 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07, 0x03, + 0x42, 0x00 }; + +const uint8_t gecc_der_header_nist384[] = { + 0x30, 0x76, 0x30, 0x10, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x05, 0x2B, + 0x81, 0x04, 0x00, 0x22, 0x03, 0x62, 0x00, }; + +const uint8_t gecc_der_header_nist521[] = { + 0x30, 0x81, 0x9B, 0x30, 0x10, 0x06, 0x07, 0x2A, + 0x86, 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x05, + 0x2B, 0x81, 0x04, 0x00, 0x23, 0x03, 0x81, 0x86, + 0x00, }; + +const uint8_t gecc_der_header_160k[] = { + 0x30, 0x3e, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, 0x2b, + 0x81, 0x04, 0x00, 0x09, 0x03, 0x2a, 0x00, }; + +const uint8_t gecc_der_header_192k[] = { + 0x30, 0x46, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, 0x2b, + 0x81, 0x04, 0x00, 0x1f, 0x03, 0x32, 0x00, }; + +const uint8_t gecc_der_header_224k[] = { + 0x30, 0x4e, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x05, 0x2b, + 0x81, 0x04, 0x00, 0x20, 0x03, 0x3a, 0x00, }; + +const uint8_t gecc_der_header_256k[] = { + 0x30, 0x56, 0x30, 0x10, 0x06, 0x07, 0x2A, 0x86, + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x05, 0x2B, + 0x81, 0x04, 0x00, 0x0A, 0x03, 0x42, 0x00 }; + +const uint8_t gecc_der_header_bp160[] = { + 0x30, 0x42, 0x30, 0x14, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x09, 0x2b, + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x01, + 0x03, 0x2a, 0x00, }; + +const uint8_t gecc_der_header_bp192[] = { + 0x30, 0x4a, 0x30, 0x14, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x09, 0x2b, + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x03, + 0x03, 0x32, 0x00, }; + +const uint8_t gecc_der_header_bp224[] = { + 0x30, 0x52, 0x30, 0x14, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x09, 0x2b, + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x05, + 0x03, 0x3a, 0x00, }; + +const uint8_t gecc_der_header_bp256[] = { + 0x30, 0x5a, 0x30, 0x14, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x09, 0x2b, + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x07, + 0x03, 0x42, 0x00, }; + +const uint8_t gecc_der_header_bp320[] = { + 0x30, 0x6a, 0x30, 0x14, 0x06, 0x07, 0x2a, 0x86, + 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x09, 0x2b, + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x09, + 0x03, 0x52, 0x00, +}; + +const uint8_t gecc_der_header_bp384[] = { + 0x30, 0x7A, 0x30, 0x14, 0x06, 0x07, 0x2A, 0x86, \ + 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x09, 0x2B, \ + 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, 0x0B, \ + 0x03, 0x62, 0x00, }; + +const uint8_t gecc_der_header_bp512[] = { + 0x30, 0x81, 0x9B, 0x30, 0x14, 0x06, 0x07, 0x2A, + 0x86, 0x48, 0xCE, 0x3D, 0x02, 0x01, 0x06, 0x09, + 0x2B, 0x24, 0x03, 0x03, 0x02, 0x08, 0x01, 0x01, + 0x0D, 0x03, 0x81, 0x82, 0x00, }; + +const uint8_t gecc_der_header_mont_dh_448[] = { + 0x30, 0x42, 0x30, 0x05, 0x06, 0x03, 0x2b, 0x65, + 0x6f, 0x03, 0x39, 0x00, }; + +const uint8_t gecc_der_header_mont_dh_25519[] = { + 0x30, 0x2a, 0x30, 0x05, 0x06, 0x03, 0x2b, 0x65, + 0x6e, 0x03, 0x21, 0x00, }; + +const uint8_t gecc_der_header_twisted_ed_25519[] = { + 0x30, 0x2a, 0x30, 0x05, 0x06, 0x03, 0x2b, 0x65, + 0x70, 0x03, 0x21, 0x00, }; + +/* clang-format on */ + +size_t const der_ecc_nistp192_header_len = sizeof(gecc_der_header_nist192); +size_t const der_ecc_nistp224_header_len = sizeof(gecc_der_header_nist224); +size_t const der_ecc_nistp256_header_len = sizeof(gecc_der_header_nist256); +size_t const der_ecc_nistp384_header_len = sizeof(gecc_der_header_nist384); +size_t const der_ecc_nistp521_header_len = sizeof(gecc_der_header_nist521); +size_t const der_ecc_160k_header_len = sizeof(gecc_der_header_160k); +size_t const der_ecc_192k_header_len = sizeof(gecc_der_header_192k); +size_t const der_ecc_224k_header_len = sizeof(gecc_der_header_224k); +size_t const der_ecc_256k_header_len = sizeof(gecc_der_header_256k); +size_t const der_ecc_bp160_header_len = sizeof(gecc_der_header_bp160); +size_t const der_ecc_bp192_header_len = sizeof(gecc_der_header_bp192); +size_t const der_ecc_bp224_header_len = sizeof(gecc_der_header_bp224); +size_t const der_ecc_bp256_header_len = sizeof(gecc_der_header_bp256); +size_t const der_ecc_bp320_header_len = sizeof(gecc_der_header_bp320); +size_t const der_ecc_bp384_header_len = sizeof(gecc_der_header_bp384); +size_t const der_ecc_bp512_header_len = sizeof(gecc_der_header_bp512); +size_t const der_ecc_mont_dh_448_header_len = sizeof(gecc_der_header_mont_dh_448); +size_t const der_ecc_mont_dh_25519_header_len = sizeof(gecc_der_header_mont_dh_25519); +size_t const der_ecc_twisted_ed_25519_header_len = sizeof(gecc_der_header_twisted_ed_25519); + +static int check_tag(int tag); + +/* ************************************************************************** */ +/* Functions : ASN.1 Functions */ +/* ************************************************************************** */ + +sss_status_t sss_util_asn1_rsa_parse_private(const uint8_t *key, + size_t keylen, + sss_cipher_type_t cipher_type, + uint8_t **modulus, + size_t *modlen, + uint8_t **pubExp, + size_t *pubExplen, + uint8_t **priExp, + size_t *priExplen, + uint8_t **prime1, + size_t *prime1len, + uint8_t **prime2, + size_t *prime2len, + uint8_t **exponent1, + size_t *exponent1len, + uint8_t **exponent2, + size_t *exponent2len, + uint8_t **coefficient, + size_t *coefficientlen) +{ + uint8_t *pBuf = (uint8_t *)key; + size_t taglen = 0; + size_t bufIndex = 0; + uint8_t tag; + int ret; + sss_status_t status = kStatus_SSS_Fail; + /* Parse ASN.1 Sequence */ + /* Example: + 0x30, 0x82, 0x02, 0x77, ;SEQUENCE + 0x02, 0x01, ;INTEGER + 0x00, ;Algorithm version + 0x30, 0x0D, ;Sequence + 0x06, 0x09, ;ObjectIdentifier + 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, + 0x01, + 0x05, 0x00, ;Null + 0x04, 0x82, 0x02, 0x61, ;OctetString + 0x30, 0x82, 0x02, 0x5D, ;Sequence + 0x02, 0x01, 0x00, ;Integer + 0x02, 0x81, 0x81, ;Integer - Modulus + */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (taglen != (keylen - bufIndex)) { + LOG_E("Invlaid Key"); + goto exit; + } + /* No need of algorithem Version */ + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == ASN_TAG_INT) { + bufIndex += 3; + } + ENSURE_OR_GO_EXIT(bufIndex < keylen); + tag = pBuf[bufIndex]; + while (tag != ASN_TAG_INT) { + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Private Key Header Nested TLV */ + if (ret != 0) + goto exit; + if (tag == ASN_TAG_SEQUENCE && pBuf[bufIndex] != ASN_TAG_INT) + bufIndex += taglen; + ENSURE_OR_GO_EXIT(bufIndex < keylen); + tag = pBuf[bufIndex]; + } + + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == ASN_TAG_INT && pBuf[bufIndex + 1] == 1) { + bufIndex += 3; + } + /* Get the Modulus*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (modlen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *modlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *modlen = taglen; + ENSURE_OR_GO_EXIT(modulus != NULL); + *modulus = SSS_MALLOC(*modlen); + if ((*modulus != NULL) && ((*modlen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*modulus, pBuf + bufIndex, *modlen); + bufIndex += *modlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Public Exponent */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (pubExplen != NULL) { + *pubExplen = taglen; + ENSURE_OR_GO_EXIT(pubExp != NULL); + *pubExp = SSS_MALLOC(*pubExplen); + if ((*pubExp != NULL) && ((*pubExplen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*pubExp, pBuf + bufIndex, *pubExplen); + bufIndex += *pubExplen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Private Exponent*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (priExplen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *priExplen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *priExplen = taglen; + ENSURE_OR_GO_EXIT(priExp != NULL); + *priExp = SSS_MALLOC(*priExplen); + if ((*priExp != NULL) && ((*priExplen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*priExp, pBuf + bufIndex, *priExplen); + bufIndex += *priExplen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get First prime (p)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (prime1len != NULL) { + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *prime1len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *prime1len = taglen; + ENSURE_OR_GO_EXIT(prime1 != NULL); + *prime1 = SSS_MALLOC(*prime1len); + if ((*prime1 != NULL) && ((*prime1len) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*prime1, pBuf + bufIndex, *prime1len); + bufIndex += *prime1len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Second prime (q)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (prime2len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *prime2len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *prime2len = taglen; + ENSURE_OR_GO_EXIT(prime2 != NULL); + *prime2 = SSS_MALLOC(*prime2len); + if (*prime2 == NULL) { + LOG_E("malloc failed"); + goto exit; + } + if (*prime2len > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*prime2, pBuf + bufIndex, *prime2len); + bufIndex += *prime2len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get First exponent (dP)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (exponent1len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *exponent1len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *exponent1len = taglen; + ENSURE_OR_GO_EXIT(exponent1 != NULL); + *exponent1 = SSS_MALLOC(*exponent1len); + if ((*exponent1 != NULL) && ((*exponent1len) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*exponent1, pBuf + bufIndex, *exponent1len); + bufIndex += *exponent1len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Second exponent (dQ)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (exponent2len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *exponent2len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *exponent2len = taglen; + ENSURE_OR_GO_EXIT(exponent2 != NULL); + *exponent2 = SSS_MALLOC(*exponent2len); + if (*exponent2 == NULL) { + LOG_E("malloc failed"); + goto exit; + } + if (*exponent2len > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*exponent2, pBuf + bufIndex, *exponent2len); + bufIndex += *exponent2len; + } + else { + LOG_E("exponent2len improper"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Coefficient (qinv)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + if (coefficientlen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *coefficientlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *coefficientlen = taglen; + ENSURE_OR_GO_EXIT(coefficient != NULL); + *coefficient = SSS_MALLOC(*coefficientlen); + if ((*coefficient != NULL) && ((*coefficientlen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*coefficient, pBuf + bufIndex, *coefficientlen); + bufIndex += *coefficientlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_asn1_rsa_parse_private_allow_invalid_key(const uint8_t *key, + size_t keylen, + sss_cipher_type_t cipher_type, + uint8_t **modulus, + size_t *modlen, + uint8_t **pubExp, + size_t *pubExplen, + uint8_t **priExp, + size_t *priExplen, + uint8_t **prime1, + size_t *prime1len, + uint8_t **prime2, + size_t *prime2len, + uint8_t **exponent1, + size_t *exponent1len, + uint8_t **exponent2, + size_t *exponent2len, + uint8_t **coefficient, + size_t *coefficientlen) +{ + uint8_t *pBuf = (uint8_t *)key; + size_t taglen = 0; + size_t bufIndex = 0; + uint8_t tag; + int ret; + sss_status_t status = kStatus_SSS_Fail; + /* Parse ASN.1 Sequence */ + /* Example: + 0x30, 0x82, 0x02, 0x77, ;SEQUENCE + 0x02, 0x01, ;INTEGER + 0x00, ;Algorithm version + 0x30, 0x0D, ;Sequence + 0x06, 0x09, ;ObjectIdentifier + 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, + 0x01, + 0x05, 0x00, ;Null + 0x04, 0x82, 0x02, 0x61, ;OctetString + 0x30, 0x82, 0x02, 0x5D, ;Sequence + 0x02, 0x01, 0x00, ;Integer + 0x02, 0x81, 0x81, ;Integer - Modulus + */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + // if (taglen != (keylen - bufIndex)) { + // LOG_E("Invlaid Key"); + // goto exit; + // } + /* No need of algorithem Version */ + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == ASN_TAG_INT) { + bufIndex += 3; + } + + ENSURE_OR_GO_EXIT(bufIndex < keylen); + tag = pBuf[bufIndex]; + while (tag != ASN_TAG_INT) { + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Private Key Head*/ + ENSURE_OR_GO_EXIT(0 == ret); + + if (tag == ASN_TAG_SEQUENCE && pBuf[bufIndex] != ASN_TAG_INT) + bufIndex += taglen; + ENSURE_OR_GO_EXIT(bufIndex < keylen); + tag = pBuf[bufIndex]; + } + + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == ASN_TAG_INT && pBuf[bufIndex + 1] == 1) { + bufIndex += 3; + } + /* Get the Modulus*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (modlen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *modlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *modlen = taglen; + ENSURE_OR_GO_EXIT(modulus != NULL); + *modulus = SSS_MALLOC(*modlen); + if ((*modulus != NULL) && ((*modlen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*modulus, pBuf + bufIndex, *modlen); + bufIndex += *modlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Public Exponent */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (pubExplen != NULL) { + *pubExplen = taglen; + ENSURE_OR_GO_EXIT(pubExp != NULL); + *pubExp = SSS_MALLOC(*pubExplen); + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if ((*pubExp != NULL) && ((*pubExplen) > 0)) { + memcpy(*pubExp, pBuf + bufIndex, *pubExplen); + bufIndex += *pubExplen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Private Exponent*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (priExplen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *priExplen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *priExplen = taglen; + ENSURE_OR_GO_EXIT(priExp != NULL); + *priExp = SSS_MALLOC(*priExplen); + if ((*priExp != NULL) && ((*priExplen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*priExp, pBuf + bufIndex, *priExplen); + bufIndex += *priExplen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get First prime (p)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (prime1len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *prime1len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *prime1len = taglen; + ENSURE_OR_GO_EXIT(prime1 != NULL); + *prime1 = SSS_MALLOC(*prime1len); + if ((*prime1 != NULL) && ((*prime1len) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*prime1, pBuf + bufIndex, *prime1len); + bufIndex += *prime1len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Second prime (q)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (prime2len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *prime2len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *prime2len = taglen; + ENSURE_OR_GO_EXIT(prime2 != NULL); + *prime2 = SSS_MALLOC(*prime2len); + if (*prime2 == NULL) { + LOG_E("malloc failed"); + goto exit; + } + if (*prime2len > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*prime2, pBuf + bufIndex, *prime2len); + bufIndex += *prime2len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get First exponent (dP)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (exponent1len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *exponent1len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *exponent1len = taglen; + ENSURE_OR_GO_EXIT(exponent1 != NULL); + *exponent1 = SSS_MALLOC(*exponent1len); + if ((*exponent1 != NULL) && ((*exponent1len) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*exponent1, pBuf + bufIndex, *exponent1len); + bufIndex += *exponent1len; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Second exponent (dQ)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (exponent2len != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *exponent2len = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *exponent2len = taglen; + ENSURE_OR_GO_EXIT(exponent2 != NULL); + *exponent2 = SSS_MALLOC(*exponent2len); + if (*exponent2 == NULL) { + LOG_E("malloc failed"); + goto exit; + } + if (*exponent2len > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*exponent2, pBuf + bufIndex, *exponent2len); + bufIndex += *exponent2len; + } + else { + LOG_E("exponent2len improper"); + goto exit; + } + } + else + bufIndex += taglen; + + /* Get Coefficient (qinv)*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + ENSURE_OR_GO_EXIT(0 == ret); + + if (coefficientlen != NULL) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *coefficientlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *coefficientlen = taglen; + ENSURE_OR_GO_EXIT(coefficient != NULL); + *coefficient = SSS_MALLOC(*coefficientlen); + if ((*coefficient != NULL) && ((*coefficientlen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*coefficient, pBuf + bufIndex, *coefficientlen); + bufIndex += *coefficientlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + } + else + bufIndex += taglen; + + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen) +{ + uint8_t *pBuf = (uint8_t *)key; + size_t taglen = 0; + size_t bufIndex = 0; + int ret; + sss_status_t status = kStatus_SSS_Fail; + size_t temp_modlen = 0, temp_pubExplen = 0; + + if ((key == NULL) || (modulus == NULL) || (modlen == NULL) || (pubExp == NULL) || (pubExplen == NULL)) { + goto exit; + } + + //int tag = (key[1] == 0x82) ? 4 : 3; + /* Parse Header Information + Public Key contains 3 Sequences as header */ + ENSURE_OR_GO_EXIT(bufIndex < keylen); + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* ASN.1 Sequence */ + if (ret != 0) + goto exit; + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Public Header Nested TLV */ + if (ret != 0) + goto exit; + bufIndex += taglen; + + /* Bit-String + NULL Byte */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + bufIndex++; + + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Sequence of interger*/ + if (ret != 0) + goto exit; + /* Get the Modulus*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + temp_modlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + temp_modlen = taglen; + + if (*modlen < temp_modlen) { + LOG_E("modulus overflow"); + goto exit; + } + + *modlen = temp_modlen; + if ((*modlen) > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(modulus, pBuf + bufIndex, *modlen); + bufIndex += *modlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + + /* Get Public Exponent */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + temp_pubExplen = taglen; + if (*pubExplen < temp_pubExplen) { + LOG_E("pubExp overflow"); + goto exit; + } + *pubExplen = temp_pubExplen; + if (*pubExplen > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(pubExp, pBuf + bufIndex, *pubExplen); + bufIndex += *pubExplen; + status = kStatus_SSS_Success; + } +exit: + return status; +} + +sss_status_t sss_util_asn1_rsa_parse_public_nomalloc_complete_modulus( + const uint8_t *key, size_t keylen, uint8_t *modulus, size_t *modlen, uint8_t *pubExp, size_t *pubExplen) +{ + uint8_t *pBuf = (uint8_t *)key; + size_t taglen = 0; + size_t bufIndex = 0; + int ret; + sss_status_t status = kStatus_SSS_Fail; + size_t temp_modlen = 0, temp_pubExplen = 0; + + if ((key == NULL) || (modulus == NULL) || (modlen == NULL) || (pubExp == NULL) || (pubExplen == NULL)) { + goto exit; + } + + //int tag = (key[1] == 0x82) ? 4 : 3; + /* Parse Header Information + Public Key contains 3 Sequences as header */ + ENSURE_OR_GO_EXIT(bufIndex < keylen); + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* ASN.1 Sequence */ + if (ret != 0) + goto exit; + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Public Header Nested TLV */ + if (ret != 0) + goto exit; + bufIndex += taglen; + + /* Bit-String + NULL Byte */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + bufIndex++; + + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Sequence of interger*/ + if (ret != 0) + goto exit; + /* Get the Modulus*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + ENSURE_OR_GO_EXIT(bufIndex < keylen); + temp_modlen = taglen; + + if (*modlen < temp_modlen) { + LOG_E("modulus overflow"); + goto exit; + } + + *modlen = temp_modlen; + if ((*modlen) > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(modulus, pBuf + bufIndex, *modlen); + bufIndex += *modlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + + /* Get Public Exponent */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + temp_pubExplen = taglen; + if (*pubExplen < temp_pubExplen) { + LOG_E("pubExp overflow"); + goto exit; + } + *pubExplen = temp_pubExplen; + if (*pubExplen > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(pubExp, pBuf + bufIndex, *pubExplen); + bufIndex += *pubExplen; + status = kStatus_SSS_Success; + } +exit: + return status; +} + +sss_status_t sss_util_asn1_rsa_parse_public( + const uint8_t *key, size_t keylen, uint8_t **modulus, size_t *modlen, uint8_t **pubExp, size_t *pubExplen) +{ + uint8_t *pBuf = (uint8_t *)key; + size_t taglen = 0; + size_t bufIndex = 0; + int ret; + sss_status_t status = kStatus_SSS_Fail; + //int tag = (key[1] == 0x82) ? 4 : 3; + /* Parse Header Information + Public Key contains 3 Sequences as header */ + ENSURE_OR_GO_EXIT(bufIndex < keylen); + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* ASN.1 Sequence */ + if (ret != 0) + goto exit; + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Public Header Nested TLV */ + if (ret != 0) + goto exit; + bufIndex += taglen; + + /* Bit-String + NULL Byte */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + bufIndex++; + + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); /* Sequence of interger*/ + if (ret != 0) + goto exit; + /* Get the Modulus*/ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + if (ret != 0) + goto exit; + ENSURE_OR_GO_EXIT(bufIndex < keylen); + if (pBuf[bufIndex] == 0x00) { + if (taglen) { + *modlen = taglen - 1; /*Exclude Starting Null*/ + bufIndex++; + } + else { + goto exit; + } + } + else + *modlen = taglen; + *modulus = SSS_MALLOC(*modlen); + if ((*modulus != NULL) && ((*modlen) > 0)) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*modulus, pBuf + bufIndex, *modlen); + bufIndex += *modlen; + } + else { + LOG_E("Either malloc failed or improper length"); + goto exit; + } + + /* Get Public Exponent */ + ret = asn_1_parse_tlv(pBuf, &taglen, &bufIndex); + *pubExplen = taglen; + *pubExp = SSS_MALLOC(*pubExplen); + if (*pubExp == NULL) { + LOG_E("malloc failed"); + goto exit; + } + if (*pubExplen > 0) { + ENSURE_OR_GO_EXIT(bufIndex < keylen); + memcpy(*pubExp, pBuf + bufIndex, *pubExplen); + bufIndex += *pubExplen; + status = kStatus_SSS_Success; + } +exit: + return status; +} + +sss_status_t sss_util_asn1_rsa_get_public( + uint8_t *key, size_t *keylen, uint8_t *modulus, size_t modlen, uint8_t *pubExp, size_t pubExplen) +{ + sss_status_t status = kStatus_SSS_Fail; + size_t pbkeylen = modlen + pubExplen + sizeof(grsa1kPubHeader) + 3 + 3; + size_t index = 0; + size_t intModLEn = modlen + 1; // RSA Key has null byte before moduls start + + ENSURE_OR_GO_EXIT(key != NULL); + ENSURE_OR_GO_EXIT(keylen != NULL); + ENSURE_OR_GO_EXIT(modulus != NULL); + ENSURE_OR_GO_EXIT(pubExp != NULL); + + if (*keylen < pbkeylen) { + LOG_E("Buffer not sufficient"); + goto exit; + } + + /* Copy the Public Header According to key bit len*/ + if (modlen == 0x40) { + memcpy(key, grsa512PubHeader, sizeof(grsa512PubHeader)); + index += sizeof(grsa512PubHeader); + } + else if (modlen == 0x80) { + memcpy(key, grsa1kPubHeader, sizeof(grsa1kPubHeader)); + index += sizeof(grsa1kPubHeader); + } + else if (modlen == 0x90) { + memcpy(key, grsa1152PubHeader, sizeof(grsa1152PubHeader)); + index += sizeof(grsa1152PubHeader); + } + else if (modlen == 0x100) { + memcpy(key, grsa2kPubHeader, sizeof(grsa2kPubHeader)); + index += sizeof(grsa2kPubHeader); + } + else if (modlen == 0x180) { + memcpy(key, grsa3kPubHeader, sizeof(grsa3kPubHeader)); + index += sizeof(grsa3kPubHeader); + } + else if (modlen == 0x200) { + memcpy(key, grsa4kPubHeader, sizeof(grsa4kPubHeader)); + index += sizeof(grsa4kPubHeader); + } + + if (intModLEn < 0x7f) + key[index++] = (uint8_t)intModLEn; + else if (intModLEn < 0xFF) { + key[index++] = 0x81; + key[index++] = (uint8_t)intModLEn; + } + else { + key[index++] = 0x82; + key[index++] = (uint8_t)(intModLEn >> 8); + key[index++] = (uint8_t)intModLEn & 0xFF; + } + + key[index++] = 0x00; // Null byte + memcpy(key + index, modulus, modlen); + index += modlen; + + /*Copy the public Exponent*/ + key[index++] = 0x02; // tag + key[index++] = (uint8_t)pubExplen; // length + memcpy(key + index, pubExp, pubExplen); // value + index += pubExplen; + *keylen = index; + status = kStatus_SSS_Success; +exit: + return status; +} + +#if SSS_HAVE_ECDAA +sss_status_t sss_util_asn1_ecdaa_get_signature( + uint8_t *signature, size_t *signatureLen, uint8_t *rawSignature, size_t rawSignatureLen) +{ + sss_status_t status = kStatus_SSS_Fail; + size_t signAsn1Len, r_len, s_len; + + ENSURE_OR_GO_EXIT(signature != NULL); + ENSURE_OR_GO_EXIT(signatureLen != NULL); + ENSURE_OR_GO_EXIT(rawSignature != NULL); + + r_len = rawSignatureLen / 2; + s_len = rawSignatureLen / 2; + // SEQUENCE (2B) + INTEGER(2B) + INTEGER(2B) + signAsn1Len = 6 + rawSignatureLen; + if (*signatureLen < signAsn1Len) { + LOG_E("ECDAA Signature buffer overflow"); + goto exit; + } + + /* + Example: + 30 44 ; SEQUENCE (68 Bytes) + 02 20 ; INTEGER (32 Bytes) + | 3d 46 28 7b 8c 6e 8c 8c 26 1c 1b 88 f2 73 b0 9a + | 32 a6 cf 28 09 fd 6e 30 d5 a7 9f 26 37 00 8f 54 + 02 20 ; INTEGER (32 Bytes) + | 4e 72 23 6e a3 90 a9 a1 7b cf 5f 7a 09 d6 3a b2 + | 17 6c 92 bb 8e 36 c0 41 98 a2 7b 90 9b 6e 8f 13 + */ + *signatureLen = signAsn1Len; + if (rawSignatureLen == 0x40) { // TPM_ECC_BN_P256 + signature[0] = 0x30; //SEQUENCE + signature[1] = (uint8_t)(rawSignatureLen + 4); //INTEGER(2B) + INTEGER(2B) + signature[2] = 0x02; //INTEGER + signature[3] = (uint8_t)r_len; //lenght of r + memcpy(&signature[4], &rawSignature[0], r_len); + signature[3 + r_len + 1] = 0x02; //INTEGER + signature[3 + r_len + 2] = (uint8_t)s_len; //lenght of s + memcpy(&signature[3 + r_len + 3], &rawSignature[r_len], s_len); + } + else { + LOG_E("Invalid ECDAA Signature data"); + goto exit; + } + + status = kStatus_SSS_Success; +exit: + return status; +} +#endif + +#if 0 +static uint8_t *asn_1_parse_header(uint8_t *key, size_t keylen) +{ + uint8_t *pBuf = key; + uint16_t taglen = 0; + sss_status_t status = kStatus_SSS_Fail; + int tag = (key[1] == 0x82) ? 4 : 3; + /* Parse Header Information*/ + pBuf = asn_1_parse_tlv(pBuf, &taglen); + if (taglen != (keylen - tag)) + { + LOG_E("Invlaid Key"); + return status; + } +} +#endif + +int asn_1_parse_tlv(uint8_t *pbuf, size_t *taglen, size_t *bufindex) +{ + size_t Len; + uint8_t *buf = pbuf + *bufindex; + int tag; + tag = *buf++; /*Exclude The Tag*/ + Len = *buf++; + int ret = 0; + if (check_tag(tag)) { + ret = 1; + goto exit; + } + if (Len <= 0x7FU) { + *taglen = Len; + *bufindex += 1 + 1; + goto exit; + } + else if (Len == 0x81) { + *taglen = *buf++; + *bufindex += 1 + 2; + goto exit; + } + else if (Len == 0x82) { + *taglen = *buf++; + *taglen = (*taglen << 8) | (*buf++); + *bufindex += 1 + 3; + goto exit; + } + ret = 1; +exit: + return ret; +} + +static int check_tag(int tag) +{ + int ret = 0; + switch (tag) { + case ASN_TAG_INT: + case ASN_TAG_SEQUENCE: + case ASN_TAG_BITSTRING: + case ASN_TAG_OBJ_IDF: + case ASN_TAG_OCTETSTRING: + break; + default: + LOG_E("Wrong Tag parsed -- %d \n", tag); + ret = 1; + break; + } + return ret; +} + +#ifdef _MSC_VER +#pragma warning(disable : 4127) +#endif + +sss_status_t sss_util_asn1_get_oid_from_header(uint8_t *input, size_t inLen, uint32_t *output, uint8_t *outLen) +{ + size_t i = 0; + size_t taglen = 0; + int objectIdCnt = 0; + int tag = 0; + uint8_t outBufindex = 0; + sss_status_t status = kStatus_SSS_Fail; + + ENSURE_OR_GO_EXIT(input != NULL); + ENSURE_OR_GO_EXIT(output != NULL); + ENSURE_OR_GO_EXIT(outLen != NULL); + + for (;;) { + ENSURE_OR_GO_EXIT(i < inLen); + tag = input[i++]; + if (tag == ASN_TAG_SEQUENCE || tag == ASN_TAG_OBJ_IDF) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i++]; + if (taglen == 0x81) { + taglen = input[i]; + i = i + 1; + } + else if (taglen == 0x82) { + ENSURE_OR_GO_EXIT(i < (inLen - 1)); + taglen = ((input[i] << (0 * 8)) & 0x00FF) + ((input[i + 1] << (1 * 8)) & 0xFF00); + i = i + 2; + } + + if (taglen > inLen) + goto exit; + + if (tag == ASN_TAG_OBJ_IDF) + objectIdCnt++; + + if (objectIdCnt == 2) { + if (taglen <= 0) + goto exit; + ENSURE_OR_GO_EXIT(i < inLen); + ENSURE_OR_GO_EXIT(outBufindex < (*outLen)); + output[outBufindex++] = input[i] / 40; + output[outBufindex++] = input[i++] % 40; + taglen--; + + while (taglen--) { + uint32_t cnt = 0; + uint32_t temp = 0; + do { + ENSURE_OR_GO_EXIT(i < inLen); + temp = temp << (7 * cnt); + temp = temp | (input[i] & 0x7F); + cnt++; + } while (input[i++] > 0x7F); + + taglen = taglen - (cnt - 1); + ENSURE_OR_GO_EXIT(outBufindex < (*outLen)); + output[outBufindex++] = temp; + } + break; + } + else { + if (tag == 0x06) { + i = i + taglen; + if (i > inLen) + goto exit; + } + } + } + else { + goto exit; + } + } + + *outLen = outBufindex; + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_asn1_get_oid_from_sssObj(sss_object_t *pkeyObject, uint32_t *output, uint8_t *outLen) +{ + sss_status_t status = kStatus_SSS_Fail; + uint8_t pbKey[256] = {0}; + size_t pbKeyBitLen = 0; + size_t pbKeyBytetLen = sizeof(pbKey); + + ENSURE_OR_GO_EXIT(pkeyObject != NULL); + ENSURE_OR_GO_EXIT(output != NULL); + ENSURE_OR_GO_EXIT(outLen != NULL); + + status = sss_key_store_get_key(pkeyObject->keyStore, pkeyObject, pbKey, &pbKeyBytetLen, &pbKeyBitLen); + + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_util_asn1_get_oid_from_header(pbKey, pbKeyBytetLen, output, outLen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_pkcs8_asn1_get_ec_public_key_index( + const uint8_t *input, size_t inLen, uint16_t *outkeyIndex, size_t *publicKeyLen) +{ + size_t i = 0; + size_t taglen = 0; + sss_status_t status = kStatus_SSS_Fail; + uint8_t value_index = 0; + + ENSURE_OR_GO_EXIT(input != NULL); + ENSURE_OR_GO_EXIT(outkeyIndex != NULL); + ENSURE_OR_GO_EXIT(publicKeyLen != NULL); + + for (;;) { + ENSURE_OR_GO_EXIT(i < inLen); + int tag = input[i++]; + if (IS_VALID_TAG(tag)) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i++]; + if (taglen == 0x81) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i]; + i = i + 1; + } + else if (taglen == 0x82) { + ENSURE_OR_GO_EXIT(i < (inLen - 1)); + taglen = ((input[i] << (0 * 8)) & 0x00FF) + ((input[i + 1] << (1 * 8)) & 0xFF00); + i = i + 2; + } + + if (taglen > inLen) + goto exit; + + value_index = (uint8_t)i; + + if (tag == ASN_TAG_SEQUENCE) { + if (i + taglen != inLen) { + i = i + taglen; + } + + continue; + } + + if (tag == ASN_TAG_BITSTRING) { + *outkeyIndex = value_index; + *publicKeyLen = taglen; + ENSURE_OR_GO_EXIT(value_index < inLen); + if (input[value_index] == 0x00 || input[value_index] == 0x01) { + *outkeyIndex = *outkeyIndex + 1; + *publicKeyLen = *publicKeyLen - 1; + } + break; + } + } + else { + goto exit; + } + } + + ENSURE_OR_GO_EXIT((*outkeyIndex) < inLen); + ENSURE_OR_GO_EXIT(((*outkeyIndex) + (*publicKeyLen)) <= inLen); + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_pkcs8_asn1_get_ec_pair_key_index(const uint8_t *input, + size_t inLen, + uint16_t *pubkeyIndex, + size_t *publicKeyLen, + uint16_t *prvkeyIndex, + size_t *privateKeyLen) +{ + size_t i = 0; + size_t taglen = 0; + sss_status_t status = kStatus_SSS_Fail; + //uint8_t octate_string_start = 0; + + ENSURE_OR_GO_EXIT(input != NULL); + ENSURE_OR_GO_EXIT(pubkeyIndex != NULL); + ENSURE_OR_GO_EXIT(publicKeyLen != NULL); + ENSURE_OR_GO_EXIT(prvkeyIndex != NULL); + ENSURE_OR_GO_EXIT(privateKeyLen != NULL); + + for (;;) { + ENSURE_OR_GO_EXIT(i < inLen); + int tag = input[i++]; + if (IS_VALID_TAG(tag)) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i++]; + if (taglen == 0x81) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i]; + i = i + 1; + } + else if (taglen == 0x82) { + ENSURE_OR_GO_EXIT(i < (inLen - 1)); + taglen = input[i] | input[i + 1] << 8; + i = i + 2; + } + + if (taglen > inLen) + goto exit; + + if (tag == ASN_TAG_OCTETSTRING) { + if (i + taglen == inLen) { + continue; + } + else { + *prvkeyIndex = (uint16_t)i; + *privateKeyLen = taglen; + } + } + + if (tag == ASN_TAG_BITSTRING) { + *pubkeyIndex = (uint16_t)i; + *publicKeyLen = taglen; + ENSURE_OR_GO_EXIT(i < inLen); + if (input[i] == 0x00 || input[i] == 0x01) { + *pubkeyIndex = *pubkeyIndex + 1; + *publicKeyLen = *publicKeyLen - 1; + } + break; + } + + if (i + taglen == inLen) { + continue; + } + else { + i = i + taglen; + } + } + else { + goto exit; + } + } + + ENSURE_OR_GO_EXIT((*pubkeyIndex) < inLen); + ENSURE_OR_GO_EXIT(((*pubkeyIndex) + (*publicKeyLen)) <= inLen); + ENSURE_OR_GO_EXIT((*prvkeyIndex) < inLen); + ENSURE_OR_GO_EXIT(((*prvkeyIndex) + (*privateKeyLen)) <= inLen); + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_rfc8410_asn1_get_ec_pair_key_index(const uint8_t *input, + size_t inLen, + uint16_t *pubkeyIndex, + size_t *publicKeyLen, + uint16_t *prvkeyIndex, + size_t *privateKeyLen) +{ + size_t i = 0; + size_t taglen = 0; + sss_status_t status = kStatus_SSS_Fail; + //uint8_t octate_string_start = 0; + + ENSURE_OR_GO_EXIT(input != NULL); + ENSURE_OR_GO_EXIT(pubkeyIndex != NULL); + ENSURE_OR_GO_EXIT(publicKeyLen != NULL); + ENSURE_OR_GO_EXIT(prvkeyIndex != NULL); + ENSURE_OR_GO_EXIT(privateKeyLen != NULL); + + for (;;) { + ENSURE_OR_GO_EXIT(i < inLen); + int tag = input[i++]; + if (IS_VALID_RFC8410_TAG(tag)) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i++]; + if (taglen == 0x81) { + ENSURE_OR_GO_EXIT(i < inLen); + taglen = input[i]; + i = i + 1; + } + else if (taglen == 0x82) { + ENSURE_OR_GO_EXIT(i < (inLen - 1)); + taglen = ((input[i] << (0 * 8)) & 0x00FF) + ((input[i + 1] << (1 * 8)) & 0xFF00); + i = i + 2; + } + + if (taglen > inLen) + goto exit; + + if (tag == ASN_TAG_OCTETSTRING) { + // With RFC8410, the private key is an Octet String packed inside an Octet String + // Following code will only work for Lengths upto 127 byte + ENSURE_OR_GO_EXIT(taglen >= 2); + ENSURE_OR_GO_EXIT(ASN_TAG_OCTETSTRING == input[i]); + ENSURE_OR_GO_EXIT(taglen - 2 == (size_t)(input[i + 1])); + i += 2; + taglen -= 2; + *prvkeyIndex = (uint16_t)i; + *privateKeyLen = taglen; + } + + if (tag == (ASN_TAG_CNT_SPECIFIC_PRIMITIVE | 0x01)) { + *pubkeyIndex = (uint16_t)i; + *publicKeyLen = taglen; + ENSURE_OR_GO_EXIT(i < inLen); + if (input[i] == 0x00 || input[i] == 0x01) { + *pubkeyIndex = *pubkeyIndex + 1; + *publicKeyLen = *publicKeyLen - 1; + } + break; + } + + if (i + taglen == inLen) { + continue; + } + else { + i = i + taglen; + } + } + else { + goto exit; + } + } + + ENSURE_OR_GO_EXIT((*pubkeyIndex) < inLen); + ENSURE_OR_GO_EXIT(((*pubkeyIndex) + (*publicKeyLen)) <= inLen); + ENSURE_OR_GO_EXIT((*prvkeyIndex) < inLen); + ENSURE_OR_GO_EXIT(((*prvkeyIndex) + (*privateKeyLen)) <= inLen); + status = kStatus_SSS_Success; +exit: + return status; +} + +sss_status_t sss_util_openssl_read_pkcs12( + const char *pkcs12_cert, const char *password, uint8_t *private_key, uint8_t *cert) +{ + sss_status_t retval = kStatus_SSS_Success; + +#if SSS_HAVE_OPENSSL + int status = 0; + FILE *pkcs12_cert_file; + PKCS12 *p12_cert; + X509 *x509_cert; + EVP_PKEY *p_key; + BIO *pem_key_bio = BIO_new(BIO_s_mem()); + BIO *cert_bio = BIO_new(BIO_s_mem()); + STACK_OF(X509) *additional_certs = NULL; + + ENSURE_OR_GO_EXIT(pkcs12_cert != NULL); + ENSURE_OR_GO_EXIT(password != NULL); + ENSURE_OR_GO_EXIT(private_key != NULL); + ENSURE_OR_GO_EXIT(cert != NULL); + + // Open PKCS12 certificate file + pkcs12_cert_file = fopen(pkcs12_cert, "rb"); + if (pkcs12_cert_file == NULL) { + retval = kStatus_SSS_Fail; + goto exit; + } + p12_cert = d2i_PKCS12_fp(pkcs12_cert_file, NULL); + fclose(pkcs12_cert_file); + + // Parse PKCS12 key and certificates to seperate pem and certificates + status = PKCS12_parse(p12_cert, password, &p_key, &x509_cert, &additional_certs); + if (!status) { + retval = kStatus_SSS_Fail; + goto exit; + } + PKCS12_free(p12_cert); + + // Dump pem key to buffer + PEM_write_bio_PrivateKey(pem_key_bio, p_key, NULL, NULL, 0, NULL, NULL); + BIO_read(pem_key_bio, private_key, 10000); + + // Dump certificate to buffer + PEM_write_bio_X509(cert_bio, x509_cert); + BIO_read(cert_bio, cert, 20000); + +exit: +#endif + return retval; +} + +sss_status_t sss_util_openssl_write_pkcs12(const char *pkcs12_cert, + const char *password, + const char *ref_key, + long ref_key_length, + const char *cert, + long cert_length) +{ + sss_status_t retval = kStatus_SSS_Success; + +#if SSS_HAVE_OPENSSL + FILE *pkcs12_file; + X509 *x509_cert = 0; + EVP_PKEY *p_key = 0; + PKCS12 *p12; + BIO *pem_key_bio = BIO_new(BIO_s_mem()); + BIO *pem_cert_bio = BIO_new(BIO_s_mem()); + + ENSURE_OR_GO_EXIT(pkcs12_cert != NULL); + ENSURE_OR_GO_EXIT(password != NULL); + ENSURE_OR_GO_EXIT(ref_key != NULL); + ENSURE_OR_GO_EXIT(cert != NULL); + + // Parse Private key + BIO_write(pem_key_bio, ref_key, ref_key_length); + PEM_read_bio_PrivateKey(pem_key_bio, &p_key, NULL, NULL); + if (p_key == NULL) { + retval = kStatus_SSS_Fail; + goto exit; + } + + BIO_write(pem_cert_bio, cert, cert_length); + PEM_read_bio_X509(pem_cert_bio, &x509_cert, NULL, NULL); + if (x509_cert == NULL) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Generate PKCS12 key and certificate +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + p12 = PKCS12_create((char *)password, +#else + p12 = PKCS12_create(password, +#endif + NULL, + p_key, + x509_cert, + NULL, + 0, + 0, + PKCS12_DEFAULT_ITER, + 1, + NID_key_usage); + if (p12 == NULL) { + retval = kStatus_SSS_Fail; + goto exit; + } + + //write into file + pkcs12_file = fopen(pkcs12_cert, "wb"); + if (i2d_PKCS12_fp(pkcs12_file, p12) != 1) { + retval = kStatus_SSS_Fail; + } + + if (pkcs12_file != NULL) { + fclose(pkcs12_file); + } +exit: +#endif + + return retval; +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c new file mode 100644 index 00000000000..15309bd88d0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c @@ -0,0 +1,553 @@ +/* +* The RSA public-key cryptosystem +* +* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved +* Copyright 2019,2020 NXP, All Rights Reserved +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* This file is part of mbed TLS (https://tls.mbed.org) +*/ + +/* +* The following sources were referenced in the design of this implementation +* of the RSA algorithm: +* +* [1] A method for obtaining digital signatures and public-key cryptosystems +* R Rivest, A Shamir, and L Adleman +* http://people.csail.mit.edu/rivest/pubs.html#RSA78 +* +* [2] Handbook of Applied Cryptography - 1997, Chapter 8 +* Menezes, van Oorschot and Vanstone +* +* [3] Malware Guard Extension: Using SGX to Conceal Cache Attacks +* Michael Schwarz, Samuel Weiser, Daniel Gruss, Clementine Maurice and +* Stefan Mangard +* https://arxiv.org/abs/1702.08719v2 +* +*/ + +#include +#include +#include +#include + +#if SSS_HAVE_APPLET_SE05X_IOT && SSSFTR_RSA + +#include "se05x_APDU.h" + +uint8_t pkcs1_v15_encode( + sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen) +{ + size_t oid_size = 0; + size_t nb_pad = 0; + unsigned char *p = out; + /* clang-format off */ + char oid1[16] = { 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, }; + /* clang-format on */ + size_t outlength = 0; + uint16_t key_size_bytes = 0; + smStatus_t ret_val = SM_NOT_OK; + + /* Constants */ + const uint8_t RSA_Sign = 0x01; + const uint8_t ASN1_sequence = 0x10; + const uint8_t ASN1_constructed = 0x20; + const uint8_t ASN1_oid = 0x06; + const uint8_t ASN1_null = 0x05; + const uint8_t ASN1_octat_string = 0x04; + + ret_val = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &key_size_bytes); + if (ret_val != SM_OK) { + return 1; + } + + outlength = key_size_bytes; + nb_pad = outlength; + + switch (context->algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + oid1[0] = 0x2b; + oid1[1] = 0x0e; + oid1[2] = 0x03; + oid1[3] = 0x02; + oid1[4] = 0x1a; + oid_size = 5; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + oid1[8] = 0x04; + oid_size = 9; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + oid1[8] = 0x01; + oid_size = 9; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + oid1[8] = 0x02; + oid_size = 9; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + oid1[8] = 0x03; + oid_size = 9; + break; + default: + return 1; + } + + if (outlength < (hashlen + oid_size + 6 /* DigestInfo TLV overhead */)) { + LOG_E("Intended encoded message length too short"); + return 1; + } + + if (*outLen < outlength) { + LOG_E("Out buffer memory is less "); + return 1; + } + *outLen = outlength; + + /* Double-check that 8 + hashlen + oid_size can be used as a + * 1-byte ASN.1 length encoding and that there's no overflow. */ + if (8 + hashlen + oid_size >= 0x80) + return 1; + + /* + * Static bounds check: + * - Need 10 bytes for five tag-length pairs. + * (Insist on 1-byte length encodings to protect against variants of + * Bleichenbacher's forgery attack against lax PKCS#1v1.5 verification) + * - Need hashlen bytes for hash + * - Need oid_size bytes for hash alg OID. + */ + if (nb_pad < 10 + hashlen + oid_size) + return 1; + nb_pad -= 10 + hashlen + oid_size; + + /* Need space for signature header and padding delimiter (3 bytes), + * and 8 bytes for the minimal padding */ + if (nb_pad < 3 + 8) + return 1; + nb_pad -= 3; + + /* Now nb_pad is the amount of memory to be filled + * with padding, and at least 8 bytes long. */ + + /* Write signature header and padding */ + *p++ = 0; + *p++ = RSA_Sign; + memset(p, 0xFF, nb_pad); + p += nb_pad; + *p++ = 0; + + /* Signing hashed data, add corresponding ASN.1 structure + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm DigestAlgorithmIdentifier, + * digest Digest } + * DigestAlgorithmIdentifier ::= AlgorithmIdentifier + * Digest ::= OCTET STRING + * + * Schematic: + * TAG-SEQ + LEN [ TAG-SEQ + LEN [ TAG-OID + LEN [ OID ] + * TAG-NULL + LEN [ NULL ] ] + * TAG-OCTET + LEN [ HASH ] ] + */ + *p++ = ASN1_sequence | ASN1_constructed; + *p++ = (unsigned char)(0x08 + oid_size + hashlen); + *p++ = ASN1_sequence | ASN1_constructed; + *p++ = (unsigned char)(0x04 + oid_size); + *p++ = ASN1_oid; + *p++ = (unsigned char)oid_size; + memcpy(p, oid1, oid_size); + p += oid_size; + *p++ = ASN1_null; + *p++ = 0x00; + *p++ = ASN1_octat_string; + *p++ = (unsigned char)hashlen; + memcpy(p, hash, hashlen); + p += hashlen; + + /* Just a sanity-check, should be automatic + * after the initial bounds check. */ + if (p != out + outlength) { + memset(out, 0, outlength); + return 1; + } + + return 0; +} + +uint8_t pkcs1_v15_encode_no_hash( + sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen) +{ + uint16_t key_size_bytes = 0; + smStatus_t ret_val = SM_NOT_OK; + + ret_val = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &key_size_bytes); + if (ret_val != SM_OK) { + return 1; + } + + if (hashlen > (size_t)(key_size_bytes - 11)) { + return 1; + } + + if (*outLen < key_size_bytes) { + return 1; + } + + memset(out, 0xFF, *outLen); + out[0] = 0x00; + out[1] = 0x01; + out[key_size_bytes - hashlen - 1] = 0x00; + memcpy(&out[key_size_bytes - hashlen], hash, hashlen); + + *outLen = key_size_bytes; + + return 0; +} + +uint8_t sss_mgf_mask_func(uint8_t *dst, + size_t dlen, + uint8_t *src, + size_t slen, + sss_algorithm_t sha_algorithm, + sss_se05x_asymmetric_t *context) +{ + uint8_t mask[64]; /* MAX - SHA512*/ + uint8_t counter[4]; + uint8_t *p; + size_t i, use_len; + uint8_t ret = 1; + sss_status_t status = kStatus_SSS_Fail; + sss_digest_t digest; + size_t digestLen = 512; /* MAX - SHA512*/ + size_t hashlength = slen; + + memset(mask, 0, 64); + memset(counter, 0, 4); + + status = sss_digest_context_init(&digest, (sss_session_t *)context->session, sha_algorithm, kMode_SSS_Digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + /* Generate and apply dbMask */ + p = dst; + + while (dlen > 0) { + use_len = hashlength; + if (dlen < hashlength) + use_len = dlen; + + status = sss_digest_init(&digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, src, slen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, counter, 4); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_finish(&digest, mask, &digestLen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + for (i = 0; i < use_len; ++i) + *p++ ^= mask[i]; + + counter[3]++; + + dlen -= use_len; + } + + sss_digest_context_free(&digest); + + ret = 0; + +exit: + return ret; +} + +// Note-1: This function does not implement the full EMSA-PSS Encoding Operation operation +// (refer to RFC 8017 Section 9.1 Figure 2), the caller MUST pass 'mHash' (= Hash(M)) as input +// via function argument(s) hash / haslen. +// +// Note-2: Any hash value passed as input that does not match (in byte length) +// the hash requested for the signature (kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHAxxx) +// will be rejected. +// +uint8_t emsa_encode(sss_se05x_asymmetric_t *context, const uint8_t *hash, size_t hashlen, uint8_t *out, size_t *outLen) +{ + size_t outlength = 0; + uint8_t *p = out; + uint8_t salt[64] = { + 0, + }; + uint32_t saltlength = 0; + uint32_t hashlength = 0; + uint32_t offset = 0; + uint8_t ret = 1; + size_t msb; + sss_rng_context_t rng; + sss_digest_t digest; + sss_algorithm_t sha_algorithm = kAlgorithm_None; + size_t digestLen = 512; /* MAX - SHA512*/ + sss_status_t status = kStatus_SSS_Fail; + uint16_t key_size_bytes = 0; + smStatus_t ret_val = SM_NOT_OK; + + ret_val = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &key_size_bytes); + if (ret_val != SM_OK) { + goto exit; + } + + outlength = key_size_bytes; + + switch (context->algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + hashlength = 20; + sha_algorithm = kAlgorithm_SSS_SHA1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + hashlength = 28; + sha_algorithm = kAlgorithm_SSS_SHA224; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + if (key_size_bytes <= 64) { /* RSA Key size = 512 */ + LOG_E("SHA256 not supported with this RSA key"); + goto exit; + } + hashlength = 32; + sha_algorithm = kAlgorithm_SSS_SHA256; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + if (key_size_bytes <= 64) { /* RSA Key size = 512 */ + LOG_E("SHA384 not supported with this RSA key"); + goto exit; + } + hashlength = 48; + sha_algorithm = kAlgorithm_SSS_SHA384; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + if (key_size_bytes <= 128) { /* RSA Key size = 1024 and 512 */ + LOG_E("SHA512 not supported with this RSA key"); + goto exit; + } + hashlength = 64; + sha_algorithm = kAlgorithm_SSS_SHA512; + break; + default: + goto exit; + } + + if (hashlength != hashlen) { + ret_val = SM_NOT_OK; + goto exit; + } + + saltlength = hashlength; + *outLen = outlength; + + /* Generate salt of length saltlength */ + status = sss_rng_context_init(&rng, (sss_session_t *)context->session /* session */); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_rng_get_random(&rng, salt, saltlength); + if (status != kStatus_SSS_Success) { + goto exit; + } + + msb = (outlength * 8) - 1; + p += outlength - hashlength * 2 - 2; + *p++ = 0x01; + memcpy(p, salt, saltlength); + p += saltlength; + + status = sss_digest_context_init(&digest, (sss_session_t *)context->session, sha_algorithm, kMode_SSS_Digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_init(&digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, p, 8); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, hash, hashlen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, salt, saltlength); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_finish(&digest, p, &digestLen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + sss_digest_context_free(&digest); + + if (msb % 8 == 0) + offset = 1; + + /* Apply MGF Mask */ + if (0 != + sss_mgf_mask_func(out + offset, outlength - hashlength - 1 - offset, p, hashlength, sha_algorithm, context)) + goto exit; + + out[0] &= 0xFF >> (outlength * 8 - msb); + + p += hashlength; + *p++ = 0xBC; + + ret = 0; + +exit: + return ret; +} + +uint8_t emsa_decode_and_compare( + sss_se05x_asymmetric_t *context, uint8_t *sig, size_t siglen, uint8_t *hash, size_t hashlen) +{ + uint8_t *p; + uint8_t *hash_start; + uint8_t result[512]; + uint8_t ret = 1; + uint32_t hlen; + uint8_t zeros[8]; + uint32_t observed_salt_len, msb; + uint8_t buf[1024]; + sss_algorithm_t sha_algorithm = kAlgorithm_None; + sss_digest_t digest; + size_t digestLen = 512; /* MAX - SHA512*/ + sss_status_t status = kStatus_SSS_Fail; + + memcpy(buf, sig, siglen); + + switch (context->algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + hlen = 20; + sha_algorithm = kAlgorithm_SSS_SHA1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + hlen = 28; + sha_algorithm = kAlgorithm_SSS_SHA224; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + hlen = 32; + sha_algorithm = kAlgorithm_SSS_SHA256; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + hlen = 48; + sha_algorithm = kAlgorithm_SSS_SHA384; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + hlen = 64; + sha_algorithm = kAlgorithm_SSS_SHA512; + break; + default: + goto exit; + } + + p = buf; + + if (buf[siglen - 1] != 0xBC) { + goto exit; + } + + memset(zeros, 0, 8); + + msb = (hlen * 8) - 1; + + if (buf[0] >> (8 - siglen * 8 + msb)) + goto exit; + + if (siglen < hlen + 2) + goto exit; + hash_start = p + siglen - hlen - 1; + + if (0 != sss_mgf_mask_func(p, siglen - hlen - 1, hash_start, hlen, sha_algorithm, context)) + goto exit; + + buf[0] &= 0xFF >> ((siglen * 8 - msb) % 8); + + while (p < hash_start - 1 && *p == 0) + p++; + + if (*p++ != 0x01) { + goto exit; + } + + observed_salt_len = hash_start - p; + + status = sss_digest_context_init(&digest, (sss_session_t *)context->session, sha_algorithm, kMode_SSS_Digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_init(&digest); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, zeros, 8); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, hash, hashlen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_update(&digest, p, observed_salt_len); + if (status != kStatus_SSS_Success) { + goto exit; + } + + status = sss_digest_finish(&digest, result, &digestLen); + if (status != kStatus_SSS_Success) { + goto exit; + } + + sss_digest_context_free(&digest); + + if (memcmp(hash_start, result, hlen) != 0) { + goto exit; + } + + ret = 0; + +exit: + return ret; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c new file mode 100644 index 00000000000..63630467fed --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c @@ -0,0 +1,291 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common Key store implementation between keystore_a7x and keystore_pc */ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#include +#include +#include +#include +#include + +/* ************************************************************************** */ +/* Local Defines */ +/* ************************************************************************** */ + +#define KEYSTORE_MAGIC (0xA71C401L) +#define KEYSTORE_VERSION (0x0004) + +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Static function declarations */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Public Functions */ +/* ************************************************************************** */ + +void ks_common_init_fat(keyStoreTable_t *keystore_shadow, keyIdAndTypeIndexLookup_t *lookup_entires, size_t max_entries) +{ + memset(keystore_shadow, 0, sizeof(*keystore_shadow)); + keystore_shadow->magic = KEYSTORE_MAGIC; + keystore_shadow->version = KEYSTORE_VERSION; + keystore_shadow->maxEntries = (uint16_t)max_entries; + keystore_shadow->entries = lookup_entires; + memset(keystore_shadow->entries, 0, sizeof(*lookup_entires) * max_entries); +} + +sss_status_t ks_common_update_fat(keyStoreTable_t *keystore_shadow, + uint32_t extId, + sss_key_part_t key_part, + sss_cipher_type_t cipherType, + uint8_t intIndex, + uint32_t accessPermission, + uint16_t keyLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + uint32_t i; + bool found_entry = FALSE; + uint8_t slots_req = 1; + uint8_t entries_written = 0; + uint16_t keyLen_roundoff = 0; + retval = isValidKeyStoreShadow(keystore_shadow); + if (retval != kStatus_SSS_Success) + goto cleanup; + for (i = 0; i < keystore_shadow->maxEntries; i++) { + keyIdAndTypeIndexLookup_t *keyEntry = &keystore_shadow->entries[i]; + if (keyEntry->extKeyId == extId) { + LOG_W("ENTRY already exists 0x%04X", extId); + retval = kStatus_SSS_Fail; + found_entry = TRUE; + break; + } + } + + if (key_part == kSSS_KeyPart_Default && (cipherType == kSSS_CipherType_AES || cipherType == kSSS_CipherType_HMAC)) { + keyLen_roundoff = ((keyLen / 16) * 16) + ((keyLen % 16) == 0 ? 0 : 16); + slots_req = (keyLen_roundoff / 16); + } + + if (!found_entry) { + retval = kStatus_SSS_Fail; + for (i = 0; i < keystore_shadow->maxEntries; i++) { + keyIdAndTypeIndexLookup_t *keyEntry = &keystore_shadow->entries[i]; + if (keyEntry->extKeyId == 0) { + keyEntry->extKeyId = extId; + keyEntry->keyIntIndex = intIndex; + keyEntry->keyPart = key_part | ((slots_req - 1) << 4); + keyEntry->cipherType = cipherType; + //keyEntry->accessPermission = accessPermission; + + entries_written++; + if (entries_written == slots_req) { + retval = kStatus_SSS_Success; + break; + } + } + } + } +cleanup: + return retval; +} + +sss_status_t ks_common_remove_fat(keyStoreTable_t *keystore_shadow, uint32_t extId) +{ + sss_status_t retval = kStatus_SSS_Fail; + uint32_t i; + bool found_entry = FALSE; + retval = isValidKeyStoreShadow(keystore_shadow); + if (retval != kStatus_SSS_Success) + goto cleanup; + + for (i = 0; i < keystore_shadow->maxEntries; i++) { + keyIdAndTypeIndexLookup_t *keyEntry = &keystore_shadow->entries[i]; + if (keyEntry->extKeyId == extId) { + retval = kStatus_SSS_Success; + memset(keyEntry, 0, sizeof(keyIdAndTypeIndexLookup_t)); + found_entry = TRUE; + } + } + if (!found_entry) { + retval = kStatus_SSS_Fail; + } +cleanup: + return retval; +} + +/* ************************************************************************** */ +/* Private Functions */ +/* ************************************************************************** */ + +sss_status_t keystore_shadow_From2_To_3(keyStoreTable_t *keystore_shadow) +{ + int i = 0; + for (i = 0; i < keystore_shadow->maxEntries; i++) { + keyIdAndTypeIndexLookup_t *keyEntry = &keystore_shadow->entries[i]; + if (keyEntry != NULL) { + uint16_t org_keyIntIndex = (keyEntry->cipherType) | ((keyEntry->keyIntIndex) << 8); + + switch (keyEntry->keyPart) { + case 0: + continue; + case 1: + keyEntry->keyPart = kSSS_KeyPart_Default; + keyEntry->cipherType = kSSS_CipherType_Certificate; + break; + case 2: + keyEntry->keyPart = kSSS_KeyPart_Default; + keyEntry->cipherType = kSSS_CipherType_AES; + break; + case 3: + keyEntry->keyPart = kSSS_KeyPart_Default; + keyEntry->cipherType = kSSS_CipherType_DES; + break; + case 4: + keyEntry->keyPart = kSSS_KeyPart_Default; + keyEntry->cipherType = kSSS_CipherType_CMAC; + break; +#if SSSFTR_RSA + case 5: + keyEntry->keyPart = kSSS_KeyPart_Public; + keyEntry->cipherType = kSSS_CipherType_RSA_CRT; + break; +#endif + case 6: + keyEntry->keyPart = kSSS_KeyPart_Public; + keyEntry->cipherType = kSSS_CipherType_EC_NIST_P; + break; + case 7: + keyEntry->keyPart = kSSS_KeyPart_Public; + keyEntry->cipherType = kSSS_CipherType_EC_MONTGOMERY; + break; + case 8: + keyEntry->keyPart = kSSS_KeyPart_Public; + keyEntry->cipherType = kSSS_CipherType_EC_TWISTED_ED; + break; +#if SSSFTR_RSA + case 9: + keyEntry->keyPart = kSSS_KeyPart_Private; + keyEntry->cipherType = kSSS_CipherType_RSA_CRT; + break; +#endif + case 10: + keyEntry->keyPart = kSSS_KeyPart_Private; + keyEntry->cipherType = kSSS_CipherType_EC_NIST_P; + break; + case 11: + keyEntry->keyPart = kSSS_KeyPart_Private; + keyEntry->cipherType = kSSS_CipherType_EC_MONTGOMERY; + break; + case 12: + keyEntry->keyPart = kSSS_KeyPart_Private; + keyEntry->cipherType = kSSS_CipherType_EC_TWISTED_ED; + break; +#if SSSFTR_RSA + case 13: + keyEntry->keyPart = kSSS_KeyPart_Pair; + keyEntry->cipherType = kSSS_CipherType_RSA_CRT; + break; +#endif + case 14: + keyEntry->keyPart = kSSS_KeyPart_Pair; + keyEntry->cipherType = kSSS_CipherType_EC_NIST_P; + break; + case 15: + keyEntry->keyPart = kSSS_KeyPart_Pair; + keyEntry->cipherType = kSSS_CipherType_EC_MONTGOMERY; + break; + case 16: + keyEntry->keyPart = kSSS_KeyPart_Pair; + keyEntry->cipherType = kSSS_CipherType_EC_TWISTED_ED; + break; + case 17: + keyEntry->keyPart = kSSS_KeyPart_Default; + keyEntry->cipherType = kSSS_CipherType_UserID; + break; + default: + LOG_E("Error in keystore_shadow_From2_To_3"); + return kStatus_SSS_Fail; + } + + keyEntry->keyIntIndex = (uint8_t)org_keyIntIndex; + } + } + + return kStatus_SSS_Success; +} + +sss_status_t keystore_shadow_From3_To_4(keyStoreTable_t *keystore_shadow) +{ + int i = 0; + for (i = 0; i < keystore_shadow->maxEntries; i++) { + keyIdAndTypeIndexLookup_t *keyEntry = &keystore_shadow->entries[i]; + if (keyEntry != NULL) { + switch (keyEntry->keyPart) { + case kSSS_KeyPart_NONE: + break; + case kSSS_KeyPart_Default: + if (keyEntry->cipherType == kSSS_CipherType_Certificate) { + keyEntry->cipherType = kSSS_CipherType_Binary; + } + break; + default: + LOG_E("Error in keystore_shadow_From3_To_4"); + return kStatus_SSS_Fail; + } + } + } + + return kStatus_SSS_Success; +} + +sss_status_t isValidKeyStoreShadow(keyStoreTable_t *keystore_shadow) +{ + sss_status_t retval = kStatus_SSS_Success; + if (keystore_shadow != NULL) { + if (keystore_shadow->magic != KEYSTORE_MAGIC) { + LOG_E("Mismatch.keystore_shadow->magic and KEYSTORE_MAGIC"); + retval = kStatus_SSS_Fail; + goto cleanup; + } + if (keystore_shadow->version != KEYSTORE_VERSION) { + if (keystore_shadow->version == 0x0002) { + retval = keystore_shadow_From2_To_3(keystore_shadow); + retval = keystore_shadow_From3_To_4(keystore_shadow); + } + else if (keystore_shadow->version == 0x0003) { + retval = keystore_shadow_From3_To_4(keystore_shadow); + } + else { + LOG_E(" Version mismatch."); + retval = kStatus_SSS_Fail; + } + goto cleanup; + } + if (keystore_shadow->maxEntries == 0) { + LOG_E("Keystore not yet allocated"); + retval = kStatus_SSS_Fail; + goto cleanup; + } + } + else { + retval = kStatus_SSS_Fail; + } +cleanup: + return retval; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c new file mode 100644 index 00000000000..8fbc6abde6a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c @@ -0,0 +1,224 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Key store in PC : For testing */ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#include +#include +#include +#include +#include + +#include "nxLog_sss.h" +#if SSS_HAVE_OPENSSL +#include + +/* ************************************************************************** */ +/* Local Defines */ +/* ************************************************************************** */ + +/* File allocation table file name */ +#define FAT_FILENAME "sss_fat.bin" +#define MAX_FILE_NAME_SIZE 255 + +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Static function declarations */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Public Functions */ +/* ************************************************************************** */ + +sss_status_t ks_openssl_load_key(sss_openssl_object_t *sss_key, keyStoreTable_t *keystore_shadow, uint32_t extKeyId) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + //const char *root_folder = sss_key->keyStore->session->szRootPath; + size_t size = 0; + uint32_t i; + keyIdAndTypeIndexLookup_t *shadowEntry = NULL; + EVP_PKEY *pkey = NULL; + + for (i = 0; i < sss_key->keyStore->max_object_count; i++) { + if (keystore_shadow->entries[i].extKeyId == extKeyId) { + shadowEntry = &keystore_shadow->entries[i]; + sss_key->keyId = shadowEntry->extKeyId; + sss_key->cipherType = shadowEntry->cipherType; + sss_key->objectType = (shadowEntry->keyPart & 0x0F); + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + retval = kStatus_SSS_Success; + break; + } + } + if (retval == kStatus_SSS_Success) { + fp = fopen(file_name, "rb"); + if (fp == NULL) { + LOG_E("Can not open file"); + retval = kStatus_SSS_Fail; + } + else { + /*Buffer: max RSA key*/ + uint8_t keyBuf[3000]; + const uint8_t *buf_ptr = keyBuf; + long signed_size = 0; + fseek(fp, 0, SEEK_END); + signed_size = ftell(fp); + if (signed_size < 0) { + retval = kStatus_SSS_Fail; + fclose(fp); + return retval; + } + size = (size_t)signed_size; + fseek(fp, 0, SEEK_SET); + if (!fread(keyBuf, size, 1, fp)) { + LOG_E("Error in fread"); + } + fclose(fp); + retval = sss_openssl_key_object_allocate(sss_key, + shadowEntry->extKeyId, + (shadowEntry->keyPart & 0x0F), + shadowEntry->cipherType, + size, + kKeyObject_Mode_Persistent); + if (retval == kStatus_SSS_Success) { + switch (sss_key->cipherType) { + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + if (sss_key->contents != NULL) + SSS_FREE((void *)sss_key->contents); + if (sss_key->objectType == kSSS_KeyPart_Public) + pkey = d2i_PublicKey(EVP_PKEY_RSA, NULL, &buf_ptr, (long)size); + else + pkey = d2i_AutoPrivateKey(NULL, &buf_ptr, (long)size); + + if (pkey == NULL) + retval = kStatus_SSS_Fail; + else + sss_key->contents = (void *)pkey; + + sss_key->keyBitLen = EVP_PKEY_bits(pkey); + } break; + case kSSS_CipherType_EC_NIST_P: + case kSSS_CipherType_EC_NIST_K: + case kSSS_CipherType_EC_BRAINPOOL: + case kSSS_CipherType_EC_MONTGOMERY: + case kSSS_CipherType_EC_TWISTED_ED: { + if (sss_key->contents != NULL) + EVP_PKEY_free((EVP_PKEY *)sss_key->contents); + if (sss_key->objectType == kSSS_KeyPart_Public) + pkey = d2i_PublicKey(EVP_PKEY_EC, NULL, &buf_ptr, (long)size); + else + pkey = d2i_AutoPrivateKey(NULL, &buf_ptr, (long)size); + + if (pkey == NULL) + retval = kStatus_SSS_Fail; + else + sss_key->contents = (void *)pkey; + sss_key->keyBitLen = EVP_PKEY_bits(pkey); + } break; + default: { + retval = sss_openssl_key_store_set_key(sss_key->keyStore, sss_key, keyBuf, size, size * 8, NULL, 0); + } break; + } + } + } + } + return retval; +} + +sss_status_t ks_openssl_store_key(const sss_openssl_object_t *sss_key) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + unsigned char *Buffer = NULL; + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + fp = fopen(file_name, "wb+"); + if (fp == NULL) { + LOG_E("Can not open file"); + retval = kStatus_SSS_Fail; + } + else { + int len = 0; + EVP_PKEY *pk; + pk = (EVP_PKEY *)sss_key->contents; + switch (sss_key->objectType) { + case kSSS_KeyPart_Default: + fwrite(sss_key->contents, sss_key->contents_max_size, 1, fp); + retval = kStatus_SSS_Success; + break; + case kSSS_KeyPart_Pair: + case kSSS_KeyPart_Private: + len = i2d_PrivateKey(pk, NULL); + if (len < 0) + goto exit; + //Buffer = (unsigned char *)malloc(len + 1); + len = i2d_PrivateKey(pk, &Buffer); + if (len < 0) + goto exit; + break; + case kSSS_KeyPart_Public: + len = i2d_PublicKey(pk, NULL); + if (len < 0) + goto exit; + + //Buffer = (unsigned char *)malloc(len + 1); + len = i2d_PublicKey(pk, &Buffer); + if (len < 0) + goto exit; + break; + } + if (len > 0 && retval != kStatus_SSS_Success) { + fwrite(Buffer, len, 1, fp); + retval = kStatus_SSS_Success; + } + } +exit: + if (fp != NULL) + fclose(fp); + if (Buffer != NULL) + SSS_FREE(Buffer); + return retval; +} + +#ifdef _MSC_VER +#define UNLINK _unlink +#else +#define UNLINK unlink +#endif + +sss_status_t ks_openssl_remove_key(const sss_openssl_object_t *sss_key) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + if (0 == UNLINK(file_name)) { + retval = kStatus_SSS_Success; + } + return retval; +} + +/* ************************************************************************** */ +/* Private Functions */ +/* ************************************************************************** */ + +#endif /* OpenSSL */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c new file mode 100644 index 00000000000..002daae06ab --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c @@ -0,0 +1,340 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Key store in PC : For testing */ + +/* ************************************************************************** */ +/* Includes */ +/* ************************************************************************** */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#include + +#if SSS_HAVE_MBEDTLS +#include +#endif + +#if SSS_HAVE_OPENSSL +#include +#endif + +#include +#include +#include +#include + +#include "nxLog_sss.h" +#include "sm_types.h" + +#if (defined(MBEDTLS_FS_IO) && !AX_EMBEDDED) || SSS_HAVE_OPENSSL + +/* ************************************************************************** */ +/* Local Defines */ +/* ************************************************************************** */ + +/* File allocation table file name */ +#define FAT_FILENAME "sss_fat.bin" +#define MAX_FILE_NAME_SIZE 255 + +/* ************************************************************************** */ +/* Structures and Typedefs */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Global Variables */ +/* ************************************************************************** */ + +// keyStoreTable_t gKeyStoreShadow; +// keyIdAndTypeIndexLookup_t gLookupEntires[KS_N_ENTIRES]; + +/* ************************************************************************** */ +/* Static function declarations */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Public Functions */ +/* ************************************************************************** */ + +/* For the key sss_key, what will the file name look like */ +void ks_sw_getKeyFileName( + char *const file_name, const size_t size, const sss_object_t *sss_key, const char *root_folder) +{ + uint32_t keyId = sss_key->keyId; + uint16_t keyType = sss_key->objectType; + uint16_t cipherType = sss_key->cipherType; + SNPRINTF(file_name, size - 1, "%s/sss_%08X_%04d_%04d.bin", root_folder, keyId, keyType, cipherType); +} + +void ks_sw_fat_allocate(keyStoreTable_t **keystore_shadow) +{ + keyStoreTable_t *pKeyStoreShadow = SSS_MALLOC(sizeof(keyStoreTable_t)); + if (pKeyStoreShadow == NULL) { + LOG_E("Error in pKeyStoreShadow mem allocation"); + return; + } + keyIdAndTypeIndexLookup_t *ppLookupEntires = SSS_MALLOC(KS_N_ENTIRES * sizeof(keyIdAndTypeIndexLookup_t)); + if (ppLookupEntires == NULL) { + LOG_E("Error in ppLookupEntires mem allocation"); + SSS_FREE(pKeyStoreShadow); + return; + } + + //for (int i = 0; i < KS_N_ENTIRES; i++) { + // ppLookupEntires[i] = calloc(1, sizeof(keyIdAndTypeIndexLookup_t)); + //} + memset(ppLookupEntires, 0, (KS_N_ENTIRES * sizeof(keyIdAndTypeIndexLookup_t))); + ks_common_init_fat(pKeyStoreShadow, ppLookupEntires, KS_N_ENTIRES); + *keystore_shadow = pKeyStoreShadow; +} + +void ks_sw_fat_free(keyStoreTable_t *keystore_shadow) +{ + if (NULL != keystore_shadow) { + if (NULL != keystore_shadow->entries) { + //for (int i = 0; i < keystore_shadow->maxEntries; i++) { + // free(keystore_shadow->entries[i]); + //} + SSS_FREE(keystore_shadow->entries); + } + memset(keystore_shadow, 0, sizeof(*keystore_shadow)); + SSS_FREE(keystore_shadow); + } +} + +void ks_sw_fat_remove(const char *szRootPath) +{ + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + SNPRINTF(file_name, sizeof(file_name), "%s/" FAT_FILENAME, szRootPath); + fp = fopen(file_name, "rb"); + if (fp == NULL) { + /* OK. File does not exist. */ + } + else { + fclose(fp); +#ifdef _WIN32 + _unlink(file_name); +#else + unlink(file_name); +#endif + } +} + +static sss_status_t ks_sw_fat_update(keyStoreTable_t *keystore_shadow, const char *szRootPath) +{ + sss_status_t retval = kStatus_SSS_Success; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + SNPRINTF(file_name, sizeof(file_name), "%s/" FAT_FILENAME, szRootPath); + fp = fopen(file_name, "wb+"); + if (fp == NULL) { + LOG_E("Can not open the file"); + retval = kStatus_SSS_Fail; + } + else { + fseek(fp, 0, SEEK_SET); + fwrite(keystore_shadow, sizeof(*keystore_shadow), 1, fp); + fwrite(keystore_shadow->entries, sizeof(*keystore_shadow->entries) * keystore_shadow->maxEntries, 1, fp); + fclose(fp); + } + return retval; +} + +#if defined(MBEDTLS_FS_IO) +sss_status_t ks_mbedtls_fat_update(sss_mbedtls_key_store_t *keyStore) +{ + return ks_sw_fat_update(keyStore->keystore_shadow, keyStore->session->szRootPath); +} +#endif + +#if SSS_HAVE_OPENSSL +sss_status_t ks_openssl_fat_update(sss_openssl_key_store_t *keyStore) +{ + return ks_sw_fat_update(keyStore->keystore_shadow, keyStore->session->szRootPath); +} +#endif + +sss_status_t ks_sw_fat_load(const char *szRootPath, keyStoreTable_t *pKeystore_shadow) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + size_t ret; + ENSURE_OR_GO_CLEANUP(pKeystore_shadow); + keyStoreTable_t fileShadow; + SNPRINTF(file_name, sizeof(file_name), "%s/" FAT_FILENAME, szRootPath); + fp = fopen(file_name, "rb"); + if (fp == NULL) { + /* File did not exist, and it's OK most of the time + * because the test code comes through this path. + * hence return fail, but do not log any message. */ + return kStatus_SSS_Fail; + } + + ret = fread(&fileShadow, 1, sizeof(fileShadow), fp); + if (ret > 0 && fileShadow.maxEntries == pKeystore_shadow->maxEntries && + fileShadow.magic == pKeystore_shadow->magic && fileShadow.version == pKeystore_shadow->version) { + ret = + fread(pKeystore_shadow->entries, 1, sizeof(*pKeystore_shadow->entries) * pKeystore_shadow->maxEntries, fp); + if (ret > 0) { + retval = kStatus_SSS_Success; + } + } + else { + LOG_E("ERROR! keystore_shadow != pKeystore_shadow"); + } + fclose(fp); +cleanup: + return retval; +} + +#if defined(MBEDTLS_FS_IO) +sss_status_t ks_mbedtls_load_key(sss_mbedtls_object_t *sss_key, keyStoreTable_t *keystore_shadow, uint32_t extKeyId) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + //const char *root_folder = sss_key->keyStore->session->szRootPath; + size_t size = 0; + uint32_t i; + keyIdAndTypeIndexLookup_t *shadowEntry = NULL; + + for (i = 0; i < sss_key->keyStore->max_object_count; i++) { + if (keystore_shadow->entries[i].extKeyId == extKeyId) { + shadowEntry = &keystore_shadow->entries[i]; + sss_key->keyId = shadowEntry->extKeyId; + sss_key->cipherType = shadowEntry->cipherType; + sss_key->objectType = (shadowEntry->keyPart & 0x0F); + + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + retval = kStatus_SSS_Success; + break; + } + } + if (retval == kStatus_SSS_Success) { + fp = fopen(file_name, "rb"); + if (fp == NULL) { + LOG_E("Can not open file"); + retval = kStatus_SSS_Fail; + } + else { + /* Buffer to hold max RSA Key*/ + uint8_t *keyBuf = NULL; + int signed_val = 0; + fseek(fp, 0, SEEK_END); + signed_val = ftell(fp); + if (signed_val < 0) { + LOG_E("File does not contain any data"); + retval = kStatus_SSS_Fail; + fclose(fp); + return retval; + } + size = (size_t)signed_val; + fseek(fp, 0, SEEK_SET); + keyBuf = SSS_CALLOC(1, size); + signed_val = (int)fread(keyBuf, size, 1, fp); + if (signed_val < 0) { + LOG_E("fread faild"); + retval = kStatus_SSS_Fail; + fclose(fp); + if (keyBuf != NULL) { + SSS_FREE(keyBuf); + } + return retval; + } + fclose(fp); + retval = ks_mbedtls_key_object_create(sss_key, + shadowEntry->extKeyId, + (shadowEntry->keyPart & 0x0F), + shadowEntry->cipherType, + size, + kKeyObject_Mode_Persistent); + if (retval == kStatus_SSS_Success) { + retval = sss_mbedtls_key_store_set_key( + sss_key->keyStore, sss_key, keyBuf, size, size * 8 /* FIXME */, NULL, 0); + } + if (keyBuf != NULL) { + SSS_FREE(keyBuf); + } + } + } + return retval; +} + +sss_status_t ks_mbedtls_store_key(const sss_mbedtls_object_t *sss_key) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + FILE *fp = NULL; + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + fp = fopen(file_name, "wb+"); + if (fp == NULL) { + LOG_E(" Can not open the file"); + retval = kStatus_SSS_Fail; + } + else { + /* Buffer to hold max RSA Key*/ + uint8_t key_buf[3000]; + int ret = 0; + unsigned char *c = key_buf; + memset(key_buf, 0, sizeof(key_buf)); + mbedtls_pk_context *pk; + pk = (mbedtls_pk_context *)sss_key->contents; + switch (sss_key->objectType) { + case kSSS_KeyPart_Default: + fwrite(sss_key->contents, sss_key->contents_max_size, 1, fp); + retval = kStatus_SSS_Success; /* Allows to skip writing pem/der files */ + break; + case kSSS_KeyPart_Pair: + case kSSS_KeyPart_Private: + ret = mbedtls_pk_write_key_der(pk, key_buf, sizeof(key_buf)); + break; + case kSSS_KeyPart_Public: + ret = mbedtls_pk_write_pubkey_der(pk, key_buf, sizeof(key_buf)); + break; + } + if (ret > 0 && retval != kStatus_SSS_Success) { + c = key_buf + sizeof(key_buf) - ret; + fwrite(c, ret, 1, fp); + retval = kStatus_SSS_Success; + } + fflush(fp); + fclose(fp); + } + return retval; +} + +#ifdef _MSC_VER +#define UNLINK _unlink +#else +#define UNLINK unlink +#endif + +sss_status_t ks_mbedtls_remove_key(const sss_mbedtls_object_t *sss_key) +{ + sss_status_t retval = kStatus_SSS_Fail; + char file_name[MAX_FILE_NAME_SIZE]; + ks_sw_getKeyFileName( + file_name, sizeof(file_name), (const sss_object_t *)sss_key, sss_key->keyStore->session->szRootPath); + if (0 == UNLINK(file_name)) { + retval = kStatus_SSS_Success; + } + return retval; +} +#endif + +/* ************************************************************************** */ +/* Private Functions */ +/* ************************************************************************** */ + +#endif /* MBEDTLS_FS_IO */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c new file mode 100644 index 00000000000..b8d4e82cfc0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c @@ -0,0 +1,3181 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define MBEDTLS_DO_LITTLE_ENDIAN + +#if SSS_HAVE_MBEDTLS + +#include +#include +#ifdef MBEDTLS_FS_IO +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// #include "../../ex/inc/ex_sss_objid.h" // Enable to test SIMW-656 + +#define MAX_KEY_OBJ_COUNT KS_N_ENTIRES +#define MAX_FILE_NAME_SIZE 255 +#define MAX_SHARED_SECRET_DERIVED_DATA 255 +#define BEGIN_PRIVATE "-----BEGIN PRIVATE KEY-----\n" +#define END_PRIVATE "\n-----END PRIVATE KEY-----" +#define BEGIN_PUBLIC "-----BEGIN PUBLIC KEY-----\n" +#define END_PUBLIC "\n-----END PUBLIC KEY-----" + +#define CIPHER_BLOCK_SIZE 16 + +/* ************************************************************************** */ +/* Functions : Private sss mbedtls delceration */ +/* ************************************************************************** */ +static sss_status_t sss_mbedtls_drbg_seed(sss_mbedtls_session_t *pSession, const char *pers, size_t persLen); + +#if SSSFTR_SW_ECC && SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_generate_ecp_key( + mbedtls_pk_context *pkey, sss_mbedtls_session_t *pSession, size_t keyBitLen, sss_cipher_type_t key_typ); +#endif + +#if SSSFTR_SW_RSA && SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_generate_rsa_key( + mbedtls_pk_context *pkey, sss_mbedtls_session_t *pSession, size_t keyBitLen); +#endif + +#if SSSFTR_SW_TESTCOUNTERPART +static sss_status_t sss_mbedtls_hkdf_extract(const mbedtls_md_info_t *md, + const uint8_t *salt, + size_t salt_len, + const uint8_t *ikm, + size_t ikm_len, + uint8_t *prk); + +static sss_status_t sss_mbedtls_hkdf_expand(const mbedtls_md_info_t *md, + const uint8_t *prk, + size_t prk_len, + const uint8_t *info, + size_t info_len, + uint8_t *okm, + size_t okm_len); +#endif + +static sss_status_t sss_mbedtls_set_key( + sss_mbedtls_object_t *keyObject, const uint8_t *data, size_t dataLen, size_t keyBitLen); + +#if SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_aead_ccm_finish( + sss_mbedtls_aead_t *context, uint8_t *destData, size_t *destLen, uint8_t *tag, size_t *tagLen); +static sss_status_t sss_mbedtls_aead_ccm_update(sss_mbedtls_aead_t *context, const uint8_t *srcData, size_t srcLen); +#endif +/* ************************************************************************** */ +/* Functions : sss_mbedtls_session */ +/* ************************************************************************** */ + +#ifndef MBEDTLS_CTR_DRBG_C +#error Need MBEDTLS_CTR_DRBG_C defined +#endif + +sss_status_t sss_mbedtls_session_create(sss_mbedtls_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_Success; + /* Nothing special to be handled */ + return retval; +} + +sss_status_t sss_mbedtls_session_open(sss_mbedtls_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_InvalidArgument; + memset(session, 0, sizeof(*session)); + static const char pers[] = "mbedtls_session"; + ENSURE_OR_GO_EXIT(connection_type == kSSS_ConnectionType_Plain); + +#ifdef MBEDTLS_FS_IO + if (connectionData == NULL) { + /* Nothing */ + } + else { + const char *szRootPath = (const char *)connectionData; + session->szRootPath = szRootPath; + } +#else + if (connectionData != NULL) { + /* Can't support connectionData != NULL for mbedTLS without + * MBEDTLS_FS_IO */ + retval = kStatus_SSS_InvalidArgument; + goto exit; + } +#endif + retval = kStatus_SSS_Fail; + session->ctr_drbg = SSS_MALLOC(sizeof(*session->ctr_drbg)); + ENSURE_OR_GO_EXIT(session->ctr_drbg != NULL); + + session->entropy = SSS_MALLOC(sizeof(*session->entropy)); + ENSURE_OR_GO_EXIT(session->entropy != NULL); + retval = kStatus_SSS_InvalidArgument; + + mbedtls_ctr_drbg_init((session->ctr_drbg)); + mbedtls_entropy_init((session->entropy)); + retval = sss_mbedtls_drbg_seed(session, pers, sizeof(pers) - 1); + if (retval != kStatus_SSS_Success) { + LOG_E("MbedTLS:DRBG Failed"); + goto exit; + } + /* Success */ + session->subsystem = subsystem; + +exit: + return retval; +} + +sss_status_t sss_mbedtls_session_prop_get_u32(sss_mbedtls_session_t *session, uint32_t property, uint32_t *pValue) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* TBU */ + return retval; +} + +sss_status_t sss_mbedtls_session_prop_get_au8( + sss_mbedtls_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* TBU */ + return retval; +} + +void sss_mbedtls_session_close(sss_mbedtls_session_t *session) +{ + if (session->ctr_drbg != NULL) + SSS_FREE(session->ctr_drbg); + if (session->entropy != NULL) + SSS_FREE(session->entropy); + memset(session, 0, sizeof(*session)); +} + +void sss_mbedtls_session_delete(sss_mbedtls_session_t *session) +{ + ; +} + +/* End: mbedtls_session */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_keyobj */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_key_object_init(sss_mbedtls_object_t *keyObject, sss_mbedtls_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyStore); + memset(keyObject, 0, sizeof(*keyObject)); + keyObject->keyStore = keyStore; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_object_allocate_handle(sss_mbedtls_object_t *keyObject, + uint32_t keyId, + sss_key_part_t key_part, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyId != 0); + ENSURE_OR_GO_CLEANUP(keyId != 0xFFFFFFFFu); + +#ifdef EX_SSS_OBJID_TEST_START + if (keyId < EX_SSS_OBJID_TEST_START) + return kStatus_SSS_Fail; + if (keyId > EX_SSS_OBJID_TEST_END) + return kStatus_SSS_Fail; +#endif + + if (options != kKeyObject_Mode_Persistent && options != kKeyObject_Mode_Transient) { + LOG_E("sss_mbedtls_key_object_allocate_handle option invalid 0x%X", options); + retval = kStatus_SSS_Fail; + goto cleanup; + } + if ((unsigned int)key_part > UINT8_MAX) { + LOG_E(" Only objectType 8 bits wide supported"); + retval = kStatus_SSS_Fail; + goto cleanup; + } +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + if (options == kKeyObject_Mode_Persistent) { + uint32_t i; + sss_mbedtls_object_t **ks; + ENSURE_OR_GO_CLEANUP(keyObject->keyStore); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore->max_object_count != 0); + retval = ks_common_update_fat( + keyObject->keyStore->keystore_shadow, keyId, key_part, cipherType, 0, 0, (uint16_t)keyByteLenMax); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + ks = keyObject->keyStore->objects; + retval = kStatus_SSS_Fail; + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (ks[i] == NULL) { + ks[i] = keyObject; + retval = ks_mbedtls_key_object_create(keyObject, keyId, key_part, cipherType, keyByteLenMax, options); + break; + } + } + } + else +#endif + { + retval = ks_mbedtls_key_object_create(keyObject, keyId, key_part, cipherType, keyByteLenMax, options); + } +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_object_get_handle(sss_mbedtls_object_t *keyObject, uint32_t keyId) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + uint32_t i; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore); + retval = kStatus_SSS_Success; + /* If key store already has loaded this and shared this - fail */ + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] != NULL && keyObject->keyStore->objects[i]->keyId == keyId) { + /* Key Object already loaded and shared in another instance */ + LOG_E("KeyID 0x%X already loaded / shared", keyId); + retval = kStatus_SSS_Fail; + break; + } + } + if (retval == kStatus_SSS_Success) { + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == NULL) { + retval = ks_mbedtls_load_key(keyObject, keyObject->keyStore->keystore_shadow, keyId); + if (retval == kStatus_SSS_Success) { + keyObject->keyStore->objects[i] = keyObject; + } + break; + } + } + } +cleanup: +#endif + return retval; +} + +sss_status_t sss_mbedtls_key_object_set_user(sss_mbedtls_object_t *keyObject, uint32_t user, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT((keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)); + retval = kStatus_SSS_Success; + keyObject->user_id = user; +exit: + return retval; +} + +sss_status_t sss_mbedtls_key_object_set_purpose(sss_mbedtls_object_t *keyObject, sss_mode_t purpose, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT((keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)); + retval = kStatus_SSS_Success; + keyObject->purpose = purpose; +exit: + return retval; +} + +sss_status_t sss_mbedtls_key_object_set_access(sss_mbedtls_object_t *keyObject, uint32_t access, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT((keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)); + retval = kStatus_SSS_Success; + keyObject->accessRights =(sss_access_permission_t) access; +exit: + return retval; +} + +sss_status_t sss_mbedtls_key_object_set_eccgfp_group(sss_mbedtls_object_t *keyObject, sss_eccgfp_group_t *group) +{ + sss_status_t retval = kStatus_SSS_Success; + /* TBU */ + return retval; +} + +sss_status_t sss_mbedtls_key_object_get_user(sss_mbedtls_object_t *keyObject, uint32_t *user) +{ + sss_status_t retval = kStatus_SSS_Success; + *user = keyObject->user_id; + return retval; +} + +sss_status_t sss_mbedtls_key_object_get_purpose(sss_mbedtls_object_t *keyObject, sss_mode_t *purpose) +{ + sss_status_t retval = kStatus_SSS_Success; + *purpose = keyObject->purpose; + return retval; +} + +sss_status_t sss_mbedtls_key_object_get_access(sss_mbedtls_object_t *keyObject, uint32_t *access) +{ + sss_status_t retval = kStatus_SSS_Success; + *access = keyObject->accessRights; + return retval; +} + +void sss_mbedtls_key_object_free(sss_mbedtls_object_t *keyObject) +{ + if (keyObject != NULL) { +#ifdef MBEDTLS_FS_IO + if (keyObject->keyStore != NULL && keyObject->objectType != 0) { + unsigned int i = 0; + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == keyObject) { + keyObject->keyStore->objects[i] = NULL; + break; + } + } + } +#endif + if (keyObject->contents != NULL && keyObject->contents_must_free) { + switch (keyObject->objectType) { + case kSSS_KeyPart_Public: + case kSSS_KeyPart_Pair: + case kSSS_KeyPart_Private: { + mbedtls_pk_context *pk; + pk = (mbedtls_pk_context *)keyObject->contents; + mbedtls_pk_free(pk); + SSS_FREE(pk); + break; + } + default: + SSS_FREE(keyObject->contents); + } + } + memset(keyObject, 0, sizeof(*keyObject)); + } /* if (keyObject != NULL) */ +} + +/* End: mbedtls_keyobj */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_keyderive */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_derive_key_context_init(sss_mbedtls_derive_key_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(session); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: +#endif + return retval; +} + +sss_status_t sss_mbedtls_derive_key_one_go(sss_mbedtls_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + size_t adjustedSaltLen = saltLen; + + if (context->mode == kMode_SSS_HKDF_ExpandOnly) { + adjustedSaltLen = 0; + } + + // The actual implementation (also used by legacy SSS API) decides + // on the saltLen parameter to apply either HKDF_EE or HKDK_ExpandOnly (saltLen == 0) + return sss_mbedtls_derive_key_go( + context, saltData, adjustedSaltLen, info, infoLen, derivedKeyObject, deriveDataLen, NULL, NULL); +} + +sss_status_t sss_mbedtls_derive_key_sobj_one_go(sss_mbedtls_derive_key_t *context, + sss_mbedtls_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + uint8_t saltData[1024] = {0}; + size_t saltLen = sizeof(saltData); + size_t dummySize; + sss_status_t status; + + // The actual implementation (also used by legacy SSS API) decides + // on the saltLen parameter to apply either HKDF_EE or HKDK_ExpandOnly (saltLen == 0) + if (context->mode != kMode_SSS_HKDF_ExpandOnly) { + status = sss_mbedtls_key_store_get_key(saltKeyObject->keyStore, saltKeyObject, saltData, &saltLen, &dummySize); + if (status != kStatus_SSS_Success) { + return kStatus_SSS_Fail; + } + } + else { + saltLen = 0; + } + + return sss_mbedtls_derive_key_go( + context, saltData, saltLen, info, infoLen, derivedKeyObject, deriveDataLen, NULL, NULL); +} + +// In HKDF Expand only mode PRK is unbounded, we set a maximum of 256 byte +// RFC5869 Section 2.3 +#define HKDF_PRK_MAX 256 +sss_status_t sss_mbedtls_derive_key_go(sss_mbedtls_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_mbedtls_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_TESTCOUNTERPART + const mbedtls_md_info_t *md = NULL; + uint8_t *secret; + size_t secretLen; + secret = context->keyObject->contents; + secretLen = context->keyObject->contents_size; + uint8_t prk[HKDF_PRK_MAX] = { + 0, + }; + size_t prk_len = 0; + mbedtls_md_type_t md_alg = MBEDTLS_MD_NONE; + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_HMAC_SHA1: + md_alg = MBEDTLS_MD_SHA1; + break; + case kAlgorithm_SSS_SHA256: + case kAlgorithm_SSS_HMAC_SHA256: + md_alg = MBEDTLS_MD_SHA256; + break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_HMAC_SHA384: + md_alg = MBEDTLS_MD_SHA384; + break; + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_HMAC_SHA512: + md_alg = MBEDTLS_MD_SHA512; + break; + default: + return kStatus_SSS_Fail; + } + + md = mbedtls_md_info_from_type(md_alg); + + if (saltLen == 0) { + /* Copy key as is */ + if (HKDF_PRK_MAX >= secretLen) { + memcpy(prk, secret, secretLen); + prk_len = secretLen; + } + else { + LOG_E("HKDF Expand only (mbedTLS implementation): buffer too small"); + return kStatus_SSS_Fail; + } + } + else { + retval = sss_mbedtls_hkdf_extract(md, saltData, saltLen, secret, secretLen, prk); + prk_len = mbedtls_md_get_size(md); + if (retval != kStatus_SSS_Success) { + return kStatus_SSS_Fail; + } + } + + retval = sss_mbedtls_hkdf_expand(md, prk, prk_len, info, infoLen, derivedKeyObject->contents, deriveDataLen); + if (retval == kStatus_SSS_Success) { + derivedKeyObject->contents_size = deriveDataLen; + } + +#endif + return retval; +} + +sss_status_t sss_mbedtls_derive_key_dh(sss_mbedtls_derive_key_t *context, + sss_mbedtls_object_t *otherPartyKeyObject, + sss_mbedtls_object_t *derivedKeyObject) +{ +#if SSSFTR_SW_ECC + sss_status_t retval = kStatus_SSS_Success; + int ret = -1; + mbedtls_pk_context *pKeyPrv; + mbedtls_ecp_keypair *pEcpPrv; + +#if defined(MBEDTLS_ECDH_C) + mbedtls_pk_context *pKeyExt; + mbedtls_ecp_keypair *pEcpExt; +#endif + size_t keyLen = 0; + size_t sharedSecretLen; + size_t sharedSecretLen_Derived; + const mbedtls_ecp_curve_info *p_curve_info = NULL; + mbedtls_mpi rawSharedData; + + ENSURE_OR_GO_EXIT(otherPartyKeyObject); + ENSURE_OR_GO_EXIT(derivedKeyObject); + + pKeyPrv = (mbedtls_pk_context *)context->keyObject->contents; + pEcpPrv = mbedtls_pk_ec(*pKeyPrv); + +#if defined(MBEDTLS_ECDH_C) + pKeyExt = (mbedtls_pk_context *)otherPartyKeyObject->contents; + pEcpExt = mbedtls_pk_ec(*pKeyExt); +#endif + + mbedtls_mpi_init(&rawSharedData); + + /* Compute the size of the shared secret */ + if (otherPartyKeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + if (pEcpPrv->grp.id == MBEDTLS_ECP_DP_CURVE448) { + keyLen = 56; + } + else { + keyLen = 32; + } + } + else { + p_curve_info = mbedtls_ecp_curve_info_from_grp_id(pEcpPrv->grp.id); + if (p_curve_info != NULL) { + keyLen = (size_t)(((p_curve_info->bit_size + 7)) / 8); + } + else { + retval = kStatus_SSS_Fail; + goto exit; + } + } + + sharedSecretLen = (size_t)(keyLen); +#if defined(MBEDTLS_ECDH_C) + ret = mbedtls_ecdh_compute_shared(&pEcpPrv->grp, + &rawSharedData, + &(pEcpExt->Q), + &(pEcpPrv->d), + mbedtls_ctr_drbg_random, + context->session->ctr_drbg); +#endif + if (ret != 0) { + LOG_E("mbedtls_ecdh_compute_shared returned -0x%04x", -ret); + retval = kStatus_SSS_Fail; + goto exit; + } + sharedSecretLen_Derived = mbedtls_mpi_size(&rawSharedData); + if (sharedSecretLen_Derived > sharedSecretLen) { + LOG_E("Failed: Incorrect shared key length"); + mbedtls_mpi_free(&rawSharedData); + retval = kStatus_SSS_Fail; + goto exit; + } + + derivedKeyObject->contents_size = keyLen; + ret = mbedtls_mpi_write_binary(&rawSharedData, derivedKeyObject->contents, derivedKeyObject->contents_size); + if (ret != 0) { + LOG_E("Failed: unable to write shared key"); + retval = kStatus_SSS_Fail; + goto exit; + } + mbedtls_mpi_free(&rawSharedData); +#ifdef MBEDTLS_DO_LITTLE_ENDIAN + if (otherPartyKeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + // Change Endianness Shared Secret in case of Montgomery Curve + uint8_t *pVal = (uint8_t *)derivedKeyObject->contents; + for (size_t keyValueIdx = 0; keyValueIdx < (derivedKeyObject->contents_size >> 1); keyValueIdx++) { + uint8_t swapByte = pVal[keyValueIdx]; + pVal[keyValueIdx] = pVal[derivedKeyObject->contents_size - 1 - keyValueIdx]; + pVal[derivedKeyObject->contents_size - 1 - keyValueIdx] = swapByte; + } + } +#endif +exit: + return retval; +#else + return kStatus_SSS_Fail; +#endif +} + +void sss_mbedtls_derive_key_context_free(sss_mbedtls_derive_key_t *context) +{ + memset(context, 0, sizeof(*context)); +} + +/* End: mbedtls_keyderive */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_keystore */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_key_store_context_init(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(session); + + memset(keyStore, 0, sizeof(*keyStore)); + keyStore->session = session; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_allocate(sss_mbedtls_key_store_t *keyStore, uint32_t keyStoreId) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyStore->session); + +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + /* This function is called once per session so keystore + object and shadow objects Should be equal to Null */ + ENSURE_OR_GO_CLEANUP(keyStore->objects == NULL); + ENSURE_OR_GO_CLEANUP(keyStore->keystore_shadow == NULL); + + keyStore->max_object_count = MAX_KEY_OBJ_COUNT; + keyStore->objects = (sss_mbedtls_object_t **)SSS_MALLOC(MAX_KEY_OBJ_COUNT * sizeof(sss_mbedtls_object_t *)); + ENSURE_OR_GO_CLEANUP(keyStore->objects != NULL); + memset(keyStore->objects, 0, (MAX_KEY_OBJ_COUNT * sizeof(sss_mbedtls_object_t *))); + ks_sw_fat_allocate(&keyStore->keystore_shadow); + if (keyStore->session->szRootPath != NULL) { + ks_sw_fat_load(keyStore->session->szRootPath, keyStore->keystore_shadow); + } + retval = kStatus_SSS_Success; + +#else + retval = kStatus_SSS_Success; +#endif +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_save(sss_mbedtls_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyStore->session); + +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + ENSURE_OR_GO_CLEANUP(keyStore->session->szRootPath) + ENSURE_OR_GO_CLEANUP(keyStore->objects) + uint32_t i; + for (i = 0; i < keyStore->max_object_count; i++) { + if (NULL != keyStore->objects[i]) { + ks_mbedtls_store_key(keyStore->objects[i]); + } + } + retval = ks_mbedtls_fat_update(keyStore); +#endif +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_load(sss_mbedtls_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyStore->session); +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + if (keyStore->objects == NULL) { + sss_mbedtls_key_store_allocate(keyStore, 0); + } + if (keyStore->session->szRootPath) { + if (NULL == keyStore->keystore_shadow) { + ks_sw_fat_allocate(&keyStore->keystore_shadow); + } + retval = ks_sw_fat_load(keyStore->session->szRootPath, keyStore->keystore_shadow); + keyStore->max_object_count = keyStore->keystore_shadow->maxEntries; + } +#endif +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_set_key(sss_mbedtls_key_store_t *keyStore, + sss_mbedtls_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + //mbedtls_pk_context *pk = NULL; + //size_t keyByteLen = keyBitLen / 8; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + + ENSURE_OR_GO_CLEANUP((keyObject->accessRights & kAccessPermission_SSS_Write)); + //pk = (mbedtls_pk_context *)keyObject->contents; + retval = sss_mbedtls_set_key(keyObject, data, dataLen, keyBitLen); +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_generate_key( + sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject, size_t keyBitLen, void *options) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART && (SSSFTR_SW_ECC || SSSFTR_SW_RSA) + sss_mbedtls_session_t *pS = NULL; + mbedtls_pk_context *pkey; + sss_key_part_t key_part = kSSS_KeyPart_NONE; + sss_cipher_type_t cipher_type = kSSS_CipherType_NONE; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); /* Must be allocated in allocate handle */ + + pS = keyStore->session; + key_part = keyObject->objectType; + cipher_type = keyObject->cipherType; + + pkey = (mbedtls_pk_context *)keyObject->contents; + if (key_part != kSSS_KeyPart_Pair) { + retval = kStatus_SSS_Success; + goto cleanup; + } + + mbedtls_pk_init(pkey); + switch (cipher_type) { +#if SSSFTR_SW_ECC + case kSSS_CipherType_EC_NIST_P: + case kSSS_CipherType_EC_NIST_K: + case kSSS_CipherType_EC_BRAINPOOL: + case kSSS_CipherType_EC_MONTGOMERY: + retval = sss_mbedtls_generate_ecp_key(pkey, pS, keyBitLen, cipher_type); + break; +#endif +#if SSSFTR_SW_RSA + case kSSS_CipherType_RSA: + retval = sss_mbedtls_generate_rsa_key(pkey, pS, keyBitLen); + break; +#endif + default: + break; + } +cleanup: +#endif + return retval; +} + +sss_status_t sss_mbedtls_key_store_get_key(sss_mbedtls_key_store_t *keyStore, + sss_mbedtls_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_RSA || SSSFTR_SW_ECC + mbedtls_pk_context *pk = NULL; + int ret = -1; + uint8_t output[1600] = {0}; + unsigned char *c = output; +#endif + + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP((keyObject->accessRights & kAccessPermission_SSS_Read)); + ENSURE_OR_GO_CLEANUP(data); + ENSURE_OR_GO_CLEANUP(dataLen); + + switch (keyObject->objectType) { + case kSSS_KeyPart_Default: + ENSURE_OR_GO_CLEANUP(*dataLen >= keyObject->contents_size); + memcpy(data, keyObject->contents, keyObject->contents_size); + *dataLen = keyObject->contents_size; + if (pKeyBitLen != NULL) { + *pKeyBitLen = keyObject->contents_size * 8; + } + retval = kStatus_SSS_Success; + break; +#if SSSFTR_SW_RSA || SSSFTR_SW_ECC + case kSSS_KeyPart_Public: + case kSSS_KeyPart_Pair: + pk = (mbedtls_pk_context *)keyObject->contents; + if (keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + mbedtls_ecp_keypair *pEcpPub = mbedtls_pk_ec(*pk); + size_t pubKey_size = 0; + size_t header_size = 0; + + if (pEcpPub->grp.id == MBEDTLS_ECP_DP_CURVE25519) { + pubKey_size = 32; + if (pKeyBitLen != NULL) { + *pKeyBitLen = 256; + } + header_size = der_ecc_mont_dh_25519_header_len; + ENSURE_OR_GO_CLEANUP(*dataLen >= (pubKey_size + header_size)); + memcpy(data, gecc_der_header_mont_dh_25519, header_size); + } + else if (pEcpPub->grp.id == MBEDTLS_ECP_DP_CURVE448) { + pubKey_size = 56; + if (pKeyBitLen != NULL) { + *pKeyBitLen = 448; + } + header_size = der_ecc_mont_dh_448_header_len; + ENSURE_OR_GO_CLEANUP(*dataLen >= (pubKey_size + header_size)); + memcpy(data, gecc_der_header_mont_dh_448, header_size); + } + else { + LOG_E( + "Only mont_dh_25519 (bit length 256) and mont_dh_448 (bit " + "length 448)"); + goto cleanup; + } + ret = mbedtls_mpi_write_binary(&pEcpPub->Q.X, output, pubKey_size); + ENSURE_OR_GO_CLEANUP(0 == ret); + *dataLen = pubKey_size + header_size; +#ifdef MBEDTLS_DO_LITTLE_ENDIAN + /* Reverse the public key */ + { + size_t i = 0; + while (i < pubKey_size) { + data[i + header_size] = output[pubKey_size - i - 1]; + i++; + } + } +#else + memcpy(data, output, pubKey_size); +#endif + retval = kStatus_SSS_Success; + } + else { + ret = mbedtls_pk_write_pubkey_der(pk, output, sizeof(output)); + if (ret > 0) { + if ((*dataLen) >= (size_t)ret) { + if (pKeyBitLen != NULL) { + *pKeyBitLen = mbedtls_pk_get_bitlen(pk); + } + *dataLen = ret; + /* Data is put at end, so copy it to front of output buffer */ + c = output + sizeof(output) - ret; + memcpy(data, c, ret); + retval = kStatus_SSS_Success; + } + } + } + break; +#endif // SSSFTR_SW_RSA || SSSFTR_SW_ECC + default: + break; + } +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_key_store_open_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Success; + return retval; +} + +sss_status_t sss_mbedtls_key_store_freeze_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Success; + return retval; +} + +sss_status_t sss_mbedtls_key_store_erase_key(sss_mbedtls_key_store_t *keyStore, sss_mbedtls_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + ENSURE_OR_GO_EXIT(keyObject->keyStore); + + ENSURE_OR_GO_EXIT((keyObject->accessRights & kAccessPermission_SSS_Delete)); + + if (keyObject->keyMode == kKeyObject_Mode_Persistent) { +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + unsigned int i = 0; + /* first check if key exists delete key from shadow KS*/ + retval = ks_common_remove_fat(keyObject->keyStore->keystore_shadow, keyObject->keyId); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + /* Update shadow keystore in file system*/ + retval = ks_mbedtls_fat_update(keyObject->keyStore); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + /*Clear key object from file*/ + retval = ks_mbedtls_remove_key(keyObject); + + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == keyObject) { + keyObject->keyStore->objects[i] = NULL; + break; + } + } +#endif + } + else { + retval = kStatus_SSS_Success; + } + +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +cleanup: +#endif +exit: +#endif + return retval; +} + +void sss_mbedtls_key_store_context_free(sss_mbedtls_key_store_t *keyStore) +{ +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED + if (NULL != keyStore->objects) { + uint32_t i; + for (i = 0; i < keyStore->max_object_count; i++) { + if (keyStore->objects[i] != NULL) { + //sss_mbedtls_key_object_free(keyStore->objects[i]); + keyStore->objects[i] = NULL; + } + } + SSS_FREE(keyStore->objects); + keyStore->objects = NULL; + } + if (NULL != keyStore->keystore_shadow) { + ks_sw_fat_free(keyStore->keystore_shadow); + } +#endif + memset(keyStore, 0, sizeof(*keyStore)); +} + +/* End: mbedtls_keystore */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_asym */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_asymmetric_context_init(sss_mbedtls_asymmetric_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore->session->subsystem == kType_SSS_mbedTLS); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: +#endif + return retval; +} + +sss_status_t sss_mbedtls_asymmetric_encrypt( + sss_mbedtls_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + int ret; + sss_mbedtls_object_t *keyObj = context->keyObject; + sss_mbedtls_session_t *pS = context->session; + mbedtls_pk_context *pKey; + pKey = (mbedtls_pk_context *)keyObj->contents; + sss_algorithm_t algo = context->algorithm; + ENSURE_OR_GO_EXIT((context->keyObject->accessRights & kAccessPermission_SSS_Use)); + retval = kStatus_SSS_Success; + + switch (algo) { + case kAlgorithm_SSS_RSAES_PKCS1_V1_5: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V15, 0); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA1); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA224); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA256); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA384); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA512); + break; + default: + retval = kStatus_SSS_Fail; + goto exit; + } + ret = mbedtls_pk_encrypt(pKey, srcData, srcLen, destData, destLen, *destLen, mbedtls_ctr_drbg_random, pS->ctr_drbg); + retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; + + *destLen = (mbedtls_pk_rsa(*pKey))->len; +exit: +#endif + return retval; +} + +sss_status_t sss_mbedtls_asymmetric_decrypt( + sss_mbedtls_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + int ret; + sss_mbedtls_object_t *keyObj = context->keyObject; + sss_mbedtls_session_t *pS = context->session; + mbedtls_pk_context *pKey; + sss_algorithm_t algo = context->algorithm; + retval = kStatus_SSS_Success; + ENSURE_OR_GO_EXIT((context->keyObject->accessRights & kAccessPermission_SSS_Use)); + + pKey = (mbedtls_pk_context *)keyObj->contents; + + switch (algo) { + case kAlgorithm_SSS_RSAES_PKCS1_V1_5: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V15, 0); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA1); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA224); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA256); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA384); + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512: + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, MBEDTLS_MD_SHA512); + break; + default: + retval = kStatus_SSS_Fail; + goto exit; + } + + ret = mbedtls_pk_decrypt(pKey, srcData, srcLen, destData, destLen, *destLen, mbedtls_ctr_drbg_random, pS->ctr_drbg); + + retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; + +exit: +#endif + return retval; +} + +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA +static mbedtls_md_type_t sss_mbedtls_set_padding_get_hash(sss_algorithm_t algorithm, mbedtls_pk_context *pKey) +{ + mbedtls_md_type_t md_alg = MBEDTLS_MD_NONE; + switch (algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + case kAlgorithm_SSS_SHA1: { + md_alg = MBEDTLS_MD_SHA1; + } break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + case kAlgorithm_SSS_SHA224: { + md_alg = MBEDTLS_MD_SHA224; + } break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + case kAlgorithm_SSS_SHA256: { + md_alg = MBEDTLS_MD_SHA256; + } break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + case kAlgorithm_SSS_SHA384: { + md_alg = MBEDTLS_MD_SHA384; + } break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + case kAlgorithm_SSS_SHA512: { + md_alg = MBEDTLS_MD_SHA512; + } break; + default: + md_alg = MBEDTLS_MD_NONE; + break; + } + + if (algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1 && + algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512) { + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V21, md_alg); + } + else if ((algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1 && + algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512) || + algorithm == kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH) { + mbedtls_rsa_set_padding(mbedtls_pk_rsa(*pKey), MBEDTLS_RSA_PKCS_V15, md_alg); + } + + return md_alg; +} +#endif + +sss_status_t sss_mbedtls_asymmetric_sign_digest( + sss_mbedtls_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + int ret = 1; + mbedtls_md_type_t md_alg = MBEDTLS_MD_NONE; + sss_mbedtls_session_t *pS; + mbedtls_pk_context *pKey; + + ENSURE_OR_GO_EXIT((context->keyObject->accessRights & kAccessPermission_SSS_Use)); + + pS = context->session; + pKey = (mbedtls_pk_context *)context->keyObject->contents; + + md_alg = sss_mbedtls_set_padding_get_hash(context->algorithm, pKey); + + ret = mbedtls_pk_sign( + pKey, md_alg, digest, digestLen, signature, signatureLen, mbedtls_ctr_drbg_random, pS->ctr_drbg); + + ENSURE_OR_GO_EXIT(ret == 0); + + retval = kStatus_SSS_Success; +exit: +#endif + return retval; +} + +sss_status_t sss_mbedtls_asymmetric_verify_digest( + sss_mbedtls_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + int ret = 1; + mbedtls_md_type_t md_alg = MBEDTLS_MD_NONE; + mbedtls_pk_context *pKey; + + ENSURE_OR_GO_EXIT((context->keyObject->accessRights & kAccessPermission_SSS_Use)); + + pKey = (mbedtls_pk_context *)context->keyObject->contents; + + md_alg = sss_mbedtls_set_padding_get_hash(context->algorithm, pKey); + + ret = mbedtls_pk_verify(pKey, md_alg, digest, digestLen, signature, signatureLen); + + ENSURE_OR_GO_EXIT(ret == 0); + + retval = kStatus_SSS_Success; +exit: +#endif + return retval; +} + +void sss_mbedtls_asymmetric_context_free(sss_mbedtls_asymmetric_t *context) +{ + memset(context, 0, sizeof(*context)); +} + +/* End: mbedtls_asym */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_symm */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_symmetric_context_init(sss_mbedtls_symmetric_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + + return retval; +} + +sss_status_t sss_mbedtls_cipher_one_go(sss_mbedtls_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + mbedtls_aes_context aes_ctx; +#if defined(MBEDTLS_DES_C) + mbedtls_des_context des_ctx; +#endif + int mbedtls_ret = 1; /* Fail by default */ + + switch (context->algorithm) { +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_ECB: +#endif //SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_CBC: + mbedtls_aes_init(&aes_ctx); + if (context->mode == kMode_SSS_Encrypt) { + mbedtls_ret = mbedtls_aes_setkey_enc( + &aes_ctx, context->keyObject->contents, (unsigned int)(context->keyObject->contents_size * 8)); + } + else if (context->mode == kMode_SSS_Decrypt) { + mbedtls_ret = mbedtls_aes_setkey_dec( + &aes_ctx, context->keyObject->contents, (unsigned int)(context->keyObject->contents_size * 8)); + } + break; +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_CTR: { + mbedtls_aes_init(&aes_ctx); + mbedtls_ret = mbedtls_aes_setkey_enc( + &aes_ctx, context->keyObject->contents, (unsigned int)(context->keyObject->contents_size * 8)); + } break; + case kAlgorithm_SSS_DES_CBC: + case kAlgorithm_SSS_DES_ECB: + case kAlgorithm_SSS_DES3_CBC: + case kAlgorithm_SSS_DES3_ECB: + mbedtls_des_init(&des_ctx); + if (context->mode == kMode_SSS_Encrypt) { + mbedtls_ret = mbedtls_des_setkey_enc(&des_ctx, context->keyObject->contents); + } + else if (context->mode == kMode_SSS_Decrypt) { + mbedtls_ret = mbedtls_des_setkey_dec(&des_ctx, context->keyObject->contents); + } + break; +#endif //SSS_HAVE_TESTCOUNTERPART + default: + goto exit; + } + + ENSURE_OR_GO_EXIT(mbedtls_ret == 0); + + if (context->mode == kMode_SSS_Encrypt) { + switch (context->algorithm) { +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_ECB: + mbedtls_ret = mbedtls_aes_crypt_ecb(&aes_ctx, MBEDTLS_AES_ENCRYPT, srcData, destData); + break; +#endif //SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_CBC: + mbedtls_ret = mbedtls_aes_crypt_cbc(&aes_ctx, MBEDTLS_AES_ENCRYPT, dataLen, iv, srcData, destData); + break; + case kAlgorithm_SSS_AES_CTR: { + uint8_t stream_block[16] = { + 0, + }; + size_t size_left = 0; + mbedtls_ret = mbedtls_aes_crypt_ctr(&aes_ctx, dataLen, &size_left, iv, stream_block, srcData, destData); + } break; +#if defined(MBEDTLS_DES_C) + case kAlgorithm_SSS_DES_ECB: + mbedtls_ret = mbedtls_des_crypt_ecb(&des_ctx, srcData, destData); + break; + case kAlgorithm_SSS_DES_CBC: + mbedtls_ret = mbedtls_des_crypt_cbc(&des_ctx, MBEDTLS_DES_ENCRYPT, dataLen, iv, srcData, destData); + break; +#endif + default: + break; + } + } + else if (context->mode == kMode_SSS_Decrypt) { + switch (context->algorithm) { + case kAlgorithm_SSS_AES_CBC: + mbedtls_ret = mbedtls_aes_crypt_cbc(&aes_ctx, MBEDTLS_AES_DECRYPT, dataLen, iv, srcData, destData); + break; +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_ECB: + mbedtls_ret = mbedtls_aes_crypt_ecb(&aes_ctx, MBEDTLS_AES_DECRYPT, srcData, destData); + break; + case kAlgorithm_SSS_AES_CTR: { + uint8_t stream_block[16] = { + 0, + }; + size_t size_left = 0; + mbedtls_ret = mbedtls_aes_crypt_ctr(&aes_ctx, dataLen, &size_left, iv, stream_block, srcData, destData); + } break; +#endif //SSS_HAVE_TESTCOUNTERPART +#if defined(MBEDTLS_DES_C) + case kAlgorithm_SSS_DES_ECB: + mbedtls_ret = mbedtls_des_crypt_ecb(&des_ctx, srcData, destData); + break; + case kAlgorithm_SSS_DES_CBC: + mbedtls_ret = mbedtls_des_crypt_cbc(&des_ctx, MBEDTLS_DES_DECRYPT, dataLen, iv, srcData, destData); + break; +#endif + default: + break; + } + } + else { + goto exit; + } + + ENSURE_OR_GO_EXIT(mbedtls_ret == 0); + + switch (context->algorithm) { +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_ECB: + case kAlgorithm_SSS_AES_CTR: +#endif //SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_AES_CBC: + mbedtls_aes_free(&aes_ctx); + break; +#if SSS_HAVE_TESTCOUNTERPART + case kAlgorithm_SSS_DES_CBC: + case kAlgorithm_SSS_DES_ECB: + case kAlgorithm_SSS_DES3_CBC: + case kAlgorithm_SSS_DES3_ECB: + mbedtls_des_free(&des_ctx); + break; +#endif //SSS_HAVE_TESTCOUNTERPART + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_mbedtls_cipher_init(sss_mbedtls_symmetric_t *context, uint8_t *iv, size_t ivLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + const mbedtls_cipher_info_t *cipher_info = NULL; + context->cipher_ctx = (mbedtls_cipher_context_t *)SSS_MALLOC(sizeof(mbedtls_cipher_context_t)); + ENSURE_OR_GO_EXIT(context->cipher_ctx != NULL); + retval = kStatus_SSS_Success; + + if (context->algorithm == kAlgorithm_SSS_AES_ECB) { + mbedtls_cipher_type_t cipher_type = MBEDTLS_CIPHER_NONE; + + switch (context->keyObject->keyBitLen) { + case 128: + cipher_type = MBEDTLS_CIPHER_AES_128_ECB; + break; + case 192: + cipher_type = MBEDTLS_CIPHER_AES_192_ECB; + break; + case 256: + cipher_type = MBEDTLS_CIPHER_AES_256_ECB; + break; + } + + if (cipher_type != MBEDTLS_CIPHER_NONE) { + cipher_info = mbedtls_cipher_info_from_type(cipher_type); + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CBC) { + mbedtls_cipher_type_t cipher_type = MBEDTLS_CIPHER_NONE; + + switch (context->keyObject->keyBitLen) { + case 128: + cipher_type = MBEDTLS_CIPHER_AES_128_CBC; + break; + case 192: + cipher_type = MBEDTLS_CIPHER_AES_192_CBC; + break; + case 256: + cipher_type = MBEDTLS_CIPHER_AES_256_CBC; + break; + } + + if (cipher_type != MBEDTLS_CIPHER_NONE) { + cipher_info = mbedtls_cipher_info_from_type(cipher_type); + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CTR) { + mbedtls_cipher_type_t cipher_type = MBEDTLS_CIPHER_NONE; + + switch (context->keyObject->keyBitLen) { + case 128: + cipher_type = MBEDTLS_CIPHER_AES_128_CTR; + break; + case 192: + cipher_type = MBEDTLS_CIPHER_AES_192_CTR; + break; + case 256: + cipher_type = MBEDTLS_CIPHER_AES_256_CTR; + break; + } + + if (cipher_type != MBEDTLS_CIPHER_NONE) { + cipher_info = mbedtls_cipher_info_from_type(cipher_type); + } + } + else { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + + mbedtls_cipher_init(context->cipher_ctx); + + if (0 == mbedtls_cipher_setup(context->cipher_ctx, cipher_info)) { + if (context->mode == kMode_SSS_Encrypt) { + if (mbedtls_cipher_setkey(context->cipher_ctx, + context->keyObject->contents, + (unsigned int)(context->keyObject->contents_size * 8), + MBEDTLS_ENCRYPT) != 0) { + retval = kStatus_SSS_InvalidArgument; + } + } + else if (context->mode == kMode_SSS_Decrypt) { + if (mbedtls_cipher_setkey(context->cipher_ctx, + context->keyObject->contents, + (unsigned int)(context->keyObject->contents_size * 8), + MBEDTLS_DECRYPT) != 0) { + retval = kStatus_SSS_InvalidArgument; + } + } + else { + retval = kStatus_SSS_InvalidArgument; + } + if (retval == kStatus_SSS_Success) { + mbedtls_cipher_set_iv(context->cipher_ctx, iv, ivLen); + mbedtls_cipher_reset(context->cipher_ctx); + } + } + +exit: +#endif + return retval; +} + +sss_status_t sss_mbedtls_cipher_update( + sss_mbedtls_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + uint8_t inputData[CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + int retMbedtlsVal; + + if ((context->cache_data_len + srcLen) < CIPHER_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + memcpy((inputData + inputData_len), srcData, (CIPHER_BLOCK_SIZE - context->cache_data_len)); + inputData_len += (CIPHER_BLOCK_SIZE - context->cache_data_len); + src_offset += (CIPHER_BLOCK_SIZE - context->cache_data_len); + context->cache_data_len = 0; + + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= inputData_len); + retMbedtlsVal = mbedtls_cipher_update( + context->cipher_ctx, inputData, inputData_len, (destData + output_offset), &blockoutLen); + ENSURE_OR_GO_EXIT(retMbedtlsVal == 0); + + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + + while (srcLen - src_offset >= CIPHER_BLOCK_SIZE) { + memcpy(inputData, (srcData + src_offset), CIPHER_BLOCK_SIZE); + src_offset += CIPHER_BLOCK_SIZE; + + blockoutLen = outBuffSize; + inputData_len = CIPHER_BLOCK_SIZE; + ENSURE_OR_GO_EXIT(blockoutLen >= inputData_len); + retMbedtlsVal = mbedtls_cipher_update( + context->cipher_ctx, inputData, inputData_len, (destData + output_offset), &blockoutLen); + ENSURE_OR_GO_EXIT(retMbedtlsVal == 0); + + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + } + + *destLen = output_offset; + + /* Copy unprocessed data to cache */ + if ((srcLen - src_offset) > 0) { + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + } + + retval = kStatus_SSS_Success; +exit: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } +#endif + return retval; +} + +sss_status_t sss_mbedtls_cipher_finish( + sss_mbedtls_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + int retMbedtlsVal; + uint8_t temp[16] = { + 0, + }; + size_t temp_len = sizeof(temp); + + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + context->cache_data_len = 0; + } + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + + srcdata_updated_len = srcdata_updated_len + (CIPHER_BLOCK_SIZE - (srcdata_updated_len % 16)); + + if (*destLen < srcdata_updated_len) { + LOG_E("Output buffer not sufficient"); + goto exit; + } + + if (srcdata_updated_len > 0) { + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= CIPHER_BLOCK_SIZE); + retMbedtlsVal = + mbedtls_cipher_update(context->cipher_ctx, srcdata_updated, CIPHER_BLOCK_SIZE, destData, &blockoutLen); + ENSURE_OR_GO_EXIT(retMbedtlsVal == 0); + *destLen = blockoutLen; + outBuffSize -= blockoutLen; + } + + if (srcdata_updated_len > CIPHER_BLOCK_SIZE) { + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= CIPHER_BLOCK_SIZE); + retMbedtlsVal = mbedtls_cipher_update(context->cipher_ctx, + srcdata_updated + CIPHER_BLOCK_SIZE, + CIPHER_BLOCK_SIZE, + destData + CIPHER_BLOCK_SIZE, + &blockoutLen); + ENSURE_OR_GO_EXIT(retMbedtlsVal == 0); + *destLen += blockoutLen; + } + + mbedtls_cipher_finish(context->cipher_ctx, temp, &temp_len); + mbedtls_cipher_free(context->cipher_ctx); + memset(context->cipher_ctx, 0, sizeof(*(context->cipher_ctx))); + SSS_FREE(context->cipher_ctx); + + retval = kStatus_SSS_Success; +exit: +#endif + return retval; +} + +sss_status_t sss_mbedtls_cipher_crypt_ctr(sss_mbedtls_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft) +{ + sss_status_t retval = kStatus_SSS_Fail; + mbedtls_aes_context ctx; + int mbedtls_ret; + + mbedtls_aes_init(&ctx); + + switch (context->mode) { + case kMode_SSS_Encrypt: + case kMode_SSS_Decrypt: + ENSURE_OR_GO_EXIT(context->algorithm == kAlgorithm_SSS_AES_CTR); + + mbedtls_ret = mbedtls_aes_setkey_enc( + &ctx, context->keyObject->contents, (unsigned int)(context->keyObject->contents_size * 8)); + ENSURE_OR_GO_EXIT(mbedtls_ret == 0); + + mbedtls_ret = + mbedtls_aes_crypt_ctr(&ctx, size, szLeft, initialCounter, lastEncryptedCounter, srcData, destData); + ENSURE_OR_GO_EXIT(mbedtls_ret == 0); + break; + default: + //retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + goto exit; + } + + mbedtls_aes_free(&ctx); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_mbedtls_symmetric_context_free(sss_mbedtls_symmetric_t *context) +{ + memset(context, 0, sizeof(*context)); +} + +/* End: mbedtls_symm */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_aead */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_aead_context_init(sss_mbedtls_aead_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(session); + ENSURE_OR_GO_CLEANUP(keyObject); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + + if (algorithm == kAlgorithm_SSS_AES_GCM) { + context->gcm_ctx = (mbedtls_gcm_context *)SSS_MALLOC(sizeof(mbedtls_gcm_context)); + ENSURE_OR_GO_CLEANUP(context->gcm_ctx); + } + else if (algorithm == kAlgorithm_SSS_AES_CCM) { + context->ccm_ctx = (mbedtls_ccm_context *)SSS_MALLOC(sizeof(mbedtls_ccm_context)); + ENSURE_OR_GO_CLEANUP(context->ccm_ctx); + } + else { + LOG_E("Improper Algorithm passed!"); + goto cleanup; + } + context->pCcm_aad = NULL; + context->pCcm_data = NULL; + context->pNonce = NULL; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_aead_one_go(sss_mbedtls_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 1; + size_t stagLength = *tagLen; + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + /* Initialize gcm context */ + mbedtls_gcm_init(context->gcm_ctx); + + /* Set key to the context */ + ret = mbedtls_gcm_setkey(context->gcm_ctx, + MBEDTLS_CIPHER_ID_AES, + context->keyObject->contents, + (unsigned int)(context->keyObject->contents_size * 8)); + ENSURE_OR_GO_CLEANUP(ret == 0); + + /* Check the mode and perform requested operation */ + if (context->mode == kMode_SSS_Encrypt) { + ret = mbedtls_gcm_crypt_and_tag(context->gcm_ctx, + MBEDTLS_GCM_ENCRYPT, + size, + nonce, + nonceLen, + aad, + aadLen, + srcData, + destData, + stagLength, + tag); + } + else { + ret = mbedtls_gcm_auth_decrypt( + context->gcm_ctx, size, nonce, nonceLen, aad, aadLen, tag, stagLength, srcData, destData); + } + } + + ENSURE_OR_GO_CLEANUP(ret == 0); + *tagLen = stagLength; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_aead_init( + sss_mbedtls_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(nonce); + /* Save the nonce and its length in context */ + context->pNonce = nonce; + context->nonceLen = nonceLen; + context->ccm_aadLen = aadLen; + context->ccm_dataTotalLen = payloadLen; + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + if (context->ccm_dataTotalLen) { + context->pCcm_data = SSS_MALLOC(payloadLen); + if (context->pCcm_data) { + memset(context->pCcm_data, 0, payloadLen); + context->ccm_dataoffset = 0; + } + else { + LOG_E("malloc failed"); + goto cleanup; + } + } + } + context->cache_data_len = 0; + memset(context->cache_data, 0x00, sizeof(context->cache_data)); + retval = kStatus_SSS_Success; + +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_aead_update_aad(sss_mbedtls_aead_t *context, const uint8_t *aadData, size_t aadDataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 1; + int mode = (context->mode == kMode_SSS_Encrypt) ? MBEDTLS_GCM_ENCRYPT : MBEDTLS_GCM_DECRYPT; + ENSURE_OR_GO_CLEANUP(context); + if (aadDataLen > 0) { + ENSURE_OR_GO_CLEANUP(aadData); + } + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + /* Initialize gcm context */ + mbedtls_gcm_init(context->gcm_ctx); + + /* Set key to the context */ + ret = mbedtls_gcm_setkey(context->gcm_ctx, + MBEDTLS_CIPHER_ID_AES, + context->keyObject->contents, + (unsigned int)(context->keyObject->contents_size * 8)); + ENSURE_OR_GO_CLEANUP(ret == 0); + + /* Add aad Data */ + ret = mbedtls_gcm_starts(context->gcm_ctx, mode, context->pNonce, context->nonceLen, aadData, aadDataLen); + ENSURE_OR_GO_CLEANUP(ret == 0); + } + else if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + /* Initialize ccm context */ + mbedtls_ccm_init(context->ccm_ctx); + /* Set key to the context */ + ret = mbedtls_ccm_setkey(context->ccm_ctx, + MBEDTLS_CIPHER_ID_AES, + context->keyObject->contents, + (unsigned int)(context->keyObject->contents_size * 8)); + ENSURE_OR_GO_CLEANUP(ret == 0); + context->pCcm_aad = aadData; + context->ccm_aadLen = aadDataLen; + } + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_mbedtls_aead_update( + sss_mbedtls_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + uint8_t inputData[CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + int ret = 1; + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + if ((srcData != NULL) && (srcLen > 0)) { + retval = sss_mbedtls_aead_ccm_update(context, srcData, srcLen); + } + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + *destLen = 0; + } + else { + if ((context->cache_data_len + srcLen) < CIPHER_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + memcpy((inputData + inputData_len), srcData, (CIPHER_BLOCK_SIZE - context->cache_data_len)); + inputData_len += (CIPHER_BLOCK_SIZE - context->cache_data_len); + src_offset += (CIPHER_BLOCK_SIZE - context->cache_data_len); + blockoutLen = outBuffSize; + + /* Add Source Data */ + ret = mbedtls_gcm_update(context->gcm_ctx, inputData_len, inputData, (destData + output_offset)); + ENSURE_OR_GO_CLEANUP(ret == 0); + blockoutLen = inputData_len; + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + + while (srcLen - src_offset >= CIPHER_BLOCK_SIZE) { + memcpy(inputData, (srcData + src_offset), 16); + src_offset += CIPHER_BLOCK_SIZE; + + blockoutLen = outBuffSize; + + /* Add Source Data */ + ret = mbedtls_gcm_update(context->gcm_ctx, inputData_len, inputData, (destData + output_offset)); + ENSURE_OR_GO_CLEANUP(ret == 0); + blockoutLen = inputData_len; + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + } + *destLen = output_offset; + /* Copy unprocessed data to cache */ + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + } + retval = kStatus_SSS_Success; +cleanup: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } +#endif /*End of SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} + +#if SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_aead_ccm_update(sss_mbedtls_aead_t *context, const uint8_t *srcData, size_t srcLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + if ((context->ccm_dataoffset + srcLen) <= (context->ccm_dataTotalLen)) { + memcpy(context->pCcm_data + context->ccm_dataoffset, srcData, srcLen); + context->ccm_dataoffset = context->ccm_dataoffset + srcLen; + retval = kStatus_SSS_Success; + } + else { + /*Free the allocated memory in init*/ + if (context->pCcm_data != NULL) { + SSS_FREE(context->pCcm_data); + context->pCcm_data = NULL; + } + } + return retval; +} +#endif //#if SSS_HAVE_TESTCOUNTERPART + +sss_status_t sss_mbedtls_aead_finish(sss_mbedtls_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + size_t stagLen = *tagLen; + int ret = 1; + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + uint8_t *pTag = NULL; + ENSURE_OR_GO_EXIT(context); + if (srcLen) { + ENSURE_OR_GO_EXIT(srcData); + } + ENSURE_OR_GO_EXIT(destData); + ENSURE_OR_GO_EXIT(tag); + ENSURE_OR_GO_EXIT(tagLen); + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { /* Check if finish has got source data */ + if ((srcData != NULL) && (srcLen > 0)) { + retval = sss_mbedtls_aead_ccm_update(context, srcData, srcLen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + } + retval = sss_mbedtls_aead_ccm_finish(context, destData, destLen, tag, tagLen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + } + else { + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + } + + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + + /* Add Source Data */ + ret = mbedtls_gcm_update(context->gcm_ctx, srcdata_updated_len, srcdata_updated, destData); + *destLen = srcdata_updated_len; + ENSURE_OR_GO_EXIT(ret == 0); + + pTag = (uint8_t *)SSS_MALLOC(*tagLen); + ENSURE_OR_GO_EXIT(pTag); + memset(pTag, 0, *tagLen); + + /* Get Tag for Enc*/ + ret = mbedtls_gcm_finish(context->gcm_ctx, pTag, stagLen); + ENSURE_OR_GO_EXIT(ret == 0); + if (context->mode == kMode_SSS_Encrypt) { + memcpy(tag, pTag, stagLen); + } + else { + if (0 != memcmp(pTag, tag, stagLen)) { + goto exit; + } + } + + *tagLen = stagLen; + } + retval = kStatus_SSS_Success; + +exit: + if (pTag) { + SSS_FREE(pTag); + } +#endif + return retval; +} +#if SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_aead_ccm_finish( + sss_mbedtls_aead_t *context, uint8_t *destData, size_t *destLen, uint8_t *tag, size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + size_t stagLen = *tagLen; + int ret = 1; + /* Check the mode and perform requested operation */ + if (context->mode == kMode_SSS_Encrypt) { + ret = mbedtls_ccm_encrypt_and_tag(context->ccm_ctx, + context->ccm_dataTotalLen, + context->pNonce, + context->nonceLen, + context->pCcm_aad, + context->ccm_aadLen, + context->pCcm_data, + destData, + tag, + stagLen); + } + else { + ret = mbedtls_ccm_auth_decrypt(context->ccm_ctx, + context->ccm_dataTotalLen, + context->pNonce, + context->nonceLen, + context->pCcm_aad, + context->ccm_aadLen, + context->pCcm_data, + destData, + tag, + stagLen); + } + ENSURE_OR_GO_EXIT(ret == 0); + *destLen = context->ccm_dataTotalLen; + retval = kStatus_SSS_Success; + +exit: + return retval; +} +#endif //if SSS_HAVE_TESTCOUNTERPART + +void sss_mbedtls_aead_context_free(sss_mbedtls_aead_t *context) +{ + if (context != NULL) { + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + if (context->gcm_ctx != NULL) { + mbedtls_gcm_free(context->gcm_ctx); + SSS_FREE(context->gcm_ctx); + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + if (context->ccm_ctx != NULL) { + mbedtls_ccm_free(context->ccm_ctx); + SSS_FREE(context->ccm_ctx); + if (context->pCcm_data != NULL) { + SSS_FREE(context->pCcm_data); + context->pCcm_data = NULL; + } + } + } + if (context->pCcm_aad != NULL) + context->pCcm_aad = NULL; + if (context->pNonce != NULL) + context->pNonce = NULL; + memset(context, 0, sizeof(*context)); + } +} + +/* End: mbedtls_aead */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_mac */ +/* ************************************************************************** */ +sss_status_t sss_mbedtls_mac_context_init(sss_mbedtls_mac_t *context, + sss_mbedtls_session_t *session, + sss_mbedtls_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t status = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(session); + ENSURE_OR_GO_CLEANUP(keyObject); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + context->cipher_ctx = NULL; + + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + context->cipher_ctx = (mbedtls_cipher_context_t *)SSS_MALLOC(sizeof(mbedtls_cipher_context_t)); + ENSURE_OR_GO_CLEANUP(context->cipher_ctx); + } +#if SSSFTR_SW_TESTCOUNTERPART + if (algorithm == kAlgorithm_SSS_HMAC_SHA1 || algorithm == kAlgorithm_SSS_HMAC_SHA224 || + algorithm == kAlgorithm_SSS_HMAC_SHA256 || algorithm == kAlgorithm_SSS_HMAC_SHA384 || + algorithm == kAlgorithm_SSS_HMAC_SHA512) { + context->HmacCtx = (mbedtls_md_context_t *)SSS_MALLOC(sizeof(mbedtls_md_context_t)); + ENSURE_OR_GO_CLEANUP(context->HmacCtx); + } +#endif + status = kStatus_SSS_Success; +cleanup: + return status; +} + +sss_status_t sss_mbedtls_mac_one_go( + sss_mbedtls_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen) +{ + sss_status_t status = kStatus_SSS_Fail; + int ret; + const mbedtls_cipher_info_t *cipher_info; +#if SSS_HAVE_TESTCOUNTERPART + const mbedtls_md_info_t *md_info = NULL; +#endif + uint8_t *key; + size_t keylen; + + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(context->keyObject->contents); + key = context->keyObject->contents; + keylen = context->keyObject->contents_size; + + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + mbedtls_cipher_type_t cipher_type = MBEDTLS_CIPHER_NONE; + + switch (keylen * 8) { + case 128: + cipher_type = MBEDTLS_CIPHER_AES_128_ECB; + break; +#if SSS_HAVE_TESTCOUNTERPART + case 192: + cipher_type = MBEDTLS_CIPHER_AES_192_ECB; + break; + case 256: + cipher_type = MBEDTLS_CIPHER_AES_256_ECB; + break; +#endif + default: + LOG_E("key bit not supported"); + goto cleanup; + } + + cipher_info = mbedtls_cipher_info_from_type(cipher_type); + if (cipher_info != NULL) { + mbedtls_cipher_init(context->cipher_ctx); + ret = mbedtls_cipher_setup(context->cipher_ctx, cipher_info); + if (ret == 0) { + if (ret == 0) { +#ifdef MBEDTLS_CMAC_C + ret = mbedtls_cipher_cmac_starts(context->cipher_ctx, key, (keylen * 8)); + if (ret == 0) { + ret = mbedtls_cipher_cmac_update(context->cipher_ctx, message, messageLen); + if (ret == 0) { + ret = mbedtls_cipher_cmac_finish(context->cipher_ctx, mac); + if (ret == 0) { + *macLen = context->cipher_ctx->cipher_info->block_size; + status = kStatus_SSS_Success; + } + } + } +#endif + } + } + } + } +#if SSS_HAVE_TESTCOUNTERPART + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + /*For HMAC any Key length is supported*/ + switch (context->algorithm) { + case kAlgorithm_SSS_HMAC_SHA1: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA1); + break; + case kAlgorithm_SSS_HMAC_SHA224: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA224); + break; + case kAlgorithm_SSS_HMAC_SHA256: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA256); + break; + case kAlgorithm_SSS_HMAC_SHA384: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA384); + break; + case kAlgorithm_SSS_HMAC_SHA512: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA512); + break; + default: + LOG_E("Invalid HMAC algorithm"); + status = kStatus_SSS_Fail; + goto cleanup; + } + + if (md_info != NULL) { + ret = mbedtls_md_hmac(md_info, key, keylen, message, messageLen, mac); + if (ret == 0) { + *macLen = mbedtls_md_get_size(md_info); + status = kStatus_SSS_Success; + } + } + } +#endif //SSS_HAVE_TESTCOUNTERPART + else { + LOG_E("Invalid algorithm type"); + } +cleanup: + return status; +} + +sss_status_t sss_mbedtls_mac_init(sss_mbedtls_mac_t *context) +{ + sss_status_t status = kStatus_SSS_Fail; + int ret; + uint8_t *key; + size_t keylen; + mbedtls_cipher_type_t cipher_type = MBEDTLS_CIPHER_NONE; + + ENSURE_OR_GO_CLEANUP(context->keyObject->contents); + key = context->keyObject->contents; + keylen = context->keyObject->contents_size; + + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + const mbedtls_cipher_info_t *cipher_info = NULL; + + switch (context->keyObject->keyBitLen) { + case 128: + cipher_type = MBEDTLS_CIPHER_AES_128_ECB; + break; +#if SSS_HAVE_TESTCOUNTERPART + case 192: + cipher_type = MBEDTLS_CIPHER_AES_192_ECB; + break; + case 256: + cipher_type = MBEDTLS_CIPHER_AES_256_ECB; + break; +#endif + default: + LOG_E("key bit not supported"); + goto cleanup; + } + + if (cipher_type != MBEDTLS_CIPHER_NONE) { + cipher_info = mbedtls_cipher_info_from_type(cipher_type); + } + + if (cipher_info != NULL) { + mbedtls_cipher_init(context->cipher_ctx); + ret = mbedtls_cipher_setup(context->cipher_ctx, cipher_info); + if (ret == 0) { +#ifdef MBEDTLS_CMAC_C + ret = mbedtls_cipher_cmac_starts(context->cipher_ctx, key, (keylen * 8)); +#endif + if (ret == 0) + status = kStatus_SSS_Success; + } + } + } +#if SSS_HAVE_TESTCOUNTERPART + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + /* for HMAC any key length is supported */ + + const mbedtls_md_info_t *md_info = NULL; + mbedtls_md_context_t *hmac_ctx; + hmac_ctx = context->HmacCtx; + mbedtls_md_init(hmac_ctx); + + switch (context->algorithm) { + case kAlgorithm_SSS_HMAC_SHA1: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA1); + break; + case kAlgorithm_SSS_HMAC_SHA224: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA224); + break; + case kAlgorithm_SSS_HMAC_SHA256: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA256); + break; + case kAlgorithm_SSS_HMAC_SHA384: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA384); + break; + case kAlgorithm_SSS_HMAC_SHA512: + md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA512); + break; + default: + status = kStatus_SSS_Fail; + goto cleanup; + } + + if (md_info != NULL) { + /* Below, third parameter '1' indicates that HMAC is to be setup*/ + ret = mbedtls_md_setup(hmac_ctx, md_info, 1); + if (ret == 0) { + ret = mbedtls_md_hmac_starts(hmac_ctx, key, (keylen)); + + if (ret == 0) { + status = kStatus_SSS_Success; + } + } + } + } +#endif //SSS_HAVE_TESTCOUNTERPART + else { + LOG_E("invalid algorithm mode for sss_mbedtls_mac_context_init "); + } + +cleanup: + return status; +} + +sss_status_t sss_mbedtls_mac_update(sss_mbedtls_mac_t *context, const uint8_t *message, size_t messageLen) +{ + int ret = 1; + sss_status_t status = kStatus_SSS_InvalidArgument; + ENSURE_OR_GO_EXIT(message != NULL); + + status = kStatus_SSS_Fail; + LOG_AU8_D(message, messageLen); + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { +#ifdef MBEDTLS_CMAC_C + mbedtls_cipher_context_t *ctx; + ctx = context->cipher_ctx; + ret = mbedtls_cipher_cmac_update(ctx, message, messageLen); +#endif + if (ret == 0) { + status = kStatus_SSS_Success; + } + } +#if SSSFTR_SW_TESTCOUNTERPART + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + mbedtls_md_context_t *hmac_ctx; + hmac_ctx = context->HmacCtx; + ret = mbedtls_md_hmac_update(hmac_ctx, message, messageLen); + + if (ret == 0) { + status = kStatus_SSS_Success; + } + } +#endif + else { + LOG_E("invalid algorithm mode for sss_mbedtls_mac_update"); + } +exit: + return status; +} + +sss_status_t sss_mbedtls_mac_finish(sss_mbedtls_mac_t *context, uint8_t *mac, size_t *macLen) +{ + int ret = 1; + sss_status_t status = kStatus_SSS_InvalidArgument; + ENSURE_OR_GO_EXIT((mac != NULL) && (macLen != NULL)); + + status = kStatus_SSS_Fail; + + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + mbedtls_cipher_context_t *ctx; + ctx = context->cipher_ctx; + +#ifdef MBEDTLS_CMAC_C + ret = mbedtls_cipher_cmac_finish(ctx, mac); +#endif + if (ret == 0) { + *macLen = ctx->cipher_info->block_size; + status = kStatus_SSS_Success; + } + } +#if SSS_HAVE_TESTCOUNTERPART + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + mbedtls_md_context_t *hmacctx; + hmacctx = context->HmacCtx; + + ret = mbedtls_md_hmac_finish(hmacctx, mac); + if (ret == 0) { + *macLen = mbedtls_md_get_size(hmacctx->md_info); + status = kStatus_SSS_Success; + } + } +#endif //SSS_HAVE_TESTCOUNTERPART + else { + LOG_E("Invalid algorithm type for sss_mbedtls_mac_finish"); + } +exit: + return status; +} + +void sss_mbedtls_mac_context_free(sss_mbedtls_mac_t *context) +{ + if (context != NULL) { + if (context->cipher_ctx != NULL) { + mbedtls_cipher_free(context->cipher_ctx); + SSS_FREE(context->cipher_ctx); + } +#if SSSFTR_SW_TESTCOUNTERPART + if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + SSS_FREE(context->HmacCtx); + } +#endif + memset(context, 0, sizeof(*context)); + } +} + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_md */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_digest_context_init( + sss_mbedtls_digest_t *context, sss_mbedtls_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + ENSURE_OR_GO_CLEANUP(context); + memset(context, 0, sizeof(*context)); + context->session = session; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: +#endif //SSS_HAVE_TESTCOUNTERPART + return retval; +} + +sss_status_t sss_mbedtls_digest_one_go( + sss_mbedtls_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + int ret; + const mbedtls_md_info_t *mdinfo = NULL; + mbedtls_md_type_t md_type = MBEDTLS_MD_NONE; + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + md_type = MBEDTLS_MD_SHA1; + *digestLen = 20; + break; + case kAlgorithm_SSS_SHA224: + md_type = MBEDTLS_MD_SHA224; + *digestLen = 28; + break; + case kAlgorithm_SSS_SHA256: + md_type = MBEDTLS_MD_SHA256; + *digestLen = 32; + break; + case kAlgorithm_SSS_SHA384: + md_type = MBEDTLS_MD_SHA384; + *digestLen = 48; + break; + case kAlgorithm_SSS_SHA512: + md_type = MBEDTLS_MD_SHA512; + *digestLen = 64; + break; + default: { + LOG_E("Algorithm mode not suported"); + goto exit; + } + } + + mdinfo = mbedtls_md_info_from_type(md_type); + + ret = mbedtls_md(mdinfo, message, messageLen, digest); + + if (ret != 0) { + LOG_E("mbedtls_md failed"); + *digestLen = 0; + goto exit; + } + + retval = kStatus_SSS_Success; +exit: +#endif //SSS_HAVE_TESTCOUNTERPART + return retval; +} + +sss_status_t sss_mbedtls_digest_init(sss_mbedtls_digest_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + const mbedtls_md_info_t *mdinfo = NULL; + mbedtls_md_type_t md_type = MBEDTLS_MD_NONE; + int ret; + + mbedtls_md_init(&context->md_ctx); + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + md_type = MBEDTLS_MD_SHA1; + break; + case kAlgorithm_SSS_SHA224: + md_type = MBEDTLS_MD_SHA224; + break; + case kAlgorithm_SSS_SHA256: + md_type = MBEDTLS_MD_SHA256; + break; + case kAlgorithm_SSS_SHA384: + md_type = MBEDTLS_MD_SHA384; + break; + case kAlgorithm_SSS_SHA512: + md_type = MBEDTLS_MD_SHA512; + break; + default: + LOG_E("Algorithm mode not suported"); + goto exit; + } + + mdinfo = mbedtls_md_info_from_type(md_type); + + ret = mbedtls_md_init_ctx(&context->md_ctx, mdinfo); + ENSURE_OR_GO_EXIT(ret == 0); + + ret = mbedtls_md_starts(&context->md_ctx); + ENSURE_OR_GO_EXIT(ret == 0); + + retval = kStatus_SSS_Success; +exit: +#endif //SSS_HAVE_TESTCOUNTERPART + return retval; +} + +sss_status_t sss_mbedtls_digest_update(sss_mbedtls_digest_t *context, const uint8_t *message, size_t messageLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + + int ret = mbedtls_md_update(&context->md_ctx, message, messageLen); + ENSURE_OR_GO_EXIT(ret == 0); + + retval = kStatus_SSS_Success; +exit: +#endif //SSS_HAVE_TESTCOUNTERPART + return retval; +} + +sss_status_t sss_mbedtls_digest_finish(sss_mbedtls_digest_t *context, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + int ret; + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + *digestLen = 20; + break; + case kAlgorithm_SSS_SHA224: + *digestLen = 28; + break; + case kAlgorithm_SSS_SHA256: + *digestLen = 32; + break; + case kAlgorithm_SSS_SHA384: + *digestLen = 48; + break; + case kAlgorithm_SSS_SHA512: + *digestLen = 64; + break; + default: { + LOG_E("Algorithm mode not suported"); + goto exit; + } + } + + ret = mbedtls_md_finish(&context->md_ctx, digest); + if (ret != 0) { + LOG_E("mbedtls_md_update failed"); + *digestLen = 0; + goto exit; + } + + retval = kStatus_SSS_Success; +exit: +#endif //SSS_HAVE_TESTCOUNTERPART + return retval; +} + +void sss_mbedtls_digest_context_free(sss_mbedtls_digest_t *context) +{ + // if (context->md_ctx) + // mbedtls_md_free(&context->md_ctx); + memset(context, 0, sizeof(*context)); +} + +/* End: mbedtls_md */ + +/* ************************************************************************** */ +/* Functions : sss_mbedtls_rng */ +/* ************************************************************************** */ + +sss_status_t sss_mbedtls_rng_context_init(sss_mbedtls_rng_context_t *context, sss_mbedtls_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Fail; + + ENSURE_OR_GO_EXIT(context); + ENSURE_OR_GO_EXIT(session); + + context->session = session; + + if (session->ctr_drbg == NULL) { + session->ctr_drbg = SSS_MALLOC(sizeof(*session->ctr_drbg)); + ENSURE_OR_GO_EXIT(session->ctr_drbg != NULL); + mbedtls_ctr_drbg_init((session->ctr_drbg)); + } + + if (session->entropy == NULL) { + session->entropy = SSS_MALLOC(sizeof(*session->entropy)); + ENSURE_OR_GO_EXIT(session->entropy != NULL); + mbedtls_entropy_init((session->entropy)); + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_mbedtls_rng_get_random(sss_mbedtls_rng_context_t *context, uint8_t *random_data, size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + size_t chunk = 0; + size_t offset = 0; + int ret = -1; + + while (dataLen > 0) { + if (dataLen > MBEDTLS_CTR_DRBG_MAX_REQUEST) { + chunk = MBEDTLS_CTR_DRBG_MAX_REQUEST; + } + else { + chunk = dataLen; + } + + ret = mbedtls_ctr_drbg_random(context->session->ctr_drbg, (random_data + offset), chunk); + ENSURE_OR_GO_EXIT(ret == 0); + + offset += chunk; + dataLen -= chunk; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_mbedtls_rng_context_free(sss_mbedtls_rng_context_t *context) +{ + sss_status_t retval = kStatus_SSS_Success; + memset(context, 0, sizeof(*context)); + return retval; +} + +/* End: mbedtls_rng */ + +/* ************************************************************************** */ +/* Functions : Private sss mbedtls functions */ +/* ************************************************************************** */ + +// FIXME: Handle data/dataLen +static sss_status_t sss_mbedtls_set_key( + sss_mbedtls_object_t *keyObject, const uint8_t *data, size_t dataLen, size_t keyBitLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + size_t base64_olen; + int ret; + char pem_format[2048]; +#endif + switch (keyObject->objectType) { + case kSSS_KeyPart_Default: + ENSURE_OR_GO_EXIT(dataLen <= keyObject->contents_max_size); + if (data != NULL) /* For empty certificate */ + memcpy(keyObject->contents, data, dataLen); + keyObject->contents_size = dataLen; + keyObject->keyBitLen = keyBitLen; + retval = kStatus_SSS_Success; + break; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + case kSSS_KeyPart_Private: + case kSSS_KeyPart_Pair: { + mbedtls_pk_context *pk = (mbedtls_pk_context *)keyObject->contents; + if (keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + mbedtls_ecp_keypair *pEcpPrv = NULL; + sss_status_t asn_retval = kStatus_SSS_Fail; + ret = mbedtls_pk_setup(pk, mbedtls_pk_info_from_type(MBEDTLS_PK_ECKEY)); + ENSURE_OR_GO_EXIT(ret == 0); + + pEcpPrv = mbedtls_pk_ec(*pk); + if (keyBitLen == 256) { + ret = mbedtls_ecp_group_load(&pEcpPrv->grp, MBEDTLS_ECP_DP_CURVE25519); + } + else if (keyBitLen == 448) { + ret = mbedtls_ecp_group_load(&pEcpPrv->grp, MBEDTLS_ECP_DP_CURVE448); + } + else { + ret = 1; + } + ENSURE_OR_GO_EXIT(ret == 0); + +#ifdef MBEDTLS_DO_LITTLE_ENDIAN // Reverse Endianness + { + size_t i = 0; + uint16_t publicKeyIndex = 0; + size_t publicKeyLen = 0; + uint16_t privateKeyIndex = 0; + size_t privateKeyLen = 0; + uint8_t pubKeyReversed[64] = { + 0, + }; + const uint8_t *pPublicKey = NULL; + uint8_t prvKeyReversed[64] = { + 0, + }; + const uint8_t *pPrivateKey = NULL; + + asn_retval = sss_util_rfc8410_asn1_get_ec_pair_key_index( + data, dataLen, &publicKeyIndex, &publicKeyLen, &privateKeyIndex, &privateKeyLen); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in sss_util_rfc8410_asn1_get_ec_pair_key_index"); + goto exit; + } + + while (i < publicKeyLen) { + pubKeyReversed[i] = data[publicKeyIndex + publicKeyLen - i - 1]; + i++; + } + pPublicKey = &pubKeyReversed[0]; + + i = 0; + while (i < privateKeyLen) { + prvKeyReversed[i] = data[privateKeyIndex + privateKeyLen - i - 1]; + i++; + } + + /* RFC 7748, Sec 5 Par 5*/ + if (keyBitLen == 256) { + prvKeyReversed[privateKeyLen - 1] = prvKeyReversed[privateKeyLen - 1] & 0xF8; + prvKeyReversed[0] = prvKeyReversed[0] & 0x7F; + prvKeyReversed[0] = prvKeyReversed[0] | 0x40; + } + else { + prvKeyReversed[privateKeyLen - 1] = prvKeyReversed[privateKeyLen - 1] & 0xFC; + prvKeyReversed[0] = prvKeyReversed[0] | 0x80; + } + + pPrivateKey = &prvKeyReversed[0]; + + ret = mbedtls_mpi_read_binary(&pEcpPrv->d, pPrivateKey, privateKeyLen); + ENSURE_OR_GO_EXIT(ret == 0); + + ret = mbedtls_mpi_read_binary(&pEcpPrv->Q.X, pPublicKey, publicKeyLen); + ENSURE_OR_GO_EXIT(ret == 0); + + ret = mbedtls_mpi_lset(&pEcpPrv->Q.Z, 1); + ENSURE_OR_GO_EXIT(ret == 0); + + retval = kStatus_SSS_Success; + } +#else + ret = mbedtls_mpi_read_binary(&pEcpPrv->d, data, dataLen); + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; +#endif + } + else { + ret = mbedtls_pk_parse_key(pk, data, dataLen, NULL, 0); + (ret == 0) ? (retval = kStatus_SSS_Success) : (retval = kStatus_SSS_Fail); + } + } break; + case kSSS_KeyPart_Public: { + // Sizeof base64_format should be limited to sizeof(pem_format) minus BEGIN_PUBLIC and END_PUBLIC + // SIMW-2696. + uint8_t base64_format[1996]; + mbedtls_pk_context *pk = (mbedtls_pk_context *)keyObject->contents; + if (keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + mbedtls_ecp_keypair *pEcpPub = NULL; + + ret = mbedtls_pk_setup(pk, mbedtls_pk_info_from_type(MBEDTLS_PK_ECKEY)); + ENSURE_OR_GO_EXIT(ret == 0); + + pEcpPub = mbedtls_pk_ec(*pk); + if (keyBitLen == 256) { + ret = mbedtls_ecp_group_load(&pEcpPub->grp, MBEDTLS_ECP_DP_CURVE25519); + } + else if (keyBitLen == 448) { + ret = mbedtls_ecp_group_load(&pEcpPub->grp, MBEDTLS_ECP_DP_CURVE448); + } + else { + ret = 1; + } + ENSURE_OR_GO_EXIT(ret == 0); + +#ifdef MBEDTLS_DO_LITTLE_ENDIAN // Reverse Endianness + { + size_t i = 0; + size_t publicKeyIndex = 0; + size_t publicKeyLen = dataLen; + size_t nByteKey = 32; // Corresponds to kSE05x_ECCurve_ECC_MONT_DH_25519 + uint8_t pubKeyReversed[64] = { + 0, + }; + const uint8_t *pPublicKey = NULL; +// #define TMP_ENDIAN_VERBOSE +#ifdef TMP_ENDIAN_VERBOSE + printf("Pub Key Before Reverse & header strip:\n"); + for (size_t z = 0; z < publicKeyLen; z++) { + printf("%02X.", data[publicKeyIndex + z]); + } + printf("\n"); + printf("keyBitLen = %d\n", (int)keyBitLen); +#endif + if (keyBitLen == 256) { + publicKeyIndex = der_ecc_mont_dh_25519_header_len; + publicKeyLen -= der_ecc_mont_dh_25519_header_len; + } + else { + nByteKey = 56; + publicKeyIndex = der_ecc_mont_dh_448_header_len; + publicKeyLen -= der_ecc_mont_dh_448_header_len; + } + + while (i < nByteKey) { + pubKeyReversed[i] = data[publicKeyIndex + publicKeyLen - i - 1]; + i++; + } + pPublicKey = &pubKeyReversed[0]; + +#ifdef TMP_ENDIAN_VERBOSE + printf("Pub Key After Reverse:\n"); + for (size_t z = 0; z < publicKeyLen; z++) { + printf("%02X.", pPublicKey[z]); + } + printf("\n"); +#endif + ret = mbedtls_mpi_read_binary(&pEcpPub->Q.X, pPublicKey, publicKeyLen); + } +#else + ret = mbedtls_mpi_read_binary(&pEcpPub->Q.X, data, dataLen); +#endif // Reverse Endianess + + (ret == 0) ? (retval = kStatus_SSS_Success) : (retval = kStatus_SSS_Fail); + + if (retval == kStatus_SSS_Success) { + ret = mbedtls_mpi_lset(&pEcpPub->Q.Z, 1); + (ret == 0) ? (retval = kStatus_SSS_Success) : (retval = kStatus_SSS_Fail); + } + } + else { + ret = mbedtls_base64_encode(base64_format, sizeof(base64_format), &base64_olen, data, dataLen); + SNPRINTF(pem_format, sizeof(pem_format), BEGIN_PUBLIC "%s" END_PUBLIC, base64_format); + ret = mbedtls_pk_parse_public_key(pk, (const uint8_t *)pem_format, strlen(pem_format) + 1); + (ret == 0) ? (retval = kStatus_SSS_Success) : (retval = kStatus_SSS_Fail); + } + } break; +#endif // SSSFTR_SW_ECC || SSSFTR_SW_RSA + default: + retval = kStatus_SSS_Fail; + LOG_E("Key type not supported"); + break; + } +exit: + return retval; +} + +static sss_status_t sss_mbedtls_drbg_seed(sss_mbedtls_session_t *pSession, const char *pers, size_t persLen) +{ + int ret; + sss_status_t retval = kStatus_SSS_Fail; + ret = mbedtls_ctr_drbg_seed( + pSession->ctr_drbg, &mbedtls_entropy_func, pSession->entropy, (const unsigned char *)pers, persLen); + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; +exit: + return (retval); +} + +#if SSSFTR_SW_ECC && SSS_HAVE_TESTCOUNTERPART +static mbedtls_ecp_group_id get_nist_p_group_id(size_t keyBitLen) +{ + mbedtls_ecp_group_id groupId = MBEDTLS_ECP_DP_NONE; + switch (keyBitLen) { + case 192: + groupId = MBEDTLS_ECP_DP_SECP192R1; + break; + case 224: + groupId = MBEDTLS_ECP_DP_SECP224R1; + break; + case 256: + groupId = MBEDTLS_ECP_DP_SECP256R1; + break; + case 384: + groupId = MBEDTLS_ECP_DP_SECP384R1; + break; + case 521: + groupId = MBEDTLS_ECP_DP_SECP521R1; + break; + default: + break; + } + return groupId; +} + +static mbedtls_ecp_group_id get_bp_group_id(size_t keyBitLen) +{ + mbedtls_ecp_group_id groupId = MBEDTLS_ECP_DP_NONE; + switch (keyBitLen) { + case 256: + groupId = MBEDTLS_ECP_DP_BP256R1; + break; + case 384: + groupId = MBEDTLS_ECP_DP_BP384R1; + break; + case 512: + groupId = MBEDTLS_ECP_DP_BP512R1; + break; + default: + break; + } + return groupId; +} + +static mbedtls_ecp_group_id get_nist_k_group_id(size_t keyBitLen) +{ + mbedtls_ecp_group_id groupId = MBEDTLS_ECP_DP_NONE; + switch (keyBitLen) { + case 192: + groupId = MBEDTLS_ECP_DP_SECP192K1; + break; + case 224: + groupId = MBEDTLS_ECP_DP_SECP224K1; + break; + case 256: + groupId = MBEDTLS_ECP_DP_SECP256K1; + break; + default: + break; + } + return groupId; +} + +static mbedtls_ecp_group_id get_mont_group_id(size_t keyBitLen) +{ + mbedtls_ecp_group_id groupId = MBEDTLS_ECP_DP_NONE; + switch (keyBitLen) { + case 256: + groupId = MBEDTLS_ECP_DP_CURVE25519; + break; + case 448: + groupId = MBEDTLS_ECP_DP_CURVE448; + break; + default: + break; + } + return groupId; +} + +static sss_status_t sss_mbedtls_generate_ecp_key( + mbedtls_pk_context *pkey, sss_mbedtls_session_t *pSession, size_t keyBitLen, sss_cipher_type_t cipher_typ) +{ + int ret; + sss_status_t retval = kStatus_SSS_Fail; + mbedtls_ecp_group_id groupId = MBEDTLS_ECP_DP_NONE; + + ret = mbedtls_pk_setup(pkey, mbedtls_pk_info_from_type(MBEDTLS_PK_ECKEY)); + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; + + if (cipher_typ == kSSS_CipherType_EC_NIST_P) { + groupId = get_nist_p_group_id(keyBitLen); + } + else if (cipher_typ == kSSS_CipherType_EC_BRAINPOOL) { + groupId = get_bp_group_id(keyBitLen); + } + else if (cipher_typ == kSSS_CipherType_EC_NIST_K) { + groupId = get_nist_k_group_id(keyBitLen); + } + else if (cipher_typ == kSSS_CipherType_EC_MONTGOMERY) { + groupId = get_mont_group_id(keyBitLen); + } + else { + LOG_E(" sss_openssl_generate_ecp_key: Invalid key type "); + } + + if (groupId != MBEDTLS_ECP_DP_NONE) { + ret = mbedtls_ecp_gen_key(groupId, mbedtls_pk_ec(*pkey), mbedtls_ctr_drbg_random, pSession->ctr_drbg); + } + else { + LOG_E(" Don't have support keyBitLen", keyBitLen); + ret = 1; + } + + if (ret != 0) { + LOG_E(" mbedtls_ecp_gen_key returned -0x%04x", -ret); + retval = kStatus_SSS_Fail; + goto exit; + } +exit: + return retval; +} +#endif // SSSFTR_SW_ECC + +#if SSSFTR_SW_RSA && SSS_HAVE_TESTCOUNTERPART +static sss_status_t sss_mbedtls_generate_rsa_key( + mbedtls_pk_context *pkey, sss_mbedtls_session_t *pSession, size_t keyBitLen) +{ + int ret; + sss_status_t retval = kStatus_SSS_Fail; + + ret = mbedtls_pk_setup(pkey, mbedtls_pk_info_from_type(MBEDTLS_PK_RSA)); + ENSURE_OR_GO_EXIT(ret == 0); + ENSURE_OR_GO_EXIT(keyBitLen == 512 || keyBitLen == 1024 || keyBitLen == 1152 || keyBitLen == 2048 || + keyBitLen == 3072 || keyBitLen == 4096); + + ret = mbedtls_rsa_gen_key( + mbedtls_pk_rsa(*pkey), mbedtls_ctr_drbg_random, (pSession->ctr_drbg), (unsigned int)keyBitLen, 65537); + + ENSURE_OR_GO_EXIT(ret == 0); + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif + +#if SSSFTR_SW_TESTCOUNTERPART +static sss_status_t sss_mbedtls_hkdf_expand(const mbedtls_md_info_t *md, + const uint8_t *prk, + size_t prk_len, + const uint8_t *info, + size_t info_len, + uint8_t *okm, + size_t okm_len) +{ + size_t hash_len; + size_t N; + size_t T_len = 0, where = 0, i, ret; + mbedtls_md_context_t ctx; + unsigned char T[MBEDTLS_MD_MAX_SIZE]; + sss_status_t retval = kStatus_SSS_Success; + + if (okm == NULL) { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + + hash_len = mbedtls_md_get_size(md); + + if (hash_len == 0) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (info == NULL) { + info = (const unsigned char *)""; + } + + N = okm_len / hash_len; + + if ((okm_len % hash_len) != 0) { + N++; + } + + if (N > 255) { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + + mbedtls_md_init(&ctx); + + if ((ret = mbedtls_md_setup(&ctx, md, 1)) != 0) { + mbedtls_md_free(&ctx); + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Section 2.3. */ + for (i = 1; i <= N; i++) { + unsigned char c = (unsigned char)i; + + ret = mbedtls_md_hmac_starts(&ctx, prk, prk_len) || mbedtls_md_hmac_update(&ctx, T, T_len) || + mbedtls_md_hmac_update(&ctx, info, info_len) || + /* The constant concatenated to the end of each T(n) is a single + octet. */ + mbedtls_md_hmac_update(&ctx, &c, 1) || mbedtls_md_hmac_finish(&ctx, T); + + if (ret != 0) { + mbedtls_md_free(&ctx); + retval = kStatus_SSS_Fail; + goto exit; + } + + memcpy(okm + where, T, (i != N) ? hash_len : (okm_len - where)); + where += hash_len; + T_len = hash_len; + } + + mbedtls_md_free(&ctx); +exit: + return retval; +} + +static sss_status_t sss_mbedtls_hkdf_extract( + const mbedtls_md_info_t *md, const uint8_t *salt, size_t salt_len, const uint8_t *ikm, size_t ikm_len, uint8_t *prk) +{ + int hash_len; + int ret; + unsigned char null_salt[MBEDTLS_MD_MAX_SIZE] = {'\0'}; + sss_status_t retval = kStatus_SSS_Success; + + hash_len = mbedtls_md_get_size(md); + + if (salt == NULL) { + salt = null_salt; + salt_len = hash_len; + } + + ret = mbedtls_md_hmac(md, salt, salt_len, ikm, ikm_len, prk); + if (ret != 0) { + retval = kStatus_SSS_Fail; + } + return retval; +} +#endif // SSSFTR_SW_TESTCOUNTERPART + +/* Low level implementation for sss_mbedtls_key_object_allocate_handle */ +sss_status_t ks_mbedtls_key_object_create(sss_mbedtls_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t keyMode) +{ + size_t size = 0; + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + + keyObject->keyId = keyId; + keyObject->objectType = keyPart; + keyObject->cipherType = cipherType; + keyObject->contents_max_size = keyByteLenMax; + keyObject->contents_must_free = 1; + keyObject->keyMode = keyMode; + /* Bitwise OR of all sss_access_permission. */ + keyObject->accessRights = kAccessPermission_SSS_All_Permission; + switch (keyPart) { + case kSSS_KeyPart_Default: + size = keyByteLenMax; + break; +#if SSSFTR_SW_ECC || SSSFTR_SW_RSA + case kSSS_KeyPart_Pair: + case kSSS_KeyPart_Private: + case kSSS_KeyPart_Public: + size = sizeof(mbedtls_pk_context); + break; +#endif // SSSFTR_SW_ECC || SSSFTR_SW_RSA + default: + break; + } + if (size != 0) { + keyObject->contents = SSS_MALLOC(size); + keyObject->contents_must_free = 1; + ENSURE_OR_GO_CLEANUP(keyObject->contents); + memset(keyObject->contents, 0, size); + retval = kStatus_SSS_Success; + } + +cleanup: + return retval; +} + +#endif /* SSS_HAVE_MBEDTLS */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c new file mode 100644 index 00000000000..de8a94926c8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c @@ -0,0 +1,3737 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if SSS_HAVE_OPENSSL + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else +#include +#endif + +#include "nxLog_sss.h" + +#define MAX_KEY_OBJ_COUNT KS_N_ENTIRES +#define MAX_FILE_NAME_SIZE 255 +#define MAX_SHARED_SECRET_DERIVED_DATA 255 +#define BEGIN_PRIVATE "-----BEGIN PRIVATE KEY-----\n" +#define END_PRIVATE "\n-----END PRIVATE KEY-----" +#define BEGIN_EC_PRIVATE "-----BEGIN EC PRIVATE KEY-----\n" +#define END_EC_PRIVATE "\n-----END EC PRIVATE KEY-----" +#define BEGIN_PUBLIC "-----BEGIN PUBLIC KEY-----\n" +#define END_PUBLIC "\n-----END PUBLIC KEY-----" +#define BEGIN_RSA_PRIVATE "-----BEGIN RSA PRIVATE KEY-----\n" +#define END_RSA_PRIVATE "\n-----END RSA PRIVATE KEY-----" + +#define CIPHER_BLOCK_SIZE 16 + +#define SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO 1 + +#ifndef RSA_PSS_SALTLEN_DIGEST +#define RSA_PSS_SALTLEN_DIGEST -1 +#endif + +/* ************************************************************************** */ +/* Functions : Private sss openssl delceration */ +/* ************************************************************************** */ +static sss_status_t sss_openssl_generate_ecp_key(sss_openssl_object_t *keyObject, size_t keyBitLen); + +static sss_status_t sss_openssl_generate_rsa_key(sss_openssl_object_t *keyObject, size_t keyBitLen); + +static sss_status_t sss_openssl_set_key( + sss_openssl_object_t *keyObject, const uint8_t *keyBuf, size_t keyBufLen, size_t keyBitLen); + +static sss_status_t sss_openssl_hkdf_extract(const EVP_MD *md, + const uint8_t *salt, + size_t salt_len, + const uint8_t *ikm, + size_t ikm_len, + uint8_t *prk, + unsigned int *prk_len); + +static sss_status_t sss_openssl_hkdf_expand(const EVP_MD *md, + const uint8_t *prk, + size_t prk_len, + const uint8_t *info, + size_t info_len, + uint8_t *okm, + size_t okm_len); + +static sss_status_t sss_openssl_aead_init_ctx(sss_openssl_aead_t *context); +static sss_status_t sss_openssl_aead_one_go_encrypt(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +static sss_status_t sss_openssl_aead_one_go_decrypt(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen); + +static int aead_update(sss_openssl_aead_t *context, + sss_mode_t mode, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen); +static sss_status_t sss_openssl_aead_ccm_init( + sss_openssl_aead_t *context, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen); +static sss_status_t sss_openssl_aead_ccm_final( + sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen, uint8_t *tag, size_t *tagLen); + +static sss_status_t sss_openssl_aead_ccm_Decryptfinal(sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen); + +static sss_status_t sss_openssl_aead_ccm_Encryptfinal(sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen); + +static sss_status_t sss_openssl_aead_ccm_update(sss_openssl_aead_t *context, const uint8_t *srcData, size_t srcLen); +/* ************************************************************************** */ +/* Functions : sss_openssl_session */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_session_create(sss_openssl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_Success; + /* Nothing special to be handled */ + return retval; +} + +sss_status_t sss_openssl_session_open(sss_openssl_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_InvalidArgument; + memset(session, 0, sizeof(*session)); + +#if SSS_HAVE_OPENSSL + memset(session, 0, sizeof(*session)); + + OpenSSL_add_all_algorithms(); + + if (connectionData == NULL) { + retval = kStatus_SSS_Success; + session->subsystem = subsystem; + } + else { + const char *szRootPath = (const char *)connectionData; + session->szRootPath = szRootPath; + retval = kStatus_SSS_Success; + session->subsystem = subsystem; + } +#else + if (connectionData == NULL) { + retval = kStatus_SSS_Success; + session->subsystem = subsystem; + } + else { + /* Can't support connectionData != NULL for openssl without + * openssl_FS_IO */ + retval = kStatus_SSS_InvalidArgument; + } +#endif + + return retval; +} + +sss_status_t sss_openssl_session_prop_get_u32(sss_openssl_session_t *session, uint32_t property, uint32_t *pValue) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* TBU */ + return retval; +} + +sss_status_t sss_openssl_session_prop_get_au8( + sss_openssl_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* TBU */ + return retval; +} + +void sss_openssl_session_close(sss_openssl_session_t *session) +{ +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + ERR_remove_thread_state(NULL); +#endif +#ifdef __linux__ + EVP_cleanup(); +#endif + memset(session, 0, sizeof(*session)); +} + +void sss_openssl_session_delete(sss_openssl_session_t *session) +{ + ; +} + +/* End: openssl_session */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_keyobj */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_key_object_init(sss_openssl_object_t *keyObject, sss_openssl_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyStore); + memset(keyObject, 0, sizeof(*keyObject)); + keyObject->keyStore = keyStore; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_object_allocate(sss_openssl_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t keyMode) +{ + size_t size = 0; + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + keyObject->keyId = keyId; + keyObject->objectType = keyPart; + keyObject->cipherType = cipherType; + keyObject->contents_max_size = keyByteLenMax; + keyObject->contents_must_free = 1; + keyObject->keyMode = keyMode; + /* Bitwise OR of all sss_access_permission. */ + keyObject->accessRights = kAccessPermission_SSS_All_Permission; + switch (keyPart) { + case kSSS_KeyPart_Default: + size = keyByteLenMax; + if (size != 0) { + keyObject->contents = SSS_MALLOC(size); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + memset(keyObject->contents, 0, size); + retval = kStatus_SSS_Success; + } + break; + case kSSS_KeyPart_Public: + case kSSS_KeyPart_Pair: + case kSSS_KeyPart_Private: + /* Initialize the Generic key strucute if not done. */ + keyObject->contents = EVP_PKEY_new(); + retval = kStatus_SSS_Success; + break; + default: + break; + } +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_object_allocate_handle(sss_openssl_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyObject); + + if (options != kKeyObject_Mode_Persistent && options != kKeyObject_Mode_Transient) { + LOG_E("sss_openssl_key_object_allocate_handle option invalid 0x%X", options); + goto cleanup; + } + ENSURE_OR_GO_CLEANUP((size_t)keyPart < UINT8_MAX); + if (options == kKeyObject_Mode_Persistent) { +#ifdef SSS_HAVE_OPENSSL + uint32_t i; + sss_openssl_object_t **ks; + ENSURE_OR_GO_CLEANUP(keyObject->keyStore); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore->max_object_count > 0); + + retval = ks_common_update_fat( + keyObject->keyStore->keystore_shadow, keyId, keyPart, cipherType, 0, 0, (uint16_t)keyByteLenMax); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + ks = keyObject->keyStore->objects; + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (ks[i] == NULL) { + ks[i] = keyObject; + retval = sss_openssl_key_object_allocate(keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + break; + } + } +#endif + } + else { + retval = sss_openssl_key_object_allocate(keyObject, keyId, keyPart, cipherType, keyByteLenMax, options); + } +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_object_get_handle(sss_openssl_object_t *keyObject, uint32_t keyId) +{ + sss_status_t retval = kStatus_SSS_Fail; +#ifdef SSS_HAVE_OPENSSL + uint32_t i; + + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore); + retval = kStatus_SSS_Success; + /* If key store already has loaded this and shared this - fail */ + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] != NULL && keyObject->keyStore->objects[i]->keyId == keyId) { + /* Key Object already loaded and shared in another instance */ + LOG_W("KeyID 0x%X already loaded / shared", keyId); + retval = kStatus_SSS_Fail; + break; + } + } + if (retval == kStatus_SSS_Success) { + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == NULL) { + retval = ks_openssl_load_key(keyObject, keyObject->keyStore->keystore_shadow, keyId); + if (retval == kStatus_SSS_Success) { + keyObject->keyStore->objects[i] = keyObject; + } + break; + } + } + } +#endif +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_object_set_user(sss_openssl_object_t *keyObject, uint32_t user, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Success; + if (!(keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)) { + LOG_E(" Don't have access rights to change the attributes"); + return kStatus_SSS_Fail; + } + keyObject->user_id = user; + return retval; +} + +sss_status_t sss_openssl_key_object_set_purpose(sss_openssl_object_t *keyObject, sss_mode_t purpose, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Success; + if (!(keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)) { + LOG_E(" Don't have access rights to change the attributes"); + return kStatus_SSS_Fail; + } + keyObject->purpose = purpose; + return retval; +} + +sss_status_t sss_openssl_key_object_set_access(sss_openssl_object_t *keyObject, uint32_t access, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Success; + if (!(keyObject->accessRights & kAccessPermission_SSS_ChangeAttributes)) { + LOG_E(" Don't have access rights to use the key"); + + return kStatus_SSS_Fail; + } + keyObject->accessRights = access; + return retval; +} + +sss_status_t sss_openssl_key_object_set_eccgfp_group(sss_openssl_object_t *keyObject, sss_eccgfp_group_t *group) +{ + sss_status_t retval = kStatus_SSS_Success; + /* TBU */ + return retval; +} + +sss_status_t sss_openssl_key_object_get_user(sss_openssl_object_t *keyObject, uint32_t *user) +{ + sss_status_t retval = kStatus_SSS_Success; + *user = keyObject->user_id; + return retval; +} + +sss_status_t sss_openssl_key_object_get_purpose(sss_openssl_object_t *keyObject, sss_mode_t *purpose) +{ + sss_status_t retval = kStatus_SSS_Success; + *purpose = keyObject->purpose; + return retval; +} + +sss_status_t sss_openssl_key_object_get_access(sss_openssl_object_t *keyObject, uint32_t *access) +{ + sss_status_t retval = kStatus_SSS_Success; + *access = keyObject->accessRights; + return retval; +} + +void sss_openssl_key_object_free(sss_openssl_object_t *keyObject) +{ + EVP_PKEY *pKey = NULL; + RSA *pRSA = NULL; + unsigned int i = 0; + + ENSURE_OR_GO_EXIT(keyObject) + if (keyObject->keyStore != NULL && keyObject->objectType != 0) { + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == keyObject) { + keyObject->keyStore->objects[i] = NULL; + break; + } + } + } + + if (keyObject->contents != NULL && keyObject->contents_must_free) { + switch (keyObject->cipherType) { + case kSSS_CipherType_RSA: + pKey = (EVP_PKEY *)keyObject->contents; + pRSA = (RSA *)EVP_PKEY_get0(pKey); + if (pRSA) { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + if (pRSA->references) + pRSA->references = 0; +#else + /* not in 1.1 and above */ +#endif + } + EVP_PKEY_free(pKey); + break; + case kSSS_CipherType_EC_NIST_P: + case kSSS_CipherType_EC_NIST_K: + case kSSS_CipherType_EC_BRAINPOOL: + case kSSS_CipherType_EC_MONTGOMERY: + case kSSS_CipherType_EC_TWISTED_ED: + pKey = (EVP_PKEY *)keyObject->contents; + EVP_PKEY_free(pKey); + break; + default: + SSS_FREE(keyObject->contents); + } + } + memset(keyObject, 0, sizeof(*keyObject)); +exit: + return; +} + +/* End: openssl_keyobj */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_keyderive */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_derive_key_context_init(sss_openssl_derive_key_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(session); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_openssl_derive_key_one_go(sss_openssl_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + size_t adjustedSaltLen = saltLen; + + if (context->mode == kMode_SSS_HKDF_ExpandOnly) { + adjustedSaltLen = 0; + } + + return sss_openssl_derive_key_go( + context, saltData, adjustedSaltLen, info, infoLen, derivedKeyObject, deriveDataLen, NULL, NULL); +} + +sss_status_t sss_openssl_derive_key_sobj_one_go(sss_openssl_derive_key_t *context, + sss_openssl_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + uint8_t saltData[1024] = {0}; + size_t saltLen = sizeof(saltData); + size_t dummySize; + sss_status_t status; + + if (context == NULL) { + return kStatus_SSS_Fail; + } + + if (context->mode != kMode_SSS_HKDF_ExpandOnly) { + status = sss_openssl_key_store_get_key(saltKeyObject->keyStore, saltKeyObject, saltData, &saltLen, &dummySize); + if (status != kStatus_SSS_Success) { + return kStatus_SSS_Fail; + } + } + else { + saltLen = 0; + } + + // Not yet fully implemented + // TODO: + // - deal with saltKeyObject + return sss_openssl_derive_key_go( + context, saltData, saltLen, info, infoLen, derivedKeyObject, deriveDataLen, NULL, NULL); +} + +// In HKDF Expand only mode PRK is unbounded, we set a maximum of 256 byte +// RFC5869 Section 2.3 +#define HKDF_PRK_MAX 256 +sss_status_t sss_openssl_derive_key_go(sss_openssl_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_openssl_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen) +{ + sss_status_t retval = kStatus_SSS_Success; + const EVP_MD *md = NULL; + uint8_t *secret = NULL; + size_t secretLen = 0; + secret = context->keyObject->contents; + secretLen = context->keyObject->contents_size; + uint8_t prk[HKDF_PRK_MAX]; + unsigned int prk_len = 0; + + /* Initialize the MD */ + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_HMAC_SHA1: + md = EVP_sha1(); + break; + case kAlgorithm_SSS_SHA256: + case kAlgorithm_SSS_HMAC_SHA256: + md = EVP_sha256(); + break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_HMAC_SHA384: + md = EVP_sha384(); + break; + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_HMAC_SHA512: + md = EVP_sha512(); + break; + default: + return kStatus_SSS_Fail; + } + + if (saltLen == 0) { + /* Copy key as is */ + if (HKDF_PRK_MAX >= secretLen) { + memcpy(prk, secret, secretLen); + prk_len = secretLen; + } + else { + LOG_E("HKDF Expand only (OpenSSL implementation): buffer too small"); + return kStatus_SSS_Fail; + } + } + else { + retval = sss_openssl_hkdf_extract(md, saltData, saltLen, secret, secretLen, prk, &prk_len); + if (retval != kStatus_SSS_Success) { + return kStatus_SSS_Fail; + } + } + + retval = sss_openssl_hkdf_expand(md, prk, prk_len, info, infoLen, derivedKeyObject->contents, deriveDataLen); + derivedKeyObject->contents_size = deriveDataLen; + + return retval; +} + +sss_status_t sss_openssl_derive_key_dh(sss_openssl_derive_key_t *context, + sss_openssl_object_t *otherPartyKeyObject, + sss_openssl_object_t *derivedKeyObject) +{ + sss_status_t retval = kStatus_SSS_Success; + EVP_PKEY *pKeyPrv = NULL; + EC_KEY *pEcpPrv = NULL; + + EVP_PKEY *pKeyExt = NULL; + EC_KEY *pEcpExt = NULL; + + size_t sharedSecretLen; + int sharedSecretLen_Derived; + EC_GROUP *pEC_Group = NULL; + uint8_t *secret = NULL; + + if (otherPartyKeyObject == NULL || derivedKeyObject == NULL) { + return kStatus_SSS_Fail; + } + + pKeyPrv = (EVP_PKEY *)context->keyObject->contents; + pKeyExt = (EVP_PKEY *)otherPartyKeyObject->contents; + + if (context->keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + EVP_PKEY_CTX *ctx; + ctx = EVP_PKEY_CTX_new(pKeyPrv, NULL); + if (!ctx) { + return kStatus_SSS_Fail; + } + + if (EVP_PKEY_derive_init(ctx) <= 0) { + return kStatus_SSS_Fail; + } + + if (EVP_PKEY_derive_set_peer(ctx, pKeyExt) <= 0) { + return kStatus_SSS_Fail; + } + + /* Determine buffer length */ + if (EVP_PKEY_derive(ctx, NULL, &sharedSecretLen) <= 0) { + return kStatus_SSS_Fail; + } + + secret = (uint8_t *)SSS_MALLOC(sharedSecretLen); + sharedSecretLen_Derived = sharedSecretLen; + + if (EVP_PKEY_derive(ctx, secret, &sharedSecretLen) <= 0) { + return kStatus_SSS_Fail; + } + EVP_PKEY_CTX_free(ctx); + } + else { + pEcpPrv = EVP_PKEY_get1_EC_KEY(pKeyPrv); + pEcpExt = EVP_PKEY_get1_EC_KEY(pKeyExt); + sharedSecretLen = (EC_GROUP_get_degree(EC_KEY_get0_group(pEcpExt)) + 7) / 8; + secret = (uint8_t *)SSS_MALLOC(sharedSecretLen); + + sharedSecretLen_Derived = + ECDH_compute_key(secret, sharedSecretLen, EC_KEY_get0_public_key(pEcpExt), pEcpPrv, NULL); + } + + memcpy(derivedKeyObject->contents, secret, sharedSecretLen_Derived); + derivedKeyObject->contents_size = sharedSecretLen_Derived; + + EC_GROUP_free(pEC_Group); + EC_KEY_free(pEcpPrv); + EC_KEY_free(pEcpExt); + SSS_FREE(secret); + return retval; +} + +void sss_openssl_derive_key_context_free(sss_openssl_derive_key_t *context) +{ + if (context->keyObject) + sss_openssl_key_object_free(context->keyObject); + memset(context, 0, sizeof(*context)); +} + +/* End: openssl_keyderive */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_keystore */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_key_store_context_init(sss_openssl_key_store_t *keyStore, sss_openssl_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(session); + memset(keyStore, 0, sizeof(*keyStore)); + keyStore->session = session; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_store_allocate(sss_openssl_key_store_t *keyStore, uint32_t keyStoreId) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + retval = kStatus_SSS_Success; +#ifdef SSS_HAVE_OPENSSL + if (keyStore->objects == NULL) { + keyStore->max_object_count = MAX_KEY_OBJ_COUNT; + keyStore->objects = (sss_openssl_object_t **)SSS_MALLOC(MAX_KEY_OBJ_COUNT * sizeof(sss_openssl_object_t *)); + memset(keyStore->objects, 0, (MAX_KEY_OBJ_COUNT * sizeof(sss_openssl_object_t *))); + if (NULL == keyStore->objects) { + LOG_E("Could not allocate key store"); + retval = kStatus_SSS_Fail; + } + else { + ks_sw_fat_allocate(&keyStore->keystore_shadow); + ks_sw_fat_load(keyStore->session->szRootPath, keyStore->keystore_shadow); + retval = kStatus_SSS_Success; + } + } + else { + LOG_E("KeyStore already allocated"); + retval = kStatus_SSS_Fail; + } +#endif +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_store_save(sss_openssl_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyStore->session); +#ifdef SSS_HAVE_OPENSSL + ENSURE_OR_GO_CLEANUP(keyStore->session->szRootPath); + if (NULL != keyStore->objects) { + uint32_t i; + for (i = 0; i < keyStore->max_object_count; i++) { + if (NULL != keyStore->objects[i]) { + retval = ks_openssl_store_key(keyStore->objects[i]); + /*Check added as part of security boundry checks*/ + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + } + } + } + retval = ks_openssl_fat_update(keyStore); +#endif +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_store_load(sss_openssl_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_CLEANUP(keyStore); + ENSURE_OR_GO_CLEANUP(keyStore->session); +#ifdef SSS_HAVE_OPENSSL + if (keyStore->objects == NULL) { + retval = sss_openssl_key_store_allocate(keyStore, 0); + /*Check added as part of security boundry checks*/ + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + } + if (keyStore->session->szRootPath) { + if (NULL == keyStore->keystore_shadow) { + ks_sw_fat_allocate(&keyStore->keystore_shadow); + } + retval = ks_sw_fat_load(keyStore->session->szRootPath, keyStore->keystore_shadow); + keyStore->max_object_count = keyStore->keystore_shadow->maxEntries; + } +#endif +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_store_set_key(sss_openssl_key_store_t *keyStore, + sss_openssl_object_t *keyObject, + const uint8_t *data, + size_t dataLen, + size_t keyBitLen, + void *options, + size_t optionsLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + uint8_t opensslData[256] = { + 0, + }; + size_t opensslDataLen = sizeof(opensslData); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + if (!(keyObject->accessRights & kAccessPermission_SSS_Write)) { + return retval; + } + + if ((keyObject->objectType == kSSS_KeyPart_Pair) && (keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY)) { + LOG_W("OpenSSL keystore cannot handle EC_MONT keypair with public key: Removing public key"); + ENSURE_OR_GO_CLEANUP(dataLen <= opensslDataLen); + memcpy(opensslData, data, dataLen); + if ((data[1] == 0x51) && (data[4] == 1)) { + opensslData[1] -= 0x23; + opensslData[4] = 0; + opensslDataLen = dataLen - 0x23; + } + else if ((data[1] == 0x81) && (data[4] == 1)) { + opensslData[1] -= 0x3b; + opensslData[4] = 0; + opensslDataLen = dataLen - 0x3b; + } + else { + LOG_E("OpenSSL keystore cannot handle EC_MONT keypair with public key: Cannot remove public key"); + opensslDataLen = dataLen; + } + retval = sss_openssl_set_key(keyObject, opensslData, opensslDataLen, keyBitLen); + } + else { + retval = sss_openssl_set_key(keyObject, data, dataLen, keyBitLen); + } +cleanup: + return retval; +} + +sss_status_t sss_openssl_key_store_generate_key( + sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject, size_t keyBitLen, void *options) +{ + sss_status_t retval = kStatus_SSS_Success; + + sss_cipher_type_t cipher_type = keyObject->cipherType; + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + + switch (cipher_type) { + case kSSS_CipherType_EC_NIST_P: + case kSSS_CipherType_EC_NIST_K: + case kSSS_CipherType_EC_BRAINPOOL: + case kSSS_CipherType_EC_MONTGOMERY: + case kSSS_CipherType_EC_TWISTED_ED: + retval = sss_openssl_generate_ecp_key(keyObject, keyBitLen); + break; + case kSSS_CipherType_RSA: + retval = sss_openssl_generate_rsa_key(keyObject, keyBitLen); + break; + default: + break; + } +exit: + return retval; +} + +sss_status_t sss_openssl_key_store_get_key(sss_openssl_key_store_t *keyStore, + sss_openssl_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + EVP_PKEY *pk = NULL; + int len = 0; + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->contents); + if (!(keyObject->accessRights & kAccessPermission_SSS_Read)) { + return kStatus_SSS_Fail; + } + + switch (keyObject->objectType) { + case kSSS_KeyPart_Default: + memcpy(data, keyObject->contents, keyObject->contents_size); + *dataLen = keyObject->contents_size; + break; + case kSSS_KeyPart_Public: + case kSSS_KeyPart_Pair: { + pk = (EVP_PKEY *)keyObject->contents; + len = i2d_PUBKEY(pk, &data); + if (len < 0 || (int)(*dataLen) < len) { + goto cleanup; + } + + *dataLen = len; + *pKeyBitLen = len * 8; + break; + } + default: + break; + } + + retval = kStatus_SSS_Success; +cleanup: + return retval; +} +#if 0 +/* To be reviewed: Purnank */ +sss_status_t sss_openssl_key_store_get_key_fromoffset(sss_openssl_key_store_t *keyStore, + sss_openssl_object_t *keyObject, + uint8_t *data, + size_t *dataLen, + size_t *pKeyBitLen, + uint16_t offset) +{ + sss_status_t retval = kStatus_SSS_Success; + return retval; +} +#endif +sss_status_t sss_openssl_key_store_open_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Success; + return retval; +} + +sss_status_t sss_openssl_key_store_freeze_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Success; + return retval; +} + +sss_status_t sss_openssl_key_store_erase_key(sss_openssl_key_store_t *keyStore, sss_openssl_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + ENSURE_OR_GO_EXIT(keyObject->keyStore); + + if (!(keyObject->accessRights & kAccessPermission_SSS_Delete)) { + LOG_E("Don't have access right to delete the key"); + return retval; + } + + if (keyObject->keyMode == kKeyObject_Mode_Persistent) { +#ifdef SSS_HAVE_OPENSSL + unsigned int i = 0; + /* first check if key exists delete key from shadow KS*/ + retval = ks_common_remove_fat(keyObject->keyStore->keystore_shadow, keyObject->keyId); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + /* Update shadow keystore in file system*/ + retval = ks_openssl_fat_update(keyObject->keyStore); + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + /*Clear key object from file*/ + retval = ks_openssl_remove_key(keyObject); + /*Check added as part of security boundary checks*/ + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + + for (i = 0; i < keyObject->keyStore->max_object_count; i++) { + if (keyObject->keyStore->objects[i] == keyObject) { + keyObject->keyStore->objects[i] = NULL; + break; + } + } +#endif + } + else { + retval = kStatus_SSS_Success; + } +#ifdef SSS_HAVE_OPENSSL +cleanup: +#endif +exit: + return retval; +} + +void sss_openssl_key_store_context_free(sss_openssl_key_store_t *keyStore) +{ + if (NULL != keyStore->objects) { + uint32_t i; + for (i = 0; i < keyStore->max_object_count; i++) { + if (keyStore->objects[i] != NULL) { + sss_openssl_key_object_free(keyStore->objects[i]); + keyStore->objects[i] = NULL; + } + } + SSS_FREE(keyStore->objects); + } + + ks_sw_fat_free(keyStore->keystore_shadow); + memset(keyStore, 0, sizeof(*keyStore)); +} + +int openssl_get_padding(sss_algorithm_t algorithm) +{ + int padding = 0; + switch (algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH: + case kAlgorithm_SSS_RSAES_PKCS1_V1_5: + padding = RSA_PKCS1_PADDING; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + padding = RSA_PKCS1_PSS_PADDING; + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512: + padding = RSA_PKCS1_OAEP_PADDING; + break; + default: + padding = RSA_PKCS1_PADDING; + } + return padding; +} + +/* End: openssl_keystore */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_asym */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_asymmetric_context_init(sss_openssl_asymmetric_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + + ENSURE_OR_GO_CLEANUP(context); + ENSURE_OR_GO_CLEANUP(keyObject); + ENSURE_OR_GO_CLEANUP(keyObject->keyStore->session->subsystem == kType_SSS_OpenSSL); + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_openssl_asymmetric_encrypt( + sss_openssl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Success; + int ret; + sss_openssl_object_t *keyObj = context->keyObject; + EVP_PKEY *pKey = NULL; + RSA *pRSA = NULL; + char *pErr = NULL; + int padding = 0; + + if (!(context->keyObject->accessRights & kAccessPermission_SSS_Use)) { + return kStatus_SSS_Fail; + } + + /* Get the RSA Key. */ + pKey = (EVP_PKEY *)keyObj->contents; + pRSA = EVP_PKEY_get1_RSA(pKey); + + padding = openssl_get_padding(context->algorithm); + + /* Encrypt the mesasage. */ + ret = RSA_public_encrypt((int)srcLen, srcData, destData, pRSA, padding); + if (ret == -1) { + retval = kStatus_SSS_Fail; + ERR_load_crypto_strings(); + pErr = SSS_MALLOC(150); + ERR_error_string(ERR_get_error(), pErr); + LOG_E("sss_openssl_asymmetric_encrypt"); + goto exit; + } + else { + *destLen = ret; + } + +exit: + return retval; +} + +sss_status_t sss_openssl_asymmetric_decrypt( + sss_openssl_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Success; + int ret; + sss_openssl_object_t *keyObj = context->keyObject; + EVP_PKEY *pKey = NULL; + RSA *pRSA = NULL; + char *pErr = NULL; + int padding = 0; + + if (!(context->keyObject->accessRights & kAccessPermission_SSS_Use)) { + return kStatus_SSS_Fail; + } + + /* Get the RSA Key. */ + pKey = (EVP_PKEY *)keyObj->contents; + pRSA = EVP_PKEY_get1_RSA(pKey); + + padding = openssl_get_padding(context->algorithm); + + /* Decrypt the mesasage. */ + ret = RSA_private_decrypt((int)srcLen, srcData, destData, pRSA, padding); + if (ret == -1) { + retval = kStatus_SSS_Fail; + ERR_load_crypto_strings(); + pErr = SSS_MALLOC(150); + ERR_error_string(ERR_get_error(), pErr); + LOG_E("sss_openssl_asymmetric_encrypt"); + goto exit; + } + else { + *destLen = ret; + } + +exit: + return retval; +} + +void *openssl_get_hash_ptr_set_padding(sss_algorithm_t algorithm, uint32_t cipherType, EVP_PKEY_CTX *pKey_Ctx) +{ + void *hashfPtr = NULL; + switch (algorithm) { + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_ECDSA_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1: { + hashfPtr = (void *)EVP_sha1(); + } break; + case kAlgorithm_SSS_SHA224: + case kAlgorithm_SSS_ECDSA_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224: { + hashfPtr = (void *)EVP_sha224(); + } break; + case kAlgorithm_SSS_SHA256: + case kAlgorithm_SSS_ECDSA_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + case kAlgorithm_SSS_RSAES_PKCS1_V1_5: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256: + case kAlgorithm_SSS_ECDAA: { + hashfPtr = (void *)EVP_sha256(); + } break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_ECDSA_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384: { + hashfPtr = (void *)EVP_sha384(); + } break; + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_ECDSA_SHA512: + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512: { + hashfPtr = (void *)EVP_sha512(); + } break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH: + default: + hashfPtr = NULL; + } + + if (cipherType == kSSS_CipherType_RSA || cipherType == kSSS_CipherType_RSA_CRT) { + EVP_PKEY_CTX_set_rsa_padding(pKey_Ctx, openssl_get_padding(algorithm)); + } + else { + //No padding for ECC Sign + //EVP_CIPHER_CTX_set_padding(pKey_Ctx, 0); + } + + return hashfPtr; +} + +sss_status_t sss_openssl_asymmetric_sign_digest( + sss_openssl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen) +{ + sss_status_t retval = kStatus_SSS_Success; + EVP_PKEY *pKey = NULL; + EVP_PKEY_CTX *pKey_Ctx = NULL; + void *hashfPtr = NULL; + int ret = 0; + + if (!(context->keyObject->accessRights & kAccessPermission_SSS_Use)) { + return kStatus_SSS_Fail; + } + + pKey = (EVP_PKEY *)context->keyObject->contents; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + if (context->keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + EVP_MD_CTX *pKey_md_Ctx = NULL; + pKey_md_Ctx = (EVP_MD_CTX *)EVP_MD_CTX_create(); + if (1 != EVP_DigestSignInit(pKey_md_Ctx, NULL, NULL, NULL, pKey)) { + retval = kStatus_SSS_Fail; + goto exit; + } + if (1 != EVP_DigestSign(pKey_md_Ctx, signature, signatureLen, digest, digestLen)) { + retval = kStatus_SSS_Fail; + } + goto exit; + } +#endif + /* Get the context from EVP_PKEY */ + pKey_Ctx = EVP_PKEY_CTX_new(pKey, NULL); + + /* Init the Signing context. */ + if (1 != EVP_PKEY_sign_init(pKey_Ctx)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Set the Signing MD. */ + hashfPtr = openssl_get_hash_ptr_set_padding(context->algorithm, context->keyObject->cipherType, pKey_Ctx); + + /* + * For RSA, null hash pointer is valid, as sign with no hash is available. + * Sign with no hash is invalid for ecc keys. + */ + if (context->keyObject->cipherType == kSSS_CipherType_EC_NIST_P || + context->keyObject->cipherType == kSSS_CipherType_EC_NIST_K || + context->keyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + context->keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED || + context->keyObject->cipherType == kSSS_CipherType_EC_BARRETO_NAEHRIG) { + ENSURE_OR_GO_EXIT(NULL != hashfPtr); + } + + /* Explicitly set the salt length to match the digest size (-1) + * #define RSA_PSS_SALTLEN_DIGEST -1, this is defined only in openssl 1.1 + * Define it explicitly in this file. + */ + EVP_PKEY_CTX_set_rsa_pss_saltlen(pKey_Ctx, RSA_PSS_SALTLEN_DIGEST); + + if (1 != EVP_PKEY_CTX_set_signature_md(pKey_Ctx, hashfPtr)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Set the Signature length to 0. */ + *signatureLen = 0; + + /* Determine buffer length */ + ret = EVP_PKEY_sign(pKey_Ctx, NULL, signatureLen, digest, digestLen); + if (ret <= 0) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Perfom Signing of the message. */ + ret = EVP_PKEY_sign(pKey_Ctx, signature, signatureLen, digest, digestLen); + if (ret <= 0) { + retval = kStatus_SSS_Fail; + goto exit; + } + +exit: + EVP_PKEY_CTX_free(pKey_Ctx); + pKey_Ctx = NULL; + return retval; +} + +sss_status_t sss_openssl_asymmetric_verify_digest( + sss_openssl_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen) +{ + sss_status_t retval = kStatus_SSS_Success; + EVP_PKEY *pKey = NULL; + EVP_PKEY_CTX *pKey_Ctx = NULL; + void *hashfPtr = NULL; + int ret = 0; + + if (!(context->keyObject->accessRights & kAccessPermission_SSS_Use)) { + return kStatus_SSS_Fail; + } + + pKey = (EVP_PKEY *)context->keyObject->contents; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + if (context->keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + EVP_MD_CTX *pKey_md_Ctx = NULL; + pKey_md_Ctx = (EVP_MD_CTX *)EVP_MD_CTX_create(); + if (1 != EVP_DigestVerifyInit(pKey_md_Ctx, NULL, NULL, NULL, pKey)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (1 != EVP_DigestVerify(pKey_md_Ctx, signature, signatureLen, digest, digestLen)) { + retval = kStatus_SSS_Fail; + } + goto exit; + } +#endif + + /* Get the context from EVP_PKEY */ + pKey_Ctx = EVP_PKEY_CTX_new(pKey, NULL); + + /* Init the Verfying context. */ + if (1 != EVP_PKEY_verify_init(pKey_Ctx)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Set the Signing MD. */ + hashfPtr = openssl_get_hash_ptr_set_padding(context->algorithm, context->keyObject->cipherType, pKey_Ctx); + + /* + * For RSA, null hash pointer is valid, as sign with no hash is available. + * Sign with no hash is invalid for ecc keys. + */ + if (context->keyObject->cipherType == kSSS_CipherType_EC_NIST_P || + context->keyObject->cipherType == kSSS_CipherType_EC_NIST_K || + context->keyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + context->keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED || + context->keyObject->cipherType == kSSS_CipherType_EC_BARRETO_NAEHRIG) { + ENSURE_OR_GO_EXIT(NULL != hashfPtr); + } + + if (1 != EVP_PKEY_CTX_set_signature_md(pKey_Ctx, hashfPtr)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Perfom Verification of the message. */ + ret = EVP_PKEY_verify(pKey_Ctx, signature, signatureLen, digest, digestLen); + if (1 != ret) { + retval = kStatus_SSS_Fail; + goto exit; + } + +exit: + EVP_PKEY_CTX_free(pKey_Ctx); + pKey_Ctx = NULL; + return retval; +} + +sss_status_t sss_openssl_asymmetric_sign( + sss_openssl_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + EVP_MD_CTX *pKey_md_Ctx = NULL; + EVP_PKEY *pKey = NULL; + + pKey = (EVP_PKEY *)context->keyObject->contents; + + if (context->keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + pKey_md_Ctx = (EVP_MD_CTX *)EVP_MD_CTX_create(); + if (1 != EVP_DigestSignInit(pKey_md_Ctx, NULL, NULL, NULL, pKey)) { + goto exit; + } + + if (1 != EVP_DigestSign(pKey_md_Ctx, destData, destLen, srcData, srcLen)) { + goto exit; + } + } + else { + goto exit; + } + + retval = kStatus_SSS_Success; +#endif +exit: + return retval; +} + +sss_status_t sss_openssl_asymmetric_verify( + sss_openssl_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + EVP_MD_CTX *pKey_md_Ctx = NULL; + EVP_PKEY *pKey = NULL; + + pKey = (EVP_PKEY *)context->keyObject->contents; + + if (context->keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + pKey_md_Ctx = (EVP_MD_CTX *)EVP_MD_CTX_create(); + if (1 != EVP_DigestVerifyInit(pKey_md_Ctx, NULL, NULL, NULL, pKey)) { + goto exit; + } + + if (1 != EVP_DigestVerify(pKey_md_Ctx, signature, signatureLen, srcData, srcLen)) { + goto exit; + } + } + else { + goto exit; + } + + retval = kStatus_SSS_Success; +#endif +exit: + return retval; +} + +void sss_openssl_asymmetric_context_free(sss_openssl_asymmetric_t *context) +{ + memset(context, 0, sizeof(*context)); +} + +/* End: openssl_asym */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_symm */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_symmetric_context_init(sss_openssl_symmetric_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + context->cache_data_len = 0; + context->cipher_ctx = NULL; + + return retval; +} + +sss_status_t sss_openssl_cipher_one_go(sss_openssl_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if !SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO + AES_KEY AESKey; +#endif + DES_key_schedule schedule; + DES_cblock DESKey; + +#if SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO + if (context->algorithm == kAlgorithm_SSS_AES_ECB || + context->algorithm == kAlgorithm_SSS_AES_CBC || + context->algorithm == kAlgorithm_SSS_AES_CTR) { + + sss_status_t status = kStatus_SSS_Fail; + size_t destLen = dataLen; + + status = sss_openssl_cipher_init(context, iv, ivLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = sss_openssl_cipher_update(context, srcData, dataLen, destData, &destLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + destLen = dataLen - destLen; + status = sss_openssl_cipher_finish(context, NULL, 0, (destData + destLen), &destLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + return kStatus_SSS_Success; + } +#endif + + switch (context->algorithm) { +#if !SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO + case kAlgorithm_SSS_AES_ECB: + case kAlgorithm_SSS_AES_CBC: { + if (context->mode == kMode_SSS_Encrypt) { + if (AES_set_encrypt_key((uint8_t *)context->keyObject->contents, + (int)(context->keyObject->contents_size * 8), + &AESKey) < 0) { + retval = kStatus_SSS_Fail; + LOG_E("Key initialization failed"); + goto exit; + } + } + else if (context->mode == kMode_SSS_Decrypt) { + if (AES_set_decrypt_key((uint8_t *)context->keyObject->contents, + (int)(context->keyObject->contents_size * 8), + &AESKey) < 0) { + retval = kStatus_SSS_Fail; + LOG_E("Key initialization failed"); + goto exit; + } + } + } break; + case kAlgorithm_SSS_AES_CTR: { + if (AES_set_encrypt_key( + (uint8_t *)context->keyObject->contents, (int)(context->keyObject->contents_size * 8), &AESKey) < 0) { + retval = kStatus_SSS_Fail; + LOG_E("Key initialization failed"); + goto exit; + } + } break; +#endif + case kAlgorithm_SSS_DES_CBC: + case kAlgorithm_SSS_DES_ECB: + case kAlgorithm_SSS_DES3_CBC: + case kAlgorithm_SSS_DES3_ECB: { + memcpy(DESKey, (const char *)context->keyObject->contents, context->keyObject->contents_size); + DES_set_key(&DESKey, &schedule); + break; + } + default: + return retval; + } + + if (context->mode == kMode_SSS_Encrypt) { + switch (context->algorithm) { +#if !SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO + case kAlgorithm_SSS_AES_ECB: + AES_ecb_encrypt(srcData, destData, &AESKey, AES_ENCRYPT); + break; + case kAlgorithm_SSS_AES_CBC: + AES_cbc_encrypt(srcData, destData, dataLen, &AESKey, iv, AES_ENCRYPT); + break; + case kAlgorithm_SSS_AES_CTR: { + unsigned char ecount_buf[16] = { + 0, + }; + unsigned int num = 0; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + AES_ctr128_encrypt(srcData, destData, dataLen, &AESKey, iv, ecount_buf, &num); +#else + CRYPTO_ctr128_encrypt(srcData, destData, dataLen, &AESKey, iv, ecount_buf, &num, (block128_f)AES_encrypt); +#endif + } break; +#endif + case kAlgorithm_SSS_DES_ECB: { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + DES_ecb_encrypt((const_DES_cblock *)srcData, (DES_cblock *)destData, &schedule, DES_ENCRYPT); +#else + size_t rem = dataLen; + int offset = 0; + if (dataLen % 8 != 0) { + LOG_E("Input should be 8 byte aligned for DES ECB"); + return kStatus_SSS_Fail; + } + + while ((rem > 0) && (rem % 8 == 0)) { + DES_ecb_encrypt( + (const_DES_cblock *)(srcData + offset), (DES_cblock *)(destData + offset), &schedule, DES_ENCRYPT); + offset = offset + 8; + rem = rem - 8; + } +#endif + } break; + case kAlgorithm_SSS_DES_CBC: + DES_cbc_encrypt(srcData, destData, (int)dataLen, &schedule, (DES_cblock *)iv, DES_ENCRYPT); + break; + default: + break; + } + } + else if (context->mode == kMode_SSS_Decrypt) { + switch (context->algorithm) { +#if !SSS_OPENSSL_USE_EVP_FOR_CIPHER_ONE_GO + case kAlgorithm_SSS_AES_ECB: + AES_ecb_encrypt(srcData, destData, &AESKey, AES_DECRYPT); + break; + case kAlgorithm_SSS_AES_CBC: + AES_cbc_encrypt(srcData, destData, dataLen, &AESKey, iv, AES_DECRYPT); + break; + case kAlgorithm_SSS_AES_CTR: { + unsigned char ecount_buf[16] = { + 0, + }; + unsigned int num = 0; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + AES_ctr128_encrypt(srcData, destData, dataLen, &AESKey, iv, ecount_buf, &num); +#else + CRYPTO_ctr128_encrypt(srcData, destData, dataLen, &AESKey, iv, ecount_buf, &num, (block128_f)AES_encrypt); +#endif + } break; +#endif + case kAlgorithm_SSS_DES_ECB: { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + DES_ecb_encrypt((const_DES_cblock *)srcData, (DES_cblock *)destData, &schedule, DES_DECRYPT); +#else + size_t rem = dataLen; + int offset = 0; + if (dataLen % 8 != 0) { + LOG_E("Input should be 8 byte aligned for DES ECB"); + return kStatus_SSS_Fail; + } + + while ((rem > 0) && (rem % 8 == 0)) { + DES_ecb_encrypt( + (const_DES_cblock *)(srcData + offset), (DES_cblock *)(destData + offset), &schedule, DES_DECRYPT); + offset = offset + 8; + rem = rem - 8; + } +#endif + } break; + case kAlgorithm_SSS_DES_CBC: + DES_cbc_encrypt(srcData, destData, (long)dataLen, &schedule, (DES_cblock *)iv, DES_DECRYPT); + break; + default: + break; + } + } + else { + return retval; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_cipher_init(sss_openssl_symmetric_t *context, uint8_t *iv, size_t ivLen) +{ + sss_status_t retval = kStatus_SSS_Success; + const EVP_CIPHER *cipher_info = NULL; + + ENSURE_OR_GO_EXIT(context != NULL); + if (ivLen > 0){ + ENSURE_OR_GO_EXIT(iv != NULL); + } + + if (context->algorithm == kAlgorithm_SSS_AES_ECB) { + switch (context->keyObject->keyBitLen) { + case 128: + cipher_info = EVP_aes_128_ecb(); + break; + case 192: + cipher_info = EVP_aes_192_ecb(); + break; + case 256: + cipher_info = EVP_aes_256_ecb(); + break; + default: + goto exit; + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CBC) { + switch (context->keyObject->keyBitLen) { + case 128: + cipher_info = EVP_aes_128_cbc(); + break; + case 192: + cipher_info = EVP_aes_192_cbc(); + break; + case 256: + cipher_info = EVP_aes_256_cbc(); + break; + default: + goto exit; + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CTR) { + switch (context->keyObject->keyBitLen) { + case 128: + cipher_info = EVP_aes_128_ctr(); + break; + case 192: + cipher_info = EVP_aes_192_ctr(); + break; + case 256: + cipher_info = EVP_aes_256_ctr(); + break; + default: + goto exit; + } + } + + /* Create and initialise the context */ + context->cipher_ctx = EVP_CIPHER_CTX_new(); + if (!(context->cipher_ctx)) { + retval = kStatus_SSS_InvalidArgument; + LOG_E(" Cipher initialization failed "); + goto exit; + } + + if (context->mode == kMode_SSS_Encrypt) { + /* Initialise the encryption operation. IMPORTANT - ensure you use a key + * and IV size appropriate for your cipher + */ + if (1 != EVP_CipherInit(context->cipher_ctx, cipher_info, context->keyObject->contents, iv, 1)) { + retval = kStatus_SSS_InvalidArgument; + LOG_E("EncryptionCipher initialization failed !!!"); + + goto exit; + } + + EVP_CIPHER_CTX_set_padding(context->cipher_ctx, 0); + } + else if (context->mode == kMode_SSS_Decrypt) { + /* Initialise the encryption operation. IMPORTANT - ensure you use a key + * and IV size appropriate for your cipher + */ + if (1 != EVP_CipherInit(context->cipher_ctx, cipher_info, context->keyObject->contents, iv, 0)) { + retval = kStatus_SSS_InvalidArgument; + LOG_E(" DecryptionCipher initialization failed"); + goto exit; + } + + EVP_CIPHER_CTX_set_padding(context->cipher_ctx, 0); + } + else { + retval = kStatus_SSS_InvalidArgument; + } + +exit: + return retval; +} + +sss_status_t sss_openssl_cipher_update( + sss_openssl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + uint8_t inputData[CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (srcLen > 0) { + ENSURE_OR_GO_EXIT(srcData != NULL); + } + ENSURE_OR_GO_EXIT(destLen != NULL); + if (*destLen > 0) { + ENSURE_OR_GO_EXIT(destData != NULL); + } + + if ((context->cache_data_len + srcLen) < CIPHER_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + memcpy((inputData + inputData_len), srcData, (CIPHER_BLOCK_SIZE - context->cache_data_len)); + inputData_len += (CIPHER_BLOCK_SIZE - context->cache_data_len); + src_offset += (CIPHER_BLOCK_SIZE - context->cache_data_len); + context->cache_data_len = 0; + + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= inputData_len); + if (1 != + EVP_CipherUpdate( + context->cipher_ctx, (destData + output_offset), (int *)&blockoutLen, inputData, (int)inputData_len)) { + goto exit; + } + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + + while (srcLen - src_offset >= CIPHER_BLOCK_SIZE) { + memcpy(inputData, (srcData + src_offset), CIPHER_BLOCK_SIZE); + src_offset += CIPHER_BLOCK_SIZE; + + blockoutLen = outBuffSize; + inputData_len = CIPHER_BLOCK_SIZE; + ENSURE_OR_GO_EXIT(blockoutLen >= inputData_len); + if (1 != EVP_CipherUpdate(context->cipher_ctx, + (destData + output_offset), + (int *)&blockoutLen, + inputData, + (int)inputData_len)) { + goto exit; + } + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + } + + *destLen = output_offset; + + /* Copy unprocessed data to cache */ + if ((srcLen - src_offset) > 0) { + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + } + + retval = kStatus_SSS_Success; +exit: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } + return retval; +} + +sss_status_t sss_openssl_cipher_finish( + sss_openssl_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + uint8_t dummyBuf[CIPHER_BLOCK_SIZE] = { + 0, + }; + int dummyBufLen = sizeof(dummyBuf); + + ENSURE_OR_GO_EXIT(context != NULL); + if (srcLen > 0) { + ENSURE_OR_GO_EXIT(srcData != NULL); + } + ENSURE_OR_GO_EXIT(destLen != NULL); + if (*destLen > 0) { + ENSURE_OR_GO_EXIT(destData != NULL); + } + + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + context->cache_data_len = 0; + } + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + + if (srcdata_updated_len > 0) { + srcdata_updated_len = srcdata_updated_len + (CIPHER_BLOCK_SIZE - (srcdata_updated_len % CIPHER_BLOCK_SIZE)); + } + + if (*destLen < srcdata_updated_len) { + LOG_E("Output buffer not sufficient"); + goto exit; + } + + if (srcdata_updated_len > 0) { + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= CIPHER_BLOCK_SIZE); + if (1 != + EVP_CipherUpdate(context->cipher_ctx, destData, (int *)&blockoutLen, srcdata_updated, CIPHER_BLOCK_SIZE)) { + goto exit; + } + *destLen = blockoutLen; + outBuffSize -= blockoutLen; + } + + if (srcdata_updated_len > CIPHER_BLOCK_SIZE) { + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= CIPHER_BLOCK_SIZE); + if (1 != EVP_CipherUpdate(context->cipher_ctx, + destData + CIPHER_BLOCK_SIZE, + (int *)&blockoutLen, + srcdata_updated + CIPHER_BLOCK_SIZE, + CIPHER_BLOCK_SIZE)) { + goto exit; + } + *destLen += blockoutLen; + outBuffSize -= blockoutLen; + } + + /* All data processed using EVP_CipherUpdate call. EVP_CipherFinal call will be dummy call. + No encrypted/decrypted output will be generated */ + if (1 != EVP_CipherFinal(context->cipher_ctx, dummyBuf, &dummyBufLen)) { + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_cipher_crypt_ctr(sss_openssl_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft) +{ + sss_status_t retval = kStatus_SSS_Fail; + AES_KEY key; + + ENSURE_OR_GO_EXIT(context != NULL); + if (size > 0) { + ENSURE_OR_GO_EXIT(srcData != NULL); + ENSURE_OR_GO_EXIT(destData != NULL); + } + + if (AES_set_encrypt_key( + (uint8_t *)context->keyObject->contents, (int)(context->keyObject->contents_size * 8), &key) < 0) { + goto exit; + } + + switch (context->keyObject->keyBitLen) { + case 128: + case 192: + case 256: { + unsigned int iLeft = (unsigned int)*szLeft; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + AES_ctr128_encrypt(srcData, destData, size, &key, initialCounter, lastEncryptedCounter, &iLeft); +#else + CRYPTO_ctr128_encrypt( + srcData, destData, size, &key, initialCounter, lastEncryptedCounter, &iLeft, (block128_f)AES_encrypt); +#endif + *szLeft = iLeft; + break; + } + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_openssl_symmetric_context_free(sss_openssl_symmetric_t *context) +{ + if (context->cipher_ctx != NULL) { + EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)context->cipher_ctx); + context->cipher_ctx = NULL; + } + memset(context, 0, sizeof(*context)); +} + +/* End: openssl_symm */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_aead */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_aead_context_init(sss_openssl_aead_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + context->session = session; + context->keyObject = keyObject; + context->mode = mode; + + ENSURE_OR_GO_EXIT(context != NULL); + ENSURE_OR_GO_EXIT(session != NULL); + ENSURE_OR_GO_EXIT(keyObject != NULL); + + if (algorithm == kAlgorithm_SSS_AES_GCM || algorithm == kAlgorithm_SSS_AES_CCM) { + context->algorithm = algorithm; + } + else { + LOG_E("AEAD improper algorithm passed!!!"); + goto exit; + } + /* Create and initialise the context */ + context->aead_ctx = EVP_CIPHER_CTX_new(); + ENSURE_OR_GO_EXIT(context->aead_ctx != NULL); + context->pCcm_aad = NULL; + context->pCcm_data = NULL; + context->pCcm_iv = NULL; + context->pCcm_tag = NULL; + retval = sss_openssl_aead_init_ctx(context); + +exit: + return retval; +} + +static sss_status_t sss_openssl_aead_init_ctx(sss_openssl_aead_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; + const EVP_CIPHER *aead_info = NULL; + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + switch (context->keyObject->keyBitLen) { + case 128: + aead_info = EVP_aes_128_gcm(); + break; + case 192: + aead_info = EVP_aes_192_gcm(); + break; + case 256: + aead_info = EVP_aes_256_gcm(); + break; + default: + LOG_E("Improper key size!"); + goto exit; + } + } + else if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + switch (context->keyObject->keyBitLen) { + case 128: + aead_info = EVP_aes_128_ccm(); + break; + case 192: + aead_info = EVP_aes_192_ccm(); + break; + case 256: + aead_info = EVP_aes_256_ccm(); + break; + default: + LOG_E("Improper key size!"); + goto exit; + } + } + if (context->mode == kMode_SSS_Encrypt) { + /* Initialise the encryption operation. */ + ret = EVP_EncryptInit_ex(context->aead_ctx, aead_info, NULL, NULL, NULL); + } + else if (context->mode == kMode_SSS_Decrypt) { + /* Initialise the decryption operation. */ + ret = EVP_DecryptInit_ex(context->aead_ctx, aead_info, NULL, NULL, NULL); + } + ENSURE_OR_GO_EXIT(ret == 1); + retval = kStatus_SSS_Success; + +exit: + return retval; +} + +sss_status_t sss_openssl_aead_one_go(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (size > 0) { + ENSURE_OR_GO_EXIT(srcData != NULL); + ENSURE_OR_GO_EXIT(destData != NULL); + } + if(nonceLen > 0){ + ENSURE_OR_GO_EXIT(nonce != NULL); + } + if(aadLen > 0){ + ENSURE_OR_GO_EXIT(aad != NULL); + } + + /* Set IV length if default 96 bits is not appropriate */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_GCM_SET_IVLEN, nonceLen, NULL); + ENSURE_OR_GO_EXIT(ret == 1); + context->pCcm_data = NULL; + + /* Check mode do the operation requested */ + if (context->mode == kMode_SSS_Encrypt) { + retval = sss_openssl_aead_one_go_encrypt( + context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } + else if (context->mode == kMode_SSS_Decrypt) { + retval = sss_openssl_aead_one_go_decrypt( + context, srcData, destData, size, nonce, nonceLen, aad, aadLen, tag, tagLen); + } + +exit: + return retval; +} + +sss_status_t sss_openssl_aead_init( + sss_openssl_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (nonceLen > 0){ + ENSURE_OR_GO_EXIT(nonce != NULL); + } + + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_GCM_SET_IVLEN, nonceLen, NULL); + ENSURE_OR_GO_EXIT(ret == 1); + context->cache_data_len = 0; + memset(context->cache_data, 0x00, sizeof(context->cache_data)); + /* Initialise key and IV */ + { + if (context->mode == kMode_SSS_Encrypt) { + ret = EVP_EncryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, nonce); + } + else { + ret = EVP_DecryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, nonce); + } + ENSURE_OR_GO_EXIT(ret == 1); + } + } + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + context->pCcm_iv = nonce; + context->ccm_ivLen = nonceLen; + context->ccm_tagLen = tagLen; + context->ccm_aadLen = aadLen; + context->ccm_dataTotalLen = payloadLen; + if (context->ccm_dataTotalLen) { + context->pCcm_data = SSS_MALLOC(payloadLen); + if (context->pCcm_data) { + memset(context->pCcm_data, 0, payloadLen); + context->ccm_dataoffset = 0; + } + else { + LOG_E("malloc failed"); + goto exit; + } + } + } + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_aead_update_aad(sss_openssl_aead_t *context, const uint8_t *aadData, size_t aadDataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + int len = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (aadDataLen > 0){ + ENSURE_OR_GO_EXIT(aadData != NULL); + } + + /* Provide AAD data */ + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + if (context->mode == kMode_SSS_Decrypt) { + ret = EVP_DecryptUpdate(context->aead_ctx, NULL, &len, aadData, aadDataLen); + } + else { + ret = EVP_EncryptUpdate(context->aead_ctx, NULL, &len, aadData, aadDataLen); + } + ENSURE_OR_GO_EXIT(ret == 1); + } + else if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + context->pCcm_aad = aadData; + context->ccm_aadLen = aadDataLen; + } + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_aead_update( + sss_openssl_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + uint8_t inputData[CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + int ret = 0; + + ENSURE_OR_GO_CLEANUP(context != NULL); + if (srcLen > 0) { + ENSURE_OR_GO_CLEANUP(srcData != NULL); + } + ENSURE_OR_GO_CLEANUP(destLen != NULL); + if (*destLen > 0) { + ENSURE_OR_GO_CLEANUP(destData != NULL); + } + + /*Note for OpenSSL AES_CCM Update data is called only once*/ + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + if ((srcData != NULL) && (srcLen > 0)) { + retval = sss_openssl_aead_ccm_update(context, srcData, srcLen); + } + ENSURE_OR_GO_CLEANUP(retval == kStatus_SSS_Success); + *destLen = 0; + } + else { + if ((context->cache_data_len + srcLen) < CIPHER_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + memcpy((inputData + inputData_len), srcData, (CIPHER_BLOCK_SIZE - context->cache_data_len)); + inputData_len += (CIPHER_BLOCK_SIZE - context->cache_data_len); + src_offset += (CIPHER_BLOCK_SIZE - context->cache_data_len); + blockoutLen = outBuffSize; + + /* Add Source Data */ + ret = + aead_update(context, context->mode, inputData, inputData_len, (destData + output_offset), &blockoutLen); + ENSURE_OR_GO_CLEANUP(ret == 1); + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + + while (srcLen - src_offset >= CIPHER_BLOCK_SIZE) { + memcpy(inputData, (srcData + src_offset), 16); + src_offset += CIPHER_BLOCK_SIZE; + blockoutLen = outBuffSize; + + /* Add Source Data */ + ret = aead_update( + context, context->mode, inputData, inputData_len, (destData + output_offset), &blockoutLen); + ENSURE_OR_GO_CLEANUP(ret == 1); + + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + } + *destLen = output_offset; + /* Copy unprocessed data to cache */ + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + } + retval = kStatus_SSS_Success; + +cleanup: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } +#endif /*End of SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} +static sss_status_t sss_openssl_aead_ccm_update(sss_openssl_aead_t *context, const uint8_t *srcData, size_t srcLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + + if ((context->ccm_dataoffset + srcLen) <= (context->ccm_dataTotalLen)) { + memcpy(context->pCcm_data + context->ccm_dataoffset, srcData, srcLen); + context->ccm_dataoffset = context->ccm_dataoffset + srcLen; + retval = kStatus_SSS_Success; + } + else { + /*Free the allocated memory in init*/ + if (context->pCcm_data != NULL) { + SSS_FREE(context->pCcm_data); + context->pCcm_data = NULL; + } + } + return retval; +} + +static int aead_update(sss_openssl_aead_t *context, + sss_mode_t mode, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen) +{ + int ret = 0; +#if SSS_HAVE_TESTCOUNTERPART + int len = 0; + if (context->mode == kMode_SSS_Encrypt) { + ret = EVP_EncryptUpdate(context->aead_ctx, destData, &len, srcData, srcLen); + } + else if (context->mode == kMode_SSS_Decrypt) { + ret = EVP_DecryptUpdate(context->aead_ctx, destData, &len, srcData, srcLen); + } + *destLen = len; +#endif /*SSS_HAVE_TESTCOUNTERPART*/ + return ret; +} + +sss_status_t sss_openssl_aead_finish(sss_openssl_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (srcLen > 0){ + ENSURE_OR_GO_EXIT(srcData != NULL); + } + + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + int len = 0; + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { /* Check if finish has got source data */ + if ((srcData != NULL) && (srcLen > 0)) { + retval = sss_openssl_aead_ccm_update(context, srcData, srcLen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + } + retval = sss_openssl_aead_ccm_final(context, destData, destLen, tag, tagLen); + } + else { + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + } + + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + + /* Add Source Data */ + ret = aead_update(context, context->mode, srcdata_updated, srcdata_updated_len, destData, destLen); + ENSURE_OR_GO_EXIT(ret == 1); + + if (context->mode == kMode_SSS_Encrypt) { + ret = EVP_EncryptFinal_ex(context->aead_ctx, destData, &len); + ENSURE_OR_GO_EXIT(ret == 1); + (*destLen) += len; + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_GCM_GET_TAG, *tagLen, tag); + // *tagLen = EVP_CTRL_GCM_GET_TAG; + } + else if (context->mode == kMode_SSS_Decrypt) { + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_GCM_SET_TAG, *tagLen, tag); + ENSURE_OR_GO_EXIT(ret == 1); + + ret = EVP_DecryptFinal_ex(context->aead_ctx, destData + (*destLen), &len); + ENSURE_OR_GO_EXIT(ret == 1); + (*destLen) += len; + } + retval = kStatus_SSS_Success; + } +exit: +#endif /*SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} + +static sss_status_t sss_openssl_aead_ccm_final( + sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen, uint8_t *tag, size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + context->pCcm_tag = tag; + if (context->mode == kMode_SSS_Decrypt) { + retval = sss_openssl_aead_ccm_Decryptfinal(context, destData, destLen); + } + else { + retval = sss_openssl_aead_ccm_Encryptfinal(context, destData, destLen); + if (retval == kStatus_SSS_Success) { + tag = context->pCcm_tag; + *tagLen = context->ccm_tagLen; + } + } + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + *destLen = context->ccm_dataTotalLen; + retval = kStatus_SSS_Success; +exit: +#endif /*SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} + +static sss_status_t sss_openssl_aead_ccm_Encryptfinal(sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + int ret = 0; + int len = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + + /*Set IV len */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_SET_IVLEN, context->ccm_ivLen, NULL); + ENSURE_OR_GO_EXIT(ret == 1) + + /* Set tag length */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_SET_TAG, context->ccm_tagLen, NULL); + ENSURE_OR_GO_EXIT(ret == 1) + + /* Initialise key and IV */ + ret = EVP_EncryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, context->pCcm_iv); + ENSURE_OR_GO_EXIT(ret == 1); + /* Provide the total plain length */ + ret = EVP_EncryptUpdate(context->aead_ctx, NULL, &len, NULL, context->ccm_dataTotalLen); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Provide any AAD data*/ + ret = EVP_EncryptUpdate(context->aead_ctx, NULL, &len, context->pCcm_aad, context->ccm_aadLen); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Provide the message to be decrypted*/ + ret = EVP_EncryptUpdate(context->aead_ctx, destData, &len, context->pCcm_data, context->ccm_dataTotalLen); + ENSURE_OR_GO_EXIT(ret == 1); + *destLen = len; + len = 0; + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_GET_TAG, context->ccm_tagLen, context->pCcm_tag); + + ENSURE_OR_GO_EXIT(ret == 1); + //context->ccm_tagLen = len; + retval = kStatus_SSS_Success; +exit: +#endif /*SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} + +static sss_status_t sss_openssl_aead_ccm_Decryptfinal(sss_openssl_aead_t *context, uint8_t *destData, size_t *destLen) + +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_TESTCOUNTERPART + int ret = 0; + int len = 0; + int payloadlen = context->ccm_dataTotalLen; + + ENSURE_OR_GO_EXIT(context != NULL); + + /*Set IV len */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_SET_IVLEN, context->ccm_ivLen, NULL); + ENSURE_OR_GO_EXIT(ret == 1) + /* Set expected tag value. */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_SET_TAG, context->ccm_tagLen, context->pCcm_tag); + ENSURE_OR_GO_EXIT(ret == 1); + /* Initialise key and IV */ + ret = EVP_DecryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, context->pCcm_iv); + ENSURE_OR_GO_EXIT(ret == 1); + /* Provide the total ciphertext length */ + ret = EVP_DecryptUpdate(context->aead_ctx, NULL, &len, NULL, payloadlen); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Provide any AAD data*/ + ret = EVP_DecryptUpdate(context->aead_ctx, NULL, &len, context->pCcm_aad, context->ccm_aadLen); + ENSURE_OR_GO_EXIT(ret == 1); + /* Provide the message to be decrypted*/ + ret = EVP_DecryptUpdate(context->aead_ctx, destData, &len, context->pCcm_data, context->ccm_dataTotalLen); + ENSURE_OR_GO_EXIT(ret == 1); + *destLen = len; + retval = kStatus_SSS_Success; +exit: +#endif /*SSS_HAVE_TESTCOUNTERPART*/ + return retval; +} + +void sss_openssl_aead_context_free(sss_openssl_aead_t *context) +{ + if (context->aead_ctx != NULL) { + if ((context->algorithm == kAlgorithm_SSS_AES_CCM) && (context->pCcm_data != NULL)) { + SSS_FREE(context->pCcm_data); + context->pCcm_data = NULL; + } + EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)context->aead_ctx); + context->aead_ctx = NULL; + } + memset(context, 0, sizeof(*context)); +} + +/* End: openssl_aead */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_mac */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_mac_context_init(sss_openssl_mac_t *context, + sss_openssl_session_t *session, + sss_openssl_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + if (context != NULL) { + if (algorithm == kAlgorithm_SSS_CMAC_AES) { + context->cmac_ctx = CMAC_CTX_new(); + } + if (algorithm == kAlgorithm_SSS_HMAC_SHA1 || algorithm == kAlgorithm_SSS_HMAC_SHA224 || + algorithm == kAlgorithm_SSS_HMAC_SHA256 || algorithm == kAlgorithm_SSS_HMAC_SHA384 || + algorithm == kAlgorithm_SSS_HMAC_SHA512) { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + context->hmac_ctx = SSS_MALLOC(sizeof(HMAC_CTX)); +#else + context->hmac_ctx = HMAC_CTX_new(); +#endif + if (context->hmac_ctx != NULL) { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + HMAC_CTX_init(context->hmac_ctx); +#endif + } + } + context->session = session; + context->keyObject = keyObject; + context->mode = mode; + context->algorithm = algorithm; + retval = kStatus_SSS_Success; + } + + return retval; +} + +sss_status_t sss_openssl_mac_one_go( + sss_openssl_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + unsigned int iMacLen; + const EVP_CIPHER *cipher_info = NULL; + uint8_t *key; + size_t keylen; + + if ((context == NULL) || (message == NULL) || (mac == NULL) || (macLen == NULL)) { + goto cleanup; + } + + if (context->keyObject->contents) { + key = context->keyObject->contents; + keylen = context->keyObject->contents_size; + } + else { + LOG_E("KeyObject key not created"); + goto cleanup; + } + + iMacLen = (unsigned int)*macLen; + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + if (context->cmac_ctx == NULL) { + retval = kStatus_SSS_InvalidArgument; + } + else { + if (!(keylen == 16 || keylen == 24 || keylen == 32)) { + LOG_E("key bit not supported"); + goto cleanup; + } + + switch (keylen * 8) { + case 128: + cipher_info = EVP_aes_128_cbc(); + break; + case 192: + cipher_info = EVP_aes_192_cbc(); + break; + case 256: + cipher_info = EVP_aes_256_cbc(); + break; + } + + ret = CMAC_Init( + context->cmac_ctx, context->keyObject->contents, context->keyObject->contents_size, cipher_info, NULL); + if (ret == 1) { + ret = CMAC_Update(context->cmac_ctx, message, messageLen); + if (ret == 1) { + ret = CMAC_Final(context->cmac_ctx, mac, macLen); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + } + } + } + } + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + iMacLen = (unsigned int)*macLen; + const EVP_MD *evp_md = NULL; + switch (context->algorithm) { + case kAlgorithm_SSS_HMAC_SHA1: + evp_md = EVP_sha1(); + break; + case kAlgorithm_SSS_HMAC_SHA224: + evp_md = EVP_sha224(); + break; + case kAlgorithm_SSS_HMAC_SHA256: + evp_md = EVP_sha256(); + break; + case kAlgorithm_SSS_HMAC_SHA384: + evp_md = EVP_sha384(); + break; + case kAlgorithm_SSS_HMAC_SHA512: + evp_md = EVP_sha512(); + break; + default: + LOG_E("Invalid HMAC algorithm"); + retval = kStatus_SSS_Fail; + goto cleanup; + } + + if (NULL != HMAC(evp_md, + context->keyObject->contents, + (int)context->keyObject->contents_size, + message, + messageLen, + mac, + &iMacLen)) { + retval = kStatus_SSS_Success; + } + *macLen = iMacLen; + } + +cleanup: + return retval; +} + +sss_status_t sss_openssl_mac_init(sss_openssl_mac_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; + const EVP_CIPHER *cipher_info = NULL; + int ret; + uint8_t *key; + size_t keylen; + + ENSURE_OR_GO_CLEANUP(context != NULL) + + if (context->keyObject->contents) { + key = context->keyObject->contents; + keylen = context->keyObject->contents_size; + } + else { + LOG_E("KeyObject key not created"); + goto cleanup; + } + + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + if (!(keylen == 16 || keylen == 24 || keylen == 32)) { + LOG_E("key bit not supported"); + goto cleanup; + } + + switch (keylen * 8) { + case 128: + cipher_info = EVP_aes_128_cbc(); + break; + case 192: + cipher_info = EVP_aes_192_cbc(); + break; + case 256: + cipher_info = EVP_aes_256_cbc(); + break; + } + + if (context->cmac_ctx) { + ret = CMAC_Init( + context->cmac_ctx, context->keyObject->contents, context->keyObject->contents_size, cipher_info, NULL); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + } + else { + LOG_W( + "cipher context not allocated call " + "sss_openssl_mac_context_init"); + } + } + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + const EVP_MD *evp_md = NULL; + switch (context->algorithm) { + case kAlgorithm_SSS_HMAC_SHA1: + evp_md = EVP_sha1(); + break; + case kAlgorithm_SSS_HMAC_SHA224: + evp_md = EVP_sha224(); + break; + case kAlgorithm_SSS_HMAC_SHA256: + evp_md = EVP_sha256(); + break; + case kAlgorithm_SSS_HMAC_SHA384: + evp_md = EVP_sha384(); + break; + case kAlgorithm_SSS_HMAC_SHA512: + evp_md = EVP_sha512(); + break; + default: + LOG_E("Invalid HMAC algorithm"); + retval = kStatus_SSS_Fail; + goto cleanup; + } + + ret = HMAC_Init_ex( + context->hmac_ctx, context->keyObject->contents, (int)context->keyObject->contents_size, evp_md, NULL); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + else { + LOG_E( + "cipher context not allocated, call " + "sss_openssl_mac_context_init"); + } + } + +cleanup: + return retval; +} + +sss_status_t sss_openssl_mac_update(sss_openssl_mac_t *context, const uint8_t *message, size_t messageLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret; + if (message == NULL || context == NULL) { + return kStatus_SSS_InvalidArgument; + } + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + CMAC_CTX *ctx; + ctx = context->cmac_ctx; + + ret = CMAC_Update(ctx, message, messageLen); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + } + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + ret = HMAC_Update(context->hmac_ctx, message, messageLen); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + } + else { + //invalid alogortihm + } + return retval; +} + +sss_status_t sss_openssl_mac_finish(sss_openssl_mac_t *context, uint8_t *mac, size_t *macLen) +{ + int ret; + sss_status_t retval = kStatus_SSS_Fail; + if (mac == NULL || macLen == NULL || context == NULL) { + return kStatus_SSS_InvalidArgument; + } + if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + CMAC_CTX *ctx; + ctx = context->cmac_ctx; + + ret = CMAC_Final(ctx, mac, macLen); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + } + else if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + unsigned int iMacLen = (unsigned int)*macLen; + ret = HMAC_Final(context->hmac_ctx, mac, &iMacLen); + if (ret == 1) { + retval = kStatus_SSS_Success; + } + *macLen = iMacLen; + } + else { + //invalid alogortihm + } + return retval; +} + +void sss_openssl_mac_context_free(sss_openssl_mac_t *context) +{ + if (context != NULL) { + //sss_openssl_key_object_free(context->keyObject); + if (context->algorithm == kAlgorithm_SSS_HMAC_SHA1 || context->algorithm == kAlgorithm_SSS_HMAC_SHA224 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA256 || context->algorithm == kAlgorithm_SSS_HMAC_SHA384 || + context->algorithm == kAlgorithm_SSS_HMAC_SHA512) { + if (context->hmac_ctx != NULL) { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + HMAC_CTX_cleanup((HMAC_CTX *)context->hmac_ctx); + +#else + HMAC_CTX_free((HMAC_CTX *)context->hmac_ctx); +#endif + } + } + else if (context->algorithm == kAlgorithm_SSS_CMAC_AES) { + if (context->cmac_ctx != NULL) { + CMAC_CTX_free((CMAC_CTX *)context->cmac_ctx); + } + } + memset(context, 0, sizeof(*context)); + } +} + +/* End: openssl_mac */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_md */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_digest_context_init( + sss_openssl_digest_t *context, sss_openssl_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + + ENSURE_OR_GO_CLEANUP(context); + context->session = session; + context->algorithm = algorithm; + context->mode = mode; + retval = kStatus_SSS_Success; +cleanup: + return retval; +} + +sss_status_t sss_openssl_digest_one_go( + sss_openssl_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + unsigned int iDigestLen = (unsigned int)*digestLen; + + const EVP_MD *md; + + ENSURE_OR_GO_EXIT(context != NULL); + if (messageLen > 0){ + ENSURE_OR_GO_EXIT(message != NULL); + } + + context->mdctx = EVP_MD_CTX_create(); + if (context->mdctx == NULL) { + LOG_E("EVP_MD_CTX_create failed"); + goto exit; + } + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + md = EVP_get_digestbyname("SHA1"); + *digestLen = 20; + break; + case kAlgorithm_SSS_SHA224: + md = EVP_get_digestbyname("SHA224"); + *digestLen = 28; + break; + case kAlgorithm_SSS_SHA256: + md = EVP_get_digestbyname("SHA256"); + *digestLen = 32; + break; + case kAlgorithm_SSS_SHA384: + md = EVP_get_digestbyname("SHA384"); + *digestLen = 48; + break; + case kAlgorithm_SSS_SHA512: + md = EVP_get_digestbyname("SHA512"); + *digestLen = 64; + break; + default: + LOG_E(" Algorithm mode not suported "); + goto exit; + } + + if (md == NULL) { + goto exit; + } + + ret = EVP_DigestInit_ex(context->mdctx, md, NULL); + if (ret != 1) { + LOG_E(" EVP_DigestInit_ex failed "); + goto exit; + } + + ret = EVP_DigestUpdate(context->mdctx, message, messageLen); + if (ret != 1) { + LOG_E(" EVP_DigestUpdate failed "); + goto exit; + } + + ret = EVP_DigestFinal_ex(context->mdctx, digest, &iDigestLen); + if (ret != 1) { + LOG_E(" EVP_DigestFinal_ex failed "); + goto exit; + } + *digestLen = iDigestLen; + + EVP_MD_CTX_destroy(context->mdctx); + context->mdctx = NULL; + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_digest_init(sss_openssl_digest_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; + const EVP_MD *md; + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + + OpenSSL_add_all_algorithms(); + + context->mdctx = EVP_MD_CTX_create(); + if (context->mdctx == NULL) { + LOG_E(" EVP_MD_CTX_create failed "); + goto exit; + } + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + md = EVP_get_digestbyname("SHA1"); + break; + case kAlgorithm_SSS_SHA224: + md = EVP_get_digestbyname("SHA224"); + break; + case kAlgorithm_SSS_SHA256: + md = EVP_get_digestbyname("SHA256"); + break; + case kAlgorithm_SSS_SHA384: + md = EVP_get_digestbyname("SHA384"); + break; + case kAlgorithm_SSS_SHA512: + md = EVP_get_digestbyname("SHA512"); + break; + default: + LOG_E(" Algorithm mode not suported "); + goto exit; + } + + ret = EVP_DigestInit_ex(context->mdctx, md, NULL); + if (ret != 1) { + LOG_E("EVP_DigestInit_ex failed "); + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_digest_update(sss_openssl_digest_t *context, const uint8_t *message, size_t messageLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + if (messageLen > 0){ + ENSURE_OR_GO_EXIT(message != NULL); + } + + ret = EVP_DigestUpdate(context->mdctx, message, messageLen); + if (ret != 1) { + LOG_E("EVP_DigestUpdate failed "); + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_digest_finish(sss_openssl_digest_t *context, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + unsigned int iDigestLen = 0; + + ENSURE_OR_GO_EXIT(context != NULL); + ENSURE_OR_GO_EXIT(digestLen != NULL); + ENSURE_OR_GO_EXIT(digest != NULL); + + iDigestLen = (unsigned int)*digestLen; + + ret = EVP_DigestFinal_ex(context->mdctx, digest, &iDigestLen); + if (ret != 1) { + LOG_E("EVP_DigestFinal_ex failed "); + goto exit; + } + *digestLen = iDigestLen; + + switch (context->algorithm) { + case kAlgorithm_SSS_SHA1: + *digestLen = 20; + break; + case kAlgorithm_SSS_SHA224: + *digestLen = 28; + break; + case kAlgorithm_SSS_SHA256: + *digestLen = 32; + break; + case kAlgorithm_SSS_SHA384: + *digestLen = 48; + break; + case kAlgorithm_SSS_SHA512: + *digestLen = 64; + break; + default: + *digestLen = 0; + LOG_E("Algorithm mode not suported "); + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_openssl_digest_context_free(sss_openssl_digest_t *context) +{ + if (NULL != context->mdctx) { +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + EVP_MD_CTX_cleanup(context->mdctx); +#else + EVP_MD_CTX_destroy(context->mdctx); +#endif + } + memset(context, 0, sizeof(*context)); +} + +/* End: openssl_md */ + +/* ************************************************************************** */ +/* Functions : sss_openssl_rng */ +/* ************************************************************************** */ + +sss_status_t sss_openssl_rng_context_init(sss_openssl_rng_context_t *context, sss_openssl_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Fail; + + ENSURE_OR_GO_CLEANUP(context); + context->session = session; + retval = kStatus_SSS_Success; + +cleanup: + return retval; +} + +sss_status_t sss_openssl_rng_get_random(sss_openssl_rng_context_t *context, uint8_t *random_data, size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + + if (random_data == NULL) { + goto exit; + } + +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + if (0 == RAND_pseudo_bytes((unsigned char *)random_data, (int)dataLen)) { + LOG_E("Error in RAND_pseudo_bytes "); + goto exit; + } +#else + if (0 == RAND_bytes((unsigned char *)random_data, (int)dataLen)) { + LOG_E("Error in RAND_pseudo_bytes "); + goto exit; + } +#endif + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_openssl_rng_context_free(sss_openssl_rng_context_t *context) +{ + sss_status_t retval = kStatus_SSS_Success; + memset(context, 0, sizeof(*context)); + return retval; +} + +/* End: openssl_rng */ + +/* ************************************************************************** */ +/* Functions : Private sss openssl functions */ +/* ************************************************************************** */ +static sss_status_t sss_openssl_generate_ecp_key(sss_openssl_object_t *keyObject, size_t keyBitLen) +{ + sss_status_t retval = kStatus_SSS_Success; + EVP_PKEY *pKey = NULL; + EC_KEY *pEC_Key = NULL; + EC_GROUP *pEC_Group = NULL; + int nid = 0; + int ret = 0; + + /* Initilaize the EC Key. */ + pEC_Key = EC_KEY_new(); + if (pEC_Key == NULL) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to initialize EC_Key"); + goto exit; + } + + if (keyObject->cipherType == kSSS_CipherType_EC_NIST_P) { + switch (keyBitLen) { + case 192: + nid = NID_X9_62_prime192v1; + break; + case 224: + nid = NID_secp224r1; + break; + case 256: + nid = NID_X9_62_prime256v1; + break; + case 384: + nid = NID_secp384r1; + break; + case 521: + nid = NID_secp521r1; + break; + default: + LOG_E("Key type EC_NIST_P not supported with key length 0x%X", keyBitLen); + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (keyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL) { + switch (keyBitLen) { + case 192: + nid = NID_brainpoolP192r1; + break; + case 224: + nid = NID_brainpoolP224r1; + break; + case 320: + nid = NID_brainpoolP320r1; + break; + case 384: + nid = NID_brainpoolP384r1; + break; + case 160: + nid = NID_brainpoolP160r1; + break; + case 256: + nid = NID_brainpoolP256r1; + break; + case 512: + nid = NID_brainpoolP512r1; + break; + default: + LOG_E("Key type EC_BRAINPOOL not supported with key length 0x%X", keyBitLen); + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (keyObject->cipherType == kSSS_CipherType_EC_NIST_K) { + switch (keyBitLen) { + case 160: + nid = NID_secp160k1; + break; + case 192: + nid = NID_secp192k1; + break; + case 224: + nid = NID_secp224k1; + break; + case 256: + nid = NID_secp256k1; + break; + default: + LOG_E("Key type EC_NIST_K not supported with key length 0x%X", keyBitLen); + retval = kStatus_SSS_Fail; + goto exit; + } + } +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + else if (keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + switch (keyBitLen) { + case 256: + nid = NID_X25519; + break; + case 448: + nid = NID_X448; + break; + default: + LOG_E("Key type EC_MONTGOMERY not supported with key length 0x%X", keyBitLen); + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + switch (keyBitLen) { + case 256: + nid = NID_ED25519; + break; + default: + LOG_E("Key type EC_TWISTED_ED not supported with key length 0x%X", keyBitLen); + retval = kStatus_SSS_Fail; + goto exit; + } + } +#endif + else { + LOG_E("sss_openssl_generate_ecp_key: Invalid key type "); + } +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) +#else + if (nid == NID_X448 || nid == NID_X25519 || nid == NID_ED25519) { + EVP_PKEY_CTX *pCtx = EVP_PKEY_CTX_new_id(nid, NULL); + if (1 != EVP_PKEY_keygen_init(pCtx)) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to generate keys."); + } + /* Assign the EC Key to generic Key context. */ + pKey = (EVP_PKEY *)keyObject->contents; + if (1 != EVP_PKEY_keygen(pCtx, &pKey)) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to generate keys."); + } + EVP_PKEY_CTX_free(pCtx); + goto exit; + } +#endif + + if (nid != 0) { + /* Get the Group by curve name. */ + pEC_Group = EC_GROUP_new_by_curve_name(nid); + if (pEC_Group == NULL) { + retval = kStatus_SSS_Fail; + LOG_E("sss_openssl_generate_ecp_key: unable to get the group."); + goto exit; + } + EC_GROUP_set_asn1_flag(pEC_Group, OPENSSL_EC_NAMED_CURVE); + + /* Set the group to ECKey context. */ + if (EC_KEY_set_group(pEC_Key, pEC_Group) == 0) { + retval = kStatus_SSS_Fail; + LOG_E("sss_openssl_generate_ecp_key: unable set the group."); + EC_KEY_free(pEC_Key); + pEC_Key = NULL; + goto exit; + } + + /* Generate the EC keys. */ + ret = EC_KEY_generate_key(pEC_Key); + if (!ret) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to generate keys."); + EC_KEY_free(pEC_Key); + pEC_Key = NULL; + goto exit; + } + + /* Assign the EC Key to generic Key context. */ + pKey = (EVP_PKEY *)keyObject->contents; + if (!EVP_PKEY_set1_EC_KEY(pKey, pEC_Key)) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to assigning ECC key to EVP_PKEY context."); + EC_GROUP_free(pEC_Group); + EC_KEY_free(pEC_Key); + pEC_Key = NULL; + pEC_Group = NULL; + goto exit; + } + } + else { + LOG_E("No support for keyBitLen."); + } + +exit: + if (pEC_Group) + EC_GROUP_free(pEC_Group); + if (pEC_Key) + EC_KEY_free(pEC_Key); + return retval; +} + +#ifdef _MSC_VER +#pragma warning(disable : 4127) +#endif + +static sss_status_t sss_openssl_generate_rsa_key(sss_openssl_object_t *keyObject, size_t keyBitLen) +{ + sss_status_t retval = kStatus_SSS_Success; + EVP_PKEY *pKey = NULL; + RSA *pRSA = NULL; + BIGNUM *pBigNum = NULL; + char *pBuffer = NULL; + unsigned long ulError = 0; + + if (keyBitLen == 512 || keyBitLen == 1024 || keyBitLen == 1152 || keyBitLen == 2048 || keyBitLen == 3072 || + keyBitLen == 4096) { + /* Load the error strings. */ + ERR_load_CRYPTO_strings(); + + pRSA = RSA_new(); + pBigNum = BN_new(); + + if (1 != BN_set_word(pBigNum, RSA_F4)) { + retval = kStatus_SSS_Fail; + LOG_E("sss_openssl_generate_rsa_key: BigNum creation Failed."); + goto exit; + } + + /* Generate the Keys. */ + if (1 != RSA_generate_key_ex(pRSA, (int)keyBitLen, pBigNum, NULL)) { + retval = kStatus_SSS_Fail; + ulError = ERR_get_error(); + pBuffer = (char *)ERR_error_string(ulError, (char *)pBuffer); + LOG_E(" sss_openssl_generate_rsa_key"); +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + ERR_free_strings(); +#endif + BN_free(pBigNum); + goto exit; + } + BN_clear_free(pBigNum); + + /* Assign the EC Key to generic Key context. */ + pKey = (EVP_PKEY *)keyObject->contents; + if (!EVP_PKEY_set1_RSA(pKey, pRSA)) { + retval = kStatus_SSS_Fail; + LOG_E("Unable to assigning RSA key to EVP_PKEY context."); + BN_free(pBigNum); + RSA_free(pRSA); + goto exit; + } + } + else { + LOG_E("No support for keyBitLen."); + retval = kStatus_SSS_Fail; + } + +exit: + RSA_free(pRSA); + return retval; +} + +sss_status_t openssl_convert_to_bio(sss_openssl_object_t *keyObject, char *base64_format, int base64_format_len) +{ + BIO *pBio_Pem = NULL; + EVP_PKEY *pKey = NULL; + char *pem_format = NULL; + char *start = NULL; + char *end = NULL; + sss_status_t ret = kStatus_SSS_Fail; + uint32_t objectType = keyObject->objectType; + + switch (objectType) { + case kSSS_KeyPart_Public: + start = BEGIN_PUBLIC; + end = END_PUBLIC; + break; + case kSSS_KeyPart_Private: + case kSSS_KeyPart_Pair: { + if (keyObject->cipherType == kSSS_CipherType_RSA || keyObject->cipherType == kSSS_CipherType_RSA_CRT) { + start = BEGIN_RSA_PRIVATE; + end = END_RSA_PRIVATE; + break; + } + else if (keyObject->cipherType == kSSS_CipherType_EC_NIST_P || + keyObject->cipherType == kSSS_CipherType_EC_NIST_K || + keyObject->cipherType == kSSS_CipherType_EC_BRAINPOOL || + keyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY || + keyObject->cipherType == kSSS_CipherType_EC_TWISTED_ED) { + start = BEGIN_EC_PRIVATE; + end = END_EC_PRIVATE; + break; + } + else { + goto exit; + } + } + default: + goto exit; + } + + pem_format = (char *)SSS_CALLOC(1, base64_format_len + strlen(start) + strlen(end) + 1); + /* Convert Base64 to PEM format. */ + snprintf(pem_format, + (strlen(base64_format) + strlen(start) + strlen(end) + 1), + "%s" + "%s" + "%s", + start, + base64_format, + end); + + /* Assign the PEM_Format to BIO. */ + pBio_Pem = BIO_new_mem_buf(pem_format, (int)strlen(pem_format)); + if (pBio_Pem == NULL) { + LOG_E("Unable to assign the PEM to BIO buffer."); + goto exit; + } + + if (objectType == kSSS_KeyPart_Public) { + /* Convert the BIO to PKEY format. */ + pKey = PEM_read_bio_PUBKEY(pBio_Pem, NULL, NULL, NULL); + } + else { + pKey = PEM_read_bio_PrivateKey(pBio_Pem, NULL, NULL, NULL); + } + + if (pKey == NULL) { + LOG_E("Unable to read the key from PEM."); + goto exit; + } + + EVP_PKEY_free((EVP_PKEY *)keyObject->contents); + keyObject->contents = pKey; + + ret = kStatus_SSS_Success; +exit: + + BIO_free(pBio_Pem); + pBio_Pem = NULL; + + if (pem_format) + SSS_FREE(pem_format); + + return ret; +} + +static sss_status_t sss_openssl_set_key( + sss_openssl_object_t *keyObject, const uint8_t *keyBuf, size_t keyBufLen, size_t keyBitLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + char *base64_format = NULL; + BIO *pBio_Mem = NULL, *pBio_64 = NULL; + BUF_MEM *pBufMem = NULL; + //EVP_PKEY *pKey = NULL; + sss_status_t ret = kStatus_SSS_Fail; + + if (keyObject->objectType == kSSS_KeyPart_Default) { + if (keyBufLen > keyObject->contents_max_size) { + LOG_E("Not enough memory for key_size."); + goto exit; + } + else { + if (keyBuf != NULL) /* For Empty Certificate */ + memcpy(keyObject->contents, keyBuf, keyBufLen); + keyObject->contents_size = keyBufLen; + } + } + else if ((keyObject->objectType == kSSS_KeyPart_Private) || (keyObject->objectType == kSSS_KeyPart_Public) || + (keyObject->objectType == kSSS_KeyPart_Pair)) { + pBio_64 = BIO_new(BIO_f_base64()); + if (pBio_64 == NULL) { + LOG_E("Unable to initialize Base64 format."); + goto exit; + } + BIO_set_flags(pBio_64, BIO_FLAGS_BASE64_NO_NL); + //BIO_set_close(pBio_64, BIO_NOCLOSE); + + pBio_Mem = BIO_new(BIO_s_mem()); + if (pBio_Mem == NULL) { + LOG_E("Unable to initialize Base64 mem format."); + goto exit; + } + //BIO_set_close(pBio_Mem, BIO_NOCLOSE); + + pBio_64 = BIO_push(pBio_64, pBio_Mem); + + BIO_write(pBio_64, keyBuf, (int)keyBufLen); + if (pBio_64 == NULL) { + LOG_E(" sss_openssl_set_key: key write failure."); + goto exit; + } + + if (BIO_flush(pBio_64) < 1) { + LOG_E("sss_openssl_set_key: flushing failed."); + goto exit; + } + + BIO_get_mem_ptr(pBio_64, &pBufMem); + base64_format = SSS_CALLOC(1, (pBufMem->length) + 1); + memcpy(base64_format, pBufMem->data, pBufMem->length); + base64_format[pBufMem->length] = '\0'; + + ret = openssl_convert_to_bio(keyObject, base64_format, (int)pBufMem->length); + if (ret != kStatus_SSS_Success) { + LOG_E(" sss_openssl_set_key: flushing failed."); + goto exit; + } + } + else { + goto exit; + } + + keyObject->keyBitLen = keyBitLen; + + retval = kStatus_SSS_Success; +exit: + BIO_free(pBio_Mem); + pBio_Mem = NULL; + + BIO_free(pBio_64); + pBio_64 = NULL; + + if (base64_format) + SSS_FREE(base64_format); + + return retval; +} + +static sss_status_t sss_openssl_hkdf_extract(const EVP_MD *md, + const uint8_t *salt, + size_t salt_len, + const uint8_t *ikm, + size_t ikm_len, + uint8_t *prk, + unsigned int *prk_len) +{ + int hash_len; + unsigned char null_salt[EVP_MAX_MD_SIZE] = {'\0'}; + sss_status_t retval = kStatus_SSS_Success; + + hash_len = EVP_MD_size(md); + + if (salt == NULL) { + salt = null_salt; + salt_len = hash_len; + } + + unsigned int iPrkLen = *prk_len; + if (HMAC(md, salt, (int)salt_len, ikm, (int)ikm_len, prk, &iPrkLen) == NULL) { + retval = kStatus_SSS_Fail; + } + *prk_len = iPrkLen; + + return retval; +} + +static sss_status_t sss_openssl_hkdf_expand(const EVP_MD *md, + const uint8_t *prk, + size_t prk_len, + const uint8_t *info, + size_t info_len, + uint8_t *okm, + size_t okm_len) +{ + size_t hash_len; + size_t N; + size_t T_len = 0, where = 0, i; +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + HMAC_CTX hmac; +#else + HMAC_CTX *hmac = NULL; +#endif + unsigned char T[EVP_MAX_MD_SIZE]; + sss_status_t retval = kStatus_SSS_Success; + + if (info_len == 0 || okm_len == 0 || okm == NULL) { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + + hash_len = EVP_MD_size(md); + + if (info == NULL) { + info = (const unsigned char *)""; + } + + N = okm_len / hash_len; + + if ((okm_len % hash_len) != 0) { + N++; + } + + if (N > 255) { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + HMAC_CTX_init(&hmac); +#else + hmac = HMAC_CTX_new(); + if (hmac == NULL) { + retval = kStatus_SSS_Fail; + goto exit; + } +#endif + +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + if (!HMAC_Init_ex(&hmac, prk, (int)prk_len, md, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Section 2.3. */ + for (i = 1; i <= N; i++) { + unsigned char c = (unsigned char)i; + + if (i > 1) { + if (!HMAC_Init_ex(&hmac, NULL, 0, NULL, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Update(&hmac, T, T_len)) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + + if (!HMAC_Update(&hmac, info, info_len)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Update(&hmac, &c, 1)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Final(&hmac, T, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + memcpy(okm + where, T, (i != N) ? hash_len : (okm_len - where)); + where += hash_len; + T_len = hash_len; + } +#else + if (!HMAC_Init_ex(hmac, prk, (int)prk_len, md, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Section 2.3. */ + for (i = 1; i <= N; i++) { + unsigned char c = (unsigned char)i; + + if (i > 1) { + if (!HMAC_Init_ex(hmac, NULL, 0, NULL, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Update(hmac, T, T_len)) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + + if (!HMAC_Update(hmac, info, info_len)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Update(hmac, &c, 1)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + if (!HMAC_Final(hmac, T, NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + memcpy(okm + where, T, (i != N) ? hash_len : (okm_len - where)); + where += hash_len; + T_len = hash_len; + } +#endif + +exit: +#if (OPENSSL_VERSION_NUMBER < 0x10100000L) + HMAC_CTX_cleanup(&hmac); +#else + HMAC_CTX_free(hmac); +#endif + return retval; +} +static sss_status_t sss_openssl_aead_one_go_encrypt(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + int len = 0; + size_t dest_len = 0; + /* Initialise key and IV */ + ret = EVP_EncryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, nonce); + ENSURE_OR_GO_EXIT(ret == 1); + if (aad != NULL) { + /* Add AAD data.*/ + ret = EVP_EncryptUpdate(context->aead_ctx, NULL, &len, aad, aadLen); + ENSURE_OR_GO_EXIT(ret == 1); + } + if (srcData != NULL) { + /* Encrypt plaintext */ + ret = EVP_EncryptUpdate(context->aead_ctx, destData, &len, srcData, size); + ENSURE_OR_GO_EXIT(ret == 1); + dest_len = len; + } + + /* Finalise the encryption */ + ret = EVP_EncryptFinal_ex(context->aead_ctx, tag, &len); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Get the tag */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_GCM_GET_TAG, EVP_CTRL_GCM_GET_TAG, tag); + ENSURE_OR_GO_EXIT(ret == 1); + *tagLen = EVP_CTRL_GCM_GET_TAG; + retval = kStatus_SSS_Success; + +exit: + return retval; +} + +static sss_status_t sss_openssl_aead_one_go_decrypt(sss_openssl_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + int ret = 0; + int len = 0; + + /* Initialise key and IV */ + ret = EVP_DecryptInit_ex(context->aead_ctx, NULL, NULL, context->keyObject->contents, nonce); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Specify any AAD */ + if (aad != NULL) { + ret = EVP_DecryptUpdate(context->aead_ctx, NULL, &len, aad, aadLen); + ENSURE_OR_GO_EXIT(ret == 1); + } + + /* Decrypt ciphertext */ + if (srcData != NULL) { + ret = EVP_DecryptUpdate(context->aead_ctx, destData, &len, srcData, size); + ENSURE_OR_GO_EXIT(ret == 1); + } + + /* Set tag value. */ + ret = EVP_CIPHER_CTX_ctrl(context->aead_ctx, EVP_CTRL_CCM_SET_TAG, 16, tag); + ENSURE_OR_GO_EXIT(ret == 1); + + /* Finalise decrypt */ + ret = EVP_DecryptFinal_ex(context->aead_ctx, destData, &len); + ENSURE_OR_GO_EXIT(ret == 1); + retval = kStatus_SSS_Success; + +exit: + return retval; +} + +#endif /* SSS_HAVE_OPENSSL */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c new file mode 100644 index 00000000000..7613140051a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c @@ -0,0 +1,7074 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if SSS_HAVE_APPLET_SE05X_IOT +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "nxEnsure.h" +#include "nxScp03_Apis.h" +#include "se05x_APDU.h" +#include "se05x_tlv.h" +#include "smCom.h" +#if defined(SMCOM_JRCP_V1_AM) +#include "sm_timer.h" +#endif + +#if (USE_RTOS) +#define LOCK_TXN(lock) \ + LOG_D("Trying to Acquire Lock"); \ + if (xSemaphoreTake(lock, portMAX_DELAY) == pdTRUE) { \ + LOG_D("LOCK Acquired"); \ + } \ + else { \ + LOG_D("LOCK Acquisition failed"); \ + } +#define UNLOCK_TXN(lock) \ + LOG_D("Trying to Released Lock"); \ + if (xSemaphoreGive(lock) == pdTRUE) { \ + LOG_D("LOCK Released"); \ + } \ + else { \ + LOG_D("LOCK Releasing failed"); \ + } +#elif (__GNUC__ && !AX_EMBEDDED) +#define LOCK_TXN(lock) \ + LOG_D("Trying to Acquire Lock thread: %ld", pthread_self()); \ + pthread_mutex_lock(&lock); \ + LOG_D("LOCK Acquired by thread: %ld", pthread_self()); + +#define UNLOCK_TXN(lock) \ + LOG_D("Trying to Released Lock by thread: %ld", pthread_self()); \ + pthread_mutex_unlock(&lock); \ + LOG_D("LOCK Released by thread: %ld", pthread_self()); +#endif + +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#define USE_LOCK 1 +#else +#define USE_LOCK 0 +#endif + +static SE05x_ECSignatureAlgo_t se05x_get_ec_sign_hash_mode(sss_algorithm_t algorithm); + +/* Used during testing as well */ +void get_ecc_raw_data(uint8_t *key, size_t keylen, uint8_t **key_buf, size_t *key_buflen, uint32_t curve_id); + +#if SSSFTR_SE05X_AuthSession +static smStatus_t se05x_CreateVerifyUserIDSession( + pSe05xSession_t se05xSession, const uint32_t auth_id, SE05x_AuthCtx_ID_t *pin, pSe05xPolicy_t policy); +#endif + +#if SSS_HAVE_SCP_SCP03_SSS +#if SSSFTR_SE05X_AuthECKey +static smStatus_t se05x_CreateECKeySession( + pSe05xSession_t se05xSession, const uint32_t auth_id, SE05x_AuthCtx_ECKey_t *pFScpCtx); +#endif + +#if SSSFTR_SE05X_AuthSession +static smStatus_t se05x_CreateVerifyAESKeySession( + pSe05xSession_t se05xSession, const uint32_t auth_id, NXSCP03_AuthCtx_t *pAppletSCPCtx); +#endif +#endif + +static smStatus_t sss_se05x_channel_txnRaw(void *conn_ctx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle); +#if 0 +static SE05x_RSASignatureAlgo_t se05x_get_rsa_sign_mode( + sss_algorithm_t algorithm); +#endif + +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA +static SE05x_RSAEncryptionAlgo_t se05x_get_rsa_encrypt_mode(sss_algorithm_t algorithm); +static SE05x_RSASignatureAlgo_t se05x_get_rsa_sign_hash_mode(sss_algorithm_t algorithm); +#endif +static SE05x_CipherMode_t se05x_get_cipher_mode(sss_algorithm_t algorithm); +static SE05x_MACAlgo_t se05x_get_mac_algo(sss_algorithm_t algorithm); +#if SSSFTR_SE05X_KEY_SET || SSSFTR_SE05X_KEY_GET +static uint8_t CheckIfKeyIdExists(uint32_t keyId, pSe05xSession_t session_ctx); +#endif +static smStatus_t sss_se05x_channel_txn(void *conn_ctx, + struct _sss_se05x_tunnel_context *pChannelCtx, + SE_AuthType_t currAuth, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle); + +static smStatus_t sss_se05x_TXn(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle); + +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession +static sss_status_t sss_session_auth_open(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t auth_id, + sss_connection_type_t connection_type, + void *connectionData); +#endif + +#if SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA +static sss_status_t sss_se05x_key_store_set_rsa_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len); +#endif + +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA +static sss_status_t se05x_check_input_len(size_t inLen, sss_algorithm_t algorithm); +#endif + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +static sss_status_t sss_se05x_aead_CCMfinish(sss_se05x_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen); +#endif + +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +static smStatus_t sss_se05x_LL_set_ec_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + SE05x_Result_t obj_exists); + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +typedef smStatus_t (*fp_Ec_KeyWrite_t)(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + uint32_t version); +#endif //SSS_HAVE_SE05X_VER_GTE_06_00 +#endif //SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_KEY_SET +static smStatus_t sss_se05x_LL_set_symm_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + SE05x_Result_t obj_exists); + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +typedef smStatus_t (*fp_Symm_KeyWrite_t)(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + uint32_t version); +#endif //SSS_HAVE_SE05X_VER_GTE_06_00 +#endif //SSSFTR_SE05X_AES && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA +static smStatus_t sss_se05x_LL_set_RSA_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + SE05x_Result_t obj_exists); + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +typedef smStatus_t (*fp_RSA_KeyWrite_t)(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + uint32_t version); +#endif //SSS_HAVE_SE05X_VER_GTE_06_00 +#endif //SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_session */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_session_create(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_Success; + /* Nothing special to be handled */ + return retval; +} + +#define HEX_EXPECTED_APPLET_VERSION \ + (0 | (APPLET_SE050_VER_MAJOR) << (8 * 3) | (APPLET_SE050_VER_MINOR) << (8 * 2) | (APPLET_SE050_VER_DEV) << (8 * 1)) + +#if defined(APPLET_SE050_VER_DEV_PATCH1) +#define HEX_EXPECTED_APPLET_VERSION_PATCH1 \ + (0 | (APPLET_SE050_VER_MAJOR) << (8 * 3) | (APPLET_SE050_VER_MINOR) << (8 * 2) | \ + (APPLET_SE050_VER_DEV_PATCH1) << (8 * 1)) +#endif + +sss_status_t sss_se05x_session_open(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t application_id, + sss_connection_type_t connection_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_InvalidArgument; + SE05x_Connect_Ctx_t *pAuthCtx = NULL; + SmCommState_t CommState = {0}; + smStatus_t status = SM_NOT_OK; + U16 lReturn; + pSe05xSession_t se05xSession; +#if defined(SMCOM_JRCP_V1_AM) + int session_open_retry_cnt = 1; + int session_open_retry_dly = 1; //seconds + int session_open_retry_cnt_max = 50; + int session_open_retry_dly_max = 10; //seconds +#endif + + ENSURE_OR_GO_EXIT(session); + se05xSession = &session->s_ctx; + + memset(session, 0, sizeof(*session)); + + ENSURE_OR_GO_EXIT(connectionData); + pAuthCtx = (SE05x_Connect_Ctx_t *)connectionData; + + if (pAuthCtx->connType != kType_SE_Conn_Type_Channel) { + uint8_t atr[100]; + uint16_t atrLen = ARRAY_SIZE(atr); + CommState.connType = pAuthCtx->connType; + if (1 == pAuthCtx->skip_select_applet) { + if (pAuthCtx->auth.authType == kSSS_AuthType_None) { + CommState.select = SELECT_NONE; + } + else if (pAuthCtx->auth.authType == kSSS_AuthType_SCP03) { + CommState.select = SELECT_SSD; + } + } +#if defined(SMCOM_JRCP_V1) || defined(SMCOM_JRCP_V2) || defined(RJCT_VCOM) || defined(SMCOM_PCSC) || \ + defined(SMCOM_RC663_VCOM) + lReturn = SM_RjctConnect(&(se05xSession->conn_ctx), pAuthCtx->portName, &CommState, atr, &atrLen); + + if (lReturn != SW_OK) { + LOG_E("SM_RjctConnect Failed. Status %04X", lReturn); + goto exit; + } + if (atrLen != 0) { + LOG_AU8_I(atr, atrLen); + } +#else + /* AX_EMBEDDED Or Native */ + lReturn = SM_I2CConnect(&(se05xSession->conn_ctx), &CommState, atr, &atrLen, pAuthCtx->portName); + if (lReturn != SW_OK) { + LOG_E("SM_Connect Failed. Status %04X", lReturn); + retval = kStatus_SSS_Fail; + return retval; + } + if (atrLen != 0) { + LOG_AU8_I(atr, atrLen); + } +#endif + if (1 == pAuthCtx->skip_select_applet) { + status = (smStatus_t)lReturn; + /* Not selecting the applet, so we don't know whether it's old or new */ + } + else { + if (HEX_EXPECTED_APPLET_VERSION == (0xFFFFFF00 & CommState.appletVersion)) { + /* Fine */ + } +#if defined(HEX_EXPECTED_APPLET_VERSION_PATCH1) + else if (HEX_EXPECTED_APPLET_VERSION_PATCH1 == (0xFFFFFF00 & CommState.appletVersion)) { + /* Fine */ + } +#endif + else if ((0xFFFFFF00 & CommState.appletVersion) < HEX_EXPECTED_APPLET_VERSION) { + LOG_E("Mismatch Applet version."); + LOG_E("Compiled for 0x%X. Got older 0x%X", + (HEX_EXPECTED_APPLET_VERSION) >> 8, + (CommState.appletVersion) >> 8); + LOG_E("Aborting!!!"); + SM_Close(se05xSession->conn_ctx, 0); + return kStatus_SSS_Fail; + } + else { + LOG_I("Newer version of Applet Found"); + LOG_I("Compiled for 0x%X. Got newer 0x%X", + (HEX_EXPECTED_APPLET_VERSION) >> 8, + (CommState.appletVersion) >> 8); + } + } + } + + if (pAuthCtx->auth.authType == kSSS_AuthType_ECKey) { + if (CommState.appletVersion == 0) { + /*Get Applet version from previously opened session*/ + uint8_t appletVersion[32] = {0}; + uint8_t versionIterator = 0; + size_t appletVersionLen = sizeof(appletVersion); + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)pAuthCtx->tunnelCtx->session; + status = Se05x_API_GetVersion(&se05x_session->s_ctx, appletVersion, &appletVersionLen); + if (status != SM_OK) { + LOG_E("Unable to retrive applet version"); + retval = kStatus_SSS_Fail; + goto exit; + } + for (versionIterator = 0; versionIterator < 3; versionIterator++) { + CommState.appletVersion = CommState.appletVersion << 8 | appletVersion[versionIterator]; + } + CommState.appletVersion = CommState.appletVersion << 8; + } + if (CommState.appletVersion >= 0x03050000) { + pAuthCtx->auth.ctx.eckey.pDyn_ctx->authType = kSSS_AuthType_INT_ECKey_Counter; + } + else { + pAuthCtx->auth.ctx.eckey.pDyn_ctx->authType = kSSS_AuthType_ECKey; + } + } + + se05xSession->fp_TXn = &sss_se05x_TXn; + se05xSession->fp_RawTXn = &sss_se05x_channel_txn; + + /* Auth type is None */ + if (1 == pAuthCtx->skip_select_applet) { + /* Not selecting the applet */ + } + else { + if ((pAuthCtx->auth.authType == kSSS_AuthType_None) && (connection_type == kSSS_ConnectionType_Plain)) { + LOG_W("Communication channel is Plain."); + LOG_W("!!!Not recommended for production use.!!!"); + se05xSession->fp_Transform = &se05x_Transform; + se05xSession->fp_DeCrypt = &se05x_DeCrypt; + se05xSession->authType = kSSS_AuthType_None; + status = SM_OK; + } + } + +#if SSS_HAVE_SCP_SCP03_SSS + /* Auth type is Platform SCP03 */ + if ((pAuthCtx->auth.authType == kSSS_AuthType_SCP03) && (connection_type == kSSS_ConnectionType_Encrypted)) { + se05xSession->fp_Transform = &se05x_Transform; + se05xSession->fp_DeCrypt = &se05x_DeCrypt; + se05xSession->authType = kSSS_AuthType_SCP03; + retval = nxScp03_AuthenticateChannel(se05xSession, &pAuthCtx->auth.ctx.scp03); + if (retval == kStatus_SSS_Success) { + /* There is a differnet behaviour of Platform SCP between SE050 and future applet. + * Here we switch make it clear. */ + if (CommState.appletVersion >= 0x04030000) { + pAuthCtx->auth.ctx.scp03.pDyn_ctx->authType = (uint8_t)kSSS_AuthType_AESKey; + } + else { + pAuthCtx->auth.ctx.scp03.pDyn_ctx->authType = (uint8_t)kSSS_AuthType_SCP03; + } + /*Auth type to Platform SCP03 again as channel authentication will modify it + to auth type None*/ + se05xSession->authType = kSSS_AuthType_SCP03; + se05xSession->pdynScp03Ctx = pAuthCtx->auth.ctx.scp03.pDyn_ctx; + status = SM_OK; + se05xSession->fp_Transform = &se05x_Transform_scp; + } + else { + LOG_E("Could not set SCP03 Secure Channel"); + } + } +#else + if (pAuthCtx->auth.authType != kSSS_AuthType_None && pAuthCtx->auth.authType != kSSS_AuthType_ID) { + LOG_E( + "Set the SCP to SCP03_SSS in the build configuration and " + "recompile.!"); + } + +#endif + +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession + if (pAuthCtx->connType == kType_SE_Conn_Type_Channel) { + se05xSession->pChannelCtx = (struct _sss_se05x_tunnel_context *)pAuthCtx->tunnelCtx; + } + + if ((application_id != 0) && + ((connection_type == kSSS_ConnectionType_Password) || (connection_type == kSSS_ConnectionType_Encrypted))) { + +#if defined(SMCOM_JRCP_V1_AM) + { + // Overwrite session_open_retry_cnt and session_open_retry_dly from env variables + const char *retry_cnt = NULL; + const char *retry_dly = NULL; + + retry_cnt = getenv("EX_SSS_SESSION_OPEN_RETRY_CNT"); + if (retry_cnt != NULL) { + session_open_retry_cnt = atoi(retry_cnt); + if (session_open_retry_cnt > session_open_retry_cnt_max) { + session_open_retry_cnt = session_open_retry_cnt_max; + } + LOG_I("Session Open Retry Count ='%d' ", session_open_retry_cnt); + } + + retry_dly = getenv("EX_SSS_SESSION_OPEN_RETRY_DLY"); + if (retry_dly != NULL) { + session_open_retry_dly = atoi(retry_dly); + if (session_open_retry_dly < 1) { + session_open_retry_dly = 1; + } + if (session_open_retry_dly > session_open_retry_dly_max) { + session_open_retry_dly = session_open_retry_dly_max; + } + LOG_I("Session Open Retry Delay ='%d' ", session_open_retry_dly); + } + } + + do { + if (session_open_retry_cnt > 0) { + session_open_retry_cnt--; + } + SM_LOCK_CHANNEL(); + retval = sss_session_auth_open(session, subsystem, application_id, connection_type, connectionData); + SM_UNLOCK_CHANNEL(); + if (retval == kStatus_SSS_Success) { + break; + } + + sm_sleep(session_open_retry_dly * 1000); + + } while (session_open_retry_cnt > 0); +#else + SM_LOCK_CHANNEL(); + retval = sss_session_auth_open(session, subsystem, application_id, connection_type, connectionData); + SM_UNLOCK_CHANNEL(); +#endif + + + if (retval == kStatus_SSS_Success) { + status = SM_OK; + } + else { + /* Check if this is not tunnel session to avoid multiple close */ + if (pAuthCtx->connType != kType_SE_Conn_Type_Channel) { + SM_Close(se05xSession->conn_ctx, 0); + } + status = SM_NOT_OK; + } + } +#endif + + if (status == SM_OK) { + session->subsystem = subsystem; + retval = kStatus_SSS_Success; + } + else { + memset(session, 0x00, sizeof(*session)); + retval = kStatus_SSS_Fail; + } +exit: + return retval; +} + +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession +static sss_status_t sss_session_auth_open(sss_se05x_session_t *session, + sss_type_t subsystem, + uint32_t auth_id, + sss_connection_type_t connect_type, + void *connectionData) +{ + sss_status_t retval = kStatus_SSS_Fail; + void *conn_ctx = session->s_ctx.conn_ctx; + memset(session, 0, sizeof(*session)); + SE05x_Connect_Ctx_t *pAuthCtx; + smStatus_t status = SM_NOT_OK; +#if SSSFTR_SE05X_AuthSession + Se05xPolicy_t se05x_policy; + uint8_t *ppolicySet; + uint8_t session_policies_buff[MAX_POLICY_BUFFER_SIZE]; + size_t valid_policy_buff_len = 0; +#endif + retval = kStatus_SSS_Fail; + pSe05xSession_t se05xSession = &session->s_ctx; + + /* Restore connection context */ + se05xSession->conn_ctx = conn_ctx; + + ENSURE_OR_GO_EXIT(connectionData != NULL); + pAuthCtx = (SE05x_Connect_Ctx_t *)connectionData; + + if ((pAuthCtx->auth.authType == kSSS_AuthType_ID) && (connect_type != kSSS_ConnectionType_Password)) { + LOG_D("ERROR: Need both AUTHType=ID and ConnType=Password"); + goto exit; + } + if (((pAuthCtx->auth.authType == kSSS_AuthType_AESKey) || (pAuthCtx->auth.authType == kSSS_AuthType_ECKey)) && + (connect_type != kSSS_ConnectionType_Encrypted)) { + LOG_D("ERROR: Need both AUTHType={AESKey||ECKey} and ConnType=Encrypted"); + goto exit; + } + + se05xSession->fp_TXn = &sss_se05x_TXn; + se05xSession->fp_RawTXn = &sss_se05x_channel_txn; + if (pAuthCtx->connType == kType_SE_Conn_Type_Channel) { + se05xSession->pChannelCtx = (struct _sss_se05x_tunnel_context *)pAuthCtx->tunnelCtx; + } + +#if SSSFTR_SE05X_AuthSession + /*Session Policy check*/ + if (pAuthCtx->session_policy) { + if (kStatus_SSS_Success != sss_se05x_create_session_policy_buffer( + pAuthCtx->session_policy, &session_policies_buff[0], &valid_policy_buff_len)) { + goto exit; + } + ppolicySet = session_policies_buff; + } + else { + ppolicySet = NULL; + } + + se05x_policy.value = (uint8_t *)ppolicySet; + se05x_policy.value_len = valid_policy_buff_len; +#endif + + /* Auth type is Platform UserID */ + + if (pAuthCtx->auth.authType == kSSS_AuthType_ID) +#if SSSFTR_SE05X_AuthSession + { + LOG_W("Communication channel is with UserID (But Plain)."); + LOG_W("!!!Not recommended for production use.!!!"); + se05xSession->fp_Transform = &se05x_Transform; + se05xSession->fp_DeCrypt = &se05x_DeCrypt; + + status = se05x_CreateVerifyUserIDSession(se05xSession, auth_id, &pAuthCtx->auth.ctx.idobj, &se05x_policy); + if (status != SM_OK) { + se05xSession->hasSession = 1; + se05xSession->authType = kSSS_AuthType_ID; + } + } +#else + LOG_W("User Id Support compiled out"); + status = SM_NOT_OK; +#endif + +#if SSS_HAVE_SCP_SCP03_SSS + /* Auth type is ECKey */ + if ((pAuthCtx->auth.authType == kSSS_AuthType_ECKey) && (auth_id != 0)) { +#if SSSFTR_SE05X_AuthECKey && SSSFTR_SE05X_AuthSession + se05xSession->fp_Transform = &se05x_Transform; + se05xSession->fp_DeCrypt = &se05x_DeCrypt; + status = se05x_CreateECKeySession(se05xSession, auth_id, &pAuthCtx->auth.ctx.eckey); + if (status == SM_OK) { + se05xSession->fp_Transform = &se05x_Transform_scp; + if (se05x_policy.value_len > 0) { + status = Se05x_API_ExchangeSessionData(se05xSession, &se05x_policy); + } + } +#else + LOG_W("ECKey Support compiled out"); + status = SM_NOT_OK; +#endif + } + /* Auth type is Applet SCP03 */ + if ((pAuthCtx->auth.authType == kSSS_AuthType_AESKey) && (auth_id != 0)) { +#if SSSFTR_SE05X_AuthSession + se05xSession->fp_Transform = &se05x_Transform; + se05xSession->fp_DeCrypt = &se05x_DeCrypt; + status = se05x_CreateVerifyAESKeySession(se05xSession, auth_id, &pAuthCtx->auth.ctx.scp03); + if (status == SM_OK) { + se05xSession->fp_Transform = &se05x_Transform_scp; + if (se05x_policy.value_len > 0) { + status = SM_NOT_OK; + status = Se05x_API_ExchangeSessionData(se05xSession, &se05x_policy); + } + } +#else + LOG_W("AppletSCP Support compiled out"); + status = SM_NOT_OK; +#endif + } + +#endif + + if (status == SM_OK) { + session->subsystem = subsystem; + retval = kStatus_SSS_Success; + } + else { + memset(session, 0x00, sizeof(*session)); + retval = kStatus_SSS_Fail; + } + /* Restore connection context */ + session->s_ctx.conn_ctx = conn_ctx; + +exit: + return retval; +} + +#endif + +sss_status_t sss_se05x_refresh_session(sss_se05x_session_t *session, void *connectionData) +{ + sss_status_t retval = kStatus_SSS_Fail; + pSe05xSession_t se05xSession = &session->s_ctx; + sss_policy_session_u *session_policy = (sss_policy_session_u *)connectionData; + smStatus_t status = SM_NOT_OK; + size_t valid_policy_buff_len = 0; + Se05xPolicy_t se05x_policy = {0}; + uint8_t *ppolicySet; + uint8_t session_policies_buff[MAX_POLICY_BUFFER_SIZE]; + + if (session_policy) { + if (kStatus_SSS_Success != + sss_se05x_create_session_policy_buffer(session_policy, &session_policies_buff[0], &valid_policy_buff_len)) { + goto exit; + } + ppolicySet = session_policies_buff; + se05x_policy.value = (uint8_t *)ppolicySet; + se05x_policy.value_len = valid_policy_buff_len; + } + else { + ppolicySet = NULL; + se05x_policy.value = NULL; + se05x_policy.value_len = 0; + } + + status = Se05x_API_RefreshSession(se05xSession, &se05x_policy); + if (status == SM_OK) { + retval = kStatus_SSS_Success; + } +exit: + return retval; +} + +sss_status_t sss_se05x_session_prop_get_u32(sss_se05x_session_t *session, uint32_t property, uint32_t *pValue) +{ + sss_status_t retval = kStatus_SSS_Success; + sss_session_prop_u32_t prop = (sss_session_prop_u32_t)property; + sss_s05x_sesion_prop_u32_t se050xprop = (sss_s05x_sesion_prop_u32_t)property; + + if (pValue == NULL) { + retval = kStatus_SSS_Fail; + goto cleanup; + } + + switch (prop) { + case kSSS_SessionProp_VerMaj: + *pValue = PLUGANDTRUST_HOSTLIB_VER_MAJOR; + break; + case kSSS_SessionProp_VerMin: + *pValue = PLUGANDTRUST_HOSTLIB_VER_MINOR; + break; + case kSSS_SessionProp_VerDev: + *pValue = PLUGANDTRUST_HOSTLIB_VER_DEV; + break; + case kSSS_SessionProp_UIDLen: + *pValue = 18; + break; + default: + *pValue = 0; + retval = kStatus_SSS_Fail; + } + + if (retval == kStatus_SSS_Success) + goto cleanup; + + switch (se050xprop) { + case kSSS_SE05x_SessionProp_CertUIDLen: { + *pValue = 10; + retval = kStatus_SSS_Success; + } break; + default: { + *pValue = 0; + retval = kStatus_SSS_Fail; + } + } + +cleanup: + return retval; +} + +sss_status_t sss_se05x_session_prop_get_au8( + sss_se05x_session_t *session, uint32_t property, uint8_t *pValue, size_t *pValueLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_session_prop_au8_t prop = (sss_session_prop_au8_t) property; + sss_s05x_sesion_prop_au8_t se050xprop = (sss_s05x_sesion_prop_au8_t)property; + smStatus_t sm_status = SM_NOT_OK; + + if (pValue == NULL || pValueLen == NULL) { + goto cleanup; + } + + switch (prop) { + case kSSS_SessionProp_UID: + if (*pValueLen >= 18) { + sm_status = Se05x_API_ReadObject(&session->s_ctx, kSE05x_AppletResID_UNIQUE_ID, 0, 18, pValue, pValueLen); + } + else { + LOG_D("Buffer too short"); + } + break; + default:; + } + + if (sm_status == SM_OK) + goto cleanup; + + switch (se050xprop) { + case kSSS_SE05x_SessionProp_CertUID: + if (*pValueLen >= 10) { + uint8_t uid18[SE050_MODULE_UNIQUE_ID_LEN]; + size_t uid18Len = sizeof(uid18); + + sm_status = Se05x_API_ReadObject( + &session->s_ctx, kSE05x_AppletResID_UNIQUE_ID, 0, (uint16_t)uid18Len, uid18, &uid18Len); + if (sm_status == SM_OK) { + int idx = 0; +#define A71CH_UID_IC_TYPE_OFFSET 2 +#define A71CH_UID_IC_FABRICATION_DATA_OFFSET 8 +#define A71CH_UID_IC_SERIAL_NR_OFFSET 10 +#define A71CH_UID_IC_BATCH_ID_OFFSET 13 + pValue[idx++] = uid18[A71CH_UID_IC_TYPE_OFFSET]; + pValue[idx++] = uid18[A71CH_UID_IC_TYPE_OFFSET + 1]; + pValue[idx++] = uid18[A71CH_UID_IC_FABRICATION_DATA_OFFSET]; + pValue[idx++] = uid18[A71CH_UID_IC_FABRICATION_DATA_OFFSET + 1]; + pValue[idx++] = uid18[A71CH_UID_IC_SERIAL_NR_OFFSET]; + pValue[idx++] = uid18[A71CH_UID_IC_SERIAL_NR_OFFSET + 1]; + pValue[idx++] = uid18[A71CH_UID_IC_SERIAL_NR_OFFSET + 2]; + pValue[idx++] = uid18[A71CH_UID_IC_BATCH_ID_OFFSET]; + pValue[idx++] = uid18[A71CH_UID_IC_BATCH_ID_OFFSET + 1]; + pValue[idx++] = uid18[A71CH_UID_IC_BATCH_ID_OFFSET + 2]; + *pValueLen = 10; + } + } + break; + } + +cleanup: + if (sm_status == SM_OK) + retval = kStatus_SSS_Success; + return retval; +} + +void sss_se05x_session_close(sss_se05x_session_t *session) +{ + Se05x_API_CloseSession(&session->s_ctx); + if (session->s_ctx.pChannelCtx == NULL) { + SM_Close(session->s_ctx.conn_ctx, 0); + } + memset(session, 0, sizeof(*session)); +} + +void sss_se05x_session_delete(sss_se05x_session_t *session) +{ + ; +} + +/* End: se05x_session */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_keyobj */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_key_object_init(sss_se05x_object_t *keyObject, sss_se05x_key_store_t *keyStore) +{ + sss_status_t retval = kStatus_SSS_Success; + memset(keyObject, 0, sizeof(*keyObject)); + keyObject->keyStore = keyStore; + + return retval; +} + +sss_status_t sss_se05x_key_object_allocate_handle(sss_se05x_object_t *keyObject, + uint32_t keyId, + sss_key_part_t keyPart, + sss_cipher_type_t cipherType, + size_t keyByteLenMax, + uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Success; + smStatus_t status; + SE05x_Result_t exists = kSE05x_Result_NA; + keyObject->objectType = keyPart; + keyObject->cipherType = cipherType; + keyObject->keyId = keyId; + if (options == kKeyObject_Mode_Persistent) + keyObject->isPersistant = 1; + + status = Se05x_API_CheckObjectExists(&keyObject->keyStore->session->s_ctx, keyId, &exists); + if (status == SM_OK) { + if (exists == kSE05x_Result_SUCCESS) { + LOG_W("Object id 0x%X exists", keyId); + } + } + else { + LOG_E("Couldn't check if object id 0x%X exists", keyId); + return kStatus_SSS_Fail; + } + + return retval; +} + +//static sss_status_t sss_se05x_key_object_get_handle_binary( +// sss_se05x_object_t *keyObject) { +// sss_status_t retval = kStatus_SSS_Success; +// keyObject->objectType = kSSS_KeyPart_Default; +// keyObject->cipherType = kSSS_CipherType_Binary; +// return retval; +//} +sss_status_t sss_se05x_key_object_get_handle(sss_se05x_object_t *keyObject, uint32_t keyId) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SE05X_KEY_GET + SE05x_SecObjTyp_t retObjectType; + uint8_t retTransientType; + SE05x_ECCurve_t retCurveId; + const SE05x_AttestationType_t attestationType = kSE05x_AttestationType_None; + smStatus_t apiRetval; + + if (0 == CheckIfKeyIdExists(keyId, &keyObject->keyStore->session->s_ctx)) { + /* Object does not exist */ + LOG_D("keyId does not exist"); + LOG_U32_D(keyId); + return retval; + } + + apiRetval = Se05x_API_ReadType( + &keyObject->keyStore->session->s_ctx, keyId, &retObjectType, &retTransientType, attestationType); + if (apiRetval == SM_OK) { + keyObject->isPersistant = retTransientType; + if (retObjectType >= kSE05x_SecObjTyp_EC_KEY_PAIR && retObjectType <= kSE05x_SecObjTyp_EC_PUB_KEY) { + apiRetval = Se05x_API_EC_CurveGetId(&keyObject->keyStore->session->s_ctx, keyId, &retCurveId); + if (apiRetval == SM_OK) { + keyObject->curve_id = retCurveId; + if ((retCurveId == kSE05x_ECCurve_NIST_P256) +#if SSS_HAVE_EC_NIST_192 + || (retCurveId == kSE05x_ECCurve_NIST_P192) +#endif +#if SSS_HAVE_EC_NIST_224 + || (retCurveId == kSE05x_ECCurve_NIST_P224) +#endif +#if SSS_HAVE_EC_NIST_521 + || (retCurveId == kSE05x_ECCurve_NIST_P521) +#endif + || (retCurveId == kSE05x_ECCurve_NIST_P384)) { + keyObject->cipherType = kSSS_CipherType_EC_NIST_P; + } +#if SSS_HAVE_EC_BP + else if ((retCurveId >= kSE05x_ECCurve_Brainpool160) && (retCurveId <= kSE05x_ECCurve_Brainpool512)) { + keyObject->cipherType = kSSS_CipherType_EC_BRAINPOOL; + } +#endif +#if SSS_HAVE_EC_NIST_K + else if ((retCurveId >= kSE05x_ECCurve_Secp160k1) && (retCurveId <= kSE05x_ECCurve_Secp256k1)) { + keyObject->cipherType = kSSS_CipherType_EC_NIST_K; + } +#endif +#if SSS_HAVE_EC_ED + else if (retCurveId == kSE05x_ECCurve_RESERVED_ID_ECC_ED_25519) { + keyObject->cipherType = kSSS_CipherType_EC_TWISTED_ED; + } +#endif +#if SSS_HAVE_EC_MONT + else if (retCurveId == kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_25519) { + keyObject->cipherType = kSSS_CipherType_EC_MONTGOMERY; + } +#endif +#if SSS_HAVE_TPM_BN + else if (retCurveId == kSE05x_ECCurve_TPM_ECC_BN_P256) { + keyObject->cipherType = kSSS_CipherType_EC_BARRETO_NAEHRIG; + } +#endif +#if SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT + else if (retCurveId == kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448) { + keyObject->cipherType = kSSS_CipherType_EC_MONTGOMERY; + } +#endif + else { + keyObject->cipherType = kSSS_CipherType_NONE; + return retval; + } + } + else { + LOG_E("error in Se05x_API_GetECCurveId"); + return retval; + } + } +#if SSSFTR_RSA && SSS_HAVE_RSA + else if (retObjectType == kSE05x_SecObjTyp_RSA_KEY_PAIR_CRT) { + keyObject->cipherType = kSSS_CipherType_RSA_CRT; + } + else if (retObjectType == kSE05x_SecObjTyp_RSA_PRIV_KEY_CRT) { + keyObject->cipherType = kSSS_CipherType_RSA_CRT; + } + else if (retObjectType >= kSE05x_SecObjTyp_RSA_KEY_PAIR && retObjectType <= kSE05x_SecObjTyp_RSA_PUB_KEY) { + keyObject->cipherType = kSSS_CipherType_RSA; + } +#endif + else if (retObjectType == kSE05x_SecObjTyp_AES_KEY) { + keyObject->cipherType = kSSS_CipherType_AES; + } + else if (retObjectType == kSE05x_SecObjTyp_DES_KEY) { + keyObject->cipherType = kSSS_CipherType_DES; + } + else if (retObjectType == kSE05x_SecObjTyp_BINARY_FILE) { + keyObject->cipherType = kSSS_CipherType_Binary; + } + else if (retObjectType == kSE05x_SecObjTyp_UserID) { + keyObject->cipherType = kSSS_CipherType_UserID; + } + else if (retObjectType == kSE05x_SecObjTyp_COUNTER) { + keyObject->cipherType = kSSS_CipherType_Count; + } + else if (retObjectType == kSE05x_SecObjTyp_PCR) { + keyObject->cipherType = kSSS_CipherType_PCR; + } + else if (retObjectType == kSE05x_SecObjTyp_HMAC_KEY) { + keyObject->cipherType = kSSS_CipherType_HMAC; + } + else { + keyObject->cipherType = kSSS_CipherType_NONE; + } + + switch (retObjectType) { + case kSE05x_SecObjTyp_EC_KEY_PAIR: +#if SSS_HAVE_RSA + case kSE05x_SecObjTyp_RSA_KEY_PAIR: + case kSE05x_SecObjTyp_RSA_KEY_PAIR_CRT: +#endif + keyObject->objectType = kSSS_KeyPart_Pair; + break; + case kSE05x_SecObjTyp_EC_PUB_KEY: + case kSE05x_SecObjTyp_RSA_PUB_KEY: + keyObject->objectType = kSSS_KeyPart_Public; + break; + case kSE05x_SecObjTyp_BINARY_FILE: + case kSE05x_SecObjTyp_PCR: + case kSE05x_SecObjTyp_AES_KEY: + case kSE05x_SecObjTyp_DES_KEY: + case kSE05x_SecObjTyp_HMAC_KEY: + case kSE05x_SecObjTyp_COUNTER: + case kSE05x_SecObjTyp_UserID: + keyObject->objectType = kSSS_KeyPart_Default; + break; + default: + keyObject->objectType = kSSS_KeyPart_NONE; + break; + } + } + else { + LOG_E("error in Se05x_API_ReadType"); + return retval; + } + + keyObject->keyId = keyId; + retval = kStatus_SSS_Success; +#endif // SSSFTR_SE05X_KEY_GET + return retval; +} + +sss_status_t sss_se05x_key_object_set_user(sss_se05x_object_t *keyObject, uint32_t user, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* Purpose / Policy is set during creation time and hence can not + * enforced in SE050 later on */ + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_set_purpose(sss_se05x_object_t *keyObject, sss_mode_t purpose, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* Purpose / Policy is set during creation time and hence can not + * enforced in SE050 later on */ + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_set_access(sss_se05x_object_t *keyObject, uint32_t access, uint32_t options) +{ + sss_status_t retval = kStatus_SSS_Fail; + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_set_eccgfp_group(sss_se05x_object_t *keyObject, sss_eccgfp_group_t *group) +{ + sss_status_t retval = kStatus_SSS_Fail; + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_get_user(sss_se05x_object_t *keyObject, uint32_t *user) +{ + sss_status_t retval = kStatus_SSS_Fail; + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_get_purpose(sss_se05x_object_t *keyObject, sss_mode_t *purpose) +{ + sss_status_t retval = kStatus_SSS_Fail; + LOG_W("Not supported in SE05X"); + return retval; +} + +sss_status_t sss_se05x_key_object_get_access(sss_se05x_object_t *keyObject, uint32_t *access) +{ + sss_status_t retval = kStatus_SSS_Fail; + LOG_W("Not supported in SE05X"); + return retval; +} + +void sss_se05x_key_object_free(sss_se05x_object_t *keyObject) +{ + memset(keyObject, 0, sizeof(*keyObject)); +} + +/* End: se05x_keyobj */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_keyderive */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_derive_key_context_init(sss_se05x_derive_key_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + + return retval; +} + +sss_status_t sss_se05x_derive_key_go(sss_se05x_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen, + uint8_t *hkdfOutput, + size_t *hkdfOutputLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t hkdfKey[SE05X_MAX_BUF_SIZE_CMD] = { + 0, + }; + size_t hkdfKeyLen = sizeof(hkdfKey); + sss_object_t *sss_derived_keyObject = (sss_object_t *)derivedKeyObject; + SE05x_DigestMode_t digestMode; + ENSURE_OR_GO_EXIT(context); + ENSURE_OR_GO_EXIT(info); + ENSURE_OR_GO_EXIT(derivedKeyObject); + if (saltLen) { + ENSURE_OR_GO_EXIT(saltData); + } + + digestMode = se05x_get_sha_algo(context->algorithm); + ENSURE_OR_GO_EXIT(digestMode != kSE05x_DigestMode_NA); + + status = Se05x_API_HKDF(&context->session->s_ctx, + context->keyObject->keyId, + digestMode, + saltData, + saltLen, + info, + infoLen, + deriveDataLen, + hkdfKey, + &hkdfKeyLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = sss_key_store_set_key((sss_key_store_t *)derivedKeyObject->keyStore, + sss_derived_keyObject, + hkdfKey, + hkdfKeyLen, + hkdfKeyLen * 8, + NULL, + 0); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + + retval = kStatus_SSS_Success; +exit: + + return retval; +} + +sss_status_t sss_se05x_derive_key_one_go(sss_se05x_derive_key_t *context, + const uint8_t *saltData, + size_t saltLen, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t hkdfKey[1024] = { + 0, + }; + size_t hkdfKeyLen = sizeof(hkdfKey); + sss_object_t *sss_derived_keyObject = (sss_object_t *)derivedKeyObject; + SE05x_DigestMode_t digestMode; + digestMode = se05x_get_sha_algo(context->algorithm); + uint32_t derivedKeyID = (derivedKeyObject == NULL ? 0 : derivedKeyObject->keyId); + uint8_t *pHkdfKey = hkdfKey; + SE05x_HkdfMode_t hkdfMode = + (context->mode == kMode_SSS_HKDF_ExpandOnly ? kSE05x_HkdfMode_ExpandOnly : kSE05x_HkdfMode_ExtractExpand); + +#if SSS_HAVE_SE05X_VER_GTE_06_00 + if (derivedKeyObject != NULL) { + if (context->keyObject->keyStore == derivedKeyObject->keyStore) { + pHkdfKey = NULL; + } + } +#endif + + ENSURE_OR_GO_EXIT(digestMode != kSE05x_DigestMode_NA); + + status = Se05x_API_HKDF_Extended(&context->session->s_ctx, + context->keyObject->keyId, + digestMode, + hkdfMode, + saltData, + saltLen, + 0, + info, + infoLen, + derivedKeyID, + deriveDataLen, + pHkdfKey, + &hkdfKeyLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (pHkdfKey != NULL) { + if (derivedKeyObject != NULL) { + retval = sss_key_store_set_key((sss_key_store_t *)derivedKeyObject->keyStore, + sss_derived_keyObject, + hkdfKey, + hkdfKeyLen, + hkdfKeyLen * 8, + NULL, + 0); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + } + } + + retval = kStatus_SSS_Success; +exit: + + return retval; +} + +sss_status_t sss_se05x_derive_key_sobj_one_go(sss_se05x_derive_key_t *context, + sss_se05x_object_t *saltKeyObject, + const uint8_t *info, + size_t infoLen, + sss_se05x_object_t *derivedKeyObject, + uint16_t deriveDataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t hkdfKey[1024] = { + 0, + }; + size_t hkdfKeyLen = sizeof(hkdfKey); + sss_object_t *sss_derived_keyObject = (sss_object_t *)derivedKeyObject; + SE05x_DigestMode_t digestMode; + digestMode = se05x_get_sha_algo(context->algorithm); + uint32_t saltID = (saltKeyObject == NULL ? 0 : saltKeyObject->keyId); + uint32_t derivedKeyID = (derivedKeyObject == NULL ? 0 : derivedKeyObject->keyId); + uint8_t *pHkdfKey = hkdfKey; + SE05x_HkdfMode_t hkdfMode = + (context->mode == kMode_SSS_HKDF_ExpandOnly ? kSE05x_HkdfMode_ExpandOnly : kSE05x_HkdfMode_ExtractExpand); + + if (saltKeyObject != NULL) { + // Enforce that Salt is stored (securely) in the same keystore as the HMAC key. + if (context->keyObject->keyStore != saltKeyObject->keyStore) { + retval = kStatus_SSS_InvalidArgument; + goto exit; + } + } + +#if SSS_HAVE_SE05X_VER_GTE_06_00 + if (derivedKeyObject != NULL) { + if (context->keyObject->keyStore == derivedKeyObject->keyStore) { + pHkdfKey = NULL; + } + } +#endif + + ENSURE_OR_GO_EXIT(digestMode != kSE05x_DigestMode_NA); + + status = Se05x_API_HKDF_Extended(&context->session->s_ctx, + context->keyObject->keyId, + digestMode, + hkdfMode, + NULL, + 0, + saltID, + info, + infoLen, + derivedKeyID, + deriveDataLen, + pHkdfKey, + &hkdfKeyLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (pHkdfKey != NULL) { + if (derivedKeyObject != NULL) { + retval = sss_key_store_set_key((sss_key_store_t *)derivedKeyObject->keyStore, + sss_derived_keyObject, + hkdfKey, + hkdfKeyLen, + hkdfKeyLen * 8, + NULL, + 0); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + } + } + + retval = kStatus_SSS_Success; +exit: + + return retval; +} + +sss_status_t sss_se05x_derive_key_dh( + sss_se05x_derive_key_t *context, sss_se05x_object_t *otherPartyKeyObject, sss_se05x_object_t *derivedKeyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t pubkey[256] = {0}; + size_t pubkeylen = sizeof(pubkey); + uint8_t sharedsecret[256]; + size_t sharedsecretLen = sizeof(sharedsecret); + size_t pbKeyBitLen = 0; + uint8_t *pPublicKey = NULL; + size_t publicKeyLen = 0; + uint16_t publicKeyIndex = 0; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + uint8_t invertEndiannes = 0x00; +#endif + + sss_object_t *sss_other_keyObject = NULL; + sss_object_t *sss_derived_keyObject = NULL; + ENSURE_OR_GO_EXIT(context); + ENSURE_OR_GO_EXIT(otherPartyKeyObject); + ENSURE_OR_GO_EXIT(derivedKeyObject); + sss_other_keyObject = (sss_object_t *)otherPartyKeyObject; + sss_derived_keyObject = (sss_object_t *)derivedKeyObject; + retval = sss_key_store_get_key( + (sss_key_store_t *)sss_other_keyObject->keyStore, sss_other_keyObject, pubkey, &pubkeylen, &pbKeyBitLen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + + switch (otherPartyKeyObject->cipherType) { +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: + /* TODO: Implement asn parser */ + publicKeyLen = pubkeylen; + publicKeyIndex = 0; + break; +#endif + default: { + retval = sss_util_pkcs8_asn1_get_ec_public_key_index( + (const uint8_t *)pubkey, pubkeylen, &publicKeyIndex, &publicKeyLen); + if (retval != kStatus_SSS_Success) { + LOG_W("error in sss_util_pkcs8_asn1_get_ec_public_key_index"); + goto exit; + } + } + } + +#if SSS_HAVE_EC_MONT + // Change Endianness Public Key in case of Montgomery Curve + { + if (otherPartyKeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + for (size_t keyValueIdx = 0; keyValueIdx < (publicKeyLen >> 1); keyValueIdx++) { + uint8_t swapByte = pubkey[publicKeyIndex + keyValueIdx]; + pubkey[publicKeyIndex + keyValueIdx] = pubkey[publicKeyIndex + publicKeyLen - 1 - keyValueIdx]; + pubkey[publicKeyIndex + publicKeyLen - 1 - keyValueIdx] = swapByte; + } + } + } +#endif + + pPublicKey = &pubkey[publicKeyIndex]; +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#if SSS_HAVE_EC_MONT + if (otherPartyKeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + // In case of Montgomery curves we want to store the + // shared secret using Little Endian Convention + invertEndiannes = 0x01; + } +#endif + + if (context->keyObject->keyStore == derivedKeyObject->keyStore) { + status = Se05x_API_ECDHGenerateSharedSecret_InObject(&context->session->s_ctx, + context->keyObject->keyId, + pPublicKey, + publicKeyLen, + derivedKeyObject->keyId, + invertEndiannes); + if (status != SM_OK) { + LOG_W("error in Se05x_API_ECDHGenerateSharedSecret_InObject"); + retval = kStatus_SSS_Fail; + goto exit; + } + } + else { +#endif + status = Se05x_API_ECGenSharedSecret(&context->session->s_ctx, + context->keyObject->keyId, + pPublicKey, + publicKeyLen, + sharedsecret, + &sharedsecretLen); + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + +#if SSS_HAVE_EC_MONT + // Change Endianness Shared Secret in case of Montgomery Curve + { + if (otherPartyKeyObject->cipherType == kSSS_CipherType_EC_MONTGOMERY) { + for (size_t keyValueIdx = 0; keyValueIdx < (publicKeyLen >> 1); keyValueIdx++) { + uint8_t swapByte = sharedsecret[keyValueIdx]; + sharedsecret[keyValueIdx] = sharedsecret[publicKeyLen - 1 - keyValueIdx]; + sharedsecret[publicKeyLen - 1 - keyValueIdx] = swapByte; + } + } + } +#endif + + retval = sss_key_store_set_key((sss_key_store_t *)derivedKeyObject->keyStore, + sss_derived_keyObject, + sharedsecret, + sharedsecretLen, + sharedsecretLen * 8, + NULL, + 0); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); +#if SSS_HAVE_SE05X_VER_GTE_06_00 + } +#endif + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_se05x_derive_key_context_free(sss_se05x_derive_key_t *context) +{ + ; +} + +/* End: se05x_keyderive */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_keystore */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_key_store_context_init(sss_se05x_key_store_t *keyStore, sss_se05x_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Success; + memset(keyStore, 0, sizeof(*keyStore)); + keyStore->session = session; + return retval; +} + +sss_status_t sss_se05x_key_store_allocate(sss_se05x_key_store_t *keyStore, uint32_t keyStoreId) +{ + return kStatus_SSS_Success; +} + +sss_status_t sss_se05x_key_store_save(sss_se05x_key_store_t *keyStore) +{ + return kStatus_SSS_Success; +} + +sss_status_t sss_se05x_key_store_load(sss_se05x_key_store_t *keyStore) +{ + return kStatus_SSS_Success; +} + +#if SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA +static sss_status_t sss_se05x_key_store_set_rsa_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + //int ret; + uint32_t key_type = keyObject->objectType; + Se05xPolicy_t se05x_policy; + //SE05x_KeyPart_t key_part; + uint8_t *rsaN = NULL, *rsaE = NULL, *rsaD = NULL; + uint8_t *rsaP = NULL, *rsaQ = NULL, *rsaDP = NULL, *rsaDQ = NULL, *rsaQINV = NULL; + size_t rsaNlen, rsaElen, rsaDlen; + size_t rsaPlen, rsaQlen, rsaDPlen, rsaDQlen, rsaQINVlen; + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + SE05x_INS_t transient_type; + SE05x_RSAKeyFormat_t rsa_format; + uint8_t IdExists = 0; + size_t keyBitLength = 0; + SE05x_Result_t obj_exists = kSE05x_Result_NA; + + /* Assign proper instruction type based on keyObject->isPersistant */ + (keyObject->isPersistant) ? (transient_type = kSE05x_INS_NA) : (transient_type = kSE05x_INS_TRANSIENT); + + if (keyObject->cipherType == kSSS_CipherType_RSA) + rsa_format = kSE05x_RSAKeyFormat_RAW; + else if (keyObject->cipherType == kSSS_CipherType_RSA_CRT) + rsa_format = kSE05x_RSAKeyFormat_CRT; + else { + retval = kStatus_SSS_Fail; + goto exit; + } + +#if 0 + if (key_type == kSSS_KeyPart_Public) + key_part = SE05x_KeyPart_Public; + else if (key_type == kSSS_KeyPart_Private) + key_part = kSE05x_KeyPart_Private; + else if (key_type == kSSS_KeyPart_Pair) + key_part = kSE05x_KeyPart_Pair; + else { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Set the kye parameters */ + status = Se05x_API_WriteRSAKey(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLen, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + key_part, + rsa_format); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } +#endif + + if (key_type == kSSS_KeyPart_Public) { + retval = sss_util_asn1_rsa_parse_public(key, keyLen, &rsaN, &rsaNlen, &rsaE, &rsaElen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + /* Set the Public Exponent */ + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLength, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + rsaE, + rsaElen, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_Public, + rsa_format, + obj_exists); + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + /* Set the Modulus */ + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + rsaN, + rsaNlen, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (key_type == kSSS_KeyPart_Private) { + if (keyObject->cipherType == kSSS_CipherType_RSA) { + retval = sss_util_asn1_rsa_parse_private(key, + keyLen, + (sss_cipher_type_t)keyObject->cipherType, + &rsaN, + &rsaNlen, + NULL, + NULL, + &rsaD, + &rsaDlen, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL); + if (retval != kStatus_SSS_Success) { + retval = kStatus_SSS_Fail; + goto exit; + } + if ((rsaN == NULL) || (rsaD == NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + // Set D(Private exponent) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLength, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + rsaD, + rsaDlen, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_Private, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set N(Modulus) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + rsaN, + rsaNlen, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (keyObject->cipherType == kSSS_CipherType_RSA_CRT) { + retval = sss_util_asn1_rsa_parse_private(key, + keyLen, + (sss_cipher_type_t)keyObject->cipherType, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + &rsaP, + &rsaPlen, + &rsaQ, + &rsaQlen, + &rsaDP, + &rsaDPlen, + &rsaDQ, + &rsaDQlen, + &rsaQINV, + &rsaQINVlen); + if (retval != kStatus_SSS_Success) { + retval = kStatus_SSS_Fail; + goto exit; + } + if ((rsaP == NULL) || (rsaQ == NULL) || (rsaDP == NULL) || (rsaDQ == NULL) || (rsaQINV == NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + // Set P component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLength, + rsaP, + rsaPlen, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_Private, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set Q component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + rsaQ, + rsaQlen, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set DP component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + rsaDP, + rsaDPlen, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set DQ component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + rsaDQ, + rsaDQlen, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set INV_Q component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + rsaQINV, + rsaQINVlen, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + } + else if (key_type == kSSS_KeyPart_Pair) { + if (keyObject->cipherType == kSSS_CipherType_RSA) { + retval = sss_util_asn1_rsa_parse_private(key, + keyLen, + (sss_cipher_type_t)keyObject->cipherType, + &rsaN, + &rsaNlen, + &rsaE, + &rsaElen, + &rsaD, + &rsaDlen, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL); + + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + ENSURE_OR_EXIT_WITH_STATUS_ON_ERROR( + !((rsaD == NULL) || (rsaE == NULL) || (rsaN == NULL)), retval, kStatus_SSS_Fail); + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + // Set E(Public exponent) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLength, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + rsaE, + rsaElen, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_Pair, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set D(Private exponent) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + rsaD, + rsaDlen, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set N(Modulus) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + rsaN, + rsaNlen, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + else if (keyObject->cipherType == kSSS_CipherType_RSA_CRT) { + retval = sss_util_asn1_rsa_parse_private(key, + keyLen, + (sss_cipher_type_t)keyObject->cipherType, + &rsaN, + &rsaNlen, + &rsaE, + &rsaElen, + NULL, + NULL, + &rsaP, + &rsaPlen, + &rsaQ, + &rsaQlen, + &rsaDP, + &rsaDPlen, + &rsaDQ, + &rsaDQlen, + &rsaQINV, + &rsaQINVlen); + ENSURE_OR_GO_EXIT(retval == kStatus_SSS_Success); + + if ((rsaP == NULL) || (rsaQ == NULL) || (rsaDP == NULL) || (rsaDQ == NULL) || (rsaQINV == NULL) || + (rsaE == NULL) || (rsaN == NULL)) { + retval = kStatus_SSS_Fail; + goto exit; + } + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + // Set P component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (U16)keyBitLength, + rsaP, + rsaPlen, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_Pair, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set Q component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + rsaQ, + rsaQlen, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set DP component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + rsaDP, + rsaDPlen, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set DQ component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + rsaDQ, + rsaDQlen, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set INV_Q component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + rsaQINV, + rsaQINVlen, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set E (Public exponent) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + rsaE, + rsaElen, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + + // Set N (Modulus) component + status = sss_se05x_LL_set_RSA_key(&keyStore->session->s_ctx, + NULL, + keyObject->keyId, + 0, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + rsaN, + rsaNlen, + transient_type, + kSE05x_KeyPart_NA, + rsa_format, + obj_exists); + + if (status != SM_OK) { + retval = kStatus_SSS_Fail; + goto exit; + } + } + } +exit: + if (rsaN != NULL) + SSS_FREE(rsaN); + if (rsaE != NULL) + SSS_FREE(rsaE); + if (rsaD != NULL) + SSS_FREE(rsaD); + if (rsaP != NULL) + SSS_FREE(rsaP); + if (rsaQ != NULL) + SSS_FREE(rsaQ); + if (rsaDP != NULL) + SSS_FREE(rsaDP); + if (rsaDQ != NULL) + SSS_FREE(rsaDQ); + if (rsaQINV != NULL) + SSS_FREE(rsaQINV); + + return retval; +} +#endif // SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA + +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +static sss_status_t getEccPrivPubKeyLen(uint32_t curve_id, size_t *pubKeyLen, size_t *privKeyLen) +{ + sss_status_t retval = kStatus_SSS_Success; + + if (privKeyLen == NULL || pubKeyLen == NULL) { + return kStatus_SSS_Fail; + } + + switch (curve_id) { +#if SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP +#if SSS_HAVE_EC_NIST_K + case kSE05x_ECCurve_Secp160k1: +#endif +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool160: +#endif + { + *privKeyLen = 20; + *pubKeyLen = 41; + } break; +#endif // SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP + +#if SSS_HAVE_EC_NIST_192 || SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP +#if SSS_HAVE_EC_NIST_192 + case kSE05x_ECCurve_NIST_P192: +#endif +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool192: +#endif +#if SSS_HAVE_EC_NIST_K + case kSE05x_ECCurve_Secp192k1: +#endif + { + *privKeyLen = 24; + *pubKeyLen = 49; + } break; +#endif // SSS_HAVE_EC_NIST_192 || SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP + +#if SSS_HAVE_EC_NIST_224| SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP +#if SSS_HAVE_EC_NIST_224 + case kSE05x_ECCurve_NIST_P224: +#endif +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool224: +#endif +#if SSS_HAVE_EC_NIST_K + case kSE05x_ECCurve_Secp224k1: +#endif + { + *privKeyLen = 28; + *pubKeyLen = 57; + } break; +#endif // SSS_HAVE_EC_NIST_224| SSS_HAVE_EC_NIST_K || SSS_HAVE_EC_BP + + case kSE05x_ECCurve_NIST_P256: +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool256: +#endif +#if SSS_HAVE_EC_NIST_K + case kSE05x_ECCurve_Secp256k1: +#endif + { + *privKeyLen = 32; + *pubKeyLen = 65; + } break; + +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool320: { + *privKeyLen = 40; + *pubKeyLen = 81; + } break; +#endif + case kSE05x_ECCurve_NIST_P384: +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool384: +#endif + { + *privKeyLen = 48; + *pubKeyLen = 97; + } break; + +#if SSS_HAVE_EC_NIST_521 + case kSE05x_ECCurve_NIST_P521: { + *privKeyLen = 66; + *pubKeyLen = 133; + } break; +#endif + +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool512: { + *privKeyLen = 64; + *pubKeyLen = 129; + } break; +#endif + +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED +#if SSS_HAVE_EC_MONT + case kSE05x_ECCurve_ECC_MONT_DH_25519: +#endif +#if SSS_HAVE_EC_ED + case kSE05x_ECCurve_ECC_ED_25519: +#endif + { + *privKeyLen = 32; + *pubKeyLen = 32; + } break; +#endif // SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + +#if SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT + case kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448: { + *privKeyLen = 56; + *pubKeyLen = 56; + } break; +#endif + default: { + *privKeyLen = 0; + *pubKeyLen = 0; + retval = kStatus_SSS_Fail; + } break; + } + + return retval; +} +#endif //SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +/* sss_se05x_create_curve_if_needed for internal to this file and for tests */ +smStatus_t sss_se05x_create_curve_if_needed(Se05xSession_t *pSession, uint32_t curve_id) +{ + smStatus_t status = SM_NOT_OK; + //uint32_t existing_curve_id = 0; + uint8_t curveList[kSE05x_ECCurve_Total_Weierstrass_Curves] = { + 0, + }; + size_t curveListLen = sizeof(curveList); + //int i = 0; + +#if SSS_HAVE_EC_ED + if (curve_id == kSE05x_ECCurve_RESERVED_ID_ECC_ED_25519) { + /* ECC_ED_25519 is always preset */ + return SM_OK; + } +#endif + +#if SSS_HAVE_EC_MONT + if (curve_id == kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_25519 +#if SSS_HAVE_SE05X_VER_GTE_06_00 + || curve_id == kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448 +#endif + ) { +#if SSS_HAVE_SE05X_VER_GTE_06_00 + status = Se05x_API_CreateECCurve(pSession, curve_id); + /* If curve is already created, Se05x_API_CreateECCurve fails. Ignore this error */ + return SM_OK; +#else + return SM_OK; + /* ECC_MONT_DH_25519 and ECC_MONT_DH_448 are always present */ +#endif + } +#endif // SSS_HAVE_EC_MONT + + status = Se05x_API_ReadECCurveList(pSession, curveList, &curveListLen); + if (status == SM_OK) { + if (curveList[curve_id - 1] == kSE05x_SetIndicator_SET) { + return SM_OK; + } + } + else { + return SM_NOT_OK; + } + + status = SM_NOT_OK; + + switch (curve_id) { +#if SSS_HAVE_EC_NIST_192 + case kSE05x_ECCurve_NIST_P192: + status = Se05x_API_CreateCurve_prime192v1(pSession, curve_id); + break; +#endif +#if SSS_HAVE_EC_NIST_224 + case kSE05x_ECCurve_NIST_P224: + status = Se05x_API_CreateCurve_secp224r1(pSession, curve_id); + break; +#endif + case kSE05x_ECCurve_NIST_P256: + status = Se05x_API_CreateCurve_prime256v1(pSession, curve_id); + break; + case kSE05x_ECCurve_NIST_P384: + status = Se05x_API_CreateCurve_secp384r1(pSession, curve_id); + break; +#if SSS_HAVE_EC_NIST_521 + case kSE05x_ECCurve_NIST_P521: + status = Se05x_API_CreateCurve_secp521r1(pSession, curve_id); + break; +#endif +#if SSS_HAVE_EC_BP + case kSE05x_ECCurve_Brainpool160: + status = Se05x_API_CreateCurve_brainpoolP160r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool192: + status = Se05x_API_CreateCurve_brainpoolP192r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool224: + status = Se05x_API_CreateCurve_brainpoolP224r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool256: + status = Se05x_API_CreateCurve_brainpoolP256r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool320: + status = Se05x_API_CreateCurve_brainpoolP320r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool384: + status = Se05x_API_CreateCurve_brainpoolP384r1(pSession, curve_id); + break; + case kSE05x_ECCurve_Brainpool512: + status = Se05x_API_CreateCurve_brainpoolP512r1(pSession, curve_id); + break; +#endif +#if SSS_HAVE_EC_NIST_K + case kSE05x_ECCurve_Secp160k1: + status = Se05x_API_CreateCurve_secp160k1(pSession, curve_id); + break; + case kSE05x_ECCurve_Secp192k1: + status = Se05x_API_CreateCurve_secp192k1(pSession, curve_id); + break; + case kSE05x_ECCurve_Secp224k1: + status = Se05x_API_CreateCurve_secp224k1(pSession, curve_id); + break; + case kSE05x_ECCurve_Secp256k1: + status = Se05x_API_CreateCurve_secp256k1(pSession, curve_id); + break; +#endif +#if SSS_HAVE_TPM_BN + case kSE05x_ECCurve_TPM_ECC_BN_P256: + status = Se05x_API_CreateCurve_tpm_bm_p256(pSession, curve_id); + break; +#endif + default: + break; + } + + ENSURE_OR_GO_EXIT(status != SM_NOT_OK); + if (status == SM_ERR_CONDITIONS_OF_USE_NOT_SATISFIED) { + LOG_W("Allowing SM_ERR_CONDITIONS_OF_USE_NOT_SATISFIED for CreateCurve"); + } +exit: + return status; +} +#endif // SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_KEY_SET || SSSFTR_SE05X_KEY_GET +static uint8_t CheckIfKeyIdExists(uint32_t keyId, pSe05xSession_t session_ctx) +{ + smStatus_t retStatus = SM_NOT_OK; + SE05x_Result_t IdExists = kSE05x_Result_NA; + + retStatus = Se05x_API_CheckObjectExists(session_ctx, keyId, &IdExists); + if (retStatus == SM_OK) { + if (IdExists == kSE05x_Result_SUCCESS) { + LOG_D("Key Id 0x%X exists", keyId); + return 1; + } + else { + return 0; + } + } + else { + LOG_E("Error in Se05x_API_CheckObjectExists"); + return 0; + } +} +#endif + +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +static sss_status_t sss_se05x_key_store_set_ecc_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_status_t asn_retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + SE05x_INS_t transient_type; + SE05x_ECCurve_t curveId = keyObject->curve_id; + SE05x_KeyPart_t key_part = kSE05x_KeyPart_NA; + SE05x_Result_t exists = kSE05x_Result_NA; + SE05x_ECCurve_t retCurveId = keyObject->curve_id; + size_t std_pubKey_len = 0; + size_t std_privKey_len = 0; +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + uint8_t privKeyReversed[64] = { + 0, + }; + uint8_t pubKeyReversed[64] = { + 0, + }; +#endif + + /* Assign proper instruction type based on keyObject->isPersistant */ + (keyObject->isPersistant) ? (transient_type = kSE05x_INS_NA) : (transient_type = kSE05x_INS_TRANSIENT); + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + if (keyObject->curve_id == 0) { + keyObject->curve_id = (SE05x_ECCurve_t)se05x_sssKeyTypeLenToCurveId((sss_cipher_type_t)keyObject->cipherType, keyBitLen); + } + + if (keyObject->curve_id == 0) { + goto exit; + } + + status = sss_se05x_create_curve_if_needed(&keyObject->keyStore->session->s_ctx, keyObject->curve_id); + + if (status == SM_NOT_OK) { + goto exit; + } + else if (status == SM_ERR_CONDITIONS_OF_USE_NOT_SATISFIED) { + LOG_W("Allowing SM_ERR_CONDITIONS_OF_USE_NOT_SATISFIED for CreateCurve"); + } + status = Se05x_API_CheckObjectExists(&keyStore->session->s_ctx, keyObject->keyId, &exists); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (exists == kSE05x_Result_SUCCESS) { + /* Check if object is of same curve id */ + status = Se05x_API_EC_CurveGetId(&keyObject->keyStore->session->s_ctx, keyObject->keyId, &retCurveId); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (retCurveId == keyObject->curve_id) { + curveId = kSE05x_ECCurve_NA; + } + else { + LOG_W("Cannot overwrite object with different curve id"); + goto exit; + } + + //if (se05x_policy.value_len != 0) { + // LOG_W("Policy + Existing Key is not a valid combination"); + //} + } + else { + curveId = keyObject->curve_id; + } + + if (keyObject->objectType == kSSS_KeyPart_Pair) { + const uint8_t *pPrivateKey = NULL; + const uint8_t *pPublicKey = NULL; + size_t privateKeyLen = 0; + size_t publicKeyLen = 0; + uint16_t privateKeyIndex = 0; + uint16_t publicKeyIndex = 0; + if (exists == kSE05x_Result_FAILURE) + key_part = kSE05x_KeyPart_Pair; + + switch (keyObject->curve_id) { +#if SSS_HAVE_TPM_BN + case kSE05x_ECCurve_TPM_ECC_BN_P256: { + LOG_I("Key pair should be paased without header"); + /* No header included in ED and BN curve keys */ + privateKeyIndex = 0; + publicKeyIndex = 32; + privateKeyLen = 32; + publicKeyLen = 32; + } break; +#endif + + default: { +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + if ((keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_ED_25519)) { + asn_retval = sss_util_rfc8410_asn1_get_ec_pair_key_index( + key, keyLen, &publicKeyIndex, &publicKeyLen, &privateKeyIndex, &privateKeyLen); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in sss_util_rfc8410_asn1_get_ec_pair_key_index"); + goto exit; + } + } + else +#endif // SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + { + asn_retval = sss_util_pkcs8_asn1_get_ec_pair_key_index( + key, keyLen, &publicKeyIndex, &publicKeyLen, &privateKeyIndex, &privateKeyLen); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in sss_util_pkcs8_asn1_get_ec_pair_key_index"); + goto exit; + } + } + + asn_retval = getEccPrivPubKeyLen((uint32_t)keyObject->curve_id, &std_pubKey_len, &std_privKey_len); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in getEccPrivPubKeyLen"); + goto exit; + } + + if (privateKeyLen != std_privKey_len) { + if (key[privateKeyIndex] == 0) { + privateKeyIndex++; + privateKeyLen--; + } + } + if (privateKeyLen != std_privKey_len) { + LOG_W("error in private key length"); + goto exit; + } + + if (publicKeyLen != std_pubKey_len) { + if (key[publicKeyIndex] == 0) { + publicKeyIndex++; + publicKeyLen--; + } + } + if (publicKeyLen != std_pubKey_len) { + LOG_W("error in public key length"); + goto exit; + } + } + } + + // Conditionally Reverse Endianness +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + if ((keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_ED_25519)) { + size_t i = 0; + size_t nByteKey = 32; // Corresponds to kSE05x_ECCurve_ECC_MONT_DH_25519 + + if (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) { + nByteKey = 56; + } + + if (keyObject->curve_id != kSE05x_ECCurve_ECC_ED_25519) { + while (i < nByteKey) { + privKeyReversed[i] = key[privateKeyIndex + privateKeyLen - i - 1]; + i++; + } + pPrivateKey = &privKeyReversed[0]; + } + else { + // SE05x expects private key to be in litte endian format + pPrivateKey = &key[privateKeyIndex]; + } + i = 0; + while (i < nByteKey) { + pubKeyReversed[i] = key[publicKeyIndex + publicKeyLen - i - 1]; + i++; + } + pPublicKey = &pubKeyReversed[0]; + } + else +#endif // SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + { + pPrivateKey = &key[privateKeyIndex]; + pPublicKey = &key[publicKeyIndex]; + } + +#ifdef TMP_ENDIAN_VERBOSE + { + printf("Private Key After Reverse:\n"); + for (size_t z = 0; z < privateKeyLen; z++) { + printf("%02X.", pPrivateKey[z]); + } + printf("\n"); + } +#endif + + status = sss_se05x_LL_set_ec_key(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_UNLIMITED, + keyObject->keyId, + curveId, + pPrivateKey, + privateKeyLen, + pPublicKey, + publicKeyLen, + transient_type, + key_part, + exists); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + else if (keyObject->objectType == kSSS_KeyPart_Public) { + const uint8_t *pPublicKey = NULL; + size_t publicKeyLen = 0; + uint16_t publicKeyIndex = 0; + if (exists == kSE05x_Result_FAILURE) + key_part = kSE05x_KeyPart_Public; + + switch (keyObject->curve_id) { +#if SSS_HAVE_TPM_BN + case kSE05x_ECCurve_TPM_ECC_BN_P256: { + LOG_I("Public key should be paased without header"); + publicKeyLen = keyLen; + } break; +#endif + default: { + asn_retval = sss_util_pkcs8_asn1_get_ec_public_key_index(key, keyLen, &publicKeyIndex, &publicKeyLen); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in sss_util_pkcs8_asn1_get_ec_public_key_index"); + goto exit; + } + + asn_retval = getEccPrivPubKeyLen((uint32_t)keyObject->curve_id, &std_pubKey_len, &std_privKey_len); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in getEccPrivPubKeyLen"); + goto exit; + } + + if (publicKeyLen != std_pubKey_len) { + if (key[publicKeyIndex] == 0) { + publicKeyIndex++; + publicKeyLen--; + } + } + if (publicKeyLen != std_pubKey_len) { + LOG_W("error in public key length"); + goto exit; + } + } + } + +#ifdef TMP_ENDIAN_VERBOSE + { + printf("Pub Key Before Reverse:\n"); + for (size_t z = 0; z < publicKeyLen; z++) { + printf("%02X.", key[publicKeyIndex + z]); + } + printf("\n"); + } +#endif + + // Conditionally Reverse Endianness +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + if ((keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_ED_25519)) { + size_t i = 0; + size_t nByteKey = 32; // Corresponds to kSE05x_ECCurve_ECC_MONT_DH_25519 + + if (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) { + nByteKey = 56; + } + + while (i < nByteKey) { + pubKeyReversed[i] = key[publicKeyIndex + publicKeyLen - i - 1]; + i++; + } + pPublicKey = &pubKeyReversed[0]; + } + else +#endif // SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + { + pPublicKey = &key[publicKeyIndex]; + } + +#ifdef TMP_ENDIAN_VERBOSE + { + printf("Pub Key After Reverse:\n"); + for (size_t z = 0; z < publicKeyLen; z++) { + printf("%02X.", pPublicKey[z]); + } + printf("\n"); + } +#endif + + status = sss_se05x_LL_set_ec_key(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_NA, + keyObject->keyId, + curveId, + NULL, + 0, + pPublicKey, + publicKeyLen, + transient_type, + key_part, + exists); + + ENSURE_OR_GO_EXIT(status == SM_OK); + } + else if (keyObject->objectType == kSSS_KeyPart_Private) { + const uint8_t *pPrivKey = NULL; + size_t privKeyLen = (uint16_t)keyLen; + uint16_t privateKeyIndex = 0; + if (exists == kSE05x_Result_FAILURE) + key_part = kSE05x_KeyPart_Private; + + LOG_I("Private key should be passed without header"); + + switch (keyObject->curve_id) { +#if SSS_HAVE_TPM_BN + case kSE05x_ECCurve_TPM_ECC_BN_P256: { + privateKeyIndex = 0; + } break; +#endif +#if SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT + case kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448: { + LOG_W( + "Private Key injection is not supported for " + "ECC_MONT_DH_448 curve"); + goto exit; + } +#endif + default: { + asn_retval = getEccPrivPubKeyLen((uint32_t)keyObject->curve_id, &std_pubKey_len, &std_privKey_len); + if (asn_retval != kStatus_SSS_Success) { + LOG_W("error in getEccPrivPubKeyLen"); + goto exit; + } + + if (keyLen != std_privKey_len) { + if (key[0] == 0) { + privKeyLen = keyLen - 1; + privateKeyIndex = 1; + } + } + if (privKeyLen != std_privKey_len) { + LOG_W("error in private key length"); + goto exit; + } + } break; + } + + pPrivKey = &key[privateKeyIndex]; + + status = sss_se05x_LL_set_ec_key(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_NA, + keyObject->keyId, + curveId, + pPrivKey, + privKeyLen, + NULL, + 0, + transient_type, + key_part, + exists); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + else { + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif // SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_AES && SSSFTR_SE05X_KEY_SET +static sss_status_t sss_se05x_key_store_set_aes_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + SE05x_INS_t transient_type; + SE05x_SymmKeyType_t type = kSE05x_SymmKeyType_NA; + SE05x_KeyID_t kekID = SE05x_KeyID_KEK_NONE; + uint8_t IdExists = 0; + SE05x_Result_t objExists = kSE05x_Result_NA; + + /* Assign proper instruction type based on keyObject->isPersistant */ + (keyObject->isPersistant) ? (transient_type = kSE05x_INS_NA) : (transient_type = kSE05x_INS_TRANSIENT); + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + objExists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + if (keyBitLen % 8 == 0) { + if (keyObject->cipherType == kSSS_CipherType_AES) { + type = kSE05x_SymmKeyType_AES; + } + else if (keyObject->cipherType == kSSS_CipherType_CMAC) { + type = kSE05x_SymmKeyType_CMAC; + } + else if (keyObject->cipherType == kSSS_CipherType_HMAC) { + type = kSE05x_SymmKeyType_HMAC; + } + + if (keyStore->kekKey != NULL) { + kekID = keyStore->kekKey->keyId; + } + status = sss_se05x_LL_set_symm_key(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_NA, + keyObject->keyId, + kekID, + key, + keyLen, + transient_type, + type, + objExists); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + else { + goto exit; + } + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif // SSSFTR_SE05X_AES && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_KEY_SET +static sss_status_t sss_se05x_key_store_set_des_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + SE05x_INS_t transient_type; + SE05x_KeyID_t kekID = SE05x_KeyID_KEK_NONE; + uint8_t IdExists = 0; + SE05x_Result_t objExists = kSE05x_Result_NA; + + /* Assign proper instruction type based on keyObject->isPersistant */ + (keyObject->isPersistant) ? (transient_type = kSE05x_INS_NA) : (transient_type = kSE05x_INS_TRANSIENT); + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + + objExists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + if (keyStore->kekKey != NULL) { + kekID = keyStore->kekKey->keyId; + } + + status = sss_se05x_LL_set_symm_key(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_NA, + keyObject->keyId, + kekID, + key, + keyLen, + transient_type, + kSE05x_SymmKeyType_DES, + objExists); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif // SSSFTR_SE05X_KEY_SET + +#if 0 +static sss_status_t sss_se05x_key_store_set_deswrapped_key( + sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + if (keyObject->isPersistant) { + status = Se05x_API_DES_SetNewWrapped_P(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + keyObject->kekId, + (U16)keyBitLen, + key, + keyLen); + } + else { + status = Se05x_API_DES_SetNewWrapped_T(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + keyObject->kekId, + (U16)keyBitLen, + key, + keyLen); + } + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +#endif + +#if SSSFTR_SE05X_KEY_SET +static sss_status_t sss_se05x_key_store_set_cert(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + uint16_t data_rem; + uint16_t offset = 0; + uint16_t fileSize = 0; + uint8_t IdExists = 0; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + SE05x_Result_t obj_exists = kSE05x_Result_NA; +#endif + + ENSURE_OR_GO_EXIT(keyLen < 0xFFFFu); + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + fileSize = (IdExists == 1) ? 0 : (uint16_t)keyLen; + data_rem = (uint16_t)keyLen; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; +#endif + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + while (data_rem > 0) { + uint16_t chunk = (data_rem > BINARY_WRITE_MAX_LEN) ? BINARY_WRITE_MAX_LEN : data_rem; + data_rem = data_rem - chunk; + +#if SSS_HAVE_SE05X_VER_GTE_06_00 + /* Call APIs For SE051 */ + obj_exists = (IdExists == 1) ? kSE05x_Result_SUCCESS : kSE05x_Result_FAILURE; + if (obj_exists == kSE05x_Result_FAILURE) { + status = Se05x_API_WriteBinary_Ver(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + offset, + (uint16_t)fileSize, + (key + offset), + chunk, + 0); + } + else if (obj_exists == kSE05x_Result_SUCCESS) { + status = Se05x_API_UpdateBinary_Ver(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + offset, + (uint16_t)fileSize, + (key + offset), + chunk, + 0); + } + else { + LOG_E("Invalid Object exist status!!!"); + } +#else + /* Call APIs For SE050 */ + status = Se05x_API_WriteBinary(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + offset, + (uint16_t)fileSize, + (key + offset), + chunk); +#endif + ENSURE_OR_GO_EXIT(status == SM_OK); + + fileSize = 0; + offset = offset + chunk; + } + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif // SSSFTR_SE05X_KEY_SET + +#if 0 +static sss_status_t sss_se05x_key_store_set_pcr( + sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + void *policy_buff, + size_t policy_buff_len) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05xPolicy_t se05x_policy; + + se05x_policy.value = (uint8_t *)policy_buff; + se05x_policy.value_len = policy_buff_len; + + if (keyObject->cipherType == kSSS_CipherType_PCR) { + status = Se05x_API_WritePCR_WithType(&keyStore->session->s_ctx, + kSE05x_INS_NA, + &se05x_policy, + keyObject->keyId, + key, + keyLen, + NULL, + 0); + } + else if (keyObject->cipherType == kSSS_CipherType_Update_PCR) { + status = Se05x_API_WritePCR_WithType(&keyStore->session->s_ctx, + kSE05x_INS_NA, + &se05x_policy, + keyObject->keyId, + NULL, + 0, + key, + keyLen + ); + } + else if (keyObject->cipherType == kSSS_CipherType_Reset_PCR) { + status = Se05x_API_WritePCR_WithType(&keyStore->session->s_ctx, + kSE05x_INS_NA, + &se05x_policy, + keyObject->keyId, + NULL, + 0, + NULL, + 0); + } + else + { + goto exit; + } + + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif + +sss_status_t sss_se05x_key_store_set_key(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + const uint8_t *key, + size_t keyLen, + size_t keyBitLen, + void *options, + size_t optionsLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + +#if SSSFTR_SE05X_KEY_SET + + sss_cipher_type_t cipher_type = kSSS_CipherType_NONE; + sss_policy_t *policies = (sss_policy_t *)options; + uint8_t *ppolicySet; + size_t valid_policy_buff_len = 0; + uint8_t policies_buff[MAX_POLICY_BUFFER_SIZE]= { 0,}; + + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + if (keyBitLen) { + ENSURE_OR_GO_EXIT(key); + } + cipher_type = (sss_cipher_type_t)keyObject->cipherType; + + if (policies) { + if (kStatus_SSS_Success != + sss_se05x_create_object_policy_buffer(policies, &policies_buff[0], &valid_policy_buff_len)) { + goto exit; + } + ppolicySet = policies_buff; + } + else { + ppolicySet = NULL; + } + + switch (cipher_type) { +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: + if (kStatus_SSS_Success != + sss_se05x_key_store_set_rsa_key( + keyStore, keyObject, key, keyLen, keyBitLen, ppolicySet, valid_policy_buff_len)) { + goto exit; + } + break; +#endif +#if SSSFTR_SE05X_ECC + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif + if (kStatus_SSS_Success != + sss_se05x_key_store_set_ecc_key( + keyStore, keyObject, key, keyLen, keyBitLen, ppolicySet, valid_policy_buff_len)) { + goto exit; + } + break; +#endif // SSSFTR_SE05X_ECC + case kSSS_CipherType_AES: + if ((keyLen != 16 && keyLen != 24 && keyLen != 32 && keyLen != 40)) { + goto exit; + } + /* fall through */ + case kSSS_CipherType_CMAC: + case kSSS_CipherType_HMAC: +#if SSSFTR_SE05X_AES && SSSFTR_SE05X_KEY_SET + if (kStatus_SSS_Success != + sss_se05x_key_store_set_aes_key( + keyStore, keyObject, key, keyLen, keyBitLen, ppolicySet, valid_policy_buff_len)) { + goto exit; + } +#else + goto exit; +#endif + break; + case kSSS_CipherType_DES: + if (kStatus_SSS_Success != + sss_se05x_key_store_set_des_key( + keyStore, keyObject, key, keyLen, keyBitLen, ppolicySet, valid_policy_buff_len)) { + goto exit; + } + break; + case kSSS_CipherType_Binary: + case kSSS_CipherType_Certificate: { + if (kStatus_SSS_Success != + sss_se05x_key_store_set_cert( + keyStore, keyObject, key, keyLen, keyBitLen, ppolicySet, valid_policy_buff_len)) { + goto exit; + } + } break; + default: + goto exit; + } + retval = kStatus_SSS_Success; +exit: +#endif /* SSSFTR_SE05X_KEY_SET */ + return retval; +} + +sss_status_t sss_se05x_key_store_generate_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, size_t keyBitLen, void *options) +{ + sss_status_t retval = kStatus_SSS_Fail; + +#if SSSFTR_SE05X_KEY_SET + smStatus_t status = SM_NOT_OK; + sss_policy_t *policies = (sss_policy_t *)options; + uint8_t *ppolicySet; + size_t valid_policy_buff_len = 0; + Se05xPolicy_t se05x_policy; + SE05x_INS_t transient_type; + uint8_t IdExists = 0; + uint8_t policies_buff[MAX_POLICY_BUFFER_SIZE]; + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + + if (policies) { + if (kStatus_SSS_Success != + sss_se05x_create_object_policy_buffer(policies, &policies_buff[0], &valid_policy_buff_len)) { + goto exit; + } + ppolicySet = policies_buff; + } + else { + ppolicySet = NULL; + } + se05x_policy.value = (uint8_t *)ppolicySet; + se05x_policy.value_len = valid_policy_buff_len; + + /* Assign proper instruction type based on keyObject->isPersistant */ + (keyObject->isPersistant) ? (transient_type = kSE05x_INS_NA) : (transient_type = kSE05x_INS_TRANSIENT); + + ENSURE_OR_GO_EXIT(keyObject->objectType == kSSS_KeyPart_Pair); + + switch (keyObject->cipherType) { +#if SSSFTR_SE05X_ECC + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif + { + SE05x_ECCurve_t curve_id; + if (keyObject->curve_id == kSE05x_ECCurve_NA) { + keyObject->curve_id = (SE05x_ECCurve_t)se05x_sssKeyTypeLenToCurveId((sss_cipher_type_t)keyObject->cipherType, keyBitLen); + } + + if (keyObject->curve_id == kSE05x_ECCurve_NA) { + goto exit; + } + + status = sss_se05x_create_curve_if_needed(&keyObject->keyStore->session->s_ctx, keyObject->curve_id); + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + curve_id = (IdExists == 1) ? kSE05x_ECCurve_NA : (SE05x_ECCurve_t)keyObject->curve_id; + + status = Se05x_API_WriteECKey(&keyStore->session->s_ctx, + &se05x_policy, + SE05x_MaxAttemps_NA, + keyObject->keyId, + curve_id, + NULL, + 0, + NULL, + 0, + transient_type, + kSE05x_KeyPart_Pair); + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + } +#endif // < SSSFTR_SE05X_ECC +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + /* Hard Coded Public exponent to be 65537 */ + //uint8_t pubexp[] = {0x01, 0x00, 0x01}; + SE05x_KeyPart_t key_part = kSE05x_KeyPart_Pair; + SE05x_RSAKeyFormat_t rsa_format; + size_t keyBitLength = 0; + if (keyObject->cipherType == kSSS_CipherType_RSA) + rsa_format = kSE05x_RSAKeyFormat_RAW; + else if (keyObject->cipherType == kSSS_CipherType_RSA_CRT) + rsa_format = kSE05x_RSAKeyFormat_CRT; + else { + retval = kStatus_SSS_Fail; + goto exit; + } + + IdExists = CheckIfKeyIdExists(keyObject->keyId, &keyStore->session->s_ctx); + keyBitLength = (IdExists == 1) ? 0 : keyBitLen; + + status = Se05x_API_WriteRSAKey(&keyStore->session->s_ctx, + &se05x_policy, + keyObject->keyId, + (uint16_t)keyBitLength, + SE05X_RSA_NO_p, + SE05X_RSA_NO_q, + SE05X_RSA_NO_dp, + SE05X_RSA_NO_dq, + SE05X_RSA_NO_qInv, + SE05X_RSA_NO_pubExp, + SE05X_RSA_NO_priv, + SE05X_RSA_NO_pubMod, + transient_type, + key_part, + rsa_format); + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + } +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA + default: { + goto exit; + } + } + + retval = kStatus_SSS_Success; +exit: +#endif // SSSFTR_SE05X_KEY_SET + return retval; +} + +#define ADD_DER_ECC_NISTP192_HEADER(x) ((x) + der_ecc_nistp192_header_len) +#define REMOVE_DER_ECC_NISTP192_HEADER(x) ((x)-der_ecc_nistp192_header_len) + +#define ADD_DER_ECC_NISTP224_HEADER(x) ((x) + der_ecc_nistp224_header_len) +#define REMOVE_DER_ECC_NISTP224_HEADER(x) ((x)-der_ecc_nistp224_header_len) + +#define ADD_DER_ECC_NISTP256_HEADER(x) ((x) + der_ecc_nistp256_header_len) +#define REMOVE_DER_ECC_NISTP256_HEADER(x) ((x)-der_ecc_nistp256_header_len) + +#define ADD_DER_ECC_NISTP384_HEADER(x) ((x) + der_ecc_nistp384_header_len) +#define REMOVE_DER_ECC_NISTP384_HEADER(x) ((x)-der_ecc_nistp384_header_len) + +#define ADD_DER_ECC_NISTP521_HEADER(x) ((x) + der_ecc_nistp521_header_len) +#define REMOVE_DER_ECC_NISTP521_HEADER(x) ((x)-der_ecc_nistp521_header_len) + +#define ADD_DER_ECC_160K_HEADER(x) ((x) + der_ecc_160k_header_len) +#define REMOVE_DER_ECC_160K_HEADER(x) ((x)-der_ecc_160k_header_len) + +#define ADD_DER_ECC_192K_HEADER(x) ((x) + der_ecc_192k_header_len) +#define REMOVE_DER_ECC_192K_HEADER(x) ((x)-der_ecc_192k_header_len) + +#define ADD_DER_ECC_224K_HEADER(x) ((x) + der_ecc_224k_header_len) +#define REMOVE_DER_ECC_224K_HEADER(x) ((x)-der_ecc_224k_header_len) + +#define ADD_DER_ECC_256K_HEADER(x) ((x) + der_ecc_256k_header_len) +#define REMOVE_DER_ECC_256K_HEADER(x) ((x)-der_ecc_256k_header_len) + +#define ADD_DER_ECC_BP160_HEADER(x) ((x) + der_ecc_bp160_header_len) +#define REMOVE_DER_ECC_BP160_HEADER(x) ((x)-der_ecc_bp160_header_len) + +#define ADD_DER_ECC_BP192_HEADER(x) ((x) + der_ecc_bp192_header_len) +#define REMOVE_DER_ECC_BP192_HEADER(x) ((x)-der_ecc_bp192_header_len) + +#define ADD_DER_ECC_BP224_HEADER(x) ((x) + der_ecc_bp224_header_len) +#define REMOVE_DER_ECC_BP224_HEADER(x) ((x)-der_ecc_bp224_header_len) + +#define ADD_DER_ECC_BP320_HEADER(x) ((x) + der_ecc_bp320_header_len) +#define REMOVE_DER_ECC_BP320_HEADER(x) ((x)-der_ecc_bp320_header_len) + +#define ADD_DER_ECC_BP384_HEADER(x) ((x) + der_ecc_bp384_header_len) +#define REMOVE_DER_ECC_BP384_HEADER(x) ((x)-der_ecc_bp384_header_len) + +#define ADD_DER_ECC_BP256_HEADER(x) ((x) + der_ecc_bp256_header_len) +#define REMOVE_DER_ECC_BP256_HEADER(x) ((x)-der_ecc_bp256_header_len) + +#define ADD_DER_ECC_BP512_HEADER(x) ((x) + der_ecc_bp512_header_len) +#define REMOVE_DER_ECC_BP512_HEADER(x) ((x)-der_ecc_bp512_header_len) + +#define ADD_DER_ECC_MONT_DH_448_HEADER(x) ((x) + der_ecc_mont_dh_448_header_len) +#define REMOVE_DER_ECC_MONT_DH_448_HEADER(x) ((x)-der_ecc_mont_dh_448_header_len) +#define ADD_DER_ECC_MONT_DH_25519_HEADER(x) ((x) + der_ecc_mont_dh_25519_header_len) +#define REMOVE_DER_ECC_MONT_DH_25519_HEADER(x) ((x)-der_ecc_mont_dh_25519_header_len) + +#define ADD_DER_ECC_TWISTED_ED_25519_HEADER(x) ((x) + der_ecc_twisted_ed_25519_header_len) +#define REMOVE_DER_ECC_TWISTED_ED_25519_HEADER(x) ((x)-der_ecc_twisted_ed_25519_header_len) + +#define CONVERT_BYTE(x) ((x) / 8) +#define CONVERT_BIT(x) ((x)*8) + +void add_ecc_header(uint8_t *key, size_t *keylen, uint8_t **key_buf, size_t *key_buflen, uint32_t curve_id) +{ + if (key == NULL || key_buf == NULL || key_buflen == NULL){ + goto exit; + } +#if SSSFTR_SE05X_KEY_SET + if (curve_id == kSE05x_ECCurve_NIST_P256) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_nistp256_header_len); + memcpy(key, gecc_der_header_nist256, der_ecc_nistp256_header_len); + *key_buf = ADD_DER_ECC_NISTP256_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_NISTP256_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_NIST_P384) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_nistp384_header_len); + memcpy(key, gecc_der_header_nist384, der_ecc_nistp384_header_len); + *key_buf = ADD_DER_ECC_NISTP384_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_NISTP384_HEADER(*key_buflen); + } +#if SSS_HAVE_EC_NIST_192 + else if (curve_id == kSE05x_ECCurve_NIST_P192) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_nistp192_header_len); + memcpy(key, gecc_der_header_nist192, der_ecc_nistp192_header_len); + *key_buf = ADD_DER_ECC_NISTP192_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_NISTP192_HEADER(*key_buflen); + } +#endif +#if SSS_HAVE_EC_NIST_224 + else if (curve_id == kSE05x_ECCurve_NIST_P224) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_nistp224_header_len); + memcpy(key, gecc_der_header_nist224, der_ecc_nistp224_header_len); + *key_buf = ADD_DER_ECC_NISTP224_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_NISTP224_HEADER(*key_buflen); + } +#endif +#if SSS_HAVE_EC_NIST_521 + else if (curve_id == kSE05x_ECCurve_NIST_P521) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_nistp521_header_len); + memcpy(key, gecc_der_header_nist521, der_ecc_nistp521_header_len); + *key_buf = ADD_DER_ECC_NISTP521_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_NISTP521_HEADER(*key_buflen); + } +#endif +#if SSS_HAVE_EC_BP + else if (curve_id == kSE05x_ECCurve_Brainpool160) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp160_header_len); + memcpy(key, gecc_der_header_bp160, der_ecc_bp160_header_len); + *key_buf = ADD_DER_ECC_BP160_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP160_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool192) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp192_header_len); + memcpy(key, gecc_der_header_bp192, der_ecc_bp192_header_len); + *key_buf = ADD_DER_ECC_BP192_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP192_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool224) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp224_header_len); + memcpy(key, gecc_der_header_bp224, der_ecc_bp224_header_len); + *key_buf = ADD_DER_ECC_BP224_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP224_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool320) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp320_header_len); + memcpy(key, gecc_der_header_bp320, der_ecc_bp320_header_len); + *key_buf = ADD_DER_ECC_BP320_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP320_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool384) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp384_header_len); + memcpy(key, gecc_der_header_bp384, der_ecc_bp384_header_len); + *key_buf = ADD_DER_ECC_BP384_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP384_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool256) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp256_header_len); + memcpy(key, gecc_der_header_bp256, der_ecc_bp256_header_len); + *key_buf = ADD_DER_ECC_BP256_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP256_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool512) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_bp512_header_len); + memcpy(key, gecc_der_header_bp512, der_ecc_bp512_header_len); + *key_buf = ADD_DER_ECC_BP512_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_BP512_HEADER(*key_buflen); + } +#endif +#if SSS_HAVE_EC_NIST_K + else if (curve_id == kSE05x_ECCurve_Secp256k1) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_256k_header_len); + memcpy(key, gecc_der_header_256k, der_ecc_256k_header_len); + *key_buf = ADD_DER_ECC_256K_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_256K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp160k1) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_160k_header_len); + memcpy(key, gecc_der_header_160k, der_ecc_160k_header_len); + *key_buf = ADD_DER_ECC_160K_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_160K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp192k1) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_192k_header_len); + memcpy(key, gecc_der_header_192k, der_ecc_192k_header_len); + *key_buf = ADD_DER_ECC_192K_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_192K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp224k1) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_224k_header_len); + memcpy(key, gecc_der_header_224k, der_ecc_224k_header_len); + *key_buf = ADD_DER_ECC_224K_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_224K_HEADER(*key_buflen); + } +#endif +#if SSS_HAVE_EC_MONT +#if SSS_HAVE_SE05X_VER_GTE_06_00 + else if (curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_mont_dh_448_header_len); + memcpy(key, gecc_der_header_mont_dh_448, der_ecc_mont_dh_448_header_len); + *key_buf = ADD_DER_ECC_MONT_DH_448_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_MONT_DH_448_HEADER(*key_buflen); + } +#endif + else if (curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_mont_dh_25519_header_len); + memcpy(key, gecc_der_header_mont_dh_25519, der_ecc_mont_dh_25519_header_len); + *key_buf = ADD_DER_ECC_MONT_DH_25519_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_MONT_DH_25519_HEADER(*key_buflen); + } +#endif // SSS_HAVE_EC_MONT +#if SSS_HAVE_EC_ED + else if (curve_id == kSE05x_ECCurve_ECC_ED_25519) { + ENSURE_OR_GO_EXIT((*keylen) > der_ecc_twisted_ed_25519_header_len); + memcpy(key, gecc_der_header_twisted_ed_25519, der_ecc_twisted_ed_25519_header_len); + *key_buf = ADD_DER_ECC_TWISTED_ED_25519_HEADER(key); + *key_buflen = (uint16_t)ADD_DER_ECC_TWISTED_ED_25519_HEADER(*key_buflen); + } +#endif + else { + LOG_W("Returned is not in DER Format"); + *key_buf = key; + *key_buflen = 0; + } +#endif +exit: + return; +} + +void get_ecc_raw_data(uint8_t *key, size_t keylen, uint8_t **key_buf, size_t *key_buflen, uint32_t curve_id) +{ + if (key == NULL || key_buf == NULL || key_buflen == NULL){ + goto exit; + } + + if (curve_id == kSE05x_ECCurve_NIST_P256) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_nistp256_header_len); + *key_buf = ADD_DER_ECC_NISTP256_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_NISTP256_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_NIST_P384) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_nistp384_header_len); + *key_buf = ADD_DER_ECC_NISTP384_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_NISTP384_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_NIST_P192) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_nistp192_header_len); + *key_buf = ADD_DER_ECC_NISTP192_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_NISTP192_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_NIST_P224) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_nistp224_header_len); + *key_buf = ADD_DER_ECC_NISTP224_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_NISTP224_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_NIST_P521) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_nistp521_header_len); + *key_buf = ADD_DER_ECC_NISTP521_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_NISTP521_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool160) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp160_header_len); + *key_buf = ADD_DER_ECC_BP160_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP160_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool192) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp192_header_len); + *key_buf = ADD_DER_ECC_BP192_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP192_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool224) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp224_header_len); + *key_buf = REMOVE_DER_ECC_BP224_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP224_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool320) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp320_header_len); + *key_buf = ADD_DER_ECC_BP320_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP320_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool384) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp384_header_len); + *key_buf = ADD_DER_ECC_BP384_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP384_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool256) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp256_header_len); + *key_buf = ADD_DER_ECC_BP256_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP256_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Brainpool512) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_bp512_header_len); + *key_buf = ADD_DER_ECC_BP512_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_BP512_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp256k1) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_256k_header_len); + *key_buf = ADD_DER_ECC_256K_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_256K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp160k1) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_160k_header_len); + *key_buf = ADD_DER_ECC_160K_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_160K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp192k1) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_192k_header_len); + *key_buf = ADD_DER_ECC_192K_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_192K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_Secp224k1) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_224k_header_len); + *key_buf = ADD_DER_ECC_224K_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_224K_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_ECC_ED_25519) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_twisted_ed_25519_header_len); + *key_buf = ADD_DER_ECC_TWISTED_ED_25519_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_TWISTED_ED_25519_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_mont_dh_25519_header_len); + *key_buf = ADD_DER_ECC_MONT_DH_25519_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_MONT_DH_25519_HEADER(*key_buflen); + } + else if (curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) { + ENSURE_OR_GO_EXIT(keylen > der_ecc_mont_dh_448_header_len); + *key_buf = ADD_DER_ECC_MONT_DH_448_HEADER(key); + *key_buflen = (uint16_t)REMOVE_DER_ECC_MONT_DH_448_HEADER(*key_buflen); + } + else { + LOG_W("Returned is not in DER Format"); + *key_buf = key; + *key_buflen = 0; + } + +exit: + return; +} + +sss_status_t sss_se05x_key_store_get_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *key, size_t *keylen, size_t *pKeyBitLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_cipher_type_t cipher_type = kSSS_CipherType_NONE; + smStatus_t status = SM_NOT_OK; + uint16_t size; + ENSURE_OR_GO_EXIT(keyObject); + ENSURE_OR_GO_EXIT(key); + ENSURE_OR_GO_EXIT(keylen); + ENSURE_OR_GO_EXIT(pKeyBitLen); + + cipher_type = (sss_cipher_type_t)keyObject->cipherType; + + switch (cipher_type) { + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif + { + uint8_t *key_buf = NULL; + size_t key_buflen = 0; + + /* Return the Key length including the ECC DER Header */ + add_ecc_header(key, keylen, &key_buf, &key_buflen, keyObject->curve_id); + (*keylen) = (*keylen) - key_buflen; + + status = Se05x_API_ReadObject(&keyStore->session->s_ctx, keyObject->keyId, 0, 0, key_buf, keylen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + /* Change Endiannes. */ +#if SSS_HAVE_TPM_BN || SSS_HAVE_EC_ED + if ((keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_ED_25519)) { + for (size_t keyValueIdx = 0; keyValueIdx < (*keylen >> 1); keyValueIdx++) { + uint8_t swapByte = key_buf[keyValueIdx]; + key_buf[keyValueIdx] = key_buf[*keylen - 1 - keyValueIdx]; + key_buf[*keylen - 1 - keyValueIdx] = swapByte; + } + } +#endif + + /* Return the Key length with header length */ + *keylen += key_buflen; + + break; + } +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + uint8_t modulus[1024] = {0}; + uint8_t exponent[4] = {0}; + size_t modLen = sizeof(modulus); + size_t expLen = sizeof(exponent); + + status = Se05x_API_ReadRSA( + &keyStore->session->s_ctx, keyObject->keyId, 0, 0, kSE05x_RSAPubKeyComp_MOD, modulus, &modLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + status = Se05x_API_ReadRSA( + &keyStore->session->s_ctx, keyObject->keyId, 0, 0, kSE05x_RSAPubKeyComp_PUB_EXP, exponent, &expLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (sss_util_asn1_rsa_get_public(key, keylen, modulus, modLen, exponent, expLen) != kStatus_SSS_Success) { + goto exit; + } + } break; +#endif // SSSFTR_SE05X_RSA && && SSS_HAVE_RSA + case kSSS_CipherType_AES: + status = Se05x_API_ReadObject(&keyStore->session->s_ctx, keyObject->keyId, 0, 0, key, keylen); + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + case kSSS_CipherType_Binary: + case kSSS_CipherType_Certificate: { + uint16_t rem_data = 0; + uint16_t offset = 0; + size_t max_buffer = 0; + status = Se05x_API_ReadSize(&keyStore->session->s_ctx, keyObject->keyId, &size); + ENSURE_OR_GO_EXIT(status == SM_OK); + if (*keylen < size) { + LOG_E("Insufficient buffer "); + goto exit; + } + + rem_data = size; + *keylen = size; + while (rem_data > 0) { + uint16_t chunk = (rem_data > BINARY_WRITE_MAX_LEN) ? BINARY_WRITE_MAX_LEN : rem_data; + rem_data = rem_data - chunk; + max_buffer = chunk; + status = Se05x_API_ReadObject( + &keyStore->session->s_ctx, keyObject->keyId, offset, chunk, (key + offset), &max_buffer); + ENSURE_OR_GO_EXIT(status == SM_OK); + offset = offset + chunk; + } + + } break; + case kSSS_CipherType_DES: + status = Se05x_API_ReadObject(&keyStore->session->s_ctx, keyObject->keyId, 0, 0, key, keylen); + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + case kSSS_CipherType_PCR: + status = Se05x_API_ReadObject(&keyStore->session->s_ctx, keyObject->keyId, 0, 0, key, keylen); + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + case kSSS_CipherType_Count: + status = Se05x_API_ReadObject(&keyStore->session->s_ctx, keyObject->keyId, 0, 0, key, keylen); + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_key_store_get_key_attst(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + uint8_t *key, + size_t *keylen, + size_t *pKeyBitLen, + sss_se05x_object_t *keyObject_attst, + sss_algorithm_t algorithm_attst, + uint8_t *random_attst, + size_t randomLen_attst, + sss_se05x_attst_data_t *attst_data) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_cipher_type_t cipher_type = (sss_cipher_type_t)keyObject->cipherType; + smStatus_t status = SM_NOT_OK; + uint16_t size; + + uint32_t attestID; + SE05x_AttestationAlgo_t attestAlgo; + + attestID = keyObject_attst->keyId; + + switch (keyObject_attst->cipherType) { + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif + { + SE05x_ECSignatureAlgo_t ecSignAlgo = (SE05x_ECSignatureAlgo_t)se05x_get_ec_sign_hash_mode(algorithm_attst); + attestAlgo = (SE05x_AttestationAlgo_t)ecSignAlgo; + } break; + +#if SSS_HAVE_EC_ED || SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_TWISTED_ED: + case kSSS_CipherType_EC_BARRETO_NAEHRIG: { + LOG_E("Attestation not supported"); + return retval; + } break; +#endif + +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + SE05x_RSASignatureAlgo_t rsaSigningAlgo = se05x_get_rsa_sign_hash_mode(algorithm_attst); + attestAlgo = (SE05x_AttestationAlgo_t)rsaSigningAlgo; + } break; +#endif + default: + goto exit; + } + + switch (cipher_type) { + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif + { + uint8_t *key_buf = NULL; + size_t key_buflen = 0; + + /* Return the Key length including the ECC DER Header */ + add_ecc_header(key, keylen, &key_buf, &key_buflen, keyObject->curve_id); + (*keylen) = (*keylen) - key_buflen; + + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key_buf, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + ENSURE_OR_GO_EXIT(status == SM_OK); + +#if SSS_HAVE_EC_MONT || SSS_HAVE_EC_ED + /* Change Endiannes. */ + if ((keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_25519) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_MONT_DH_448) || + (keyObject->curve_id == kSE05x_ECCurve_ECC_ED_25519)) { + for (size_t keyValueIdx = 0; keyValueIdx < (*keylen >> 1); keyValueIdx++) { + uint8_t swapByte = key_buf[keyValueIdx]; + key_buf[keyValueIdx] = key_buf[*keylen - 1 - keyValueIdx]; + key_buf[*keylen - 1 - keyValueIdx] = swapByte; + } + } +#endif + + attst_data->valid_number = 1; + /* Return the Key length with header length */ + *keylen += key_buflen; + + break; + } +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + uint8_t modulus[1024]; + uint8_t exponent[4]; + size_t modLen = sizeof(modulus); + size_t expLen = sizeof(exponent); + uint16_t key_size_bytes = 0; + + if (attestAlgo == kSE05x_AttestationAlgo_RSA_SHA_512_PKCS1 || + attestAlgo == kSE05x_AttestationAlgo_RSA_SHA512_PKCS1_PSS) { + status = Se05x_API_ReadSize(&keyStore->session->s_ctx, keyObject_attst->keyId, &key_size_bytes); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + + if ((key_size_bytes * 8) == 512) { + return kStatus_SSS_Fail; + } + } + + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadRSA_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + kSE05x_RSAPubKeyComp_MOD, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + modulus, + &modLen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + ENSURE_OR_GO_EXIT(status == SM_OK); + + attst_data->data[1].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadRSA_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + kSE05x_RSAPubKeyComp_PUB_EXP, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + exponent, + &expLen, + attst_data->data[1].attribute, + &(attst_data->data[1].attributeLen), + &(attst_data->data[1].timeStamp), + attst_data->data[1].outrandom, + &(attst_data->data[1].outrandomLen), + attst_data->data[1].chipId, + &(attst_data->data[1].chipIdLen), + attst_data->data[1].signature, + &(attst_data->data[1].signatureLen)); + + attst_data->valid_number = 2; + + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (sss_util_asn1_rsa_get_public(key, keylen, modulus, modLen, exponent, expLen) != kStatus_SSS_Success) { + goto exit; + } + } break; +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_AES: + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + + attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + case kSSS_CipherType_Binary: + case kSSS_CipherType_Certificate: { + uint16_t rem_data = 0; + uint16_t offset = 0; + size_t dataLen = 0; + // size_t signatureLen = 0; + status = Se05x_API_ReadSize(&keyStore->session->s_ctx, keyObject->keyId, &size); + ENSURE_OR_GO_EXIT(status == SM_OK); + + if (*keylen < size) { + LOG_E("Insufficient buffer "); + goto exit; + } + + rem_data = size; + *keylen = size; + if (size > BINARY_WRITE_MAX_LEN) { + LOG_E("Cannot read large binary data with attestation"); + goto exit; + } + // while (rem_data > 0) { + // uint16_t chunk = (rem_data > BINARY_WRITE_MAX_LEN) ? + // BINARY_WRITE_MAX_LEN : + // rem_data; + // rem_data = rem_data - chunk; + dataLen = rem_data; + + // signatureLen = attst_data->data[0].signatureLen; + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + offset, + rem_data, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + (key + 0), + &dataLen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &attst_data->data[0].signatureLen); + + // attst_data->data[0].signatureLen -= signatureLen; + // attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + + // offset = offset + chunk; + // } + } break; + case kSSS_CipherType_DES: + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + + attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + + case kSSS_CipherType_PCR: + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + + attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + + case kSSS_CipherType_Count: + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + + attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + + case kSSS_CipherType_HMAC: + case kSSS_CipherType_CMAC: + case kSSS_CipherType_UserID: { + attst_data->data[0].timeStampLen = sizeof(SE05x_TimeStamp_t); + status = Se05x_API_ReadObject_W_Attst(&keyStore->session->s_ctx, + keyObject->keyId, + 0, + 0, + attestID, + attestAlgo, + random_attst, + randomLen_attst, + key, + keylen, + attst_data->data[0].attribute, + &(attst_data->data[0].attributeLen), + &(attst_data->data[0].timeStamp), + attst_data->data[0].outrandom, + &(attst_data->data[0].outrandomLen), + attst_data->data[0].chipId, + &(attst_data->data[0].chipIdLen), + attst_data->data[0].signature, + &(attst_data->data[0].signatureLen)); + + attst_data->valid_number = 1; + + ENSURE_OR_GO_EXIT(status == SM_OK); + break; + } + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +#if 0 +/* To be reviewed: Purnank */ +sss_status_t sss_se05x_key_store_get_key_fromoffset(sss_se05x_key_store_t *keyStore, + sss_se05x_object_t *keyObject, + uint8_t *key, + size_t *keylen, + size_t *pKeyBitLen, + uint16_t offset) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_key_type_t key_type = keyObject->objectType; + smStatus_t status = SM_NOT_OK; + + switch (key_type) { + case kSSS_KeyType_Certificate: + status = + Se05x_API_FIL_BinaryReadFromOffset(&keyStore->session->s_ctx, + keyObject->keyId, + (uint16_t)*keylen, + offset, + key, + keylen); + if (status != SM_OK) + goto exit; + break; + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} +#endif +sss_status_t sss_se05x_key_store_open_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; + + if (NULL == keyObject) { + keyStore->kekKey = NULL; + retval = kStatus_SSS_Success; + } + else if (keyObject->keyStore == keyStore) { + keyStore->kekKey = keyObject; + retval = kStatus_SSS_Success; + } + else { + LOG_W("KeyObject must be of same KeyStore."); + } + + return retval; +} + +sss_status_t sss_se05x_key_store_freeze_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; + /* Purpose / Policy is set during creation time and hence can not + * enforced in SE050 later on */ + return retval; +} + +sss_status_t sss_se05x_key_store_erase_key(sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + ENSURE_OR_GO_EXIT(keyStore); + ENSURE_OR_GO_EXIT(keyObject); + + status = Se05x_API_DeleteSecureObject(&keyStore->session->s_ctx, keyObject->keyId); + if (SM_OK == status) { + LOG_D("Erased Key id %X", keyObject->keyId); + retval = kStatus_SSS_Success; + } + else { + LOG_W("Could not delete Key id %X", keyObject->keyId); + } +exit: + return retval; +} + +void sss_se05x_key_store_context_free(sss_se05x_key_store_t *keyStore) +{ + memset(keyStore, 0, sizeof(*keyStore)); +} + +sss_status_t sss_se05x_key_store_export_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *key, size_t *keylen) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_cipher_type_t cipher_type = (sss_cipher_type_t)keyObject->cipherType; + smStatus_t status = SM_NOT_OK; + + switch (cipher_type) { + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif + case kSSS_CipherType_AES: + case kSSS_CipherType_DES: { + status = + Se05x_API_ExportObject(&keyStore->session->s_ctx, keyObject->keyId, kSE05x_RSAKeyComponent_NA, key, keylen); + if (status != SM_OK) { + goto exit; + } + + break; + } + + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_key_store_import_key( + sss_se05x_key_store_t *keyStore, sss_se05x_object_t *keyObject, uint8_t *key, size_t keylen) +{ + sss_status_t retval = kStatus_SSS_Fail; + sss_cipher_type_t cipher_type = (sss_cipher_type_t)keyObject->cipherType; + smStatus_t status = SM_NOT_OK; + + switch (cipher_type) { + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: +#endif + case kSSS_CipherType_AES: + case kSSS_CipherType_DES: { + status = + Se05x_API_ImportObject(&keyStore->session->s_ctx, keyObject->keyId, kSE05x_RSAKeyComponent_NA, key, keylen); + if (status != SM_OK) { + goto exit; + } + + break; + } + + default: + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +/* End: se05x_keystore */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_asym */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_asymmetric_context_init(sss_se05x_asymmetric_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + + return retval; +} + +sss_status_t sss_se05x_asymmetric_encrypt( + sss_se05x_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + smStatus_t status = SM_NOT_OK; + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo = se05x_get_rsa_encrypt_mode(context->algorithm); + status = Se05x_API_RSAEncrypt( + &context->session->s_ctx, context->keyObject->keyId, rsaEncryptionAlgo, srcData, srcLen, destData, destLen); + if (status == SM_OK) + retval = kStatus_SSS_Success; +#endif + return retval; +} + +sss_status_t sss_se05x_asymmetric_decrypt( + sss_se05x_asymmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + smStatus_t status = SM_NOT_OK; + + SE05x_RSAEncryptionAlgo_t rsaEncryptionAlgo = se05x_get_rsa_encrypt_mode(context->algorithm); + status = Se05x_API_RSADecrypt( + &context->session->s_ctx, context->keyObject->keyId, rsaEncryptionAlgo, srcData, srcLen, destData, destLen); + if (status == SM_OK) + retval = kStatus_SSS_Success; +#endif + return retval; +} + +sss_status_t sss_se05x_asymmetric_sign_digest( + sss_se05x_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t *signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + if (kStatus_SSS_Success != se05x_check_input_len(digestLen, context->algorithm)) { + LOG_E("Algorithm and digest length do not match"); + return kStatus_SSS_Fail; + } +#endif + + switch (context->keyObject->cipherType) { +#if SSSFTR_SE05X_ECC + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif + { + SE05x_ECSignatureAlgo_t ecSignAlgo = se05x_get_ec_sign_hash_mode(context->algorithm); + status = Se05x_API_ECDSASign(&context->session->s_ctx, + context->keyObject->keyId, + ecSignAlgo, + digest, + digestLen, + signature, + signatureLen); + } break; +#if SSS_HAVE_TPM_BN && SSS_HAVE_ECDAA + case kSSS_CipherType_EC_BARRETO_NAEHRIG: { + if (context->algorithm != kAlgorithm_SSS_ECDAA) { + return kStatus_SSS_Fail; + } + /* clang-format off */ + uint8_t random[32] = { + 0x7A, 0xCB, 0x93, 0x3D, 0xBE, 0x70, 0x39, 0x9B, 0xF6, + 0xC9, 0x2D, 0xA3, 0x3A, 0xF0, 0x1D, 0x4F, 0xB7, 0x70, + 0xE9, 0x8C, 0x03, 0x25, 0xF4, 0x1D, 0x3E, 0xBA, 0xF8, + 0x98, 0x6D, 0xA7, 0x12, 0xCA + }; + /* clang-format on */ + uint8_t raw_signature[64]; + size_t raw_signatureLen = sizeof(raw_signature); + SE05x_ECDAASignatureAlgo_t ecSignAlgo = kSE05x_ECDAASignatureAlgo_ECDAA; + sss_status_t asn_retval = kStatus_SSS_Fail; + + status = Se05x_API_ECDAASign(&context->session->s_ctx, + context->keyObject->keyId, + ecSignAlgo, + digest, + digestLen, + random, + sizeof(random), + raw_signature, + &raw_signatureLen); + if (status != SM_OK) { + LOG_E("SE050 ECDAA Sign failed"); + return kStatus_SSS_Fail; + } + + asn_retval = sss_util_asn1_ecdaa_get_signature(signature, signatureLen, raw_signature, raw_signatureLen); + if (asn_retval != kStatus_SSS_Success) { + LOG_E("SE050 ECDAA Sign failed"); + return kStatus_SSS_Fail; + } + } break; +#endif // SSS_HAVE_TPM_BN && SSS_HAVE_ECDAA +#if SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: { + LOG_W( + "Sign operation is not supported for " + "kSSS_CipherType_EC_MONTGOMERY curve"); + return kStatus_SSS_Fail; + } break; +#endif // SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT +#endif //SSSFTR_SE05X_ECC +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + if ((context->algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512) && + (context->algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1)) { + /* Perform EMSA encoding on input data and and RSA decrypt on emsa data --> RSA sign without hash */ + /* clang-format off */ + uint8_t emsa_data[512] = {0,}; /* MAX - SHA512*/ + size_t emsa_len = sizeof(emsa_data); + /* clang-format on */ + + if (0 != emsa_encode(context, digest, digestLen, emsa_data, &emsa_len)) { + return kStatus_SSS_Fail; + } + status = Se05x_API_RSADecrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + emsa_data, + emsa_len, + signature, + signatureLen); + } + else if ((context->algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512) && + (context->algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1)) { + /* Perform PKCS1-v15 encoding on input data and and RSA decrypt on PKCS1-v15 data --> RSA sign without hash */ + /* clang-format off */ + uint8_t pkcs1v15_encode_data[512] = {0,}; /* MAX - SHA512*/ + size_t encode_data_len = sizeof(pkcs1v15_encode_data); + /* clang-format on */ + + if (0 != pkcs1_v15_encode(context, digest, digestLen, pkcs1v15_encode_data, &encode_data_len)) { + return kStatus_SSS_Fail; + } + status = Se05x_API_RSADecrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + pkcs1v15_encode_data, + encode_data_len, + signature, + signatureLen); + } + else if (context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH) { + /* Perform PKCS1-v15 encoding on input data and and RSA decrypt on PKCS1-v15 data --> RSA sign without hash */ + /* clang-format off */ + uint8_t pkcs1v15_encode_data[512] = {0,}; /* MAX - SHA512*/ + size_t encode_data_len = sizeof(pkcs1v15_encode_data); + /* clang-format on */ + + if (0 != pkcs1_v15_encode_no_hash(context, digest, digestLen, pkcs1v15_encode_data, &encode_data_len)) { + return kStatus_SSS_Fail; + } + status = Se05x_API_RSADecrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + pkcs1v15_encode_data, + encode_data_len, + signature, + signatureLen); + } + else if (context->algorithm == kAlgorithm_SSS_RSASSA_NO_PADDING) { + uint8_t padded_data[512] = {0}; + size_t padded_len = sizeof(padded_data); + + size_t parsedKeyByteLen = 0; + uint16_t u16parsedKeyByteLen = 0; + status = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &u16parsedKeyByteLen); + parsedKeyByteLen = u16parsedKeyByteLen; + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + + if (digestLen <= parsedKeyByteLen && digestLen > 0) { + memset(padded_data, 0x00, padded_len); + memcpy(&padded_data[parsedKeyByteLen - digestLen], &digest[0], digestLen); + padded_len = parsedKeyByteLen; + } + else { + return kStatus_SSS_Fail; + } + status = Se05x_API_RSADecrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + padded_data, + padded_len, + signature, + signatureLen); + } + else { + LOG_E("Selected padding is not supported for RSA Sign in SE050"); + return kStatus_SSS_Fail; + } + } break; +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA + default: + break; + } + + if (status == SM_OK) { + retval = kStatus_SSS_Success; + +#if 0 // SSS_HAVE_MBEDTLS && SSSFTR_SE05X_ECC + if (context->keyObject->cipherType >= kSSS_CipherType_EC_NIST_P && + context->keyObject->cipherType < + kSSS_CipherType_EC_BARRETO_NAEHRIG) { + int ret; + /* Workaround for ECDSA signiture to omit prefix zeros if asn1 + signiutre tag (integer) length in R and S component is 20 */ + + size_t length = 0, bufIndex = 0; + ret = asn_1_parse_tlv(signature, &length, &bufIndex); + if (ret != 0) { + retval = kStatus_SSS_Fail; + return retval; + } + if (signature[bufIndex] == 0x02) /* Check for tag interger */ + { + LOG_AU8_D(signature, *signatureLen); + + int count = 0; + uint16_t i = 0; + /* For R and S component */ + for (i = 0; i < 2; i++) { + count = 0; + ret = asn_1_parse_tlv(signature, &length, &bufIndex); + if (ret != 0) { + retval = kStatus_SSS_Fail; + return retval; + } + if (length == 0x20) { + size_t j = bufIndex; + for (;; j++) { + if (signature[j] == 0 && signature[j + 1] > 0x7F) { + count++; + } + else { + break; + } + } + } + if (count) { + uint16_t k = 0; + signature[bufIndex - 1] -= + count; /* Update the tag length */ + signature[1] -= + count; /* Update the Sequence tag length */ + + for (k = 0; k < (*signatureLen - bufIndex - count); + k++) { + signature[bufIndex + k] = + signature[bufIndex + count + k]; + } + + *signatureLen -= count; + } + bufIndex += length - count; + } + } + } +#endif // SSS_HAVE_MBEDTLS && SSSFTR_SE05X_ECC + } + + return retval; +} + +sss_status_t sss_se05x_asymmetric_sign( + sss_se05x_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if (SSSFTR_SE05X_RSA && SSS_HAVE_RSA) || (SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED) + smStatus_t status = SM_NOT_OK; +#endif + + switch (context->keyObject->cipherType) { +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + SE05x_RSASignatureAlgo_t rsaSigningAlgo = se05x_get_rsa_sign_hash_mode(context->algorithm); + uint16_t key_size_bytes = 0; + + if (context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512 || + context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512) { + status = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &key_size_bytes); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + + if ((key_size_bytes * 8) == 512) { + return kStatus_SSS_Fail; + } + } + + status = Se05x_API_RSASign( + &context->session->s_ctx, context->keyObject->keyId, rsaSigningAlgo, srcData, srcLen, destData, destLen); + } break; +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA +#if SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: { + if (context->algorithm == kAlgorithm_SSS_SHA512) { + SE05x_EDSignatureAlgo_t ecSignAlgo = kSE05x_EDSignatureAlgo_ED25519PURE_SHA_512; + status = Se05x_API_EdDSASign( + &context->session->s_ctx, context->keyObject->keyId, ecSignAlgo, srcData, srcLen, destData, destLen); + } + +#ifdef TMP_ENDIAN_VERBOSE_SIGN + { + printf("Signature before Reverse:\n"); + for (size_t z = 0; z < *destLen; z++) { + printf("%02X.", destData[z]); + } + printf("\n"); + } +#endif + + // Revert Endianness + size_t offset = 0; + + for (size_t keyValueIdx = 0; keyValueIdx < (*destLen >> 2); keyValueIdx++) { + uint8_t swapByte = destData[keyValueIdx]; + destData[offset + keyValueIdx] = destData[offset + (*destLen >> 1) - 1 - keyValueIdx]; + destData[offset + (*destLen >> 1) - 1 - keyValueIdx] = swapByte; + } + + offset = *destLen >> 1; + + for (size_t keyValueIdx = 0; keyValueIdx < (*destLen >> 2); keyValueIdx++) { + uint8_t swapByte = destData[offset + keyValueIdx]; + destData[offset + keyValueIdx] = destData[offset + (*destLen >> 1) - 1 - keyValueIdx]; + destData[offset + (*destLen >> 1) - 1 - keyValueIdx] = swapByte; + } + +#ifdef TMP_ENDIAN_VERBOSE_SIGN + { + printf("Signature after Reverse:\n"); + for (size_t z = 0; z < *destLen; z++) { + printf("%02X.", destData[z]); + } + printf("\n"); + } +#endif + + } break; +#endif // SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED + default: + break; + } + +#if (SSSFTR_SE05X_RSA && SSS_HAVE_RSA) || (SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED) + // status is set only in case of RSA or ED. + if (status == SM_OK) { + retval = kStatus_SSS_Success; + } +#endif + + return retval; +} + +sss_status_t sss_se05x_asymmetric_verify_digest( + sss_se05x_asymmetric_t *context, uint8_t *digest, size_t digestLen, uint8_t *signature, size_t signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + smStatus_t status = SM_NOT_OK; + SE05x_Result_t result = kSE05x_Result_FAILURE; +#endif // SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + if (kStatus_SSS_Success != se05x_check_input_len(digestLen, context->algorithm)) { + LOG_E("Algorithm and digest length do not match"); + return kStatus_SSS_Fail; + } + + switch (context->keyObject->cipherType) { +#if SSSFTR_SE05X_ECC + case kSSS_CipherType_EC_NIST_P: +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: +#endif +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: +#endif + { + SE05x_ECSignatureAlgo_t ecSignAlgo = se05x_get_ec_sign_hash_mode(context->algorithm); + status = Se05x_API_ECDSAVerify(&context->session->s_ctx, + context->keyObject->keyId, + ecSignAlgo, + digest, + digestLen, + signature, + signatureLen, + &result); + } break; +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: { + retval = kStatus_SSS_Fail; + LOG_W("Verify not supported for BN Curve"); + } break; +#endif +#if SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: { + LOG_W( + "Verify operation is not supported for " + "kSSS_CipherType_EC_MONTGOMERY curve"); + return kStatus_SSS_Fail; + } break; +#endif // SSS_HAVE_SE05X_VER_GTE_06_00 && SSS_HAVE_EC_MONT +#endif // SSSFTR_SE05X_ECC +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + if ((context->algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512) && + (context->algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1)) { + /* clang-format off */ + uint8_t dec_data[512] = { 0, }; /* MAX - SHA512*/ + size_t dec_len = sizeof(dec_data); + /* clang-format on */ + + status = Se05x_API_RSAEncrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + signature, + signatureLen, + dec_data, + &dec_len); + + if (0 == emsa_decode_and_compare(context, dec_data, dec_len, digest, digestLen)) { + result = kSE05x_Result_SUCCESS; + } + } + else if ((context->algorithm <= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512) && + (context->algorithm >= kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1)) { + /* clang-format off */ + uint8_t dec_data[512] = { 0, }; /* MAX - SHA512*/ + size_t dec_len = sizeof(dec_data); + uint8_t pkcs1v15_encode_data[512] = { 0, }; /* MAX - SHA512*/ + size_t encode_data_len = sizeof(pkcs1v15_encode_data); + /* clang-format on */ + + status = Se05x_API_RSAEncrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + signature, + signatureLen, + dec_data, + &dec_len); + + if (0 != pkcs1_v15_encode(context, digest, digestLen, pkcs1v15_encode_data, &encode_data_len)) { + return kStatus_SSS_Fail; + } + + if (memcmp(dec_data, pkcs1v15_encode_data, encode_data_len) == 0) { + result = kSE05x_Result_SUCCESS; + } + } + else if (context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH) { + /* clang-format off */ + uint8_t dec_data[512] = { 0, }; /* MAX - SHA512*/ + size_t dec_len = sizeof(dec_data); + uint8_t pkcs1v15_encode_data[512] = { 0, }; /* MAX - SHA512*/ + size_t encode_data_len = sizeof(pkcs1v15_encode_data); + /* clang-format on */ + + status = Se05x_API_RSAEncrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + signature, + signatureLen, + dec_data, + &dec_len); + + if (0 != pkcs1_v15_encode_no_hash(context, digest, digestLen, pkcs1v15_encode_data, &encode_data_len)) { + return kStatus_SSS_Fail; + } + + if (memcmp(dec_data, pkcs1v15_encode_data, encode_data_len) == 0) { + result = kSE05x_Result_SUCCESS; + } + } + else if (context->algorithm == kAlgorithm_SSS_RSASSA_NO_PADDING) { + uint8_t dec_data[512] = { + 0, + }; /*MAX - RSA4096*/ + size_t dec_len = sizeof(dec_data); + + status = Se05x_API_RSAEncrypt(&context->session->s_ctx, + context->keyObject->keyId, + kSE05x_RSAEncryptionAlgo_NO_PAD, + signature, + signatureLen, + dec_data, + &dec_len); + + uint8_t padded_data[512] = {0}; + size_t padded_len = sizeof(padded_data); + + size_t parsedKeyByteLen = 0; + uint16_t u16parsedKeyByteLen = 0; + status = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &u16parsedKeyByteLen); + parsedKeyByteLen = u16parsedKeyByteLen; + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + + if (digestLen <= parsedKeyByteLen && digestLen > 0) { + memset(padded_data, 0x00, padded_len); + memcpy(&padded_data[parsedKeyByteLen - digestLen], &digest[0], digestLen); + padded_len = parsedKeyByteLen; + } + + else { + return kStatus_SSS_Fail; + } + + if (memcmp(&dec_data[0], &padded_data[0], padded_len) == 0) { + result = kSE05x_Result_SUCCESS; + } + } + else { + LOG_E("Selected padding is not supported for RSA Sign in SE050"); + return kStatus_SSS_Fail; + } + + } break; +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA + default: + break; + } +#endif // SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + if (status == SM_OK) { + if (result == kSE05x_Result_SUCCESS) { + retval = kStatus_SSS_Success; + } + } +#endif // SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA + + return retval; +} + +sss_status_t sss_se05x_asymmetric_verify( + sss_se05x_asymmetric_t *context, uint8_t *srcData, size_t srcLen, uint8_t *signature, size_t signatureLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if (SSSFTR_SE05X_RSA && SSS_HAVE_RSA) || (SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED) + smStatus_t status = SM_NOT_OK; + SE05x_Result_t result = kSE05x_Result_FAILURE; +#endif + + switch (context->keyObject->cipherType) { +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA + case kSSS_CipherType_RSA: + case kSSS_CipherType_RSA_CRT: { + SE05x_RSASignatureAlgo_t rsaSigningAlgo = se05x_get_rsa_sign_hash_mode(context->algorithm); + uint16_t key_size_bytes = 0; + + if (context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512 || + context->algorithm == kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512) { + status = Se05x_API_ReadSize(&context->session->s_ctx, context->keyObject->keyId, &key_size_bytes); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + + if ((key_size_bytes * 8) == 512) { + return kStatus_SSS_Fail; + } + } + + status = Se05x_API_RSAVerify(&context->session->s_ctx, + context->keyObject->keyId, + rsaSigningAlgo, + srcData, + srcLen, + signature, + signatureLen, + &result); + } break; +#endif // SSSFTR_SE05X_RSA && SSS_HAVE_RSA +#if SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: { +#ifdef TMP_ENDIAN_VERBOSE + { + printf("Signatire before Reverse:\n"); + for (size_t z = 0; z < signatureLen; z++) { + printf("%02X.", signature[z]); + } + printf("\n"); + } +#endif + + // Revert Endianness + size_t offset = 0; + + for (size_t keyValueIdx = 0; keyValueIdx < (signatureLen >> 2); keyValueIdx++) { + uint8_t swapByte = signature[keyValueIdx]; + signature[offset + keyValueIdx] = signature[offset + (signatureLen >> 1) - 1 - keyValueIdx]; + signature[offset + (signatureLen >> 1) - 1 - keyValueIdx] = swapByte; + } + + offset = signatureLen >> 1; + + for (size_t keyValueIdx = 0; keyValueIdx < (signatureLen >> 2); keyValueIdx++) { + uint8_t swapByte = signature[offset + keyValueIdx]; + signature[offset + keyValueIdx] = signature[offset + (signatureLen >> 1) - 1 - keyValueIdx]; + signature[offset + (signatureLen >> 1) - 1 - keyValueIdx] = swapByte; + } + +#ifdef TMP_ENDIAN_VERBOSE + { + printf("Signatire after Reverse:\n"); + for (size_t z = 0; z < signatureLen; z++) { + printf("%02X.", signature[z]); + } + printf("\n"); + } +#endif + + if (context->algorithm == kAlgorithm_SSS_SHA512) { + SE05x_EDSignatureAlgo_t ecSignAlgo = kSE05x_EDSignatureAlgo_ED25519PURE_SHA_512; + status = Se05x_API_EdDSAVerify(&context->session->s_ctx, + context->keyObject->keyId, + ecSignAlgo, + srcData, + srcLen, + signature, + signatureLen, + &result); + } + } break; +#endif // SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED + default: + break; + } + +#if ((SSSFTR_SE05X_RSA && SSS_HAVE_RSA) || (SSSFTR_SE05X_ECC && SSS_HAVE_EC_ED)) + // status is set only in case of RSA or ED. + if (status == SM_OK) { + if (result == kSE05x_Result_SUCCESS) { + retval = kStatus_SSS_Success; + } + } +#endif + + return retval; +} + +void sss_se05x_asymmetric_context_free(sss_se05x_asymmetric_t *context) +{ + memset(context, 0, sizeof(*context)); +} + +/* End: se05x_asym */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_symm */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_symmetric_context_init(sss_se05x_symmetric_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + context->cache_data_len = 0; + return retval; +} + +sss_status_t sss_se05x_cipher_one_go(sss_se05x_symmetric_t *context, + uint8_t *iv, + size_t ivLen, + const uint8_t *srcData, + uint8_t *destData, + size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + SE05x_CipherMode_t cipherMode = se05x_get_cipher_mode(context->algorithm); + SE05x_Cipher_Oper_OneShot_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_OneShot_Encrypt : kSE05x_Cipher_Oper_OneShot_Decrypt; + + status = Se05x_API_CipherOneShot(&context->session->s_ctx, + context->keyObject->keyId, + cipherMode, + srcData, + dataLen, + iv, + ivLen, + destData, + &dataLen, + OperType); + + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_cipher_init(sss_se05x_symmetric_t *context, uint8_t *iv, size_t ivLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + //size_t retdataLen = 0; + SE05x_Cipher_Oper_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_Encrypt : kSE05x_Cipher_Oper_Decrypt; + SE05x_CipherMode_t cipherMode = se05x_get_cipher_mode(context->algorithm); + +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + SE05x_CryptoModeSubType_t subtype; + uint8_t list[1024] = { + 0, + }; + switch (context->algorithm) { + case kAlgorithm_SSS_AES_ECB: + subtype.cipher = kSE05x_CipherMode_AES_ECB_NOPAD; + context->cryptoObjectId = kSE05x_CryptoObject_AES_ECB_NOPAD; + break; + case kAlgorithm_SSS_AES_CBC: + subtype.cipher = kSE05x_CipherMode_AES_CBC_NOPAD; + context->cryptoObjectId = kSE05x_CryptoObject_AES_CBC_NOPAD; + break; + case kAlgorithm_SSS_AES_CTR: + subtype.cipher = kSE05x_CipherMode_AES_CTR; + context->cryptoObjectId = kSE05x_CryptoObject_AES_CTR; + break; + case kAlgorithm_SSS_DES_ECB: + subtype.cipher = kSE05x_CipherMode_DES_ECB_NOPAD; + context->cryptoObjectId = kSE05x_CryptoObject_DES_ECB_NOPAD; + break; + case kAlgorithm_SSS_DES_CBC: + subtype.cipher = kSE05x_CipherMode_DES_ECB_NOPAD; + context->cryptoObjectId = kSE05x_CryptoObject_DES_CBC_NOPAD; + break; + default: + return kStatus_SSS_Fail; + } + + size_t listlen = sizeof(list); + size_t i; + uint8_t create_crypto_obj = 1; + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + create_crypto_obj = 0; + } + } + + if (create_crypto_obj) { + status = Se05x_API_CreateCryptoObject( + &context->session->s_ctx, context->cryptoObjectId, kSE05x_CryptoContext_CIPHER, subtype); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + } +#endif + + if (cipherMode == kSE05x_CipherMode_AES_ECB_NOPAD) { + ivLen = 0; + } + + status = Se05x_API_CipherInit( + &context->session->s_ctx, context->keyObject->keyId, context->cryptoObjectId, iv, ivLen, OperType); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_cipher_update( + sss_se05x_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t inputData[CIPHER_UPDATE_DATA_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + + ENSURE_OR_GO_EXIT(srcData != NULL); + ENSURE_OR_GO_EXIT(destData != NULL); + ENSURE_OR_GO_EXIT(destLen != NULL); + ENSURE_OR_GO_EXIT(srcLen > 0); + + /* Check overflow */ + ENSURE_OR_GO_EXIT((context->cache_data_len + srcLen) >= context->cache_data_len); + + if ((context->cache_data_len + srcLen) < CIPHER_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + size_t total_data = srcLen + context->cache_data_len; + const uint8_t *pSrcData = NULL; + + do { + size_t data_to_copy = (total_data > CIPHER_UPDATE_DATA_SIZE) ? (CIPHER_UPDATE_DATA_SIZE) : (total_data); + data_to_copy = data_to_copy - (data_to_copy % CIPHER_BLOCK_SIZE); + inputData_len = 0; + + if (context->cache_data_len > 0) { + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + data_to_copy = data_to_copy - context->cache_data_len; + context->cache_data_len = 0; + } + + if (inputData_len == 0) { + //if cache data is 0, directly assign the address of srcData. This will avoid the memcpy on srcData + pSrcData = (srcData + src_offset); + } + else { + memcpy((inputData + inputData_len), (srcData + src_offset), data_to_copy); + pSrcData = inputData; + } + + inputData_len = inputData_len + data_to_copy; + src_offset = src_offset + data_to_copy; + total_data = total_data - inputData_len; + + blockoutLen = outBuffSize; + ENSURE_OR_GO_EXIT(blockoutLen >= inputData_len); + status = Se05x_API_CipherUpdate(&context->session->s_ctx, + context->cryptoObjectId, + pSrcData, + inputData_len, + (destData + output_offset), + &blockoutLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + *destLen = output_offset; + + } while (srcLen - src_offset >= CIPHER_BLOCK_SIZE); + + /* Copy unprocessed data to cache */ + if ((srcLen - src_offset) > 0) { + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + } + + retval = kStatus_SSS_Success; +exit: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } + return retval; +} + +sss_status_t sss_se05x_cipher_finish( + sss_se05x_symmetric_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + context->cache_data_len = 0; + } + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + + if (context->algorithm == kAlgorithm_SSS_AES_ECB || context->algorithm == kAlgorithm_SSS_AES_CBC) { + if (srcdata_updated_len > 0) { + if (srcdata_updated_len % CIPHER_BLOCK_SIZE != 0) { + srcdata_updated_len = srcdata_updated_len + (CIPHER_BLOCK_SIZE - (srcdata_updated_len % 16)); + } + } + } + + if (*destLen < srcdata_updated_len) { + LOG_E("Output buffer not sufficient"); + goto exit; + } + + status = Se05x_API_CipherFinal( + &context->session->s_ctx, context->cryptoObjectId, srcdata_updated, srcdata_updated_len, destData, destLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_cipher_crypt_ctr(sss_se05x_symmetric_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *initialCounter, + uint8_t *lastEncryptedCounter, + size_t *szLeft) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + size_t outputDataLen = 128; + SE05x_CipherMode_t cipherMode = se05x_get_cipher_mode(context->algorithm); + SE05x_Cipher_Oper_OneShot_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_OneShot_Encrypt : kSE05x_Cipher_Oper_OneShot_Decrypt; + + status = Se05x_API_CipherOneShot(&context->session->s_ctx, + context->keyObject->keyId, + cipherMode, + srcData, + size, + initialCounter, + 16, + destData, + &outputDataLen, + OperType); + + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_se05x_symmetric_context_free(sss_se05x_symmetric_t *context) +{ +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + smStatus_t status; + uint8_t list[1024] = { + 0, + }; + uint8_t object_exists = 0; + size_t listlen = sizeof(list); + + if (context->cryptoObjectId != 0) { + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (size_t i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + object_exists = 1; + } + } + + if (object_exists) { + status = Se05x_API_DeleteCryptoObject(&context->session->s_ctx, context->cryptoObjectId); + if (status != SM_OK) { + LOG_D("Could not delete crypto object 0x04X", context->cryptoObjectId); + return; + } + } + } +#endif + memset(context, 0, sizeof(*context)); +} + +/* End: se05x_symm */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_aead */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_aead_context_init(sss_se05x_aead_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Fail; + context->session = session; + context->keyObject = keyObject; + if ((algorithm == kAlgorithm_SSS_AES_CCM) || (algorithm == kAlgorithm_SSS_AES_GCM) || + (algorithm == kAlgorithm_SSS_AES_GCM_INT_IV)) { + context->algorithm = algorithm; + } + else { + LOG_E("Improper Algorithm provided!!!"); + goto exit; + } + context->mode = mode; + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_aead_one_go(sss_se05x_aead_t *context, + const uint8_t *srcData, + uint8_t *destData, + size_t size, + uint8_t *nonce, + size_t nonceLen, + const uint8_t *aad, + size_t aadLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + smStatus_t status = SM_NOT_OK; + size_t destDataLen = size; + SE05x_CipherMode_t cipherMode = + (context->algorithm == kAlgorithm_SSS_AES_GCM) ? kSE05x_CipherMode_AES_GCM : kSE05x_CipherMode_AES_GCM_INT_IV; + SE05x_Cipher_Oper_OneShot_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_OneShot_Encrypt : kSE05x_Cipher_Oper_OneShot_Decrypt; + + status = Se05x_API_AeadOneShot(&context->session->s_ctx, + context->keyObject->keyId, + cipherMode, + srcData, + size, + aad, + aadLen, + nonce, + nonceLen, + tag, + tagLen, + destData, + &destDataLen, + OperType); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ + return retval; +} + +sss_status_t sss_se05x_aead_init( + sss_se05x_aead_t *context, uint8_t *nonce, size_t nonceLen, size_t tagLen, size_t aadLen, size_t payloadLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + smStatus_t status = SM_NOT_OK; + context->cache_data_len = 0; + SE05x_CipherMode_t cipherMode = kSE05x_CipherMode_NA; + SE05x_Cipher_Oper_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_Encrypt : kSE05x_Cipher_Oper_Decrypt; +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + SE05x_CryptoModeSubType_t subtype; + uint8_t list[1024] = { + 0, + }; + size_t listlen = sizeof(list); + size_t i; + uint8_t create_crypto_obj = 1; + + if (context->algorithm == kAlgorithm_SSS_AES_GCM) { + context->cryptoObjectId = kSE05x_CryptoObject_AES_GCM; + subtype.aead = kSE05x_AeadGCMAlgo; + } + else if (context->algorithm == kAlgorithm_SSS_AES_GCM_INT_IV) { + context->cryptoObjectId = kSE05x_CryptoObject_AES_GCM_INT_IV; + subtype.aead = kSE05x_AeadGCM_IVAlgo; + } + else if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + context->cryptoObjectId = kSE05x_CryptoObject_AES_CCM; + subtype.aead = kSE05x_AeadCCMAlgo; + } + else { + goto exit; + } + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + create_crypto_obj = 0; + } + } + + if (create_crypto_obj) { + status = Se05x_API_CreateCryptoObject( + &context->session->s_ctx, context->cryptoObjectId, kSE05x_CryptoContext_AEAD, subtype); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + } + + if (status != SM_OK) { + LOG_W("CreateCryptoObject Failed"); + return kStatus_SSS_Fail; + } +#endif + memset(context->cache_data, 0x00, sizeof(context->cache_data)); + if ((context->algorithm == (kAlgorithm_SSS_AES_GCM)) || (context->algorithm == (kAlgorithm_SSS_AES_GCM_INT_IV))) { + cipherMode = (context->algorithm == kAlgorithm_SSS_AES_GCM) ? kSE05x_CipherMode_AES_GCM : + kSE05x_CipherMode_AES_GCM_INT_IV; + status = Se05x_API_AeadInit(&context->session->s_ctx, + context->keyObject->keyId, + cipherMode, + context->cryptoObjectId, + nonce, + nonceLen, + OperType); + } + else { + status = Se05x_API_AeadCCMInit(&context->session->s_ctx, + context->keyObject->keyId, + context->cryptoObjectId, + nonce, + nonceLen, + aadLen, + payloadLen, + tagLen, + OperType); + } + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ + return retval; +} + +sss_status_t sss_se05x_aead_update_aad(sss_se05x_aead_t *context, const uint8_t *aadData, size_t aadDataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + smStatus_t status = SM_NOT_OK; + size_t src_offset = 0; + if (aadDataLen > AEAD_BLOCK_SIZE) { + while ((aadDataLen - src_offset) >= AEAD_BLOCK_SIZE) { + /*For the subsequent blocks which are of block size 16*/ + status = Se05x_API_AeadUpdate_aad( + &context->session->s_ctx, context->cryptoObjectId, (aadData + src_offset), AEAD_BLOCK_SIZE); + ENSURE_OR_GO_EXIT(status == SM_OK); + src_offset += AEAD_BLOCK_SIZE; + } + if ((aadDataLen - src_offset) > 0) { + /*For the subsequent blocks which are yet to process*/ + status = Se05x_API_AeadUpdate_aad( + &context->session->s_ctx, context->cryptoObjectId, (aadData + src_offset), (aadDataLen - src_offset)); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + } + else { + status = Se05x_API_AeadUpdate_aad(&context->session->s_ctx, context->cryptoObjectId, aadData, aadDataLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + retval = kStatus_SSS_Success; +exit: +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ + return retval; +} + +sss_status_t sss_se05x_aead_update( + sss_se05x_aead_t *context, const uint8_t *srcData, size_t srcLen, uint8_t *destData, size_t *destLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + smStatus_t status = SM_NOT_OK; + uint8_t inputData[AEAD_BLOCK_SIZE] = { + 0, + }; + size_t inputData_len = 0; + size_t src_offset = 0; + size_t output_offset = 0; + size_t outBuffSize = *destLen; + size_t blockoutLen = 0; + + if ((context->cache_data_len + srcLen) < AEAD_BLOCK_SIZE) { + /* Insufficinet data to process . Cache the data */ + memcpy((context->cache_data + context->cache_data_len), srcData, srcLen); + context->cache_data_len = context->cache_data_len + srcLen; + *destLen = 0; + return kStatus_SSS_Success; + } + else { + /* Concatenate the unprocessed and current input data*/ + memcpy(inputData, context->cache_data, context->cache_data_len); + inputData_len = context->cache_data_len; + memcpy((inputData + inputData_len), srcData, (AEAD_BLOCK_SIZE - context->cache_data_len)); + inputData_len += (AEAD_BLOCK_SIZE - context->cache_data_len); + src_offset += (AEAD_BLOCK_SIZE - context->cache_data_len); + + blockoutLen = outBuffSize; + status = Se05x_API_AeadUpdate(&context->session->s_ctx, + context->cryptoObjectId, + inputData, + inputData_len, + (destData + output_offset), + &blockoutLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + while ((srcLen - src_offset) >= AEAD_BLOCK_SIZE) { + /*For the subsequent blocks which are of block size 16*/ + memcpy(inputData, (srcData + src_offset), AEAD_BLOCK_SIZE); + src_offset += AEAD_BLOCK_SIZE; + blockoutLen = outBuffSize; + + status = Se05x_API_AeadUpdate(&context->session->s_ctx, + context->cryptoObjectId, + inputData, + inputData_len, + (destData + output_offset), + &blockoutLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + outBuffSize -= blockoutLen; + output_offset += blockoutLen; + } + *destLen = output_offset; + /* Copy unprocessed data to cache */ + memcpy(context->cache_data, (srcData + src_offset), (srcLen - src_offset)); + context->cache_data_len = (srcLen - src_offset); + } + retval = kStatus_SSS_Success; +exit: + if (retval == kStatus_SSS_Fail) { + *destLen = 0; + } +#endif /*SSS_HAVE_SE05X_VER_GTE_06_00*/ + return retval; +} + +sss_status_t sss_se05x_aead_finish(sss_se05x_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + smStatus_t status = SM_NOT_OK; + + SE05x_Cipher_Oper_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_Encrypt : kSE05x_Cipher_Oper_Decrypt; + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + + if (srcLen > CIPHER_BLOCK_SIZE) { + LOG_E("srcLen cannot be grater than 16 bytes. Call update function "); + *destLen = 0; + goto exit; + } + + if (context->algorithm == kAlgorithm_SSS_AES_CCM) { + retval = sss_se05x_aead_CCMfinish(context, srcData, srcLen, destData, destLen, tag, tagLen); + } + else { + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + } + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + if (srcdata_updated_len > 0) { + status = Se05x_API_AeadUpdate(&context->session->s_ctx, + context->cryptoObjectId, + srcdata_updated, + srcdata_updated_len, + destData, + destLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + } + else { + /* This condition will occur if all data including cache is alread processed */ + LOG_D("No Data in cache, All data are already processed"); + *destLen = 0; + } + status = Se05x_API_AeadFinal(&context->session->s_ctx, context->cryptoObjectId, tag, tagLen, OperType); + ENSURE_OR_GO_EXIT(status == SM_OK); + retval = kStatus_SSS_Success; + } +exit: +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ + return retval; +} + +#if SSS_HAVE_SE05X_VER_GTE_06_00 +static sss_status_t sss_se05x_aead_CCMfinish(sss_se05x_aead_t *context, + const uint8_t *srcData, + size_t srcLen, + uint8_t *destData, + size_t *destLen, + uint8_t *tag, + size_t *tagLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t dataprocessed = 1; + SE05x_Cipher_Oper_t OperType = + (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_Encrypt : kSE05x_Cipher_Oper_Decrypt; + uint8_t srcdata_updated[2 * CIPHER_BLOCK_SIZE] = { + 0, + }; + size_t srcdata_updated_len = 0; + size_t outLen = 0; + size_t tempoutLen = 0; + size_t destBufLen = *destLen; + + if (context->cache_data_len != 0) { + memcpy(srcdata_updated, context->cache_data, context->cache_data_len); + srcdata_updated_len = context->cache_data_len; + } + if (srcLen != 0) { + memcpy((srcdata_updated + srcdata_updated_len), srcData, srcLen); + srcdata_updated_len += srcLen; + } + if (srcdata_updated_len > 0) { + if (srcdata_updated_len < CIPHER_BLOCK_SIZE) { + status = Se05x_API_AeadCCMLastUpdate( + &context->session->s_ctx, context->cryptoObjectId, srcdata_updated, srcdata_updated_len); + ENSURE_OR_GO_EXIT(status == SM_OK); + dataprocessed = 0; + } + else if (srcdata_updated_len >= CIPHER_BLOCK_SIZE) { + tempoutLen = destBufLen - outLen; + status = Se05x_API_AeadUpdate(&context->session->s_ctx, + context->cryptoObjectId, + srcdata_updated, + CIPHER_BLOCK_SIZE, + destData, + &tempoutLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + srcdata_updated_len = srcdata_updated_len - CIPHER_BLOCK_SIZE; + outLen = outLen + tempoutLen; + + /* Put the remaining data in CCMLastUpdate if present (will always be less than CIPHER_BLOCK_SIZE) */ + if (srcdata_updated_len) { + status = Se05x_API_AeadCCMLastUpdate(&context->session->s_ctx, + context->cryptoObjectId, + srcdata_updated + CIPHER_BLOCK_SIZE, + srcdata_updated_len); + ENSURE_OR_GO_EXIT(status == SM_OK); + dataprocessed = 0; + } + } + } + else { + /* This condition will occur if all data including + cache is already processed just send final*/ + dataprocessed = 1; + } + + if (dataprocessed == 0) { + /*All data is updated, lastupdate datalen < 16 o/p + is expected here */ + tempoutLen = destBufLen - outLen; + status = Se05x_API_AeadCCMFinal( + &context->session->s_ctx, context->cryptoObjectId, (destData + outLen), &tempoutLen, tag, tagLen, OperType); + outLen = outLen + tempoutLen; + } + else { + /*All data is processed no destination data*/ + status = Se05x_API_AeadFinal(&context->session->s_ctx, context->cryptoObjectId, tag, tagLen, OperType); + } + ENSURE_OR_GO_EXIT(status == SM_OK); + retval = kStatus_SSS_Success; + *destLen = outLen; +exit: + return retval; +} +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ + +void sss_se05x_aead_context_free(sss_se05x_aead_t *context) +{ +#if SSS_HAVE_SE05X_VER_GTE_06_00 +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + smStatus_t status; + uint8_t list[1024] = { + 0, + }; + uint8_t object_exists = 0; + size_t listlen = sizeof(list); + + if (context->cryptoObjectId != 0) { + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (size_t i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + object_exists = 1; + } + } + if (object_exists) { + status = Se05x_API_DeleteCryptoObject(&context->session->s_ctx, context->cryptoObjectId); + if (status != SM_OK) { + LOG_D("Could not delete crypto object 0x04X", context->cryptoObjectId); + return; + } + } + } +#endif /* SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ */ + memset(context, 0, sizeof(*context)); +#endif /* SSS_HAVE_SE05X_VER_GTE_06_00 */ +} + +/* End: se05x_aead */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_mac */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_mac_context_init(sss_se05x_mac_t *context, + sss_se05x_session_t *session, + sss_se05x_object_t *keyObject, + sss_algorithm_t algorithm, + sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + context->session = session; + context->keyObject = keyObject; + context->algorithm = algorithm; + context->mode = mode; + return retval; +} + +sss_status_t sss_se05x_mac_one_go( + sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t *macLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + + smStatus_t status = SM_NOT_OK; + + SE05x_MACAlgo_t macOperation = se05x_get_mac_algo(context->algorithm); + + ENSURE_OR_GO_EXIT(macOperation != kSE05x_MACAlgo_NA); + + status = Se05x_API_MACOneShot_G( + &context->session->s_ctx, context->keyObject->keyId, macOperation, message, messageLen, mac, macLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_mac_validate_one_go( + sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen, uint8_t *mac, size_t macLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + SE05x_MACAlgo_t macOperation; + SE05x_Result_t result = kSE05x_Result_FAILURE; + size_t result_size = sizeof(result); + + if (context == NULL) { + goto exit; + } + + macOperation = se05x_get_mac_algo(context->algorithm); + + ENSURE_OR_GO_EXIT(macOperation != kSE05x_MACAlgo_NA); + + status = Se05x_API_MACOneShot_V(&context->session->s_ctx, + context->keyObject->keyId, + macOperation, + message, + messageLen, + mac, + macLen, + (uint8_t *)&result, + &result_size); + + if (status == SM_OK) { + if (result == kSE05x_Result_SUCCESS) { + retval = kStatus_SSS_Success; + } + } + +exit: + return retval; +} + +sss_status_t sss_se05x_mac_init(sss_se05x_mac_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + SE05x_CryptoModeSubType_t subtype; + + uint8_t list[1024] = { + 0, + }; + size_t listlen = sizeof(list); + size_t i; + uint8_t create_crypto_obj = 1; + + SE05x_CryptoContext_t cryptoContext; + + switch (context->algorithm) { + case kAlgorithm_SSS_CMAC_AES: + subtype.mac = kSE05x_MACAlgo_CMAC_128; + cryptoContext = kSE05x_CryptoContext_SIGNATURE; + context->cryptoObjectId = kSE05x_CryptoObject_CMAC_128; + break; +#if SSS_HAVE_HASH_1 + case kAlgorithm_SSS_HMAC_SHA1: + subtype.mac = kSE05x_MACAlgo_HMAC_SHA1; + cryptoContext = kSE05x_CryptoContext_SIGNATURE; + context->cryptoObjectId = kSE05x_CryptoObject_HMAC_SHA1; + break; +#endif + case kAlgorithm_SSS_HMAC_SHA256: + subtype.mac = kSE05x_MACAlgo_HMAC_SHA256; + cryptoContext = kSE05x_CryptoContext_SIGNATURE; + context->cryptoObjectId = kSE05x_CryptoObject_HMAC_SHA256; + break; + case kAlgorithm_SSS_HMAC_SHA384: + subtype.mac = kSE05x_MACAlgo_HMAC_SHA384; + cryptoContext = kSE05x_CryptoContext_SIGNATURE; + context->cryptoObjectId = kSE05x_CryptoObject_HMAC_SHA384; + break; +#if SSS_HAVE_HASH_512 + case kAlgorithm_SSS_HMAC_SHA512: + subtype.mac = kSE05x_MACAlgo_HMAC_SHA512; + cryptoContext = kSE05x_CryptoContext_SIGNATURE; + context->cryptoObjectId = kSE05x_CryptoObject_HMAC_SHA512; + break; +#endif + default: + return kStatus_SSS_Fail; + } + + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + create_crypto_obj = 0; + } + } + + if (create_crypto_obj) { + status = + Se05x_API_CreateCryptoObject(&context->session->s_ctx, context->cryptoObjectId, cryptoContext, subtype); + if (status != SM_OK) { + LOG_W("CreateCryptoObject Failed"); + return kStatus_SSS_Fail; + } + } +#endif + SE05x_Mac_Oper_t operType = kSE05x_Mac_Oper_Generate; + + status = Se05x_API_MACInit(&context->session->s_ctx, context->keyObject->keyId, context->cryptoObjectId, operType); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_mac_update(sss_se05x_mac_t *context, const uint8_t *message, size_t messageLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + + //SE05x_MACAlgo_t macOperation = se05x_get_mac_algo(context->algorithm); + + status = Se05x_API_MACUpdate(&context->session->s_ctx, message, messageLen, context->cryptoObjectId); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_mac_finish(sss_se05x_mac_t *context, uint8_t *mac, size_t *macLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + + //SE05x_MACAlgo_t macOperation = se05x_get_mac_algo(context->algorithm); + + status = Se05x_API_MACFinal(&context->session->s_ctx, NULL, 0, context->cryptoObjectId, NULL, 0, mac, macLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_se05x_mac_context_free(sss_se05x_mac_t *context) +{ + if (context->cryptoObjectId != 0) { + smStatus_t status = Se05x_API_DeleteCryptoObject(&context->session->s_ctx, context->cryptoObjectId); + if (status != SM_OK) { + LOG_D("Could not delete crypto object 0x04X", context->cryptoObjectId); + return; + } + } + memset(context, 0, sizeof(*context)); +} + +/* End: se05x_mac */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_md */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_digest_context_init( + sss_se05x_digest_t *context, sss_se05x_session_t *session, sss_algorithm_t algorithm, sss_mode_t mode) +{ + sss_status_t retval = kStatus_SSS_Success; + context->session = session; + context->algorithm = algorithm; + context->mode = mode; + return retval; +} + +sss_status_t sss_se05x_digest_one_go( + sss_se05x_digest_t *context, const uint8_t *message, size_t messageLen, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + uint8_t sha_type = se05x_get_sha_algo(context->algorithm); + + ENSURE_OR_GO_EXIT(sha_type != kSE05x_DigestMode_NA); + + status = Se05x_API_SHAOneShot(&context->session->s_ctx, sha_type, message, messageLen, digest, digestLen); + if (status != SM_OK) { + *digestLen = 0; + goto exit; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_digest_init(sss_se05x_digest_t *context) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; +#if SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ + SE05x_CryptoModeSubType_t subtype; + uint8_t list[1024] = { + 0, + }; + size_t listlen = sizeof(list); + size_t i; + uint8_t create_crypto_obj = 1; + + switch (context->algorithm) { +#if SSS_HAVE_HASH_1 + case kAlgorithm_SSS_SHA1: + subtype.digest = kSE05x_DigestMode_SHA; + context->cryptoObjectId = kSE05x_CryptoObject_DIGEST_SHA; + break; +#endif +#if SSS_HAVE_HASH_224 + case kAlgorithm_SSS_SHA224: + subtype.digest = kSE05x_DigestMode_SHA224; + context->cryptoObjectId = kSE05x_CryptoObject_DIGEST_SHA224; + break; +#endif + case kAlgorithm_SSS_SHA256: + subtype.digest = kSE05x_DigestMode_SHA256; + context->cryptoObjectId = kSE05x_CryptoObject_DIGEST_SHA256; + break; + case kAlgorithm_SSS_SHA384: + subtype.digest = kSE05x_DigestMode_SHA384; + context->cryptoObjectId = kSE05x_CryptoObject_DIGEST_SHA384; + break; +#if SSS_HAVE_HASH_512 + case kAlgorithm_SSS_SHA512: + subtype.digest = kSE05x_DigestMode_SHA512; + context->cryptoObjectId = kSE05x_CryptoObject_DIGEST_SHA512; + break; +#endif + default: + return kStatus_SSS_Fail; + } + + status = Se05x_API_ReadCryptoObjectList(&context->session->s_ctx, list, &listlen); + for (i = 0; i < listlen; i += 4) { + uint16_t cryptoObjectId = list[i + 1] | (list[i + 0] << 8); + if (cryptoObjectId == context->cryptoObjectId) { + create_crypto_obj = 0; + } + } + + if (create_crypto_obj) { + status = Se05x_API_CreateCryptoObject( + &context->session->s_ctx, context->cryptoObjectId, kSE05x_CryptoContext_DIGEST, subtype); + if (status != SM_OK) { + return kStatus_SSS_Fail; + } + } +#endif + + status = Se05x_API_DigestInit(&context->session->s_ctx, context->cryptoObjectId); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_digest_update(sss_se05x_digest_t *context, const uint8_t *message, size_t messageLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + + status = Se05x_API_DigestUpdate(&context->session->s_ctx, context->cryptoObjectId, message, messageLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_digest_finish(sss_se05x_digest_t *context, uint8_t *digest, size_t *digestLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + + status = Se05x_API_DigestFinal(&context->session->s_ctx, context->cryptoObjectId, NULL, 0, digest, digestLen); + ENSURE_OR_GO_EXIT(status == SM_OK); + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +void sss_se05x_digest_context_free(sss_se05x_digest_t *context) +{ + if (context->cryptoObjectId != 0) { + smStatus_t status = Se05x_API_DeleteCryptoObject(&context->session->s_ctx, context->cryptoObjectId); + if (status != SM_OK) { + LOG_D("Could not delete crypto object 0x04X", context->cryptoObjectId); + return; + } + } + memset(context, 0, sizeof(*context)); +} + +/* End: se05x_md */ + +/* ************************************************************************** */ +/* Functions : sss_se05x_rng */ +/* ************************************************************************** */ + +sss_status_t sss_se05x_rng_context_init(sss_se05x_rng_context_t *context, sss_se05x_session_t *session) +{ + sss_status_t retval = kStatus_SSS_Success; + context->session = session; + return retval; +} + +sss_status_t sss_se05x_rng_get_random(sss_se05x_rng_context_t *context, uint8_t *random_data, size_t dataLen) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + size_t chunk = 0; + size_t offset = 0; + + while (dataLen > 0) { + /* TODO - Replace 512 with max rsp buffer size based on with/without SCP */ + if (dataLen > 512) { + chunk = 512; + } + else { + chunk = dataLen; + } + + status = Se05x_API_GetRandom(&context->session->s_ctx, (uint16_t)chunk, (random_data + offset), &chunk); + ENSURE_OR_GO_EXIT(status == SM_OK); + + offset += chunk; + dataLen -= chunk; + } + + retval = kStatus_SSS_Success; +exit: + return retval; +} + +sss_status_t sss_se05x_rng_context_free(sss_se05x_rng_context_t *context) +{ + sss_status_t retval = kStatus_SSS_Success; + memset(context, 0, sizeof(*context)); + return retval; +} +/* End: se05x_rng */ + +sss_status_t sss_se05x_tunnel_context_init(sss_se05x_tunnel_context_t *context, sss_se05x_session_t *session) +{ + context->se05x_session = session; + sss_status_t retval = kStatus_SSS_Success; +#if USE_RTOS + context->channelLock = xSemaphoreCreateMutex(); + if (context->channelLock == NULL) { + LOG_E("xSemaphoreCreateMutex failed"); + return kStatus_SSS_Fail; + } +#elif (__GNUC__ && !AX_EMBEDDED) + if (pthread_mutex_init(&context->channelLock, NULL) != 0) { + LOG_E("\n mutex init has failed"); + return kStatus_SSS_Fail; + } + else { + LOG_D("Mutex Init successfull"); + } +#endif + return retval; +} + +sss_status_t sss_se05x_tunnel(sss_se05x_tunnel_context_t *context, + uint8_t *data, + size_t dataLen, + sss_se05x_object_t *keyObjects, + uint32_t keyObjectCount, + uint32_t tunnelType) +{ + sss_status_t retval = kStatus_SSS_Fail; + return retval; +} + +void sss_se05x_tunnel_context_free(sss_se05x_tunnel_context_t *context) +{ +#if USE_RTOS + vSemaphoreDelete(context->channelLock); +#elif (__GNUC__ && !AX_EMBEDDED) + pthread_mutex_destroy(&context->channelLock); +#endif + memset(context, 0, sizeof(*context)); +} + +static smStatus_t sss_se05x_TXn(struct Se05xSession *pSession, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle) +{ + smStatus_t ret = SM_NOT_OK; + tlvHeader_t outHdr = { + 0, + }; + uint8_t txBuf[SE05X_MAX_BUF_SIZE_CMD] = { + 0, + }; + size_t txBufLen = sizeof(txBuf); + + ret = pSession->fp_Transform(pSession, hdr, cmdBuf, cmdBufLen, &outHdr, txBuf, &txBufLen, hasle); + ENSURE_OR_GO_EXIT(ret == SM_OK); + ret = pSession->fp_RawTXn( + pSession->conn_ctx, pSession->pChannelCtx, pSession->authType, &outHdr, txBuf, txBufLen, rsp, rspLen, hasle); + + ret = pSession->fp_DeCrypt(pSession, cmdBufLen, rsp, rspLen, hasle); + + ENSURE_OR_GO_EXIT(ret == SM_OK); +exit: + return ret; +} + +static smStatus_t sss_se05x_channel_txnRaw(void *conn_ctx, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle) +{ + uint8_t txBuf[SE05X_MAX_BUF_SIZE_CMD] = {0}; + size_t i = 0; + memcpy(&txBuf[i], hdr, sizeof(*hdr)); + smStatus_t ret = SM_NOT_OK; + i += sizeof(*hdr); + if (cmdBufLen > 0) { + // The Lc field must be extended in case the length does not fit + // into a single byte (Note, while the standard would allow to + // encode 0x100 as 0x00 in the Lc field, nobody who is sane in his mind + // would actually do that). + if ((cmdBufLen < 0xFF) && !hasle) { + txBuf[i++] = (uint8_t)cmdBufLen; + } + else { + txBuf[i++] = 0x00; + txBuf[i++] = 0xFFu & (cmdBufLen >> 8); + txBuf[i++] = 0xFFu & (cmdBufLen); + } + memcpy(&txBuf[i], cmdBuf, cmdBufLen); + i += cmdBufLen; + } + else { + if (cmdBufLen == 0) { + txBuf[i++] = 0x00; + } + } + + if (hasle) { + txBuf[i++] = 0x00; + txBuf[i++] = 0x00; + } + + uint32_t U32rspLen = (uint32_t)*rspLen; + ret = (smStatus_t)smCom_TransceiveRaw(conn_ctx, txBuf, (U16)i, rsp, &U32rspLen); + *rspLen = U32rspLen; + return ret; +} + +static smStatus_t sss_se05x_channel_txn(void *conn_ctx, + struct _sss_se05x_tunnel_context *pChannelCtx, + SE_AuthType_t currAuth, + const tlvHeader_t *hdr, + uint8_t *cmdBuf, + size_t cmdBufLen, + uint8_t *rsp, + size_t *rspLen, + uint8_t hasle) +{ + smStatus_t retStatus = SM_NOT_OK; + + if ((pChannelCtx != NULL)) { +#if SSSFTR_SE05X_AuthECKey || SSSFTR_SE05X_AuthSession + struct Se05xSession *se05xCtx = (struct Se05xSession *)&pChannelCtx->se05x_session->s_ctx; + if (se05xCtx->authType == kSSS_AuthType_SCP03) { +#if USE_LOCK + LOCK_TXN(pChannelCtx->channelLock); +#endif + retStatus = se05xCtx->fp_TXn(se05xCtx, hdr, cmdBuf, cmdBufLen, rsp, rspLen, hasle); + +#if USE_LOCK + UNLOCK_TXN(pChannelCtx->channelLock); +#endif + ENSURE_OR_GO_EXIT(retStatus == SM_OK); + } + else if (se05xCtx->authType == kSSS_AuthType_None) { +#if USE_LOCK + LOCK_TXN(pChannelCtx->channelLock); +#endif + retStatus = se05xCtx->fp_TXn(se05xCtx, hdr, cmdBuf, cmdBufLen, rsp, rspLen, hasle); + +#if USE_LOCK + UNLOCK_TXN(pChannelCtx->channelLock); +#endif + ENSURE_OR_GO_EXIT(retStatus == SM_OK); + } + else { + LOG_E("Invalid auth type"); + goto exit; + } +#endif + } + else { + if (currAuth == kSSS_AuthType_SCP03) { + uint32_t u32rspLen = (uint32_t)*rspLen; + retStatus = (smStatus_t)smCom_TransceiveRaw(conn_ctx, cmdBuf, (uint16_t)cmdBufLen, rsp, &u32rspLen); + ENSURE_OR_GO_EXIT(retStatus == SM_OK); + *rspLen = u32rspLen; + } + else { + retStatus = sss_se05x_channel_txnRaw(conn_ctx, hdr, cmdBuf, cmdBufLen, rsp, rspLen, hasle); + ENSURE_OR_GO_EXIT(retStatus == SM_OK); + } + } + +exit: + return retStatus; +} + +/* End: se05x_tunnel */ + +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +sss_status_t sss_se05x_key_store_create_curve(Se05xSession_t *pSession, uint32_t curve_id) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + + status = sss_se05x_create_curve_if_needed(pSession, curve_id); + + if (SM_OK == status) + retval = kStatus_SSS_Success; + + return retval; +} +#endif + +sss_status_t sss_se05x_set_feature( + sss_se05x_session_t *session, SE05x_Applet_Feature_t feature, SE05x_Applet_Feature_Disable_t disable_features) +{ + sss_status_t retval = kStatus_SSS_Fail; + smStatus_t status = SM_NOT_OK; + Se05x_AppletFeatures_t applet_features = { kSE05x_AppletConfig_NA,NULL }; + applet_features.extended_features = NULL; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + SE05x_ExtendedFeatures_t extended = {0}; +#endif + + if (session == NULL) + goto exit; + +#if SSS_HAVE_SE05X_VER_GTE_06_00 + + /** Disable feature ECDH B2b8 */ + if (disable_features.EXTCFG_FORBID_ECDH == 1) + extended.features[1] |= 0x80; // 8th bit + /** Disable feature ECDAA B2b7 */ + if (disable_features.EXTCFG_FORBID_ECDAA == 1) + extended.features[1] |= 0x40; // 7th bit + /** Disable feature RSA_LT_2K B6b8 */ + if (disable_features.EXTCFG_FORBID_RSA_LT_2K == 1) + extended.features[5] |= 0x80; // 8th bit + /** Disable feature RSA_SHA1 B6b7 */ + if (disable_features.EXTCFG_FORBID_RSA_SHA1 == 1) + extended.features[5] |= 0x40; // 7th bit + /** Disable feature AES_GCM B8b8 */ + if (disable_features.EXTCFG_FORBID_AES_GCM == 1) + extended.features[7] |= 0x80; // 8th bit + /** Disable feature AES_GCM_EXT_IV B8b7 */ + if (disable_features.EXTCFG_FORBID_AES_GCM_EXT_IV == 1) + extended.features[7] |= 0x40; // 7th bit + /** Disable feature HKDF_EXTRACT B10b7 */ + if (disable_features.EXTCFG_FORBID_HKDF_EXTRACT == 1) + extended.features[9] |= 0x40; // 7th bit + + applet_features.extended_features = &extended; +#endif + + if (feature.AppletConfig_ECDAA == 1) + applet_features.variant |= kSE05x_AppletConfig_ECDAA; + else if (feature.AppletConfig_ECDSA_ECDH_ECDHE == 1) + applet_features.variant |= kSE05x_AppletConfig_ECDSA_ECDH_ECDHE; + else if (feature.AppletConfig_EDDSA == 1) + applet_features.variant |= kSE05x_AppletConfig_EDDSA; + else if (feature.AppletConfig_DH_MONT == 1) + applet_features.variant |= kSE05x_AppletConfig_DH_MONT; + else if (feature.AppletConfig_HMAC == 1) + applet_features.variant |= kSE05x_AppletConfig_HMAC; + else if (feature.AppletConfig_RSA_PLAIN == 1) + applet_features.variant |= kSE05x_AppletConfig_RSA_PLAIN; + else if (feature.AppletConfig_RSA_CRT == 1) + applet_features.variant |= kSE05x_AppletConfig_RSA_CRT; + else if (feature.AppletConfig_AES == 1) + applet_features.variant |= kSE05x_AppletConfig_AES; + else if (feature.AppletConfig_DES == 1) + applet_features.variant |= kSE05x_AppletConfig_DES; + else if (feature.AppletConfig_PBKDF == 1) + applet_features.variant |= kSE05x_AppletConfig_PBKDF; + else if (feature.AppletConfig_TLS == 1) + applet_features.variant |= kSE05x_AppletConfig_TLS; + else if (feature.AppletConfig_MIFARE == 1) + applet_features.variant |= kSE05x_AppletConfig_MIFARE; + else if (feature.AppletConfig_I2CM == 1) + applet_features.variant |= kSE05x_AppletConfig_I2CM; + else + goto exit; + + status = Se05x_API_SetAppletFeatures(&session->s_ctx, &applet_features); + + if (status == SM_OK) { + retval = kStatus_SSS_Success; + } + +exit: + return retval; +} + +#if SSSFTR_SE05X_AuthSession +static smStatus_t se05x_CreateVerifyUserIDSession( + pSe05xSession_t se05xSession, const uint32_t auth_id, SE05x_AuthCtx_ID_t *userId, pSe05xPolicy_t policy) +{ + sss_status_t retval = kStatus_SSS_Fail; + SE05x_Result_t exists = kSE05x_Result_FAILURE; + smStatus_t status = SM_NOT_OK; + size_t sessionIdLen = 8; + uint8_t keyVal[60]; + size_t keyValLen = sizeof(keyVal); + size_t keyBitLen = sizeof(keyVal) * 8; + + /* Check if Object exists only if auth_id is non kSE05x_AppletResID_TRANSPORT */ + /* CheckObjectExists returns 6985 SE05x if transport is Locked */ + if (auth_id == kSE05x_AppletResID_TRANSPORT) { + status = SM_OK; + LOG_D("Create Session with kSE05x_AppletResID_TRANSPORT"); + } + else { + status = Se05x_API_CheckObjectExists(se05xSession, auth_id, &exists); + if (status == SM_OK && exists == kSE05x_Result_FAILURE) { + status = SM_NOT_OK; + LOG_E("UserID is not Provisioned!!!"); + } + } + if (status == SM_OK) { + status = Se05x_API_CreateSession(se05xSession, auth_id, se05xSession->value, &sessionIdLen); + } + if (status == SM_OK) { + status = SM_NOT_OK; + retval = sss_host_key_store_get_key(userId->pObj->keyStore, userId->pObj, keyVal, &keyValLen, &keyBitLen); + + if (keyValLen < 4) { + LOG_W("User ID cannot be less than 4 bytes"); + return SM_NOT_OK; + } + + if (retval == kStatus_SSS_Success) { + se05xSession->hasSession = 1; + status = Se05x_API_VerifySessionUserID(se05xSession, keyVal, keyValLen); + if (status == SM_OK) { + if (policy->value > 0) { + status = SM_NOT_OK; + status = Se05x_API_ExchangeSessionData(se05xSession, policy); + } + } + } + } + return status; +} +#endif + +#if SSS_HAVE_SCP_SCP03_SSS +#if SSSFTR_SE05X_AuthSession +static smStatus_t se05x_CreateVerifyAESKeySession( + pSe05xSession_t se05xSession, const uint32_t auth_id, NXSCP03_AuthCtx_t *pAppletSCPCtx) +{ + SE05x_Result_t exists = kSE05x_Result_FAILURE; + smStatus_t status = SM_NOT_OK; + size_t sessionIdLen = 8; + sss_status_t retval = kStatus_SSS_Fail; + + if (auth_id == kSE05x_AppletResID_TRANSPORT) { + /* SKIP */ + /* If there's a transport lock, Se05x_API_CheckObjectExists would fail. */ + status = SM_OK; + } + else { + status = Se05x_API_CheckObjectExists(se05xSession, auth_id, &exists); + if (status == SM_OK && exists == kSE05x_Result_FAILURE) { + status = SM_NOT_OK; + LOG_E("Applet key is not Provisioned!!!"); + } + } + if (status == SM_OK) { + status = Se05x_API_CreateSession(se05xSession, auth_id, se05xSession->value, &sessionIdLen); + if (status != SM_OK) { + se05xSession->hasSession = 0; + } + else { + se05xSession->hasSession = 1; + se05xSession->authType = kSSS_AuthType_AESKey; + retval = nxScp03_AuthenticateChannel(se05xSession, pAppletSCPCtx); + if (retval == kStatus_SSS_Success) { + pAppletSCPCtx->pDyn_ctx->authType = kSSS_AuthType_AESKey; + se05xSession->pdynScp03Ctx = pAppletSCPCtx->pDyn_ctx; + status = SM_OK; + } + else { + status = SM_NOT_OK; + } + } + } + return status; +} +#endif + +#if SSSFTR_SE05X_AuthECKey +static smStatus_t se05x_CreateECKeySession( + pSe05xSession_t se05xSession, const uint32_t auth_id, SE05x_AuthCtx_ECKey_t *pFScpCtx) +{ + sss_status_t retval = kStatus_SSS_Fail; + SE05x_Result_t exists = kSE05x_Result_FAILURE; + smStatus_t status = SM_NOT_OK; + size_t sessionIdLen = 8; + + status = Se05x_API_CheckObjectExists(se05xSession, auth_id, &exists); + if (status == SM_OK && exists == kSE05x_Result_FAILURE) { + status = SM_NOT_OK; + LOG_E("SE ECDSA Public Key is not Provisioned!!!"); + } + if (status == SM_OK) { + status = Se05x_API_CreateSession(se05xSession, auth_id, se05xSession->value, &sessionIdLen); + if (status != SM_OK) { + se05xSession->hasSession = 0; + } + else { + status = SM_NOT_OK; + se05xSession->hasSession = 1; + retval = nxECKey_AuthenticateChannel(se05xSession, pFScpCtx); + if (retval == kStatus_SSS_Success) { + NXSCP03_DynCtx_t *pDyn_ctx = pFScpCtx->pDyn_ctx; + + pDyn_ctx->authType = se05xSession->authType = kSSS_AuthType_ECKey; + se05xSession->pdynScp03Ctx = pFScpCtx->pDyn_ctx; + status = SM_OK; + } + } + } + return status; +} +#endif /* SSSFTR_SE05X_AuthECKey */ +#endif + +#if SSSFTR_SE05X_ECC || SSSFTR_SE05X_RSA +static sss_status_t se05x_check_input_len(size_t inLen, sss_algorithm_t algorithm) +{ + sss_status_t retval = kStatus_SSS_Fail; + + switch (algorithm) { + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_ECDSA_SHA1: +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: +#endif + retval = (inLen == 20) ? kStatus_SSS_Success : kStatus_SSS_Fail; + break; + case kAlgorithm_SSS_SHA224: + case kAlgorithm_SSS_ECDSA_SHA224: +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: +#endif + retval = (inLen == 28) ? kStatus_SSS_Success : kStatus_SSS_Fail; + break; + case kAlgorithm_SSS_SHA256: +#if SSS_HAVE_ECDAA + case kAlgorithm_SSS_ECDAA: +#endif + case kAlgorithm_SSS_ECDSA_SHA256: +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: +#endif + retval = (inLen == 32) ? kStatus_SSS_Success : kStatus_SSS_Fail; + break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_ECDSA_SHA384: +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: +#endif + retval = (inLen == 48) ? kStatus_SSS_Success : kStatus_SSS_Fail; + break; + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_ECDSA_SHA512: +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: +#endif + retval = (inLen == 64) ? kStatus_SSS_Success : kStatus_SSS_Fail; + break; +#if SSS_HAVE_RSA + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_NO_HASH: + case kAlgorithm_SSS_RSASSA_NO_PADDING: + retval = kStatus_SSS_Success; + break; +#endif + default: + LOG_E("Unkown algorithm"); + retval = kStatus_SSS_Fail; + } + return retval; +} +#endif + +static SE05x_ECSignatureAlgo_t se05x_get_ec_sign_hash_mode(sss_algorithm_t algorithm) +{ + SE05x_ECSignatureAlgo_t mode; + switch (algorithm) { + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_ECDSA_SHA1: + mode = kSE05x_ECSignatureAlgo_SHA; + break; + case kAlgorithm_SSS_SHA224: + case kAlgorithm_SSS_ECDSA_SHA224: + mode = kSE05x_ECSignatureAlgo_SHA_224; + break; + case kAlgorithm_SSS_SHA256: + case kAlgorithm_SSS_ECDSA_SHA256: + mode = kSE05x_ECSignatureAlgo_SHA_256; + break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_ECDSA_SHA384: + mode = kSE05x_ECSignatureAlgo_SHA_384; + break; + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_ECDSA_SHA512: + mode = kSE05x_ECSignatureAlgo_SHA_512; + break; + default: + mode = kSE05x_ECSignatureAlgo_PLAIN; + break; + } + return mode; +} + +#if SSSFTR_SE05X_RSA && SSS_HAVE_RSA +static SE05x_RSAEncryptionAlgo_t se05x_get_rsa_encrypt_mode(sss_algorithm_t algorithm) +{ + SE05x_RSAEncryptionAlgo_t mode; + switch (algorithm) { + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA1: + mode = kSE05x_RSAEncryptionAlgo_PKCS1_OAEP; + break; + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA224: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA256: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA384: + case kAlgorithm_SSS_RSAES_PKCS1_OAEP_SHA512: + mode = kSE05x_RSAEncryptionAlgo_NA; + break; + case kAlgorithm_SSS_RSAES_PKCS1_V1_5: + mode = kSE05x_RSAEncryptionAlgo_PKCS1; + break; + default: + mode = kSE05x_RSAEncryptionAlgo_NO_PAD; + break; + } + return mode; +} + +static SE05x_RSASignatureAlgo_t se05x_get_rsa_sign_hash_mode(sss_algorithm_t algorithm) +{ + SE05x_RSASignatureAlgo_t mode; + switch (algorithm) { + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA1: + mode = kSE05x_RSASignatureAlgo_SHA1_PKCS1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA224: + mode = kSE05x_RSASignatureAlgo_SHA_224_PKCS1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA256: + mode = kSE05x_RSASignatureAlgo_SHA_256_PKCS1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA384: + mode = kSE05x_RSASignatureAlgo_SHA_384_PKCS1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_V1_5_SHA512: + mode = kSE05x_RSASignatureAlgo_SHA_512_PKCS1; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA1: + mode = kSE05x_RSASignatureAlgo_SHA1_PKCS1_PSS; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA224: + mode = kSE05x_RSASignatureAlgo_SHA224_PKCS1_PSS; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA256: + mode = kSE05x_RSASignatureAlgo_SHA256_PKCS1_PSS; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA384: + mode = kSE05x_RSASignatureAlgo_SHA384_PKCS1_PSS; + break; + case kAlgorithm_SSS_RSASSA_PKCS1_PSS_MGF1_SHA512: + mode = kSE05x_RSASignatureAlgo_SHA512_PKCS1_PSS; + break; + default: + mode = kSE05x_RSASignatureAlgo_NA; + } + return mode; +} +#endif // SSSFTR_SE05X_RSA + +static SE05x_CipherMode_t se05x_get_cipher_mode(sss_algorithm_t algorithm) +{ + SE05x_CipherMode_t mode; + switch (algorithm) { + case kAlgorithm_SSS_AES_ECB: + mode = kSE05x_CipherMode_AES_ECB_NOPAD; + break; + case kAlgorithm_SSS_DES_ECB: + mode = kSE05x_CipherMode_DES_ECB_NOPAD; + break; + case kAlgorithm_SSS_AES_CBC: + mode = kSE05x_CipherMode_AES_CBC_NOPAD; + break; + case kAlgorithm_SSS_DES_CBC: + mode = kSE05x_CipherMode_DES_CBC_NOPAD; + break; + case kAlgorithm_SSS_AES_CTR: + mode = kSE05x_CipherMode_AES_CTR; + break; + default: + mode = 0; + } + return mode; +} + +SE05x_MACAlgo_t se05x_get_mac_algo(sss_algorithm_t algorithm) +{ + SE05x_MACAlgo_t mode; + switch (algorithm) { + case kAlgorithm_SSS_CMAC_AES: + mode = kSE05x_MACAlgo_CMAC_128; + break; +#if SSS_HAVE_HASH_1 + case kAlgorithm_SSS_HMAC_SHA1: + mode = kSE05x_MACAlgo_HMAC_SHA1; + break; +#endif + case kAlgorithm_SSS_HMAC_SHA256: + mode = kSE05x_MACAlgo_HMAC_SHA256; + break; + case kAlgorithm_SSS_HMAC_SHA384: + mode = kSE05x_MACAlgo_HMAC_SHA384; + break; +#if SSS_HAVE_HASH_512 + case kAlgorithm_SSS_HMAC_SHA512: + mode = kSE05x_MACAlgo_HMAC_SHA512; + break; +#endif + default: + mode = kSE05x_MACAlgo_NA; + } + return mode; +} + +SE05x_DigestMode_t se05x_get_sha_algo(sss_algorithm_t algorithm) +{ + SE05x_DigestMode_t sha_type; + + switch (algorithm) { +#if SSS_HAVE_HASH_1 + case kAlgorithm_SSS_SHA1: + case kAlgorithm_SSS_HMAC_SHA1: + sha_type = kSE05x_DigestMode_SHA; + break; +#endif +#if SSS_HAVE_HASH_224 + case kAlgorithm_SSS_SHA224: + sha_type = kSE05x_DigestMode_SHA224; + break; +#endif + case kAlgorithm_SSS_SHA256: + case kAlgorithm_SSS_HMAC_SHA256: + sha_type = kSE05x_DigestMode_SHA256; + break; + case kAlgorithm_SSS_SHA384: + case kAlgorithm_SSS_HMAC_SHA384: + sha_type = kSE05x_DigestMode_SHA384; + break; +#if SSS_HAVE_HASH_512 + case kAlgorithm_SSS_SHA512: + case kAlgorithm_SSS_HMAC_SHA512: + sha_type = kSE05x_DigestMode_SHA512; + break; +#endif + default: + sha_type = 0x00; + } + + return sha_type; +} +//////////////////////////////////////////////////////////////////////// +#if SSSFTR_SE05X_ECC && SSSFTR_SE05X_KEY_SET +static smStatus_t sss_se05x_LL_set_ec_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_ECCurve_t curveID, + const uint8_t *privKey, + size_t privKeyLen, + const uint8_t *pubKey, + size_t pubKeyLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + SE05x_Result_t obj_exists) +{ + smStatus_t status = SM_NOT_OK; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + fp_Ec_KeyWrite_t fpEcKey_Ver = NULL; + /* Call APIs For SE051 */ + if (obj_exists == kSE05x_Result_FAILURE) { + fpEcKey_Ver = &Se05x_API_WriteECKey_Ver; + } + else if (obj_exists == kSE05x_Result_SUCCESS) { + fpEcKey_Ver = &Se05x_API_UpdateECKey_Ver; + } + + if (fpEcKey_Ver != NULL) { + status = fpEcKey_Ver(session_ctx, + policy, + maxAttempt, + objectID, + curveID, + privKey, + privKeyLen, + pubKey, + pubKeyLen, + ins_type, + key_part, + 0); + } + else { + LOG_E("Invalid Object exist status!!!"); + } + +#else + /* Call APIs For SE050 */ + status = Se05x_API_WriteECKey( + session_ctx, policy, maxAttempt, objectID, curveID, privKey, privKeyLen, pubKey, pubKeyLen, ins_type, key_part); +#endif + return status; +} +#endif //SSSFTR_SE05X_ECC + +#if SSSFTR_SE05X_KEY_SET +static smStatus_t sss_se05x_LL_set_symm_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + SE05x_MaxAttemps_t maxAttempt, + uint32_t objectID, + SE05x_KeyID_t kekID, + const uint8_t *keyValue, + size_t keyValueLen, + const SE05x_INS_t ins_type, + const SE05x_SymmKeyType_t type, + SE05x_Result_t obj_exists) +{ + smStatus_t status = SM_NOT_OK; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + fp_Symm_KeyWrite_t fpSymmKey_Ver = NULL; + /* Call APIs For SE051 */ + if (obj_exists == kSE05x_Result_FAILURE) { + fpSymmKey_Ver = &Se05x_API_WriteSymmKey_Ver; + } + else if (obj_exists == kSE05x_Result_SUCCESS) { + fpSymmKey_Ver = &Se05x_API_UpdateSymmKey_Ver; + } + + if (fpSymmKey_Ver != NULL) { + status = (*fpSymmKey_Ver)( + session_ctx, policy, maxAttempt, objectID, kekID, keyValue, keyValueLen, ins_type, type, 0); + } + else { + LOG_E("Invalid Object exist status!!!"); + } +#else + /* Call APIs For SE050 */ + status = + Se05x_API_WriteSymmKey(session_ctx, policy, maxAttempt, objectID, kekID, keyValue, keyValueLen, ins_type, type); +#endif + return status; +} +#endif //SSSFTR_SE05X_AES && SSSFTR_SE05X_KEY_SET + +#if SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET && SSS_HAVE_RSA +static smStatus_t sss_se05x_LL_set_RSA_key(pSe05xSession_t session_ctx, + pSe05xPolicy_t policy, + uint32_t objectID, + uint16_t size, + const uint8_t *p, + size_t pLen, + const uint8_t *q, + size_t qLen, + const uint8_t *dp, + size_t dpLen, + const uint8_t *dq, + size_t dqLen, + const uint8_t *qInv, + size_t qInvLen, + const uint8_t *pubExp, + size_t pubExpLen, + const uint8_t *priv, + size_t privLen, + const uint8_t *pubMod, + size_t pubModLen, + const SE05x_INS_t ins_type, + const SE05x_KeyPart_t key_part, + const SE05x_RSAKeyFormat_t rsa_format, + SE05x_Result_t obj_exists) +{ + smStatus_t status = SM_NOT_OK; +#if SSS_HAVE_SE05X_VER_GTE_06_00 + fp_RSA_KeyWrite_t fpRSAKey_Ver = NULL; + /* Call APIs For SE051 */ + if (obj_exists == kSE05x_Result_FAILURE) { + fpRSAKey_Ver = &Se05x_API_WriteRSAKey_Ver; + } + else if (obj_exists == kSE05x_Result_SUCCESS) { + fpRSAKey_Ver = &Se05x_API_UpdateRSAKey_Ver; + } + + if (fpRSAKey_Ver != NULL) { + status = (*fpRSAKey_Ver)(session_ctx, + policy, + objectID, + size, + p, + pLen, + q, + qLen, + dp, + dpLen, + dq, + dqLen, + qInv, + qInvLen, + pubExp, + pubExpLen, + priv, + privLen, + pubMod, + pubModLen, + ins_type, + key_part, + rsa_format, + 0); + } + else { + LOG_E("Invalid Object exist status!!!"); + } +#else + /* Call APIs For SE050 */ + status = Se05x_API_WriteRSAKey(session_ctx, + policy, + objectID, + size, + p, + pLen, + q, + qLen, + dp, + dpLen, + dq, + dqLen, + qInv, + qInvLen, + pubExp, + pubExpLen, + priv, + privLen, + pubMod, + pubModLen, + ins_type, + key_part, + rsa_format); +#endif + return status; +} +#endif //SSSFTR_SE05X_RSA && SSSFTR_SE05X_KEY_SET + +#ifdef __cplusplus +} +#endif + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c new file mode 100644 index 00000000000..632786dffd6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c @@ -0,0 +1,534 @@ +/* Copyright 2019,2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ + +#if defined(FLOW_VERBOSE) +#define NX_LOG_ENABLE_SCP_DEBUG 1 +#endif + +#include + +#if SSS_HAVE_APPLET_SE05X_IOT +#if SSS_HAVE_SCP_SCP03_SSS && SSSFTR_SE05X_AuthECKey + +#include +#include +#include +#include +#include +#include +#include +#include +#if SSS_HAVE_MBEDTLS +#include "fsl_sss_mbedtls_types.h" +#elif SSS_HAVE_OPENSSL +#include "fsl_sss_openssl_types.h" +#endif + +/* ************************************************************************** */ +/* Functions : Private function declaration */ +/* ************************************************************************** */ +static sss_status_t nxECKey_InternalAuthenticate(pSe05xSession_t se05xSession, + SE05x_AuthCtx_ECKey_t *pAuthFScp, + uint8_t *hostEckaPubKey, + size_t hostEckaPubKeyLen, + uint8_t *rndData, + size_t *rndDataLen, + uint8_t *receipt, + size_t *receiptLen); + +static sss_status_t nxECKey_calculate_master_secret( + SE05x_AuthCtx_ECKey_t *pAuthFScp, uint8_t *rnd, size_t rndLen, uint8_t *sharedSecret, size_t sharedSecretLen); + +static sss_status_t nxECKey_HostLocal_CalculateSessionKeys(SE05x_AuthCtx_ECKey_t *pAuthFScp); + +static sss_status_t nxECKey_Calculate_Initial_Mac_Chaining_Value(SE05x_AuthCtx_ECKey_t *pAuthFScp); + +static sss_status_t nxECKey_Calculate_Shared_secret( + SE05x_AuthCtx_ECKey_t *pAuthFScp, uint8_t *sharedSecret, size_t *sharedSecretLen); + +#define TAG_PK_SE_ECKA 0x7F49 +#define TAG_SIG_SE_ECKA 0x5F37 +static sss_status_t nxECKey_GetVerify_SE_Ecka_Public( + pSe05xSession_t se05xSession, uint8_t *pSePubEcka, size_t *pSePubEckaLen); + +static void set_secp256r1nist_header(uint8_t *pbKey, size_t *pbKeyByteLen); + +int get_u8buf_2bTag(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, uint16_t tag, uint8_t *rsp, size_t *pRspLen); + +/* ************************************************************************** */ +/* Functions : Function definition */ +/* ************************************************************************** */ + +sss_status_t nxECKey_AuthenticateChannel(pSe05xSession_t se05xSession, SE05x_AuthCtx_ECKey_t *pAuthFScp) +{ + sss_status_t status = kStatus_SSS_Fail; + // Host public key to send to the SE for internal authenticate + uint8_t hostEckaPub[100]; + size_t hostEckaPubLen = sizeof(hostEckaPub); + size_t hostEckabitLen; + // Random bytes to retrive from SE in internal authenticate + uint8_t drSE[20]; + size_t drSELen = sizeof(drSE); + uint8_t receipt[16]; + size_t receiptLen = sizeof(receipt); + uint8_t shsSecret[32]; + size_t shsSecretLen = sizeof(shsSecret); + size_t offset = 0; + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthFScp->pDyn_ctx; + uint8_t sePubkey[150] = { + 0, + }; // SE ECKA Public Key + size_t sePubkeyLen = sizeof(sePubkey); + uint8_t *pkSeEcka; + + /* clang-format off */ + const uint8_t commandCounter[16] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; + /* clang-format on */ + + /* Get the Host ephemeral key */ + uint8_t hostPubkey[100]; + status = sss_host_key_store_get_key( + pStatic_ctx->HostEcKeypair.keyStore, &pStatic_ctx->HostEcKeypair, hostPubkey, &hostEckaPubLen, &hostEckabitLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Get Ecc public key in the plain form required for Security Storage + * according to GPCS Ammendment E For ECC Nist 256 key + */ + hostEckaPub[offset++] = GPCS_KEY_TYPE_ECC_NIST256; //Tag EC public key + hostEckaPub[offset++] = 0x41; // public key len + memcpy( + hostEckaPub + offset, hostPubkey + ASN_ECC_NIST_256_HEADER_LEN, hostEckaPubLen - ASN_ECC_NIST_256_HEADER_LEN); + offset += hostEckaPubLen - ASN_ECC_NIST_256_HEADER_LEN; + hostEckaPub[offset++] = KEY_PARAMETER_REFERENCE_TAG; + hostEckaPub[offset++] = KEY_PARAMETER_REFERENCE_VALUE_LEN; + hostEckaPub[offset++] = KEY_PARAMETER_REFERENCE_VALUE; + hostEckaPubLen = offset; + + /* Get SE ECKA Public Key*/ + status = nxECKey_GetVerify_SE_Ecka_Public(se05xSession, sePubkey, &sePubkeyLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Create the Key in ASN1 Der format */ + pkSeEcka = &sePubkey[2]; // Exclude first two bytes Tag and len + sePubkeyLen = sePubkeyLen - 2; + set_secp256r1nist_header(pkSeEcka, &sePubkeyLen); + sePubkeyLen = sePubkeyLen - 2; // Exclude last three bytes Key parameter tag len and value + /*Set the key in Fast scp Host context*/ + status = sss_host_key_store_set_key( + pStatic_ctx->SeEcPubKey.keyStore, &pStatic_ctx->SeEcPubKey, pkSeEcka, sePubkeyLen, 256, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = nxECKey_InternalAuthenticate( + se05xSession, pAuthFScp, hostEckaPub, hostEckaPubLen, drSE, &drSELen, receipt, &receiptLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /*Calculate the Shared Secret */ + status = nxECKey_Calculate_Shared_secret(pAuthFScp, shsSecret, &shsSecretLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /*Erase the host key pair as it is no longer needed*/ + memset(hostEckaPub, 0, sizeof(hostEckaPub)); + memset(hostPubkey, 0, sizeof(hostPubkey)); + sss_key_object_free(&pStatic_ctx->HostEcKeypair); + + status = nxECKey_calculate_master_secret(pAuthFScp, drSE, drSELen, shsSecret, shsSecretLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = nxECKey_HostLocal_CalculateSessionKeys(pAuthFScp); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + /* Increment the command Encreption counter to 1*/ + memcpy(pDyn_ctx->cCounter, commandCounter, AES_KEY_LEN_nBYTE); + + /* compute the initial MAC chaining value */ + status = nxECKey_Calculate_Initial_Mac_Chaining_Value(pAuthFScp); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + pDyn_ctx->SecurityLevel = (uint8_t)SECURITY_LEVEL; +exit: + return status; +} + +static sss_status_t nxECKey_Calculate_Initial_Mac_Chaining_Value(SE05x_AuthCtx_ECKey_t *pAuthFScp) +{ + sss_status_t status = kStatus_SSS_Fail; + uint8_t ddA[128]; + uint16_t ddALen = sizeof(ddA); + uint8_t iniMacChaining[AES_KEY_LEN_nBYTE]; + uint32_t signatureLen = AES_KEY_LEN_nBYTE; + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthFScp->pDyn_ctx; + + // Set the Derviation data + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_INITIAL_MCV, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, NULL, 0); + // Calculate the Initial MCV value + status = nxScp03_Generate_SessionKey(&pStatic_ctx->masterSec, ddA, ddALen, iniMacChaining, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D("Initial MCV", iniMacChaining, AES_KEY_LEN_nBYTE); + // Set the Initial MCV value + memcpy(pDyn_ctx->MCV, iniMacChaining, AES_KEY_LEN_nBYTE); +exit: + return status; +} + +static sss_status_t nxECKey_HostLocal_CalculateSessionKeys(SE05x_AuthCtx_ECKey_t *pAuthFScp) +{ + sss_status_t status = kStatus_SSS_Fail; + uint8_t ddA[128]; + uint16_t ddALen = sizeof(ddA); + uint8_t sessionEncKey[AES_KEY_LEN_nBYTE]; + uint8_t sessionMacKey[AES_KEY_LEN_nBYTE]; + uint8_t sessionRmacKey[AES_KEY_LEN_nBYTE]; + uint32_t signatureLen = AES_KEY_LEN_nBYTE; + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthFScp->pDyn_ctx; + + /* Generation and Creation of Session ENC SSS Key Object */ + + // Set the Derviation data + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SENC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, NULL, 0); + // Calculate the Session-ENC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->masterSec, ddA, ddALen, sessionEncKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D("sessionEncKey", sessionEncKey, AES_KEY_LEN_nBYTE); + // Set the Session-ENC key + status = sss_host_key_store_set_key(pDyn_ctx->Enc.keyStore, &pDyn_ctx->Enc, sessionEncKey, 16, (16) * 8, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Generation and Creation of Session MAC SSS Key Object */ + + // Set the Derviation data + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SMAC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, NULL, 0); + // Calculate the Session-MAC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->masterSec, ddA, ddALen, sessionMacKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D("sessionMacKey", sessionMacKey, AES_KEY_LEN_nBYTE); + // Set the Session-MAC key + status = sss_host_key_store_set_key(pDyn_ctx->Mac.keyStore, &pDyn_ctx->Mac, sessionMacKey, 16, (16) * 8, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Generation and Creation of Session RMAC SSS Key Object */ + + // Set the Derviation data + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SRMAC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, NULL, 0); + // Calculate the Session-RMAC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->masterSec, ddA, ddALen, sessionRmacKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D("sessionRmacKey", sessionRmacKey, AES_KEY_LEN_nBYTE); + // Set the Session-RMAC key + status = + sss_host_key_store_set_key(pDyn_ctx->Rmac.keyStore, &pDyn_ctx->Rmac, sessionRmacKey, 16, (16) * 8, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); +exit: + return status; +} + +static sss_status_t nxECKey_calculate_master_secret( + SE05x_AuthCtx_ECKey_t *pAuthFScp, uint8_t *rnd, size_t rndLen, uint8_t *sharedSecret, size_t sharedSecretLen) +{ + sss_status_t status = kStatus_SSS_Fail; + sss_digest_t md; + uint8_t derivationInput[100] = {0}; + uint8_t masterSk[32]; + size_t masterSkLen = sizeof(masterSk); + size_t derivationInputLen = 0; + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + + if (pAuthFScp->pDyn_ctx->authType == kSSS_AuthType_INT_ECKey_Counter) { + const uint8_t kdf_counter[] = {0x00, 0x00, 0x00, 0x01}; + memcpy(&derivationInput[derivationInputLen], kdf_counter, sizeof(kdf_counter)); + derivationInputLen += sizeof(kdf_counter); + } + memcpy(&derivationInput[derivationInputLen], sharedSecret, sharedSecretLen); + derivationInputLen += sharedSecretLen; + memcpy(&derivationInput[derivationInputLen], rnd, rndLen); + derivationInputLen += rndLen; + + derivationInput[derivationInputLen++] = SCP_CONFIG; + derivationInput[derivationInputLen++] = SECURITY_LEVEL; + derivationInput[derivationInputLen++] = GPCS_KEY_TYPE_AES; + derivationInput[derivationInputLen++] = GPCS_KEY_LEN_AES; + + status = sss_host_digest_context_init( + &md, pStatic_ctx->HostEcdsaObj.keyStore->session, kAlgorithm_SSS_SHA256, kMode_SSS_Digest); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + status = sss_host_digest_one_go(&md, derivationInput, derivationInputLen, masterSk, &masterSkLen); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + sss_host_digest_context_free(&md); + masterSkLen = 16; + LOG_MAU8_D("Master Secret", masterSk, masterSkLen); + /*Set the Master secret as AES Key*/ + status = sss_host_key_store_set_key( + pStatic_ctx->masterSec.keyStore, &pStatic_ctx->masterSec, masterSk, masterSkLen, masterSkLen * 8, NULL, 0); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); +cleanup: + return status; +} + +static void set_secp256r1nist_header(uint8_t *pbKey, size_t *pbKeyByteLen) +{ + unsigned int i = 0; + /* clang-format off */ + char temp[112] = { 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D, + 0x02, 0x01, 0x06, 0x08, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, + 0x07, 0x03, 0x42, 0x00 }; + /* clang-format on */ + + for (i = 0; i < *pbKeyByteLen; i++) { + temp[26 + i] = pbKey[i]; + } + + *pbKeyByteLen = *pbKeyByteLen + 26; + memcpy(pbKey, temp, *pbKeyByteLen); +} + +sss_status_t nxECKey_InternalAuthenticate(pSe05xSession_t se05xSession, + SE05x_AuthCtx_ECKey_t *pAuthFScp, + uint8_t *hostEckaPubKey, + size_t hostEckaPubKeyLen, + uint8_t *rndData, + size_t *rndDataLen, + uint8_t *receipt, + size_t *receiptLen) +{ + sss_status_t status = kStatus_SSS_Fail; + smStatus_t retStatus = SM_NOT_OK; + int tlvRet = 0; + uint8_t cmdbuf[256]; + size_t cmdbufLen = 0; + uint8_t *pCmdbuf = NULL; + uint8_t rspbuf[256]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + size_t rspIndex = 0; + sss_digest_t md; + uint8_t md_host5F37[32]; + size_t md_host5F37Len = sizeof(md_host5F37); + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + + const uint8_t tagEpkSeEcka[] = {0x7F, 0x49}; + const uint8_t tagSigSeEcka[] = {0x5F, 0x37}; + + const tlvHeader_t hdr = {{CLA_GP_7816 | CLA_GP_SECURITY_BIT, INS_GP_INTERNAL_AUTHENTICATE, 00, 00}}; + uint8_t scpParms[3] = {0xAB, SCP_CONFIG, SECURITY_LEVEL}; + uint8_t appletName[APPLET_NAME_LEN] = APPLET_NAME; + sss_asymmetric_t asym; + uint8_t sig_host5F37[100]; + size_t sig_host5F37Len = sizeof(sig_host5F37); + + size_t cntrlRefTemp_Len = 0 + 1 + 1 + APPLET_NAME_LEN /*TLV AID */ + 1 + 1 + sizeof(scpParms) /* TLV SCP Params */ + + 1 + 1 + 1 /* TLV Keytype */ + 1 + 1 + 1 /* TLV KeyLEN */; + +#if NX_LOG_ENABLE_SCP_DEBUG + nLog("APDU", NX_LEVEL_DEBUG, "ECKey Internal authenticate []"); +#endif /* VERBOSE_APDU_LOGS */ + cmdbuf[0] = kSE05x_TAG_GP_CONTRL_REF_PARM; // Tag Control reference template + cmdbuf[1] = (uint8_t)cntrlRefTemp_Len; + cmdbufLen = 2; + pCmdbuf = &cmdbuf[2]; + tlvRet = TLVSET_u8buf("SE05x AID", &pCmdbuf, &cmdbufLen, kSE05x_GP_TAG_AID, appletName, APPLET_NAME_LEN); + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + tlvRet = TLVSET_u8buf("SCP parameters", &pCmdbuf, &cmdbufLen, kSE05x_GP_TAG_SCP_PARMS, scpParms, sizeof(scpParms)); + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + tlvRet = TLVSET_U8("Key Type", &pCmdbuf, &cmdbufLen, kSE05x_GP_TAG_KEY_TYPE, GPCS_KEY_TYPE_AES); + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + tlvRet = TLVSET_U8("Key length", &pCmdbuf, &cmdbufLen, kSE05x_GP_TAG_KEY_LEN, GPCS_KEY_LEN_AES); + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + + /*Put the ephemral host ECKA pub key */ + *pCmdbuf++ = tagEpkSeEcka[0]; //Tag is 2 byte */ + cmdbufLen++; + *pCmdbuf++ = tagEpkSeEcka[1]; + cmdbufLen++; + *pCmdbuf++ = (uint8_t)hostEckaPubKeyLen; + cmdbufLen++; + memcpy(pCmdbuf, hostEckaPubKey, hostEckaPubKeyLen); + cmdbufLen += hostEckaPubKeyLen; + + /* Get the sha256 hash of Control_refernce_template + host ECKA Pub key */ + status = sss_host_digest_context_init( + &md, pStatic_ctx->HostEcdsaObj.keyStore->session, kAlgorithm_SSS_SHA256, kMode_SSS_Digest); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + status = sss_host_digest_one_go(&md, cmdbuf, cmdbufLen, md_host5F37, &md_host5F37Len); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + sss_host_digest_context_free(&md); + + /* Get the signiture over hash*/ + status = sss_host_asymmetric_context_init(&asym, + pStatic_ctx->HostEcdsaObj.keyStore->session, + &pStatic_ctx->HostEcdsaObj, + kAlgorithm_SSS_SHA256, + kMode_SSS_Sign); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + status = sss_host_asymmetric_sign_digest(&asym, md_host5F37, md_host5F37Len, sig_host5F37, &sig_host5F37Len); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + sss_host_asymmetric_context_free(&asym); + + /* Put the Control refernce template Value signiture*/ + pCmdbuf = &cmdbuf[cmdbufLen]; + *pCmdbuf++ = tagSigSeEcka[0]; + cmdbufLen++; + *pCmdbuf++ = tagSigSeEcka[1]; + cmdbufLen++; + *pCmdbuf++ = (uint8_t)sig_host5F37Len; + cmdbufLen++; + memcpy(pCmdbuf, sig_host5F37, sig_host5F37Len); + cmdbufLen += sig_host5F37Len; + status = kStatus_SSS_Fail; + retStatus = DoAPDUTxRx_s_Case4(se05xSession, &hdr, cmdbuf, cmdbufLen, rspbuf, &rspbufLen); + ENSURE_OR_GO_CLEANUP(retStatus == SM_OK); + tlvRet = + tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_GP_TAG_DR_SE, rndData, rndDataLen); /* Get the Random No */ + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + tlvRet = + tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_GP_TAG_RECEIPT, receipt, receiptLen); /* Get the Receipt */ + ENSURE_OR_GO_CLEANUP(tlvRet == 0); + ENSURE_OR_GO_CLEANUP((rspIndex + 2) == rspbufLen); + retStatus = (pRspbuf[rspIndex] << 8) | (pRspbuf[rspIndex + 1]); + ENSURE_OR_GO_CLEANUP(retStatus == SM_OK); + status = kStatus_SSS_Success; + +cleanup: + return status; +} + +sss_status_t nxECKey_GetVerify_SE_Ecka_Public(pSe05xSession_t se05xSession, uint8_t *pSePubEcka, size_t *pSePubEckaLen) +{ + smStatus_t retStatus = SM_NOT_OK; + sss_status_t status = kStatus_SSS_Fail; + int tlvRet = 0; + uint8_t cmdbuf[100]; + uint8_t rspbuf[512]; + uint8_t *pRspbuf = &rspbuf[0]; + size_t rspbufLen = ARRAY_SIZE(rspbuf); + + uint8_t sigSePubkey[100]; + size_t sigSePubkeyLen = sizeof(sigSePubkey); + size_t i = 0; + + const tlvHeader_t hdr = {{CLA_GP_7816, INS_GP_GET_DATA, P1_GP_GET_DATA, P2_GP_GET_DATA}}; + size_t cntrlRefTemp_Len = 0 + 1 + 1 + 2; /*TLV Key */ + + cmdbuf[i++] = kSE05x_TAG_GP_CONTRL_REF_PARM; // Tag Control reference template + cmdbuf[i++] = (uint8_t)cntrlRefTemp_Len; + cmdbuf[i++] = kSE05x_GP_TAG_GET_DATA; + cmdbuf[i++] = 0x02; + cmdbuf[i++] = 0x00; //Key Identifier + cmdbuf[i++] = 0x00; //Key Version Number + + retStatus = DoAPDUTxRx_s_Case4(se05xSession, &hdr, cmdbuf, i, rspbuf, &rspbufLen); + ENSURE_OR_GO_CLEANUP(retStatus == SM_OK); + + i = 0; + /* Get the Public Key*/ + tlvRet = get_u8buf_2bTag(pRspbuf, &i, rspbufLen, (uint16_t)TAG_PK_SE_ECKA, pSePubEcka, pSePubEckaLen); + if (0 != tlvRet) { + goto cleanup; + } + /* Get the signiture */ + tlvRet = get_u8buf_2bTag(pRspbuf, &i, rspbufLen, (uint16_t)TAG_SIG_SE_ECKA, sigSePubkey, &sigSePubkeyLen); + if (0 != tlvRet) { + goto cleanup; + } + + ENSURE_OR_GO_CLEANUP((i + 2) == rspbufLen) + retStatus = (pRspbuf[i] << 8) | (pRspbuf[i + 1]); + ENSURE_OR_GO_CLEANUP(retStatus == SM_OK); + status = kStatus_SSS_Success; +cleanup: + return status; +} + +int get_u8buf_2bTag(uint8_t *buf, size_t *pBufIndex, const size_t bufLen, uint16_t tag, uint8_t *rsp, size_t *pRspLen) +{ + int retVal = 1; + uint8_t *pBuf = buf + (*pBufIndex); + uint16_t got_tag; + got_tag = ((*pBuf++) << 8) & 0xFFFF; + got_tag |= ((*pBuf++)) & 0xFFFF; + size_t extendedLen; + size_t rspLen; + //size_t len; + if (got_tag != tag) + goto cleanup; + rspLen = *pBuf++; + + if (rspLen <= 0x7FU) { + extendedLen = rspLen; + *pBufIndex += (2 + 1); + } + else if (rspLen == 0x81) { + extendedLen = *pBuf++; + *pBufIndex += (2 + 1 + 1); + } + else if (rspLen == 0x82) { + extendedLen = *pBuf++; + extendedLen = (extendedLen << 8) | *pBuf++; + *pBufIndex += (2 + 1 + 2); + } + else { + goto cleanup; + } + + if (extendedLen > *pRspLen) + goto cleanup; + if (extendedLen > bufLen) + goto cleanup; + + *pRspLen = extendedLen; + *pBufIndex += extendedLen; + while (extendedLen-- > 0) { + *rsp++ = *pBuf++; + } + retVal = 0; +cleanup: + return retVal; +} + +sss_status_t nxECKey_Calculate_Shared_secret( + SE05x_AuthCtx_ECKey_t *pAuthFScp, uint8_t *sharedSecret, size_t *sharedSecretLen) +{ + sss_status_t status = kStatus_SSS_Fail; + sss_derive_key_t dervCtx; + sss_object_t shsSecret; + + NXECKey03_StaticCtx_t *pStatic_ctx = pAuthFScp->pStatic_ctx; + size_t sharedSecBitLen = 0; + + status = sss_host_key_object_init(&shsSecret, pStatic_ctx->SeEcPubKey.keyStore); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_host_key_object_allocate_handle( + &shsSecret, __LINE__, kSSS_KeyPart_Default, kSSS_CipherType_AES, 32, kKeyObject_Mode_Transient); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_host_derive_key_context_init(&dervCtx, + pStatic_ctx->HostEcKeypair.keyStore->session, + &pStatic_ctx->HostEcKeypair, + kAlgorithm_SSS_ECDH, + kMode_SSS_ComputeSharedSecret); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = sss_host_derive_key_dh(&dervCtx, &pStatic_ctx->SeEcPubKey, &shsSecret); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + status = + sss_host_key_store_get_key(&shsSecret.keyStore, &shsSecret, sharedSecret, sharedSecretLen, &sharedSecBitLen); + ENSURE_OR_GO_CLEANUP(status == kStatus_SSS_Success); + + LOG_MAU8_D("Shared Secret", sharedSecret, *sharedSecretLen); + +cleanup: + sss_host_derive_key_context_free(&dervCtx); + sss_host_key_object_free(&shsSecret); + return status; +} +#endif /* defined SSS_HAVE_SCP_SCP03_SSS */ +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c new file mode 100644 index 00000000000..b22940b21a5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c @@ -0,0 +1,509 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file */ + +#include +#include + +#if SSS_HAVE_APPLET_SE05X_IOT +#include +#include +#include +#include +#include + +uint32_t se05x_sssKeyTypeLenToCurveId(sss_cipher_type_t cipherType, size_t keyBits) +{ + uint32_t u32_curve_id = 0; + switch (cipherType) { + case kSSS_CipherType_EC_NIST_P: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { +#if SSS_HAVE_EC_NIST_192 + case 192: + eCurveID = kSE05x_ECCurve_NIST_P192; + break; +#endif +#if SSS_HAVE_EC_NIST_224 + case 224: + eCurveID = kSE05x_ECCurve_NIST_P224; + break; +#endif + case 256: + eCurveID = kSE05x_ECCurve_NIST_P256; + break; + case 384: + eCurveID = kSE05x_ECCurve_NIST_P384; + break; +#if SSS_HAVE_EC_NIST_192 + case 521: + eCurveID = kSE05x_ECCurve_NIST_P521; + break; +#endif + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#if SSS_HAVE_EC_BP + case kSSS_CipherType_EC_BRAINPOOL: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { + case 160: + eCurveID = kSE05x_ECCurve_Brainpool160; + break; + case 192: + eCurveID = kSE05x_ECCurve_Brainpool192; + break; + case 224: + eCurveID = kSE05x_ECCurve_Brainpool224; + break; + case 256: + eCurveID = kSE05x_ECCurve_Brainpool256; + break; + case 320: + eCurveID = kSE05x_ECCurve_Brainpool320; + break; + case 384: + eCurveID = kSE05x_ECCurve_Brainpool384; + break; + case 512: + eCurveID = kSE05x_ECCurve_Brainpool512; + break; + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#endif +#if SSS_HAVE_EC_NIST_K + case kSSS_CipherType_EC_NIST_K: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { + case 160: + eCurveID = kSE05x_ECCurve_Secp160k1; + break; + case 192: + eCurveID = kSE05x_ECCurve_Secp192k1; + break; + case 224: + eCurveID = kSE05x_ECCurve_Secp224k1; + break; + case 256: + eCurveID = kSE05x_ECCurve_Secp256k1; + break; + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#endif +#if SSS_HAVE_EC_MONT + case kSSS_CipherType_EC_MONTGOMERY: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { +#if SSS_HAVE_SE05X_VER_GTE_06_00 + case 448: + eCurveID = kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_448; + break; +#endif + case 256: + eCurveID = kSE05x_ECCurve_RESERVED_ID_ECC_MONT_DH_25519; + break; + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#endif +#if SSS_HAVE_EC_ED + case kSSS_CipherType_EC_TWISTED_ED: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { + case 256: + eCurveID = kSE05x_ECCurve_RESERVED_ID_ECC_ED_25519; + break; + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#endif +#if SSS_HAVE_TPM_BN + case kSSS_CipherType_EC_BARRETO_NAEHRIG: { + SE05x_ECCurve_t eCurveID; + switch (keyBits) { + case 256: + eCurveID = kSE05x_ECCurve_TPM_ECC_BN_P256; + break; + default: + eCurveID = kSE05x_ECCurve_NA; + } + u32_curve_id = (uint32_t)eCurveID; + break; + } +#endif + default: + break; + } + return u32_curve_id; +} + +smStatus_t Se05x_API_EC_CurveGetId(pSe05xSession_t session_ctx, uint32_t objectID, SE05x_ECCurve_t *pcurveId) +{ + smStatus_t ret = SM_NOT_OK; + if (pcurveId) { + uint8_t u8curve = 0; + ret = Se05x_API_GetECCurveId(session_ctx, objectID, &u8curve); + if (ret == SM_OK) { + *pcurveId = (SE05x_ECCurve_t)u8curve; + } + } + return ret; +} + +smStatus_t Se05x_i2c_master_txn(sss_session_t *sess, SE05x_I2CM_cmd_t *p, uint8_t noOftags) +{ + smStatus_t retval = SM_NOT_OK; + uint8_t buffer[SE05X_I2CM_MAX_BUF_SIZE_CMD] = {0}; + size_t bufferLen = 0; + uint8_t iCnt = 0; + uint8_t remainingCnt = 0; + int tlvRet = 0; + uint8_t rspbuffer[SE05X_I2CM_MAX_BUF_SIZE_RSP] = {0}; + size_t rspbufferLen = sizeof(rspbuffer); + + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)sess; + Se05xSession_t *se050session_id = NULL; + + uint8_t *pCmdbuf = &buffer[0]; + const uint8_t *pSendbuf = &buffer[0]; + size_t SendLen = 0; + + if (se05x_session->subsystem == kType_SSS_SE_SE05x) { + se050session_id = &se05x_session->s_ctx; + } + else { + goto cleanup; + } + + for (iCnt = 0; iCnt < noOftags; iCnt++) { + if (p[iCnt].type == kSE05x_I2CM_Configure) { + uint8_t configBuf[2] = {0}; + size_t configBufLen = sizeof(configBuf); + configBuf[0] = p[iCnt].cmd.cfg.I2C_addr; + configBuf[1] = p[iCnt].cmd.cfg.I2C_baudRate; + tlvRet = TLVSET_u8buf_I2CM( + "I2CM Configure", &pCmdbuf, &bufferLen, kSE05x_TAG_I2CM_Config, configBuf, configBufLen); + if (0 != tlvRet) { + goto cleanup; + } + } + //else if (p[iCnt].type == kSE05x_I2CM_Security) { + //} + else if (p[iCnt].type == kSE05x_I2CM_Write) { + tlvRet = TLVSET_u8buf_I2CM("I2CM Write", + &pCmdbuf, + &bufferLen, + kSE05x_TAG_I2CM_Write, + p[iCnt].cmd.w.writebuf, + p[iCnt].cmd.w.writeLength); + if (0 != tlvRet) { + goto cleanup; + } + } + else if (p[iCnt].type == kSE05x_I2CM_Read) { + uint8_t readLenBuf[2]; + size_t readLenBufLen = sizeof(readLenBuf); + readLenBuf[0] = (uint8_t)(p[iCnt].cmd.rd.readLength >> 8); + readLenBuf[1] = (uint8_t)(p[iCnt].cmd.rd.readLength); + tlvRet = + TLVSET_u8buf_I2CM("I2CM Read", &pCmdbuf, &bufferLen, kSE05x_TAG_I2CM_Read, readLenBuf, readLenBufLen); + if (0 != tlvRet) { + goto cleanup; + } + } + else { + break; + } + } + + SendLen = bufferLen; + retval = Se05x_API_I2CM_Send(se050session_id, pSendbuf, SendLen, rspbuffer, &rspbufferLen); + + if (retval == SM_OK) { + // Walk through the result. + // In principle the order of results matches the order the incoming commands. + // Exception: Structural error in format incoming commands + uint8_t *rspTag = &rspbuffer[0]; + unsigned int rspPos = 1u; + for (iCnt = 0; iCnt < noOftags; iCnt++) { + if (*rspTag == kSE05x_I2CM_StructuralIssue) { + // Modify TLV type of command to report back error + p[iCnt].type = kSE05x_I2CM_StructuralIssue; + p[iCnt].cmd.issue.issueStatus = rspbuffer[rspPos]; + break; + } + else if (p[iCnt].type == kSE05x_I2CM_Configure) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.cfg.status = rspbuffer[rspPos]; + } + //else if (p[iCnt].type == kSE05x_I2CM_Security) { + //} + else if (p[iCnt].type == kSE05x_I2CM_Write) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.w.wrStatus = rspbuffer[rspPos]; + } + else if (p[iCnt].type == kSE05x_I2CM_Read) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.rd.rdStatus = rspbuffer[rspPos]; + if (p[iCnt].cmd.rd.rdStatus == kSE05x_I2CM_Success) { + // Receiving less data than requested is not considered an error + uint16_t reportedRead = (rspbuffer[rspPos + 1] << 8) + rspbuffer[rspPos + 2]; + rspPos += 2; + if (reportedRead < p[iCnt].cmd.rd.readLength) { + LOG_W("kSE05x_I2CM_Read: Requested %d, Received %d byte", + p[iCnt].cmd.rd.readLength, + reportedRead); + p[iCnt].cmd.rd.readLength = reportedRead; + } + // Did we receive enough data? + if (rspbufferLen > (rspPos + p[iCnt].cmd.rd.readLength)) { + memcpy(p[iCnt].cmd.rd.rdBuf, &rspbuffer[rspPos + 1], p[iCnt].cmd.rd.readLength); + rspPos += p[iCnt].cmd.rd.readLength; + } + else { + // TODO: Indicate we could not transfer result into buffer + LOG_E( + "kSE05x_I2CM_Read: Expecting more data (%d) than " + "was received", + p[iCnt].cmd.rd.readLength); + break; + } + } + } + else { + break; + } + // Update parsing position + if (rspbufferLen > rspPos + 2u) { + rspTag = &rspbuffer[rspPos + 1]; + rspPos += 2; + } + } + // If we dropped out before handling all tags, clear the tagtype of the tags + // that were not handled + for (remainingCnt = iCnt + 1; remainingCnt < noOftags; remainingCnt++) { + p[remainingCnt].type = kSE05x_I2CM_None; + } + } + +cleanup: + return retval; +} + +smStatus_t Se05x_i2c_master_attst_txn(sss_session_t *sess, + sss_object_t *keyObject, + SE05x_I2CM_cmd_t *p, + uint8_t *random_attst, + size_t random_attstLen, + SE05x_AttestationAlgo_t attst_algo, + SE05x_TimeStamp_t *ptimeStamp, + size_t *timeStampLen, + uint8_t *freshness, + size_t *pfreshnessLen, + uint8_t *chipId, + size_t *pchipIdLen, + uint8_t *signature, + size_t *psignatureLen, + uint8_t noOftags) +{ + smStatus_t retval = SM_NOT_OK; + uint8_t buffer[SE05X_I2CM_MAX_BUF_SIZE_CMD] = {0}; + size_t bufferLen = 0; + uint8_t iCnt = 0; + uint8_t remainingCnt = 0; + int tlvRet = 0; + uint8_t rspbuffer[SE05X_I2CM_MAX_BUF_SIZE_RSP] = {0}; + size_t rspbufferLen = sizeof(rspbuffer); + uint32_t attestID; + + sss_se05x_session_t *se05x_session = (sss_se05x_session_t *)sess; + Se05xSession_t *se050session_id = NULL; + + sss_se05x_object_t *keyObject_attst = (sss_se05x_object_t *)keyObject; + attestID = keyObject_attst->keyId; + + uint8_t *pCmdbuf = &buffer[0]; + const uint8_t *pSendbuf = &buffer[0]; + size_t SendLen = 0; + + if (se05x_session->subsystem == kType_SSS_SE_SE05x) { + se050session_id = &se05x_session->s_ctx; + } + else { + goto cleanup; + } + + for (iCnt = 0; iCnt < noOftags; iCnt++) { + if (p[iCnt].type == kSE05x_I2CM_Configure) { + uint8_t configBuf[2] = {0}; + size_t configBufLen = sizeof(configBuf); + configBuf[0] = p[iCnt].cmd.cfg.I2C_addr; + configBuf[1] = p[iCnt].cmd.cfg.I2C_baudRate; + tlvRet = TLVSET_u8buf_I2CM( + "I2CM Configure", &pCmdbuf, &bufferLen, kSE05x_TAG_I2CM_Config, configBuf, configBufLen); + if (0 != tlvRet) { + goto cleanup; + } + } + else if (p[iCnt].type == kSE05x_I2CM_Write) { + tlvRet = TLVSET_u8buf_I2CM("I2CM Write", + &pCmdbuf, + &bufferLen, + kSE05x_TAG_I2CM_Write, + p[iCnt].cmd.w.writebuf, + p[iCnt].cmd.w.writeLength); + if (0 != tlvRet) { + goto cleanup; + } + } + else if (p[iCnt].type == kSE05x_I2CM_Read) { + uint8_t readLenBuf[2]; + size_t readLenBufLen = sizeof(readLenBuf); + readLenBuf[0] = (uint8_t)(p[iCnt].cmd.rd.readLength >> 8); + readLenBuf[1] = (uint8_t)(p[iCnt].cmd.rd.readLength); + tlvRet = + TLVSET_u8buf_I2CM("I2CM Read", &pCmdbuf, &bufferLen, kSE05x_TAG_I2CM_Read, readLenBuf, readLenBufLen); + if (0 != tlvRet) { + goto cleanup; + } + } + else { + break; + } + } + *timeStampLen = sizeof(SE05x_TimeStamp_t); + SendLen = bufferLen; + retval = Se05x_API_I2CM_ExecuteCommandSet(se050session_id, + pSendbuf, + SendLen, + attestID, + attst_algo, + rspbuffer, + &rspbufferLen, + ptimeStamp, + freshness, + pfreshnessLen, + chipId, + pchipIdLen, + signature, + psignatureLen, + random_attst, + random_attstLen); + + if (retval == SM_OK) { + // Walk through the result. + // In principle the order of results matches the order the incoming commands. + // Exception: Structural error in format incoming commands + uint8_t *rspTag = &rspbuffer[0]; + unsigned int rspPos = 1u; + for (iCnt = 0; iCnt < noOftags; iCnt++) { + if (*rspTag == kSE05x_I2CM_StructuralIssue) { + // Modify TLV type of command to report back error + p[iCnt].type = kSE05x_I2CM_StructuralIssue; + p[iCnt].cmd.issue.issueStatus = rspbuffer[rspPos]; + break; + } + else if (p[iCnt].type == kSE05x_I2CM_Configure) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.cfg.status = rspbuffer[rspPos]; + } + //else if (p[iCnt].type == kSE05x_I2CM_Security) { + //} + else if (p[iCnt].type == kSE05x_I2CM_Write) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.w.wrStatus = rspbuffer[rspPos]; + } + else if (p[iCnt].type == kSE05x_I2CM_Read) { + // Check whether response is in expected order + if (*rspTag != p[iCnt].type) { + LOG_W("Response out-of-order"); + break; + } + p[iCnt].cmd.rd.rdStatus = rspbuffer[rspPos]; + if (p[iCnt].cmd.rd.rdStatus == kSE05x_I2CM_Success) { + // Receiving less data than requested is not considered an error + uint16_t reportedRead = (rspbuffer[rspPos + 1] << 8) + rspbuffer[rspPos + 2]; + rspPos += 2; + if (reportedRead < p[iCnt].cmd.rd.readLength) { + LOG_W("kSE05x_I2CM_Read: Requested %d, Received %d byte", + p[iCnt].cmd.rd.readLength, + reportedRead); + p[iCnt].cmd.rd.readLength = reportedRead; + } + // Did we receive enough data? + if (rspbufferLen > (rspPos + p[iCnt].cmd.rd.readLength)) { + memcpy(p[iCnt].cmd.rd.rdBuf, &rspbuffer[rspPos + 1], p[iCnt].cmd.rd.readLength); + rspPos += p[iCnt].cmd.rd.readLength; + } + else { + // TODO: Indicate we could not transfer result into buffer + LOG_E( + "kSE05x_I2CM_Read: Expecting more data (%d) than " + "was received", + p[iCnt].cmd.rd.readLength); + break; + } + } + } + else { + break; + } + // Update parsing position + if (rspbufferLen > rspPos + 2u) { + rspTag = &rspbuffer[rspPos + 1]; + rspPos += 2; + } + } + // If we dropped out before handling all tags, clear the tagtype of the tags + // that were not handled + for (remainingCnt = iCnt + 1; remainingCnt < noOftags; remainingCnt++) { + p[remainingCnt].type = kSE05x_I2CM_None; + } + } + +cleanup: + return retval; +} + +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c new file mode 100644 index 00000000000..4bc6015adc1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c @@ -0,0 +1,392 @@ +/* +* +* Copyright 2018-2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +/** @file */ + +#include +#include +#include + +#if SSS_HAVE_APPLET_SE05X_IOT +#include + +/*Update header bit of policy based on the access rights sets in the policy + Input:policy object of type sss_policy_sym_key_u + Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_sym_key_policy(sss_policy_sym_key_u key_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy + Input:policy object of type sss_policy_asym_key_u + Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_asym_key_policy(sss_policy_asym_key_u key_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_common_u +Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_common_policy(sss_policy_common_u common_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_userid_u +Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_pin_policy(sss_policy_userid_u pin_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_file_u +Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_file_policy(sss_policy_file_u file_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_counter_u +Output:pbuffer pointing to policy header offset*/ +static void sss_se05x_update_header_counter_policy(sss_policy_counter_u counter_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_pcr_u +Output:pbuffer pointing to policy header offset +*/ +static void sss_se05x_update_header_pcr_policy(sss_policy_pcr_u pcr_pol, uint8_t *pbuffer); + +/*Update header bit of policy based on the access rights sets in the policy +Input:policy object of type sss_policy_common_pcr_value_u +Output:pbuffer pointing to policy header offset +*/ +static void sss_se05x_update_header_pcr_value_policy(sss_policy_common_pcr_value_u pcr_value_pol, uint8_t *pbuffer); + +static void sss_se05x_update_ext_pcr_value_policy( + sss_policy_common_pcr_value_u pcr_value_pol, uint8_t *pbuffer, uint32_t *ext_offset); + +/* +finds indices of all same auth Ids in a group of polices and returns the count +of same auth ids with in a group of Ids, it laso copies indices in to an array passed by user +Input: authId to be searched + policies: array of all policies with diversified auth ids +Output: pindices " array contains index of all input authid +retuns :count of same auth ids with in a group of Ids +*/ +static int sss_se05x_find_authId_instances(uint32_t authId, uint8_t *pindices, sss_policy_t *policies); +static void sss_se05x_copy_uint32_to_u8_array(uint32_t u32, uint8_t *pbuffer); +static void sss_se05x_copy_uint16_to_u8_array(uint16_t u16, uint8_t *pbuffer); + +static void sss_se05x_update_header_sym_key_policy(sss_policy_sym_key_u key_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (key_pol.can_Sign) { + header |= POLICY_OBJ_ALLOW_SIGN; + } + if (key_pol.can_Verify) { + header |= POLICY_OBJ_ALLOW_VERIFY; + } + if (key_pol.can_Encrypt) { + header |= POLICY_OBJ_ALLOW_ENC; + } + if (key_pol.can_Decrypt) { + header |= POLICY_OBJ_ALLOW_DEC; + } + if (key_pol.can_KD) { + header |= POLICY_OBJ_ALLOW_KDF; + } + if (key_pol.can_Wrap) { + header |= POLICY_OBJ_ALLOW_WRAP; + } + if (key_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + if (key_pol.can_Gen) { + header |= POLICY_OBJ_ALLOW_GEN; + } + if (key_pol.can_Desfire_Auth) { + header |= POLICY_OBJ_ALLOW_DESFIRE_AUTHENTICATION; + } + if (key_pol.can_Desfire_Dump) { + header |= POLICY_OBJ_ALLOW_DESFIRE_DUMP_SESSION_KEYS; + } + if (key_pol.can_Import_Export) { + header |= POLICY_OBJ_ALLOW_IMPORT_EXPORT; + } +#if SSS_HAVE_SE05X_VER_GTE_06_00 + if (key_pol.forbid_Derived_Output) { + header |= POLICY_OBJ_FORBID_DERIVED_OUTPUT; + } +#endif +#if SSS_HAVE_SE05X_VER_GTE_06_00 + if (key_pol.allow_kdf_ext_rnd) { + header |= POLICY_OBJ_ALLOW_KDF_EXT_RANDOM; + } +#endif + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_asym_key_policy(sss_policy_asym_key_u key_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (key_pol.can_Sign) { + header |= POLICY_OBJ_ALLOW_SIGN; + } + if (key_pol.can_Verify) { + header |= POLICY_OBJ_ALLOW_VERIFY; + } + if (key_pol.can_Encrypt) { + header |= POLICY_OBJ_ALLOW_ENC; + } + if (key_pol.can_Decrypt) { + header |= POLICY_OBJ_ALLOW_DEC; + } + if (key_pol.can_KD) { + header |= POLICY_OBJ_ALLOW_KDF; + } + if (key_pol.can_Wrap) { + header |= POLICY_OBJ_ALLOW_WRAP; + } + if (key_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + if (key_pol.can_Gen) { + header |= POLICY_OBJ_ALLOW_GEN; + } + if (key_pol.can_Import_Export) { + header |= POLICY_OBJ_ALLOW_IMPORT_EXPORT; + } + if (key_pol.can_KA) { + header |= POLICY_OBJ_ALLOW_KA; + } + if (key_pol.can_Read) { + header |= POLICY_OBJ_ALLOW_READ; + } + if (key_pol.can_Attest) { + header |= POLICY_OBJ_ALLOW_ATTESTATION; + } +#if SSS_HAVE_SE05X_VER_GTE_06_00 + if (key_pol.forbid_Derived_Output) { + header |= POLICY_OBJ_FORBID_DERIVED_OUTPUT; + } +#endif + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_common_policy(sss_policy_common_u common_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (common_pol.can_Delete) { + header |= POLICY_OBJ_ALLOW_DELETE; + } + if (common_pol.forbid_All) { + header |= POLICY_OBJ_FORBID_ALL; + } + if (common_pol.req_Sm) { + header |= POLICY_OBJ_REQUIRE_SM; + } + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_pin_policy(sss_policy_userid_u pin_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (pin_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_file_policy(sss_policy_file_u file_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (file_pol.can_Read) { + header |= POLICY_OBJ_ALLOW_READ; + } + if (file_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_counter_policy(sss_policy_counter_u counter_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (counter_pol.can_Read) { + header |= POLICY_OBJ_ALLOW_READ; + } + if (counter_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_pcr_policy(sss_policy_pcr_u pcr_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + if (pcr_pol.can_Read) { + header |= POLICY_OBJ_ALLOW_READ; + } + if (pcr_pol.can_Write) { + header |= POLICY_OBJ_ALLOW_WRITE; + } + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_header_pcr_value_policy(sss_policy_common_pcr_value_u pcr_pol, uint8_t *pbuffer) +{ + uint32_t header = 0; + header |= POLICY_OBJ_REQUIRE_PCR_VALUE; + sss_se05x_copy_uint32_to_u8_array(header, pbuffer); +} + +static void sss_se05x_update_ext_pcr_value_policy( + sss_policy_common_pcr_value_u pcr_pol, uint8_t *pbuffer, uint32_t *ext_offset) +{ + /*copy 4 bytes PCR Object ID*/ + sss_se05x_copy_uint32_to_u8_array(pcr_pol.pcrObjId, pbuffer + *ext_offset); + *ext_offset += sizeof(pcr_pol.pcrObjId); + /*copy 32 bytes PCR value*/ + memcpy(pbuffer + *ext_offset, pcr_pol.pcrExpectedValue, sizeof(pcr_pol.pcrExpectedValue)); + *ext_offset += sizeof(pcr_pol.pcrExpectedValue); +} + +static void sss_se05x_copy_uint32_to_u8_array(uint32_t u32, uint8_t *pbuffer) +{ + pbuffer[0] |= (uint8_t)((u32 >> 3 * 8) & 0xFF); + pbuffer[1] |= (uint8_t)((u32 >> 2 * 8) & 0xFF); + pbuffer[2] |= (uint8_t)((u32 >> 1 * 8) & 0xFF); + pbuffer[3] |= (uint8_t)((u32 >> 0 * 8) & 0xFF); +} + +static void sss_se05x_copy_uint16_to_u8_array(uint16_t u16, uint8_t *pbuffer) +{ + pbuffer[0] |= (uint8_t)((u16 >> 8) & 0xFF); + pbuffer[1] |= (uint8_t)((u16)&0xFF); +} +static int sss_se05x_find_authId_instances(uint32_t authId, uint8_t *pindices, sss_policy_t *policies) +{ + int count = 0; + for (uint32_t i = 0; i <= policies->nPolicies - 1; i++) { + if (policies->policies[i] != NULL && policies->policies[i]->auth_obj_id == authId) { + *pindices++ = i; + count++; + } + } + return count; +} + +sss_status_t sss_se05x_create_object_policy_buffer(sss_policy_t *policies, uint8_t *pbuff, size_t *buf_len) +{ + uint8_t temp_buffer[MAX_OBJ_POLICY_SIZE] = {0}; + uint8_t indexArray[MAX_OBJ_POLICY_TYPES] = {0}; + uint8_t auth_id_count = 0; + uint8_t policiesCopied = 0; + uint32_t ext_offset = 0; + uint32_t offset = 0; + + if ((policies == NULL) || (pbuff == NULL) || (buf_len == NULL)) + return kStatus_SSS_InvalidArgument; + + if (policies->nPolicies > SSS_POLICY_COUNT_MAX) { + return kStatus_SSS_InvalidArgument; + } + + *buf_len = 0; + /*Reinitialize policy buffer for every Secure object*/ + memset(pbuff, 0x00, MAX_POLICY_BUFFER_SIZE); + for (uint32_t i = 0; i < policies->nPolicies && policiesCopied < policies->nPolicies; i++) { + if (policies->policies[i] != NULL) { + auth_id_count = + sss_se05x_find_authId_instances(policies->policies[i]->auth_obj_id, &indexArray[0], policies); + /*length is initialized with default length + will be updated when extensions are copied*/ + temp_buffer[OBJ_POLICY_LENGTH_OFFSET] = DEFAULT_OBJECT_POLICY_SIZE; + /* Copy Auth Id*/ + sss_se05x_copy_uint32_to_u8_array( + policies->policies[i]->auth_obj_id, &temp_buffer[OBJ_POLICY_AUTHID_OFFSET]); + for (int j = 0; j < auth_id_count; j++) { + /* Update AR Header as per object type*/ + switch (policies->policies[indexArray[j]]->type) { + case KPolicy_Sym_Key: + sss_se05x_update_header_sym_key_policy( + (policies->policies[indexArray[j]])->policy.symmkey, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_Asym_Key: + sss_se05x_update_header_asym_key_policy( + (policies->policies[indexArray[j]])->policy.asymmkey, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_Common: + sss_se05x_update_header_common_policy( + (policies->policies[indexArray[j]])->policy.common, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_Common_PCR_Value: + sss_se05x_update_header_pcr_value_policy( + (policies->policies[indexArray[j]])->policy.common_pcr_value, + &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + sss_se05x_update_ext_pcr_value_policy((policies->policies[indexArray[j]])->policy.common_pcr_value, + &temp_buffer[OBJ_POLICY_EXT_OFFSET], + &ext_offset); + temp_buffer[OBJ_POLICY_LENGTH_OFFSET] += OBJ_POLICY_PCR_DATA_SIZE; + break; + case KPolicy_File: + sss_se05x_update_header_file_policy( + (policies->policies[indexArray[j]])->policy.file, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_Counter: + sss_se05x_update_header_counter_policy( + (policies->policies[indexArray[j]])->policy.counter, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_PCR: + sss_se05x_update_header_pcr_policy( + (policies->policies[indexArray[j]])->policy.pcr, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + case KPolicy_UserID: + sss_se05x_update_header_pin_policy( + (policies->policies[indexArray[j]])->policy.pin, &temp_buffer[OBJ_POLICY_HEADER_OFFSET]); + break; + default: + break; + } + policies->policies[indexArray[j]] = NULL; + } + memcpy(pbuff + offset, temp_buffer, (temp_buffer[0] + 1)); + *buf_len += (temp_buffer[0] + 1); + policiesCopied = policiesCopied + auth_id_count; + offset += (temp_buffer[0] + 1); + /* reinitialize temp buffer for a new policy*/ + memset(&temp_buffer[0], 0x00, sizeof(temp_buffer)); + ext_offset = 0; + } + } + + return kStatus_SSS_Success; +} + +sss_status_t sss_se05x_create_session_policy_buffer( + sss_policy_session_u *session_policy, uint8_t *session_pol_buff, size_t *buf_len) +{ + uint16_t session_header = 0; + /*Reinitialize policy buffer for every Secure object*/ + memset(session_pol_buff, 0x00, MAX_POLICY_BUFFER_SIZE); + + if ((session_policy == NULL) || (session_pol_buff == NULL) || (buf_len == NULL)) + return kStatus_SSS_InvalidArgument; + + *buf_len = DEFAULT_SESSION_POLICY_SIZE; + + /*set default length*/ + session_pol_buff[SESSION_POLICY_LENGTH_OFFSET] = DEFAULT_SESSION_POLICY_SIZE; + if (session_policy->has_MaxOperationsInSession) { + session_header |= POLICY_SESSION_MAX_APDU; + sss_se05x_copy_uint16_to_u8_array(session_header, &session_pol_buff[SESSION_POLICY_AR_HEADER_OFFSET]); + sss_se05x_copy_uint16_to_u8_array(session_policy->maxOperationsInSession, &session_pol_buff[*buf_len]); + *buf_len += sizeof(session_policy->maxOperationsInSession); + } + if (session_policy->has_MaxDurationOfSession_sec) { + session_header |= POLICY_SESSION_MAX_TIME; + sss_se05x_copy_uint16_to_u8_array(session_header, &session_pol_buff[SESSION_POLICY_AR_HEADER_OFFSET]); + sss_se05x_copy_uint16_to_u8_array(session_policy->maxDurationOfSession_sec, &session_pol_buff[*buf_len]); + *buf_len += sizeof(session_policy->maxDurationOfSession_sec); + } + if (session_policy->allowRefresh) { + session_header |= POLICY_SESSION_ALLOW_REFRESH; + sss_se05x_copy_uint16_to_u8_array(session_header, &session_pol_buff[SESSION_POLICY_AR_HEADER_OFFSET]); + } + session_pol_buff[0] = (uint8_t)(*buf_len - 1); //Exclude Length of Policy field. + return kStatus_SSS_Success; +} +#endif /* SSS_HAVE_APPLET_SE05X_IOT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c new file mode 100644 index 00000000000..50b2affed4e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c @@ -0,0 +1,520 @@ +/* +* +* Copyright 2018-2020 NXP +* SPDX-License-Identifier: Apache-2.0 +*/ + +/** @file */ + +#if defined(SSS_USE_FTR_FILE) +#include "fsl_sss_ftr.h" +#else +#include "fsl_sss_ftr_default.h" +#endif + +#if SSS_HAVE_APPLET_SE05X_IOT + +#if SSS_HAVE_HOSTCRYPTO_USER +#include +#endif + +#if defined(FLOW_VERBOSE) +#define NX_LOG_ENABLE_SCP_DEBUG 1 +#endif + +#if SSS_HAVE_HOSTCRYPTO_ANY + +#include +#include +#include +#include + +#include "nxEnsure.h" +#include "nxScp03_Apis.h" +#include "smCom.h" +#if defined(SECURE_WORLD) +#include "fsl_sss_lpc55s_apis.h" +#endif + +/* ************************************************************************** */ +/* Functions : Private function declaration */ +/* ************************************************************************** */ + +//#define INITIAL_HOST_CHALLANGE {0xAF,0x28,0xE1,0x16,0xD1,0x58,0x1E,0x89} + +/** +* To Initiate secure channel +*/ +static sss_status_t nxScp03_GP_InitializeUpdate(pSe05xSession_t se05xSession, + uint8_t *hostChallenge, + uint16_t hostChallengeLen, + uint8_t *keyDivData, + uint16_t *pKeyDivDataLen, + uint8_t *keyInfo, + uint16_t *pKeyInfoLen, + uint8_t *cardChallenge, + uint16_t *pCardChallengeLen, + uint8_t *cardCryptoGram, + uint16_t *pCardCryptoGramLen, + uint8_t *seqCounter, + uint16_t *pSeqCounterLen, + uint8_t keyVerNo); + +static sss_status_t nxScp03_HostLocal_CalculateSessionKeys( + NXSCP03_AuthCtx_t *pAuthScp03, uint8_t *hostChallenge, uint8_t *cardChallenge); + +/** +* To authenticate the initiated secure channel +*/ +static sss_status_t nxScp03_GP_ExternalAuthenticate( + pSe05xSession_t se05xSession, sss_object_t *keyObj, uint8_t *updateMCV, uint8_t *hostCryptogram); + +sss_status_t nxScp03_AuthenticateChannel(pSe05xSession_t se05xSession, NXSCP03_AuthCtx_t *pAuthScp03) +{ +#ifdef INITIAL_HOST_CHALLANGE + uint8_t hostChallenge[] = INITIAL_HOST_CHALLANGE; +#else + uint8_t hostChallenge[SCP_GP_HOST_CHALLENGE_LEN]; + sss_rng_context_t rngctx; +#endif + uint8_t keyDivData[SCP_GP_IU_KEY_DIV_DATA_LEN]; + uint16_t keyDivDataLen = sizeof(keyDivData); + uint8_t keyInfo[SCP_GP_IU_KEY_INFO_LEN]; + uint16_t keyInfoLen = sizeof(keyInfo); + uint8_t cardChallenge[SCP_GP_CARD_CHALLENGE_LEN]; + uint16_t cardChallengeLen = sizeof(cardChallenge); + uint8_t cardCryptoGram[SCP_GP_IU_CARD_CRYPTOGRAM_LEN]; + uint16_t cardCryptoGramLen = sizeof(cardCryptoGram); + uint8_t seqCounter[SCP_GP_IU_SEQ_COUNTER_LEN]; + uint16_t seqCounterLen = sizeof(seqCounter); + uint8_t hostCryptogram[SCP_GP_IU_CARD_CRYPTOGRAM_LEN]; + + NXSCP03_StaticCtx_t *pStatic_ctx = pAuthScp03->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthScp03->pDyn_ctx; + + /* clang-format off */ + const uint8_t commandCounter[16] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; + /* clang-format on */ + sss_status_t status = kStatus_SSS_Fail; + + if ((pStatic_ctx->Enc.keyStore == NULL) || (pStatic_ctx->Mac.keyStore == NULL) || + (pStatic_ctx->Dek.keyStore == NULL) || (pDyn_ctx->Enc.keyStore == NULL) || (pDyn_ctx->Mac.keyStore == NULL) || + (pDyn_ctx->Rmac.keyStore == NULL)) { + LOG_E("nxScp03_GP_InitializeUpdate fails Invalid objects sent %04X", status); + return status; + } + LOG_D("FN: %s", __FUNCTION__); + /* Get a random host challenge */ +#ifndef INITIAL_HOST_CHALLANGE + status = sss_host_rng_context_init(&rngctx, pStatic_ctx->Enc.keyStore->session); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = sss_host_rng_get_random(&rngctx, hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + LOG_MAU8_D(" Output: hostChallenge", hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + + sss_host_rng_context_free(&rngctx); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); +#endif + + status = nxScp03_GP_InitializeUpdate(se05xSession, + hostChallenge, + sizeof(hostChallenge), + keyDivData, + &keyDivDataLen, + keyInfo, + &keyInfoLen, + cardChallenge, + &cardChallengeLen, + cardCryptoGram, + &cardCryptoGramLen, + seqCounter, + &seqCounterLen, + pStatic_ctx->keyVerNo); + + if (status != kStatus_SSS_Success) { + LOG_E("nxScp03_GP_InitializeUpdate fails with Status %04X", status); + return status; + } + + status = nxScp03_HostLocal_CalculateSessionKeys(pAuthScp03, hostChallenge, cardChallenge); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = nxScp03_HostLocal_VerifyCardCryptogram(&pDyn_ctx->Mac, hostChallenge, cardChallenge, cardCryptoGram); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D("cardCryptoGram", cardCryptoGram, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + + LOG_D("CardCryptogram verified successfully...Calculate HostCryptogram"); + status = nxScp03_HostLocal_CalculateHostCryptogram(&pDyn_ctx->Mac, hostChallenge, cardChallenge, hostCryptogram); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_AU8_D(hostCryptogram, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + + status = nxScp03_GP_ExternalAuthenticate(se05xSession, &pDyn_ctx->Mac, pDyn_ctx->MCV, hostCryptogram); + if (status != kStatus_SSS_Success) { + LOG_E("GP_ExternalAuthenticate fails with Status %04X", status); + return status; + } + else { + // At this stage we have authenticated successfully. + status = kStatus_SSS_Success; + pDyn_ctx->SecurityLevel = (C_MAC | C_ENC | R_MAC | R_ENC); + memcpy(pDyn_ctx->cCounter, commandCounter, AES_KEY_LEN_nBYTE); + LOG_D("Authentication Successful!!!"); + } + +exit: + return status; +} + +static sss_status_t nxScp03_GP_ExternalAuthenticate( + pSe05xSession_t se05xSession, sss_object_t *keyObj, uint8_t *updateMCV, uint8_t *hostCryptogram) +{ + smStatus_t st = SM_NOT_OK; + uint8_t txBuf[64]; + uint8_t macToAdd[AES_KEY_LEN_nBYTE] = {0}; + + sss_mac_t macCtx; + sss_algorithm_t algorithm = kAlgorithm_SSS_CMAC_AES; + sss_mode_t mode = kMode_SSS_Mac; + size_t signatureLen = sizeof(macToAdd); + sss_status_t status = kStatus_SSS_Fail; + + tlvHeader_t hdr = { + {CLA_GP_7816 | CLA_GP_SECURITY_BIT, INS_GP_EXTERNAL_AUTHENTICATE, SECLVL_CDEC_RENC_CMAC_RMAC, 0x00}}; + + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input: hostCryptogram", hostCryptogram, SCP_COMMAND_MAC_SIZE); + + txBuf[0] = CLA_GP_7816 | CLA_GP_SECURITY_BIT; //Set CLA Byte + + txBuf[1] = INS_GP_EXTERNAL_AUTHENTICATE; //Set INS Byte + txBuf[2] = SECLVL_CDEC_RENC_CMAC_RMAC; //Set Security Level + + txBuf[3] = 0x00; + txBuf[4] = 0x10; // The Lc value is set as-if the MAC has already been appended (SCP03 spec p16. Fig.6-1) + memcpy(&txBuf[5], hostCryptogram, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + + LOG_D("Calculate the MAC on data"); + // Calculate the MAC value + status = sss_host_mac_context_init(&macCtx, keyObj->keyStore->session, keyObj, algorithm, mode); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = sss_host_mac_init(&macCtx); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* + * For the EXTERNAL AUTHENTICATE command MAC verification, the "MAC chaining value" is set to 16 + * bytes '00'. (SCP03 spec p16) + */ + memset(updateMCV, 0, SCP_MCV_LEN); + + status = sss_host_mac_update(&macCtx, updateMCV, AES_KEY_LEN_nBYTE); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = sss_host_mac_update(&macCtx, txBuf, 13); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + status = sss_host_mac_finish(&macCtx, macToAdd, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + LOG_MAU8_D(" Output: Calculated MAC", macToAdd, SCP_COMMAND_MAC_SIZE); + sss_host_mac_context_free(&macCtx); + + LOG_D("Add calculated MAC Value to cmd Data"); + memcpy(updateMCV, macToAdd, AES_KEY_LEN_nBYTE); + memcpy(&txBuf[5 + SCP_GP_IU_CARD_CRYPTOGRAM_LEN], macToAdd, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + + LOG_D("Sending GP External Authenticate Command !!!"); + st = DoAPDUTx_s_Case3(se05xSession, &hdr, &txBuf[5], 16); + if (st != SM_OK) { + LOG_E("GP_ExternalAuthenticate transmit failed"); + status = kStatus_SSS_Fail; + } + else { + status = kStatus_SSS_Success; + } + +exit: + return status; +} + +sss_status_t nxScp03_HostLocal_CalculateHostCryptogram( + sss_object_t *keyObj, uint8_t *hostChallenge, uint8_t *cardChallenge, uint8_t *hostCryptogram) +{ + uint8_t ddA[128]; + uint16_t ddALen = sizeof(ddA); + uint8_t context[128]; + uint16_t contextLen = 0; + uint8_t hostCryptogramFullLength[AES_KEY_LEN_nBYTE] = {0}; + uint32_t signatureLen = sizeof(hostCryptogramFullLength); + sss_status_t status = kStatus_SSS_Fail; + + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input:hostChallenge", hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + LOG_MAU8_D(" Input:cardChallenge", cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + + memcpy(context, hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + memcpy(&context[SCP_GP_HOST_CHALLENGE_LEN], cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + contextLen = SCP_GP_HOST_CHALLENGE_LEN + SCP_GP_CARD_CHALLENGE_LEN; + + nxScp03_setDerivationData( + ddA, &ddALen, DATA_HOST_CRYPTOGRAM, DATA_DERIVATION_L_64BIT, DATA_DERIVATION_KDF_CTR, context, contextLen); + + status = nxScp03_Generate_SessionKey(keyObj, ddA, ddALen, hostCryptogramFullLength, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + LOG_MAU8_D(" Output:hostCryptogram", hostCryptogramFullLength, AES_KEY_LEN_nBYTE); + + // Chop of the tail of the hostCryptogramFullLength + memcpy(hostCryptogram, hostCryptogramFullLength, SCP_GP_IU_CARD_CRYPTOGRAM_LEN); +exit: + return status; +} + +sss_status_t nxScp03_HostLocal_VerifyCardCryptogram( + sss_object_t *keyObj, uint8_t *hostChallenge, uint8_t *cardChallenge, uint8_t *cardCryptogram) +{ + uint8_t ddA[128]; + uint16_t ddALen = sizeof(ddA); + uint8_t context[128]; + uint16_t contextLen = 0; + uint8_t cardCryptogramFullLength[AES_KEY_LEN_nBYTE] = {0}; + uint32_t signatureLen = sizeof(cardCryptogramFullLength); + sss_status_t status = kStatus_SSS_Fail; + + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input:hostChallenge", hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + LOG_MAU8_D(" Input:cardChallenge", cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + + memcpy(context, hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + memcpy(&context[SCP_GP_HOST_CHALLENGE_LEN], cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + contextLen = SCP_GP_HOST_CHALLENGE_LEN + SCP_GP_CARD_CHALLENGE_LEN; + + nxScp03_setDerivationData( + ddA, &ddALen, DATA_CARD_CRYPTOGRAM, DATA_DERIVATION_L_64BIT, DATA_DERIVATION_KDF_CTR, context, contextLen); + + status = nxScp03_Generate_SessionKey(keyObj, ddA, ddALen, cardCryptogramFullLength, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + LOG_MAU8_D(" Output:cardCryptogram", cardCryptogramFullLength, AES_KEY_LEN_nBYTE); + + // Verify whether the 8 left most byte of cardCryptogramFullLength match cardCryptogram + if (memcmp(cardCryptogramFullLength, cardCryptogram, SCP_GP_IU_CARD_CRYPTOGRAM_LEN) != 0) + status = kStatus_SSS_Fail; +exit: + return status; +} + +static sss_status_t nxScp03_HostLocal_CalculateSessionKeys( + NXSCP03_AuthCtx_t *pAuthScp03, uint8_t *hostChallenge, uint8_t *cardChallenge) +{ + uint8_t ddA[128]; + uint16_t ddALen = sizeof(ddA); + uint8_t context[128]; + uint16_t contextLen = 0; + uint8_t sessionEncKey[AES_KEY_LEN_nBYTE]; + uint8_t sessionMacKey[AES_KEY_LEN_nBYTE]; + uint8_t sessionRmacKey[AES_KEY_LEN_nBYTE]; + uint32_t signatureLen = AES_KEY_LEN_nBYTE; + sss_status_t status = kStatus_SSS_Fail; + NXSCP03_StaticCtx_t *pStatic_ctx = pAuthScp03->pStatic_ctx; + NXSCP03_DynCtx_t *pDyn_ctx = pAuthScp03->pDyn_ctx; + + // Calculate the Derviation data + memcpy(context, hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + memcpy(&context[SCP_GP_HOST_CHALLENGE_LEN], cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + contextLen = SCP_GP_HOST_CHALLENGE_LEN + SCP_GP_CARD_CHALLENGE_LEN; + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input:hostChallenge", hostChallenge, SCP_GP_HOST_CHALLENGE_LEN); + LOG_MAU8_D(" Input:cardChallenge", cardChallenge, SCP_GP_CARD_CHALLENGE_LEN); + + /* Generation and Creation of Session ENC SSS Key Object */ + + // Set the Derviation data + LOG_D("Set the Derviation data to generate Session ENC key"); + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SENC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, context, contextLen); + // Calculate the Session-ENC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->Enc, ddA, ddALen, sessionEncKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D(" Output:sessionEncKey", sessionEncKey, AES_KEY_LEN_nBYTE); + + // Set the Session-ENC key + status = sss_host_key_store_set_key(pDyn_ctx->Enc.keyStore, &pDyn_ctx->Enc, sessionEncKey, 16, (16) * 8, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Generation and Creation of Session MAC SSS Key Object */ + + // Set the Derviation data + LOG_D("Set the Derviation data to generate Session MAC key"); + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SMAC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, context, contextLen); + // Calculate the Session-MAC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->Mac, ddA, ddALen, sessionMacKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D(" Output:sessionMacKey", sessionMacKey, AES_KEY_LEN_nBYTE); + + // Set the Session-MAC key + status = sss_host_key_store_set_key(pDyn_ctx->Mac.keyStore, &pDyn_ctx->Mac, sessionMacKey, 16, (16) * 8, NULL, 0); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + /* Generation and Creation of Session RMAC SSS Key Object */ + // Set the Derviation data + LOG_D("Set the Derviation data to generate Session RMAC key"); + nxScp03_setDerivationData( + ddA, &ddALen, DATA_DERIVATION_SRMAC, DATA_DERIVATION_L_128BIT, DATA_DERIVATION_KDF_CTR, context, contextLen); + // Calculate the Session-RMAC key + status = nxScp03_Generate_SessionKey(&pStatic_ctx->Mac, ddA, ddALen, sessionRmacKey, &signatureLen); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + LOG_MAU8_D(" Output:sessionRmacKey", sessionRmacKey, AES_KEY_LEN_nBYTE); + + // Set the Session-RMAC key + status = + sss_host_key_store_set_key(pDyn_ctx->Rmac.keyStore, &pDyn_ctx->Rmac, sessionRmacKey, 16, (16) * 8, NULL, 0); +exit: + return status; +} + +sss_status_t nxScp03_Generate_SessionKey( + sss_object_t *keyObj, uint8_t *inData, uint32_t inDataLen, uint8_t *outSignature, uint32_t *outSignatureLen) +{ + sss_mac_t macCtx; + sss_algorithm_t algorithm = kAlgorithm_SSS_CMAC_AES; + sss_mode_t mode = kMode_SSS_Mac; + sss_status_t status = kStatus_SSS_Fail; + size_t sigLen = *outSignatureLen; + LOG_D("FN: %s", __FUNCTION__); + LOG_MAU8_D(" Input: inData", inData, inDataLen); + // Init MAC Context + status = sss_host_mac_context_init(&macCtx, keyObj->keyStore->session, keyObj, algorithm, mode); + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + // Calculate Session key with MAC one go + status = sss_host_mac_one_go(&macCtx, inData, inDataLen, outSignature, &sigLen); + *outSignatureLen = (uint32_t)sigLen; + ENSURE_OR_GO_EXIT(status == kStatus_SSS_Success); + + LOG_MAU8_D(" Output:outSignature", outSignature, *outSignatureLen); + + // Free MAC context + sss_host_mac_context_free(&macCtx); +exit: + return status; +} + +static sss_status_t nxScp03_GP_InitializeUpdate(pSe05xSession_t se05xSession, + uint8_t *hostChallenge, + uint16_t hostChallengeLen, + uint8_t *keyDivData, + uint16_t *pKeyDivDataLen, + uint8_t *keyInfo, + uint16_t *pKeyInfoLen, + uint8_t *cardChallenge, + uint16_t *pCardChallengeLen, + uint8_t *cardCryptoGram, + uint16_t *pCardCryptoGramLen, + uint8_t *seqCounter, + uint16_t *pSeqCounterLen, + uint8_t keyVerNo) +{ + smStatus_t st = SM_NOT_OK; + uint8_t response[64]; + size_t responseLen = 64; + uint16_t parsePos = 0; + uint16_t sw = 0; + uint32_t iuResponseLenSmall = SCP_GP_IU_KEY_DIV_DATA_LEN + SCP_GP_IU_KEY_INFO_LEN + SCP_GP_CARD_CHALLENGE_LEN + + SCP_GP_IU_CARD_CRYPTOGRAM_LEN + SCP_GP_SW_LEN; + uint32_t iuResponseLenBig = SCP_GP_IU_KEY_DIV_DATA_LEN + SCP_GP_IU_KEY_INFO_LEN + SCP_GP_CARD_CHALLENGE_LEN + + SCP_GP_IU_CARD_CRYPTOGRAM_LEN + SCP_GP_IU_SEQ_COUNTER_LEN + SCP_GP_SW_LEN; + sss_status_t status = kStatus_SSS_Fail; + /* Default Key version no for applet scp is 0x00*/ + uint8_t keyVersion = 0x00; + if (se05xSession->authType == kSSS_AuthType_SCP03) { + /* Key version no. for Platform SCP03 passed by user*/ + keyVersion = keyVerNo; + /*Initialise update and external authenticate should go with auth type None + For Platform SCP03 as this is the authentication without session with JCOP */ + se05xSession->authType = kSSS_AuthType_None; + } + + tlvHeader_t hdr = {{CLA_GP_7816, INS_GP_INITIALIZE_UPDATE, keyVersion, 0x00}}; + + uint8_t cmdBuf[60]; + ENSURE_OR_GO_CLEANUP(hostChallengeLen == SCP_GP_HOST_CHALLENGE_LEN); + ENSURE_OR_GO_CLEANUP(*pKeyDivDataLen == SCP_GP_IU_KEY_DIV_DATA_LEN); + ENSURE_OR_GO_CLEANUP(*pKeyInfoLen == SCP_GP_IU_KEY_INFO_LEN); + ENSURE_OR_GO_CLEANUP(*pCardChallengeLen == SCP_GP_CARD_CHALLENGE_LEN); + ENSURE_OR_GO_CLEANUP(*pCardCryptoGramLen == SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + + LOG_D("FN: %s", __FUNCTION__); + LOG_D("Input:keyVersion %02x", keyVersion); + LOG_MAU8_D(" Input: hostChallenge", hostChallenge, hostChallengeLen); + LOG_D("Sending GP Initialize Update Command !!!"); + memcpy(cmdBuf, hostChallenge, hostChallengeLen); + st = DoAPDUTxRx_s_Case4(se05xSession, &hdr, cmdBuf, hostChallengeLen, response, &responseLen); + if (st != SM_OK) { + LOG_E("GP_InitializeUpdate Failure on communication Link %04X", st); + return status; + } + + // Parse Response + // The expected result length depends on random (HOST-Channel) or pseudo-random (ADMIN-Channel) challenge type. + // The pseudo-random challenge case also includes a 3 byte sequence counter + if ((responseLen != iuResponseLenSmall) && (responseLen != iuResponseLenBig)) { + // Note: A response of length 2 (a proper SW) is also collapsed into return code SCP_FAIL + LOG_E("GP_InitializeUpdate Unexpected amount of data returned"); + return status; + } + + memcpy(keyDivData, response, SCP_GP_IU_KEY_DIV_DATA_LEN); + parsePos = SCP_GP_IU_KEY_DIV_DATA_LEN; + memcpy(keyInfo, &(response[parsePos]), SCP_GP_IU_KEY_INFO_LEN); + parsePos += SCP_GP_IU_KEY_INFO_LEN; + memcpy(cardChallenge, &(response[parsePos]), SCP_GP_CARD_CHALLENGE_LEN); + parsePos += SCP_GP_CARD_CHALLENGE_LEN; + memcpy(cardCryptoGram, &(response[parsePos]), SCP_GP_IU_CARD_CRYPTOGRAM_LEN); + parsePos += SCP_GP_IU_CARD_CRYPTOGRAM_LEN; + + // Construct Return Value + sw = (response[responseLen - 2] << 8) + response[responseLen - 1]; + if (sw == SM_OK) { + LOG_MAU8_D(" Output: keyDivData", keyDivData, *pKeyDivDataLen); + LOG_MAU8_D(" Output: keyInfo", keyInfo, *pKeyInfoLen); + LOG_MAU8_D(" Output: cardChallenge", cardChallenge, *pCardChallengeLen); + LOG_MAU8_D(" Output: cardCryptoGram", cardCryptoGram, *pCardCryptoGramLen); + status = kStatus_SSS_Success; + } +cleanup: + return status; +} + +void nxScp03_setDerivationData(uint8_t ddA[], + uint16_t *pDdALen, + uint8_t ddConstant, + uint16_t ddL, + uint8_t iCounter, + uint8_t *context, + uint16_t contextLen) +{ + LOG_D("FN: %s", __FUNCTION__); + LOG_D("Input:ddConstant %02x", ddConstant); + LOG_D("Input:ddL %02x", ddL); + LOG_D("Input:iCounter %02x", iCounter); + LOG_MAU8_D(" Input: keyInfo", context, contextLen); + // SCPO3 spec p9&10 + memset(ddA, 0, DD_LABEL_LEN - 1); + ddA[DD_LABEL_LEN - 1] = ddConstant; + ddA[DD_LABEL_LEN] = 0x00; // Separation Indicator + ddA[DD_LABEL_LEN + 1] = (uint8_t)(ddL >> 8); + ddA[DD_LABEL_LEN + 2] = (uint8_t)ddL; + ddA[DD_LABEL_LEN + 3] = iCounter; + memcpy(&ddA[DD_LABEL_LEN + 4], context, contextLen); + *pDdALen = DD_LABEL_LEN + 4 + contextLen; + + LOG_MAU8_D("Output: KeyDivData", ddA, *pDdALen); +} + +#endif // SSS_HAVE_HOSTCRYPTO_ANY + +#endif // SSS_HAVE_APPLET_SE05X_IOT From 6dc397d9b538f20ef0bf659ec38cec3322e2f985 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 18 Jan 2022 14:59:17 +0100 Subject: [PATCH 121/227] Port sss hostLib to mbed-os --- .../hostlib/hostLib/libCommon/log/nxLog.c | 41 +- .../hostlib/hostLib/libCommon/smCom/smCom.c | 44 +- .../hostLib/platform/generic/sm_timer.c | 9 + .../hostlib/hostLib/platform/inc/ax_reset.h | 45 -- .../hostlib/hostLib/platform/inc/se05x_apis.h | 2 + .../hostlib/hostLib/platform/linux/i2c_a7.c | 385 ------------------ .../hostLib/platform/rsp/se05x_reset.c | 155 ------- .../hostlib/hostLib/platform/se05x_i2c.cpp | 59 +++ .../hostlib/hostLib/platform/se05x_power.cpp | 42 ++ .../COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c | 4 + .../sss/ex/mbedtls/ex_sss_ssl2.c | 3 + .../sss/inc/fsl_sss_se05x_types.h | 9 +- .../sss/port/default/fsl_sss_types.h | 7 +- .../sss/src/keystore/keystore_pc.c | 2 +- .../sss/src/se05x/fsl_sss_se05x_apis.c | 38 +- 15 files changed, 241 insertions(+), 604 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c index cfcfda378b2..c3122bb21d6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c @@ -20,7 +20,7 @@ extern "C" { #include "semphr.h" #endif -#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) || (__MBED__) #define USE_LOCK 1 #else #define USE_LOCK 0 @@ -107,10 +107,15 @@ static const char *szLevel[] = {"ERROR", "WARN ", "INFO ", "DEBUG"}; #if USE_RTOS static SemaphoreHandle_t gLogginglock; -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) #include /* Only for base session with os */ static pthread_mutex_t gLogginglock; +#elif __MBED__ +#include "cmsis_os2.h" +#include "mbed_rtos_storage.h" + static osSemaphoreId_t gLogginglock; + static mbed_rtos_storage_semaphore_t gLogginglock_mem; #endif static void nLog_AcquireLock(); static void nLog_ReleaseLock(); @@ -125,10 +130,14 @@ static void nLog_AcquireLock() if (xSemaphoreTake(gLogginglock, portMAX_DELAY) != pdTRUE) { PRINTF("Acquiring logging semaphore failed"); } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) if (pthread_mutex_lock(&gLogginglock) != 0) { PRINTF("Acquiring logging mutext failed"); } +#elif __MBED__ + if (osSemaphoreAcquire(gLogginglock, 0) != osOK) { + PRINTF("Acquiring logging mutext failed\n"); + } #endif } #endif @@ -142,10 +151,14 @@ static void nLog_ReleaseLock() if (xSemaphoreGive(gLogginglock) != pdTRUE) { PRINTF("Releasing logging semaphore failed"); } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) if (pthread_mutex_unlock(&gLogginglock) != 0) { PRINTF("Releasing logging semaphore failed"); } +#elif __MBED__ + if (osSemaphoreRelease(gLogginglock) != osOK) { + PRINTF("Releasing logging semaphore failed\n"); + } #endif } #endif @@ -160,11 +173,22 @@ uint8_t nLog_Init() PRINTF("xSemaphoreCreateMutex failed"); return 1; } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) if (pthread_mutex_init(&gLogginglock, NULL) != 0) { PRINTF("pthread_mutex_init failed"); return 1; } +#elif __MBED__ + osSemaphoreAttr_t attr; + attr.name = NULL; + attr.attr_bits = 0; + attr.cb_mem = &gLogginglock_mem; + attr.cb_size = sizeof gLogginglock_mem; + gLogginglock = osSemaphoreNew(1, 0, &attr); + if (gLogginglock == NULL) { + PRINTF("xSemaphoreCreateMutex failed"); + return 1; + } #endif lockInitialised = true; #endif @@ -179,8 +203,13 @@ void nLog_DeInit() vSemaphoreDelete(gLogginglock); gLogginglock = NULL; } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) pthread_mutex_destroy(&gLogginglock); +#elif __MBED__ + if (gLogginglock != NULL) { + osSemaphoreRelease(gLogginglock); + gLogginglock = NULL; + } #endif lockInitialised = false; #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c index 0412ae65d10..f7dfc1943cb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c @@ -25,13 +25,18 @@ #if USE_RTOS static SemaphoreHandle_t gSmComlock; -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) #include /* Only for base session with os */ static pthread_mutex_t gSmComlock; +#elif __MBED__ +#include "cmsis_os2.h" +#include "mbed_rtos_storage.h" + static osSemaphoreId_t gSmComlock; + static mbed_rtos_storage_semaphore_t gSmComlock_mem; #endif -#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) || (__MBED__) #define USE_LOCK 1 #else #define USE_LOCK 0 @@ -50,7 +55,7 @@ LOG_D("LOCK Released"); \ else \ LOG_D("LOCK Releasing failed"); -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) #define LOCK_TXN() \ LOG_D("Trying to Acquire Lock thread: %ld", pthread_self()); \ pthread_mutex_lock(&gSmComlock); \ @@ -60,6 +65,19 @@ LOG_D("Trying to Released Lock by thread: %ld", pthread_self()); \ pthread_mutex_unlock(&gSmComlock); \ LOG_D("LOCK Released by thread: %ld", pthread_self()); +#elif __MBED__ +#define LOCK_TXN() \ + LOG_D("Trying to Acquire Lock"); \ + if (osSemaphoreAcquire(gSmComlock, 0) == osOK) \ + LOG_D("LOCK Acquired"); \ + else \ + LOG_D("LOCK Acquisition failed"); +#define UNLOCK_TXN() \ + LOG_D("Trying to Released Lock"); \ + if (osSemaphoreRelease(gSmComlock) == osOK) \ + LOG_D("LOCK Released"); \ + else \ + LOG_D("LOCK Releasing failed"); #else #define LOCK_TXN() LOG_D("no lock mode"); #define UNLOCK_TXN() LOG_D("no lock mode"); @@ -81,12 +99,23 @@ U16 smCom_Init(ApduTransceiveFunction_t pTransceive, ApduTransceiveRawFunction_t LOG_E("\n xSemaphoreCreateMutex failed"); return ret; } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) if (pthread_mutex_init(&gSmComlock, NULL) != 0) { LOG_E("\n mutex init has failed"); return ret; } +#elif __MBED__ + osSemaphoreAttr_t attr; + attr.name = NULL; + attr.attr_bits = 0; + attr.cb_mem = &gSmComlock_mem; + attr.cb_size = sizeof gSmComlock_mem; + gSmComlock = osSemaphoreNew(1, 0, &attr); + if (gSmComlock == NULL) { + LOG_E("\n xSemaphoreCreateMutex failed"); + return 1; + } #endif pSmCom_Transceive = pTransceive; pSmCom_TransceiveRaw = pTransceiveRaw; @@ -101,8 +130,13 @@ void smCom_DeInit(void) vSemaphoreDelete(gSmComlock); gSmComlock = NULL; } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) pthread_mutex_destroy(&gSmComlock); +#elif __MBED__ + if (gSmComlock != NULL) { + osSemaphoreRelease(gSmComlock); + gSmComlock = NULL; + } #endif pSmCom_Transceive = NULL; pSmCom_TransceiveRaw = NULL; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c index 4196d778b38..78fbe9574c1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c @@ -24,6 +24,11 @@ #include "task.h" #endif +#if defined(__MBED__) +#include "mbed_thread.h" +#include "mbed_wait_api.h" +#endif + /* initializes the system tick counter * return 0 on succes, 1 on failure */ uint32_t sm_initSleep() @@ -51,6 +56,8 @@ void sm_sleep(uint32_t msec) usleep(microsec); #elif defined(USE_RTOS) && USE_RTOS == 1 vTaskDelay(1 >= pdMS_TO_TICKS(msec) ? 1 : pdMS_TO_TICKS(msec)); +#elif defined(__MBED__) + thread_sleep_for(msec); #else clock_t goal = msec + clock(); while (goal > clock()); @@ -70,6 +77,8 @@ void sm_usleep(uint32_t microsec) usleep(microsec); #elif defined(__OpenBSD__) #warning "No sm_usleep implemented" +#elif defined(__MBED__) + wait_us(microsec); #else //#warning "No sm_usleep implemented" #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h deleted file mode 100644 index 0ef2fb0f3e3..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/ax_reset.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * - * Copyright 2018-2019 NXP - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _AX_RESET_H -#define _AX_RESET_H - -#include "sm_types.h" - -/* - * Where applicable, Configure the PINs on the Host - * - */ -void axReset_HostConfigure(void); - -/* - * Where applicable, PowerCycle the SE - * - * Pre-Requistie: @ref axReset_Configure has been called - */ -void axReset_ResetPluseDUT(void); - -/* - * Where applicable, put SE in low power/standby mode - * - * Pre-Requistie: @ref axReset_Configure has been called - */ -void axReset_PowerDown(void); - -/* - * Where applicable, put SE in powered/active mode - * - * Pre-Requistie: @ref axReset_Configure has been called - */ -void axReset_PowerUp(void); - -/* - * Where applicable, Unconfigure the PINs on the Host - * - */ -void axReset_HostUnconfigure(void); - -#endif // _AX_RESET_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h index 8db632e6750..1c1da67dd5d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h @@ -14,5 +14,7 @@ #define SE_RESET_LOGIC 1 void se05x_ic_reset(void); +void se05x_ic_power_on(void); +void se05x_ic_power_off(void); #endif // _SE05X_API_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c deleted file mode 100644 index f28cf17e39d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/linux/i2c_a7.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * - * Copyright 2017-2020 NXP - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @par Description - * MCIMX6UL-EVK / MCIMX8M-EVK board specific & Generic i2c code - * @par History - * - **/ -#include "i2c_a7.h" -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -// #define NX_LOG_ENABLE_SMCOM_DEBUG 1 - -#include "nxLog_smCom.h" - -static char* default_axSmDevice_name = "/dev/i2c-1"; -static int default_axSmDevice_addr = 0x48; // 7-bit address - -#define DEV_NAME_BUFFER_SIZE 64 - -/** -* Opens the communication channel to I2C device -*/ -i2c_error_t axI2CInit(void **conn_ctx, const char *pDevName) -{ - unsigned long funcs; - int axSmDevice = 0; - char *pdev_name = NULL; - char *pdev_addr_str = NULL; - U32 dev_addr = 0x00; - char temp[DEV_NAME_BUFFER_SIZE] = { 0, }; - - if (pDevName != NULL && (strcasecmp("none", pDevName) != 0) ) { - if ((strlen(pDevName) + 1) < DEV_NAME_BUFFER_SIZE) { - memcpy(temp, pDevName, strlen(pDevName)); - temp[strlen(pDevName)] = '\0'; - } - else { - LOG_E("Connection string passed as argument is too long (%d).", strlen(pDevName)); - LOG_I("Pass i2c device address in the format :."); - LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); - } - - pdev_name = strtok(temp, ":"); - if (pdev_name == NULL) { - perror("Invalid connection string"); - LOG_I("Pass i2c device address in the format :."); - LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); - return I2C_FAILED; - } - - pdev_addr_str = strtok(NULL, ":"); - if (pdev_addr_str != NULL) { - dev_addr = strtol(pdev_addr_str, NULL, 0); - } - else { - dev_addr = default_axSmDevice_addr; - } - } - else { - pdev_name = default_axSmDevice_name; - dev_addr = default_axSmDevice_addr; - } - - LOG_D("I2CInit: opening %s\n", pdev_name); - - if ((axSmDevice = open(pdev_name, O_RDWR)) < 0) - { - LOG_E("opening failed..."); - perror("Failed to open the i2c bus"); - LOG_I("Pass i2c device address in the format :."); - LOG_I("Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1"); - return I2C_FAILED; - } - - if (ioctl(axSmDevice, I2C_SLAVE, dev_addr) < 0) - { - LOG_E("I2C driver failed setting address\n"); - } - - // clear PEC flag - if (ioctl(axSmDevice, I2C_PEC, 0) < 0) - { - LOG_E("I2C driver: PEC flag clear failed\n"); - } - else - { - LOG_D("I2C driver: PEC flag cleared\n"); - } - - // Query functional capacity of I2C driver - if (ioctl(axSmDevice, I2C_FUNCS, &funcs) < 0) - { - LOG_E("Cannot get i2c adapter functionality\n"); - close(axSmDevice); - return I2C_FAILED; - } - else - { - if (funcs & I2C_FUNC_I2C) - { - LOG_D("I2C driver supports plain i2c-level commands.\n"); -#if defined(SCI2C) //if SCI2C is enabled - if ( (funcs & I2C_FUNC_SMBUS_READ_BLOCK_DATA) == I2C_FUNC_SMBUS_READ_BLOCK_DATA ) - { - LOG_D("I2C driver supports Read Block.\n"); - } - else - { - LOG_E("I2C driver does not support Read Block!\n"); - close(axSmDevice); - return I2C_FAILED; - } -#endif - } - else - { - LOG_E("I2C driver CANNOT support plain i2c-level commands!\n"); - close(axSmDevice); - return I2C_FAILED; - } - } - - *conn_ctx = malloc(sizeof(int)); - *(int*)(*conn_ctx) = axSmDevice; - return I2C_OK; -} - -/** -* Closes the communication channel to I2C device -*/ -void axI2CTerm(void* conn_ctx, int mode) -{ - AX_UNUSED_ARG(mode); - // printf("axI2CTerm (enter) i2c device = %d\n", *(int*)(conn_ctx)); - if (conn_ctx != NULL) { - if (close(*(int*)(conn_ctx)) != 0) { - LOG_E("Failed to close i2c device %d.\n", *(int*)(conn_ctx)); - } - else { - LOG_D("Close i2c device %d.\n", *(int*)(conn_ctx)); - } - free(conn_ctx); - } - // printf("axI2CTerm (exit)\n"); - return; -} - -#if defined(SCI2C) -/** - * Write a single byte to the slave device. - * In the context of the SCI2C protocol, this command is only invoked - * to trigger a wake-up of the attached secure module. As such this - * wakeup command 'wakes' the device, but does not receive a valid response. - * \note \par bus is currently not used to distinguish between I2C masters. -*/ -i2c_error_t axI2CWriteByte(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx) -{ - int nrWritten = -1; - i2c_error_t rv; - int axSmDevice = *(int*)conn_ctx; - - if (bus != I2C_BUS_0) - { - LOG_E("axI2CWriteByte on wrong bus %x (addr %x)\n", bus, addr); - } - - nrWritten = write(axSmDevice, pTx, 1); - if (nrWritten < 0) - { - // I2C_LOG_PRINTF("Failed writing data (nrWritten=%d).\n", nrWritten); - rv = I2C_FAILED; - } - else - { - if (nrWritten == 1) - { - rv = I2C_OK; - } - else - { - rv = I2C_FAILED; - } - } - - return rv; -} -#endif // defined(SCI2C) - -#if defined(SCI2C) || defined(T1oI2C) -i2c_error_t axI2CWrite(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, unsigned short txLen) -{ - int nrWritten = -1; - i2c_error_t rv; - int axSmDevice = *(int*)conn_ctx; -#ifdef LOG_I2C - int i = 0; -#endif - - if(pTx == NULL || txLen > MAX_DATA_LEN) - { - return I2C_FAILED; - } - - if (bus != I2C_BUS_0) - { - LOG_E("axI2CWrite on wrong bus %x (addr %x)\n", bus, addr); - } - LOG_MAU8_D("TX (axI2CWrite) > ",pTx,txLen); - nrWritten = write(axSmDevice, pTx, txLen); - if (nrWritten < 0) - { - LOG_E("Failed writing data (nrWritten=%d).\n", nrWritten); - rv = I2C_FAILED; - } - else - { - if (nrWritten == txLen) // okay - { - rv = I2C_OK; - } - else - { - rv = I2C_FAILED; - } - } - LOG_D("Done with rv = %02x ", rv); - - return rv; -} -#endif // defined(SCI2C) || defined(T1oI2C) - -#if defined(SCI2C) -i2c_error_t axI2CWriteRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, - unsigned short txLen, unsigned char * pRx, unsigned short * pRxLen) -{ - struct i2c_rdwr_ioctl_data packets; - struct i2c_msg messages[2]; - int r = 0; - int i = 0; - int axSmDevice = *(int*)conn_ctx; - - if(pTx == NULL || txLen > MAX_DATA_LEN) - { - return I2C_FAILED; - } - - if(pRx == NULL || *pRxLen > MAX_DATA_LEN) - { - return I2C_FAILED; - } - - if (bus != I2C_BUS_0) // change if bus 0 is not the correct bus - { - LOG_E("axI2CWriteRead on wrong bus %x (addr %x)\n", bus, addr); - } - - messages[0].addr = default_axSmDevice_addr; - messages[0].flags = 0; - messages[0].len = txLen; - messages[0].buf = pTx; - - // NOTE: - // By setting the 'I2C_M_RECV_LEN' bit in 'messages[1].flags' one ensures - // the I2C Block Read feature is used. - messages[1].addr = default_axSmDevice_addr; - messages[1].flags = I2C_M_RD | I2C_M_RECV_LEN; - messages[1].len = 256; - messages[1].buf = pRx; - messages[1].buf[0] = 1; - - // NOTE: - // By passing the two message structures via the packets structure as - // a parameter to the ioctl call one ensures a Repeated Start is triggered. - packets.msgs = messages; - packets.nmsgs = 2; - - LOG_MAU8_D("TX (axI2CWriteRead ) > ",&packets.msgs[0].buf[i], txLen); - - // Send the request to the kernel and get the result back - r = ioctl(axSmDevice, I2C_RDWR, &packets); - - // NOTE: - // The ioctl return value in case of a NACK on the write address is '-1' - // This impacts the error handling routine of the caller. - // If possible distinguish between a general I2C error and a NACK on address - // The way to do this is platform specific (depends on I2C bus driver). - if (r < 0) - { - // LOG_E("axI2CWriteRead: ioctl cmd I2C_RDWR fails with value %d (errno: 0x%08X)\n", r, errno); - // perror("Errorstring: "); -#ifdef PLATFORM_IMX - #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0) - #define E_NACK_I2C_IMX ENXIO - // #warning "ENXIO" - #else - #define E_NACK_I2C_IMX EIO - // #warning "EIO" - #endif // LINUX_VERSION_CODE - // In case of IMX, errno == E_NACK_I2C_IMX is not exclusively bound to NACK on address, - // it can also signal a NACK on a data byte - if (errno == E_NACK_I2C_IMX) { - // I2C_LOG_PRINTF("axI2CWriteRead: ioctl signal NACK (errno = %d)\n", errno); - return I2C_NACK_ON_ADDRESS; - } - else { - // printf("axI2CWriteRead: ioctl error (errno = %d)\n", errno); - return I2C_FAILED; - } -#else - // I2C_LOG_PRINTF("axI2CWriteRead: ioctl cmd I2C_RDWR fails with value %d (errno: 0x%08X)\n", r, errno); - return I2C_FAILED; -#endif // PLATFORM_IMX - } - else - { - int rlen = packets.msgs[1].buf[0]+1; - - //I2C_LOG_PRINTF("packets.msgs[1].len is %d \n", packets.msgs[1].len); - LOG_MAU8_D("RX (axI2CWriteRead) < ",&packets.msgs[1].buf[i], rlen); - for (i = 0; i < rlen; i++) - { - pRx[i] = packets.msgs[1].buf[i]; - } - *pRxLen = rlen; - } - - return I2C_OK; -} -#endif // defined(SCI2C) - -#ifdef T1oI2C -i2c_error_t axI2CRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pRx, unsigned short rxLen) -{ - int nrRead = -1; - i2c_error_t rv; - int axSmDevice = *(int*)conn_ctx; - - if(pRx == NULL || rxLen > MAX_DATA_LEN) - { - return I2C_FAILED; - } - - if (bus != I2C_BUS_0) - { - LOG_E("axI2CRead on wrong bus %x (addr %x)\n", bus, addr); - } - - nrRead = read(axSmDevice, pRx, rxLen); - if (nrRead < 0) - { - //LOG_E("Failed Read data (nrRead=%d).\n", nrRead); - rv = I2C_FAILED; - } - else - { - if (nrRead == rxLen) // okay - { - rv = I2C_OK; - } - else - { - rv = I2C_FAILED; - } - } - LOG_D("Done with rv = %02x ", rv); - LOG_MAU8_D("TX (axI2CRead): ",pRx,rxLen); - return rv; -} -#endif // T1oI2C diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c deleted file mode 100644 index 6d5fc8015d3..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/rsp/se05x_reset.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * - * Copyright 2019 NXP - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include "sm_timer.h" -#include "ax_reset.h" -#include "se05x_apis.h" - -#define EN_PIN 22 - -void axReset_HostConfigure() -{ - int fd; - char buf[50]; - /* Open export file to export GPIO */ - fd = open("/sys/class/gpio/export", O_WRONLY); - if (fd < 0) { - perror("Failed to open GPIO export file "); - return; - } - /* Export GPIO pin to toggle */ - snprintf(buf, sizeof(buf), "%d", EN_PIN); - if (write(fd, buf, strlen(buf)) < 1) { - perror("Failed to export Enable pin "); - goto exit; - } - close(fd); - - /* Open direction file to configure GPIO direction */ - snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/direction", EN_PIN); - fd = open(buf, O_WRONLY); - if (fd < 0) { - sm_usleep(1000 * 1000); - fd = open(buf, O_WRONLY); - if (fd < 0) { - axReset_HostUnconfigure(); - perror("Failed to open GPIO direction file "); - return; - } - } - /* Configure direction of exported GPIO */ - if (write(fd, "out", 3) < 1) { - perror("Failed to Configure Enable pin "); - axReset_HostUnconfigure(); - goto exit; - } - -exit: - close(fd); - return; -} - -void axReset_HostUnconfigure() -{ - int fd; - char buf[50]; - fd = open("/sys/class/gpio/unexport", O_WRONLY); - if (fd < 0) { - perror("Failed to open unexport file "); - return; - } - - snprintf(buf, sizeof(buf), "%d", EN_PIN); - if (write(fd, buf, strlen(buf)) < 1) { - perror("Failed to unexport GPIO "); - } - - close(fd); - return; -} - -/* - * Where applicable, PowerCycle the SE - * - * Pre-Requisite: @ref axReset_Configure has been called - */ -void axReset_ResetPluseDUT() -{ - axReset_PowerDown(); - sm_usleep(2000); - axReset_PowerUp(); - return; -} - -/* - * Where applicable, put SE in low power/standby mode - * - * Pre-Requisite: @ref axReset_Configure has been called - */ -void axReset_PowerDown() -{ - int fd; - char buf[50]; - char logic[10]; - snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/value", EN_PIN); - fd = open(buf, O_WRONLY); - if (fd < 0) { - perror("Failed to open GPIO value file "); - axReset_HostUnconfigure(); - return; - } - - snprintf(logic, sizeof(logic), "%d", !SE_RESET_LOGIC); - if (write(fd, logic, 1) < 1) { - perror("Failed to toggle GPIO high "); - axReset_HostUnconfigure(); - } - - close(fd); -} - -/* - * Where applicable, put SE in powered/active mode - * - * Pre-Requisite: @ref axReset_Configure has been called - */ -void axReset_PowerUp() -{ - int fd; - char buf[50]; - char logic[10]; - snprintf(buf, sizeof(buf), "/sys/class/gpio/gpio%d/value", EN_PIN); - fd = open(buf, O_WRONLY); - if (fd < 0) { - perror("Failed to open GPIO value file "); - axReset_HostUnconfigure(); - return; - } - - snprintf(logic, sizeof(logic), "%d", SE_RESET_LOGIC); - if (write(fd, logic, 1) < 1) { - perror("Failed to toggle GPIO high "); - axReset_HostUnconfigure(); - } - - close(fd); -} - -#if SSS_HAVE_SE05X || SSS_HAVE_LOOPBACK - -void se05x_ic_reset() -{ - axReset_ResetPluseDUT(); - smComT1oI2C_ComReset(); - sm_usleep(3000); - return; -} - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp new file mode 100644 index 00000000000..575e087e81c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp @@ -0,0 +1,59 @@ +/* + * Copyright 2022 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_a7.h" +#include "mbed.h" + +static I2C * se05x_i2c; + +i2c_error_t axI2CInit(void **conn_ctx, const char *pDevName) +{ + se05x_i2c = new I2C(PB_7, PB_6); + if(se05x_i2c != NULL) + { + se05x_i2c->frequency(400000); + return I2C_OK; + } + return I2C_FAILED; +} + +void axI2CTerm(void* conn_ctx, int mode) +{ + if(se05x_i2c != NULL) + { + delete se05x_i2c; + } +} + +i2c_error_t axI2CWrite(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pTx, unsigned short txLen) +{ + if(se05x_i2c->write(addr, (const char *)pTx, txLen)) + { + return I2C_FAILED; + } + return I2C_OK; +} + +i2c_error_t axI2CRead(void* conn_ctx, unsigned char bus, unsigned char addr, unsigned char * pRx, unsigned short rxLen) +{ + if(se05x_i2c->read(addr, (char *)pRx, rxLen)) + { + return I2C_FAILED; + } + return I2C_OK; +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp new file mode 100644 index 00000000000..1c6af5a24e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp @@ -0,0 +1,42 @@ +/* + * Copyright 2022 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "se05x_apis.h" +#include "sm_timer.h" +#include "mbed.h" + +#define NICLA_VISION_SE05X_ENA_PIN PG_0 +#define PORTENTA_H7_SE05X_ENA_PIN PI_12 + +static DigitalOut se05x_ic_enable(PORTENTA_H7_SE05X_ENA_PIN, 0); + +void se05x_ic_reset(void) +{ + se05x_ic_power_off(); + sm_sleep(100); + se05x_ic_power_on(); +} + +void se05x_ic_power_on(void) +{ + se05x_ic_enable = 1; +} + +void se05x_ic_power_off(void) +{ + se05x_ic_enable = 0; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c index 97f9854fb7f..1a9c072d7bc 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c @@ -8,6 +8,8 @@ /* Includes */ /* ************************************************************************** */ +#if !defined(__MBED__) + #include #include #include @@ -173,3 +175,5 @@ sss_status_t ex_sss_entry(ex_sss_boot_ctx_t *pCtx) sss_asymmetric_context_free(&ctx_verify); return status; } + +#endif //__MBED__ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c index c7f878a2dbb..8b6071fac76 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c @@ -22,6 +22,8 @@ /* clang-format off */ +#if !defined(__MBED__) + #if defined(SSS_USE_FTR_FILE) #include "fsl_sss_ftr.h" #else @@ -2270,3 +2272,4 @@ MBEDTLS_SSL_CLI_C && MBEDTLS_NET_C && MBEDTLS_RSA_C && MBEDTLS_CTR_DRBG_C MBEDTLS_TIMING_C */ /* clang-format on */ +#endif //__MBED__ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h index 26a8e0d3fef..12cb2dd9a3f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h @@ -25,9 +25,12 @@ #include "se05x_const.h" #include "se05x_tlv.h" #include "sm_api.h" -#if (__GNUC__ && !AX_EMBEDDED) +#if (__GNUC__ && !AX_EMBEDDED && !__MBED__) #include /* Only for base session with os */ +#elif __MBED__ +#include "cmsis_os2.h" +#include "mbed_rtos_storage.h" #endif /* FreeRTOS includes. */ #if USE_RTOS @@ -101,8 +104,10 @@ typedef struct _sss_se05x_tunnel_context /** For systems where we potentially have multi-threaded operations, have a lock */ #if USE_RTOS SemaphoreHandle_t channelLock; -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) pthread_mutex_t channelLock; +#elif __MBED__ + osSemaphoreId_t channelLock; #endif } sss_se05x_tunnel_context_t; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h index 0fff01ab17e..969be876730 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h @@ -10,7 +10,7 @@ #include #include -#ifdef __STDC__ +#if (__STDC__ && !__MBED__) #include #endif @@ -26,11 +26,16 @@ #define ARRAY_SIZE(array) (sizeof(array) / (sizeof(array[0]))) #endif +#if __MBED__ +#include "mbed_assert.h" +#define assert_static(e) MBED_ASSERT(e) +#else #define assert_static(e) \ { \ char assert_static__[(e) ? 1 : -1]; \ assert_static__; \ } +#endif /** Compile time assert */ #define SSS_ASSERT(condition) assert_static(condition) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c index 002daae06ab..5e344549fd5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c @@ -34,7 +34,7 @@ #include "nxLog_sss.h" #include "sm_types.h" -#if (defined(MBEDTLS_FS_IO) && !AX_EMBEDDED) || SSS_HAVE_OPENSSL +#if (defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__) || SSS_HAVE_OPENSSL /* ************************************************************************** */ /* Local Defines */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c index 7613140051a..cabfdff7d3b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c @@ -51,7 +51,7 @@ extern "C" { else { \ LOG_D("LOCK Releasing failed"); \ } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) #define LOCK_TXN(lock) \ LOG_D("Trying to Acquire Lock thread: %ld", pthread_self()); \ pthread_mutex_lock(&lock); \ @@ -61,14 +61,31 @@ extern "C" { LOG_D("Trying to Released Lock by thread: %ld", pthread_self()); \ pthread_mutex_unlock(&lock); \ LOG_D("LOCK Released by thread: %ld", pthread_self()); +#elif __MBED__ +#define LOCK_TXN(lock) \ + LOG_D("Trying to Acquire Lock"); \ + if (osSemaphoreAcquire(lock, 0) == osOK) \ + LOG_D("LOCK Acquired"); \ + else \ + LOG_D("LOCK Acquisition failed"); +#define UNLOCK_TXN(lock) \ + LOG_D("Trying to Released Lock"); \ + if (osSemaphoreRelease(lock) == osOK) \ + LOG_D("LOCK Released"); \ + else \ + LOG_D("LOCK Releasing failed"); #endif -#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) +#if (__GNUC__ && !AX_EMBEDDED) || (USE_RTOS) || (__MBED__) #define USE_LOCK 1 #else #define USE_LOCK 0 #endif +#if __MBED__ +static mbed_rtos_storage_semaphore_t channelLock_mem; +#endif + static SE05x_ECSignatureAlgo_t se05x_get_ec_sign_hash_mode(sss_algorithm_t algorithm); /* Used during testing as well */ @@ -6231,7 +6248,7 @@ sss_status_t sss_se05x_tunnel_context_init(sss_se05x_tunnel_context_t *context, LOG_E("xSemaphoreCreateMutex failed"); return kStatus_SSS_Fail; } -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) if (pthread_mutex_init(&context->channelLock, NULL) != 0) { LOG_E("\n mutex init has failed"); return kStatus_SSS_Fail; @@ -6239,6 +6256,17 @@ sss_status_t sss_se05x_tunnel_context_init(sss_se05x_tunnel_context_t *context, else { LOG_D("Mutex Init successfull"); } +#elif __MBED__ + osSemaphoreAttr_t attr; + attr.name = NULL; + attr.attr_bits = 0; + attr.cb_mem = &channelLock_mem; + attr.cb_size = sizeof channelLock_mem; + context->channelLock = osSemaphoreNew(1, 0, &attr); + if (context->channelLock == NULL) { + LOG_E("xSemaphoreCreateMutex failed"); + return kStatus_SSS_Fail; + } #endif return retval; } @@ -6258,8 +6286,10 @@ void sss_se05x_tunnel_context_free(sss_se05x_tunnel_context_t *context) { #if USE_RTOS vSemaphoreDelete(context->channelLock); -#elif (__GNUC__ && !AX_EMBEDDED) +#elif (__GNUC__ && !AX_EMBEDDED && !__MBED__) pthread_mutex_destroy(&context->channelLock); +#elif __MBED__ + osSemaphoreRelease(context->channelLock); #endif memset(context, 0, sizeof(*context)); } From fc41f7ffa287b4280336247dccdb1114f2afd5c7 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 19 Jan 2022 14:17:07 +0100 Subject: [PATCH 122/227] Do not build ecdh.c from mbedtls stack if MBEDTLS_ECDH_ALT is defined --- connectivity/mbedtls/source/ecdh.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/connectivity/mbedtls/source/ecdh.c b/connectivity/mbedtls/source/ecdh.c index 9dfa8680637..6cb53b40154 100644 --- a/connectivity/mbedtls/source/ecdh.c +++ b/connectivity/mbedtls/source/ecdh.c @@ -27,7 +27,7 @@ #include "common.h" #if defined(MBEDTLS_ECDH_C) - +#if !defined(MBEDTLS_ECDH_ALT) #include "mbedtls/ecdh.h" #include "mbedtls/platform_util.h" #include "mbedtls/error.h" @@ -726,4 +726,5 @@ int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen, #endif } +#endif /* MBEDTLS_ECDH_ALT */ #endif /* MBEDTLS_ECDH_C */ From 75563328e3bb5b7010ade25035b6f0c0512e2d5a Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 19 Jan 2022 14:18:07 +0100 Subject: [PATCH 123/227] Enable MBEDTLS alternative implementation over SSS --- .../COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h index 7ad9a873d25..0113d794bca 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h @@ -172,7 +172,7 @@ */ /** Use SSS Layer ALT implementation */ -#define SSS_HAVE_MBEDTLS_ALT_SSS 0 +#define SSS_HAVE_MBEDTLS_ALT_SSS 1 /** Legacy implementation */ #define SSS_HAVE_MBEDTLS_ALT_A71CH 0 @@ -180,7 +180,7 @@ /** Not using any mbedTLS_ALT * * When this is selected, cloud demos can not work with mbedTLS */ -#define SSS_HAVE_MBEDTLS_ALT_NONE 1 +#define SSS_HAVE_MBEDTLS_ALT_NONE 0 #if (( 0 \ + SSS_HAVE_MBEDTLS_ALT_SSS \ From a1614740e435e833df6a65a20658ddb6deacbb70 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 09:52:58 +0100 Subject: [PATCH 124/227] Enable DEBUG log by default. To disable it define FLOW_SILENT macro --- .../hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h index 9e37d5616bb..1b0cee9dea5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h @@ -15,7 +15,7 @@ * - 0 => Disable Debug level logging. This has to be * enabled individually by other logging * header/source files */ -#define NX_LOG_ENABLE_DEFAULT_DEBUG 0 +#define NX_LOG_ENABLE_DEFAULT_DEBUG 1 /* Same as NX_LOG_ENABLE_DEFAULT_DEBUG but for Info Level */ #define NX_LOG_ENABLE_DEFAULT_INFO 1 From ce40d81423ddc8351b10f1836d81943f83e36a81 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 09:53:57 +0100 Subject: [PATCH 125/227] Add 1ms delays to let communication work also with debug disabled --- .../hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c index 4ee1665c42b..5f375185d2b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c @@ -134,7 +134,7 @@ int phPalEse_i2c_read(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToRead) ; int numRead = 0; LOG_D("%s Read Requested %d bytes ", __FUNCTION__, nNbBytesToRead); - //sm_sleep(ESE_POLL_DELAY_MS); + sm_sleep(ESE_POLL_DELAY_MS); while (numRead != nNbBytesToRead) { ret = axI2CRead(pDevHandle, I2C_BUS_0, SMCOM_I2C_ADDRESS, pBuffer, nNbBytesToRead); if (ret != I2C_OK) { @@ -143,7 +143,7 @@ int phPalEse_i2c_read(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToRead) retryCount++; /* 1ms delay to give ESE polling delay */ /*i2c driver back off delay is providing 1ms wait time so ignoring waiting time at this level*/ - //sm_sleep(ESE_POLL_DELAY_MS); + sm_sleep(ESE_POLL_DELAY_MS); LOG_D("_i2c_read() failed. Going to retry, counter:%d !", retryCount); continue; } @@ -186,7 +186,7 @@ int phPalEse_i2c_write(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToWrite) retryCount++; /* 1ms delay to give ESE polling delay */ /*i2c driver back off delay is providing 1ms wait time so ignoring waiting time at this level*/ - //sm_sleep(ESE_POLL_DELAY_MS); + sm_sleep(ESE_POLL_DELAY_MS); LOG_D("_i2c_write() failed. Going to retry, counter:%d !", retryCount); continue; } @@ -194,7 +194,7 @@ int phPalEse_i2c_write(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToWrite) } else { numWrote = nNbBytesToWrite; - //sm_sleep(ESE_POLL_DELAY_MS); + sm_sleep(ESE_POLL_DELAY_MS); break; } } while (ret != I2C_OK); From 3f266fc95d0604789e6f2eebbb21bfee59d656f2 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 10:10:46 +0100 Subject: [PATCH 126/227] Make i2c and resets pin configurable --- .../COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp | 4 ++-- .../COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp | 5 +---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp index 575e087e81c..07ef0db92bb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp @@ -22,10 +22,10 @@ static I2C * se05x_i2c; i2c_error_t axI2CInit(void **conn_ctx, const char *pDevName) { - se05x_i2c = new I2C(PB_7, PB_6); + se05x_i2c = new I2C(MBED_CONF_TARGET_SE050_SDA, MBED_CONF_TARGET_SE050_SCL); if(se05x_i2c != NULL) { - se05x_i2c->frequency(400000); + se05x_i2c->frequency(MBED_CONF_TARGET_SE050_I2C_FREQ); return I2C_OK; } return I2C_FAILED; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp index 1c6af5a24e5..0d7ffcac8c7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp @@ -19,10 +19,7 @@ #include "sm_timer.h" #include "mbed.h" -#define NICLA_VISION_SE05X_ENA_PIN PG_0 -#define PORTENTA_H7_SE05X_ENA_PIN PI_12 - -static DigitalOut se05x_ic_enable(PORTENTA_H7_SE05X_ENA_PIN, 0); +static DigitalOut se05x_ic_enable(MBED_CONF_TARGET_SE050_ENA, 0); void se05x_ic_reset(void) { From f08dc49f252f73cb5002c40e2c347dbd8d66cabd Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 10:02:13 +0100 Subject: [PATCH 127/227] Add missing __MBED__ define to avoid build mbedtls keystore --- .../sss/src/mbedtls/fsl_sss_mbedtls_apis.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c index b8d4e82cfc0..614e8f0abb1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c @@ -226,7 +226,7 @@ sss_status_t sss_mbedtls_key_object_allocate_handle(sss_mbedtls_object_t *keyObj retval = kStatus_SSS_Fail; goto cleanup; } -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ if (options == kKeyObject_Mode_Persistent) { uint32_t i; sss_mbedtls_object_t **ks; @@ -257,7 +257,7 @@ sss_status_t sss_mbedtls_key_object_allocate_handle(sss_mbedtls_object_t *keyObj sss_status_t sss_mbedtls_key_object_get_handle(sss_mbedtls_object_t *keyObject, uint32_t keyId) { sss_status_t retval = kStatus_SSS_Fail; -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ uint32_t i; ENSURE_OR_GO_CLEANUP(keyObject); ENSURE_OR_GO_CLEANUP(keyObject->keyStore); @@ -663,7 +663,7 @@ sss_status_t sss_mbedtls_key_store_allocate(sss_mbedtls_key_store_t *keyStore, u ENSURE_OR_GO_CLEANUP(keyStore); ENSURE_OR_GO_CLEANUP(keyStore->session); -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ /* This function is called once per session so keystore object and shadow objects Should be equal to Null */ ENSURE_OR_GO_CLEANUP(keyStore->objects == NULL); @@ -692,7 +692,7 @@ sss_status_t sss_mbedtls_key_store_save(sss_mbedtls_key_store_t *keyStore) ENSURE_OR_GO_CLEANUP(keyStore); ENSURE_OR_GO_CLEANUP(keyStore->session); -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ ENSURE_OR_GO_CLEANUP(keyStore->session->szRootPath) ENSURE_OR_GO_CLEANUP(keyStore->objects) uint32_t i; @@ -712,7 +712,7 @@ sss_status_t sss_mbedtls_key_store_load(sss_mbedtls_key_store_t *keyStore) sss_status_t retval = kStatus_SSS_Fail; ENSURE_OR_GO_CLEANUP(keyStore); ENSURE_OR_GO_CLEANUP(keyStore->session); -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ if (keyStore->objects == NULL) { sss_mbedtls_key_store_allocate(keyStore, 0); } @@ -921,7 +921,7 @@ sss_status_t sss_mbedtls_key_store_erase_key(sss_mbedtls_key_store_t *keyStore, ENSURE_OR_GO_EXIT((keyObject->accessRights & kAccessPermission_SSS_Delete)); if (keyObject->keyMode == kKeyObject_Mode_Persistent) { -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ unsigned int i = 0; /* first check if key exists delete key from shadow KS*/ retval = ks_common_remove_fat(keyObject->keyStore->keystore_shadow, keyObject->keyId); @@ -946,7 +946,7 @@ sss_status_t sss_mbedtls_key_store_erase_key(sss_mbedtls_key_store_t *keyStore, retval = kStatus_SSS_Success; } -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ cleanup: #endif exit: @@ -956,7 +956,7 @@ sss_status_t sss_mbedtls_key_store_erase_key(sss_mbedtls_key_store_t *keyStore, void sss_mbedtls_key_store_context_free(sss_mbedtls_key_store_t *keyStore) { -#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED +#if defined(MBEDTLS_FS_IO) && !AX_EMBEDDED && !__MBED__ if (NULL != keyStore->objects) { uint32_t i; for (i = 0; i < keyStore->max_object_count; i++) { From cb121838ea93483ee2147019231af2dd230b7271 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 14:23:36 +0100 Subject: [PATCH 128/227] Moved COMPONENT_SE050 from TARGET_PORTENTA_H7 to STM32H747xI plugAndTrust: rename log folder to nxlog and revert 86184757e34 --- .gitignore | 1 + .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/Apache_2_0.txt | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/BSD3_license.txt | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/ChangeLog.md | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/LICENSE | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/README.rst | 0 .../COMPONENT_SE050/ecc_example/CMakeLists.txt | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/fsl_sss_ftr.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h | 0 .../hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/scp.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h | 0 .../hostlib/hostLib/inc/se05x_ecc_curves_values.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h | 0 .../COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h | 0 .../hostlib/hostLib/libCommon/infra/global_platf.c | 0 .../hostlib/hostLib/libCommon/infra/global_platf.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h | 0 .../hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog.c | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_App.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_DefaultConfig.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_hostLib.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_mbedtls.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_scp.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_smCom.h | 0 .../hostlib/hostLib/libCommon/nxlog}/nxLog_sss.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h | 0 .../hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c | 0 .../COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h | 0 .../hostlib/hostLib/libCommon/smCom/smComT1oI2C.c | 0 .../hostlib/hostLib/libCommon/smCom/smComT1oI2C.h | 0 .../COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c | 0 .../COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp | 0 .../COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp | 0 .../COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c | 0 .../COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c | 0 .../COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c | 0 .../hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h | 0 .../hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h | 0 .../COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c | 0 .../COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h | 0 .../hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h | 0 .../hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h | 0 .../COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt | 0 .../COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c | 0 .../COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h | 0 .../COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h | 0 .../COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_boot.c | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c | 0 .../COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c | 0 .../{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sscp.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_api.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_config.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_policy.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_sscp.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_user_types.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h | 0 .../COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c | 0 .../sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c | 0 .../COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h | 0 .../COMPONENT_SE050/sss/port/default/fsl_sss_types.h | 0 .../COMPONENT_SE050/sss/src/fsl_sss_apis.c | 0 .../COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c | 0 .../COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c | 0 .../COMPONENT_SE050/sss/src/keystore/keystore_cmn.c | 0 .../COMPONENT_SE050/sss/src/keystore/keystore_openssl.c | 0 .../COMPONENT_SE050/sss/src/keystore/keystore_pc.c | 0 .../COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c | 0 .../COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c | 0 .../COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c | 0 .../COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c | 0 .../COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c | 0 .../COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c | 0 .../COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c | 0 141 files changed, 1 insertion(+) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/Apache_2_0.txt (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/BSD3_license.txt (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/ChangeLog.md (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/LICENSE (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/README.rst (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/ecc_example/CMakeLists.txt (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/fsl_sss_ftr.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/scp.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_App.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_DefaultConfig.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_hostLib.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_mbedtls.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_scp.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_smCom.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log => COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog}/nxLog_sss.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sscp.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_api.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_config.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_policy.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/port/default/fsl_sss_types.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/fsl_sss_apis.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/keystore/keystore_pc.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/{TARGET_PORTENTA_H7 => }/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c (100%) diff --git a/.gitignore b/.gitignore index 7a68e77ae89..3e907cf52c9 100644 --- a/.gitignore +++ b/.gitignore @@ -90,6 +90,7 @@ tags features/FEATURE_BLE/targets/TARGET_CORDIO/stack_backup/ .pytest_cache +log # Icetea related file test_suite.json diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/Apache_2_0.txt similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/Apache_2_0.txt rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/Apache_2_0.txt diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/BSD3_license.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/BSD3_license.txt similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/BSD3_license.txt rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/BSD3_license.txt diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/ChangeLog.md similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ChangeLog.md rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/ChangeLog.md diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/LICENSE similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/LICENSE rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/LICENSE diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/README.rst similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/README.rst rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/README.rst diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ecc_example/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/ecc_example/CMakeLists.txt similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/ecc_example/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/ecc_example/CMakeLists.txt diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/fsl_sss_ftr.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/fsl_sss_ftr.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/fsl_sss_ftr.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/fsl_sss_ftr.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/Applet_SE050_Ver.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_HostLib_Ver.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/PlugAndTrust_Pkg_Ver.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxEnsure.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Const.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/nxScp03_Types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/scp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/scp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/scp.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/scp.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_const.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_inc.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ecc_curves_values.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_enums.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_ftr.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/se05x_tlv.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/inc/sm_const.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/global_platf.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_apdu.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_api.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_connect.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_errors.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_printf.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/infra/sm_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxScp/nxScp03_Com.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_App.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_App.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_App.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_App.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_DefaultConfig.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_DefaultConfig.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_DefaultConfig.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_hostLib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_hostLib.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_hostLib.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_hostLib.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_mbedtls.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_mbedtls.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_mbedtls.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_mbedtls.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_scp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_scp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_scp.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_scp.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_smCom.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_smCom.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_smCom.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_smCom.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_sss.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_sss.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/log/nxLog_sss.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/nxlog/nxLog_sss.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseStatus.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phEseTypes.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEsePal_i2c.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEseProto7816_3.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Api.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/T1oI2C/phNxpEse_Internal.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/apduComm.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smCom.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/libCommon/smCom/smComT1oI2C.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/ecdh_alt.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/mbedtls/src/rsa_alt.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/generic/sm_timer.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/i2c_a7.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/se05x_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_printf.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/inc/sm_timer.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/se05x_i2c.cpp diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/platform/se05x_power.cpp diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_ECC_curves.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_mw.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x/src/se05x_tlv.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_04_xx_APDU_impl.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/hostlib/hostLib/se05x_03_xx_xx/se05x_APDU_impl.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/mbedtls_cli_srv/CMakeLists.txt diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/ecc/ex_sss_ecc.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_scp03_puf.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_auth.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_boot.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_main_inc_linux.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_objid.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_ports.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_scp03_keys.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/inc/ex_sss_tp_scp03_keys.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/mbedtls/ex_sss_ssl2.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot_connectstring.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_boot_int.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_scp03_auth.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_se05x.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/ex/src/ex_sss_se05x_auth.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sscp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sscp.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sscp.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_api.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_api.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_api_ver.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_config.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_config.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_config.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_ftr_default.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_keyid_map.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_lpc55s_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_mbedtls_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_openssl_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_openssl_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_policy.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_policy.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_policy.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_policy.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_scp03.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_se05x_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_sscp.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_user_apis.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_user_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_util_asn1_der.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/inc/fsl_sss_util_rsa_sign_utils.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdh_alt_ax.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecdsa_verify_alt.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/ecp_alt.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_alt.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/port/ksdk/ecp_curves_alt.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/rsa_alt.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_rsa.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/plugin/mbedtls/sss_mbedtls_x86_config.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/port/default/fsl_sss_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/port/default/fsl_sss_types.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/port/default/fsl_sss_types.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_apis.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_apis.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_apis.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_util_asn1_der.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/fsl_sss_util_rsa_sign_utils.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_cmn.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_openssl.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_pc.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/keystore/keystore_pc.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/keystore/keystore_pc.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/openssl/fsl_sss_openssl_apis.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_apis.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_eckey.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_mw.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_policy.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/se05x/fsl_sss_se05x_scp03.c From 01ce92bb04d45102aa279897e28e0a0a4963145e Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 14:24:59 +0100 Subject: [PATCH 129/227] NICLA_VISION: Enable component SE050 --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 5bfe2292a04..08443a97f9e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3618,7 +3618,8 @@ "QSPIF", "WHD", "4343W_FS", - "CYW43XXX" + "CYW43XXX", + "SE050" ], "macros_add": [ "MBEDTLS_FS_IO", From a8d6db44ffe69a3cb8c322909ec00b9feaf4fc28 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 14:26:18 +0100 Subject: [PATCH 130/227] NICLA_VISION: Add configuration macros used for APDU communication protocol --- targets/targets.json | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 08443a97f9e..90233a1e335 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3626,7 +3626,9 @@ "MBEDTLS_SHA1_C", "CM4_BOOT_BY_APPLICATION", "QSPI_NO_SAMPLE_SHIFT", - "CYW43XXX_UNBUFFERED_UART" + "CYW43XXX_UNBUFFERED_UART", + "T1oI2C", + "T1oI2C_UM11225" ], "device_has_add": [ "USBDEVICE", From 19569825ee77f8d2a7377c5e776c8d166e1430c5 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 14:30:07 +0100 Subject: [PATCH 131/227] NICLA_VISION: Add configuration for reset pin and i2c --- targets/targets.json | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index 90233a1e335..88efda3f330 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3603,6 +3603,22 @@ "usb_speed": { "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", "value": "USE_USB_OTG_HS" + }, + "se050_ena": { + "help": "SE050 ENA Pin", + "value" : "PG_0" + }, + "se050_sda": { + "help": "SE050 I2C SDA Pin", + "value" : "PF_0" + }, + "se050_scl": { + "help": "SE050 I2C SCL Pin", + "value" : "PF_1" + }, + "se050_i2c_freq": { + "help": "SE050 I2C bus frequency", + "value" : "1000000" } }, "overrides": { From de99bbf08b423fd6dc88bc2735070f8faf988646 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Feb 2022 15:04:02 +0100 Subject: [PATCH 132/227] NICLA_VISION: DISABLE debug log with FLOW_SILENT macro --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 88efda3f330..050ce7e9325 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3644,7 +3644,8 @@ "QSPI_NO_SAMPLE_SHIFT", "CYW43XXX_UNBUFFERED_UART", "T1oI2C", - "T1oI2C_UM11225" + "T1oI2C_UM11225", + "FLOW_SILENT" ], "device_has_add": [ "USBDEVICE", From 17c7616bce7af1a0290ba4bb971fdb2c161d9d05 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 16 Feb 2022 14:57:11 +0100 Subject: [PATCH 133/227] NICLA_VISION: Add overload for TLSSocketWrapper::set_client_cert_key() --- .../include/netsocket/TLSSocketWrapper.h | 3 ++ .../netsocket/source/TLSSocketWrapper.cpp | 41 +++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h index 143dda3aff8..df476f27c4e 100644 --- a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h @@ -148,6 +148,9 @@ class TLSSocketWrapper : public Socket { * @retval NSAPI_ERROR_PARAMETER in case the provided root_ca parameter failed parsing. */ nsapi_error_t set_client_cert_key(const char *client_cert_pem, const char *client_private_key_pem); +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS + nsapi_error_t set_client_cert_key(const void *client_cert, size_t client_cert_len, sss_object_t *pkeyObject); +#endif /** Send data over a TLS socket. * diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 8202151eb7b..c0b33dacee8 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -32,6 +32,12 @@ #include "psa/crypto.h" #endif +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS +extern "C" { +#include "sss_mbedtls.h" +} +#endif + // This class requires Mbed TLS SSL/TLS client code #if defined(MBEDTLS_SSL_CLI_C) @@ -205,6 +211,41 @@ nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, siz #endif /* MBEDTLS_X509_CRT_PARSE_C */ } +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS +nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, size_t client_cert_len, + sss_object_t *pkeyObject) +{ +#if !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PK_C) + return NSAPI_ERROR_UNSUPPORTED; +#else + + int ret; + mbedtls_x509_crt *crt = new (std::nothrow) mbedtls_x509_crt; + if (!crt) { + return NSAPI_ERROR_NO_MEMORY; + } + mbedtls_x509_crt_init(crt); + if ((ret = mbedtls_x509_crt_parse(crt, static_cast(client_cert), + client_cert_len)) != 0) { + print_mbedtls_error("mbedtls_x509_crt_parse", ret); + mbedtls_x509_crt_free(crt); + delete crt; + return NSAPI_ERROR_PARAMETER; + } + mbedtls_pk_init(&_pkctx); + if ((ret = sss_mbedtls_associate_keypair(&_pkctx, pkeyObject)) != 0) { + print_mbedtls_error("sss_mbedtls_associate_keypair", ret); + mbedtls_x509_crt_free(crt); + delete crt; + return NSAPI_ERROR_PARAMETER; + } + set_own_cert(crt); + _clicert_allocated = true; + + return NSAPI_ERROR_OK; +#endif /* MBEDTLS_X509_CRT_PARSE_C */ +} +#endif nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) { From 96f8aec6c620a921a00a9c1997ad724f4917c6c7 Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 21 Feb 2022 11:32:33 +0100 Subject: [PATCH 134/227] TLSSocketWrapper: store SE050 keystore pointer and keyObject --- .../include/netsocket/TLSSocketWrapper.h | 17 ++++++++++++++++- .../netsocket/source/TLSSocketWrapper.cpp | 11 ++++------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h index df476f27c4e..968bb9170a6 100644 --- a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h @@ -32,6 +32,16 @@ #include "mbedtls/hmac_drbg.h" #include "mbedtls/error.h" +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS +extern "C" { +#include "sss_mbedtls.h" +} +#include "ex_sss_boot.h" +extern "C" { +#include "ecdsa_verify_alt.h" +} +#endif + // This class requires Mbed TLS SSL/TLS client code #if defined(MBEDTLS_SSL_CLI_C) || defined(DOXYGEN_ONLY) @@ -149,7 +159,7 @@ class TLSSocketWrapper : public Socket { */ nsapi_error_t set_client_cert_key(const char *client_cert_pem, const char *client_private_key_pem); #if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS - nsapi_error_t set_client_cert_key(const void *client_cert, size_t client_cert_len, sss_object_t *pkeyObject); + nsapi_error_t set_client_cert_key(const void *client_cert, size_t client_cert_len, sss_object_t *pkeyObject, ex_sss_boot_ctx_t *deviceCtx); #endif /** Send data over a TLS socket. @@ -332,6 +342,11 @@ class TLSSocketWrapper : public Socket { mbedtls_pk_context _pkctx; #endif +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS + sss_object_t *_sss_key_pair_ptr; + sss_key_store_t *_sss_ks_ptr; +#endif + DRBG_CTX _drbg; mbedtls_entropy_context _entropy; diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index c0b33dacee8..48135fabf4d 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -32,12 +32,6 @@ #include "psa/crypto.h" #endif -#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS -extern "C" { -#include "sss_mbedtls.h" -} -#endif - // This class requires Mbed TLS SSL/TLS client code #if defined(MBEDTLS_SSL_CLI_C) @@ -213,7 +207,7 @@ nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, siz #if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, size_t client_cert_len, - sss_object_t *pkeyObject) + sss_object_t *pkeyObject, ex_sss_boot_ctx_t *deviceCtx) { #if !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PK_C) return NSAPI_ERROR_UNSUPPORTED; @@ -242,6 +236,9 @@ nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, siz set_own_cert(crt); _clicert_allocated = true; + _sss_key_pair_ptr = pkeyObject; + _sss_ks_ptr = &deviceCtx->ks; + return NSAPI_ERROR_OK; #endif /* MBEDTLS_X509_CRT_PARSE_C */ } From 0b8d97a73c55023868b878525b28f3962aea8529 Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 21 Feb 2022 11:33:44 +0100 Subject: [PATCH 135/227] TLSSocketWrapper: Force correct cipher suite for SE050 integration --- connectivity/netsocket/source/TLSSocketWrapper.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 48135fabf4d..0826d053465 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -236,6 +236,9 @@ nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, siz set_own_cert(crt); _clicert_allocated = true; + static const int CIPHER_SUITES[] = { MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 }; + mbedtls_ssl_conf_ciphersuites(get_ssl_config(), CIPHER_SUITES); + _sss_key_pair_ptr = pkeyObject; _sss_ks_ptr = &deviceCtx->ks; From 922fb1cc11e129ef608ba186d7ae9a112b23d158 Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 21 Feb 2022 11:34:40 +0100 Subject: [PATCH 136/227] TLSSocketWrapper: Associate SE050 ecdh context to mbedtls --- connectivity/netsocket/source/TLSSocketWrapper.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 0826d053465..58f47b54c83 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -307,6 +307,12 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) _transport->set_blocking(false); _transport->sigio(mbed::callback(this, &TLSSocketWrapper::event)); +#if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS + if ((_sss_key_pair_ptr != nullptr) && (_sss_ks_ptr != nullptr)) { + sss_mbedtls_associate_ecdhctx(_ssl.handshake, _sss_key_pair_ptr, _sss_ks_ptr); + } +#endif + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, // these defines can't be used. From ed87a2d75f36470e370cc0bd6c76df2634711432 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 22 Feb 2022 14:16:16 +0100 Subject: [PATCH 137/227] TLSSocketWrapper: Add function to append a certificate to an existing ca chain --- .../include/netsocket/TLSSocketWrapper.h | 23 +++++++++++++++ .../netsocket/source/TLSSocketWrapper.cpp | 28 +++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h index 968bb9170a6..13365428fdb 100644 --- a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h @@ -126,6 +126,29 @@ class TLSSocketWrapper : public Socket { */ nsapi_error_t set_root_ca_cert(const char *root_ca_pem); + /** Appends the certificate to an existing ca chain. + * + * @note Must be called before calling connect() + * + * @param root_ca Root CA Certificate in any Mbed TLS-supported format. + * @param len Length of certificate (including terminating 0 for PEM). + * @retval NSAPI_ERROR_OK on success. + * @retval NSAPI_ERROR_NO_MEMORY in case there is not enough memory to allocate certificate. + * @retval NSAPI_ERROR_PARAMETER in case the provided root_ca parameter failed parsing. + */ + nsapi_error_t append_root_ca_cert(const void *root_ca, size_t len); + + /** Appends the certificate to an existing ca chain. + * + * @note Must be called before calling connect() + * + * @param root_ca_pem Root CA Certificate in PEM format. + * @retval NSAPI_ERROR_OK on success. + * @retval NSAPI_ERROR_NO_MEMORY in case there is not enough memory to allocate certificate. + * @retval NSAPI_ERROR_PARAMETER in case the provided root_ca parameter failed parsing. + */ + nsapi_error_t append_root_ca_cert(const char *root_ca_pem); + /** Sets the certification of Root CA. * * @note Must be called before calling connect() diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 58f47b54c83..6665f64cc0b 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -136,6 +136,34 @@ nsapi_error_t TLSSocketWrapper::set_root_ca_cert(const char *root_ca_pem) return set_root_ca_cert(root_ca_pem, strlen(root_ca_pem) + 1); } +nsapi_error_t TLSSocketWrapper::append_root_ca_cert(const void *root_ca, size_t len) +{ +#if !defined(MBEDTLS_X509_CRT_PARSE_C) + return NSAPI_ERROR_UNSUPPORTED; +#else + mbedtls_x509_crt *crt; + + crt = get_ca_chain(); + if (!crt) { + return NSAPI_ERROR_NO_MEMORY; + } + + /* Parse CA certification */ + int ret; + if ((ret = mbedtls_x509_crt_parse(crt, static_cast(root_ca), + len)) != 0) { + print_mbedtls_error("mbedtls_x509_crt_parse", ret); + return NSAPI_ERROR_PARAMETER; + } + return NSAPI_ERROR_OK; +#endif +} + +nsapi_error_t TLSSocketWrapper::append_root_ca_cert(const char *root_ca_pem) +{ + return append_root_ca_cert(root_ca_pem, strlen(root_ca_pem) + 1); +} + nsapi_error_t TLSSocketWrapper::set_root_ca_cert_path(const char *root_ca) { #if !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_FS_IO) From b3b0bdb971db0225a24bf9388f9a85c78c960782 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 2 Mar 2022 11:31:01 +0100 Subject: [PATCH 138/227] Initialize sss_object and sss_keystore to nullptr --- connectivity/netsocket/include/netsocket/TLSSocketWrapper.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h index 13365428fdb..2dc3b4b0004 100644 --- a/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/TLSSocketWrapper.h @@ -366,8 +366,8 @@ class TLSSocketWrapper : public Socket { #endif #if defined(COMPONENT_SE050) && defined(MBEDTLS_ECDH_ALT) && SSS_HAVE_ALT_SSS - sss_object_t *_sss_key_pair_ptr; - sss_key_store_t *_sss_ks_ptr; + sss_object_t *_sss_key_pair_ptr = nullptr; + sss_key_store_t *_sss_ks_ptr = nullptr; #endif DRBG_CTX _drbg; From 74006cbfeb637492de7916e6cc0c31052ffcd6c8 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 7 Feb 2022 17:52:46 +0100 Subject: [PATCH 139/227] RP2040: fix high speed uart by enabling FIFO + timeout --- .../pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h | 3 ++- targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h index c957a335284..2eafc7ac50d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -213,7 +213,8 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_ */ static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { uart_get_hw(uart)->imsc = (!!tx_needs_data << UART_UARTIMSC_TXIM_LSB) | - (!!rx_has_data << UART_UARTIMSC_RXIM_LSB); + (!!rx_has_data << UART_UARTIMSC_RXIM_LSB) | + (1 << UART_UARTIMSC_RTIM_LSB); if (rx_has_data) { // Set minimum threshold hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB, diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c index 8d95f6c2a32..a6f01a60635 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c @@ -60,7 +60,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) gpio_set_function(rx, GPIO_FUNC_UART); //uart_set_translate_crlf(obj->dev, false); - uart_set_fifo_enabled(obj->dev, false); + uart_set_fifo_enabled(obj->dev, true); if (tx == STDIO_UART_TX) { memmove(&stdio_uart, obj, sizeof(serial_t)); @@ -77,7 +77,7 @@ void serial_baud(serial_t *obj, int baudrate) { obj->baud = (uint32_t)baudrate; uart_init(obj->dev, obj->baud); - uart_set_fifo_enabled(obj->dev, false); + uart_set_fifo_enabled(obj->dev, true); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) From 6cf0ccd07425a4324b23ba1093cf0d8e27ef3b28 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 28 Mar 2022 11:02:58 +0200 Subject: [PATCH 140/227] Fix Ethernet pins configuration --- .../TARGET_PORTENTA_H7/stm32h7_eth_init.c | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c index 3fbac0555f1..643fc5acd36 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c @@ -100,9 +100,12 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure); HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1); HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1); - gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin; + + gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_eth_rst_init_structure.Pin = GPIO_PIN_1; + gpio_eth_rst_init_structure.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure); - HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, 1); HAL_Delay(25); HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); @@ -127,14 +130,35 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) GPIO_InitStruct.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin; + GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin; + GPIO_InitStruct.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_CRS_DV_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_MDIO_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_REF_CLK_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; From 889080679b3974ff8b482222cbcce90499398481 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 17 Mar 2022 10:05:32 +0100 Subject: [PATCH 141/227] COMPONENT_SE050: Add defines to exclude DES functions if MBEDTLS_DES_C module is not enabled --- .../COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c index 614e8f0abb1..20cd12d46cd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/COMPONENT_SE050/sss/src/mbedtls/fsl_sss_mbedtls_apis.c @@ -1265,6 +1265,7 @@ sss_status_t sss_mbedtls_cipher_one_go(sss_mbedtls_symmetric_t *context, mbedtls_ret = mbedtls_aes_setkey_enc( &aes_ctx, context->keyObject->contents, (unsigned int)(context->keyObject->contents_size * 8)); } break; +#if defined(MBEDTLS_DES_C) case kAlgorithm_SSS_DES_CBC: case kAlgorithm_SSS_DES_ECB: case kAlgorithm_SSS_DES3_CBC: @@ -1277,6 +1278,7 @@ sss_status_t sss_mbedtls_cipher_one_go(sss_mbedtls_symmetric_t *context, mbedtls_ret = mbedtls_des_setkey_dec(&des_ctx, context->keyObject->contents); } break; +#endif #endif //SSS_HAVE_TESTCOUNTERPART default: goto exit; @@ -1356,7 +1358,7 @@ sss_status_t sss_mbedtls_cipher_one_go(sss_mbedtls_symmetric_t *context, case kAlgorithm_SSS_AES_CBC: mbedtls_aes_free(&aes_ctx); break; -#if SSS_HAVE_TESTCOUNTERPART +#if SSS_HAVE_TESTCOUNTERPART && defined(MBEDTLS_DES_C) case kAlgorithm_SSS_DES_CBC: case kAlgorithm_SSS_DES_ECB: case kAlgorithm_SSS_DES3_CBC: From d69c66dc52b1600042520fd909963000d5ede81d Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 24 Aug 2021 17:02:47 +0200 Subject: [PATCH 142/227] Add build options to allow to disable device functionalities i.e DEVICE_ANALOGOUT --- targets/TARGET_STM/TARGET_STM32H7/objects.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index aa2bf285ef1..02ed6ea8cd7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -50,10 +50,13 @@ struct port_s { __IO uint32_t *reg_out; }; +#if DEVICE_TRNG struct trng_s { RNG_HandleTypeDef handle; }; +#endif +#if DEVICE_PWMOUT struct pwmout_s { PWMName pwm; PinName pin; @@ -63,7 +66,9 @@ struct pwmout_s { uint8_t channel; uint8_t inverted; }; +#endif +#if DEVICE_SPI struct spi_s { SPI_HandleTypeDef handle; IRQn_Type spiIRQ; @@ -77,6 +82,7 @@ struct spi_s { uint8_t transfer_type; #endif }; +#endif struct serial_s { UARTName uart; @@ -97,12 +103,14 @@ struct serial_s { #endif }; +#if DEVICE_ANALOGIN struct analogin_s { ADC_HandleTypeDef handle; PinName pin; uint8_t channel; uint8_t differential; }; +#endif #if DEVICE_QSPI struct qspi_s { @@ -144,12 +152,14 @@ struct qspi_s { #endif /* DUAL_CORE */ #include "gpio_object.h" +#if DEVICE_ANALOGOUT struct dac_s { DACName dac; PinName pin; uint32_t channel; DAC_HandleTypeDef handle; }; +#endif struct flash_s { /* nothing to be stored for now */ From 2625f097c5a782c362554b99499ec6059561f221 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 24 Aug 2021 17:03:39 +0200 Subject: [PATCH 143/227] MCUboot:PORTENTA_H7_M7:Change ST HAL configuration removing unnecessary modules --- .../STM32Cube_FW/stm32h7xx_hal_conf.h | 32 ++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h index afcfc242104..524bb2dd528 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h @@ -35,32 +35,42 @@ * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) #define HAL_ADC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED #define HAL_CORDIC_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED #define HAL_DAC_MODULE_ENABLED #define HAL_DCMI_MODULE_ENABLED #define HAL_DFSDM_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED #define HAL_DTS_MODULE_ENABLED #define HAL_DSI_MODULE_ENABLED #define HAL_ETH_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_FDCAN_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED #define HAL_GFXMMU_MODULE_ENABLED #define HAL_FMAC_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED #define HAL_HRTIM_MODULE_ENABLED -#define HAL_HSEM_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED #define HAL_I2S_MODULE_ENABLED #define HAL_IRDA_MODULE_ENABLED #define HAL_IWDG_MODULE_ENABLED @@ -68,23 +78,16 @@ #define HAL_LPTIM_MODULE_ENABLED #define HAL_LTDC_MODULE_ENABLED #define HAL_MDIOS_MODULE_ENABLED -#define HAL_MDMA_MODULE_ENABLED #define HAL_MMC_MODULE_ENABLED #define HAL_NAND_MODULE_ENABLED #define HAL_NOR_MODULE_ENABLED #define HAL_OPAMP_MODULE_ENABLED #define HAL_OSPI_MODULE_ENABLED #define HAL_OTFDEC_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED #define HAL_PSSI_MODULE_ENABLED -#define HAL_QSPI_MODULE_ENABLED #define HAL_RAMECC_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED #define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -92,10 +95,9 @@ #define HAL_SPI_MODULE_ENABLED #define HAL_SRAM_MODULE_ENABLED #define HAL_SWPMI_MODULE_ENABLED -#define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED +#endif /* ########################## Oscillator Values adaptation ####################*/ /** From 3f564015d9e834659ab420cef445b667f2454695 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 24 Aug 2021 17:04:35 +0200 Subject: [PATCH 144/227] Add build option to allow FATFS customization: remove mkfs --- storage/filesystem/fat/include/fat/FATFileSystem.h | 4 ++++ storage/filesystem/fat/source/FATFileSystem.cpp | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/storage/filesystem/fat/include/fat/FATFileSystem.h b/storage/filesystem/fat/include/fat/FATFileSystem.h index 581662b2cea..f15e0815027 100644 --- a/storage/filesystem/fat/include/fat/FATFileSystem.h +++ b/storage/filesystem/fat/include/fat/FATFileSystem.h @@ -45,6 +45,7 @@ class FATFileSystem : public FileSystem { FATFileSystem(const char *name = NULL, BlockDevice *bd = NULL); virtual ~FATFileSystem(); +#if MBED_CONF_FAT_CHAN_FF_USE_MKFS /** Format a logical drive, FDISK partitioning rule. * * The block device to format should be mounted when this function is called. @@ -62,6 +63,7 @@ class FATFileSystem : public FileSystem { * @return 0 on success, negative error code on failure. */ static int format(BlockDevice *bd, bd_size_t cluster_size = 0); +#endif /** Mount a file system to a block device. * @@ -76,6 +78,7 @@ class FATFileSystem : public FileSystem { */ virtual int unmount(); +#if MBED_CONF_FAT_CHAN_FF_USE_MKFS /** Reformat a file system, results in an empty and mounted file system. * * @param bd @@ -108,6 +111,7 @@ class FATFileSystem : public FileSystem { // Required for virtual inheritance shenanigans. return reformat(bd, 0); } +#endif /** Remove a file from the file system. * diff --git a/storage/filesystem/fat/source/FATFileSystem.cpp b/storage/filesystem/fat/source/FATFileSystem.cpp index 98fa2a5f981..3c32cc6f27d 100644 --- a/storage/filesystem/fat/source/FATFileSystem.cpp +++ b/storage/filesystem/fat/source/FATFileSystem.cpp @@ -340,7 +340,7 @@ int FATFileSystem::unmount() unlock(); return fat_error_remap(res); } - +#if MBED_CONF_FAT_CHAN_FF_USE_MKFS /* See http://elm-chan.org/fsw/ff/en/mkfs.html for details of f_mkfs() and * associated arguments. */ int FATFileSystem::format(BlockDevice *bd, bd_size_t cluster_size) @@ -464,6 +464,7 @@ int FATFileSystem::reformat(BlockDevice *bd, int allocation_unit) unlock(); return err; } +#endif int FATFileSystem::remove(const char *path) { From ae42794929193a17ed241d1ff43738617c94b48a Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 26 Aug 2021 15:40:48 +0200 Subject: [PATCH 145/227] Optimize HAL_RCCEx_PeriphCLKConfig using only HAL enabled modules --- .../stm32h7xx_hal_rcc_ex.c | 42 +++++++++++++------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c index afde46b3b81..c349750263c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c @@ -111,8 +111,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ HAL_StatusTypeDef status = HAL_OK; /* Final status */ +#if defined(HAL_SPDIFRX_MODULE_ENABLED) /*---------------------------- SPDIFRX configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { @@ -159,7 +159,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif +#if defined(HAL_SAI_MODULE_ENABLED) /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) { @@ -211,8 +213,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif -#if defined(SAI3) +#if defined(SAI3) && defined(HAL_SAI_MODULE_ENABLED) /*---------------------------- SAI2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) { @@ -267,7 +270,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* SAI3 */ -#if defined(RCC_CDCCIP1R_SAI2ASEL) +#if defined(RCC_CDCCIP1R_SAI2ASEL) && defined(HAL_SAI_MODULE_ENABLED) /*---------------------------- SAI2A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) { @@ -326,8 +329,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*SAI2A*/ -#if defined(RCC_CDCCIP1R_SAI2BSEL) - +#if defined(RCC_CDCCIP1R_SAI2BSEL) && defined(HAL_SAI_MODULE_ENABLED) /*---------------------------- SAI2B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) { @@ -386,7 +388,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*SAI2B*/ -#if defined(SAI4) +#if defined(SAI4) && defined(HAL_SAI_MODULE_ENABLED) /*---------------------------- SAI4A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) { @@ -421,7 +423,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; - + #if defined(RCC_VER_3_0) case RCC_SAI4ACLKSOURCE_SPDIF: /* SPDIF clock is used as source of SAI4A clock */ @@ -505,7 +507,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*SAI4*/ -#if defined(QUADSPI) +#if defined(QUADSPI) && defined(HAL_QSPI_MODULE_ENABLED) /*---------------------------- QSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) { @@ -601,6 +603,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*OCTOSPI*/ +#if defined(HAL_SPI_MODULE_ENABLED) /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) { @@ -761,8 +764,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif -#if defined(DSI) +#if defined(DSI) && defined(HAL_DSI_MODULE_ENABLED) /*---------------------------- DSI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) { @@ -799,7 +803,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*DSI*/ -#if defined(FDCAN1) || defined(FDCAN2) +#if (defined(FDCAN1) || defined(FDCAN2)) && defined(HAL_FDCAN_MODULE_ENABLED) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) { @@ -1111,6 +1115,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#if defined(HAL_LPTIM_MODULE_ENABLED) /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { @@ -1269,6 +1274,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ #if defined(I2C5) @@ -1325,6 +1331,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } +#if defined(HAL_ADC_MODULE_ENABLED) /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { @@ -1365,6 +1372,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) @@ -1448,7 +1456,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } -#if defined(LTDC) +#if defined(LTDC) && defined(HAL_LTDC_MODULE_ENABLED) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { @@ -1459,6 +1467,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /* LTDC */ +#if defined(HAL_RNG_MODULE_ENABLED) /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) { @@ -1503,7 +1512,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#endif +#if defined(HAL_SWPMI_MODULE_ENABLED) /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) { @@ -1513,7 +1524,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); } -#if defined(HRTIM1) +#endif + +#if defined(HRTIM1) && defined(HAL_HRTIM_MODULE_ENABLED) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) { @@ -1524,6 +1537,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ + +#if defined(HAL_DFSDM_MODULE_ENABLED) /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) { @@ -1545,6 +1560,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ +#endif /* HAL_DFSDM_MODULE_ENABLED */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) @@ -1566,6 +1582,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); } +#if defined(HAL_CEC_MODULE_ENABLED) /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { @@ -1575,6 +1592,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } +#endif if (status == HAL_OK) { From d81aa7300c499a8a8304712b5bab330155d13ba2 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 26 Aug 2021 15:42:18 +0200 Subject: [PATCH 146/227] MCUboot:PORTENTA_H7_M7:Remove HSI,CSI,LSI,HSI48 support from HAL_RCC_OscConfig --- .../STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c index b5e93c78b91..eb5485dc7d7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c @@ -469,6 +469,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } } +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { @@ -687,6 +688,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } } +#endif /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { From 19af3fd984266b17e77b6c4f2442de7053210eed Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 4 Aug 2021 09:33:11 +0200 Subject: [PATCH 147/227] MCUBoot:PORTENTA_H7_M7:Add linker sections to store boot configuration and gain space --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 68280f47574..41c72141ed5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -45,6 +45,15 @@ MEMORY ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K } + +#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) +_ConfigStart = 0x0802F000; +_IdentificationStart = 0x080002F0; +_EncryptKeyStart = 0x08000300; +_SigningKeyStart = 0x08000400; +#endif + + /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: @@ -79,6 +88,12 @@ SECTIONS .text : { KEEP(*(.isr_vector)) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) + . = ABSOLUTE(0x080002F0); + KEEP(*(.bootloader_identification)) + KEEP(*(.signing_key)) + KEEP(*(.encrypt_key)) +#endif *(.text*) KEEP(*(.init)) @@ -98,6 +113,18 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) + *lib*.o(.rodata*) + *ltrans0*.o(.rodata*) + *ltrans1*.o(.rodata*) + *ltrans2*.o(.rodata*) + *ltrans3*.o(.rodata*) + *ltrans4*.o(.rodata*) + + . = ABSOLUTE(0x0801F000); + KEEP(*(.bootloader_version)) +#endif + *(.rodata*) KEEP(*(.eh_frame*)) From 67a544b73890d0501ccbc65dc864295206e290da Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 14 Mar 2022 09:39:31 +0100 Subject: [PATCH 148/227] Add build option DEVICE_SERIAL_FC preventing build if flow control is disabled --- drivers/source/SerialBase.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/source/SerialBase.cpp b/drivers/source/SerialBase.cpp index 7c21d12e9c4..33a049c844a 100644 --- a/drivers/source/SerialBase.cpp +++ b/drivers/source/SerialBase.cpp @@ -71,9 +71,11 @@ int SerialBase::readable() { lock(); int ret = serial_readable(&_serial); +#if DEVICE_SERIAL_FC if (sw_flow_control == true && _rts_pin != nullptr) { *_rts_pin = !!!ret; } +#endif unlock(); return ret; } @@ -83,9 +85,11 @@ int SerialBase::writeable() { lock(); int ret = serial_writable(&_serial); +#if DEVICE_SERIAL_FC if (sw_flow_control) { ret = ret & !(*_cts_pin); } +#endif unlock(); return ret; } From ac2dbd7ef81a842d8fec3d4fe60a7a43f31cd7d4 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 18 Mar 2022 14:57:45 +0100 Subject: [PATCH 149/227] MCUboot:PORTENTA_H7_M7:Remove FATFS mkdir and rename --- storage/filesystem/fat/include/fat/FATFileSystem.h | 4 ++++ storage/filesystem/fat/source/FATFileSystem.cpp | 2 ++ 2 files changed, 6 insertions(+) diff --git a/storage/filesystem/fat/include/fat/FATFileSystem.h b/storage/filesystem/fat/include/fat/FATFileSystem.h index f15e0815027..24a67996867 100644 --- a/storage/filesystem/fat/include/fat/FATFileSystem.h +++ b/storage/filesystem/fat/include/fat/FATFileSystem.h @@ -120,6 +120,7 @@ class FATFileSystem : public FileSystem { */ virtual int remove(const char *path); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Rename a file in the file system. * * @param path The current name of the file to rename. @@ -127,6 +128,7 @@ class FATFileSystem : public FileSystem { * @return 0 on success, negative error code on failure. */ virtual int rename(const char *path, const char *newpath); +#endif /** Store information about the file in a stat structure. * @@ -136,6 +138,7 @@ class FATFileSystem : public FileSystem { */ virtual int stat(const char *path, struct stat *st); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Create a directory in the file system. * * @param path The name of the directory to create. @@ -143,6 +146,7 @@ class FATFileSystem : public FileSystem { * @return 0 on success, negative error code on failure. */ virtual int mkdir(const char *path, mode_t mode); +#endif /** Store information about the mounted file system in a statvfs structure. * diff --git a/storage/filesystem/fat/source/FATFileSystem.cpp b/storage/filesystem/fat/source/FATFileSystem.cpp index 3c32cc6f27d..8d206c6b06d 100644 --- a/storage/filesystem/fat/source/FATFileSystem.cpp +++ b/storage/filesystem/fat/source/FATFileSystem.cpp @@ -483,6 +483,7 @@ int FATFileSystem::remove(const char *path) return fat_error_remap(res); } +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) int FATFileSystem::rename(const char *oldpath, const char *newpath) { Deferred oldfpath = fat_path_prefix(_id, oldpath); @@ -511,6 +512,7 @@ int FATFileSystem::mkdir(const char *path, mode_t mode) } return fat_error_remap(res); } +#endif int FATFileSystem::stat(const char *path, struct stat *st) { From 0747bafcc3578c73a9d2d6a9badbb6ca78c0aa44 Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Tue, 29 Mar 2022 13:01:34 +0200 Subject: [PATCH 150/227] Fix: Only return true for 'uart_is_writeable' if the TX FIFO is empty. This allows the Arduino_Braccio_plusplus library to work again, since it depends on precisely trimmed timeouts to change data direction on the RS485 lines. This means that when '_serial->flush();' is called, we do wait until the FIFO is empty before turning of DATA ENABLE. Currently if we call _serial->flush(); we are instead only waiting until at least one element has been removed from the transmit FIFO. --- .../pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h | 4 ++-- targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h index 2eafc7ac50d..58c0e800bec 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -253,14 +253,14 @@ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { // ---------------------------------------------------------------------------- // Generic input/output -/*! \brief Determine if space is available in the TX FIFO +/*! \brief Determine if the TX FIFO is empty. * \ingroup hardware_uart * * \param uart UART instance. \ref uart0 or \ref uart1 * \return false if no space available, true otherwise */ static inline bool uart_is_writable(uart_inst_t *uart) { - return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS); + return (uart_get_hw(uart)->fr & UART_UARTFR_TXFE_BITS); } /*! \brief Wait for the UART TX fifo to be drained diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c index a6f01a60635..4b2398b397a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c @@ -212,4 +212,4 @@ const PinMap *serial_rts_pinmap(void) return PinMap_UART_RTS; } -#endif \ No newline at end of file +#endif From cf206a80c3521bab961bb0a42089d88fc7092933 Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 4 Apr 2022 10:12:28 +0200 Subject: [PATCH 151/227] MCUboot:PORTENTA_H7_M7:Remove LittleFS format, reformat, rename --- .../filesystem/littlefs/include/littlefs/LittleFileSystem.h | 6 ++++++ storage/filesystem/littlefs/source/LittleFileSystem.cpp | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h b/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h index c1e3a3c299c..0051f18da6d 100644 --- a/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h +++ b/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h @@ -65,6 +65,7 @@ class LittleFileSystem : public mbed::FileSystem { virtual ~LittleFileSystem(); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Format a block device with the LittleFileSystem. * * The block device to format should be mounted when this function is called. @@ -94,6 +95,7 @@ class LittleFileSystem : public mbed::FileSystem { lfs_size_t block_size = MBED_LFS_BLOCK_SIZE, lfs_size_t lookahead = MBED_LFS_LOOKAHEAD); +#endif /** Mount a file system to a block device. * * @param bd Block device to mount to. @@ -107,6 +109,7 @@ class LittleFileSystem : public mbed::FileSystem { */ virtual int unmount(); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Reformat a file system. Results in an empty and mounted file system. * * @param bd @@ -118,6 +121,7 @@ class LittleFileSystem : public mbed::FileSystem { * @return 0 on success, negative error code on failure */ virtual int reformat(mbed::BlockDevice *bd); +#endif /** Remove a file from the file system. * @@ -126,6 +130,7 @@ class LittleFileSystem : public mbed::FileSystem { */ virtual int remove(const char *path); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Rename a file in the file system. * * @param path The name of the file to rename. @@ -133,6 +138,7 @@ class LittleFileSystem : public mbed::FileSystem { * @return 0 on success, negative error code on failure */ virtual int rename(const char *path, const char *newpath); +#endif /** Store information about the file in a stat structure * diff --git a/storage/filesystem/littlefs/source/LittleFileSystem.cpp b/storage/filesystem/littlefs/source/LittleFileSystem.cpp index 752fa99aa5f..3b808cf0177 100644 --- a/storage/filesystem/littlefs/source/LittleFileSystem.cpp +++ b/storage/filesystem/littlefs/source/LittleFileSystem.cpp @@ -241,6 +241,7 @@ int LittleFileSystem::unmount() return res; } +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) int LittleFileSystem::format(BlockDevice *bd, lfs_size_t read_size, lfs_size_t prog_size, lfs_size_t block_size, lfs_size_t lookahead) @@ -338,6 +339,7 @@ int LittleFileSystem::reformat(BlockDevice *bd) _mutex.unlock(); return 0; } +#endif int LittleFileSystem::remove(const char *filename) { @@ -349,6 +351,7 @@ int LittleFileSystem::remove(const char *filename) return lfs_toerror(err); } +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) int LittleFileSystem::rename(const char *oldname, const char *newname) { _mutex.lock(); @@ -358,6 +361,7 @@ int LittleFileSystem::rename(const char *oldname, const char *newname) _mutex.unlock(); return lfs_toerror(err); } +#endif int LittleFileSystem::mkdir(const char *name, mode_t mode) { From f70719ab23d010515a54d8e86ebf230407f67b3f Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 5 Apr 2022 16:43:07 +0200 Subject: [PATCH 152/227] MCUboot:PORTENTA_H7_Move libc rodata after bootloader data to gain flash space --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 41c72141ed5..0a54d17c76c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -114,7 +114,6 @@ SECTIONS *(.dtors) #if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) - *lib*.o(.rodata*) *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) *ltrans2*.o(.rodata*) @@ -123,6 +122,8 @@ SECTIONS . = ABSOLUTE(0x0801F000); KEEP(*(.bootloader_version)) + + *lib*.o(.rodata*) #endif *(.rodata*) From 0b1a01ad4adb0cbee9bea76e80ebb08baeff86a6 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 6 Apr 2022 13:55:55 +0200 Subject: [PATCH 153/227] NICLA_VISION:Add device name in target.json --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 050ce7e9325..9baf7bfa971 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3656,7 +3656,8 @@ ], "features": [ "BLE" - ] + ], + "device_name": "STM32H747XIHx" }, "PORTENTA_H7_M4": { "inherits": ["PORTENTA_H7"], From e2718d9be59a19d1ef32dcc0c430f076994480bf Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 6 Apr 2022 13:56:50 +0200 Subject: [PATCH 154/227] MCUboot:NICLA_VISION: linker file:Reserve space for keys and bootloader id --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 0a54d17c76c..3e84731230b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -46,7 +46,7 @@ MEMORY } -#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) _ConfigStart = 0x0802F000; _IdentificationStart = 0x080002F0; _EncryptKeyStart = 0x08000300; @@ -88,7 +88,7 @@ SECTIONS .text : { KEEP(*(.isr_vector)) -#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) . = ABSOLUTE(0x080002F0); KEEP(*(.bootloader_identification)) KEEP(*(.signing_key)) @@ -113,7 +113,7 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) -#if defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) *ltrans2*.o(.rodata*) From 4b805b51458f021a5e8b2f8cbe1f8f783b34cb1e Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 10 May 2022 18:07:10 +0200 Subject: [PATCH 155/227] ST: CAN: allow sending CAN remote frames --- targets/TARGET_STM/can_api.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index b18b9cb7470..c579c19a7ee 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -408,7 +408,11 @@ int can_write(can_t *obj, CAN_Message msg, int cc) TxHeader.IdType = FDCAN_EXTENDED_ID; } - TxHeader.TxFrameType = FDCAN_DATA_FRAME; + if (msg.type == CANData) { + TxHeader.TxFrameType = FDCAN_DATA_FRAME; + } else { + TxHeader.TxFrameType = FDCAN_REMOTE_FRAME; + } TxHeader.DataLength = msg.len << 16; TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE; TxHeader.BitRateSwitch = FDCAN_BRS_OFF; From 9daeaec8a1dcb3e0d3d9999ad64063478d17f422 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 18 Jan 2022 16:53:27 +0100 Subject: [PATCH 156/227] Add Portenta X8 target --- .../TARGET_PORTENTA_X8/CMakeLists.txt | 16 + .../TARGET_PORTENTA_X8/PeripheralPins.c | 570 ++++++++++++++++++ .../TARGET_PORTENTA_X8/PinNames.h | 381 ++++++++++++ targets/targets.json | 34 +- 4 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/CMakeLists.txt new file mode 100644 index 00000000000..d5015acdf49 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-portenta-x8 INTERFACE) + +target_sources(mbed-portenta-x8 + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-portenta-x8 + INTERFACE + . +) + +target_link_libraries(mbed-portenta-x8 INTERFACE mbed-stm32h747xi-cm4) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PeripheralPins.c new file mode 100644 index 00000000000..3b1cf1075bf --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PeripheralPins.c @@ -0,0 +1,570 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NC, 0} +}; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h new file mode 100644 index 00000000000..1cce05b2e2e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h @@ -0,0 +1,381 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +/* MBED TARGET LIST: PORTENTA_H7_M4, PORTENTA_H7_M7 */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0C = PA_0 | DUAL_PAD, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | DUAL_PAD, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PD_5, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PD_6, +#endif + + //Led mappings + LED_RED = PA_0, //Red + LED_GREEN = PA_0, //Green + LED_BLUE = PA_0, //Blue + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_TRGIO = PC_7, + SYS_WKUP0 = PA_0, + SYS_WKUP1 = PA_2, + SYS_WKUP2 = PC_13, + SYS_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define BUTTON1 PE_5 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/targets.json b/targets/targets.json index 9baf7bfa971..80206371e94 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3677,6 +3677,37 @@ "MPU" ] }, + "PORTENTA_X8": { + "inherits": ["MCU_STM32H747xI_CM4"], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "25000000", + "macro_name": "HSE_VALUE" + }, + "lse_bypass": { + "help": "1 to use an oscillator (not a crystal) on 32k LSE", + "value": "1" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_HS" + } + }, + "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", + "CM4_BOOT_BY_APPLICATION" + ], + "detect_code": ["0813"], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY", + "clock_source": "USE_PLL_HSI", + "lse_available": 1, + "lpticker_delay_ticks": 0, + "i2c_timing_value_algo": true + } + }, "MCU_STM32H750xB": { "inherits": [ "MCU_STM32H7" @@ -3695,7 +3726,8 @@ ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" - } + }, + "device_name": "STM32H747XIHx" }, "MCU_STM32H753xI": { "inherits": [ From 7e0b9dcc37ea577f80832fe554aa558c795064d3 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 25 Jan 2022 17:17:58 +0100 Subject: [PATCH 157/227] PortentaX8: remove MPU support --- targets/targets.json | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 80206371e94..33f42a4f9a1 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3697,7 +3697,12 @@ "macros_add": [ "MBEDTLS_FS_IO", "MBEDTLS_SHA1_C", - "CM4_BOOT_BY_APPLICATION" + "CM4_BOOT_BY_APPLICATION", + "CORE_CM4", + "MBED_MPU_CUSTOM" + ], + "device_has_remove": [ + "MPU" ], "detect_code": ["0813"], "overrides": { From 6eb213ea9d765658679966b8729236c86f7d639f Mon Sep 17 00:00:00 2001 From: Giampaolo Mancini Date: Fri, 29 Apr 2022 17:12:22 +0200 Subject: [PATCH 158/227] Enable Watchdog for ARDUINO_NANO33BLE --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index 33f42a4f9a1..3276150b923 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7193,6 +7193,7 @@ "components_remove": [ "QSPIF" ], + "device_has_add": ["WATCHDOG"], "device_has_remove": [ "QSPI", "ITM" From 6f80aa99c5b3e496e42b3e68187d93232412fff5 Mon Sep 17 00:00:00 2001 From: Giampaolo Mancini Date: Fri, 29 Apr 2022 17:13:01 +0200 Subject: [PATCH 159/227] Enable Watchdog for NICLA --- .../TARGET_MCU_NRF52832/config/sdk_config.h | 12 ++++++++++++ targets/targets.json | 1 + 2 files changed, 13 insertions(+) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h index b1112d715ad..dea0276ddbc 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h @@ -4487,6 +4487,18 @@ #define NRFX_WDT_CONFIG_LOG_LEVEL 3 #endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver. +//========================================================== + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 1 +#endif + + // NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. // <0=> Default diff --git a/targets/targets.json b/targets/targets.json index 3276150b923..e3409dc9640 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7019,6 +7019,7 @@ "components_add": [ "FLASHIAP" ], + "device_has_add": ["WATCHDOG"], "release_versions": ["5"], "device_name": "nRF52832_xxAA", "macros_add": [ From 293b05ed88933644de2b0aa5553c4cb767d47660 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 20 Apr 2022 10:20:41 +0200 Subject: [PATCH 160/227] Port pico-sdk 1.3.0 - initial --- .../TARGET_RP2040/pico-sdk/CMakeLists.txt | 40 +- .../TARGET_RP2040/pico-sdk/board_setup.cmake | 2 +- .../include/boards/adafruit_feather_rp2040.h | 93 + .../boards/adafruit_itsybitsy_rp2040.h | 96 + .../include/boards/adafruit_qtpy_rp2040.h | 95 + .../include/boards/adafruit_trinkey_qt2040.h | 73 + .../boards/arduino_nano_rp2040_connect.h | 84 + .../include/boards/melopero_shake_rp2040.h | 91 + .../pico-sdk/boards/include/boards/pico.h | 48 +- .../include/boards/pimoroni_interstate75.h | 181 + .../include/boards/pimoroni_keybow2040.h | 154 + .../boards/include/boards/pimoroni_pga2040.h | 79 + .../include/boards/pimoroni_picolipo_16mb.h | 92 + .../include/boards/pimoroni_picolipo_4mb.h | 92 + .../include/boards/pimoroni_picosystem.h | 163 + .../include/boards/pimoroni_plasma2040.h | 137 + .../boards/include/boards/pimoroni_tiny2040.h | 127 + .../boards/include/boards/pybstick26_rp2040.h | 85 + .../boards/include/boards/sparkfun_micromod.h | 86 + .../boards/include/boards/sparkfun_promicro.h | 86 + .../include/boards/sparkfun_thingplus.h | 92 + .../pico-sdk/boards/include/boards/vgaboard.h | 70 +- .../boards/waveshare_rp2040_lcd_0.96.h | 104 + .../boards/waveshare_rp2040_plus_16mb.h | 84 + .../boards/waveshare_rp2040_plus_4mb.h | 84 + .../include/boards/waveshare_rp2040_zero.h | 79 + .../pico-sdk/boards/include/placeholder.h | 0 .../pico-sdk/common/CMakeLists.txt | 5 +- .../pico-sdk/common/pico_base/CMakeLists.txt | 33 +- .../pico_base/generate_config_header.cmake | 29 + .../pico-sdk/common/pico_base/include/pico.h | 10 +- .../common/pico_base/include/pico/assert.h | 4 +- .../common/pico_base/include/pico/config.h | 4 +- .../common/pico_base/include/pico/error.h | 4 + .../common/pico_base/include/pico/types.h | 49 +- .../common/pico_binary_info/CMakeLists.txt | 6 +- .../include/pico/binary_info.h | 13 +- .../include/pico/binary_info/code.h | 4 +- .../include/pico/binary_info/structure.h | 1 + .../common/pico_stdlib/include/pico/stdlib.h | 20 +- .../common/pico_stdlib/include/placeholder.h | 0 .../pico-sdk/common/pico_sync/CMakeLists.txt | 10 +- .../common/pico_sync/critical_section.c | 15 +- .../pico_sync/include/pico/critical_section.h | 37 +- .../common/pico_sync/include/pico/lock_core.h | 177 +- .../common/pico_sync/include/pico/mutex.h | 212 +- .../common/pico_sync/include/pico/sem.h | 29 +- .../pico-sdk/common/pico_sync/lock_core.c | 2 +- .../pico-sdk/common/pico_sync/mutex.c | 163 +- .../pico-sdk/common/pico_sync/sem.c | 61 +- .../pico-sdk/common/pico_time/CMakeLists.txt | 2 +- .../common/pico_time/include/pico/time.h | 62 +- .../common/pico_time/include/placeholder.h | 0 .../pico-sdk/common/pico_time/time.c | 172 +- .../pico_usb_reset_interface/CMakeLists.txt | 2 + .../include/pico/usb_reset_interface.h | 28 + .../pico-sdk/common/pico_util/CMakeLists.txt | 2 +- .../pico_util/include/pico/util/datetime.h | 7 + .../pico_util/include/pico/util/pheap.h | 164 +- .../pico_util/include/pico/util/queue.h | 57 +- .../pico-sdk/common/pico_util/pheap.c | 32 +- .../pico-sdk/common/pico_util/queue.c | 123 +- .../pico-sdk/generated/pico/config_autogen.h | 7 + .../pico-sdk/generated/pico/version.h | 6 +- .../pico-sdk/host/CMakeLists.txt | 11 +- .../TARGET_RP2040/pico-sdk/host/boot_stage2.c | 4 +- .../include/hardware/divider.h | 2 +- .../pico-sdk/host/hardware_gpio/gpio.c | 31 +- .../hardware_gpio/include/hardware/gpio.h | 27 + .../pico-sdk/host/hardware_timer/timer.c | 7 +- .../pico-sdk/host/hardware_uart/uart.c | 16 +- .../pico-sdk/host/pico_bit_ops/CMakeLists.txt | 2 +- .../pico-sdk/host/pico_divider/CMakeLists.txt | 2 +- .../host/pico_multicore/CMakeLists.txt | 2 +- .../pico_multicore/include/pico/multicore.h | 23 +- .../host/pico_platform/CMakeLists.txt | 10 +- .../include/hardware/platform_defs.h | 4 + .../pico_platform/include/pico/platform.h | 22 +- .../pico-sdk/host/pico_printf/CMakeLists.txt | 2 +- .../pico-sdk/host/pico_stdio/CMakeLists.txt | 8 +- .../host/pico_stdio/include/pico/stdio.h | 5 +- .../pico-sdk/host/pico_stdlib/CMakeLists.txt | 2 +- .../pico-sdk/rp2040/CMakeLists.txt | 2 + .../include/hardware/platform_defs.h | 59 +- .../hardware_regs/include/hardware/regs/adc.h | 270 +- .../include/hardware/regs/addressmap.h | 114 +- .../include/hardware/regs/busctrl.h | 308 +- .../include/hardware/regs/clocks.h | 2388 +-- .../hardware_regs/include/hardware/regs/dma.h | 4180 ++--- .../hardware_regs/include/hardware/regs/i2c.h | 1762 +- .../include/hardware/regs/io_bank0.h | 14862 ++++++++-------- .../include/hardware/regs/io_qspi.h | 2904 +-- .../include/hardware/regs/m0plus.h | 876 +- .../include/hardware/regs/pads_bank0.h | 2254 +-- .../include/hardware/regs/pads_qspi.h | 434 +- .../hardware_regs/include/hardware/regs/pio.h | 2891 +-- .../hardware_regs/include/hardware/regs/pll.h | 100 +- .../hardware_regs/include/hardware/regs/psm.h | 568 +- .../hardware_regs/include/hardware/regs/pwm.h | 1422 +- .../include/hardware/regs/resets.h | 618 +- .../include/hardware/regs/rosc.h | 248 +- .../hardware_regs/include/hardware/regs/rtc.h | 362 +- .../hardware_regs/include/hardware/regs/sio.h | 1368 +- .../hardware_regs/include/hardware/regs/spi.h | 440 +- .../hardware_regs/include/hardware/regs/ssi.h | 724 +- .../include/hardware/regs/syscfg.h | 214 +- .../include/hardware/regs/sysinfo.h | 54 +- .../include/hardware/regs/tbman.h | 22 +- .../include/hardware/regs/timer.h | 294 +- .../include/hardware/regs/uart.h | 868 +- .../hardware_regs/include/hardware/regs/usb.h | 3514 ++-- .../include/hardware/regs/usb_device_dpram.h | 6807 +++++++ .../hardware/regs/vreg_and_chip_reset.h | 98 +- .../include/hardware/regs/watchdog.h | 200 +- .../hardware_regs/include/hardware/regs/xip.h | 120 +- .../include/hardware/regs/xosc.h | 121 +- .../pico-sdk/rp2040/hardware_regs/rp2040.svd | 6925 ++++++- .../include/hardware/placeholder.h | 0 .../include/hardware/structs/adc.h | 77 +- .../include/hardware/structs/bus_ctrl.h | 43 +- .../include/hardware/structs/clocks.h | 278 +- .../include/hardware/structs/dma.h | 161 +- .../include/hardware/structs/i2c.h | 392 +- .../include/hardware/structs/interp.h | 58 +- .../include/hardware/structs/iobank0.h | 197 +- .../include/hardware/structs/ioqspi.h | 163 +- .../include/hardware/structs/mpu.h | 40 +- .../include/hardware/structs/pads_qspi.h | 32 +- .../include/hardware/structs/padsbank0.h | 34 +- .../include/hardware/structs/pio.h | 270 +- .../include/hardware/structs/pll.h | 33 +- .../include/hardware/structs/psm.h | 94 +- .../include/hardware/structs/pwm.h | 101 +- .../include/hardware/structs/resets.h | 98 +- .../include/hardware/structs/rosc.h | 65 +- .../include/hardware/structs/rtc.h | 95 +- .../include/hardware/structs/scb.h | 51 +- .../include/hardware/structs/sio.h | 135 +- .../include/hardware/structs/spi.h | 79 +- .../include/hardware/structs/ssi.h | 193 +- .../include/hardware/structs/syscfg.h | 55 +- .../include/hardware/structs/systick.h | 34 +- .../include/hardware/structs/timer.h | 80 +- .../include/hardware/structs/uart.h | 150 +- .../include/hardware/structs/usb.h | 457 +- .../hardware/structs/vreg_and_chip_reset.h | 31 +- .../include/hardware/structs/watchdog.h | 42 +- .../include/hardware/structs/xip_ctrl.h | 57 +- .../include/hardware/structs/xosc.h | 39 +- .../TARGET_RP2040/pico-sdk/rp2_common.cmake | 12 +- .../pico-sdk/rp2_common/CMakeLists.txt | 6 + .../rp2_common/boot_stage2/CMakeLists.txt | 61 +- .../rp2_common/boot_stage2/boot2_at25sf128a.S | 285 + .../boot_stage2/compile_time_choice.S | 19 + .../boot_stage2/include/boot_stage2/config.h | 94 + .../pico-sdk/rp2_common/cmsis/CMakeLists.txt | 66 + .../cmsis/include/cmsis/rename_exceptions.h | 53 + .../stub/CMSIS/Core/Include/cmsis_armcc.h | 885 + .../stub/CMSIS/Core/Include/cmsis_armclang.h | 1467 ++ .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1893 ++ .../stub/CMSIS/Core/Include/cmsis_compiler.h | 283 + .../cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h | 2177 +++ .../stub/CMSIS/Core/Include/cmsis_iccarm.h | 968 + .../stub/CMSIS/Core/Include/cmsis_version.h | 39 + .../stub/CMSIS/Core/Include/core_cm0plus.h | 1087 ++ .../cmsis/stub/CMSIS/Core/Include/mpu_armv7.h | 275 + .../RaspberryPi/RP2040/Include/RP2040.h | 109 + .../RP2040/Include/system_RP2040.h | 65 + .../RaspberryPi/RP2040/Source/system_RP2040.c | 52 + .../rp2_common/cmsis/stub/CMSIS/LICENSE.txt | 201 + .../hardware_adc/include/hardware/adc.h | 41 +- .../include/hardware/address_mapped.h | 56 +- .../rp2_common/hardware_claim/CMakeLists.txt | 6 +- .../rp2_common/hardware_claim/claim.c | 27 +- .../hardware_claim/include/hardware/claim.h | 16 +- .../rp2_common/hardware_clocks/CMakeLists.txt | 6 +- .../rp2_common/hardware_clocks/clocks.c | 17 +- .../hardware_clocks/include/hardware/clocks.h | 6 +- .../hardware_divider/CMakeLists.txt | 3 +- .../include/hardware/divider.h | 40 +- .../include/hardware/divider_helper.S | 68 + .../pico-sdk/rp2_common/hardware_dma/dma.c | 30 +- .../hardware_dma/include/hardware/dma.h | 209 +- .../hardware_exception/CMakeLists.txt | 1 + .../rp2_common/hardware_exception/exception.c | 65 + .../include/hardware/exception.h | 106 + .../rp2_common/hardware_flash/CMakeLists.txt | 10 +- .../rp2_common/hardware_flash/flash.c | 51 +- .../hardware_flash/include/hardware/flash.h | 57 +- .../pico-sdk/rp2_common/hardware_gpio/gpio.c | 74 +- .../hardware_gpio/include/hardware/gpio.h | 141 +- .../pico-sdk/rp2_common/hardware_i2c/i2c.c | 116 +- .../hardware_i2c/include/hardware/i2c.h | 90 +- .../hardware_interp/include/hardware/interp.h | 33 +- .../rp2_common/hardware_interp/interp.c | 21 +- .../hardware_irq/include/hardware/irq.h | 63 +- .../pico-sdk/rp2_common/hardware_irq/irq.c | 86 +- .../hardware_irq/irq_handler_chain.S | 2 +- .../hardware_pio/include/hardware/pio.h | 508 +- .../include/hardware/pio_instructions.h | 366 +- .../pico-sdk/rp2_common/hardware_pio/pio.c | 42 +- .../hardware_pll/include/hardware/pll.h | 2 +- .../pico-sdk/rp2_common/hardware_pll/pll.c | 35 +- .../hardware_pwm/include/hardware/pwm.h | 174 +- .../rp2_common/hardware_resets/CMakeLists.txt | 3 +- .../hardware_resets/include/hardware/resets.h | 8 + .../hardware_rtc/include/hardware/rtc.h | 19 +- .../pico-sdk/rp2_common/hardware_rtc/rtc.c | 79 +- .../hardware_spi/include/hardware/spi.h | 111 +- .../hardware_spi/include/placeholder.h | 0 .../pico-sdk/rp2_common/hardware_spi/spi.c | 39 +- .../hardware_sync/include/hardware/sync.h | 143 +- .../pico-sdk/rp2_common/hardware_sync/sync.c | 10 +- .../hardware_timer/include/hardware/timer.h | 34 +- .../rp2_common/hardware_timer/timer.c | 55 +- .../hardware_uart/include/hardware/uart.h | 81 +- .../pico-sdk/rp2_common/hardware_uart/uart.c | 4 +- .../pico-sdk/rp2_common/hardware_vreg/vreg.c | 2 +- .../include/hardware/watchdog.h | 41 +- .../rp2_common/hardware_watchdog/watchdog.c | 31 +- .../hardware_xosc/include/hardware/xosc.h | 9 + .../pico-sdk/rp2_common/hardware_xosc/xosc.c | 21 +- .../rp2_common/pico_bit_ops/CMakeLists.txt | 15 +- .../rp2_common/pico_bit_ops/bit_ops_aeabi.S | 10 +- .../rp2_common/pico_bootrom/bootrom.c | 4 +- .../pico_bootrom/include/pico/bootrom.h | 87 +- .../CMakeLists.txt | 10 + .../pico_bootsel_via_double_reset.c | 85 + .../rp2_common/pico_divider/CMakeLists.txt | 13 +- .../rp2_common/pico_divider/divider.S | 133 +- .../rp2_common/pico_double/CMakeLists.txt | 18 +- .../rp2_common/pico_double/double_aeabi.S | 102 +- .../rp2_common/pico_double/double_init_rom.c | 14 +- .../rp2_common/pico_double/double_math.c | 83 +- .../pico_double/double_v1_rom_shim.S | 26 +- .../CMakeLists.txt | 2 +- .../rp2040_usb_device_enumeration.c | 25 +- .../rp2_common/pico_float/CMakeLists.txt | 21 +- .../rp2_common/pico_float/float_aeabi.S | 73 +- .../rp2_common/pico_float/float_init_rom.c | 14 +- .../rp2_common/pico_float/float_math.c | 125 +- .../rp2_common/pico_float/float_none.S | 1 + .../rp2_common/pico_float/float_v1_rom_shim.S | 2 +- .../pico_float/include/placeholder.h | 0 .../rp2_common/pico_int64_ops/CMakeLists.txt | 15 +- .../pico_int64_ops/pico_int64_ops_aeabi.S | 4 + .../rp2_common/pico_malloc/CMakeLists.txt | 4 +- .../pico_malloc/include/pico/malloc.h | 2 +- .../rp2_common/pico_malloc/pico_malloc.c | 7 +- .../rp2_common/pico_mem_ops/CMakeLists.txt | 16 +- .../rp2_common/pico_mem_ops/mem_ops_aeabi.S | 25 +- .../rp2_common/pico_multicore/CMakeLists.txt | 8 +- .../pico_multicore/include/pico/multicore.h | 217 +- .../rp2_common/pico_multicore/multicore.c | 62 +- .../rp2_common/pico_platform/CMakeLists.txt | 2 +- .../pico_platform/include/pico/asm_helper.S | 8 +- .../pico_platform/include/pico/platform.h | 389 +- .../rp2_common/pico_platform/platform.c | 14 +- .../rp2_common/pico_printf/CMakeLists.txt | 19 +- .../pico_printf/include/pico/printf.h | 2 +- .../pico-sdk/rp2_common/pico_printf/printf.c | 53 +- .../rp2_common/pico_runtime/CMakeLists.txt | 2 +- .../rp2_common/pico_runtime/runtime.c | 116 +- .../pico_standard_link/CMakeLists.txt | 10 +- .../pico_standard_link/binary_info.c | 16 +- .../rp2_common/pico_standard_link/crt0.S | 55 +- .../pico_standard_link/new_delete.cpp | 10 +- .../rp2_common/pico_stdio/CMakeLists.txt | 3 +- .../pico_stdio/include/pico/stdio.h | 23 +- .../pico_stdio/include/pico/stdio/driver.h | 2 +- .../pico-sdk/rp2_common/pico_stdio/stdio.c | 91 +- .../pico_stdio_semihosting/CMakeLists.txt | 6 +- .../include/pico/stdio_semihosting.h | 10 +- .../stdio_semihosting.c | 6 +- .../rp2_common/pico_stdio_uart/CMakeLists.txt | 6 +- .../pico_stdio_uart/include/pico/stdio_uart.h | 16 +- .../rp2_common/pico_stdio_uart/stdio_uart.c | 30 +- .../rp2_common/pico_stdio_usb/CMakeLists.txt | 11 +- .../pico_stdio_usb/include/pico/stdio_usb.h | 81 +- .../include/pico/stdio_usb/reset_interface.h | 13 + .../pico_stdio_usb/include/tusb_config.h | 4 + .../pico_stdio_usb/reset_interface.c | 112 + .../rp2_common/pico_stdio_usb/stdio_usb.c | 32 +- .../pico_stdio_usb/stdio_usb_descriptors.c | 50 +- .../rp2_common/pico_stdlib/CMakeLists.txt | 2 +- .../pico-sdk/rp2_common/pico_stdlib/stdlib.c | 4 +- .../rp2_common/pico_unique_id/CMakeLists.txt | 2 +- .../pico_unique_id/include/pico/unique_id.h | 17 + .../rp2_common/pico_unique_id/unique_id.c | 13 +- .../rp2_common/tinyusb/CMakeLists.txt | 94 +- 290 files changed, 57310 insertions(+), 24766 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/generate_config_header.cmake delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_at25sf128a.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/compile_time_choice.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/include/boot_stage2/config.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/exception.c create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c delete mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/reset_interface.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt index 5d7a4c77833..f800c2f8623 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/CMakeLists.txt @@ -11,10 +11,12 @@ if (NOT EXISTS "${PICO_PLATFORM_CMAKE_FILE}") Either specify a valid PICO_PLATFORM (or PICO_PLATFORM_CMAKE_FILE).") endif () +# Initialize board related build/compile settings include(${CMAKE_CURRENT_LIST_DIR}/board_setup.cmake) -# todo add option to disable skip flag +# call add_subdirectory(subdir) unless SKIP_SUBDIR evaluates to true function(pico_add_subdirectory subdir) + # todo add option to disable skip flag string(TOUPPER ${subdir} subdir_upper) set(replace_flag SKIP_${subdir_upper}) if (NOT ${replace_flag}) @@ -22,26 +24,41 @@ function(pico_add_subdirectory subdir) else () message("Not including ${subdir} because ${replace_flag} defined.") endif () + pico_promote_common_scope_vars() endfunction() +# add a link option to wrap the given function name; i.e. -Wl:wrap=FUNCNAME for gcc function(pico_wrap_function TARGET FUNCNAME) target_link_options(${TARGET} INTERFACE "LINKER:--wrap=${FUNCNAME}") endfunction() +# add map file generation for the given target function(pico_add_map_output TARGET) get_target_property(target_type ${TARGET} TYPE) if ("EXECUTABLE" STREQUAL "${target_type}") - target_link_options(${TARGET} PRIVATE "LINKER:-Map=$${CMAKE_EXECUTABLE_SUFFIX}.map") + target_link_options(${TARGET} PRIVATE "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") else () - target_link_options(${TARGET} INTERFACE "LINKER:-Map=$${CMAKE_EXECUTABLE_SUFFIX}.map") + target_link_options(${TARGET} INTERFACE "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") endif () endfunction() +# create a hardware_NAME_headers target (see pico_pico_simple_hardware_headers_target) +# create a hardware_NAME target (see pico_pico_simple_hardware_target) macro(pico_simple_hardware_target NAME) pico_simple_hardware_headers_target(${NAME}) pico_simple_hardware_impl_target(${NAME}) endmacro() +# create an INTERFACE library named target, and define LIB_TARGET=1 (upper case) as a compile option +function(pico_add_impl_library target) + add_library(${target} INTERFACE) + string(TOUPPER ${target} TARGET_UPPER) + target_compile_definitions(${target} INTERFACE LIB_${TARGET_UPPER}=1) +endfunction() + +# create an INTERFACE library named hardware_NAME_headers INTERFACE library if it doesn't already exist, +# and add include/ relative to the calling directory to the includes. +# and hardware_structs and hardware_claim as dependencies of the library macro(pico_simple_hardware_headers_target NAME) if (NOT TARGET hardware_${NAME}_headers) add_library(hardware_${NAME}_headers INTERFACE) @@ -54,8 +71,15 @@ macro(pico_simple_hardware_headers_target NAME) endif() endmacro() +# create an INTERFACE library named hardware_NAME if it doesn't exist, along with a hardware_NAME_headers +# INTERFACE library that it depends on. The hardware_NAME_headers library add include/ relative to +# and pico_base_headers, and harddware_structs as a dependency of the library macro(pico_simple_hardware_headers_only_target NAME) if (NOT TARGET hardware_${NAME}) + # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't + # super interesting except to determine functionality as they are mostly passive accessors, however + # they could be useful to determine if the header is available. + # pico_add_sdk_impl_library(hardware_${NAME}) add_library(hardware_${NAME} INTERFACE) target_include_directories(hardware_${NAME} INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) @@ -66,8 +90,14 @@ macro(pico_simple_hardware_headers_only_target NAME) endif() endmacro() +# create an INTERFACE library named hardware_NAME if it doesn't exist, dependent on a pre-existing hardware_NAME_headers +# INTERFACE library and pico_platform. The file NAME.c relative to the caller is added to the C sources for the hardware_NAME macro(pico_simple_hardware_impl_target NAME) if (NOT TARGET hardware_${NAME}) + # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't + # super interesting except to determine functionality as they are mostly passive accessors, however + # they could be useful to determine if the header is available. + # pico_add_sdk_impl_library(hardware_${NAME}) add_library(hardware_${NAME} INTERFACE) target_sources(hardware_${NAME} INTERFACE @@ -86,4 +116,6 @@ function(pico_add_doxygen_exclude SOURCE_DIR) set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "") endfunction() -include(${PICO_PLATFORM_CMAKE_FILE}) \ No newline at end of file +include(${PICO_PLATFORM_CMAKE_FILE}) + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake index 86b80f9e0a6..405d7848591 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/board_setup.cmake @@ -1,4 +1,4 @@ -# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=rp2040, group=build +# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=pico, group=build if (DEFINED ENV{PICO_BOARD}) set(PICO_BOARD $ENV{PICO_BOARD}) message("Using PICO_BOARD from environment ('${PICO_BOARD}')") diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h new file mode 100644 index 00000000000..2da8e7009c4 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_H +#define _BOARDS_ADAFRUIT_FEATHER_RP2040_H + +// For board detection +#define ADAFRUIT_FEATHER_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 13 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +//------------- FLASH -------------// + +// Use slower generic flash access +#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h new file mode 100644 index 00000000000..f9d27e919f2 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H +#define _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H + +// For board detection +#define ADAFRUIT_ITSYBITSY_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 11 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 17 +#endif + +#ifndef PICO_DEFAULT_WS2812_POWER_PIN +#define PICO_DEFAULT_WS2812_POWER_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h new file mode 100644 index 00000000000..24184c27ffe --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_QTPY_RP2040_H +#define _BOARDS_ADAFRUIT_QTPY_RP2040_H + +// For board detection +#define ADAFRUIT_QTPY_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +//------------- LED -------------// +// No normal LED +// #define PICO_DEFAULT_LED_PIN 13 + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 12 +#endif + +#ifndef PICO_DEFAULT_WS2812_POWER_PIN +#define PICO_DEFAULT_WS2812_POWER_PIN 11 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 24 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 25 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h new file mode 100644 index 00000000000..f9b49df74d3 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H +#define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H + +// For board detection +#define ADAFRUIT_TRINKEY_QT2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +//------------- LED -------------// +// No normal LED +// #define PICO_DEFAULT_LED_PIN 13 + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 27 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 16 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 17 +#endif + +//------------- SPI -------------// +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h new file mode 100644 index 00000000000..39c6564fb85 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H +#define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H + +// For board detection +#define ARDUINO_NANO_RP2040_CONNECT + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 6 +#endif +// no PICO_DEFAULT_WS2812_PIN + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 12 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 13 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h new file mode 100644 index 00000000000..d07ca612309 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H +#define _BOARDS_MELOPERO_SHAKE_RP2040_H + +// For board detection +#define MELOPERO_SHAKE_RP2040 + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 8 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 9 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 13 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 1 +#endif + +//------------- FLASH -------------// + + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h index c1ab7819a24..9e7f5375218 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h @@ -14,21 +14,57 @@ #ifndef _BOARDS_PICO_H #define _BOARDS_PICO_H +// For board detection +#define RASPBERRYPI_PICO + +// --- UART --- #ifndef PICO_DEFAULT_UART #define PICO_DEFAULT_UART 0 #endif - #ifndef PICO_DEFAULT_UART_TX_PIN #define PICO_DEFAULT_UART_TX_PIN 0 #endif - #ifndef PICO_DEFAULT_UART_RX_PIN #define PICO_DEFAULT_UART_RX_PIN 1 #endif +// --- LED --- #ifndef PICO_DEFAULT_LED_PIN #define PICO_DEFAULT_LED_PIN 25 #endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 #ifndef PICO_FLASH_SPI_CLKDIV #define PICO_FLASH_SPI_CLKDIV 2 @@ -41,12 +77,8 @@ // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 #endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h new file mode 100644 index 00000000000..e2621b0bf27 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_INTERSTATE75_H +#define _BOARDS_PIMORONI_INTERSTATE75_H + +// For board detection +#define PIMORONI_INTERSTATE75 + +// --- BOARD SPECIFIC --- +#ifndef INTERSTATE75_R0_PIN +#define INTERSTATE75_R0_PIN 0 +#endif + +#ifndef INTERSTATE75_G0_PIN +#define INTERSTATE75_G0_PIN 1 +#endif + +#ifndef INTERSTATE75_B0_PIN +#define INTERSTATE75_B0_PIN 2 +#endif + +#ifndef INTERSTATE75_R1_PIN +#define INTERSTATE75_R1_PIN 3 +#endif + +#ifndef INTERSTATE75_G1_PIN +#define INTERSTATE75_G1_PIN 4 +#endif + +#ifndef INTERSTATE75_B1_PIN +#define INTERSTATE75_B1_PIN 5 +#endif + +#ifndef INTERSTATE75_ROW_A_PIN +#define INTERSTATE75_ROW_A_PIN 6 +#endif + +#ifndef INTERSTATE75_ROW_B_PIN +#define INTERSTATE75_ROW_B_PIN 7 +#endif + +#ifndef INTERSTATE75_ROW_C_PIN +#define INTERSTATE75_ROW_C_PIN 8 +#endif + +#ifndef INTERSTATE75_ROW_D_PIN +#define INTERSTATE75_ROW_D_PIN 9 +#endif + +#ifndef INTERSTATE75_ROW_E_PIN +#define INTERSTATE75_ROW_E_PIN 10 +#endif + +#ifndef INTERSTATE75_CLK_PIN +#define INTERSTATE75_CLK_PIN 11 +#endif + +#ifndef INTERSTATE75_LAT_PIN +#define INTERSTATE75_LAT_PIN 12 +#endif + +#ifndef INTERSTATE75_OE_PIN +#define INTERSTATE75_OE_PIN 13 +#endif + +#ifndef INTERSTATE75_SW_A_PIN +#define INTERSTATE75_SW_A_PIN 14 +#endif + +#ifndef INTERSTATE75_LED_R_PIN +#define INTERSTATE75_LED_R_PIN 16 +#endif + +#ifndef INTERSTATE75_LED_G_PIN +#define INTERSTATE75_LED_G_PIN 17 +#endif + +#ifndef INTERSTATE75_LED_B_PIN +#define INTERSTATE75_LED_B_PIN 18 +#endif + +#ifndef INTERSTATE75_I2C +#define INTERSTATE75_I2C 0 +#endif + +#ifndef INTERSTATE75_INT_PIN +#define INTERSTATE75_INT_PIN 19 +#endif + +#ifndef INTERSTATE75_SDA_PIN +#define INTERSTATE75_SDA_PIN 20 +#endif + +#ifndef INTERSTATE75_SCL_PIN +#define INTERSTATE75_SCL_PIN 21 +#endif + +#ifndef INTERSTATE75_USER_SW_PIN +#define INTERSTATE75_USER_SW_PIN 23 +#endif + +#ifndef INTERSTATE75_A0_PIN +#define INTERSTATE75_A0_PIN 26 +#endif + +#ifndef INTERSTATE75_A1_PIN +#define INTERSTATE75_A1_PIN 27 +#endif + +#ifndef INTERSTATE75_A2_PIN +#define INTERSTATE75_A2_PIN 28 +#endif + +#ifndef INTERSTATE75_NUM_ADC_PINS +#define INTERSTATE75_NUM_ADC_PINS 3 +#endif + +#ifndef INTERSTATE75_CURRENT_SENSE_PIN +#define INTERSTATE75_CURRENT_SENSE_PIN 29 +#endif + +// --- UART --- +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN INTERSTATE75_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C INTERSTATE75_I2C +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN INTERSTATE75_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN INTERSTATE75_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h new file mode 100644 index 00000000000..43772e84014 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_KEYBOW2040_H +#define _BOARDS_PIMORONI_KEYBOW2040_H + +// For board detection +#define PIMORONI_KEYBOW2040 + +// --- BOARD SPECIFIC --- +#ifndef KEYBOW2040_I2C_SDA_PIN +#define KEYBOW2040_I2C_SDA_PIN 4 +#endif + +#ifndef KEYBOW2040_I2C_SCL_PIN +#define KEYBOW2040_I2C_SCL_PIN 5 +#endif + +#ifndef KEYBOW2040_I2C_INT_PIN +#define KEYBOW2040_I2C_INT_PIN 3 +#endif + +#ifndef KEYBOW2040_USER_SW_PIN +#define KEYBOW2040_USER_SW_PIN 23 +#endif + +#ifndef KEYBOW2040_SW0_PIN +#define KEYBOW2040_SW0_PIN 21 +#endif + +#ifndef KEYBOW2040_SW1_PIN +#define KEYBOW2040_SW1_PIN 20 +#endif + +#ifndef KEYBOW2040_SW2_PIN +#define KEYBOW2040_SW2_PIN 19 +#endif + +#ifndef KEYBOW2040_SW3_PIN +#define KEYBOW2040_SW3_PIN 18 +#endif + +#ifndef KEYBOW2040_SW4_PIN +#define KEYBOW2040_SW4_PIN 17 +#endif + +#ifndef KEYBOW2040_SW5_PIN +#define KEYBOW2040_SW5_PIN 16 +#endif + +#ifndef KEYBOW2040_SW6_PIN +#define KEYBOW2040_SW6_PIN 15 +#endif + +#ifndef KEYBOW2040_SW7_PIN +#define KEYBOW2040_SW7_PIN 14 +#endif + +#ifndef KEYBOW2040_SW8_PIN +#define KEYBOW2040_SW8_PIN 13 +#endif + +#ifndef KEYBOW2040_SW9_PIN +#define KEYBOW2040_SW9_PIN 12 +#endif + +#ifndef KEYBOW2040_SW10_PIN +#define KEYBOW2040_SW10_PIN 11 +#endif + +#ifndef KEYBOW2040_SW11_PIN +#define KEYBOW2040_SW11_PIN 10 +#endif + +#ifndef KEYBOW2040_SW12_PIN +#define KEYBOW2040_SW12_PIN 9 +#endif + +#ifndef KEYBOW2040_SW13_PIN +#define KEYBOW2040_SW13_PIN 8 +#endif + +#ifndef KEYBOW2040_SW14_PIN +#define KEYBOW2040_SW14_PIN 7 +#endif + +#ifndef KEYBOW2040_SW15_PIN +#define KEYBOW2040_SW15_PIN 6 +#endif + +#ifndef KEYBOW2040_NUM_SWITCHES_PINS +#define KEYBOW2040_NUM_SWITCHES_PINS 16 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN KEYBOW2040_I2C_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN KEYBOW2040_I2C_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h new file mode 100644 index 00000000000..980f1680020 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PGA2040_H +#define _BOARDS_PIMORONI_PGA2040_H + +// For board detection +#define PIMORONI_PGA2040 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h new file mode 100644 index 00000000000..338977b44e5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOLIPO_16MB_H +#define _BOARDS_PIMORONI_PICOLIPO_16MB_H + +// For board detection +#define PIMORONI_PICOLIPO_16MB + +// --- BOARD SPECIFIC --- +#ifndef PICOLIPO_USER_SW_PIN +#define PICOLIPO_USER_SW_PIN 23 +#endif + +#ifndef PICOLIPO_VBUS_DETECT_PIN +#define PICOLIPO_VBUS_DETECT_PIN 24 +#endif + +#ifndef PICOLIPO_BAT_SENSE_PIN +#define PICOLIPO_BAT_SENSE_PIN 29 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h new file mode 100644 index 00000000000..871ed8368a1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOLIPO_4MB_H +#define _BOARDS_PIMORONI_PICOLIPO_4MB_H + +// For board detection +#define PIMORONI_PICOLIPO_4MB + +// --- BOARD SPECIFIC --- +#ifndef PICOLIPO_USER_SW_PIN +#define PICOLIPO_USER_SW_PIN 23 +#endif + +#ifndef PICOLIPO_VBUS_DETECT_PIN +#define PICOLIPO_VBUS_DETECT_PIN 24 +#endif + +#ifndef PICOLIPO_BAT_SENSE_PIN +#define PICOLIPO_BAT_SENSE_PIN 29 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h new file mode 100644 index 00000000000..1e7c80e82c7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOSYSTEM_H +#define _BOARDS_PIMORONI_PICOSYSTEM_H + +// For board detection +#define PIMORONI_PICOSYSTEM + +// --- BOARD SPECIFIC --- +#ifndef PICOSYSTEM_VBUS_DETECT_PIN +#define PICOSYSTEM_VBUS_DETECT_PIN 2 +#endif + +#ifndef PICOSYSTEM_LCD_SPI +#define PICOSYSTEM_LCD_SPI 0 +#endif + +#ifndef PICOSYSTEM_LCD_RESET_PIN +#define PICOSYSTEM_LCD_RESET_PIN 4 +#endif + +#ifndef PICOSYSTEM_LCD_CSN_PIN +#define PICOSYSTEM_LCD_CSN_PIN 5 +#endif + +#ifndef PICOSYSTEM_LCD_SCLK_PIN +#define PICOSYSTEM_LCD_SCLK_PIN 6 +#endif + +#ifndef PICOSYSTEM_LCD_MOSI_PIN +#define PICOSYSTEM_LCD_MOSI_PIN 7 +#endif + +#ifndef PICOSYSTEM_LCD_VSYNC_PIN +#define PICOSYSTEM_LCD_VSYNC_PIN 8 +#endif + +#ifndef PICOSYSTEM_LCD_DC_PIN +#define PICOSYSTEM_LCD_DC_PIN 9 +#endif + +#ifndef PICOSYSTEM_AUDIO_PIN +#define PICOSYSTEM_AUDIO_PIN 11 +#endif + +#ifndef PICOSYSTEM_BACKLIGHT_PIN +#define PICOSYSTEM_BACKLIGHT_PIN 12 +#endif + +#ifndef PICOSYSTEM_LED_G_PIN +#define PICOSYSTEM_LED_G_PIN 13 +#endif + +#ifndef PICOSYSTEM_LED_R_PIN +#define PICOSYSTEM_LED_R_PIN 14 +#endif + +#ifndef PICOSYSTEM_LED_B_PIN +#define PICOSYSTEM_LED_B_PIN 15 +#endif + +#ifndef PICOSYSTEM_SW_Y_PIN +#define PICOSYSTEM_SW_Y_PIN 16 +#endif + +#ifndef PICOSYSTEM_SW_X_PIN +#define PICOSYSTEM_SW_X_PIN 17 +#endif + +#ifndef PICOSYSTEM_SW_A_PIN +#define PICOSYSTEM_SW_A_PIN 18 +#endif + +#ifndef PICOSYSTEM_SW_B_PIN +#define PICOSYSTEM_SW_B_PIN 19 +#endif + +#ifndef PICOSYSTEM_SW_DOWN_PIN +#define PICOSYSTEM_SW_DOWN_PIN 20 +#endif + +#ifndef PICOSYSTEM_SW_RIGHT_PIN +#define PICOSYSTEM_SW_RIGHT_PIN 21 +#endif + +#ifndef PICOSYSTEM_SW_LEFT_PIN +#define PICOSYSTEM_SW_LEFT_PIN 22 +#endif + +#ifndef PICOSYSTEM_SW_UP_PIN +#define PICOSYSTEM_SW_UP_PIN 23 +#endif + +#ifndef PICOSYSTEM_CHARGE_STAT_PIN +#define PICOSYSTEM_CHARGE_STAT_PIN 24 +#endif + +#ifndef PICOSYSTEM_BAT_SENSE_PIN +#define PICOSYSTEM_BAT_SENSE_PIN 26 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN PICOSYSTEM_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +//no PICO_DEFAULT_I2C +//no PICO_DEFAULT_I2C_SDA_PIN +//no PICO_DEFAULT_I2C_SCL_PIN + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h new file mode 100644 index 00000000000..226aaf53847 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PLASMA2040_H +#define _BOARDS_PIMORONI_PLASMA2040_H + +// For board detection +#define PIMORONI_PLASMA2040 + +// --- BOARD SPECIFIC --- +#ifndef PLASMA2040_SW_A_PIN +#define PLASMA2040_SW_A_PIN 12 +#endif + +#ifndef PLASMA2040_SW_B_PIN +#define PLASMA2040_SW_B_PIN 13 +#endif + +#ifndef PLASMA2040_CLK_PIN +#define PLASMA2040_CLK_PIN 14 +#endif + +#ifndef PLASMA2040_DATA_PIN +#define PLASMA2040_DATA_PIN 15 +#endif + +#ifndef PLASMA2040_LED_R_PIN +#define PLASMA2040_LED_R_PIN 16 +#endif + +#ifndef PLASMA2040_LED_G_PIN +#define PLASMA2040_LED_G_PIN 17 +#endif + +#ifndef PLASMA2040_LED_B_PIN +#define PLASMA2040_LED_B_PIN 18 +#endif + +#ifndef PLASMA2040_I2C +#define PLASMA2040_I2C 0 +#endif + +#ifndef PLASMA2040_INT_PIN +#define PLASMA2040_INT_PIN 19 +#endif + +#ifndef PLASMA2040_SDA_PIN +#define PLASMA2040_SDA_PIN 20 +#endif + +#ifndef PLASMA2040_SCL_PIN +#define PLASMA2040_SCL_PIN 21 +#endif + +#ifndef PLASMA2040_USER_SW_PIN +#define PLASMA2040_USER_SW_PIN 23 +#endif + +#ifndef PLASMA2040_A0_PIN +#define PLASMA2040_A0_PIN 26 +#endif + +#ifndef PLASMA2040_A1_PIN +#define PLASMA2040_A1_PIN 27 +#endif + +#ifndef PLASMA2040_A2_PIN +#define PLASMA2040_A2_PIN 28 +#endif + +#ifndef PLASMA2040_NUM_ADC_PINS +#define PLASMA2040_NUM_ADC_PINS 3 +#endif + +#ifndef PLASMA2040_CURRENT_SENSE_PIN +#define PLASMA2040_CURRENT_SENSE_PIN 29 +#endif + +// --- UART --- +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN PLASMA2040_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C PLASMA2040_I2C +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2040_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2040_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h new file mode 100644 index 00000000000..51d17f66a4b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_TINY2040_H +#define _BOARDS_PIMORONI_TINY2040_H + +// For board detection +#define PIMORONI_TINY2040 + +// --- BOARD SPECIFIC --- +#ifndef TINY2040_LED_R_PIN +#define TINY2040_LED_R_PIN 18 +#endif + +#ifndef TINY2040_LED_G_PIN +#define TINY2040_LED_G_PIN 19 +#endif + +#ifndef TINY2040_LED_B_PIN +#define TINY2040_LED_B_PIN 20 +#endif + +#ifndef TINY2040_USER_SW_PIN +#define TINY2040_USER_SW_PIN 23 +#endif + +#ifndef TINY2040_A0_PIN +#define TINY2040_A0_PIN 26 +#endif + +#ifndef TINY2040_A1_PIN +#define TINY2040_A1_PIN 27 +#endif + +#ifndef TINY2040_A2_PIN +#define TINY2040_A2_PIN 28 +#endif + +#ifndef TINY2040_A3_PIN +#define TINY2040_A3_PIN 29 +#endif + +#ifndef TINY2040_NUM_IO_PINS +#define TINY2040_NUM_IO_PINS 8 +#endif + +#ifndef TINY2040_NUM_ADC_PINS +#define TINY2040_NUM_ADC_PINS 4 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN TINY2040_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 5 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h new file mode 100644 index 00000000000..8a9ca415605 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PYBSTICK26_RP2040_H +#define _BOARDS_PYBSTICK26_RP2040_H + +// For board detection +#define PYBSTICK26_RP2040 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 23 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 10 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 11 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 8 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 9 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +// Linear regulator on Pybstick26 +//#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif +// of #define _BOARDS_PYBSTICK26_RP2040_H diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h new file mode 100644 index 00000000000..0c6e5687c5e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 MicroMod processor board +// +// This header may be included by other board headers as "boards/sparkfun_micromod.h" + +#ifndef _BOARDS_SPARKFUN_MICROMOD_H +#define _BOARDS_SPARKFUN_MICROMOD_H + +// For board detection +#define SPARKFUN_MICROMOD + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// Default I2C - for qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// spi flash +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h new file mode 100644 index 00000000000..45bb4a244f7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 ProMicro +// +// This header may be included by other board headers as "boards/sparkfun_promicro.h" + +#ifndef _BOARDS_SPARKFUN_PROMICRO_H +#define _BOARDS_SPARKFUN_PROMICRO_H + +// For board detection +#define SPARKFUN_PROMICRO + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// The PRO Micro doesnt have a plain LED, but a WS2812 +//#ifndef PICO_DEFAULT_LED_PIN +//#define PICO_DEFAULT_LED_PIN 25 +//#endif +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 25 +#endif + +// Default I2C - for the onboard qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 16 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 17 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// board has 16M onboard flash +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h new file mode 100644 index 00000000000..d1e69d566f7 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 Thing Plus +// +// This header may be included by other board headers as "boards/sparkfun_thingplus.h" + +#ifndef _BOARDS_SPARKFUN_THINGPLUS_H +#define _BOARDS_SPARKFUN_THINGPLUS_H + +// For board detection +#define SPARKFUN_THINGPLUS + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// Default I2C - for qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 2 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + + +// spi flash + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// The thing plus has a SD Card. +#define PICO_SD_CLK_PIN 14 +#define PICO_SD_CMD_PIN 15 +#define PICO_SD_DAT0_PIN 12 +// DAT pins count down +#define PICO_SD_DAT_PIN_INCREMENT -1 + +#ifndef PICO_SD_DAT_PIN_COUNT +#define PICO_SD_DAT_PIN_COUNT 4 +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h index e2c3674c26d..f0b6f0e1007 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h @@ -12,21 +12,8 @@ #ifndef _BOARDS_VGABOARD_H #define _BOARDS_VGABOARD_H -#ifndef PICO_DEFAULT_UART -#define PICO_DEFAULT_UART 1 -#endif - -#ifndef PICO_DEFAULT_UART_TX_PIN -#define PICO_DEFAULT_UART_TX_PIN 20 -#endif - -#ifndef PICO_DEFAULT_UART_RX_PIN -#define PICO_DEFAULT_UART_RX_PIN 21 -#endif - -#ifndef PICO_DEFAULT_LED_PIN -#define PICO_DEFAULT_LED_PIN 25 // same as Pico -#endif +// For board detection +#define RASPBERRYPI_VGABOARD // Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R. // - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as @@ -42,8 +29,8 @@ #define VGABOARD_VGA_COLOR_PIN_BASE 0 #define VGABOARD_VGA_SYNC_PIN_BASE 16 -// Note DAT2/3 are shared with UART TX/RX (pull jumpers off header to access -// UART pins and disconnect SD DAT2/3) +// Note DAT1/2 are shared with UART TX/RX (pull jumpers off header to access +// UART pins and disconnect SD DAT1/2) #define VGABOARD_SD_CLK_PIN 5 #define VGABOARD_SD_CMD_PIN 18 #define VGABOARD_SD_DAT0_PIN 19 @@ -54,51 +41,42 @@ #define VGABOARD_BUTTON_B_PIN 6 #define VGABOARD_BUTTON_C_PIN 11 -#ifndef PICO_SCANVIDEO_COLOR_PIN_BASE -#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 #endif -#ifndef PICO_SCANVIDEO_SYMC_PIN_BASE -#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 20 #endif -#ifndef PICO_SD_CLK_PIN -#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 21 #endif -#ifndef PICO_SD_CMD_PIN -#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN -#endif +#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE +#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE -#ifndef PICO_SD_DAT0_PIN +#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN +#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN #define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN + +// 1 or 4 +#ifndef PICO_SD_DAT_PIN_COUNT +#define PICO_SD_DAT_PIN_COUNT 4 #endif +// 1 or -1 +#define PICO_SD_DAT_PIN_INCREMENT 1 + #define PICO_AUDIO_I2S_DATA_PIN VGABOARD_I2S_DIN_PIN #define PICO_AUDIO_I2S_CLOCK_PIN_BASE VGABOARD_I2S_BCK_PIN #define PICO_AUDIO_PWM_L_PIN VGABOARD_PWM_L_PIN #define PICO_AUDIO_PWM_R_PIN VGABOARD_PWM_R_PIN -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 2 -#endif - -#ifndef PICO_FLASH_SIZE_BYTES -#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) -#endif - -// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) -#define PICO_SMPS_MODE_PIN 23 - -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 -#endif - #define PICO_VGA_BOARD +// vgaboard has a Pico on it, so default anything we haven't set above +#include "boards/pico.h" + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h new file mode 100644 index 00000000000..8c59c5c49fe --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H +#define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H + +// For board detection +#define WAVESHARE_RP2040_LCD_0_96 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- LCD --- +#ifndef WAVESHARE_RP2040_LCD_SPI +#define WAVESHARE_RP2040_LCD_SPI 1 +#endif +#ifndef WAVESHARE_RP2040_LCD_DC_PIN +#define WAVESHARE_RP2040_LCD_DC_PIN 8 +#endif +#ifndef WAVESHARE_RP2040_LCD_CS_PIN +#define WAVESHARE_RP2040_LCD_CS_PIN 9 +#endif +#ifndef WAVESHARE_RP2040_LCD_SCLK_PIN +#define WAVESHARE_RP2040_LCD_SCLK_PIN 10 +#endif +#ifndef WAVESHARE_RP2040_LCD_TX_PIN +#define WAVESHARE_RP2040_LCD_TX_PIN 11 +#endif +#ifndef WAVESHARE_RP2040_LCD_RST_PIN +#define WAVESHARE_RP2040_LCD_RST_PIN 12 +#endif +#ifndef WAVESHARE_RP2040_LCD_BL_PIN +#define WAVESHARE_RP2040_LCD_BL_PIN 25 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h new file mode 100644 index 00000000000..6f5e1441c82 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H +#define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H + +// For board detection +#define WAVESHARE_RP2040_PLUS_16MB + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h new file mode 100644 index 00000000000..d8dd8f6b395 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H +#define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H + +// For board detection +#define WAVESHARE_RP2040_PLUS_4MB + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h new file mode 100644 index 00000000000..281b4dc8b45 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H +#define _BOARDS_WAVESHARE_RP2040_ZERO_H + +// For board detection +#define WAVESHARE_RP2040_ZERO + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- WS2812 --- +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 10 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 11 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 12 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 13 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt index 9b256a080cd..38cf238187b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/CMakeLists.txt @@ -1,6 +1,7 @@ pico_add_subdirectory(boot_picoboot) pico_add_subdirectory(boot_uf2) pico_add_subdirectory(pico_base) +pico_add_subdirectory(pico_usb_reset_interface) # PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build if (NOT PICO_BARE_METAL) @@ -13,4 +14,6 @@ if (NOT PICO_BARE_METAL) pico_add_subdirectory(pico_stdlib) endif() -pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) \ No newline at end of file +pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt index af04c121c7c..3555dc0c37e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/CMakeLists.txt @@ -1,40 +1,13 @@ if (NOT TARGET pico_base_headers) - # build the auto gen config headers - - set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES\n// DO NOT EDIT!\n") - string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER) - - macro(add_header_content_from_var VAR) - set(header_content "${header_content}\n\n// based on ${VAR}:\n") - foreach(var IN LISTS ${VAR}) - set(header_content "${header_content}\n#include \"${var}\"") - endforeach() - endmacro() - - # PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base - add_header_content_from_var(PICO_CONFIG_HEADER_FILES) - - # PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base - # PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base - add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) - - file(GENERATE - OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h - CONTENT "${header_content}" - ) - - configure_file( include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h) - add_library(pico_base_headers INTERFACE) target_include_directories(pico_base_headers INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base) - foreach(DIR IN LISTS PICO_INCLUDE_DIRS) - target_include_directories(pico_base_headers INTERFACE ${DIR}) - endforeach() - # PICO_BUILD_DEFINE: PICO_BOARD, Name of board, type=string, default=CMake PICO_BOARD variable, group=pico_base target_compile_definitions(pico_base_headers INTERFACE PICO_BOARD="${PICO_BOARD}") target_link_libraries(pico_base_headers INTERFACE pico_platform_headers) + + list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/generate_config_header.cmake) + pico_promote_common_scope_vars() endif() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/generate_config_header.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/generate_config_header.cmake new file mode 100644 index 00000000000..333dfa7507a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/generate_config_header.cmake @@ -0,0 +1,29 @@ +# build the auto gen config headers + +set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES\n// DO NOT EDIT!\n") +string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER) + +macro(add_header_content_from_var VAR) + set(header_content "${header_content}\n\n// based on ${VAR}:\n") + foreach(var IN LISTS ${VAR}) + set(header_content "${header_content}\n#include \"${var}\"") + endforeach() +endmacro() + +# PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base +add_header_content_from_var(PICO_CONFIG_HEADER_FILES) + +# PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base +# PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base +add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) + +file(GENERATE + OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h + CONTENT "${header_content}" + ) + +configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h) + +foreach(DIR IN LISTS PICO_INCLUDE_DIRS) + target_include_directories(pico_base_headers INTERFACE ${DIR}) +endforeach() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h index cdd5c237381..1b73651207b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h @@ -8,16 +8,18 @@ #define PICO_H_ /** \file pico.h -* \defgroup pico_base pico_base -* -* Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code + * \defgroup pico_base pico_base + * + * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code + * as it includes configuration headers and overrides in the correct order + * + * This header may be included by assembly code */ #include "pico/types.h" #include "pico/version.h" #include "pico/config.h" #include "pico/platform.h" -#include "pico/assert.h" #include "pico/error.h" #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h index 7d2beff9538..8910ebdb8cf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h @@ -7,7 +7,7 @@ #ifndef _PICO_ASSERT_H #define _PICO_ASSERT_H -#include "pico/types.h" +#include #ifdef __cplusplus @@ -36,7 +36,7 @@ extern "C" { #define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) #ifdef NDEBUG -extern void hard_assertion_failure(); +extern void hard_assertion_failure(void); static inline void hard_assert(bool condition, ...) { if (!condition) hard_assertion_failure(); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h index a0d5c0b4058..8d692694163 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h @@ -8,7 +8,7 @@ #define PICO_CONFIG_H_ // ----------------------------------------------------- -// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // OR USE #ifndef __ASSEMBLER__ guards // ------------- @@ -16,4 +16,6 @@ // PICO_CONFIG_HEADER_FILES and then PICO_SDK__CONFIG_INCLUDE_FILES // entries are dumped in order at build time into this generated header +#include "pico/config_autogen.h" + #endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h index 722a696f511..fadb45ec0d6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h @@ -7,6 +7,8 @@ #ifndef _PICO_ERROR_H #define _PICO_ERROR_H +#ifndef __ASSEMBLER__ + /*! * Common return codes from pico_sdk methods that return a status */ @@ -18,4 +20,6 @@ enum { PICO_ERROR_NO_DATA = -3, }; +#endif // !__ASSEMBLER__ + #endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h index 37a4c303c04..8e1627ca81b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h @@ -7,55 +7,67 @@ #ifndef _PICO_TYPES_H #define _PICO_TYPES_H +#ifndef __ASSEMBLER__ + +#include "pico/assert.h" + #include #include #include typedef unsigned int uint; -#ifdef NDEBUG /*! \typedef absolute_time_t \brief An opaque 64 bit timestamp in microseconds The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong time units where an absolute time is required. It is equivalent to uint64_t in release builds. - \see to_us_since_boot - \see update_us_since_boot + \see to_us_since_boot() + \see update_us_since_boot() + \ingroup timestamp */ +#ifdef NDEBUG typedef uint64_t absolute_time_t; +#else +typedef struct { + uint64_t _private_us_since_boot; +} absolute_time_t; +#endif /*! fn to_us_since_boot * \brief convert an absolute_time_t into a number of microseconds since boot. - * \param t the number of microseconds since boot - * \return an absolute_time_t value equivalent to t + * \param t the absolute time to convert + * \return a number of microseconds since boot, equivalent to t + * \ingroup timestamp */ static inline uint64_t to_us_since_boot(absolute_time_t t) { +#ifdef NDEBUG return t; +#else + return t._private_us_since_boot; +#endif } /*! fn update_us_since_boot * \brief update an absolute_time_t value to represent a given number of microseconds since boot * \param t the absolute time value to update - * \param us_since_boot the number of microseconds since boot to represent + * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable + * as a signed 64 bit integer + * \ingroup timestamp */ static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { +#ifdef NDEBUG *t = us_since_boot; +#else + assert(us_since_boot <= INT64_MAX); + t->_private_us_since_boot = us_since_boot; +#endif } +#ifdef NDEBUG #define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value #else -typedef struct { - uint64_t _private_us_since_boot; -} absolute_time_t; - -static inline uint64_t to_us_since_boot(absolute_time_t t) { - return t._private_us_since_boot; -} - -static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { - t->_private_us_since_boot = us_since_boot; -} #define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} #endif @@ -76,4 +88,7 @@ typedef struct { int8_t sec; ///< 0..59 } datetime_t; +#define bool_to_bit(x) ((uint)!!(x)) + +#endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt index 2660e9114ac..eb0c3f66b19 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/CMakeLists.txt @@ -2,7 +2,11 @@ add_library(pico_binary_info_headers INTERFACE) target_include_directories(pico_binary_info_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) -add_library(pico_binary_info INTERFACE) +if (COMMAND pico_add_platform_library) + pico_add_platform_library(pico_binary_info) +else() + add_library(pico_binary_info INTERFACE) +endif() target_link_libraries(pico_binary_info INTERFACE pico_binary_info_headers) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h index 2a641abda06..77b1c08a6ea 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h @@ -7,7 +7,9 @@ #ifndef _PICO_BINARY_INFO_H #define _PICO_BINARY_INFO_H -/** +/** \file binary_info.h + * \defgroup pico_binary_info pico_binary_info + * * Binary info is intended for embedding machine readable information with the binary in FLASH. * * Example uses include: @@ -20,9 +22,10 @@ #include "pico/binary_info/defs.h" #include "pico/binary_info/structure.h" -#if PICO_ON_DEVICE +#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO) +#define PICO_NO_BINARY_INFO 1 +#endif +#if !PICO_NO_BINARY_INFO #include "pico/binary_info/code.h" #endif - - -#endif \ No newline at end of file +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h index af3ce554e6b..e87a2cd1412 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h @@ -25,12 +25,14 @@ #endif /** * Declare some binary information that will be included if the contain source file/line is compiled into the binary + * \ingroup pico_binary_info */ #define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); /** * Declare some binary information that will be included if the function containing the decl is linked into the binary. * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated * binary information declared this way will also be stripped + * \ingroup pico_binary_info */ #define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;}); @@ -136,4 +138,4 @@ static const struct _binary_info_named_group __bi_lineno_var_name = { \ #define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2) #define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3) -#endif \ No newline at end of file +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h index 2e261b252b6..49d2fd690b1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h @@ -54,6 +54,7 @@ typedef struct _binary_info_core binary_info_t; #define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3 #define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab #define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb +#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1 #if PICO_ON_DEVICE #define bi_ptr_of(x) x * diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h index 04e62750d3d..da0eef53ca0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h @@ -44,18 +44,28 @@ extern "C" { // respective INTERFACE libraries, so these defines are set if the library // is included for the target executable -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART #include "pico/stdio_uart.h" #endif -#if PICO_STDIO_USB +#if LIB_PICO_STDIO_USB #include "pico/stdio_usb.h" #endif -#if PICO_STDIO_SEMIHOSTING +#if LIB_PICO_STDIO_SEMIHOSTING #include "pico/stdio_semihosting.h" #endif +// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib + +// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 0 +#endif + +// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib +// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib + /*! \brief Set up the default UART and assign it to the default GPIO's * \ingroup pico_stdlib * @@ -71,14 +81,14 @@ extern "C" { * PICO_DEFAULT_UART_TX_PIN * PICO_DEFAULT_UART_RX_PIN */ -void setup_default_uart(); +void setup_default_uart(void); /*! \brief Initialise the system clock to 48MHz * \ingroup pico_stdlib * * Set the system clock to 48MHz, and set the peripheral clock to match. */ -void set_sys_clock_48mhz(); +void set_sys_clock_48mhz(void); /*! \brief Initialise the system clock * \ingroup pico_stdlib diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt index 8d1d0f832f1..2f8bde2b8e0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/CMakeLists.txt @@ -5,7 +5,7 @@ if (NOT TARGET pico_sync_headers) endif() if (NOT TARGET pico_sync_core) - add_library(pico_sync_core INTERFACE) + pico_add_impl_library(pico_sync_core) target_sources(pico_sync_core INTERFACE ${CMAKE_CURRENT_LIST_DIR}/lock_core.c ) @@ -13,7 +13,7 @@ if (NOT TARGET pico_sync_core) endif() if (NOT TARGET pico_sync_sem) - add_library(pico_sync_sem INTERFACE) + pico_add_impl_library(pico_sync_sem) target_sources(pico_sync_sem INTERFACE ${CMAKE_CURRENT_LIST_DIR}/sem.c ) @@ -21,7 +21,7 @@ if (NOT TARGET pico_sync_sem) endif() if (NOT TARGET pico_sync_mutex) - add_library(pico_sync_mutex INTERFACE) + pico_add_impl_library(pico_sync_mutex) target_sources(pico_sync_mutex INTERFACE ${CMAKE_CURRENT_LIST_DIR}/mutex.c ) @@ -29,7 +29,7 @@ if (NOT TARGET pico_sync_mutex) endif() if (NOT TARGET pico_sync_critical_section) - add_library(pico_sync_critical_section INTERFACE) + pico_add_impl_library(pico_sync_critical_section) target_sources(pico_sync_critical_section INTERFACE ${CMAKE_CURRENT_LIST_DIR}/critical_section.c ) @@ -37,7 +37,7 @@ if (NOT TARGET pico_sync_critical_section) endif() if (NOT TARGET pico_sync) - add_library(pico_sync INTERFACE) + pico_add_impl_library(pico_sync) target_link_libraries(pico_sync INTERFACE pico_sync_sem pico_sync_mutex pico_sync_critical_section pico_sync_core) endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c index 5f47090d7c6..f28732b7f28 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/critical_section.c @@ -10,15 +10,18 @@ static_assert(sizeof(critical_section_t) == 8, ""); #endif -void critical_section_init(critical_section_t *critsec) { - critical_section_init_with_lock_num(critsec, spin_lock_claim_unused(true)); +void critical_section_init(critical_section_t *crit_sec) { + critical_section_init_with_lock_num(crit_sec, (uint)spin_lock_claim_unused(true)); } -void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num) { - lock_init(&critsec->core, lock_num); +void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num) { + crit_sec->spin_lock = spin_lock_instance(lock_num); __mem_fence_release(); } -void critical_section_deinit(critical_section_t *critsec) { - spin_lock_unclaim(spin_lock_get_num(critsec->core.spin_lock)); +void critical_section_deinit(critical_section_t *crit_sec) { + spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock)); +#ifndef NDEBUG + crit_sec->spin_lock = (spin_lock_t *)-1; +#endif } \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h index 17a8b3f4754..2f9449475c1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h @@ -22,11 +22,12 @@ extern "C" { * from the other core, and from (higher priority) interrupts on the same core. It does the former * using a spin lock and the latter by disabling interrupts on the calling core. * - * Because interrupts are disabled by this function, uses of the critical_section should be as short as possible. + * Because interrupts are disabled when a critical_section is owned, uses of the critical_section + * should be as short as possible. */ typedef struct __packed_aligned critical_section { - lock_core_t core; + spin_lock_t *spin_lock; uint32_t save; } critical_section_t; @@ -38,16 +39,16 @@ typedef struct __packed_aligned critical_section { * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num * to ensure that the spin lock's used are different. * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -void critical_section_init(critical_section_t *critsec); +void critical_section_init(critical_section_t *crit_sec); /*! \brief Initialise a critical_section structure assigning a specific spin lock number * \ingroup critical_section - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure * \param lock_num the specific spin lock number to use */ -void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num); +void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num); /*! \brief Enter a critical_section * \ingroup critical_section @@ -55,20 +56,32 @@ void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_ * If the spin lock associated with this critical section is in use, then this * method will block until it is released. * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -static inline void critical_section_enter_blocking(critical_section_t *critsec) { - critsec->save = spin_lock_blocking(critsec->core.spin_lock); +static inline void critical_section_enter_blocking(critical_section_t *crit_sec) { + crit_sec->save = spin_lock_blocking(crit_sec->spin_lock); } /*! \brief Release a critical_section * \ingroup critical_section * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -static inline void critical_section_exit(critical_section_t *critsec) { - spin_unlock(critsec->core.spin_lock, critsec->save); +static inline void critical_section_exit(critical_section_t *crit_sec) { + spin_unlock(crit_sec->spin_lock, crit_sec->save); } + +/*! \brief De-Initialise a critical_section created by the critical_section_init method + * \ingroup critical_section + * + * This method is only used to free the associated spin lock allocated via + * the critical_section_init method (it should not be used to de-initialize a spin lock + * created via critical_section_init_with_lock_num). After this call, the critical section is invalid + * + * \param crit_sec Pointer to critical_section structure + */ +void critical_section_deinit(critical_section_t *crit_sec); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h index 758eb94fb51..bf8bee7932e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h @@ -8,21 +8,190 @@ #define _PICO_LOCK_CORE_H #include "pico.h" +#include "pico/time.h" #include "hardware/sync.h" /** \file lock_core.h + * \defgroup lock_core lock_core * \ingroup pico_sync + * \brief base synchronization/lock primitive support * - * Base implementation for locking primitives protected by a spin lock + * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin + * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization + * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive. + * + * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing + * methods to lock and unlock said spin lock. + * + * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block + * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again. + * + * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for + * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait + * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment. + * + * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield), + * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting + * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is + * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call + * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts + * following the corresponding SEV is not missed. */ -typedef struct lock_core { + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync +#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE +#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0 +#endif + +/** \file lock_core.h + * \ingroup lock_core + * + * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect + * access to the remaining lock state (in primitives using lock_core); it is never left locked outside + * of the function implementations + */ +struct lock_core { // spin lock protecting this lock's state spin_lock_t *spin_lock; // note any lock members in containing structures need not be volatile; // they are protected by memory/compiler barriers when gaining and release spin locks -} lock_core_t; +}; +typedef struct lock_core lock_core_t; + +/*! \brief Initialise a lock structure + * \ingroup lock_core + * + * Inititalize a lock structure, providing the spin lock number to use for protecting internal state. + * + * \param core Pointer to the lock_core to initialize + * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive + * method implementations, this does not need to be globally unique, however could suffer contention + */ void lock_init(lock_core_t *core, uint lock_num); -#endif \ No newline at end of file +#ifndef lock_owner_id_t +/*! \brief type to use to store the 'owner' of a lock. + * \ingroup lock_core + * By default this is int8_t as it only needs to store the core number or -1, however it may be + * overridden if a larger type is required (e.g. for an RTOS task id) + */ +#define lock_owner_id_t int8_t +#endif + +#ifndef LOCK_INVALID_OWNER_ID +/*! \brief marker value to use for a lock_owner_id_t which does not refer to any valid owner + * \ingroup lock_core + */ +#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1) +#endif + +#ifndef lock_get_caller_owner_id +/*! \brief return the owner id for the caller + * \ingroup lock_core + * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id) + */ +#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num()) +#ifndef lock_is_owner_id_valid +#define lock_is_owner_id_valid(id) ((id)>=0) +#endif +#endif + +#ifndef lock_is_owner_id_valid +#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID) +#endif + +#ifndef lock_internal_spin_unlock_with_wait +/*! \brief Atomically unlock the lock's spin lock, and wait for a notification. + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify + * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify + * for the same lock, which completes after this call starts. + * + * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify + * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that; + * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then + * waits again if the calling thread should not proceed. + * + * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden + * (e.g. to actually block the RTOS task). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK` + * state when the spin lock was acquire + */ +#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe() +#endif + +#ifndef lock_internal_spin_unlock_with_notify +/*! \brief Atomically unlock the lock's spin lock, and send a notification + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a + * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait + * which started before this call completes. + * + * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait + * that has been called on the same lock instance, however it is free to wake up any of them, as they will check + * their condition and then re-wait if necessary/ + * + * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden + * (e.g. to actually un-block RTOS task(s)). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK + * state when the spin lock was acquire) + */ +#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev() +#endif + +#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout +/*! \brief Atomically unlock the lock's spin lock, and wait for a notification or a timeout + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify + * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify + * for the same lock, which completes after this call starts. + * + * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify + * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return + * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking + * primitive state and then waits again if the calling thread should not proceed. + * + * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout + * but may be overridden (e.g. to actually block the RTOS task with a timeout). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK + * state when the spin lock was acquire) + * \param until the \ref absolute_time_t value + * \return true if the timeout has been reached + */ +#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \ + spin_unlock((lock)->spin_lock, save); \ + best_effort_wfe_or_timeout(until); \ +}) +#endif + +#ifndef sync_internal_yield_until_before +/*! \brief yield to other processing until some time before the requested time + * \ingroup lock_core + * + * This method is provided for cases where the caller has no useful work to do + * until the specified time. + * + * By default this method does nothing, however it can be overridden (for example by an + * RTOS which is able to block the current task until the scheduler tick before + * the given time) + * + * \param until the \ref absolute_time_t value + */ +#define sync_internal_yield_until_before(until) ((void)0) +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h index 4b5d1759c1e..e834dc513af 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h @@ -19,20 +19,51 @@ extern "C" { * \brief Mutex API for non IRQ mutual exclusion between cores * * Mutexes are application level locks usually used protecting data structures that might be used by - * multiple cores. Unlike critical sections, the mutex protected code is not necessarily - * required/expected to complete quickly, as no other sytemwide locks are held on account of a locked mutex. + * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily + * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex. * - * Because they are not re-entrant on the same core, blocking on a mutex should never be done in an IRQ - * handler. It is valid to call \ref mutex_try_enter from within an IRQ handler, if the operation - * that would be conducted under lock can be skipped if the mutex is locked (at least by the same core). + * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just + * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context. + * + * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot + * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t + * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by + * the same caller, at the expense of some more overhead when acquiring and releasing. + * + * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler. + * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation + * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner). + * + * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define + * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions + * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK. * * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers */ +/*! \brief recursive mutex instance + * \ingroup mutex + */ +typedef struct __packed_aligned { + lock_core_t core; + lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned + uint8_t enter_count; //! ownership count +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + bool recursive; +#endif +} recursive_mutex_t; + +/*! \brief regular (non recursive) mutex instance + * \ingroup mutex + */ +#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY typedef struct __packed_aligned mutex { lock_core_t core; - int8_t owner; //! core number or -1 for unowned + lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned } mutex_t; +#else +typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0 +#endif /*! \brief Initialise a mutex structure * \ingroup mutex @@ -41,54 +72,145 @@ typedef struct __packed_aligned mutex { */ void mutex_init(mutex_t *mtx); +/*! \brief Initialise a recursive mutex structure + * \ingroup mutex + * + * A recursive mutex may be entered in a nested fashion by the same owner + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_init(recursive_mutex_t *mtx); + /*! \brief Take ownership of a mutex * \ingroup mutex * - * This function will block until the calling core can claim ownership of the mutex. - * On return the caller core owns the mutex + * This function will block until the caller can be granted ownership of the mutex. + * On return the caller owns the mutex * * \param mtx Pointer to mutex structure */ void mutex_enter_blocking(mutex_t *mtx); -/*! \brief Check to see if a mutex is available +/*! \brief Take ownership of a recursive mutex + * \ingroup mutex + * + * This function will block until the caller can be granted ownership of the mutex. + * On return the caller owns the mutex + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_enter_blocking(recursive_mutex_t *mtx); + +/*! \brief Attempt to take ownership of a mutex * \ingroup mutex * - * Will return true if the mutex is unowned, false otherwise + * If the mutex wasn't owned, this will claim the mutex for the caller and return true. + * Otherwise (if the mutex was already owned) this will return false and the + * caller will NOT own the mutex. * * \param mtx Pointer to mutex structure - * \param owner_out If mutex is owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex + * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex + * \return true if mutex now owned, false otherwise */ bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out); +/*! \brief Attempt to take ownership of a recursive mutex + * \ingroup mutex + * + * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true. + * Otherwise (if the mutex was already owned by another owner) this will return false and the + * caller will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero, + * it will be filled in with the owner id of the current owner of the mutex + * \return true if the recursive mutex (now) owned, false otherwise + */ +bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out); + /*! \brief Wait for mutex with timeout * \ingroup mutex * - * Wait for up to the specific time to take ownership of the mutex. If the calling - * core can take ownership of the mutex before the timeout expires, then true will be returned - * and the calling core will own the mutex, otherwise false will be returned and the calling - * core will *NOT* own the mutex. + * Wait for up to the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex. * * \param mtx Pointer to mutex structure * \param timeout_ms The timeout in milliseconds. - * \return true if mutex now owned, false if timeout occurred before mutex became available + * \return true if mutex now owned, false if timeout occurred before ownership could be granted */ bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms); +/*! \brief Wait for recursive mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the recursive mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param timeout_ms The timeout in milliseconds. + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms); + +/*! \brief Wait for mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to mutex structure + * \param timeout_us The timeout in microseconds. + * \return true if mutex now owned, false if timeout occurred before ownership could be granted + */ +bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us); + +/*! \brief Wait for recursive mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the recursive mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to mutex structure + * \param timeout_us The timeout in microseconds. + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us); + /*! \brief Wait for mutex until a specific time * \ingroup mutex * - * Wait until the specific time to take ownership of the mutex. If the calling - * core can take ownership of the mutex before the timeout expires, then true will be returned - * and the calling core will own the mutex, otherwise false will be returned and the calling - * core will *NOT* own the mutex. + * Wait until the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. * * \param mtx Pointer to mutex structure - * \param until The time after which to return if the core cannot take owner ship of the mutex - * \return true if mutex now owned, false if timeout occurred before mutex became available + * \param until The time after which to return if the caller cannot be granted ownership of the mutex + * \return true if mutex now owned, false if timeout occurred before ownership could be granted */ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); +/*! \brief Wait for mutex until a specific time + * \ingroup mutex + * + * Wait until the specific time to take ownership of the mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param until The time after which to return if the caller cannot be granted ownership of the mutex + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until); + /*! \brief Release ownership of a mutex * \ingroup mutex * @@ -96,13 +218,30 @@ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); */ void mutex_exit(mutex_t *mtx); -/*! \brief Test for mutex initialised state +/*! \brief Release ownership of a recursive mutex + * \ingroup mutex + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_exit(recursive_mutex_t *mtx); + +/*! \brief Test for mutex initialized state * \ingroup mutex * * \param mtx Pointer to mutex structure - * \return true if the mutex is initialised, false otherwise + * \return true if the mutex is initialized, false otherwise + */ +static inline bool mutex_is_initialized(mutex_t *mtx) { + return mtx->core.spin_lock != 0; +} + +/*! \brief Test for recursive mutex initialized state + * \ingroup mutex + * + * \param mtx Pointer to recursive mutex structure + * \return true if the recursive mutex is initialized, false otherwise */ -static inline bool mutex_is_initialzed(mutex_t *mtx) { +static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) { return mtx->core.spin_lock != 0; } @@ -129,6 +268,29 @@ static inline bool mutex_is_initialzed(mutex_t *mtx) { */ #define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name +/*! \brief Helper macro for static definition of recursive mutexes + * \ingroup mutex + * + * A recursive mutex defined as follows: + * + * ```c + * auto_init_recursive_mutex(my_recursive_mutex); + * ``` + * + * Is equivalent to doing + * + * ```c + * static recursive_mutex_t my_recursive_mutex; + * + * void my_init_function() { + * recursive_mutex_init(&my_recursive_mutex); + * } + * ``` + * + * But the initialization of the mutex is performed automatically during runtime initialization + */ +#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ } + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h index 19ac2925a36..6244e324628 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h @@ -90,11 +90,38 @@ void sem_acquire_blocking(semaphore_t *sem); * return false, otherwise it will return true. * * \param sem Pointer to semaphore structure - * \param timeout_ms Time to wait to acquire the semaphore, in ms. + * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds. * \return false if timeout reached, true if permit was acquired. */ bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms); +/*! \brief Acquire a permit from a semaphore, with timeout + * \ingroup sem + * + * This function will block and wait if no permits are available, until the + * defined timeout has been reached. If the timeout is reached the function will + * return false, otherwise it will return true. + * + * \param sem Pointer to semaphore structure + * \param timeout_us Time to wait to acquire the semaphore, in microseconds. + * \return false if timeout reached, true if permit was acquired. + */ +bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us); + +/*! \brief Wait to acquire a permit from a semaphore until a specific time + * \ingroup sem + * + * This function will block and wait if no permits are available, until the + * specified timeout time. If the timeout is reached the function will + * return false, otherwise it will return true. + * + * \param sem Pointer to semaphore structure + * \param until The time after which to return if the sem is not available. + * \return true if permit was acquired, false if the until time was reached before + * acquiring. + */ +bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c index cf53a05c635..1bc8df9d565 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/lock_core.c @@ -7,7 +7,7 @@ #include "pico/lock_core.h" void lock_init(lock_core_t *core, uint lock_num) { - assert(lock_num >= 0 && lock_num < NUM_SPIN_LOCKS); + valid_params_if(LOCK_CORE, lock_num < NUM_SPIN_LOCKS); core->spin_lock = spin_lock_instance(lock_num); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c index 531666fbea8..3ea81c75235 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/mutex.c @@ -7,40 +7,90 @@ #include "pico/mutex.h" #include "pico/time.h" -#if !PICO_NO_HARDWARE -static_assert(sizeof(mutex_t) == 8, ""); +void mutex_init(mutex_t *mtx) { + lock_init(&mtx->core, next_striped_spin_lock_num()); + mtx->owner = LOCK_INVALID_OWNER_ID; +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + mtx->recursive = false; #endif + __mem_fence_release(); +} -void mutex_init(mutex_t *mtx) { +void recursive_mutex_init(recursive_mutex_t *mtx) { lock_init(&mtx->core, next_striped_spin_lock_num()); - mtx->owner = -1; + mtx->owner = LOCK_INVALID_OWNER_ID; + mtx->enter_count = 0; +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + mtx->recursive = true; +#endif __mem_fence_release(); } void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) { - assert(mtx->core.spin_lock); - bool block = true; +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + if (mtx->recursive) { + recursive_mutex_enter_blocking(mtx); + return; + } +#endif + lock_owner_id_t caller = lock_get_caller_owner_id(); do { uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (mtx->owner < 0) { - mtx->owner = get_core_num(); - block = false; + if (!lock_is_owner_id_valid(mtx->owner)) { + mtx->owner = caller; + spin_unlock(mtx->core.spin_lock, save); + break; } - spin_unlock(mtx->core.spin_lock, save); - if (block) { - __wfe(); + lock_internal_spin_unlock_with_wait(&mtx->core, save); + } while (true); +} + +void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) { + lock_owner_id_t caller = lock_get_caller_owner_id(); + do { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) { + mtx->owner = caller; + uint __unused total = ++mtx->enter_count; + spin_unlock(mtx->core.spin_lock, save); + assert(total); // check for overflow + return; + } else { + lock_internal_spin_unlock_with_wait(&mtx->core, save); } - } while (block); + } while (true); } bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) { +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + if (mtx->recursive) { + return recursive_mutex_try_enter(mtx, owner_out); + } +#endif + bool entered; + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (!lock_is_owner_id_valid(mtx->owner)) { + mtx->owner = lock_get_caller_owner_id(); + entered = true; + } else { + if (owner_out) *owner_out = (uint32_t) mtx->owner; + entered = false; + } + spin_unlock(mtx->core.spin_lock, save); + return entered; +} + +bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) { bool entered; + lock_owner_id_t caller = lock_get_caller_owner_id(); uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (mtx->owner < 0) { - mtx->owner = get_core_num(); + if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) { + mtx->owner = caller; + uint __unused total = ++mtx->enter_count; + assert(total); // check for overflow entered = true; } else { - if (owner_out) *owner_out = mtx->owner; + if (owner_out) *owner_out = (uint32_t) mtx->owner; entered = false; } spin_unlock(mtx->core.spin_lock, save); @@ -51,29 +101,84 @@ bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms)); } +bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) { + return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms)); +} + +bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) { + return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us)); +} + +bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) { + return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us)); +} + bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) { +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + if (mtx->recursive) { + return recursive_mutex_enter_block_until(mtx, until); + } +#endif assert(mtx->core.spin_lock); - bool block = true; + lock_owner_id_t caller = lock_get_caller_owner_id(); do { uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - if (mtx->owner < 0) { - mtx->owner = get_core_num(); - block = false; + if (!lock_is_owner_id_valid(mtx->owner)) { + mtx->owner = caller; + spin_unlock(mtx->core.spin_lock, save); + return true; + } else { + if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) { + // timed out + return false; + } + // not timed out; spin lock already unlocked, so loop again } - spin_unlock(mtx->core.spin_lock, save); - if (block) { - if (best_effort_wfe_or_timeout(until)) { + } while (true); +} + +bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) { + assert(mtx->core.spin_lock); + lock_owner_id_t caller = lock_get_caller_owner_id(); + do { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) { + mtx->owner = caller; + uint __unused total = ++mtx->enter_count; + spin_unlock(mtx->core.spin_lock, save); + assert(total); // check for overflow + return true; + } else { + if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) { + // timed out return false; } + // not timed out; spin lock already unlocked, so loop again } - } while (block); - return true; + } while (true); } void __time_critical_func(mutex_exit)(mutex_t *mtx) { +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + if (mtx->recursive) { + recursive_mutex_exit(mtx); + return; + } +#endif uint32_t save = spin_lock_blocking(mtx->core.spin_lock); - assert(mtx->owner >= 0); - mtx->owner = -1; - __sev(); - spin_unlock(mtx->core.spin_lock, save); + assert(lock_is_owner_id_valid(mtx->owner)); + mtx->owner = LOCK_INVALID_OWNER_ID; + lock_internal_spin_unlock_with_notify(&mtx->core, save); } + +void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) { + uint32_t save = spin_lock_blocking(mtx->core.spin_lock); + assert(lock_is_owner_id_valid(mtx->owner)); + assert(mtx->enter_count); + if (!--mtx->enter_count) { + mtx->owner = LOCK_INVALID_OWNER_ID; + lock_internal_spin_unlock_with_notify(&mtx->core, save); + } else { + spin_unlock(mtx->core.spin_lock, save); + } +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c index 4ed7285450b..06b4946ef9a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/sem.c @@ -19,64 +19,61 @@ int __time_critical_func(sem_available)(semaphore_t *sem) { } void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) { - bool block = true; do { uint32_t save = spin_lock_blocking(sem->core.spin_lock); if (sem->permits > 0) { sem->permits--; - __sev(); - block = false; + lock_internal_spin_unlock_with_notify(&sem->core, save); + break; } - spin_unlock(sem->core.spin_lock, save); - if (block) { - __wfe(); - } - } while (block); + lock_internal_spin_unlock_with_wait(&sem->core, save); + } while (true); } bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) { - bool block = true; - absolute_time_t target = nil_time; + return sem_acquire_block_until(sem, make_timeout_time_ms(timeout_ms)); +} + +bool __time_critical_func(sem_acquire_timeout_us)(semaphore_t *sem, uint32_t timeout_us) { + return sem_acquire_block_until(sem, make_timeout_time_us(timeout_us)); +} + +bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_time_t until) { do { uint32_t save = spin_lock_blocking(sem->core.spin_lock); if (sem->permits > 0) { sem->permits--; - __sev(); - block = false; + lock_internal_spin_unlock_with_notify(&sem->core, save); + return true; } - spin_unlock(sem->core.spin_lock, save); - if (block) { - if (is_nil_time(target)) { - target = make_timeout_time_ms(timeout_ms); - } - if (best_effort_wfe_or_timeout(target)) { - return false; - } + if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) { + return false; } - } while (block); - return true; + } while (true); } // todo this should really have a blocking variant for when permits are maxed out bool __time_critical_func(sem_release)(semaphore_t *sem) { - bool rc; uint32_t save = spin_lock_blocking(sem->core.spin_lock); int32_t count = sem->permits; if (count < sem->max_permits) { - sem->permits = count + 1; - __sev(); - rc = true; + sem->permits = (int16_t)(count + 1); + lock_internal_spin_unlock_with_notify(&sem->core, save); + return true; } else { - rc = false; + spin_unlock(sem->core.spin_lock, save); + return false; } - spin_unlock(sem->core.spin_lock, save); - return rc; } void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) { assert(permits >= 0 && permits <= sem->max_permits); uint32_t save = spin_lock_blocking(sem->core.spin_lock); - if (permits > sem->permits) __sev(); - sem->permits = permits; - spin_unlock(sem->core.spin_lock, save); + if (permits > sem->permits) { + sem->permits = permits; + lock_internal_spin_unlock_with_notify(&sem->core, save); + } else { + sem->permits = permits; + spin_unlock(sem->core.spin_lock, save); + } } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt index fe388558513..9e497a73f40 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/CMakeLists.txt @@ -7,7 +7,7 @@ if (NOT TARGET pico_time_headers) endif() if (NOT TARGET pico_time) - add_library(pico_time INTERFACE) + pico_add_impl_library(pico_time) target_sources(pico_time INTERFACE ${CMAKE_CURRENT_LIST_DIR}/time.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h index ae0a84f7c5d..c00b7a82c3a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h @@ -58,7 +58,7 @@ extern "C" { * \sa sleep_until() * \sa time_us_64() */ -static inline absolute_time_t get_absolute_time() { +static inline absolute_time_t get_absolute_time(void) { absolute_time_t t; update_us_since_boot(&t, time_us_64()); return t; @@ -77,7 +77,7 @@ static inline uint32_t us_to_ms(uint64_t us) { * \brief Convert a timestamp into a number of milliseconds since boot. * \param t an absolute_time_t value to convert * \return the number of microseconds since boot represented by t - * \sa to_us_since_boot + * \sa to_us_since_boot() */ static inline uint32_t to_ms_since_boot(absolute_time_t t) { uint64_t us = to_us_since_boot(t); @@ -152,10 +152,12 @@ static inline absolute_time_t make_timeout_time_ms(uint32_t ms) { * in case of overflow) */ static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) { - return to_us_since_boot(to) - to_us_since_boot(from); + return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from)); } -/*! \brief The timestamp representing the end of time; no timestamp is after this +/*! \brief The timestamp representing the end of time; this is actually not the maximum possible + * timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time + * arithmetic. This is still over 7 million years, so should be sufficient. * \ingroup timestamp */ extern const absolute_time_t at_the_end_of_time; @@ -169,7 +171,7 @@ extern const absolute_time_t nil_time; * \ingroup timestamp * \param t the timestamp * \return true if the timestamp is nil - * \sa nil_time() + * \sa nil_time */ static inline bool is_nil_time(absolute_time_t t) { return !to_us_since_boot(t); @@ -228,7 +230,7 @@ void sleep_ms(uint32_t ms); /*! \brief Helper method for blocking on a timeout * \ingroup sleep * - * This method will return in response to a an event (as per __wfe) or + * This method will return in response to an event (as per __wfe) or * when the target time is reached, or at any point before. * * This method can be used to implement a lower power polling loop waiting on @@ -350,7 +352,7 @@ typedef struct alarm_pool alarm_pool_t; * \brief Create the default alarm pool (if not already created or disabled) * \ingroup alarm */ -void alarm_pool_init_default(); +void alarm_pool_init_default(void); #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED /*! @@ -360,7 +362,7 @@ void alarm_pool_init_default(); * \ingroup alarm * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM */ -alarm_pool_t *alarm_pool_get_default(); +alarm_pool_t *alarm_pool_get_default(void); #endif /** @@ -414,9 +416,12 @@ void alarm_pool_destroy(alarm_pool_t *pool); * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call - * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead + * @return >0 the alarm id for an active (at the time of return) alarm + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past); @@ -436,9 +441,12 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala * @param us the delay (from now) in microseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -460,9 +468,12 @@ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t * @param ms the delay (from now) in milliseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -494,9 +505,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id); * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -517,9 +531,12 @@ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t cal * @param us the delay (from now) in microseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -540,9 +557,12 @@ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, * @param ms the delay (from now) in milliseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c index e004c00d81e..3a585f6520b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/time.c @@ -5,16 +5,16 @@ */ #include +#include #include #include #include "pico.h" #include "pico/time.h" #include "pico/util/pheap.h" -#include "hardware/sync.h" -#include "hardware/gpio.h" +#include "pico/sync.h" const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0); -const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, ULONG_MAX); +const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX); typedef struct alarm_pool_entry { absolute_time_t target; @@ -34,26 +34,26 @@ typedef struct alarm_pool { } alarm_pool_t; #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -static alarm_pool_t *default_alarm_pool; +// To avoid bringing in calloc, we statically allocate the arrays and the heap +PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); +static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS]; +static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS]; +static lock_core_t sleep_notifier; + +static alarm_pool_t default_alarm_pool = { + .heap = &default_alarm_pool_heap, + .entries = default_alarm_pool_entries, + .entry_ids_high = default_alarm_pool_entry_ids_high, +}; + +static inline bool default_alarm_pool_initialized(void) { + return default_alarm_pool.lock != NULL; +} #endif + static alarm_pool_t *pools[NUM_TIMERS]; +static void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num); -void alarm_pool_init_default() { -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED - // allow multiple calls for ease of use from host tests - if (!default_alarm_pool) { - default_alarm_pool = alarm_pool_create(PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, - PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); - } -#endif -} - -#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -alarm_pool_t *alarm_pool_get_default() { - assert(default_alarm_pool); - return default_alarm_pool; -} -#endif static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) { assert(id && id <= pool->heap->max_nodes); @@ -71,14 +71,34 @@ bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_ } static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) { - return ((uint)id_high << 8u * sizeof(id)) | id; + return (alarm_id_t)(((uint)id_high << 8u * sizeof(id)) | id); } -static alarm_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, - void *user_data, alarm_id_t reuse_id, bool create_if_past, bool *missed) { - alarm_id_t id; +void alarm_pool_init_default() { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + // allow multiple calls for ease of use from host tests + if (!default_alarm_pool_initialized()) { + ph_post_alloc_init(default_alarm_pool.heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, + timer_pool_entry_comparator, &default_alarm_pool); + alarm_pool_post_alloc_init(&default_alarm_pool, + PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM); + } + lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER); +#endif +} + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +alarm_pool_t *alarm_pool_get_default() { + assert(default_alarm_pool_initialized()); + return &default_alarm_pool; +} +#endif + +static pheap_node_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, + void *user_data, pheap_node_id_t reuse_id, bool create_if_past, bool *missed) { + pheap_node_id_t id; if (reuse_id) { - assert(!ph_contains(pool->heap, reuse_id)); + assert(!ph_contains_node(pool->heap, reuse_id)); id = reuse_id; } else { id = ph_new_node(pool->heap); @@ -88,10 +108,10 @@ static alarm_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, entry->target = time; entry->callback = callback; entry->user_data = user_data; - if (id == ph_insert(pool->heap, id)) { + if (id == ph_insert_node(pool->heap, id)) { bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time); if (is_missed && !create_if_past) { - ph_delete(pool->heap, id); + ph_remove_and_free_node(pool->heap, id); } if (missed) *missed = is_missed; } @@ -115,8 +135,8 @@ static void alarm_pool_alarm_callback(uint alarm_num) { if (next_id) { alarm_pool_entry_t *entry = get_entry(pool, next_id); if (absolute_time_diff_us(now, entry->target) <= 0) { - // we reserve the id in case we need to re-add the timer - pheap_node_id_t __unused removed_id = ph_remove_head_reserve(pool->heap, true); + // we don't free the id in case we need to re-add the timer + pheap_node_id_t __unused removed_id = ph_remove_head(pool->heap, false); assert(removed_id == next_id); // will be true under lock target = entry->target; callback = entry->callback; @@ -137,14 +157,14 @@ static void alarm_pool_alarm_callback(uint alarm_num) { // todo think more about whether we want to keep calling if (repeat < 0 && pool->alarm_in_progress) { assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); - add_alarm_under_lock(pool, delayed_by_us(target, -repeat), callback, user_data, next_id, true, NULL); + add_alarm_under_lock(pool, delayed_by_us(target, (uint64_t)-repeat), callback, user_data, next_id, true, NULL); } else if (repeat > 0 && pool->alarm_in_progress) { assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); - add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), repeat), callback, user_data, next_id, + add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), (uint64_t)repeat), callback, user_data, next_id, true, NULL); } else { // need to return the id to the heap - ph_add_to_free_list(pool->heap, next_id); + ph_free_node(pool->heap, next_id); (*get_entry_id_high(pool, next_id))++; // we bump it for next use of id } pool->alarm_in_progress = 0; @@ -156,20 +176,30 @@ static void alarm_pool_alarm_callback(uint alarm_num) { // note the timer is create with IRQs on this core alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) { + alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); + pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool); + pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t)); + pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t)); + alarm_pool_post_alloc_init(pool, hardware_alarm_num); + return pool; +} + +void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) { hardware_alarm_claim(hardware_alarm_num); hardware_alarm_cancel(hardware_alarm_num); hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback); - alarm_pool_t *pool = (alarm_pool_t *)malloc(sizeof(alarm_pool_t)); pool->lock = spin_lock_instance(next_striped_spin_lock_num()); - pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool); - pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t)); - pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t)); - pool->hardware_alarm_num = hardware_alarm_num; + pool->hardware_alarm_num = (uint8_t) hardware_alarm_num; pools[hardware_alarm_num] = pool; - return pool; } void alarm_pool_destroy(alarm_pool_t *pool) { +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED + if (pool == &default_alarm_pool) { + assert(false); // attempt to delete default alarm pool + return; + } +#endif assert(pools[pool->hardware_alarm_num] == pool); pools[pool->hardware_alarm_num] = NULL; // todo clear out timers @@ -185,31 +215,43 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala void *user_data, bool fire_if_past) { bool missed = false; - uint public_id; + alarm_id_t public_id; do { uint8_t id_high = 0; uint32_t save = spin_lock_blocking(pool->lock); + pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed); if (id) id_high = *get_entry_id_high(pool, id); spin_unlock(pool->lock, save); if (!id) { + // no space in pheap to allocate an alarm return -1; } + // note that if missed was true, then the id was never added to the pheap (because we + // passed false for create_if_past arg above) public_id = missed ? 0 : make_public_id(id_high, id); if (missed && fire_if_past) { + // ... so if fire_if_past == true we call the callback int64_t repeat = callback(public_id, user_data); + // if not repeated we have no id to return so set public_id to 0, + // otherwise we need to repeat, but will assign a new id next time + // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls if (!repeat) { public_id = 0; break; } else if (repeat < 0) { - time = delayed_by_us(time, -repeat); + time = delayed_by_us(time, (uint64_t)-repeat); } else { - time = delayed_by_us(get_absolute_time(), repeat); + time = delayed_by_us(get_absolute_time(), (uint64_t)repeat); } } else { + // either: + // a) missed == false && public_id is > 0 + // b) missed == true && fire_if_past == false && public_id = 0 + // but we are done in either case break; } } while (true); @@ -220,12 +262,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) { bool rc = false; uint32_t save = spin_lock_blocking(pool->lock); pheap_node_id_t id = (pheap_node_id_t) alarm_id; - if (ph_contains(pool->heap, id)) { + if (ph_contains_node(pool->heap, id)) { assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress // check we have the right high value uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t)); if (id_high == *get_entry_id_high(pool, id)) { - rc = ph_delete(pool->heap, id); + rc = ph_remove_and_free_node(pool->heap, id); // note we don't bother to remove the actual hardware alarm timeout... // it will either do callbacks or not depending on other alarms, and reset the next timeout itself assert(rc); @@ -249,12 +291,13 @@ static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) { #if PICO_ON_DEVICE printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id)); #else - printf("%ld", to_us_since_boot(get_entry(pool, id)->target)); + printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target)); #endif } -static int64_t repeating_timer_callback(alarm_id_t id, void *user_data) { +static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) { repeating_timer_t *rt = (repeating_timer_t *)user_data; + assert(rt->alarm_id == id); if (rt->callback(rt)) { return rt->delay_us; } else { @@ -269,8 +312,11 @@ bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, rep out->callback = callback; out->delay_us = delay_us; out->user_data = user_data; - out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us(delay_us >= 0 ? delay_us : -delay_us), repeating_timer_callback, out, true); - return out->alarm_id > 0; + out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)), + repeating_timer_callback, out, true); + // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true) + // and then the callback removed itself. + return out->alarm_id >= 0; } bool cancel_repeating_timer(repeating_timer_t *timer) { @@ -289,13 +335,19 @@ void alarm_pool_dump(alarm_pool_t *pool) { } #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -static int64_t sev_callback(alarm_id_t id, void *user_data) { - __sev(); +static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) { + uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock); + lock_internal_spin_unlock_with_notify(&sleep_notifier, save); return 0; } #endif void sleep_until(absolute_time_t t) { +#if PICO_ON_DEVICE && !defined(NDEBUG) + if (__get_current_exception()) { + panic("Attempted to sleep inside of an exception handler; use busy_wait if you must"); + } +#endif #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED uint64_t t_us = to_us_since_boot(t); uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US; @@ -304,13 +356,17 @@ void sleep_until(absolute_time_t t) { absolute_time_t t_before; update_us_since_boot(&t_before, t_before_us); if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) { - if (add_alarm_at(t_before, sev_callback, NULL, false) >= 0) { + if (add_alarm_at(t_before, sleep_until_callback, NULL, false) >= 0) { // able to add alarm for just before the time while (!time_reached(t_before)) { - __wfe(); + uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock); + lock_internal_spin_unlock_with_wait(&sleep_notifier, save); } } } +#else + // hook in case we're in RTOS; note we assume using the alarm pool is better always if available. + sync_internal_yield_until_before(t); #endif // now wait until the exact time busy_wait_until(t); @@ -320,13 +376,17 @@ void sleep_us(uint64_t us) { #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED sleep_until(make_timeout_time_us(us)); #else - if (us >> 32u) { - busy_wait_until(make_timeout_time_us(us)); + if (us < PICO_TIME_SLEEP_OVERHEAD_ADJUST_US) { + busy_wait_us(us); } else { - busy_wait_us_32(us); + // hook in case we're in RTOS; note we assume using the alarm pool is better always if available. + absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US); + sync_internal_yield_until_before(t); + + // then wait the rest of thw way + busy_wait_until(t); } #endif - } void sleep_ms(uint32_t ms) { @@ -336,7 +396,7 @@ void sleep_ms(uint32_t ms) { bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) { #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED alarm_id_t id; - id = add_alarm_at(timeout_timestamp, sev_callback, NULL, false); + id = add_alarm_at(timeout_timestamp, sleep_until_callback, NULL, false); if (id <= 0) { tight_loop_contents(); return time_reached(timeout_timestamp); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/CMakeLists.txt new file mode 100644 index 00000000000..369375c39f0 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(pico_usb_reset_interface_headers INTERFACE) +target_include_directories(pico_usb_reset_interface_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h new file mode 100644 index 00000000000..153acf8101c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_USB_RESET_INTERFACE_H +#define _PICO_USB_RESET_INTERFACE_H + +/** \file usb_reset_interface.h + * \defgroup pico_usb_reset_interface pico_usb_reset_interface + * + * Definition for the reset interface that may be exposed by the pico_stdio_usb library + */ + +// VENDOR sub-class for the reset interface +#define RESET_INTERFACE_SUBCLASS 0x00 +// VENDOR protocol for the reset interface +#define RESET_INTERFACE_PROTOCOL 0x01 + +// CONTROL requests: + +// reset to BOOTSEL +#define RESET_REQUEST_BOOTSEL 0x01 +// regular flash boot +#define RESET_REQUEST_FLASH 0x02 + +#endif \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt index a829c14e94c..3eb699845c0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/CMakeLists.txt @@ -5,7 +5,7 @@ if (NOT TARGET pico_util_headers) endif() if (NOT TARGET pico_util) - add_library(pico_util INTERFACE) + pico_add_impl_library(pico_util) target_sources(pico_util INTERFACE ${CMAKE_CURRENT_LIST_DIR}/datetime.c ${CMAKE_CURRENT_LIST_DIR}/pheap.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h index 61b5c7e9230..bb328351a29 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h @@ -9,6 +9,10 @@ #include "pico.h" +#ifdef __cplusplus +extern "C" { +#endif + /** \file datetime.h * \defgroup util_datetime datetime * \brief Date/Time formatting @@ -24,4 +28,7 @@ */ void datetime_to_str(char *buf, uint buf_size, const datetime_t *t); +#ifdef __cplusplus +} +#endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h index 59617e7def8..25351b44fae 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h @@ -29,7 +29,7 @@ extern "C" { * * NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore * if used concurrently, the caller needs to protect around their use of the returned id. - * for example, ph_remove_head returns the id of an element that is no longer in the heap. + * for example, ph_remove_and_free_head returns the id of an element that is no longer in the heap. * * The user can still use this to look at the data in their companion array, however obviously further operations * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations @@ -53,7 +53,11 @@ typedef struct pheap_node { pheap_node_id_t child, sibling, parent; } pheap_node_t; -// return true if a < b in natural order +/** + * A user comparator function for nodes in a pairing heap. + * + * \return true if a < b in natural order. Note this relative ordering must be stable from call to call. + */ typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b); typedef struct pheap { @@ -67,17 +71,42 @@ typedef struct pheap { pheap_node_id_t free_tail_id; } pheap_t; +/** + * Create a pairing heap, which effectively maintains an efficient sorted ordering + * of nodes. The heap itself stores no user per-node state, it is expected + * that the user maintains a companion array. A comparator function must + * be provided so that the heap implementation can determine the relative ordering of nodes + * + * \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by + * PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes + * in a single byte). + * \param comparator the node comparison function + * \param user_data a user data pointer associated with the heap that is provided in callbacks + * \return a newly allocated and initialized heap + */ pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data); +/** + * Removes all nodes from the pairing heap + * \param heap the heap + */ void ph_clear(pheap_t *heap); +/** + * De-allocates a pairing heap + * + * Note this method must *ONLY* be called on heaps created by ph_create() + * \param heap the heap + */ void ph_destroy(pheap_t *heap); +// internal method static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) { assert(id && id <= heap->max_nodes); return heap->nodes + id - 1; } +// internal method static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) { pheap_node_t *n = ph_get_node(heap, parent_id); assert(parent_id); @@ -93,6 +122,7 @@ static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_no } } +// internal method static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) { if (!a) return b; if (!b) return a; @@ -105,17 +135,34 @@ static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_no } } +/** + * Allocate a new node from the unused space in the heap + * + * \param heap the heap + * \return an identifier for the node, or 0 if the heap is full + */ static inline pheap_node_id_t ph_new_node(pheap_t *heap) { if (!heap->free_head_id) return 0; pheap_node_id_t id = heap->free_head_id; - heap->free_head_id = ph_get_node(heap, id)->sibling; + pheap_node_t *hn = ph_get_node(heap, id); + heap->free_head_id = hn->sibling; if (!heap->free_head_id) heap->free_tail_id = 0; + hn->child = hn->sibling = hn->parent = 0; return id; } -// note this will callback the comparator for the node -// returns the (new) root of the heap -static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) { +/** + * Inserts a node into the heap. + * + * This method inserts a node (previously allocated by ph_new_node()) + * into the heap, determining the correct order by calling + * the heap's comparator + * + * \param heap the heap + * \param id the id of the node to insert + * \return the id of the new head of the pairing heap (i.e. node that compares first) + */ +static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) { assert(id); pheap_node_t *hn = ph_get_node(heap, id); hn->child = hn->sibling = hn->parent = 0; @@ -123,31 +170,120 @@ static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) { return heap->root_id; } +/** + * Returns the head node in the heap, i.e. the node + * which compares first, but without removing it from the heap. + * + * \param heap the heap + * \return the current head node id + */ static inline pheap_node_id_t ph_peek_head(pheap_t *heap) { return heap->root_id; } -pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve); +/** + * Remove the head node from the pairing heap. This head node is + * the node which compares first in the logical ordering provided + * by the comparator. + * + * Note that in the case of free == true, the returned id is no longer + * allocated and may be re-used by future node allocations, so the caller + * should retrieve any per node state from the companion array before modifying + * the heap further. + * + * @param heap the heap + * @param free true if the id is also to be freed; false if not - useful if the caller + * may wish to re-insert an item with the same id) + * @return the old head node id. + */ +pheap_node_id_t ph_remove_head(pheap_t *heap, bool free); -static inline pheap_node_id_t ph_remove_head(pheap_t *heap) { - return ph_remove_head_reserve(heap, false); +/** + * Remove the head node from the pairing heap. This head node is + * the node which compares first in the logical ordering provided + * by the comparator. + * + * Note that the returned id will be freed, and thus may be re-used by future node allocations, + * so the caller should retrieve any per node state from the companion array before modifying + * the heap further. + * + * @param heap the heap + * @return the old head node id. + */ +static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) { + return ph_remove_head(heap, true); } -static inline bool ph_contains(pheap_t *heap, pheap_node_id_t id) { +/** + * Remove and free an arbitrary node from the pairing heap. This is a more + * costly operation than removing the head via ph_remove_and_free_head() + * + * @param heap the heap + * @param id the id of the node to free + * @return true if the the node was in the heap, false otherwise + */ +bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id); + +/** + * Determine if the heap contains a given node. Note containment refers + * to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node()) + * + * @param heap the heap + * @param id the id of the node + * @return true if the heap contains a node with the given id, false otherwise. + */ +static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) { return id == heap->root_id || ph_get_node(heap, id)->parent; } -bool ph_delete(pheap_t *heap, pheap_node_id_t id); -static inline void ph_add_to_free_list(pheap_t *heap, pheap_node_id_t id) { - assert(id && !ph_contains(heap, id)); +/** + * Free a node that is not currently in the heap, but has been allocated + * + * @param heap the heap + * @param id the id of the node + */ +static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) { + assert(id && !ph_contains_node(heap, id)); if (heap->free_tail_id) { ph_get_node(heap, heap->free_tail_id)->sibling = id; } heap->free_tail_id = id; } -void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data); +/** + * Print a representation of the heap for debugging + * + * @param heap the heap + * @param dump_key a method to print a node value + * @param user_data the user data to pass to the dump_key method + */ +void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data); + +/** + * Initialize a statically allocated heap (ph_create() using the C heap). + * The heap member `nodes` must be allocated of size max_nodes. + * + * @param heap the heap + * @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array) + * @param comparator the comparator for the heap + * @param user_data the user data for the heap. + */ +void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data); + +/** + * Define a statically allocated pairing heap. This must be initialized + * by ph_post_alloc_init + */ +#define PHEAP_DEFINE_STATIC(name, _max_nodes) \ + static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \ + static pheap_node_t name ## _nodes[_max_nodes]; \ + static pheap_t name = { \ + .nodes = name ## _nodes, \ + .max_nodes = _max_nodes \ + }; + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h index d65548eaa72..097578a6169 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h @@ -10,6 +10,11 @@ #include "pico.h" #include "hardware/sync.h" +// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue +#ifndef PICO_QUEUE_MAX_LEVEL +#define PICO_QUEUE_MAX_LEVEL 0 +#endif + /** \file queue.h * \defgroup queue queue * Multi-core and IRQ safe queue implementation. @@ -18,13 +23,22 @@ * \ingroup pico_util */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "pico/lock_core.h" + typedef struct { - spin_lock_t *lock; + lock_core_t core; uint8_t *data; uint16_t wptr; uint16_t rptr; uint16_t element_size; uint16_t element_count; +#if PICO_QUEUE_MAX_LEVEL + uint16_t max_level; +#endif } queue_t; /*! \brief Initialise a queue with a specific spinlock for concurrency protection @@ -69,9 +83,9 @@ void queue_free(queue_t *q); static inline uint queue_get_level_unsafe(queue_t *q) { int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr; if (rc < 0) { - rc += + q->element_count + 1; + rc += q->element_count + 1; } - return rc; + return (uint)rc; } /*! \brief Check of level of the specified queue. @@ -81,12 +95,38 @@ static inline uint queue_get_level_unsafe(queue_t *q) { * \return Number of entries in the queue */ static inline uint queue_get_level(queue_t *q) { - uint32_t save = spin_lock_blocking(q->lock); + uint32_t save = spin_lock_blocking(q->core.spin_lock); uint level = queue_get_level_unsafe(q); - spin_unlock(q->lock, save); + spin_unlock(q->core.spin_lock, save); return level; } +/*! \brief Returns the highest level reached by the specified queue since it was created + * or since the max level was reset + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return Maximum level of the queue + */ +#if PICO_QUEUE_MAX_LEVEL +static inline uint queue_get_max_level(queue_t *q) { + return q->max_level; +} +#endif + +/*! \brief Reset the highest level reached of the specified queue. + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + */ +#if PICO_QUEUE_MAX_LEVEL +static inline void queue_reset_max_level(queue_t *q) { + uint32_t save = spin_lock_blocking(q->core.spin_lock); + q->max_level = queue_get_level_unsafe(q); + spin_unlock(q->core.spin_lock, save); +} +#endif + /*! \brief Check if queue is empty * \ingroup queue * @@ -123,7 +163,7 @@ static inline bool queue_is_full(queue_t *q) { * If the queue is full this function will return immediately with false, otherwise * the data is copied into a new value added to the queue, and this function will return true. */ -bool queue_try_add(queue_t *q, void *data); +bool queue_try_add(queue_t *q, const void *data); /*! \brief Non-blocking removal of entry from the queue if non empty * \ingroup queue @@ -159,7 +199,7 @@ bool queue_try_peek(queue_t *q, void *data); * * If the queue is full this function will block, until a removal happens on the queue */ -void queue_add_blocking(queue_t *q, void *data); +void queue_add_blocking(queue_t *q, const void *data); /*! \brief Blocking remove entry from queue * \ingroup queue @@ -181,4 +221,7 @@ void queue_remove_blocking(queue_t *q, void *data); */ void queue_peek_blocking(queue_t *q, void *data); +#ifdef __cplusplus +} +#endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c index 8e9c68614c3..fc8043552e2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/pheap.c @@ -9,22 +9,27 @@ #include "pico/util/pheap.h" pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) { - invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << sizeof(pheap_node_id_t))); + invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t)))); pheap_t *heap = calloc(1, sizeof(pheap_t)); - heap->max_nodes = max_nodes; - heap->comparator = comparator; heap->nodes = calloc(max_nodes, sizeof(pheap_node_t)); + ph_post_alloc_init(heap, max_nodes, comparator, user_data); + return heap; +} + +void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data) { + invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t)))); + heap->max_nodes = (pheap_node_id_t) max_nodes; + heap->comparator = comparator; heap->user_data = user_data; ph_clear(heap); - return heap; } void ph_clear(pheap_t *heap) { heap->root_id = 0; heap->free_head_id = 1; heap->free_tail_id = heap->max_nodes; - for(uint i = 1; i < heap->max_nodes; i++) { - ph_get_node(heap, i)->sibling = i + 1; + for(pheap_node_id_t i = 1; i < heap->max_nodes; i++) { + ph_get_node(heap, i)->sibling = (pheap_node_id_t)(i + 1); } ph_get_node(heap, heap->max_nodes)->sibling = 0; } @@ -47,13 +52,13 @@ pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) { } } -static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool reserve) { +static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool free) { assert(root_id); // printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling); assert(!ph_get_node(heap, root_id)->sibling); assert(!ph_get_node(heap, root_id)->parent); pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child); - if (!reserve) { + if (free) { if (heap->free_tail_id) { ph_get_node(heap, heap->free_tail_id)->sibling = root_id; } @@ -64,18 +69,17 @@ static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id return new_root_id; } -pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve) { +pheap_node_id_t ph_remove_head(pheap_t *heap, bool free) { pheap_node_id_t old_root_id = ph_peek_head(heap); - heap->root_id = ph_remove_any_head(heap, old_root_id, reserve); + heap->root_id = ph_remove_any_head(heap, old_root_id, free); return old_root_id; } -#include -bool ph_delete(pheap_t *heap, pheap_node_id_t id) { +bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id) { // 1) trivial cases if (!id) return false; if (id == heap->root_id) { - ph_remove_head(heap); + ph_remove_and_free_head(heap); return true; } // 2) unlink the node from the tree @@ -101,7 +105,7 @@ bool ph_delete(pheap_t *heap, pheap_node_id_t id) { node->sibling = node->parent = 0; // ph_dump(heap, NULL, NULL); // 3) remove it from the head of its own subtree - pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, false); + pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, true); assert(new_sub_tree != heap->root_id); heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree); return true; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c index 785e7f01ade..a5c8e181f7d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/queue.c @@ -9,10 +9,10 @@ #include "pico/util/queue.h" void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) { - q->lock = spin_lock_instance(spinlock_num); + lock_init(&q->core, spinlock_num); q->data = (uint8_t *)calloc(element_count + 1, element_size); - q->element_count = element_count; - q->element_size = element_size; + q->element_count = (uint16_t)element_count; + q->element_size = (uint16_t)element_size; q->wptr = 0; q->rptr = 0; } @@ -30,69 +30,90 @@ static inline uint16_t inc_index(queue_t *q, uint16_t index) { if (++index > q->element_count) { // > because we have element_count + 1 elements index = 0; } + +#if PICO_QUEUE_MAX_LEVEL + uint16_t level = queue_get_level_unsafe(q); + if (level > q->max_level) { + q->max_level = level; + } +#endif + return index; } -bool queue_try_add(queue_t *q, void *data) { - bool success = false; - uint32_t flags = spin_lock_blocking(q->lock); - if (queue_get_level_unsafe(q) != q->element_count) { - memcpy(element_ptr(q, q->wptr), data, q->element_size); - q->wptr = inc_index(q, q->wptr); - success = true; - } - spin_unlock(q->lock, flags); - if (success) __sev(); - return success; +static bool queue_add_internal(queue_t *q, const void *data, bool block) { + do { + uint32_t save = spin_lock_blocking(q->core.spin_lock); + if (queue_get_level_unsafe(q) != q->element_count) { + memcpy(element_ptr(q, q->wptr), data, q->element_size); + q->wptr = inc_index(q, q->wptr); + lock_internal_spin_unlock_with_notify(&q->core, save); + return true; + } + if (block) { + lock_internal_spin_unlock_with_wait(&q->core, save); + } else { + spin_unlock(q->core.spin_lock, save); + return false; + } + } while (true); +} + +static bool queue_remove_internal(queue_t *q, void *data, bool block) { + do { + uint32_t save = spin_lock_blocking(q->core.spin_lock); + if (queue_get_level_unsafe(q) != 0) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + q->rptr = inc_index(q, q->rptr); + lock_internal_spin_unlock_with_notify(&q->core, save); + return true; + } + if (block) { + lock_internal_spin_unlock_with_wait(&q->core, save); + } else { + spin_unlock(q->core.spin_lock, save); + return false; + } + } while (true); +} + +static bool queue_peek_internal(queue_t *q, void *data, bool block) { + do { + uint32_t save = spin_lock_blocking(q->core.spin_lock); + if (queue_get_level_unsafe(q) != 0) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + lock_internal_spin_unlock_with_notify(&q->core, save); + return true; + } + if (block) { + lock_internal_spin_unlock_with_wait(&q->core, save); + } else { + spin_unlock(q->core.spin_lock, save); + return false; + } + } while (true); +} + +bool queue_try_add(queue_t *q, const void *data) { + return queue_add_internal(q, data, false); } bool queue_try_remove(queue_t *q, void *data) { - bool success = false; - uint32_t flags = spin_lock_blocking(q->lock); - if (queue_get_level_unsafe(q) != 0) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); - q->rptr = inc_index(q, q->rptr); - success = true; - } - spin_unlock(q->lock, flags); - if (success) __sev(); - return success; + return queue_remove_internal(q, data, false); } bool queue_try_peek(queue_t *q, void *data) { - bool success = false; - uint32_t flags = spin_lock_blocking(q->lock); - if (queue_get_level_unsafe(q) != 0) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); - success = true; - } - spin_unlock(q->lock, flags); - return success; + return queue_peek_internal(q, data, false); } -void queue_add_blocking(queue_t *q, void *data) { - bool done; - do { - done = queue_try_add(q, data); - if (done) break; - __wfe(); - } while (true); +void queue_add_blocking(queue_t *q, const void *data) { + queue_add_internal(q, data, true); } void queue_remove_blocking(queue_t *q, void *data) { - bool done; - do { - done = queue_try_remove(q, data); - if (done) break; - __wfe(); - } while (true); + queue_remove_internal(q, data, true); } void queue_peek_blocking(queue_t *q, void *data) { - bool done; - do { - done = queue_try_peek(q, data); - if (done) break; - __wfe(); - } while (true); + queue_peek_internal(q, data, true); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h new file mode 100644 index 00000000000..e1e1e33f6b5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h @@ -0,0 +1,7 @@ +// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES +// DO NOT EDIT! + + +// based on PICO_CONFIG_HEADER_FILES: + +#include "boards/pico.h" \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h index 7b537522f9a..96e417bdd50 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h @@ -12,8 +12,8 @@ #define _PICO_VERSION_H #define PICO_SDK_VERSION_MAJOR 1 -#define PICO_SDK_VERSION_MINOR 0 -#define PICO_SDK_VERSION_REVISION 1 -#define PICO_SDK_VERSION_STRING "1.0.1" +#define PICO_SDK_VERSION_MINOR 3 +#define PICO_SDK_VERSION_REVISION 0 +#define PICO_SDK_VERSION_STRING "1.3.0" #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt index 56790055b06..9edcd7b09cc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/CMakeLists.txt @@ -14,15 +14,24 @@ pico_add_subdirectory(pico_stdlib) pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) macro(pico_set_float_implementation TARGET IMPL) + # ignore endmacro() macro(pico_set_double_implementation TARGET IMPL) + # ignore +endmacro() + +macro(pico_set_binary_type TARGET IMPL) + # ignore endmacro() macro(pico_set_boot_stage2 TARGET IMPL) + # ignore endmacro() set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") function(pico_define_boot_stage2 NAME) add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c) -endfunction() \ No newline at end of file +endfunction() + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c index cfa374bdb67..52794b155c6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c @@ -1 +1,3 @@ -// empty \ No newline at end of file +void main() { + +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h index 4d818747add..c12668852ce 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_divider/include/hardware/divider.h @@ -78,7 +78,7 @@ static inline int32_t hw_divider_s32_remainder_wait() { } static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { - return b ? (a / b) : -1; + return b ? (a / b) : (uint32_t)(-1); } static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c index d5f4996f25a..1cbcbed3097 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/gpio.c @@ -27,6 +27,10 @@ void gpio_set_pulls(uint gpio, bool up, bool down) { } +void gpio_set_irqover(uint gpio, uint value) { + +} + void gpio_set_outover(uint gpio, uint value) { } @@ -39,6 +43,31 @@ void gpio_set_oeover(uint gpio, uint value) { } +void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled){ + +} + +bool gpio_is_input_hysteresis_enabled(uint gpio){ + return true; +} + +void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew){ + +} + +enum gpio_slew_rate gpio_get_slew_rate(uint gpio){ + return GPIO_SLEW_RATE_FAST; +} + +void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive){ + +} + +enum gpio_drive_strength gpio_get_drive_strength(uint gpio){ + return GPIO_DRIVE_STRENGTH_4MA; +} + + void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) { } @@ -115,4 +144,4 @@ void gpio_set_input_enabled(uint gpio, bool enable) { void gpio_init_mask(uint gpio_mask) { -} \ No newline at end of file +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h index d1b14ba9d90..b2b83a1efa4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_gpio/include/hardware/gpio.h @@ -27,6 +27,17 @@ enum gpio_function { GPIO_FUNC_NULL = 0xf, }; +enum gpio_slew_rate { + GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled + GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled +}; + +enum gpio_drive_strength { + GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength + GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength + GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength + GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength +}; #define GPIO_OUT 1 #define GPIO_IN 0 @@ -50,6 +61,8 @@ void gpio_disable_pulls(uint gpio); void gpio_set_pulls(uint gpio, bool up, bool down); +void gpio_set_irqover(uint gpio, uint value); + void gpio_set_outover(uint gpio, uint value); void gpio_set_inover(uint gpio, uint value); @@ -58,6 +71,18 @@ void gpio_set_oeover(uint gpio, uint value); void gpio_set_input_enabled(uint gpio, bool enable); +void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); + +bool gpio_is_input_hysteresis_enabled(uint gpio); + +void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew); + +enum gpio_slew_rate gpio_get_slew_rate(uint gpio); + +void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive); + +enum gpio_drive_strength gpio_get_drive_strength(uint gpio); + // Configure a GPIO for direct input/output from software void gpio_init(uint gpio); @@ -127,7 +152,9 @@ void gpio_set_dir_all_bits(uint32_t value); void gpio_set_dir(uint gpio, bool out); // debugging +#ifndef PICO_DEBUG_PIN_BASE #define PICO_DEBUG_PIN_BASE 19u +#endif // note these two macros may only be used once per compilation unit #define CU_REGISTER_DEBUG_PINS(p, ...) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c index d6dfa1cee2c..30f6a2070fc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_timer/timer.c @@ -51,7 +51,6 @@ uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() { PICO_WEAK_FUNCTION_DEF(time_reached) bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) { uint64_t target = to_us_since_boot(t); - if (target > 0xffffffffu) return false; return time_us_64() >= target; } @@ -66,12 +65,12 @@ void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) { const int chunk = 1u<<30u; uint64_t target_us = to_us_since_boot(target); uint64_t time_us = time_us_64(); - while (target_us - time_us >= chunk) { + while ((int64_t)(target_us - time_us) >= chunk) { busy_wait_us_32(chunk); time_us = time_us_64(); } - if (target_us != time_us) { - busy_wait_us_32(target_us - chunk); + if (target_us > time_us) { + busy_wait_us_32(target_us - time_us); } #endif } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_uart/uart.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_uart/uart.c index 2e5dae3f4b9..e610402839b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_uart/uart.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/hardware_uart/uart.c @@ -24,7 +24,7 @@ struct termios _tty; static tcflag_t _res_oflg = 0; static tcflag_t _res_lflg = 0; -void _resetty(void) { +void _resettty(void) { if (!isatty(STDIN_FILENO)) return; @@ -49,7 +49,7 @@ void _inittty(void) { tcsetattr(STDIN_FILENO, TCSANOW, &_tty); fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK); - atexit(_resetty); + atexit(_resettty); } #else @@ -88,10 +88,18 @@ size_t uart_is_readable(uart_inst_t *uart) { } // Write len bytes directly from src to the UART -//void uart_write_blocking(uart_inst_t uart, const uint8_t *src, size_t len); +void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) { + for (size_t i = 0; i < len; i++) { + uart_putc(uart, src[i]); + } +} // Read len bytes directly from the UART to dst -//void uart_read_blocking(uart_inst_t uart, uint8_t *dst, size_t len); +void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) { + for (size_t i = 0; i < len; i++) { + dst[i] = uart_getc(uart); + } +} // ---------------------------------------------------------------------------- // UART-specific operations and aliases diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt index e4f88292287..7732b1e8f54 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_bit_ops/CMakeLists.txt @@ -1,4 +1,4 @@ -add_library(pico_bit_ops INTERFACE) +pico_add_impl_library(pico_bit_ops) target_sources(pico_bit_ops INTERFACE ${CMAKE_CURRENT_LIST_DIR}/bit_ops.c) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt index 7a26204c2d4..f6936dda93c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_divider/CMakeLists.txt @@ -1,4 +1,4 @@ -add_library(pico_divider INTERFACE) +pico_add_impl_library(pico_divider) target_sources(pico_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.c) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt index c5eabdab2be..5b90fa39207 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_multicore) - add_library(pico_multicore INTERFACE) + pico_add_impl_library(pico_multicore) target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h index de6672ae278..1be16948997 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_multicore/include/pico/multicore.h @@ -13,29 +13,30 @@ extern "C" { #endif -void multicore_reset_core1(); +void multicore_reset_core1(void); void multicore_launch_core1(void (*entry)(void)); void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); -void multicore_sleep_core1(); void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); -bool multicore_fifo_rvalid(); -bool multicore_fifo_wready(); -void multicore_fifo_push(uint32_t data); +bool multicore_fifo_rvalid(void); +bool multicore_fifo_wready(void); +void multicore_fifo_push_blocking(uint32_t data); +bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); uint32_t multicore_fifo_pop_blocking(); -void multicore_fifo_drain(); -void multicore_fifo_clear_irq(); -int32_t multicore_fifo_get_status(); +bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); +void multicore_fifo_drain(void); +void multicore_fifo_clear_irq(void); +uint32_t multicore_fifo_get_status(void); // call this from the lockout victim thread -void multicore_lockout_victim_init(); +void multicore_lockout_victim_init(void); // start locking out the other core (it will be bool multicore_lockout_start_timeout_us(uint64_t timeout_us); -void multicore_lockout_start_blocking(); +void multicore_lockout_start_blocking(void); bool multicore_lockout_end_timeout_us(uint64_t timeout_us); -void multicore_lockout_end_blocking(); +void multicore_lockout_end_blocking(void); #ifdef __cplusplus } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt index 92ae6a2b703..c78e330bc83 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/CMakeLists.txt @@ -1,3 +1,5 @@ +# This file may be included directly by a build to get common SDK macros and types + if (NOT TARGET pico_platform_headers) add_library(pico_platform_headers INTERFACE) @@ -11,7 +13,11 @@ if (NOT TARGET pico_platform_headers) endif() if (NOT TARGET pico_platform) - add_library(pico_platform INTERFACE) + if (COMMAND pico_add_platform_library) + pico_add_platform_library(pico_platform) + else() + add_library(pico_platform INTERFACE) + endif() target_sources(pico_platform INTERFACE ${CMAKE_CURRENT_LIST_DIR}/platform_base.c @@ -22,4 +28,4 @@ endif() function(pico_add_platform_library TARGET) target_link_libraries(pico_platform INTERFACE ${TARGET}) -endfunction() \ No newline at end of file +endfunction() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h index 1ca575e29b8..6d0aa841c39 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/hardware/platform_defs.h @@ -21,4 +21,8 @@ #define NUM_SPIN_LOCKS 32u +#ifndef _u +#define _u(x) x ## u +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h index 0e994d9b480..27e5c0854bf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_platform/include/pico/platform.h @@ -20,15 +20,21 @@ extern "C" { #endif -#define __not_in_flash(grup) +#define __not_in_flash(group) #define __not_in_flash_func(func) func #define __no_inline_not_in_flash_func(func) #define __in_flash(group) #define __scratch_x(group) #define __scratch_y(group) -#define __packed_aligned +#ifndef _MSC_VER +#define __packed __attribute__((packed)) +#define __packed_aligned __packed __attribute((aligned)) +#else +// MSVC requires #pragma pack which isn't compatible with a single attribute style define #define __packed +#define __packed_aligned +#endif #define __time_critical_func(x) x #define __after_data(group) @@ -36,6 +42,10 @@ extern "C" { //int running_on_fpga() { return false; } extern void tight_loop_contents(); +#ifndef __STRING +#define __STRING(x) #x +#endif + #ifndef _MSC_VER #ifndef __noreturn #define __noreturn __attribute((noreturn)) @@ -77,10 +87,6 @@ extern void tight_loop_contents(); #define __CONCAT(x,y) x ## y #endif -#ifndef __STRING -#define __STRING(x) #x -#endif() - #define __thread __declspec( thread ) #define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak))); @@ -126,11 +132,13 @@ void *decode_host_safe_hw_ptr(uint32_t ptr); typedef unsigned int uint; -inline static int32_t __mul_instruction(int32_t a,int32_t b) +static inline int32_t __mul_instruction(int32_t a,int32_t b) { return a*b; } +static inline void __compiler_memory_barrier(void) { +} #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt index 2151746d73c..8bfbdee810c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_printf/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_printf) - add_library(pico_printf INTERFACE) + pico_add_impl_library(pico_printf) function(pico_set_printf_implementation) endfunction() endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt index 8ab5ed466d4..428c1a9e538 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/CMakeLists.txt @@ -1,14 +1,14 @@ if (NOT TARGET pico_stdio) - add_library(pico_stdio INTERFACE) + pico_add_impl_library(pico_stdio) target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio.c ) - add_library(pico_stdio_usb INTERFACE) - add_library(pico_stdio_uart INTERFACE) - add_library(pico_stdio_semihosting INTERFACE) + pico_add_impl_library(pico_stdio_usb) + pico_add_impl_library(pico_stdio_uart) + pico_add_impl_library(pico_stdio_semihosting) function(pico_enable_stdio_uart) endfunction() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h index 798edb3a171..de0bde16733 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdio/include/pico/stdio.h @@ -14,8 +14,11 @@ typedef struct stdio_driver stdio_driver_t; static inline void stdio_usb_init() {} void stdio_uart_init(); static inline void stdio_init_all() { stdio_uart_init(); } -static inline void stdio_filter_driver(stdio_driver_t *); +static inline void stdio_filter_driver(stdio_driver_t *driver) {} static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {} +static inline bool stdio_usb_connected(void) { return true; } int getchar_timeout_us(uint32_t timeout_us); +#define puts_raw puts +#define putchar_raw putchar #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt index f4dac4d8dee..257798cfbf8 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/pico_stdlib/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_stdlib) - add_library(pico_stdlib INTERFACE) + pico_add_impl_library(pico_stdlib) target_sources(pico_stdlib INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdlib.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt index a6089de0646..a19ea5ceb9b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/CMakeLists.txt @@ -4,3 +4,5 @@ pico_add_subdirectory(hardware_structs) pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h index 51c027222df..08c715944c9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h @@ -7,41 +7,38 @@ #ifndef _HARDWARE_PLATFORM_DEFS_H #define _HARDWARE_PLATFORM_DEFS_H -// This header is included from C and assembler - only define macros +// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ -#include "hardware/regs/addressmap.h" - -#define NUM_CORES 2u -#define NUM_DMA_CHANNELS 12u -#define NUM_IRQS 32u -#define NUM_PIOS 2u -#define NUM_PIO_STATE_MACHINES 4u -#define NUM_PWM_SLICES 8u -#define NUM_SPIN_LOCKS 32u -#define NUM_UARTS 2u -#define NUM_BANK0_GPIOS 30u - -#define PIO_INSTRUCTION_COUNT 32u - -#define XOSC_MHZ 12u - -// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE 0x800u +#ifndef _u +#ifdef __ASSEMBLER__ +#define _u(x) x +#else +#define _u(x) x ## u #endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE 0x800 -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 #endif -#ifndef PICO_FLASH_SIZE_BYTES -#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#define NUM_CORES _u(2) +#define NUM_DMA_CHANNELS _u(12) +#define NUM_DMA_TIMERS _u(4) +#define NUM_IRQS _u(32) +#define NUM_PIOS _u(2) +#define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PWM_SLICES _u(8) +#define NUM_SPIN_LOCKS _u(32) +#define NUM_UARTS _u(2) +#define NUM_I2CS _u(2) +#define NUM_SPIS _u(2) +#define NUM_TIMERS _u(4) +#define NUM_ADC_CHANNELS _u(5) + +#define NUM_BANK0_GPIOS _u(30) +#define NUM_QSPI_GPIOS _u(6) + +#define PIO_INSTRUCTION_COUNT _u(32) + +// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base +#ifndef XOSC_MHZ +#define XOSC_MHZ _u(12) #endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h index 82bb0f8fb69..47510be51e0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : ADC_CS // Description : ADC Control and Status -#define ADC_CS_OFFSET 0x00000000 -#define ADC_CS_BITS 0x001f770f -#define ADC_CS_RESET 0x00000000 +#define ADC_CS_OFFSET _u(0x00000000) +#define ADC_CS_BITS _u(0x001f770f) +#define ADC_CS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_CS_RROBIN // Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to @@ -27,202 +27,202 @@ // indicated by AINSEL. // AINSEL will be updated after each conversion with the // newly-selected channel. -#define ADC_CS_RROBIN_RESET 0x00 -#define ADC_CS_RROBIN_BITS 0x001f0000 -#define ADC_CS_RROBIN_MSB 20 -#define ADC_CS_RROBIN_LSB 16 +#define ADC_CS_RROBIN_RESET _u(0x00) +#define ADC_CS_RROBIN_BITS _u(0x001f0000) +#define ADC_CS_RROBIN_MSB _u(20) +#define ADC_CS_RROBIN_LSB _u(16) #define ADC_CS_RROBIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_AINSEL // Description : Select analog mux input. Updated automatically in round-robin // mode. -#define ADC_CS_AINSEL_RESET 0x0 -#define ADC_CS_AINSEL_BITS 0x00007000 -#define ADC_CS_AINSEL_MSB 14 -#define ADC_CS_AINSEL_LSB 12 +#define ADC_CS_AINSEL_RESET _u(0x0) +#define ADC_CS_AINSEL_BITS _u(0x00007000) +#define ADC_CS_AINSEL_MSB _u(14) +#define ADC_CS_AINSEL_LSB _u(12) #define ADC_CS_AINSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_ERR_STICKY // Description : Some past ADC conversion encountered an error. Write 1 to // clear. -#define ADC_CS_ERR_STICKY_RESET 0x0 -#define ADC_CS_ERR_STICKY_BITS 0x00000400 -#define ADC_CS_ERR_STICKY_MSB 10 -#define ADC_CS_ERR_STICKY_LSB 10 +#define ADC_CS_ERR_STICKY_RESET _u(0x0) +#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) +#define ADC_CS_ERR_STICKY_MSB _u(10) +#define ADC_CS_ERR_STICKY_LSB _u(10) #define ADC_CS_ERR_STICKY_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_CS_ERR // Description : The most recent ADC conversion encountered an error; result is // undefined or noisy. -#define ADC_CS_ERR_RESET 0x0 -#define ADC_CS_ERR_BITS 0x00000200 -#define ADC_CS_ERR_MSB 9 -#define ADC_CS_ERR_LSB 9 +#define ADC_CS_ERR_RESET _u(0x0) +#define ADC_CS_ERR_BITS _u(0x00000200) +#define ADC_CS_ERR_MSB _u(9) +#define ADC_CS_ERR_LSB _u(9) #define ADC_CS_ERR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_CS_READY // Description : 1 if the ADC is ready to start a new conversion. Implies any // previous conversion has completed. // 0 whilst conversion in progress. -#define ADC_CS_READY_RESET 0x0 -#define ADC_CS_READY_BITS 0x00000100 -#define ADC_CS_READY_MSB 8 -#define ADC_CS_READY_LSB 8 +#define ADC_CS_READY_RESET _u(0x0) +#define ADC_CS_READY_BITS _u(0x00000100) +#define ADC_CS_READY_MSB _u(8) +#define ADC_CS_READY_LSB _u(8) #define ADC_CS_READY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_CS_START_MANY // Description : Continuously perform conversions whilst this bit is 1. A new // conversion will start immediately after the previous finishes. -#define ADC_CS_START_MANY_RESET 0x0 -#define ADC_CS_START_MANY_BITS 0x00000008 -#define ADC_CS_START_MANY_MSB 3 -#define ADC_CS_START_MANY_LSB 3 +#define ADC_CS_START_MANY_RESET _u(0x0) +#define ADC_CS_START_MANY_BITS _u(0x00000008) +#define ADC_CS_START_MANY_MSB _u(3) +#define ADC_CS_START_MANY_LSB _u(3) #define ADC_CS_START_MANY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_START_ONCE // Description : Start a single conversion. Self-clearing. Ignored if start_many // is asserted. -#define ADC_CS_START_ONCE_RESET 0x0 -#define ADC_CS_START_ONCE_BITS 0x00000004 -#define ADC_CS_START_ONCE_MSB 2 -#define ADC_CS_START_ONCE_LSB 2 +#define ADC_CS_START_ONCE_RESET _u(0x0) +#define ADC_CS_START_ONCE_BITS _u(0x00000004) +#define ADC_CS_START_ONCE_MSB _u(2) +#define ADC_CS_START_ONCE_LSB _u(2) #define ADC_CS_START_ONCE_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : ADC_CS_TS_EN // Description : Power on temperature sensor. 1 - enabled. 0 - disabled. -#define ADC_CS_TS_EN_RESET 0x0 -#define ADC_CS_TS_EN_BITS 0x00000002 -#define ADC_CS_TS_EN_MSB 1 -#define ADC_CS_TS_EN_LSB 1 +#define ADC_CS_TS_EN_RESET _u(0x0) +#define ADC_CS_TS_EN_BITS _u(0x00000002) +#define ADC_CS_TS_EN_MSB _u(1) +#define ADC_CS_TS_EN_LSB _u(1) #define ADC_CS_TS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_EN // Description : Power on ADC and enable its clock. // 1 - enabled. 0 - disabled. -#define ADC_CS_EN_RESET 0x0 -#define ADC_CS_EN_BITS 0x00000001 -#define ADC_CS_EN_MSB 0 -#define ADC_CS_EN_LSB 0 +#define ADC_CS_EN_RESET _u(0x0) +#define ADC_CS_EN_BITS _u(0x00000001) +#define ADC_CS_EN_MSB _u(0) +#define ADC_CS_EN_LSB _u(0) #define ADC_CS_EN_ACCESS "RW" // ============================================================================= // Register : ADC_RESULT // Description : Result of most recent ADC conversion -#define ADC_RESULT_OFFSET 0x00000004 -#define ADC_RESULT_BITS 0x00000fff -#define ADC_RESULT_RESET 0x00000000 -#define ADC_RESULT_MSB 11 -#define ADC_RESULT_LSB 0 +#define ADC_RESULT_OFFSET _u(0x00000004) +#define ADC_RESULT_BITS _u(0x00000fff) +#define ADC_RESULT_RESET _u(0x00000000) +#define ADC_RESULT_MSB _u(11) +#define ADC_RESULT_LSB _u(0) #define ADC_RESULT_ACCESS "RO" // ============================================================================= // Register : ADC_FCS // Description : FIFO control and status -#define ADC_FCS_OFFSET 0x00000008 -#define ADC_FCS_BITS 0x0f0f0f0f -#define ADC_FCS_RESET 0x00000000 +#define ADC_FCS_OFFSET _u(0x00000008) +#define ADC_FCS_BITS _u(0x0f0f0f0f) +#define ADC_FCS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_FCS_THRESH // Description : DREQ/IRQ asserted when level >= threshold -#define ADC_FCS_THRESH_RESET 0x0 -#define ADC_FCS_THRESH_BITS 0x0f000000 -#define ADC_FCS_THRESH_MSB 27 -#define ADC_FCS_THRESH_LSB 24 +#define ADC_FCS_THRESH_RESET _u(0x0) +#define ADC_FCS_THRESH_BITS _u(0x0f000000) +#define ADC_FCS_THRESH_MSB _u(27) +#define ADC_FCS_THRESH_LSB _u(24) #define ADC_FCS_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_LEVEL // Description : The number of conversion results currently waiting in the FIFO -#define ADC_FCS_LEVEL_RESET 0x0 -#define ADC_FCS_LEVEL_BITS 0x000f0000 -#define ADC_FCS_LEVEL_MSB 19 -#define ADC_FCS_LEVEL_LSB 16 +#define ADC_FCS_LEVEL_RESET _u(0x0) +#define ADC_FCS_LEVEL_BITS _u(0x000f0000) +#define ADC_FCS_LEVEL_MSB _u(19) +#define ADC_FCS_LEVEL_LSB _u(16) #define ADC_FCS_LEVEL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_OVER // Description : 1 if the FIFO has been overflowed. Write 1 to clear. -#define ADC_FCS_OVER_RESET 0x0 -#define ADC_FCS_OVER_BITS 0x00000800 -#define ADC_FCS_OVER_MSB 11 -#define ADC_FCS_OVER_LSB 11 +#define ADC_FCS_OVER_RESET _u(0x0) +#define ADC_FCS_OVER_BITS _u(0x00000800) +#define ADC_FCS_OVER_MSB _u(11) +#define ADC_FCS_OVER_LSB _u(11) #define ADC_FCS_OVER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_UNDER // Description : 1 if the FIFO has been underflowed. Write 1 to clear. -#define ADC_FCS_UNDER_RESET 0x0 -#define ADC_FCS_UNDER_BITS 0x00000400 -#define ADC_FCS_UNDER_MSB 10 -#define ADC_FCS_UNDER_LSB 10 +#define ADC_FCS_UNDER_RESET _u(0x0) +#define ADC_FCS_UNDER_BITS _u(0x00000400) +#define ADC_FCS_UNDER_MSB _u(10) +#define ADC_FCS_UNDER_LSB _u(10) #define ADC_FCS_UNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_FULL // Description : None -#define ADC_FCS_FULL_RESET 0x0 -#define ADC_FCS_FULL_BITS 0x00000200 -#define ADC_FCS_FULL_MSB 9 -#define ADC_FCS_FULL_LSB 9 +#define ADC_FCS_FULL_RESET _u(0x0) +#define ADC_FCS_FULL_BITS _u(0x00000200) +#define ADC_FCS_FULL_MSB _u(9) +#define ADC_FCS_FULL_LSB _u(9) #define ADC_FCS_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EMPTY // Description : None -#define ADC_FCS_EMPTY_RESET 0x0 -#define ADC_FCS_EMPTY_BITS 0x00000100 -#define ADC_FCS_EMPTY_MSB 8 -#define ADC_FCS_EMPTY_LSB 8 +#define ADC_FCS_EMPTY_RESET _u(0x0) +#define ADC_FCS_EMPTY_BITS _u(0x00000100) +#define ADC_FCS_EMPTY_MSB _u(8) +#define ADC_FCS_EMPTY_LSB _u(8) #define ADC_FCS_EMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_DREQ_EN // Description : If 1: assert DMA requests when FIFO contains data -#define ADC_FCS_DREQ_EN_RESET 0x0 -#define ADC_FCS_DREQ_EN_BITS 0x00000008 -#define ADC_FCS_DREQ_EN_MSB 3 -#define ADC_FCS_DREQ_EN_LSB 3 +#define ADC_FCS_DREQ_EN_RESET _u(0x0) +#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) +#define ADC_FCS_DREQ_EN_MSB _u(3) +#define ADC_FCS_DREQ_EN_LSB _u(3) #define ADC_FCS_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_ERR // Description : If 1: conversion error bit appears in the FIFO alongside the // result -#define ADC_FCS_ERR_RESET 0x0 -#define ADC_FCS_ERR_BITS 0x00000004 -#define ADC_FCS_ERR_MSB 2 -#define ADC_FCS_ERR_LSB 2 +#define ADC_FCS_ERR_RESET _u(0x0) +#define ADC_FCS_ERR_BITS _u(0x00000004) +#define ADC_FCS_ERR_MSB _u(2) +#define ADC_FCS_ERR_LSB _u(2) #define ADC_FCS_ERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_SHIFT // Description : If 1: FIFO results are right-shifted to be one byte in size. // Enables DMA to byte buffers. -#define ADC_FCS_SHIFT_RESET 0x0 -#define ADC_FCS_SHIFT_BITS 0x00000002 -#define ADC_FCS_SHIFT_MSB 1 -#define ADC_FCS_SHIFT_LSB 1 +#define ADC_FCS_SHIFT_RESET _u(0x0) +#define ADC_FCS_SHIFT_BITS _u(0x00000002) +#define ADC_FCS_SHIFT_MSB _u(1) +#define ADC_FCS_SHIFT_LSB _u(1) #define ADC_FCS_SHIFT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EN // Description : If 1: write result to the FIFO after each conversion. -#define ADC_FCS_EN_RESET 0x0 -#define ADC_FCS_EN_BITS 0x00000001 -#define ADC_FCS_EN_MSB 0 -#define ADC_FCS_EN_LSB 0 +#define ADC_FCS_EN_RESET _u(0x0) +#define ADC_FCS_EN_BITS _u(0x00000001) +#define ADC_FCS_EN_MSB _u(0) +#define ADC_FCS_EN_LSB _u(0) #define ADC_FCS_EN_ACCESS "RW" // ============================================================================= // Register : ADC_FIFO // Description : Conversion result FIFO -#define ADC_FIFO_OFFSET 0x0000000c -#define ADC_FIFO_BITS 0x00008fff -#define ADC_FIFO_RESET 0x00000000 +#define ADC_FIFO_OFFSET _u(0x0000000c) +#define ADC_FIFO_BITS _u(0x00008fff) +#define ADC_FIFO_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_FIFO_ERR // Description : 1 if this particular sample experienced a conversion error. // Remains in the same location if the sample is shifted. #define ADC_FIFO_ERR_RESET "-" -#define ADC_FIFO_ERR_BITS 0x00008000 -#define ADC_FIFO_ERR_MSB 15 -#define ADC_FIFO_ERR_LSB 15 +#define ADC_FIFO_ERR_BITS _u(0x00008000) +#define ADC_FIFO_ERR_MSB _u(15) +#define ADC_FIFO_ERR_LSB _u(15) #define ADC_FIFO_ERR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : ADC_FIFO_VAL // Description : None #define ADC_FIFO_VAL_RESET "-" -#define ADC_FIFO_VAL_BITS 0x00000fff -#define ADC_FIFO_VAL_MSB 11 -#define ADC_FIFO_VAL_LSB 0 +#define ADC_FIFO_VAL_BITS _u(0x00000fff) +#define ADC_FIFO_VAL_MSB _u(11) +#define ADC_FIFO_VAL_LSB _u(0) #define ADC_FIFO_VAL_ACCESS "RF" // ============================================================================= // Register : ADC_DIV @@ -231,84 +231,84 @@ // at regular intervals rather than back-to-back. // The divider is reset when either of these fields are written. // Total period is 1 + INT + FRAC / 256 -#define ADC_DIV_OFFSET 0x00000010 -#define ADC_DIV_BITS 0x00ffffff -#define ADC_DIV_RESET 0x00000000 +#define ADC_DIV_OFFSET _u(0x00000010) +#define ADC_DIV_BITS _u(0x00ffffff) +#define ADC_DIV_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_DIV_INT // Description : Integer part of clock divisor. -#define ADC_DIV_INT_RESET 0x0000 -#define ADC_DIV_INT_BITS 0x00ffff00 -#define ADC_DIV_INT_MSB 23 -#define ADC_DIV_INT_LSB 8 +#define ADC_DIV_INT_RESET _u(0x0000) +#define ADC_DIV_INT_BITS _u(0x00ffff00) +#define ADC_DIV_INT_MSB _u(23) +#define ADC_DIV_INT_LSB _u(8) #define ADC_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_DIV_FRAC // Description : Fractional part of clock divisor. First-order delta-sigma. -#define ADC_DIV_FRAC_RESET 0x00 -#define ADC_DIV_FRAC_BITS 0x000000ff -#define ADC_DIV_FRAC_MSB 7 -#define ADC_DIV_FRAC_LSB 0 +#define ADC_DIV_FRAC_RESET _u(0x00) +#define ADC_DIV_FRAC_BITS _u(0x000000ff) +#define ADC_DIV_FRAC_MSB _u(7) +#define ADC_DIV_FRAC_LSB _u(0) #define ADC_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : ADC_INTR // Description : Raw Interrupts -#define ADC_INTR_OFFSET 0x00000014 -#define ADC_INTR_BITS 0x00000001 -#define ADC_INTR_RESET 0x00000000 +#define ADC_INTR_OFFSET _u(0x00000014) +#define ADC_INTR_BITS _u(0x00000001) +#define ADC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTR_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTR_FIFO_RESET 0x0 -#define ADC_INTR_FIFO_BITS 0x00000001 -#define ADC_INTR_FIFO_MSB 0 -#define ADC_INTR_FIFO_LSB 0 +#define ADC_INTR_FIFO_RESET _u(0x0) +#define ADC_INTR_FIFO_BITS _u(0x00000001) +#define ADC_INTR_FIFO_MSB _u(0) +#define ADC_INTR_FIFO_LSB _u(0) #define ADC_INTR_FIFO_ACCESS "RO" // ============================================================================= // Register : ADC_INTE // Description : Interrupt Enable -#define ADC_INTE_OFFSET 0x00000018 -#define ADC_INTE_BITS 0x00000001 -#define ADC_INTE_RESET 0x00000000 +#define ADC_INTE_OFFSET _u(0x00000018) +#define ADC_INTE_BITS _u(0x00000001) +#define ADC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTE_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTE_FIFO_RESET 0x0 -#define ADC_INTE_FIFO_BITS 0x00000001 -#define ADC_INTE_FIFO_MSB 0 -#define ADC_INTE_FIFO_LSB 0 +#define ADC_INTE_FIFO_RESET _u(0x0) +#define ADC_INTE_FIFO_BITS _u(0x00000001) +#define ADC_INTE_FIFO_MSB _u(0) +#define ADC_INTE_FIFO_LSB _u(0) #define ADC_INTE_FIFO_ACCESS "RW" // ============================================================================= // Register : ADC_INTF // Description : Interrupt Force -#define ADC_INTF_OFFSET 0x0000001c -#define ADC_INTF_BITS 0x00000001 -#define ADC_INTF_RESET 0x00000000 +#define ADC_INTF_OFFSET _u(0x0000001c) +#define ADC_INTF_BITS _u(0x00000001) +#define ADC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTF_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTF_FIFO_RESET 0x0 -#define ADC_INTF_FIFO_BITS 0x00000001 -#define ADC_INTF_FIFO_MSB 0 -#define ADC_INTF_FIFO_LSB 0 +#define ADC_INTF_FIFO_RESET _u(0x0) +#define ADC_INTF_FIFO_BITS _u(0x00000001) +#define ADC_INTF_FIFO_MSB _u(0) +#define ADC_INTF_FIFO_LSB _u(0) #define ADC_INTF_FIFO_ACCESS "RW" // ============================================================================= // Register : ADC_INTS // Description : Interrupt status after masking & forcing -#define ADC_INTS_OFFSET 0x00000020 -#define ADC_INTS_BITS 0x00000001 -#define ADC_INTS_RESET 0x00000000 +#define ADC_INTS_OFFSET _u(0x00000020) +#define ADC_INTS_BITS _u(0x00000001) +#define ADC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTS_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTS_FIFO_RESET 0x0 -#define ADC_INTS_FIFO_BITS 0x00000001 -#define ADC_INTS_FIFO_MSB 0 -#define ADC_INTS_FIFO_LSB 0 +#define ADC_INTS_FIFO_RESET _u(0x0) +#define ADC_INTS_FIFO_BITS _u(0x00000001) +#define ADC_INTS_FIFO_MSB _u(0) +#define ADC_INTS_FIFO_LSB _u(0) #define ADC_INTS_FIFO_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_ADC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h index 39451ac22ce..b39ab45fdcf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h @@ -6,67 +6,69 @@ #ifndef _ADDRESSMAP_H_ #define _ADDRESSMAP_H_ +#include "hardware/platform_defs.h" + // Register address offsets for atomic RMW aliases #define REG_ALIAS_RW_BITS (0x0u << 12u) #define REG_ALIAS_XOR_BITS (0x1u << 12u) #define REG_ALIAS_SET_BITS (0x2u << 12u) #define REG_ALIAS_CLR_BITS (0x3u << 12u) -#define ROM_BASE 0x00000000 -#define XIP_BASE 0x10000000 -#define XIP_MAIN_BASE 0x10000000 -#define XIP_NOALLOC_BASE 0x11000000 -#define XIP_NOCACHE_BASE 0x12000000 -#define XIP_NOCACHE_NOALLOC_BASE 0x13000000 -#define XIP_CTRL_BASE 0x14000000 -#define XIP_SRAM_BASE 0x15000000 -#define XIP_SRAM_END 0x15004000 -#define XIP_SSI_BASE 0x18000000 -#define SRAM_BASE 0x20000000 -#define SRAM_STRIPED_BASE 0x20000000 -#define SRAM_STRIPED_END 0x20040000 -#define SRAM4_BASE 0x20040000 -#define SRAM5_BASE 0x20041000 -#define SRAM_END 0x20042000 -#define SRAM0_BASE 0x21000000 -#define SRAM1_BASE 0x21010000 -#define SRAM2_BASE 0x21020000 -#define SRAM3_BASE 0x21030000 -#define SYSINFO_BASE 0x40000000 -#define SYSCFG_BASE 0x40004000 -#define CLOCKS_BASE 0x40008000 -#define RESETS_BASE 0x4000c000 -#define PSM_BASE 0x40010000 -#define IO_BANK0_BASE 0x40014000 -#define IO_QSPI_BASE 0x40018000 -#define PADS_BANK0_BASE 0x4001c000 -#define PADS_QSPI_BASE 0x40020000 -#define XOSC_BASE 0x40024000 -#define PLL_SYS_BASE 0x40028000 -#define PLL_USB_BASE 0x4002c000 -#define BUSCTRL_BASE 0x40030000 -#define UART0_BASE 0x40034000 -#define UART1_BASE 0x40038000 -#define SPI0_BASE 0x4003c000 -#define SPI1_BASE 0x40040000 -#define I2C0_BASE 0x40044000 -#define I2C1_BASE 0x40048000 -#define ADC_BASE 0x4004c000 -#define PWM_BASE 0x40050000 -#define TIMER_BASE 0x40054000 -#define WATCHDOG_BASE 0x40058000 -#define RTC_BASE 0x4005c000 -#define ROSC_BASE 0x40060000 -#define VREG_AND_CHIP_RESET_BASE 0x40064000 -#define TBMAN_BASE 0x4006c000 -#define DMA_BASE 0x50000000 -#define USBCTRL_DPRAM_BASE 0x50100000 -#define USBCTRL_BASE 0x50100000 -#define USBCTRL_REGS_BASE 0x50110000 -#define PIO0_BASE 0x50200000 -#define PIO1_BASE 0x50300000 -#define XIP_AUX_BASE 0x50400000 -#define SIO_BASE 0xd0000000 -#define PPB_BASE 0xe0000000 +#define ROM_BASE _u(0x00000000) +#define XIP_BASE _u(0x10000000) +#define XIP_MAIN_BASE _u(0x10000000) +#define XIP_NOALLOC_BASE _u(0x11000000) +#define XIP_NOCACHE_BASE _u(0x12000000) +#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000) +#define XIP_CTRL_BASE _u(0x14000000) +#define XIP_SRAM_BASE _u(0x15000000) +#define XIP_SRAM_END _u(0x15004000) +#define XIP_SSI_BASE _u(0x18000000) +#define SRAM_BASE _u(0x20000000) +#define SRAM_STRIPED_BASE _u(0x20000000) +#define SRAM_STRIPED_END _u(0x20040000) +#define SRAM4_BASE _u(0x20040000) +#define SRAM5_BASE _u(0x20041000) +#define SRAM_END _u(0x20042000) +#define SRAM0_BASE _u(0x21000000) +#define SRAM1_BASE _u(0x21010000) +#define SRAM2_BASE _u(0x21020000) +#define SRAM3_BASE _u(0x21030000) +#define SYSINFO_BASE _u(0x40000000) +#define SYSCFG_BASE _u(0x40004000) +#define CLOCKS_BASE _u(0x40008000) +#define RESETS_BASE _u(0x4000c000) +#define PSM_BASE _u(0x40010000) +#define IO_BANK0_BASE _u(0x40014000) +#define IO_QSPI_BASE _u(0x40018000) +#define PADS_BANK0_BASE _u(0x4001c000) +#define PADS_QSPI_BASE _u(0x40020000) +#define XOSC_BASE _u(0x40024000) +#define PLL_SYS_BASE _u(0x40028000) +#define PLL_USB_BASE _u(0x4002c000) +#define BUSCTRL_BASE _u(0x40030000) +#define UART0_BASE _u(0x40034000) +#define UART1_BASE _u(0x40038000) +#define SPI0_BASE _u(0x4003c000) +#define SPI1_BASE _u(0x40040000) +#define I2C0_BASE _u(0x40044000) +#define I2C1_BASE _u(0x40048000) +#define ADC_BASE _u(0x4004c000) +#define PWM_BASE _u(0x40050000) +#define TIMER_BASE _u(0x40054000) +#define WATCHDOG_BASE _u(0x40058000) +#define RTC_BASE _u(0x4005c000) +#define ROSC_BASE _u(0x40060000) +#define VREG_AND_CHIP_RESET_BASE _u(0x40064000) +#define TBMAN_BASE _u(0x4006c000) +#define DMA_BASE _u(0x50000000) +#define USBCTRL_DPRAM_BASE _u(0x50100000) +#define USBCTRL_BASE _u(0x50100000) +#define USBCTRL_REGS_BASE _u(0x50110000) +#define PIO0_BASE _u(0x50200000) +#define PIO1_BASE _u(0x50300000) +#define XIP_AUX_BASE _u(0x50400000) +#define SIO_BASE _u(0xd0000000) +#define PPB_BASE _u(0xe0000000) #endif // _ADDRESSMAP_H_ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h index 6c02aee54a1..8be0d8666a8 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h @@ -15,40 +15,40 @@ // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY // Description : Set the priority of each master for bus arbitration. -#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000 -#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111 -#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) +#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_DMA_W // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000 -#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12 -#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) #define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_DMA_R // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100 -#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8 -#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) #define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_PROC1 // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010 -#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4 -#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) #define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_PROC0 // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001 -#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0 -#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) #define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY_ACK @@ -58,11 +58,11 @@ // Arbiters update their local priority when servicing a new // nonsequential access. // In normal circumstances this will happen almost immediately. -#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004 -#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001 -#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000 -#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0 -#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) +#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) #define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" // ============================================================================= // Register : BUSCTRL_PERFCTR0 @@ -71,22 +71,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL0 -#define BUSCTRL_PERFCTR0_OFFSET 0x00000008 -#define BUSCTRL_PERFCTR0_BITS 0x00ffffff -#define BUSCTRL_PERFCTR0_RESET 0x00000000 -#define BUSCTRL_PERFCTR0_MSB 23 -#define BUSCTRL_PERFCTR0_LSB 0 +#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008) +#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR0_MSB _u(23) +#define BUSCTRL_PERFCTR0_LSB _u(0) #define BUSCTRL_PERFCTR0_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL0 // Description : Bus fabric performance event select for PERFCTR0 -// Select a performance event for PERFCTR0 -#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c -#define BUSCTRL_PERFSEL0_BITS 0x0000001f -#define BUSCTRL_PERFSEL0_RESET 0x0000001f -#define BUSCTRL_PERFSEL0_MSB 4 -#define BUSCTRL_PERFSEL0_LSB 0 -#define BUSCTRL_PERFSEL0_ACCESS "RW" +// Select an event for PERFCTR0. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(4) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR1 // Description : Bus fabric performance counter 1 @@ -94,22 +135,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL1 -#define BUSCTRL_PERFCTR1_OFFSET 0x00000010 -#define BUSCTRL_PERFCTR1_BITS 0x00ffffff -#define BUSCTRL_PERFCTR1_RESET 0x00000000 -#define BUSCTRL_PERFCTR1_MSB 23 -#define BUSCTRL_PERFCTR1_LSB 0 +#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010) +#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR1_MSB _u(23) +#define BUSCTRL_PERFCTR1_LSB _u(0) #define BUSCTRL_PERFCTR1_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL1 // Description : Bus fabric performance event select for PERFCTR1 -// Select a performance event for PERFCTR1 -#define BUSCTRL_PERFSEL1_OFFSET 0x00000014 -#define BUSCTRL_PERFSEL1_BITS 0x0000001f -#define BUSCTRL_PERFSEL1_RESET 0x0000001f -#define BUSCTRL_PERFSEL1_MSB 4 -#define BUSCTRL_PERFSEL1_LSB 0 -#define BUSCTRL_PERFSEL1_ACCESS "RW" +// Select an event for PERFCTR1. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(4) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR2 // Description : Bus fabric performance counter 2 @@ -117,22 +199,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL2 -#define BUSCTRL_PERFCTR2_OFFSET 0x00000018 -#define BUSCTRL_PERFCTR2_BITS 0x00ffffff -#define BUSCTRL_PERFCTR2_RESET 0x00000000 -#define BUSCTRL_PERFCTR2_MSB 23 -#define BUSCTRL_PERFCTR2_LSB 0 +#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018) +#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR2_MSB _u(23) +#define BUSCTRL_PERFCTR2_LSB _u(0) #define BUSCTRL_PERFCTR2_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL2 // Description : Bus fabric performance event select for PERFCTR2 -// Select a performance event for PERFCTR2 -#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c -#define BUSCTRL_PERFSEL2_BITS 0x0000001f -#define BUSCTRL_PERFSEL2_RESET 0x0000001f -#define BUSCTRL_PERFSEL2_MSB 4 -#define BUSCTRL_PERFSEL2_LSB 0 -#define BUSCTRL_PERFSEL2_ACCESS "RW" +// Select an event for PERFCTR2. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(4) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR3 // Description : Bus fabric performance counter 3 @@ -140,21 +263,62 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL3 -#define BUSCTRL_PERFCTR3_OFFSET 0x00000020 -#define BUSCTRL_PERFCTR3_BITS 0x00ffffff -#define BUSCTRL_PERFCTR3_RESET 0x00000000 -#define BUSCTRL_PERFCTR3_MSB 23 -#define BUSCTRL_PERFCTR3_LSB 0 +#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020) +#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR3_MSB _u(23) +#define BUSCTRL_PERFCTR3_LSB _u(0) #define BUSCTRL_PERFCTR3_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL3 // Description : Bus fabric performance event select for PERFCTR3 -// Select a performance event for PERFCTR3 -#define BUSCTRL_PERFSEL3_OFFSET 0x00000024 -#define BUSCTRL_PERFSEL3_BITS 0x0000001f -#define BUSCTRL_PERFSEL3_RESET 0x0000001f -#define BUSCTRL_PERFSEL3_MSB 4 -#define BUSCTRL_PERFSEL3_LSB 0 -#define BUSCTRL_PERFSEL3_ACCESS "RW" +// Select an event for PERFCTR3. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(4) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) // ============================================================================= #endif // HARDWARE_REGS_BUSCTRL_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h index 1b44490f7c6..c0d2eaba4dc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h @@ -14,52 +14,52 @@ // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET 0x00000000 -#define CLOCKS_CLK_GPOUT0_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT0_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) +#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC @@ -75,102 +75,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT0_DIV_OFFSET 0x00000004 -#define CLOCKS_CLK_GPOUT0_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT0_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) +#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET 0x00000008 -#define CLOCKS_CLK_GPOUT0_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT0_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT0_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT0_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET 0x0000000c -#define CLOCKS_CLK_GPOUT1_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT1_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) +#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC @@ -186,102 +190,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT1_DIV_OFFSET 0x00000010 -#define CLOCKS_CLK_GPOUT1_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT1_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) +#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET 0x00000014 -#define CLOCKS_CLK_GPOUT1_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT1_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT1_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT1_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET 0x00000018 -#define CLOCKS_CLK_GPOUT2_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT2_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) +#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC @@ -297,102 +305,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT2_DIV_OFFSET 0x0000001c -#define CLOCKS_CLK_GPOUT2_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT2_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) +#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET 0x00000020 -#define CLOCKS_CLK_GPOUT2_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT2_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT2_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT2_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET 0x00000024 -#define CLOCKS_CLK_GPOUT3_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT3_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) +#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC @@ -408,73 +420,77 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT3_DIV_OFFSET 0x00000028 -#define CLOCKS_CLK_GPOUT3_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT3_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) +#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET 0x0000002c -#define CLOCKS_CLK_GPOUT3_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT3_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT3_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT3_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_REF_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_REF_CTRL_OFFSET 0x00000030 -#define CLOCKS_CLK_REF_CTRL_BITS 0x00000063 -#define CLOCKS_CLK_REF_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) +#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) +#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_AUXSRC // Description : Selects the auxiliary clock source, will glitch when switching // 0x0 -> clksrc_pll_usb // 0x1 -> clksrc_gpin0 // 0x2 -> clksrc_gpin1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS 0x00000060 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB 6 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_SRC // Description : Selects the clock source glitchlessly, can be changed @@ -483,42 +499,51 @@ // 0x1 -> clksrc_clk_ref_aux // 0x2 -> xosc_clksrc #define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS 0x00000003 -#define CLOCKS_CLK_REF_CTRL_SRC_MSB 1 -#define CLOCKS_CLK_REF_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) #define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH 0x0 -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX 0x1 -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC 0x2 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) // ============================================================================= // Register : CLOCKS_CLK_REF_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_REF_DIV_OFFSET 0x00000034 -#define CLOCKS_CLK_REF_DIV_BITS 0x00000300 -#define CLOCKS_CLK_REF_DIV_RESET 0x00000100 +#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) +#define CLOCKS_CLK_REF_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_REF_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_REF_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_REF_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_REF_DIV_INT_MSB 9 -#define CLOCKS_CLK_REF_DIV_INT_LSB 8 +#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_REF_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_REF_DIV_INT_LSB _u(8) #define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_REF_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_REF_SELECTED_OFFSET 0x00000038 -#define CLOCKS_CLK_REF_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_REF_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_REF_SELECTED_MSB 31 -#define CLOCKS_CLK_REF_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) +#define CLOCKS_CLK_REF_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_REF_SELECTED_MSB _u(31) +#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) #define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_SYS_CTRL_OFFSET 0x0000003c -#define CLOCKS_CLK_SYS_CTRL_BITS 0x000000e1 -#define CLOCKS_CLK_SYS_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) +#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) +#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_AUXSRC // Description : Selects the auxiliary clock source, will glitch when switching @@ -528,82 +553,91 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x2 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_SRC // Description : Selects the clock source glitchlessly, can be changed // on-the-fly // 0x0 -> clk_ref // 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET 0x0 -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS 0x00000001 -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB 0 -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) #define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF 0x0 -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX 0x1 +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) // ============================================================================= // Register : CLOCKS_CLK_SYS_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_SYS_DIV_OFFSET 0x00000040 -#define CLOCKS_CLK_SYS_DIV_BITS 0xffffffff -#define CLOCKS_CLK_SYS_DIV_RESET 0x00000100 +#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) +#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_SYS_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_SYS_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_SYS_DIV_INT_MSB 31 -#define CLOCKS_CLK_SYS_DIV_INT_LSB 8 +#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(8) #define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_SYS_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_SYS_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_SYS_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_SYS_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_SYS_SELECTED_OFFSET 0x00000044 -#define CLOCKS_CLK_SYS_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_SYS_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_SYS_SELECTED_MSB 31 -#define CLOCKS_CLK_SYS_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) +#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_SYS_SELECTED_MSB _u(31) +#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) #define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_PERI_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_PERI_CTRL_OFFSET 0x00000048 -#define CLOCKS_CLK_PERI_CTRL_BITS 0x00000ce0 -#define CLOCKS_CLK_PERI_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) +#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x00000ce0) +#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_PERI_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_PERI_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_PERI_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_AUXSRC @@ -615,68 +649,72 @@ // 0x4 -> xosc_clksrc // 0x5 -> clksrc_gpin0 // 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS 0x0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x2 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x3 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x4 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x5 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x6 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) // ============================================================================= // Register : CLOCKS_CLK_PERI_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_PERI_SELECTED_OFFSET 0x00000050 -#define CLOCKS_CLK_PERI_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_PERI_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_PERI_SELECTED_MSB 31 -#define CLOCKS_CLK_PERI_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) +#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_MSB _u(31) +#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) #define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_USB_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_USB_CTRL_OFFSET 0x00000054 -#define CLOCKS_CLK_USB_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_USB_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054) +#define CLOCKS_CLK_USB_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_USB_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_USB_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_USB_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_USB_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_USB_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_USB_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_AUXSRC @@ -687,81 +725,85 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_USB_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_USB_DIV_OFFSET 0x00000058 -#define CLOCKS_CLK_USB_DIV_BITS 0x00000300 -#define CLOCKS_CLK_USB_DIV_RESET 0x00000100 +#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058) +#define CLOCKS_CLK_USB_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_USB_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_USB_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_USB_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_USB_DIV_INT_MSB 9 -#define CLOCKS_CLK_USB_DIV_INT_LSB 8 +#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_USB_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_USB_DIV_INT_LSB _u(8) #define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_USB_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_USB_SELECTED_OFFSET 0x0000005c -#define CLOCKS_CLK_USB_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_USB_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_USB_SELECTED_MSB 31 -#define CLOCKS_CLK_USB_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c) +#define CLOCKS_CLK_USB_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_MSB _u(31) +#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) #define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_ADC_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_ADC_CTRL_OFFSET 0x00000060 -#define CLOCKS_CLK_ADC_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_ADC_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060) +#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_ADC_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_ADC_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_ADC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_AUXSRC @@ -772,81 +814,85 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_ADC_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_ADC_DIV_OFFSET 0x00000064 -#define CLOCKS_CLK_ADC_DIV_BITS 0x00000300 -#define CLOCKS_CLK_ADC_DIV_RESET 0x00000100 +#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064) +#define CLOCKS_CLK_ADC_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_ADC_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_ADC_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_ADC_DIV_INT_MSB 9 -#define CLOCKS_CLK_ADC_DIV_INT_LSB 8 +#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(8) #define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_ADC_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_ADC_SELECTED_OFFSET 0x00000068 -#define CLOCKS_CLK_ADC_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_ADC_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_ADC_SELECTED_MSB 31 -#define CLOCKS_CLK_ADC_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068) +#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_MSB _u(31) +#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) #define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_RTC_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_RTC_CTRL_OFFSET 0x0000006c -#define CLOCKS_CLK_RTC_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_RTC_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c) +#define CLOCKS_CLK_RTC_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_RTC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_RTC_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_RTC_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_RTC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_AUXSRC @@ -857,153 +903,157 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_RTC_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_RTC_DIV_OFFSET 0x00000070 -#define CLOCKS_CLK_RTC_DIV_BITS 0xffffffff -#define CLOCKS_CLK_RTC_DIV_RESET 0x00000100 +#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070) +#define CLOCKS_CLK_RTC_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_RTC_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_RTC_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_RTC_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_RTC_DIV_INT_MSB 31 -#define CLOCKS_CLK_RTC_DIV_INT_LSB 8 +#define CLOCKS_CLK_RTC_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_RTC_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_RTC_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_RTC_DIV_INT_LSB _u(8) #define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_RTC_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_RTC_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_RTC_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_RTC_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_RTC_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_RTC_SELECTED_OFFSET 0x00000074 -#define CLOCKS_CLK_RTC_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_RTC_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_RTC_SELECTED_MSB 31 -#define CLOCKS_CLK_RTC_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074) +#define CLOCKS_CLK_RTC_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_RTC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_RTC_SELECTED_MSB _u(31) +#define CLOCKS_CLK_RTC_SELECTED_LSB _u(0) #define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_CTRL // Description : None -#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x00000078 -#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS 0x000111ff -#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET 0x000000ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078) +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR // Description : For clearing the resus after the fault that triggered it has // been corrected -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS 0x00010000 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB 16 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE // Description : Force a resus, for test purposes only -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS 0x00001000 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB 12 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE // Description : Enable resus -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS 0x00000100 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB 8 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT // Description : This is expressed as a number of clk_ref cycles // and must be >= 2x clk_ref_freq/min_clk_tst_freq -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET 0xff -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS 0x000000ff -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB 7 -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_STATUS // Description : None -#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x0000007c -#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS 0x00000001 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET 0x00000000 +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c) +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED // Description : Clock has been resuscitated, correct the error then send // ctrl_clear=1 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS 0x00000001 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB 0 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_FC0_REF_KHZ // Description : Reference clock frequency in kHz -#define CLOCKS_FC0_REF_KHZ_OFFSET 0x00000080 -#define CLOCKS_FC0_REF_KHZ_BITS 0x000fffff -#define CLOCKS_FC0_REF_KHZ_RESET 0x00000000 -#define CLOCKS_FC0_REF_KHZ_MSB 19 -#define CLOCKS_FC0_REF_KHZ_LSB 0 +#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080) +#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) +#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_REF_KHZ_MSB _u(19) +#define CLOCKS_FC0_REF_KHZ_LSB _u(0) #define CLOCKS_FC0_REF_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_MIN_KHZ // Description : Minimum pass frequency in kHz. This is optional. Set to 0 if // you are not using the pass/fail flags -#define CLOCKS_FC0_MIN_KHZ_OFFSET 0x00000084 -#define CLOCKS_FC0_MIN_KHZ_BITS 0x01ffffff -#define CLOCKS_FC0_MIN_KHZ_RESET 0x00000000 -#define CLOCKS_FC0_MIN_KHZ_MSB 24 -#define CLOCKS_FC0_MIN_KHZ_LSB 0 +#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084) +#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) +#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) #define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_MAX_KHZ // Description : Maximum pass frequency in kHz. This is optional. Set to // 0x1ffffff if you are not using the pass/fail flags -#define CLOCKS_FC0_MAX_KHZ_OFFSET 0x00000088 -#define CLOCKS_FC0_MAX_KHZ_BITS 0x01ffffff -#define CLOCKS_FC0_MAX_KHZ_RESET 0x01ffffff -#define CLOCKS_FC0_MAX_KHZ_MSB 24 -#define CLOCKS_FC0_MAX_KHZ_LSB 0 +#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088) +#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) +#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) #define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_DELAY // Description : Delays the start of frequency counting to allow the mux to // settle // Delay is measured in multiples of the reference clock period -#define CLOCKS_FC0_DELAY_OFFSET 0x0000008c -#define CLOCKS_FC0_DELAY_BITS 0x00000007 -#define CLOCKS_FC0_DELAY_RESET 0x00000001 -#define CLOCKS_FC0_DELAY_MSB 2 -#define CLOCKS_FC0_DELAY_LSB 0 +#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c) +#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) +#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) +#define CLOCKS_FC0_DELAY_MSB _u(2) +#define CLOCKS_FC0_DELAY_LSB _u(0) #define CLOCKS_FC0_DELAY_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_INTERVAL // Description : The test interval is 0.98us * 2**interval, but let's call it // 1us * 2**interval // The default gives a test interval of 250us -#define CLOCKS_FC0_INTERVAL_OFFSET 0x00000090 -#define CLOCKS_FC0_INTERVAL_BITS 0x0000000f -#define CLOCKS_FC0_INTERVAL_RESET 0x00000008 -#define CLOCKS_FC0_INTERVAL_MSB 3 -#define CLOCKS_FC0_INTERVAL_LSB 0 +#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090) +#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) +#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) +#define CLOCKS_FC0_INTERVAL_MSB _u(3) +#define CLOCKS_FC0_INTERVAL_LSB _u(0) #define CLOCKS_FC0_INTERVAL_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_SRC @@ -1023,1337 +1073,1337 @@ // 0x0b -> clk_usb // 0x0c -> clk_adc // 0x0d -> clk_rtc -#define CLOCKS_FC0_SRC_OFFSET 0x00000094 -#define CLOCKS_FC0_SRC_BITS 0x000000ff -#define CLOCKS_FC0_SRC_RESET 0x00000000 -#define CLOCKS_FC0_SRC_MSB 7 -#define CLOCKS_FC0_SRC_LSB 0 +#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) #define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL 0x00 -#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY 0x01 -#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY 0x02 -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC 0x03 -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH 0x04 -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC 0x05 -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 0x06 -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 0x07 -#define CLOCKS_FC0_SRC_VALUE_CLK_REF 0x08 -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS 0x09 -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI 0x0a -#define CLOCKS_FC0_SRC_VALUE_CLK_USB 0x0b -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC 0x0c -#define CLOCKS_FC0_SRC_VALUE_CLK_RTC 0x0d +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) // ============================================================================= // Register : CLOCKS_FC0_STATUS // Description : Frequency counter status -#define CLOCKS_FC0_STATUS_OFFSET 0x00000098 -#define CLOCKS_FC0_STATUS_BITS 0x11111111 -#define CLOCKS_FC0_STATUS_RESET 0x00000000 +#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098) +#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) +#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_DIED // Description : Test clock stopped during test -#define CLOCKS_FC0_STATUS_DIED_RESET 0x0 -#define CLOCKS_FC0_STATUS_DIED_BITS 0x10000000 -#define CLOCKS_FC0_STATUS_DIED_MSB 28 -#define CLOCKS_FC0_STATUS_DIED_LSB 28 +#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) +#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) #define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_FAST // Description : Test clock faster than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_FAST_RESET 0x0 -#define CLOCKS_FC0_STATUS_FAST_BITS 0x01000000 -#define CLOCKS_FC0_STATUS_FAST_MSB 24 -#define CLOCKS_FC0_STATUS_FAST_LSB 24 +#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) +#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) #define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_SLOW // Description : Test clock slower than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_SLOW_RESET 0x0 -#define CLOCKS_FC0_STATUS_SLOW_BITS 0x00100000 -#define CLOCKS_FC0_STATUS_SLOW_MSB 20 -#define CLOCKS_FC0_STATUS_SLOW_LSB 20 +#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) +#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) #define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_FAIL // Description : Test failed -#define CLOCKS_FC0_STATUS_FAIL_RESET 0x0 -#define CLOCKS_FC0_STATUS_FAIL_BITS 0x00010000 -#define CLOCKS_FC0_STATUS_FAIL_MSB 16 -#define CLOCKS_FC0_STATUS_FAIL_LSB 16 +#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) +#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) #define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_WAITING // Description : Waiting for test clock to start -#define CLOCKS_FC0_STATUS_WAITING_RESET 0x0 -#define CLOCKS_FC0_STATUS_WAITING_BITS 0x00001000 -#define CLOCKS_FC0_STATUS_WAITING_MSB 12 -#define CLOCKS_FC0_STATUS_WAITING_LSB 12 +#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) +#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) #define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_RUNNING // Description : Test running -#define CLOCKS_FC0_STATUS_RUNNING_RESET 0x0 -#define CLOCKS_FC0_STATUS_RUNNING_BITS 0x00000100 -#define CLOCKS_FC0_STATUS_RUNNING_MSB 8 -#define CLOCKS_FC0_STATUS_RUNNING_LSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) +#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) #define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_DONE // Description : Test complete -#define CLOCKS_FC0_STATUS_DONE_RESET 0x0 -#define CLOCKS_FC0_STATUS_DONE_BITS 0x00000010 -#define CLOCKS_FC0_STATUS_DONE_MSB 4 -#define CLOCKS_FC0_STATUS_DONE_LSB 4 +#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) +#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) #define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_PASS // Description : Test passed -#define CLOCKS_FC0_STATUS_PASS_RESET 0x0 -#define CLOCKS_FC0_STATUS_PASS_BITS 0x00000001 -#define CLOCKS_FC0_STATUS_PASS_MSB 0 -#define CLOCKS_FC0_STATUS_PASS_LSB 0 +#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) +#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) #define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_FC0_RESULT // Description : Result of frequency measurement, only valid when status_done=1 -#define CLOCKS_FC0_RESULT_OFFSET 0x0000009c -#define CLOCKS_FC0_RESULT_BITS 0x3fffffff -#define CLOCKS_FC0_RESULT_RESET 0x00000000 +#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c) +#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) +#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_KHZ // Description : None -#define CLOCKS_FC0_RESULT_KHZ_RESET 0x0000000 -#define CLOCKS_FC0_RESULT_KHZ_BITS 0x3fffffe0 -#define CLOCKS_FC0_RESULT_KHZ_MSB 29 -#define CLOCKS_FC0_RESULT_KHZ_LSB 5 +#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) +#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) +#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) +#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) #define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_FRAC // Description : None -#define CLOCKS_FC0_RESULT_FRAC_RESET 0x00 -#define CLOCKS_FC0_RESULT_FRAC_BITS 0x0000001f -#define CLOCKS_FC0_RESULT_FRAC_MSB 4 -#define CLOCKS_FC0_RESULT_FRAC_LSB 0 +#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) +#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) +#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) +#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) #define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" // ============================================================================= // Register : CLOCKS_WAKE_EN0 // Description : enable clock in wake mode -#define CLOCKS_WAKE_EN0_OFFSET 0x000000a0 -#define CLOCKS_WAKE_EN0_BITS 0xffffffff -#define CLOCKS_WAKE_EN0_RESET 0xffffffff +#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0) +#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) +#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC // Description : None -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_IO // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB 8 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC // Description : None -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_WAKE_EN1 // Description : enable clock in wake mode -#define CLOCKS_WAKE_EN1_OFFSET 0x000000a4 -#define CLOCKS_WAKE_EN1_BITS 0x00007fff -#define CLOCKS_WAKE_EN1_RESET 0x00007fff +#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4) +#define CLOCKS_WAKE_EN1_BITS _u(0x00007fff) +#define CLOCKS_WAKE_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 // Description : None -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 // Description : None -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" // ============================================================================= // Register : CLOCKS_SLEEP_EN0 // Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN0_OFFSET 0x000000a8 -#define CLOCKS_SLEEP_EN0_BITS 0xffffffff -#define CLOCKS_SLEEP_EN0_RESET 0xffffffff +#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8) +#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) +#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB 8 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_SLEEP_EN1 // Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN1_OFFSET 0x000000ac -#define CLOCKS_SLEEP_EN1_BITS 0x00007fff -#define CLOCKS_SLEEP_EN1_RESET 0x00007fff +#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac) +#define CLOCKS_SLEEP_EN1_BITS _u(0x00007fff) +#define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" // ============================================================================= // Register : CLOCKS_ENABLED0 // Description : indicates the state of the clock enable -#define CLOCKS_ENABLED0_OFFSET 0x000000b0 -#define CLOCKS_ENABLED0_BITS 0xffffffff -#define CLOCKS_ENABLED0_RESET 0x00000000 +#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0) +#define CLOCKS_ENABLED0_BITS _u(0xffffffff) +#define CLOCKS_ENABLED0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SIO // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RTC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_RTC_RTC // Description : None -#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROSC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RESETS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PWM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PSM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PADS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_JTAG // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_IO // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB 8 -#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_DMA // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ADC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_ADC_ADC // Description : None -#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_ENABLED1 // Description : indicates the state of the clock enable -#define CLOCKS_ENABLED1_OFFSET 0x000000b4 -#define CLOCKS_ENABLED1_BITS 0x00007fff -#define CLOCKS_ENABLED1_RESET 0x00000000 +#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4) +#define CLOCKS_ENABLED1_BITS _u(0x00007fff) +#define CLOCKS_ENABLED1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XOSC // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XIP // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART1 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART1 // Description : None -#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART0 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART0 // Description : None -#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TIMER // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" // ============================================================================= // Register : CLOCKS_INTR // Description : Raw Interrupts -#define CLOCKS_INTR_OFFSET 0x000000b8 -#define CLOCKS_INTR_BITS 0x00000001 -#define CLOCKS_INTR_RESET 0x00000000 +#define CLOCKS_INTR_OFFSET _u(0x000000b8) +#define CLOCKS_INTR_BITS _u(0x00000001) +#define CLOCKS_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTR_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTR_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTR_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTR_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTR_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_INTE // Description : Interrupt Enable -#define CLOCKS_INTE_OFFSET 0x000000bc -#define CLOCKS_INTE_BITS 0x00000001 -#define CLOCKS_INTE_RESET 0x00000000 +#define CLOCKS_INTE_OFFSET _u(0x000000bc) +#define CLOCKS_INTE_BITS _u(0x00000001) +#define CLOCKS_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTE_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTE_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTE_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTE_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTE_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_INTF // Description : Interrupt Force -#define CLOCKS_INTF_OFFSET 0x000000c0 -#define CLOCKS_INTF_BITS 0x00000001 -#define CLOCKS_INTF_RESET 0x00000000 +#define CLOCKS_INTF_OFFSET _u(0x000000c0) +#define CLOCKS_INTF_BITS _u(0x00000001) +#define CLOCKS_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTF_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTF_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTF_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTF_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTF_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_INTS // Description : Interrupt status after masking & forcing -#define CLOCKS_INTS_OFFSET 0x000000c4 -#define CLOCKS_INTS_BITS 0x00000001 -#define CLOCKS_INTS_RESET 0x00000000 +#define CLOCKS_INTS_OFFSET _u(0x000000c4) +#define CLOCKS_INTS_BITS _u(0x00000001) +#define CLOCKS_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTS_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTS_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTS_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTS_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTS_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_CLOCKS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h index 3a1fdbca12e..042c3c17cb7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -17,11 +17,11 @@ // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH0_READ_ADDR_OFFSET 0x00000000 -#define DMA_CH0_READ_ADDR_BITS 0xffffffff -#define DMA_CH0_READ_ADDR_RESET 0x00000000 -#define DMA_CH0_READ_ADDR_MSB 31 -#define DMA_CH0_READ_ADDR_LSB 0 +#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) +#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH0_READ_ADDR_MSB _u(31) +#define DMA_CH0_READ_ADDR_LSB _u(0) #define DMA_CH0_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_WRITE_ADDR @@ -29,11 +29,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH0_WRITE_ADDR_OFFSET 0x00000004 -#define DMA_CH0_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH0_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH0_WRITE_ADDR_MSB 31 -#define DMA_CH0_WRITE_ADDR_LSB 0 +#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) +#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH0_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_WRITE_ADDR_LSB _u(0) #define DMA_CH0_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_TRANS_COUNT @@ -57,27 +57,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH0_TRANS_COUNT_OFFSET 0x00000008 -#define DMA_CH0_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH0_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH0_TRANS_COUNT_MSB 31 -#define DMA_CH0_TRANS_COUNT_LSB 0 +#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) +#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH0_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_TRANS_COUNT_LSB _u(0) #define DMA_CH0_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_CTRL_TRIG // Description : DMA Channel 0 Control and Status -#define DMA_CH0_CTRL_TRIG_OFFSET 0x0000000c -#define DMA_CH0_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH0_CTRL_TRIG_RESET 0x00000000 +#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_READ_ERROR @@ -86,10 +86,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR @@ -98,10 +98,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_BUSY @@ -112,10 +112,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH0_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH0_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH0_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_SNIFF_EN @@ -126,10 +126,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_BSWAP @@ -137,10 +137,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH0_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH0_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH0_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET @@ -151,10 +151,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_TREQ_SEL @@ -168,36 +168,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (0). -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_RING_SIZE @@ -210,12 +210,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -223,10 +223,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_READ @@ -235,10 +235,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_DATA_SIZE @@ -248,14 +248,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -268,10 +268,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_EN @@ -281,136 +281,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH0_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH0_CTRL_TRIG_EN_MSB 0 -#define DMA_CH0_CTRL_TRIG_EN_LSB 0 +#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL1_CTRL_OFFSET 0x00000010 -#define DMA_CH0_AL1_CTRL_BITS 0xffffffff +#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) +#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL1_CTRL_RESET "-" -#define DMA_CH0_AL1_CTRL_MSB 31 -#define DMA_CH0_AL1_CTRL_LSB 0 -#define DMA_CH0_AL1_CTRL_ACCESS "RO" +#define DMA_CH0_AL1_CTRL_MSB _u(31) +#define DMA_CH0_AL1_CTRL_LSB _u(0) +#define DMA_CH0_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_READ_ADDR // Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL1_READ_ADDR_OFFSET 0x00000014 -#define DMA_CH0_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) +#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL1_READ_ADDR_RESET "-" -#define DMA_CH0_AL1_READ_ADDR_MSB 31 -#define DMA_CH0_AL1_READ_ADDR_LSB 0 -#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL1_WRITE_ADDR_OFFSET 0x00000018 -#define DMA_CH0_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) +#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH0_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 0 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000001c -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL2_CTRL_OFFSET 0x00000020 -#define DMA_CH0_AL2_CTRL_BITS 0xffffffff +#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) +#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL2_CTRL_RESET "-" -#define DMA_CH0_AL2_CTRL_MSB 31 -#define DMA_CH0_AL2_CTRL_LSB 0 -#define DMA_CH0_AL2_CTRL_ACCESS "RO" +#define DMA_CH0_AL2_CTRL_MSB _u(31) +#define DMA_CH0_AL2_CTRL_LSB _u(0) +#define DMA_CH0_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL2_TRANS_COUNT_OFFSET 0x00000024 -#define DMA_CH0_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) +#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH0_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH0_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_READ_ADDR // Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL2_READ_ADDR_OFFSET 0x00000028 -#define DMA_CH0_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) +#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL2_READ_ADDR_RESET "-" -#define DMA_CH0_AL2_READ_ADDR_MSB 31 -#define DMA_CH0_AL2_READ_ADDR_LSB 0 -#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 0 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000002c -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL3_CTRL_OFFSET 0x00000030 -#define DMA_CH0_AL3_CTRL_BITS 0xffffffff +#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) +#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL3_CTRL_RESET "-" -#define DMA_CH0_AL3_CTRL_MSB 31 -#define DMA_CH0_AL3_CTRL_LSB 0 -#define DMA_CH0_AL3_CTRL_ACCESS "RO" +#define DMA_CH0_AL3_CTRL_MSB _u(31) +#define DMA_CH0_AL3_CTRL_LSB _u(0) +#define DMA_CH0_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL3_WRITE_ADDR_OFFSET 0x00000034 -#define DMA_CH0_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) +#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH0_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL3_TRANS_COUNT_OFFSET 0x00000038 -#define DMA_CH0_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) +#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH0_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH0_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_READ_ADDR_TRIG // Description : Alias for channel 0 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET 0x0000003c -#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_READ_ADDR // Description : DMA Channel 1 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH1_READ_ADDR_OFFSET 0x00000040 -#define DMA_CH1_READ_ADDR_BITS 0xffffffff -#define DMA_CH1_READ_ADDR_RESET 0x00000000 -#define DMA_CH1_READ_ADDR_MSB 31 -#define DMA_CH1_READ_ADDR_LSB 0 +#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) +#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH1_READ_ADDR_MSB _u(31) +#define DMA_CH1_READ_ADDR_LSB _u(0) #define DMA_CH1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_WRITE_ADDR @@ -418,11 +418,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH1_WRITE_ADDR_OFFSET 0x00000044 -#define DMA_CH1_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH1_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH1_WRITE_ADDR_MSB 31 -#define DMA_CH1_WRITE_ADDR_LSB 0 +#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) +#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_WRITE_ADDR_LSB _u(0) #define DMA_CH1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_TRANS_COUNT @@ -446,27 +446,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH1_TRANS_COUNT_OFFSET 0x00000048 -#define DMA_CH1_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH1_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH1_TRANS_COUNT_MSB 31 -#define DMA_CH1_TRANS_COUNT_LSB 0 +#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) +#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH1_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_TRANS_COUNT_LSB _u(0) #define DMA_CH1_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_CTRL_TRIG // Description : DMA Channel 1 Control and Status -#define DMA_CH1_CTRL_TRIG_OFFSET 0x0000004c -#define DMA_CH1_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH1_CTRL_TRIG_RESET 0x00000800 +#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) +#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_READ_ERROR @@ -475,10 +475,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR @@ -487,10 +487,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_BUSY @@ -501,10 +501,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH1_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH1_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH1_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_SNIFF_EN @@ -515,10 +515,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_BSWAP @@ -526,10 +526,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH1_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH1_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH1_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET @@ -540,10 +540,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_TREQ_SEL @@ -557,36 +557,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (1). -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET 0x1 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_RING_SIZE @@ -599,12 +599,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -612,10 +612,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_READ @@ -624,10 +624,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_DATA_SIZE @@ -637,14 +637,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -657,10 +657,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_EN @@ -670,136 +670,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH1_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH1_CTRL_TRIG_EN_MSB 0 -#define DMA_CH1_CTRL_TRIG_EN_LSB 0 +#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL1_CTRL_OFFSET 0x00000050 -#define DMA_CH1_AL1_CTRL_BITS 0xffffffff +#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) +#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL1_CTRL_RESET "-" -#define DMA_CH1_AL1_CTRL_MSB 31 -#define DMA_CH1_AL1_CTRL_LSB 0 -#define DMA_CH1_AL1_CTRL_ACCESS "RO" +#define DMA_CH1_AL1_CTRL_MSB _u(31) +#define DMA_CH1_AL1_CTRL_LSB _u(0) +#define DMA_CH1_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_READ_ADDR // Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL1_READ_ADDR_OFFSET 0x00000054 -#define DMA_CH1_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) +#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL1_READ_ADDR_RESET "-" -#define DMA_CH1_AL1_READ_ADDR_MSB 31 -#define DMA_CH1_AL1_READ_ADDR_LSB 0 -#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL1_WRITE_ADDR_OFFSET 0x00000058 -#define DMA_CH1_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) +#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH1_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 1 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000005c -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL2_CTRL_OFFSET 0x00000060 -#define DMA_CH1_AL2_CTRL_BITS 0xffffffff +#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) +#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL2_CTRL_RESET "-" -#define DMA_CH1_AL2_CTRL_MSB 31 -#define DMA_CH1_AL2_CTRL_LSB 0 -#define DMA_CH1_AL2_CTRL_ACCESS "RO" +#define DMA_CH1_AL2_CTRL_MSB _u(31) +#define DMA_CH1_AL2_CTRL_LSB _u(0) +#define DMA_CH1_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL2_TRANS_COUNT_OFFSET 0x00000064 -#define DMA_CH1_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) +#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH1_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH1_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_READ_ADDR // Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL2_READ_ADDR_OFFSET 0x00000068 -#define DMA_CH1_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) +#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL2_READ_ADDR_RESET "-" -#define DMA_CH1_AL2_READ_ADDR_MSB 31 -#define DMA_CH1_AL2_READ_ADDR_LSB 0 -#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 1 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000006c -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL3_CTRL_OFFSET 0x00000070 -#define DMA_CH1_AL3_CTRL_BITS 0xffffffff +#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) +#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL3_CTRL_RESET "-" -#define DMA_CH1_AL3_CTRL_MSB 31 -#define DMA_CH1_AL3_CTRL_LSB 0 -#define DMA_CH1_AL3_CTRL_ACCESS "RO" +#define DMA_CH1_AL3_CTRL_MSB _u(31) +#define DMA_CH1_AL3_CTRL_LSB _u(0) +#define DMA_CH1_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL3_WRITE_ADDR_OFFSET 0x00000074 -#define DMA_CH1_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) +#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH1_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL3_TRANS_COUNT_OFFSET 0x00000078 -#define DMA_CH1_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) +#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH1_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH1_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_READ_ADDR_TRIG // Description : Alias for channel 1 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET 0x0000007c -#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_READ_ADDR // Description : DMA Channel 2 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH2_READ_ADDR_OFFSET 0x00000080 -#define DMA_CH2_READ_ADDR_BITS 0xffffffff -#define DMA_CH2_READ_ADDR_RESET 0x00000000 -#define DMA_CH2_READ_ADDR_MSB 31 -#define DMA_CH2_READ_ADDR_LSB 0 +#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) +#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH2_READ_ADDR_MSB _u(31) +#define DMA_CH2_READ_ADDR_LSB _u(0) #define DMA_CH2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_WRITE_ADDR @@ -807,11 +807,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH2_WRITE_ADDR_OFFSET 0x00000084 -#define DMA_CH2_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH2_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH2_WRITE_ADDR_MSB 31 -#define DMA_CH2_WRITE_ADDR_LSB 0 +#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) +#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH2_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_WRITE_ADDR_LSB _u(0) #define DMA_CH2_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_TRANS_COUNT @@ -835,27 +835,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH2_TRANS_COUNT_OFFSET 0x00000088 -#define DMA_CH2_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH2_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH2_TRANS_COUNT_MSB 31 -#define DMA_CH2_TRANS_COUNT_LSB 0 +#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) +#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_TRANS_COUNT_LSB _u(0) #define DMA_CH2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_CTRL_TRIG // Description : DMA Channel 2 Control and Status -#define DMA_CH2_CTRL_TRIG_OFFSET 0x0000008c -#define DMA_CH2_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH2_CTRL_TRIG_RESET 0x00001000 +#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) +#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_READ_ERROR @@ -864,10 +864,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR @@ -876,10 +876,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_BUSY @@ -890,10 +890,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH2_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH2_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH2_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_SNIFF_EN @@ -904,10 +904,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_BSWAP @@ -915,10 +915,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH2_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH2_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH2_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET @@ -929,10 +929,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_TREQ_SEL @@ -946,36 +946,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (2). -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET 0x2 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_RING_SIZE @@ -988,12 +988,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1001,10 +1001,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_READ @@ -1013,10 +1013,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_DATA_SIZE @@ -1026,14 +1026,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1046,10 +1046,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_EN @@ -1059,136 +1059,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH2_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH2_CTRL_TRIG_EN_MSB 0 -#define DMA_CH2_CTRL_TRIG_EN_LSB 0 +#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL1_CTRL_OFFSET 0x00000090 -#define DMA_CH2_AL1_CTRL_BITS 0xffffffff +#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) +#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL1_CTRL_RESET "-" -#define DMA_CH2_AL1_CTRL_MSB 31 -#define DMA_CH2_AL1_CTRL_LSB 0 -#define DMA_CH2_AL1_CTRL_ACCESS "RO" +#define DMA_CH2_AL1_CTRL_MSB _u(31) +#define DMA_CH2_AL1_CTRL_LSB _u(0) +#define DMA_CH2_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_READ_ADDR // Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL1_READ_ADDR_OFFSET 0x00000094 -#define DMA_CH2_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) +#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL1_READ_ADDR_RESET "-" -#define DMA_CH2_AL1_READ_ADDR_MSB 31 -#define DMA_CH2_AL1_READ_ADDR_LSB 0 -#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL1_WRITE_ADDR_OFFSET 0x00000098 -#define DMA_CH2_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) +#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH2_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 2 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000009c -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL2_CTRL_OFFSET 0x000000a0 -#define DMA_CH2_AL2_CTRL_BITS 0xffffffff +#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) +#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL2_CTRL_RESET "-" -#define DMA_CH2_AL2_CTRL_MSB 31 -#define DMA_CH2_AL2_CTRL_LSB 0 -#define DMA_CH2_AL2_CTRL_ACCESS "RO" +#define DMA_CH2_AL2_CTRL_MSB _u(31) +#define DMA_CH2_AL2_CTRL_LSB _u(0) +#define DMA_CH2_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL2_TRANS_COUNT_OFFSET 0x000000a4 -#define DMA_CH2_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) +#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH2_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH2_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_READ_ADDR // Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL2_READ_ADDR_OFFSET 0x000000a8 -#define DMA_CH2_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) +#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL2_READ_ADDR_RESET "-" -#define DMA_CH2_AL2_READ_ADDR_MSB 31 -#define DMA_CH2_AL2_READ_ADDR_LSB 0 -#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 2 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ac -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL3_CTRL_OFFSET 0x000000b0 -#define DMA_CH2_AL3_CTRL_BITS 0xffffffff +#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) +#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL3_CTRL_RESET "-" -#define DMA_CH2_AL3_CTRL_MSB 31 -#define DMA_CH2_AL3_CTRL_LSB 0 -#define DMA_CH2_AL3_CTRL_ACCESS "RO" +#define DMA_CH2_AL3_CTRL_MSB _u(31) +#define DMA_CH2_AL3_CTRL_LSB _u(0) +#define DMA_CH2_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL3_WRITE_ADDR_OFFSET 0x000000b4 -#define DMA_CH2_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) +#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH2_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL3_TRANS_COUNT_OFFSET 0x000000b8 -#define DMA_CH2_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) +#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH2_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH2_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_READ_ADDR_TRIG // Description : Alias for channel 2 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET 0x000000bc -#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_READ_ADDR // Description : DMA Channel 3 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH3_READ_ADDR_OFFSET 0x000000c0 -#define DMA_CH3_READ_ADDR_BITS 0xffffffff -#define DMA_CH3_READ_ADDR_RESET 0x00000000 -#define DMA_CH3_READ_ADDR_MSB 31 -#define DMA_CH3_READ_ADDR_LSB 0 +#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) +#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH3_READ_ADDR_MSB _u(31) +#define DMA_CH3_READ_ADDR_LSB _u(0) #define DMA_CH3_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_WRITE_ADDR @@ -1196,11 +1196,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH3_WRITE_ADDR_OFFSET 0x000000c4 -#define DMA_CH3_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH3_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH3_WRITE_ADDR_MSB 31 -#define DMA_CH3_WRITE_ADDR_LSB 0 +#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) +#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_WRITE_ADDR_LSB _u(0) #define DMA_CH3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_TRANS_COUNT @@ -1224,27 +1224,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH3_TRANS_COUNT_OFFSET 0x000000c8 -#define DMA_CH3_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH3_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH3_TRANS_COUNT_MSB 31 -#define DMA_CH3_TRANS_COUNT_LSB 0 +#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) +#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_TRANS_COUNT_LSB _u(0) #define DMA_CH3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_CTRL_TRIG // Description : DMA Channel 3 Control and Status -#define DMA_CH3_CTRL_TRIG_OFFSET 0x000000cc -#define DMA_CH3_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH3_CTRL_TRIG_RESET 0x00001800 +#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) +#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_READ_ERROR @@ -1253,10 +1253,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR @@ -1265,10 +1265,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_BUSY @@ -1279,10 +1279,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH3_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH3_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH3_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_SNIFF_EN @@ -1293,10 +1293,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_BSWAP @@ -1304,10 +1304,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH3_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH3_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH3_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET @@ -1318,10 +1318,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_TREQ_SEL @@ -1335,36 +1335,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (3). -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET 0x3 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_RING_SIZE @@ -1377,12 +1377,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1390,10 +1390,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_READ @@ -1402,10 +1402,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_DATA_SIZE @@ -1415,14 +1415,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1435,10 +1435,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_EN @@ -1448,136 +1448,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH3_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH3_CTRL_TRIG_EN_MSB 0 -#define DMA_CH3_CTRL_TRIG_EN_LSB 0 +#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL1_CTRL_OFFSET 0x000000d0 -#define DMA_CH3_AL1_CTRL_BITS 0xffffffff +#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) +#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL1_CTRL_RESET "-" -#define DMA_CH3_AL1_CTRL_MSB 31 -#define DMA_CH3_AL1_CTRL_LSB 0 -#define DMA_CH3_AL1_CTRL_ACCESS "RO" +#define DMA_CH3_AL1_CTRL_MSB _u(31) +#define DMA_CH3_AL1_CTRL_LSB _u(0) +#define DMA_CH3_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_READ_ADDR // Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL1_READ_ADDR_OFFSET 0x000000d4 -#define DMA_CH3_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) +#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL1_READ_ADDR_RESET "-" -#define DMA_CH3_AL1_READ_ADDR_MSB 31 -#define DMA_CH3_AL1_READ_ADDR_LSB 0 -#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL1_WRITE_ADDR_OFFSET 0x000000d8 -#define DMA_CH3_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) +#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH3_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 3 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET 0x000000dc -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL2_CTRL_OFFSET 0x000000e0 -#define DMA_CH3_AL2_CTRL_BITS 0xffffffff +#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) +#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL2_CTRL_RESET "-" -#define DMA_CH3_AL2_CTRL_MSB 31 -#define DMA_CH3_AL2_CTRL_LSB 0 -#define DMA_CH3_AL2_CTRL_ACCESS "RO" +#define DMA_CH3_AL2_CTRL_MSB _u(31) +#define DMA_CH3_AL2_CTRL_LSB _u(0) +#define DMA_CH3_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL2_TRANS_COUNT_OFFSET 0x000000e4 -#define DMA_CH3_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) +#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH3_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH3_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_READ_ADDR // Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL2_READ_ADDR_OFFSET 0x000000e8 -#define DMA_CH3_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) +#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL2_READ_ADDR_RESET "-" -#define DMA_CH3_AL2_READ_ADDR_MSB 31 -#define DMA_CH3_AL2_READ_ADDR_LSB 0 -#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 3 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ec -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL3_CTRL_OFFSET 0x000000f0 -#define DMA_CH3_AL3_CTRL_BITS 0xffffffff +#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) +#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL3_CTRL_RESET "-" -#define DMA_CH3_AL3_CTRL_MSB 31 -#define DMA_CH3_AL3_CTRL_LSB 0 -#define DMA_CH3_AL3_CTRL_ACCESS "RO" +#define DMA_CH3_AL3_CTRL_MSB _u(31) +#define DMA_CH3_AL3_CTRL_LSB _u(0) +#define DMA_CH3_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL3_WRITE_ADDR_OFFSET 0x000000f4 -#define DMA_CH3_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) +#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH3_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL3_TRANS_COUNT_OFFSET 0x000000f8 -#define DMA_CH3_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) +#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH3_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH3_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_READ_ADDR_TRIG // Description : Alias for channel 3 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET 0x000000fc -#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_READ_ADDR // Description : DMA Channel 4 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH4_READ_ADDR_OFFSET 0x00000100 -#define DMA_CH4_READ_ADDR_BITS 0xffffffff -#define DMA_CH4_READ_ADDR_RESET 0x00000000 -#define DMA_CH4_READ_ADDR_MSB 31 -#define DMA_CH4_READ_ADDR_LSB 0 +#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) +#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH4_READ_ADDR_MSB _u(31) +#define DMA_CH4_READ_ADDR_LSB _u(0) #define DMA_CH4_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_WRITE_ADDR @@ -1585,11 +1585,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH4_WRITE_ADDR_OFFSET 0x00000104 -#define DMA_CH4_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH4_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH4_WRITE_ADDR_MSB 31 -#define DMA_CH4_WRITE_ADDR_LSB 0 +#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) +#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH4_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_WRITE_ADDR_LSB _u(0) #define DMA_CH4_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_TRANS_COUNT @@ -1613,27 +1613,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH4_TRANS_COUNT_OFFSET 0x00000108 -#define DMA_CH4_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH4_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH4_TRANS_COUNT_MSB 31 -#define DMA_CH4_TRANS_COUNT_LSB 0 +#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) +#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH4_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_TRANS_COUNT_LSB _u(0) #define DMA_CH4_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_CTRL_TRIG // Description : DMA Channel 4 Control and Status -#define DMA_CH4_CTRL_TRIG_OFFSET 0x0000010c -#define DMA_CH4_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH4_CTRL_TRIG_RESET 0x00002000 +#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) +#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_READ_ERROR @@ -1642,10 +1642,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR @@ -1654,10 +1654,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_BUSY @@ -1668,10 +1668,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH4_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH4_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH4_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_SNIFF_EN @@ -1682,10 +1682,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_BSWAP @@ -1693,10 +1693,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH4_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH4_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH4_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET @@ -1707,10 +1707,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_TREQ_SEL @@ -1724,36 +1724,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (4). -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET 0x4 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_RING_SIZE @@ -1766,12 +1766,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1779,10 +1779,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_READ @@ -1791,10 +1791,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_DATA_SIZE @@ -1804,14 +1804,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1824,10 +1824,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_EN @@ -1837,136 +1837,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH4_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH4_CTRL_TRIG_EN_MSB 0 -#define DMA_CH4_CTRL_TRIG_EN_LSB 0 +#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL1_CTRL_OFFSET 0x00000110 -#define DMA_CH4_AL1_CTRL_BITS 0xffffffff +#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) +#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL1_CTRL_RESET "-" -#define DMA_CH4_AL1_CTRL_MSB 31 -#define DMA_CH4_AL1_CTRL_LSB 0 -#define DMA_CH4_AL1_CTRL_ACCESS "RO" +#define DMA_CH4_AL1_CTRL_MSB _u(31) +#define DMA_CH4_AL1_CTRL_LSB _u(0) +#define DMA_CH4_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_READ_ADDR // Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL1_READ_ADDR_OFFSET 0x00000114 -#define DMA_CH4_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) +#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL1_READ_ADDR_RESET "-" -#define DMA_CH4_AL1_READ_ADDR_MSB 31 -#define DMA_CH4_AL1_READ_ADDR_LSB 0 -#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL1_WRITE_ADDR_OFFSET 0x00000118 -#define DMA_CH4_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) +#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH4_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 4 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000011c -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL2_CTRL_OFFSET 0x00000120 -#define DMA_CH4_AL2_CTRL_BITS 0xffffffff +#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) +#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL2_CTRL_RESET "-" -#define DMA_CH4_AL2_CTRL_MSB 31 -#define DMA_CH4_AL2_CTRL_LSB 0 -#define DMA_CH4_AL2_CTRL_ACCESS "RO" +#define DMA_CH4_AL2_CTRL_MSB _u(31) +#define DMA_CH4_AL2_CTRL_LSB _u(0) +#define DMA_CH4_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL2_TRANS_COUNT_OFFSET 0x00000124 -#define DMA_CH4_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) +#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH4_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH4_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_READ_ADDR // Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL2_READ_ADDR_OFFSET 0x00000128 -#define DMA_CH4_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) +#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL2_READ_ADDR_RESET "-" -#define DMA_CH4_AL2_READ_ADDR_MSB 31 -#define DMA_CH4_AL2_READ_ADDR_LSB 0 -#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 4 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000012c -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL3_CTRL_OFFSET 0x00000130 -#define DMA_CH4_AL3_CTRL_BITS 0xffffffff +#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) +#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL3_CTRL_RESET "-" -#define DMA_CH4_AL3_CTRL_MSB 31 -#define DMA_CH4_AL3_CTRL_LSB 0 -#define DMA_CH4_AL3_CTRL_ACCESS "RO" +#define DMA_CH4_AL3_CTRL_MSB _u(31) +#define DMA_CH4_AL3_CTRL_LSB _u(0) +#define DMA_CH4_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL3_WRITE_ADDR_OFFSET 0x00000134 -#define DMA_CH4_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) +#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH4_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL3_TRANS_COUNT_OFFSET 0x00000138 -#define DMA_CH4_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) +#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH4_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH4_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_READ_ADDR_TRIG // Description : Alias for channel 4 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET 0x0000013c -#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_READ_ADDR // Description : DMA Channel 5 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH5_READ_ADDR_OFFSET 0x00000140 -#define DMA_CH5_READ_ADDR_BITS 0xffffffff -#define DMA_CH5_READ_ADDR_RESET 0x00000000 -#define DMA_CH5_READ_ADDR_MSB 31 -#define DMA_CH5_READ_ADDR_LSB 0 +#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) +#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH5_READ_ADDR_MSB _u(31) +#define DMA_CH5_READ_ADDR_LSB _u(0) #define DMA_CH5_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_WRITE_ADDR @@ -1974,11 +1974,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH5_WRITE_ADDR_OFFSET 0x00000144 -#define DMA_CH5_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH5_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH5_WRITE_ADDR_MSB 31 -#define DMA_CH5_WRITE_ADDR_LSB 0 +#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) +#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH5_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_WRITE_ADDR_LSB _u(0) #define DMA_CH5_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_TRANS_COUNT @@ -2002,27 +2002,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH5_TRANS_COUNT_OFFSET 0x00000148 -#define DMA_CH5_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH5_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH5_TRANS_COUNT_MSB 31 -#define DMA_CH5_TRANS_COUNT_LSB 0 +#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) +#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH5_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_TRANS_COUNT_LSB _u(0) #define DMA_CH5_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_CTRL_TRIG // Description : DMA Channel 5 Control and Status -#define DMA_CH5_CTRL_TRIG_OFFSET 0x0000014c -#define DMA_CH5_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH5_CTRL_TRIG_RESET 0x00002800 +#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) +#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_READ_ERROR @@ -2031,10 +2031,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR @@ -2043,10 +2043,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_BUSY @@ -2057,10 +2057,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH5_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH5_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH5_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_SNIFF_EN @@ -2071,10 +2071,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_BSWAP @@ -2082,10 +2082,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH5_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH5_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH5_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET @@ -2096,10 +2096,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_TREQ_SEL @@ -2113,36 +2113,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (5). -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET 0x5 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_RING_SIZE @@ -2155,12 +2155,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2168,10 +2168,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_READ @@ -2180,10 +2180,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_DATA_SIZE @@ -2193,14 +2193,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2213,10 +2213,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_EN @@ -2226,136 +2226,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH5_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH5_CTRL_TRIG_EN_MSB 0 -#define DMA_CH5_CTRL_TRIG_EN_LSB 0 +#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL1_CTRL_OFFSET 0x00000150 -#define DMA_CH5_AL1_CTRL_BITS 0xffffffff +#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) +#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL1_CTRL_RESET "-" -#define DMA_CH5_AL1_CTRL_MSB 31 -#define DMA_CH5_AL1_CTRL_LSB 0 -#define DMA_CH5_AL1_CTRL_ACCESS "RO" +#define DMA_CH5_AL1_CTRL_MSB _u(31) +#define DMA_CH5_AL1_CTRL_LSB _u(0) +#define DMA_CH5_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_READ_ADDR // Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL1_READ_ADDR_OFFSET 0x00000154 -#define DMA_CH5_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) +#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL1_READ_ADDR_RESET "-" -#define DMA_CH5_AL1_READ_ADDR_MSB 31 -#define DMA_CH5_AL1_READ_ADDR_LSB 0 -#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL1_WRITE_ADDR_OFFSET 0x00000158 -#define DMA_CH5_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) +#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH5_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 5 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000015c -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL2_CTRL_OFFSET 0x00000160 -#define DMA_CH5_AL2_CTRL_BITS 0xffffffff +#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) +#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL2_CTRL_RESET "-" -#define DMA_CH5_AL2_CTRL_MSB 31 -#define DMA_CH5_AL2_CTRL_LSB 0 -#define DMA_CH5_AL2_CTRL_ACCESS "RO" +#define DMA_CH5_AL2_CTRL_MSB _u(31) +#define DMA_CH5_AL2_CTRL_LSB _u(0) +#define DMA_CH5_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL2_TRANS_COUNT_OFFSET 0x00000164 -#define DMA_CH5_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) +#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH5_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH5_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_READ_ADDR // Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL2_READ_ADDR_OFFSET 0x00000168 -#define DMA_CH5_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) +#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL2_READ_ADDR_RESET "-" -#define DMA_CH5_AL2_READ_ADDR_MSB 31 -#define DMA_CH5_AL2_READ_ADDR_LSB 0 -#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 5 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000016c -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL3_CTRL_OFFSET 0x00000170 -#define DMA_CH5_AL3_CTRL_BITS 0xffffffff +#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) +#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL3_CTRL_RESET "-" -#define DMA_CH5_AL3_CTRL_MSB 31 -#define DMA_CH5_AL3_CTRL_LSB 0 -#define DMA_CH5_AL3_CTRL_ACCESS "RO" +#define DMA_CH5_AL3_CTRL_MSB _u(31) +#define DMA_CH5_AL3_CTRL_LSB _u(0) +#define DMA_CH5_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL3_WRITE_ADDR_OFFSET 0x00000174 -#define DMA_CH5_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) +#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH5_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL3_TRANS_COUNT_OFFSET 0x00000178 -#define DMA_CH5_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) +#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH5_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH5_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_READ_ADDR_TRIG // Description : Alias for channel 5 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET 0x0000017c -#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_READ_ADDR // Description : DMA Channel 6 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH6_READ_ADDR_OFFSET 0x00000180 -#define DMA_CH6_READ_ADDR_BITS 0xffffffff -#define DMA_CH6_READ_ADDR_RESET 0x00000000 -#define DMA_CH6_READ_ADDR_MSB 31 -#define DMA_CH6_READ_ADDR_LSB 0 +#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) +#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH6_READ_ADDR_MSB _u(31) +#define DMA_CH6_READ_ADDR_LSB _u(0) #define DMA_CH6_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_WRITE_ADDR @@ -2363,11 +2363,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH6_WRITE_ADDR_OFFSET 0x00000184 -#define DMA_CH6_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH6_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH6_WRITE_ADDR_MSB 31 -#define DMA_CH6_WRITE_ADDR_LSB 0 +#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) +#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH6_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_WRITE_ADDR_LSB _u(0) #define DMA_CH6_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_TRANS_COUNT @@ -2391,27 +2391,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH6_TRANS_COUNT_OFFSET 0x00000188 -#define DMA_CH6_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH6_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH6_TRANS_COUNT_MSB 31 -#define DMA_CH6_TRANS_COUNT_LSB 0 +#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) +#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH6_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_TRANS_COUNT_LSB _u(0) #define DMA_CH6_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_CTRL_TRIG // Description : DMA Channel 6 Control and Status -#define DMA_CH6_CTRL_TRIG_OFFSET 0x0000018c -#define DMA_CH6_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH6_CTRL_TRIG_RESET 0x00003000 +#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) +#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_READ_ERROR @@ -2420,10 +2420,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR @@ -2432,10 +2432,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_BUSY @@ -2446,10 +2446,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH6_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH6_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH6_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_SNIFF_EN @@ -2460,10 +2460,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_BSWAP @@ -2471,10 +2471,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH6_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH6_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH6_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET @@ -2485,10 +2485,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_TREQ_SEL @@ -2502,36 +2502,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (6). -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET 0x6 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_RING_SIZE @@ -2544,12 +2544,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2557,10 +2557,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_READ @@ -2569,10 +2569,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_DATA_SIZE @@ -2582,14 +2582,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2602,10 +2602,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_EN @@ -2615,136 +2615,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH6_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH6_CTRL_TRIG_EN_MSB 0 -#define DMA_CH6_CTRL_TRIG_EN_LSB 0 +#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL1_CTRL_OFFSET 0x00000190 -#define DMA_CH6_AL1_CTRL_BITS 0xffffffff +#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) +#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL1_CTRL_RESET "-" -#define DMA_CH6_AL1_CTRL_MSB 31 -#define DMA_CH6_AL1_CTRL_LSB 0 -#define DMA_CH6_AL1_CTRL_ACCESS "RO" +#define DMA_CH6_AL1_CTRL_MSB _u(31) +#define DMA_CH6_AL1_CTRL_LSB _u(0) +#define DMA_CH6_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_READ_ADDR // Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL1_READ_ADDR_OFFSET 0x00000194 -#define DMA_CH6_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) +#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL1_READ_ADDR_RESET "-" -#define DMA_CH6_AL1_READ_ADDR_MSB 31 -#define DMA_CH6_AL1_READ_ADDR_LSB 0 -#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL1_WRITE_ADDR_OFFSET 0x00000198 -#define DMA_CH6_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) +#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH6_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 6 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000019c -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL2_CTRL_OFFSET 0x000001a0 -#define DMA_CH6_AL2_CTRL_BITS 0xffffffff +#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) +#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL2_CTRL_RESET "-" -#define DMA_CH6_AL2_CTRL_MSB 31 -#define DMA_CH6_AL2_CTRL_LSB 0 -#define DMA_CH6_AL2_CTRL_ACCESS "RO" +#define DMA_CH6_AL2_CTRL_MSB _u(31) +#define DMA_CH6_AL2_CTRL_LSB _u(0) +#define DMA_CH6_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL2_TRANS_COUNT_OFFSET 0x000001a4 -#define DMA_CH6_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) +#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH6_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH6_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_READ_ADDR // Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL2_READ_ADDR_OFFSET 0x000001a8 -#define DMA_CH6_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) +#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL2_READ_ADDR_RESET "-" -#define DMA_CH6_AL2_READ_ADDR_MSB 31 -#define DMA_CH6_AL2_READ_ADDR_LSB 0 -#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 6 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ac -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL3_CTRL_OFFSET 0x000001b0 -#define DMA_CH6_AL3_CTRL_BITS 0xffffffff +#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) +#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL3_CTRL_RESET "-" -#define DMA_CH6_AL3_CTRL_MSB 31 -#define DMA_CH6_AL3_CTRL_LSB 0 -#define DMA_CH6_AL3_CTRL_ACCESS "RO" +#define DMA_CH6_AL3_CTRL_MSB _u(31) +#define DMA_CH6_AL3_CTRL_LSB _u(0) +#define DMA_CH6_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL3_WRITE_ADDR_OFFSET 0x000001b4 -#define DMA_CH6_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) +#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH6_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL3_TRANS_COUNT_OFFSET 0x000001b8 -#define DMA_CH6_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) +#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH6_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH6_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_READ_ADDR_TRIG // Description : Alias for channel 6 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET 0x000001bc -#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_READ_ADDR // Description : DMA Channel 7 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH7_READ_ADDR_OFFSET 0x000001c0 -#define DMA_CH7_READ_ADDR_BITS 0xffffffff -#define DMA_CH7_READ_ADDR_RESET 0x00000000 -#define DMA_CH7_READ_ADDR_MSB 31 -#define DMA_CH7_READ_ADDR_LSB 0 +#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) +#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH7_READ_ADDR_MSB _u(31) +#define DMA_CH7_READ_ADDR_LSB _u(0) #define DMA_CH7_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_WRITE_ADDR @@ -2752,11 +2752,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH7_WRITE_ADDR_OFFSET 0x000001c4 -#define DMA_CH7_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH7_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH7_WRITE_ADDR_MSB 31 -#define DMA_CH7_WRITE_ADDR_LSB 0 +#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) +#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH7_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_WRITE_ADDR_LSB _u(0) #define DMA_CH7_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_TRANS_COUNT @@ -2780,27 +2780,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH7_TRANS_COUNT_OFFSET 0x000001c8 -#define DMA_CH7_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH7_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH7_TRANS_COUNT_MSB 31 -#define DMA_CH7_TRANS_COUNT_LSB 0 +#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) +#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH7_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_TRANS_COUNT_LSB _u(0) #define DMA_CH7_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_CTRL_TRIG // Description : DMA Channel 7 Control and Status -#define DMA_CH7_CTRL_TRIG_OFFSET 0x000001cc -#define DMA_CH7_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH7_CTRL_TRIG_RESET 0x00003800 +#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) +#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_READ_ERROR @@ -2809,10 +2809,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR @@ -2821,10 +2821,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_BUSY @@ -2835,10 +2835,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH7_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH7_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH7_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_SNIFF_EN @@ -2849,10 +2849,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_BSWAP @@ -2860,10 +2860,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH7_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH7_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH7_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET @@ -2874,10 +2874,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_TREQ_SEL @@ -2891,36 +2891,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (7). -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET 0x7 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_RING_SIZE @@ -2933,12 +2933,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2946,10 +2946,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_READ @@ -2958,10 +2958,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_DATA_SIZE @@ -2971,14 +2971,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2991,10 +2991,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_EN @@ -3004,136 +3004,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH7_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH7_CTRL_TRIG_EN_MSB 0 -#define DMA_CH7_CTRL_TRIG_EN_LSB 0 +#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL1_CTRL_OFFSET 0x000001d0 -#define DMA_CH7_AL1_CTRL_BITS 0xffffffff +#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) +#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL1_CTRL_RESET "-" -#define DMA_CH7_AL1_CTRL_MSB 31 -#define DMA_CH7_AL1_CTRL_LSB 0 -#define DMA_CH7_AL1_CTRL_ACCESS "RO" +#define DMA_CH7_AL1_CTRL_MSB _u(31) +#define DMA_CH7_AL1_CTRL_LSB _u(0) +#define DMA_CH7_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_READ_ADDR // Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL1_READ_ADDR_OFFSET 0x000001d4 -#define DMA_CH7_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) +#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL1_READ_ADDR_RESET "-" -#define DMA_CH7_AL1_READ_ADDR_MSB 31 -#define DMA_CH7_AL1_READ_ADDR_LSB 0 -#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL1_WRITE_ADDR_OFFSET 0x000001d8 -#define DMA_CH7_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) +#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH7_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 7 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET 0x000001dc -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL2_CTRL_OFFSET 0x000001e0 -#define DMA_CH7_AL2_CTRL_BITS 0xffffffff +#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) +#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL2_CTRL_RESET "-" -#define DMA_CH7_AL2_CTRL_MSB 31 -#define DMA_CH7_AL2_CTRL_LSB 0 -#define DMA_CH7_AL2_CTRL_ACCESS "RO" +#define DMA_CH7_AL2_CTRL_MSB _u(31) +#define DMA_CH7_AL2_CTRL_LSB _u(0) +#define DMA_CH7_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL2_TRANS_COUNT_OFFSET 0x000001e4 -#define DMA_CH7_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) +#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH7_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH7_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_READ_ADDR // Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL2_READ_ADDR_OFFSET 0x000001e8 -#define DMA_CH7_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) +#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL2_READ_ADDR_RESET "-" -#define DMA_CH7_AL2_READ_ADDR_MSB 31 -#define DMA_CH7_AL2_READ_ADDR_LSB 0 -#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 7 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ec -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL3_CTRL_OFFSET 0x000001f0 -#define DMA_CH7_AL3_CTRL_BITS 0xffffffff +#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) +#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL3_CTRL_RESET "-" -#define DMA_CH7_AL3_CTRL_MSB 31 -#define DMA_CH7_AL3_CTRL_LSB 0 -#define DMA_CH7_AL3_CTRL_ACCESS "RO" +#define DMA_CH7_AL3_CTRL_MSB _u(31) +#define DMA_CH7_AL3_CTRL_LSB _u(0) +#define DMA_CH7_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL3_WRITE_ADDR_OFFSET 0x000001f4 -#define DMA_CH7_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) +#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH7_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL3_TRANS_COUNT_OFFSET 0x000001f8 -#define DMA_CH7_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) +#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH7_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH7_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_READ_ADDR_TRIG // Description : Alias for channel 7 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET 0x000001fc -#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_READ_ADDR // Description : DMA Channel 8 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH8_READ_ADDR_OFFSET 0x00000200 -#define DMA_CH8_READ_ADDR_BITS 0xffffffff -#define DMA_CH8_READ_ADDR_RESET 0x00000000 -#define DMA_CH8_READ_ADDR_MSB 31 -#define DMA_CH8_READ_ADDR_LSB 0 +#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) +#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH8_READ_ADDR_MSB _u(31) +#define DMA_CH8_READ_ADDR_LSB _u(0) #define DMA_CH8_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_WRITE_ADDR @@ -3141,11 +3141,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH8_WRITE_ADDR_OFFSET 0x00000204 -#define DMA_CH8_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH8_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH8_WRITE_ADDR_MSB 31 -#define DMA_CH8_WRITE_ADDR_LSB 0 +#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) +#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH8_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_WRITE_ADDR_LSB _u(0) #define DMA_CH8_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_TRANS_COUNT @@ -3169,27 +3169,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH8_TRANS_COUNT_OFFSET 0x00000208 -#define DMA_CH8_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH8_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH8_TRANS_COUNT_MSB 31 -#define DMA_CH8_TRANS_COUNT_LSB 0 +#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) +#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH8_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_TRANS_COUNT_LSB _u(0) #define DMA_CH8_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_CTRL_TRIG // Description : DMA Channel 8 Control and Status -#define DMA_CH8_CTRL_TRIG_OFFSET 0x0000020c -#define DMA_CH8_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH8_CTRL_TRIG_RESET 0x00004000 +#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) +#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_READ_ERROR @@ -3198,10 +3198,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR @@ -3210,10 +3210,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_BUSY @@ -3224,10 +3224,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH8_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH8_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH8_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_SNIFF_EN @@ -3238,10 +3238,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_BSWAP @@ -3249,10 +3249,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH8_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH8_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH8_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET @@ -3263,10 +3263,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_TREQ_SEL @@ -3280,36 +3280,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (8). -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET 0x8 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_RING_SIZE @@ -3322,12 +3322,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -3335,10 +3335,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_READ @@ -3347,10 +3347,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_DATA_SIZE @@ -3360,14 +3360,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3380,10 +3380,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_EN @@ -3393,136 +3393,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH8_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH8_CTRL_TRIG_EN_MSB 0 -#define DMA_CH8_CTRL_TRIG_EN_LSB 0 +#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL1_CTRL_OFFSET 0x00000210 -#define DMA_CH8_AL1_CTRL_BITS 0xffffffff +#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) +#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL1_CTRL_RESET "-" -#define DMA_CH8_AL1_CTRL_MSB 31 -#define DMA_CH8_AL1_CTRL_LSB 0 -#define DMA_CH8_AL1_CTRL_ACCESS "RO" +#define DMA_CH8_AL1_CTRL_MSB _u(31) +#define DMA_CH8_AL1_CTRL_LSB _u(0) +#define DMA_CH8_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_READ_ADDR // Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL1_READ_ADDR_OFFSET 0x00000214 -#define DMA_CH8_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) +#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL1_READ_ADDR_RESET "-" -#define DMA_CH8_AL1_READ_ADDR_MSB 31 -#define DMA_CH8_AL1_READ_ADDR_LSB 0 -#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL1_WRITE_ADDR_OFFSET 0x00000218 -#define DMA_CH8_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) +#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH8_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 8 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000021c -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL2_CTRL_OFFSET 0x00000220 -#define DMA_CH8_AL2_CTRL_BITS 0xffffffff +#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) +#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL2_CTRL_RESET "-" -#define DMA_CH8_AL2_CTRL_MSB 31 -#define DMA_CH8_AL2_CTRL_LSB 0 -#define DMA_CH8_AL2_CTRL_ACCESS "RO" +#define DMA_CH8_AL2_CTRL_MSB _u(31) +#define DMA_CH8_AL2_CTRL_LSB _u(0) +#define DMA_CH8_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL2_TRANS_COUNT_OFFSET 0x00000224 -#define DMA_CH8_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) +#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH8_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH8_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_READ_ADDR // Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL2_READ_ADDR_OFFSET 0x00000228 -#define DMA_CH8_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) +#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL2_READ_ADDR_RESET "-" -#define DMA_CH8_AL2_READ_ADDR_MSB 31 -#define DMA_CH8_AL2_READ_ADDR_LSB 0 -#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 8 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000022c -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL3_CTRL_OFFSET 0x00000230 -#define DMA_CH8_AL3_CTRL_BITS 0xffffffff +#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) +#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL3_CTRL_RESET "-" -#define DMA_CH8_AL3_CTRL_MSB 31 -#define DMA_CH8_AL3_CTRL_LSB 0 -#define DMA_CH8_AL3_CTRL_ACCESS "RO" +#define DMA_CH8_AL3_CTRL_MSB _u(31) +#define DMA_CH8_AL3_CTRL_LSB _u(0) +#define DMA_CH8_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL3_WRITE_ADDR_OFFSET 0x00000234 -#define DMA_CH8_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) +#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH8_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL3_TRANS_COUNT_OFFSET 0x00000238 -#define DMA_CH8_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) +#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH8_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH8_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_READ_ADDR_TRIG // Description : Alias for channel 8 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET 0x0000023c -#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_READ_ADDR // Description : DMA Channel 9 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH9_READ_ADDR_OFFSET 0x00000240 -#define DMA_CH9_READ_ADDR_BITS 0xffffffff -#define DMA_CH9_READ_ADDR_RESET 0x00000000 -#define DMA_CH9_READ_ADDR_MSB 31 -#define DMA_CH9_READ_ADDR_LSB 0 +#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) +#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH9_READ_ADDR_MSB _u(31) +#define DMA_CH9_READ_ADDR_LSB _u(0) #define DMA_CH9_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_WRITE_ADDR @@ -3530,11 +3530,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH9_WRITE_ADDR_OFFSET 0x00000244 -#define DMA_CH9_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH9_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH9_WRITE_ADDR_MSB 31 -#define DMA_CH9_WRITE_ADDR_LSB 0 +#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) +#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH9_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_WRITE_ADDR_LSB _u(0) #define DMA_CH9_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_TRANS_COUNT @@ -3558,27 +3558,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH9_TRANS_COUNT_OFFSET 0x00000248 -#define DMA_CH9_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH9_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH9_TRANS_COUNT_MSB 31 -#define DMA_CH9_TRANS_COUNT_LSB 0 +#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) +#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH9_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_TRANS_COUNT_LSB _u(0) #define DMA_CH9_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_CTRL_TRIG // Description : DMA Channel 9 Control and Status -#define DMA_CH9_CTRL_TRIG_OFFSET 0x0000024c -#define DMA_CH9_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH9_CTRL_TRIG_RESET 0x00004800 +#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) +#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_READ_ERROR @@ -3587,10 +3587,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR @@ -3599,10 +3599,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_BUSY @@ -3613,10 +3613,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH9_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH9_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH9_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_SNIFF_EN @@ -3627,10 +3627,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_BSWAP @@ -3638,10 +3638,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH9_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH9_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH9_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET @@ -3652,10 +3652,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_TREQ_SEL @@ -3669,36 +3669,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (9). -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET 0x9 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_RING_SIZE @@ -3711,12 +3711,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -3724,10 +3724,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_READ @@ -3736,10 +3736,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_DATA_SIZE @@ -3749,14 +3749,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3769,10 +3769,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_EN @@ -3782,136 +3782,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH9_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH9_CTRL_TRIG_EN_MSB 0 -#define DMA_CH9_CTRL_TRIG_EN_LSB 0 +#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL1_CTRL_OFFSET 0x00000250 -#define DMA_CH9_AL1_CTRL_BITS 0xffffffff +#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) +#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL1_CTRL_RESET "-" -#define DMA_CH9_AL1_CTRL_MSB 31 -#define DMA_CH9_AL1_CTRL_LSB 0 -#define DMA_CH9_AL1_CTRL_ACCESS "RO" +#define DMA_CH9_AL1_CTRL_MSB _u(31) +#define DMA_CH9_AL1_CTRL_LSB _u(0) +#define DMA_CH9_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_READ_ADDR // Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL1_READ_ADDR_OFFSET 0x00000254 -#define DMA_CH9_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) +#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL1_READ_ADDR_RESET "-" -#define DMA_CH9_AL1_READ_ADDR_MSB 31 -#define DMA_CH9_AL1_READ_ADDR_LSB 0 -#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL1_WRITE_ADDR_OFFSET 0x00000258 -#define DMA_CH9_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) +#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH9_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 9 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000025c -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL2_CTRL_OFFSET 0x00000260 -#define DMA_CH9_AL2_CTRL_BITS 0xffffffff +#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) +#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL2_CTRL_RESET "-" -#define DMA_CH9_AL2_CTRL_MSB 31 -#define DMA_CH9_AL2_CTRL_LSB 0 -#define DMA_CH9_AL2_CTRL_ACCESS "RO" +#define DMA_CH9_AL2_CTRL_MSB _u(31) +#define DMA_CH9_AL2_CTRL_LSB _u(0) +#define DMA_CH9_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL2_TRANS_COUNT_OFFSET 0x00000264 -#define DMA_CH9_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) +#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH9_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH9_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_READ_ADDR // Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL2_READ_ADDR_OFFSET 0x00000268 -#define DMA_CH9_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) +#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL2_READ_ADDR_RESET "-" -#define DMA_CH9_AL2_READ_ADDR_MSB 31 -#define DMA_CH9_AL2_READ_ADDR_LSB 0 -#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 9 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000026c -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL3_CTRL_OFFSET 0x00000270 -#define DMA_CH9_AL3_CTRL_BITS 0xffffffff +#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) +#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL3_CTRL_RESET "-" -#define DMA_CH9_AL3_CTRL_MSB 31 -#define DMA_CH9_AL3_CTRL_LSB 0 -#define DMA_CH9_AL3_CTRL_ACCESS "RO" +#define DMA_CH9_AL3_CTRL_MSB _u(31) +#define DMA_CH9_AL3_CTRL_LSB _u(0) +#define DMA_CH9_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL3_WRITE_ADDR_OFFSET 0x00000274 -#define DMA_CH9_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) +#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH9_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL3_TRANS_COUNT_OFFSET 0x00000278 -#define DMA_CH9_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) +#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH9_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH9_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_READ_ADDR_TRIG // Description : Alias for channel 9 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET 0x0000027c -#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_READ_ADDR // Description : DMA Channel 10 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH10_READ_ADDR_OFFSET 0x00000280 -#define DMA_CH10_READ_ADDR_BITS 0xffffffff -#define DMA_CH10_READ_ADDR_RESET 0x00000000 -#define DMA_CH10_READ_ADDR_MSB 31 -#define DMA_CH10_READ_ADDR_LSB 0 +#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) +#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH10_READ_ADDR_MSB _u(31) +#define DMA_CH10_READ_ADDR_LSB _u(0) #define DMA_CH10_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_WRITE_ADDR @@ -3919,11 +3919,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH10_WRITE_ADDR_OFFSET 0x00000284 -#define DMA_CH10_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH10_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH10_WRITE_ADDR_MSB 31 -#define DMA_CH10_WRITE_ADDR_LSB 0 +#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) +#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH10_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_WRITE_ADDR_LSB _u(0) #define DMA_CH10_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_TRANS_COUNT @@ -3947,27 +3947,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH10_TRANS_COUNT_OFFSET 0x00000288 -#define DMA_CH10_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH10_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH10_TRANS_COUNT_MSB 31 -#define DMA_CH10_TRANS_COUNT_LSB 0 +#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) +#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH10_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_TRANS_COUNT_LSB _u(0) #define DMA_CH10_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_CTRL_TRIG // Description : DMA Channel 10 Control and Status -#define DMA_CH10_CTRL_TRIG_OFFSET 0x0000028c -#define DMA_CH10_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH10_CTRL_TRIG_RESET 0x00005000 +#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) +#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_READ_ERROR @@ -3976,10 +3976,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR @@ -3988,10 +3988,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_BUSY @@ -4002,10 +4002,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH10_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH10_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH10_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_SNIFF_EN @@ -4016,10 +4016,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_BSWAP @@ -4027,10 +4027,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH10_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH10_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH10_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET @@ -4041,10 +4041,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_TREQ_SEL @@ -4058,36 +4058,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (10). -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET 0xa -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_RING_SIZE @@ -4100,12 +4100,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -4113,10 +4113,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_READ @@ -4125,10 +4125,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_DATA_SIZE @@ -4138,14 +4138,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4158,10 +4158,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_EN @@ -4171,136 +4171,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH10_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH10_CTRL_TRIG_EN_MSB 0 -#define DMA_CH10_CTRL_TRIG_EN_LSB 0 +#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL1_CTRL_OFFSET 0x00000290 -#define DMA_CH10_AL1_CTRL_BITS 0xffffffff +#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) +#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL1_CTRL_RESET "-" -#define DMA_CH10_AL1_CTRL_MSB 31 -#define DMA_CH10_AL1_CTRL_LSB 0 -#define DMA_CH10_AL1_CTRL_ACCESS "RO" +#define DMA_CH10_AL1_CTRL_MSB _u(31) +#define DMA_CH10_AL1_CTRL_LSB _u(0) +#define DMA_CH10_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_READ_ADDR // Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL1_READ_ADDR_OFFSET 0x00000294 -#define DMA_CH10_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) +#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL1_READ_ADDR_RESET "-" -#define DMA_CH10_AL1_READ_ADDR_MSB 31 -#define DMA_CH10_AL1_READ_ADDR_LSB 0 -#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL1_WRITE_ADDR_OFFSET 0x00000298 -#define DMA_CH10_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) +#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH10_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 10 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000029c -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL2_CTRL_OFFSET 0x000002a0 -#define DMA_CH10_AL2_CTRL_BITS 0xffffffff +#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) +#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL2_CTRL_RESET "-" -#define DMA_CH10_AL2_CTRL_MSB 31 -#define DMA_CH10_AL2_CTRL_LSB 0 -#define DMA_CH10_AL2_CTRL_ACCESS "RO" +#define DMA_CH10_AL2_CTRL_MSB _u(31) +#define DMA_CH10_AL2_CTRL_LSB _u(0) +#define DMA_CH10_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL2_TRANS_COUNT_OFFSET 0x000002a4 -#define DMA_CH10_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) +#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH10_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH10_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_READ_ADDR // Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL2_READ_ADDR_OFFSET 0x000002a8 -#define DMA_CH10_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) +#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL2_READ_ADDR_RESET "-" -#define DMA_CH10_AL2_READ_ADDR_MSB 31 -#define DMA_CH10_AL2_READ_ADDR_LSB 0 -#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 10 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ac -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL3_CTRL_OFFSET 0x000002b0 -#define DMA_CH10_AL3_CTRL_BITS 0xffffffff +#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) +#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL3_CTRL_RESET "-" -#define DMA_CH10_AL3_CTRL_MSB 31 -#define DMA_CH10_AL3_CTRL_LSB 0 -#define DMA_CH10_AL3_CTRL_ACCESS "RO" +#define DMA_CH10_AL3_CTRL_MSB _u(31) +#define DMA_CH10_AL3_CTRL_LSB _u(0) +#define DMA_CH10_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL3_WRITE_ADDR_OFFSET 0x000002b4 -#define DMA_CH10_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) +#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH10_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL3_TRANS_COUNT_OFFSET 0x000002b8 -#define DMA_CH10_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) +#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH10_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH10_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_READ_ADDR_TRIG // Description : Alias for channel 10 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET 0x000002bc -#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_READ_ADDR // Description : DMA Channel 11 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH11_READ_ADDR_OFFSET 0x000002c0 -#define DMA_CH11_READ_ADDR_BITS 0xffffffff -#define DMA_CH11_READ_ADDR_RESET 0x00000000 -#define DMA_CH11_READ_ADDR_MSB 31 -#define DMA_CH11_READ_ADDR_LSB 0 +#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) +#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH11_READ_ADDR_MSB _u(31) +#define DMA_CH11_READ_ADDR_LSB _u(0) #define DMA_CH11_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_WRITE_ADDR @@ -4308,11 +4308,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH11_WRITE_ADDR_OFFSET 0x000002c4 -#define DMA_CH11_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH11_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH11_WRITE_ADDR_MSB 31 -#define DMA_CH11_WRITE_ADDR_LSB 0 +#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) +#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH11_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_WRITE_ADDR_LSB _u(0) #define DMA_CH11_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_TRANS_COUNT @@ -4336,27 +4336,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH11_TRANS_COUNT_OFFSET 0x000002c8 -#define DMA_CH11_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH11_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH11_TRANS_COUNT_MSB 31 -#define DMA_CH11_TRANS_COUNT_LSB 0 +#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) +#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH11_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_TRANS_COUNT_LSB _u(0) #define DMA_CH11_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_CTRL_TRIG // Description : DMA Channel 11 Control and Status -#define DMA_CH11_CTRL_TRIG_OFFSET 0x000002cc -#define DMA_CH11_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH11_CTRL_TRIG_RESET 0x00005800 +#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) +#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_READ_ERROR @@ -4365,10 +4365,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR @@ -4377,10 +4377,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_BUSY @@ -4391,10 +4391,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH11_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH11_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH11_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_SNIFF_EN @@ -4405,10 +4405,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_BSWAP @@ -4416,10 +4416,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH11_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH11_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH11_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET @@ -4430,10 +4430,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_TREQ_SEL @@ -4447,36 +4447,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (11). -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET 0xb -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_RING_SIZE @@ -4489,12 +4489,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -4502,10 +4502,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_READ @@ -4514,10 +4514,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_DATA_SIZE @@ -4527,14 +4527,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4547,10 +4547,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_EN @@ -4560,125 +4560,125 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH11_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH11_CTRL_TRIG_EN_MSB 0 -#define DMA_CH11_CTRL_TRIG_EN_LSB 0 +#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL1_CTRL_OFFSET 0x000002d0 -#define DMA_CH11_AL1_CTRL_BITS 0xffffffff +#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) +#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL1_CTRL_RESET "-" -#define DMA_CH11_AL1_CTRL_MSB 31 -#define DMA_CH11_AL1_CTRL_LSB 0 -#define DMA_CH11_AL1_CTRL_ACCESS "RO" +#define DMA_CH11_AL1_CTRL_MSB _u(31) +#define DMA_CH11_AL1_CTRL_LSB _u(0) +#define DMA_CH11_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_READ_ADDR // Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL1_READ_ADDR_OFFSET 0x000002d4 -#define DMA_CH11_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) +#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL1_READ_ADDR_RESET "-" -#define DMA_CH11_AL1_READ_ADDR_MSB 31 -#define DMA_CH11_AL1_READ_ADDR_LSB 0 -#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL1_WRITE_ADDR_OFFSET 0x000002d8 -#define DMA_CH11_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) +#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH11_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 11 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET 0x000002dc -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL2_CTRL_OFFSET 0x000002e0 -#define DMA_CH11_AL2_CTRL_BITS 0xffffffff +#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) +#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL2_CTRL_RESET "-" -#define DMA_CH11_AL2_CTRL_MSB 31 -#define DMA_CH11_AL2_CTRL_LSB 0 -#define DMA_CH11_AL2_CTRL_ACCESS "RO" +#define DMA_CH11_AL2_CTRL_MSB _u(31) +#define DMA_CH11_AL2_CTRL_LSB _u(0) +#define DMA_CH11_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL2_TRANS_COUNT_OFFSET 0x000002e4 -#define DMA_CH11_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) +#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH11_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH11_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_READ_ADDR // Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL2_READ_ADDR_OFFSET 0x000002e8 -#define DMA_CH11_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) +#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL2_READ_ADDR_RESET "-" -#define DMA_CH11_AL2_READ_ADDR_MSB 31 -#define DMA_CH11_AL2_READ_ADDR_LSB 0 -#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 11 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ec -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL3_CTRL_OFFSET 0x000002f0 -#define DMA_CH11_AL3_CTRL_BITS 0xffffffff +#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) +#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL3_CTRL_RESET "-" -#define DMA_CH11_AL3_CTRL_MSB 31 -#define DMA_CH11_AL3_CTRL_LSB 0 -#define DMA_CH11_AL3_CTRL_ACCESS "RO" +#define DMA_CH11_AL3_CTRL_MSB _u(31) +#define DMA_CH11_AL3_CTRL_LSB _u(0) +#define DMA_CH11_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL3_WRITE_ADDR_OFFSET 0x000002f4 -#define DMA_CH11_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) +#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH11_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL3_TRANS_COUNT_OFFSET 0x000002f8 -#define DMA_CH11_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) +#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH11_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH11_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_READ_ADDR_TRIG // Description : Alias for channel 11 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET 0x000002fc -#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_INTR // Description : Interrupt Status (raw) @@ -4697,32 +4697,32 @@ // // It is also valid to ignore this behaviour and just use // INTE0/INTS0/IRQ 0. -#define DMA_INTR_OFFSET 0x00000400 -#define DMA_INTR_BITS 0x0000ffff -#define DMA_INTR_RESET 0x00000000 -#define DMA_INTR_MSB 15 -#define DMA_INTR_LSB 0 +#define DMA_INTR_OFFSET _u(0x00000400) +#define DMA_INTR_BITS _u(0x0000ffff) +#define DMA_INTR_RESET _u(0x00000000) +#define DMA_INTR_MSB _u(15) +#define DMA_INTR_LSB _u(0) #define DMA_INTR_ACCESS "RO" // ============================================================================= // Register : DMA_INTE0 // Description : Interrupt Enables for IRQ 0 // Set bit n to pass interrupts from channel n to DMA IRQ 0. -#define DMA_INTE0_OFFSET 0x00000404 -#define DMA_INTE0_BITS 0x0000ffff -#define DMA_INTE0_RESET 0x00000000 -#define DMA_INTE0_MSB 15 -#define DMA_INTE0_LSB 0 +#define DMA_INTE0_OFFSET _u(0x00000404) +#define DMA_INTE0_BITS _u(0x0000ffff) +#define DMA_INTE0_RESET _u(0x00000000) +#define DMA_INTE0_MSB _u(15) +#define DMA_INTE0_LSB _u(0) #define DMA_INTE0_ACCESS "RW" // ============================================================================= // Register : DMA_INTF0 // Description : Force Interrupts // Write 1s to force the corresponding bits in INTE0. The // interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF0_OFFSET 0x00000408 -#define DMA_INTF0_BITS 0x0000ffff -#define DMA_INTF0_RESET 0x00000000 -#define DMA_INTF0_MSB 15 -#define DMA_INTF0_LSB 0 +#define DMA_INTF0_OFFSET _u(0x00000408) +#define DMA_INTF0_BITS _u(0x0000ffff) +#define DMA_INTF0_RESET _u(0x00000000) +#define DMA_INTF0_MSB _u(15) +#define DMA_INTF0_LSB _u(0) #define DMA_INTF0_ACCESS "RW" // ============================================================================= // Register : DMA_INTS0 @@ -4730,32 +4730,32 @@ // Indicates active channel interrupt requests which are currently // causing IRQ 0 to be asserted. // Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS0_OFFSET 0x0000040c -#define DMA_INTS0_BITS 0x0000ffff -#define DMA_INTS0_RESET 0x00000000 -#define DMA_INTS0_MSB 15 -#define DMA_INTS0_LSB 0 +#define DMA_INTS0_OFFSET _u(0x0000040c) +#define DMA_INTS0_BITS _u(0x0000ffff) +#define DMA_INTS0_RESET _u(0x00000000) +#define DMA_INTS0_MSB _u(15) +#define DMA_INTS0_LSB _u(0) #define DMA_INTS0_ACCESS "WC" // ============================================================================= // Register : DMA_INTE1 // Description : Interrupt Enables for IRQ 1 // Set bit n to pass interrupts from channel n to DMA IRQ 1. -#define DMA_INTE1_OFFSET 0x00000414 -#define DMA_INTE1_BITS 0x0000ffff -#define DMA_INTE1_RESET 0x00000000 -#define DMA_INTE1_MSB 15 -#define DMA_INTE1_LSB 0 +#define DMA_INTE1_OFFSET _u(0x00000414) +#define DMA_INTE1_BITS _u(0x0000ffff) +#define DMA_INTE1_RESET _u(0x00000000) +#define DMA_INTE1_MSB _u(15) +#define DMA_INTE1_LSB _u(0) #define DMA_INTE1_ACCESS "RW" // ============================================================================= // Register : DMA_INTF1 // Description : Force Interrupts for IRQ 1 // Write 1s to force the corresponding bits in INTE0. The // interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF1_OFFSET 0x00000418 -#define DMA_INTF1_BITS 0x0000ffff -#define DMA_INTF1_RESET 0x00000000 -#define DMA_INTF1_MSB 15 -#define DMA_INTF1_LSB 0 +#define DMA_INTF1_OFFSET _u(0x00000418) +#define DMA_INTF1_BITS _u(0x0000ffff) +#define DMA_INTF1_RESET _u(0x00000000) +#define DMA_INTF1_MSB _u(15) +#define DMA_INTF1_LSB _u(0) #define DMA_INTF1_ACCESS "RW" // ============================================================================= // Register : DMA_INTS1 @@ -4763,11 +4763,11 @@ // Indicates active channel interrupt requests which are currently // causing IRQ 1 to be asserted. // Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS1_OFFSET 0x0000041c -#define DMA_INTS1_BITS 0x0000ffff -#define DMA_INTS1_RESET 0x00000000 -#define DMA_INTS1_MSB 15 -#define DMA_INTS1_LSB 0 +#define DMA_INTS1_OFFSET _u(0x0000041c) +#define DMA_INTS1_BITS _u(0x0000ffff) +#define DMA_INTS1_RESET _u(0x00000000) +#define DMA_INTS1_MSB _u(15) +#define DMA_INTS1_LSB _u(0) #define DMA_INTS1_ACCESS "WC" // ============================================================================= // Register : DMA_TIMER0 @@ -4776,26 +4776,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER0_OFFSET 0x00000420 -#define DMA_TIMER0_BITS 0xffffffff -#define DMA_TIMER0_RESET 0x00000000 +#define DMA_TIMER0_OFFSET _u(0x00000420) +#define DMA_TIMER0_BITS _u(0xffffffff) +#define DMA_TIMER0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER0_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER0_X_RESET 0x0000 -#define DMA_TIMER0_X_BITS 0xffff0000 -#define DMA_TIMER0_X_MSB 31 -#define DMA_TIMER0_X_LSB 16 +#define DMA_TIMER0_X_RESET _u(0x0000) +#define DMA_TIMER0_X_BITS _u(0xffff0000) +#define DMA_TIMER0_X_MSB _u(31) +#define DMA_TIMER0_X_LSB _u(16) #define DMA_TIMER0_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER0_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER0_Y_RESET 0x0000 -#define DMA_TIMER0_Y_BITS 0x0000ffff -#define DMA_TIMER0_Y_MSB 15 -#define DMA_TIMER0_Y_LSB 0 +#define DMA_TIMER0_Y_RESET _u(0x0000) +#define DMA_TIMER0_Y_BITS _u(0x0000ffff) +#define DMA_TIMER0_Y_MSB _u(15) +#define DMA_TIMER0_Y_LSB _u(0) #define DMA_TIMER0_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER1 @@ -4804,26 +4804,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER1_OFFSET 0x00000424 -#define DMA_TIMER1_BITS 0xffffffff -#define DMA_TIMER1_RESET 0x00000000 +#define DMA_TIMER1_OFFSET _u(0x00000424) +#define DMA_TIMER1_BITS _u(0xffffffff) +#define DMA_TIMER1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER1_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER1_X_RESET 0x0000 -#define DMA_TIMER1_X_BITS 0xffff0000 -#define DMA_TIMER1_X_MSB 31 -#define DMA_TIMER1_X_LSB 16 +#define DMA_TIMER1_X_RESET _u(0x0000) +#define DMA_TIMER1_X_BITS _u(0xffff0000) +#define DMA_TIMER1_X_MSB _u(31) +#define DMA_TIMER1_X_LSB _u(16) #define DMA_TIMER1_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER1_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER1_Y_RESET 0x0000 -#define DMA_TIMER1_Y_BITS 0x0000ffff -#define DMA_TIMER1_Y_MSB 15 -#define DMA_TIMER1_Y_LSB 0 +#define DMA_TIMER1_Y_RESET _u(0x0000) +#define DMA_TIMER1_Y_BITS _u(0x0000ffff) +#define DMA_TIMER1_Y_MSB _u(15) +#define DMA_TIMER1_Y_LSB _u(0) #define DMA_TIMER1_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER2 @@ -4832,26 +4832,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER2_OFFSET 0x00000428 -#define DMA_TIMER2_BITS 0xffffffff -#define DMA_TIMER2_RESET 0x00000000 +#define DMA_TIMER2_OFFSET _u(0x00000428) +#define DMA_TIMER2_BITS _u(0xffffffff) +#define DMA_TIMER2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER2_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER2_X_RESET 0x0000 -#define DMA_TIMER2_X_BITS 0xffff0000 -#define DMA_TIMER2_X_MSB 31 -#define DMA_TIMER2_X_LSB 16 +#define DMA_TIMER2_X_RESET _u(0x0000) +#define DMA_TIMER2_X_BITS _u(0xffff0000) +#define DMA_TIMER2_X_MSB _u(31) +#define DMA_TIMER2_X_LSB _u(16) #define DMA_TIMER2_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER2_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER2_Y_RESET 0x0000 -#define DMA_TIMER2_Y_BITS 0x0000ffff -#define DMA_TIMER2_Y_MSB 15 -#define DMA_TIMER2_Y_LSB 0 +#define DMA_TIMER2_Y_RESET _u(0x0000) +#define DMA_TIMER2_Y_BITS _u(0x0000ffff) +#define DMA_TIMER2_Y_MSB _u(15) +#define DMA_TIMER2_Y_LSB _u(0) #define DMA_TIMER2_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER3 @@ -4860,26 +4860,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER3_OFFSET 0x0000042c -#define DMA_TIMER3_BITS 0xffffffff -#define DMA_TIMER3_RESET 0x00000000 +#define DMA_TIMER3_OFFSET _u(0x0000042c) +#define DMA_TIMER3_BITS _u(0xffffffff) +#define DMA_TIMER3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER3_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER3_X_RESET 0x0000 -#define DMA_TIMER3_X_BITS 0xffff0000 -#define DMA_TIMER3_X_MSB 31 -#define DMA_TIMER3_X_LSB 16 +#define DMA_TIMER3_X_RESET _u(0x0000) +#define DMA_TIMER3_X_BITS _u(0xffff0000) +#define DMA_TIMER3_X_MSB _u(31) +#define DMA_TIMER3_X_LSB _u(16) #define DMA_TIMER3_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER3_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER3_Y_RESET 0x0000 -#define DMA_TIMER3_Y_BITS 0x0000ffff -#define DMA_TIMER3_Y_MSB 15 -#define DMA_TIMER3_Y_LSB 0 +#define DMA_TIMER3_Y_RESET _u(0x0000) +#define DMA_TIMER3_Y_BITS _u(0x0000ffff) +#define DMA_TIMER3_Y_MSB _u(15) +#define DMA_TIMER3_Y_LSB _u(0) #define DMA_TIMER3_Y_ACCESS "RW" // ============================================================================= // Register : DMA_MULTI_CHAN_TRIGGER @@ -4888,38 +4888,38 @@ // a 1 to the relevant bit is the same as writing to that // channel's trigger register; the channel will start if it is // currently enabled and not already busy. -#define DMA_MULTI_CHAN_TRIGGER_OFFSET 0x00000430 -#define DMA_MULTI_CHAN_TRIGGER_BITS 0x0000ffff -#define DMA_MULTI_CHAN_TRIGGER_RESET 0x00000000 -#define DMA_MULTI_CHAN_TRIGGER_MSB 15 -#define DMA_MULTI_CHAN_TRIGGER_LSB 0 +#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430) +#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) +#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) +#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) +#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) #define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" // ============================================================================= // Register : DMA_SNIFF_CTRL // Description : Sniffer Control -#define DMA_SNIFF_CTRL_OFFSET 0x00000434 -#define DMA_SNIFF_CTRL_BITS 0x00000fff -#define DMA_SNIFF_CTRL_RESET 0x00000000 +#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434) +#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) +#define DMA_SNIFF_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_OUT_INV // Description : If set, the result appears inverted (bitwise complement) when // read. This does not affect the way the checksum is calculated; // the result is transformed on-the-fly between the result // register and the bus. -#define DMA_SNIFF_CTRL_OUT_INV_RESET 0x0 -#define DMA_SNIFF_CTRL_OUT_INV_BITS 0x00000800 -#define DMA_SNIFF_CTRL_OUT_INV_MSB 11 -#define DMA_SNIFF_CTRL_OUT_INV_LSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) +#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) #define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_OUT_REV // Description : If set, the result appears bit-reversed when read. This does // not affect the way the checksum is calculated; the result is // transformed on-the-fly between the result register and the bus. -#define DMA_SNIFF_CTRL_OUT_REV_RESET 0x0 -#define DMA_SNIFF_CTRL_OUT_REV_BITS 0x00000400 -#define DMA_SNIFF_CTRL_OUT_REV_MSB 10 -#define DMA_SNIFF_CTRL_OUT_REV_LSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) +#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) #define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_BSWAP @@ -4930,10 +4930,10 @@ // byteswap performed in the read master: if channel CTRL_BSWAP // and SNIFF_CTRL_BSWAP are both enabled, their effects cancel // from the sniffer's point of view. -#define DMA_SNIFF_CTRL_BSWAP_RESET 0x0 -#define DMA_SNIFF_CTRL_BSWAP_BITS 0x00000200 -#define DMA_SNIFF_CTRL_BSWAP_MSB 9 -#define DMA_SNIFF_CTRL_BSWAP_LSB 9 +#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) +#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) +#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) #define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC @@ -4946,32 +4946,32 @@ // population count is odd. // 0xf -> Calculate a simple 32-bit checksum (addition with a 32 // bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET 0x0 -#define DMA_SNIFF_CTRL_CALC_BITS 0x000001e0 -#define DMA_SNIFF_CTRL_CALC_MSB 8 -#define DMA_SNIFF_CTRL_CALC_LSB 5 +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) #define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 0x0 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R 0x1 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 0x2 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R 0x3 -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN 0xe -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM 0xf +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_DMACH // Description : DMA channel for Sniffer to observe -#define DMA_SNIFF_CTRL_DMACH_RESET 0x0 -#define DMA_SNIFF_CTRL_DMACH_BITS 0x0000001e -#define DMA_SNIFF_CTRL_DMACH_MSB 4 -#define DMA_SNIFF_CTRL_DMACH_LSB 1 +#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) +#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) +#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) +#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) #define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_EN // Description : Enable sniffer -#define DMA_SNIFF_CTRL_EN_RESET 0x0 -#define DMA_SNIFF_CTRL_EN_BITS 0x00000001 -#define DMA_SNIFF_CTRL_EN_MSB 0 -#define DMA_SNIFF_CTRL_EN_LSB 0 +#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) +#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) +#define DMA_SNIFF_CTRL_EN_MSB _u(0) +#define DMA_SNIFF_CTRL_EN_LSB _u(0) #define DMA_SNIFF_CTRL_EN_ACCESS "RW" // ============================================================================= // Register : DMA_SNIFF_DATA @@ -4981,41 +4981,41 @@ // update this register each time it observes a read from the // indicated channel. Once the channel completes, the final result // can be read from this register. -#define DMA_SNIFF_DATA_OFFSET 0x00000438 -#define DMA_SNIFF_DATA_BITS 0xffffffff -#define DMA_SNIFF_DATA_RESET 0x00000000 -#define DMA_SNIFF_DATA_MSB 31 -#define DMA_SNIFF_DATA_LSB 0 +#define DMA_SNIFF_DATA_OFFSET _u(0x00000438) +#define DMA_SNIFF_DATA_BITS _u(0xffffffff) +#define DMA_SNIFF_DATA_RESET _u(0x00000000) +#define DMA_SNIFF_DATA_MSB _u(31) +#define DMA_SNIFF_DATA_LSB _u(0) #define DMA_SNIFF_DATA_ACCESS "RW" // ============================================================================= // Register : DMA_FIFO_LEVELS // Description : Debug RAF, WAF, TDF levels -#define DMA_FIFO_LEVELS_OFFSET 0x00000440 -#define DMA_FIFO_LEVELS_BITS 0x00ffffff -#define DMA_FIFO_LEVELS_RESET 0x00000000 +#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440) +#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) +#define DMA_FIFO_LEVELS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_RAF_LVL // Description : Current Read-Address-FIFO fill level -#define DMA_FIFO_LEVELS_RAF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_RAF_LVL_BITS 0x00ff0000 -#define DMA_FIFO_LEVELS_RAF_LVL_MSB 23 -#define DMA_FIFO_LEVELS_RAF_LVL_LSB 16 +#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) +#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) +#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) #define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_WAF_LVL // Description : Current Write-Address-FIFO fill level -#define DMA_FIFO_LEVELS_WAF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_WAF_LVL_BITS 0x0000ff00 -#define DMA_FIFO_LEVELS_WAF_LVL_MSB 15 -#define DMA_FIFO_LEVELS_WAF_LVL_LSB 8 +#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) +#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) +#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) #define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_TDF_LVL // Description : Current Transfer-Data-FIFO fill level -#define DMA_FIFO_LEVELS_TDF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_TDF_LVL_BITS 0x000000ff -#define DMA_FIFO_LEVELS_TDF_LVL_MSB 7 -#define DMA_FIFO_LEVELS_TDF_LVL_LSB 0 +#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) +#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) +#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) #define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" // ============================================================================= // Register : DMA_CHAN_ABORT @@ -5028,22 +5028,22 @@ // After writing, this register must be polled until it returns // all-zero. Until this point, it is unsafe to restart the // channel. -#define DMA_CHAN_ABORT_OFFSET 0x00000444 -#define DMA_CHAN_ABORT_BITS 0x0000ffff -#define DMA_CHAN_ABORT_RESET 0x00000000 -#define DMA_CHAN_ABORT_MSB 15 -#define DMA_CHAN_ABORT_LSB 0 +#define DMA_CHAN_ABORT_OFFSET _u(0x00000444) +#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) +#define DMA_CHAN_ABORT_RESET _u(0x00000000) +#define DMA_CHAN_ABORT_MSB _u(15) +#define DMA_CHAN_ABORT_LSB _u(0) #define DMA_CHAN_ABORT_ACCESS "SC" // ============================================================================= // Register : DMA_N_CHANNELS // Description : The number of channels this DMA instance is equipped with. This // DMA supports up to 16 hardware channels, but can be configured // with as few as one, to minimise silicon area. -#define DMA_N_CHANNELS_OFFSET 0x00000448 -#define DMA_N_CHANNELS_BITS 0x0000001f +#define DMA_N_CHANNELS_OFFSET _u(0x00000448) +#define DMA_N_CHANNELS_BITS _u(0x0000001f) #define DMA_N_CHANNELS_RESET "-" -#define DMA_N_CHANNELS_MSB 4 -#define DMA_N_CHANNELS_LSB 0 +#define DMA_N_CHANNELS_MSB _u(4) +#define DMA_N_CHANNELS_LSB _u(0) #define DMA_N_CHANNELS_ACCESS "RO" // ============================================================================= // Register : DMA_CH0_DBG_CTDREQ @@ -5051,21 +5051,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH0_DBG_CTDREQ_OFFSET 0x00000800 -#define DMA_CH0_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH0_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH0_DBG_CTDREQ_MSB 5 -#define DMA_CH0_DBG_CTDREQ_LSB 0 -#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) +#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH0_DBG_CTDREQ_MSB _u(5) +#define DMA_CH0_DBG_CTDREQ_LSB _u(0) +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH0_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH0_DBG_TCR_OFFSET 0x00000804 -#define DMA_CH0_DBG_TCR_BITS 0xffffffff -#define DMA_CH0_DBG_TCR_RESET 0x00000000 -#define DMA_CH0_DBG_TCR_MSB 31 -#define DMA_CH0_DBG_TCR_LSB 0 +#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) +#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH0_DBG_TCR_MSB _u(31) +#define DMA_CH0_DBG_TCR_LSB _u(0) #define DMA_CH0_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH1_DBG_CTDREQ @@ -5073,21 +5073,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH1_DBG_CTDREQ_OFFSET 0x00000840 -#define DMA_CH1_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH1_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH1_DBG_CTDREQ_MSB 5 -#define DMA_CH1_DBG_CTDREQ_LSB 0 -#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) +#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH1_DBG_CTDREQ_MSB _u(5) +#define DMA_CH1_DBG_CTDREQ_LSB _u(0) +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH1_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH1_DBG_TCR_OFFSET 0x00000844 -#define DMA_CH1_DBG_TCR_BITS 0xffffffff -#define DMA_CH1_DBG_TCR_RESET 0x00000000 -#define DMA_CH1_DBG_TCR_MSB 31 -#define DMA_CH1_DBG_TCR_LSB 0 +#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) +#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH1_DBG_TCR_MSB _u(31) +#define DMA_CH1_DBG_TCR_LSB _u(0) #define DMA_CH1_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH2_DBG_CTDREQ @@ -5095,21 +5095,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH2_DBG_CTDREQ_OFFSET 0x00000880 -#define DMA_CH2_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH2_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH2_DBG_CTDREQ_MSB 5 -#define DMA_CH2_DBG_CTDREQ_LSB 0 -#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) +#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH2_DBG_CTDREQ_MSB _u(5) +#define DMA_CH2_DBG_CTDREQ_LSB _u(0) +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH2_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH2_DBG_TCR_OFFSET 0x00000884 -#define DMA_CH2_DBG_TCR_BITS 0xffffffff -#define DMA_CH2_DBG_TCR_RESET 0x00000000 -#define DMA_CH2_DBG_TCR_MSB 31 -#define DMA_CH2_DBG_TCR_LSB 0 +#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) +#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH2_DBG_TCR_MSB _u(31) +#define DMA_CH2_DBG_TCR_LSB _u(0) #define DMA_CH2_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH3_DBG_CTDREQ @@ -5117,21 +5117,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH3_DBG_CTDREQ_OFFSET 0x000008c0 -#define DMA_CH3_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH3_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH3_DBG_CTDREQ_MSB 5 -#define DMA_CH3_DBG_CTDREQ_LSB 0 -#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) +#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH3_DBG_CTDREQ_MSB _u(5) +#define DMA_CH3_DBG_CTDREQ_LSB _u(0) +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH3_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH3_DBG_TCR_OFFSET 0x000008c4 -#define DMA_CH3_DBG_TCR_BITS 0xffffffff -#define DMA_CH3_DBG_TCR_RESET 0x00000000 -#define DMA_CH3_DBG_TCR_MSB 31 -#define DMA_CH3_DBG_TCR_LSB 0 +#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) +#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH3_DBG_TCR_MSB _u(31) +#define DMA_CH3_DBG_TCR_LSB _u(0) #define DMA_CH3_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH4_DBG_CTDREQ @@ -5139,21 +5139,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH4_DBG_CTDREQ_OFFSET 0x00000900 -#define DMA_CH4_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH4_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH4_DBG_CTDREQ_MSB 5 -#define DMA_CH4_DBG_CTDREQ_LSB 0 -#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) +#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH4_DBG_CTDREQ_MSB _u(5) +#define DMA_CH4_DBG_CTDREQ_LSB _u(0) +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH4_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH4_DBG_TCR_OFFSET 0x00000904 -#define DMA_CH4_DBG_TCR_BITS 0xffffffff -#define DMA_CH4_DBG_TCR_RESET 0x00000000 -#define DMA_CH4_DBG_TCR_MSB 31 -#define DMA_CH4_DBG_TCR_LSB 0 +#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) +#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH4_DBG_TCR_MSB _u(31) +#define DMA_CH4_DBG_TCR_LSB _u(0) #define DMA_CH4_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH5_DBG_CTDREQ @@ -5161,21 +5161,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH5_DBG_CTDREQ_OFFSET 0x00000940 -#define DMA_CH5_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH5_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH5_DBG_CTDREQ_MSB 5 -#define DMA_CH5_DBG_CTDREQ_LSB 0 -#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) +#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH5_DBG_CTDREQ_MSB _u(5) +#define DMA_CH5_DBG_CTDREQ_LSB _u(0) +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH5_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH5_DBG_TCR_OFFSET 0x00000944 -#define DMA_CH5_DBG_TCR_BITS 0xffffffff -#define DMA_CH5_DBG_TCR_RESET 0x00000000 -#define DMA_CH5_DBG_TCR_MSB 31 -#define DMA_CH5_DBG_TCR_LSB 0 +#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) +#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH5_DBG_TCR_MSB _u(31) +#define DMA_CH5_DBG_TCR_LSB _u(0) #define DMA_CH5_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH6_DBG_CTDREQ @@ -5183,21 +5183,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH6_DBG_CTDREQ_OFFSET 0x00000980 -#define DMA_CH6_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH6_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH6_DBG_CTDREQ_MSB 5 -#define DMA_CH6_DBG_CTDREQ_LSB 0 -#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) +#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH6_DBG_CTDREQ_MSB _u(5) +#define DMA_CH6_DBG_CTDREQ_LSB _u(0) +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH6_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH6_DBG_TCR_OFFSET 0x00000984 -#define DMA_CH6_DBG_TCR_BITS 0xffffffff -#define DMA_CH6_DBG_TCR_RESET 0x00000000 -#define DMA_CH6_DBG_TCR_MSB 31 -#define DMA_CH6_DBG_TCR_LSB 0 +#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) +#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH6_DBG_TCR_MSB _u(31) +#define DMA_CH6_DBG_TCR_LSB _u(0) #define DMA_CH6_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH7_DBG_CTDREQ @@ -5205,21 +5205,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH7_DBG_CTDREQ_OFFSET 0x000009c0 -#define DMA_CH7_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH7_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH7_DBG_CTDREQ_MSB 5 -#define DMA_CH7_DBG_CTDREQ_LSB 0 -#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) +#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH7_DBG_CTDREQ_MSB _u(5) +#define DMA_CH7_DBG_CTDREQ_LSB _u(0) +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH7_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH7_DBG_TCR_OFFSET 0x000009c4 -#define DMA_CH7_DBG_TCR_BITS 0xffffffff -#define DMA_CH7_DBG_TCR_RESET 0x00000000 -#define DMA_CH7_DBG_TCR_MSB 31 -#define DMA_CH7_DBG_TCR_LSB 0 +#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) +#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH7_DBG_TCR_MSB _u(31) +#define DMA_CH7_DBG_TCR_LSB _u(0) #define DMA_CH7_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH8_DBG_CTDREQ @@ -5227,21 +5227,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH8_DBG_CTDREQ_OFFSET 0x00000a00 -#define DMA_CH8_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH8_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH8_DBG_CTDREQ_MSB 5 -#define DMA_CH8_DBG_CTDREQ_LSB 0 -#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) +#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH8_DBG_CTDREQ_MSB _u(5) +#define DMA_CH8_DBG_CTDREQ_LSB _u(0) +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH8_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH8_DBG_TCR_OFFSET 0x00000a04 -#define DMA_CH8_DBG_TCR_BITS 0xffffffff -#define DMA_CH8_DBG_TCR_RESET 0x00000000 -#define DMA_CH8_DBG_TCR_MSB 31 -#define DMA_CH8_DBG_TCR_LSB 0 +#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) +#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH8_DBG_TCR_MSB _u(31) +#define DMA_CH8_DBG_TCR_LSB _u(0) #define DMA_CH8_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH9_DBG_CTDREQ @@ -5249,21 +5249,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH9_DBG_CTDREQ_OFFSET 0x00000a40 -#define DMA_CH9_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH9_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH9_DBG_CTDREQ_MSB 5 -#define DMA_CH9_DBG_CTDREQ_LSB 0 -#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) +#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH9_DBG_CTDREQ_MSB _u(5) +#define DMA_CH9_DBG_CTDREQ_LSB _u(0) +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH9_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH9_DBG_TCR_OFFSET 0x00000a44 -#define DMA_CH9_DBG_TCR_BITS 0xffffffff -#define DMA_CH9_DBG_TCR_RESET 0x00000000 -#define DMA_CH9_DBG_TCR_MSB 31 -#define DMA_CH9_DBG_TCR_LSB 0 +#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) +#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH9_DBG_TCR_MSB _u(31) +#define DMA_CH9_DBG_TCR_LSB _u(0) #define DMA_CH9_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH10_DBG_CTDREQ @@ -5271,21 +5271,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH10_DBG_CTDREQ_OFFSET 0x00000a80 -#define DMA_CH10_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH10_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH10_DBG_CTDREQ_MSB 5 -#define DMA_CH10_DBG_CTDREQ_LSB 0 -#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) +#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH10_DBG_CTDREQ_MSB _u(5) +#define DMA_CH10_DBG_CTDREQ_LSB _u(0) +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH10_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH10_DBG_TCR_OFFSET 0x00000a84 -#define DMA_CH10_DBG_TCR_BITS 0xffffffff -#define DMA_CH10_DBG_TCR_RESET 0x00000000 -#define DMA_CH10_DBG_TCR_MSB 31 -#define DMA_CH10_DBG_TCR_LSB 0 +#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) +#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH10_DBG_TCR_MSB _u(31) +#define DMA_CH10_DBG_TCR_LSB _u(0) #define DMA_CH10_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH11_DBG_CTDREQ @@ -5293,21 +5293,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH11_DBG_CTDREQ_OFFSET 0x00000ac0 -#define DMA_CH11_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH11_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH11_DBG_CTDREQ_MSB 5 -#define DMA_CH11_DBG_CTDREQ_LSB 0 -#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) +#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH11_DBG_CTDREQ_MSB _u(5) +#define DMA_CH11_DBG_CTDREQ_LSB _u(0) +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH11_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH11_DBG_TCR_OFFSET 0x00000ac4 -#define DMA_CH11_DBG_TCR_BITS 0xffffffff -#define DMA_CH11_DBG_TCR_RESET 0x00000000 -#define DMA_CH11_DBG_TCR_MSB 31 -#define DMA_CH11_DBG_TCR_LSB 0 +#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) +#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH11_DBG_TCR_MSB _u(31) +#define DMA_CH11_DBG_TCR_LSB _u(0) #define DMA_CH11_DBG_TCR_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_DMA_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h index c027119a8ef..dcddb06a096 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h @@ -8,6 +8,80 @@ // Version : 1 // Bus type : apb // Description : DW_apb_i2c address block +// +// List of configuration constants for the Synopsys I2C +// hardware (you may see references to these in I2C register +// header; these are *fixed* values, set at hardware design +// time): +// +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 // ============================================================================= #ifndef HARDWARE_REGS_I2C_DEFINED #define HARDWARE_REGS_I2C_DEFINED @@ -21,17 +95,17 @@ // Read/Write Access: - bit 10 is read only. - bit 11 is read only // - bit 16 is read only - bit 17 is read only - bits 18 and 19 // are read only. -#define I2C_IC_CON_OFFSET 0x00000000 -#define I2C_IC_CON_BITS 0x000007ff -#define I2C_IC_CON_RESET 0x00000065 +#define I2C_IC_CON_OFFSET _u(0x00000000) +#define I2C_IC_CON_BITS _u(0x000007ff) +#define I2C_IC_CON_RESET _u(0x00000065) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE // Description : Master issues the STOP_DET interrupt irrespective of whether // master is active or not -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS 0x00000400 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL @@ -42,13 +116,13 @@ // Reset value: 0x0. // 0x0 -> Overflow when RX_FIFO is full // 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS 0x00000200 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED 0x0 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED 0x1 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_TX_EMPTY_CTRL // Description : This bit controls the generation of the TX_EMPTY interrupt, as @@ -57,13 +131,13 @@ // Reset value: 0x0. // 0x0 -> Default behaviour of TX_EMPTY interrupt // 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0 -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS 0x00000100 -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB 8 -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) #define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED 0x0 -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED 0x1 +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IFADDRESSED // Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when @@ -77,13 +151,13 @@ // transmitted address matches the slave address (SAR). // 0x0 -> slave issues STOP_DET intr always // 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS 0x00000080 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) #define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED 0x0 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED 0x1 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_SLAVE_DISABLE // Description : This bit controls whether I2C has its slave disabled, which @@ -98,13 +172,13 @@ // 0, then bit 0 should also be written with a 0. // 0x0 -> Slave mode is enabled // 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1 -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS 0x00000040 -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6 -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) #define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED 0x0 -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED 0x1 +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_RESTART_EN // Description : Determines whether RESTART conditions may be sent when acting @@ -124,13 +198,13 @@ // Reset value: ENABLED // 0x0 -> Master restart disabled // 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET 0x1 -#define I2C_IC_CON_IC_RESTART_EN_BITS 0x00000020 -#define I2C_IC_CON_IC_RESTART_EN_MSB 5 -#define I2C_IC_CON_IC_RESTART_EN_LSB 5 +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) #define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" -#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED 0x0 -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED 0x1 +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_MASTER // Description : Controls whether the DW_apb_i2c starts its transfers in 7- or @@ -138,13 +212,13 @@ // addressing - 1: 10-bit addressing // 0x0 -> Master 7Bit addressing mode // 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET 0x0 -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS 0x00000010 -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB 4 -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) #define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS 0x0 -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS 0x1 +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_SLAVE // Description : When acting as a slave, this bit controls whether the @@ -156,13 +230,13 @@ // that match the full 10 bits of the IC_SAR register. // 0x0 -> Slave 7Bit addressing // 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x0 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS 0x00000008 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) #define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS 0x0 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS 0x1 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_SPEED // Description : These bits control at which speed the DW_apb_i2c operates; its @@ -186,14 +260,14 @@ // 0x1 -> Standard Speed mode of operation // 0x2 -> Fast or Fast Plus mode of operation // 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET 0x2 -#define I2C_IC_CON_SPEED_BITS 0x00000006 -#define I2C_IC_CON_SPEED_MSB 2 -#define I2C_IC_CON_SPEED_LSB 1 +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) #define I2C_IC_CON_SPEED_ACCESS "RW" -#define I2C_IC_CON_SPEED_VALUE_STANDARD 0x1 -#define I2C_IC_CON_SPEED_VALUE_FAST 0x2 -#define I2C_IC_CON_SPEED_VALUE_HIGH 0x3 +#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_MASTER_MODE // Description : This bit controls whether the DW_apb_i2c master is enabled. @@ -202,13 +276,13 @@ // '1' then bit 6 should also be written with a '1'. // 0x0 -> Master mode is disabled // 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET 0x1 -#define I2C_IC_CON_MASTER_MODE_BITS 0x00000001 -#define I2C_IC_CON_MASTER_MODE_MSB 0 -#define I2C_IC_CON_MASTER_MODE_LSB 0 +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) #define I2C_IC_CON_MASTER_MODE_ACCESS "RW" -#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED 0x0 -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED 0x1 +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_TAR // Description : I2C Target Address Register @@ -223,9 +297,9 @@ // address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - // It is not necessary to perform any write to this register if // DW_apb_i2c is enabled as an I2C slave only. -#define I2C_IC_TAR_OFFSET 0x00000004 -#define I2C_IC_TAR_BITS 0x00000fff -#define I2C_IC_TAR_RESET 0x00000055 +#define I2C_IC_TAR_OFFSET _u(0x00000004) +#define I2C_IC_TAR_BITS _u(0x00000fff) +#define I2C_IC_TAR_RESET _u(0x00000055) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_SPECIAL // Description : This bit indicates whether software performs a Device-ID or @@ -237,13 +311,13 @@ // transmission // 0x1 -> Enables programming of GENERAL_CALL or START_BYTE // transmission -#define I2C_IC_TAR_SPECIAL_RESET 0x0 -#define I2C_IC_TAR_SPECIAL_BITS 0x00000800 -#define I2C_IC_TAR_SPECIAL_MSB 11 -#define I2C_IC_TAR_SPECIAL_LSB 11 +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) #define I2C_IC_TAR_SPECIAL_ACCESS "RW" -#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED 0x0 -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED 0x1 +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_GC_OR_START // Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to @@ -256,13 +330,13 @@ // value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 // 0x0 -> GENERAL_CALL byte transmission // 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET 0x0 -#define I2C_IC_TAR_GC_OR_START_BITS 0x00000400 -#define I2C_IC_TAR_GC_OR_START_MSB 10 -#define I2C_IC_TAR_GC_OR_START_LSB 10 +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) #define I2C_IC_TAR_GC_OR_START_ACCESS "RW" -#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL 0x0 -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE 0x1 +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_IC_TAR // Description : This is the target address for any master transaction. When @@ -275,17 +349,17 @@ // not feasible. Only one direction loopback mode is supported // (simplex), not duplex. A master cannot transmit to itself; it // can transmit to only a slave. -#define I2C_IC_TAR_IC_TAR_RESET 0x055 -#define I2C_IC_TAR_IC_TAR_BITS 0x000003ff -#define I2C_IC_TAR_IC_TAR_MSB 9 -#define I2C_IC_TAR_IC_TAR_LSB 0 +#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) +#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) +#define I2C_IC_TAR_IC_TAR_MSB _u(9) +#define I2C_IC_TAR_IC_TAR_LSB _u(0) #define I2C_IC_TAR_IC_TAR_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SAR // Description : I2C Slave Address Register -#define I2C_IC_SAR_OFFSET 0x00000008 -#define I2C_IC_SAR_BITS 0x000003ff -#define I2C_IC_SAR_RESET 0x00000055 +#define I2C_IC_SAR_OFFSET _u(0x00000008) +#define I2C_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_RESET _u(0x00000055) // ----------------------------------------------------------------------------- // Field : I2C_IC_SAR_IC_SAR // Description : The IC_SAR holds the slave address when the I2C is operating as @@ -301,10 +375,10 @@ // IC_SAR or IC_TAR to a reserved value. Refer to // <> for a complete list of these // reserved values. -#define I2C_IC_SAR_IC_SAR_RESET 0x055 -#define I2C_IC_SAR_IC_SAR_BITS 0x000003ff -#define I2C_IC_SAR_IC_SAR_MSB 9 -#define I2C_IC_SAR_IC_SAR_LSB 0 +#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) +#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_IC_SAR_MSB _u(9) +#define I2C_IC_SAR_IC_SAR_LSB _u(0) #define I2C_IC_SAR_IC_SAR_ACCESS "RW" // ============================================================================= // Register : I2C_IC_DATA_CMD @@ -321,9 +395,9 @@ // to continue acknowledging reads, a read command should be // written for every byte that is to be received; otherwise the // DW_apb_i2c will stop acknowledging. -#define I2C_IC_DATA_CMD_OFFSET 0x00000010 -#define I2C_IC_DATA_CMD_BITS 0x00000fff -#define I2C_IC_DATA_CMD_RESET 0x00000000 +#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) +#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) +#define I2C_IC_DATA_CMD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE // Description : Indicates the first data byte received after the address phase @@ -347,13 +421,13 @@ // FIRST_DATA_BYTE status. // 0x0 -> Sequential data byte received // 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS 0x00000800 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) #define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE 0x0 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE 0x1 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_RESTART // Description : This bit controls whether a RESTART is issued before the byte @@ -373,13 +447,13 @@ // Reset value: 0x0 // 0x0 -> Don't Issue RESTART before this command // 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET 0x0 -#define I2C_IC_DATA_CMD_RESTART_BITS 0x00000400 -#define I2C_IC_DATA_CMD_RESTART_MSB 10 -#define I2C_IC_DATA_CMD_RESTART_LSB 10 +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) #define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" -#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE 0x0 -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE 0x1 +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_STOP // Description : This bit controls whether a STOP is issued after the byte is @@ -397,13 +471,13 @@ // is available in the Tx FIFO. Reset value: 0x0 // 0x0 -> Don't Issue STOP after this command // 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET 0x0 -#define I2C_IC_DATA_CMD_STOP_BITS 0x00000200 -#define I2C_IC_DATA_CMD_STOP_MSB 9 -#define I2C_IC_DATA_CMD_STOP_LSB 9 +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) #define I2C_IC_DATA_CMD_STOP_ACCESS "SC" -#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE 0x0 -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE 0x1 +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_CMD // Description : This bit controls whether a read or a write is performed. This @@ -428,13 +502,13 @@ // Reset value: 0x0 // 0x0 -> Master Write Command // 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET 0x0 -#define I2C_IC_DATA_CMD_CMD_BITS 0x00000100 -#define I2C_IC_DATA_CMD_CMD_MSB 8 -#define I2C_IC_DATA_CMD_CMD_LSB 8 +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) #define I2C_IC_DATA_CMD_CMD_ACCESS "SC" -#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE 0x0 -#define I2C_IC_DATA_CMD_CMD_VALUE_READ 0x1 +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_DAT // Description : This register contains the data to be transmitted or received @@ -444,17 +518,17 @@ // value of data received on the DW_apb_i2c interface. // // Reset value: 0x0 -#define I2C_IC_DATA_CMD_DAT_RESET 0x00 -#define I2C_IC_DATA_CMD_DAT_BITS 0x000000ff -#define I2C_IC_DATA_CMD_DAT_MSB 7 -#define I2C_IC_DATA_CMD_DAT_LSB 0 +#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) +#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) +#define I2C_IC_DATA_CMD_DAT_MSB _u(7) +#define I2C_IC_DATA_CMD_DAT_LSB _u(0) #define I2C_IC_DATA_CMD_DAT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SS_SCL_HCNT // Description : Standard Speed I2C Clock SCL High Count Register -#define I2C_IC_SS_SCL_HCNT_OFFSET 0x00000014 -#define I2C_IC_SS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_HCNT_RESET 0x00000028 +#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) +#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) // ----------------------------------------------------------------------------- // Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT // Description : This register must be set before any I2C bus transaction can @@ -477,17 +551,17 @@ // than 65525, because DW_apb_i2c uses a 16-bit counter to flag an // I2C bus idle condition when this counter reaches a value of // IC_SS_SCL_HCNT + 10. -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x0028 -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) #define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SS_SCL_LCNT // Description : Standard Speed I2C Clock SCL Low Count Register -#define I2C_IC_SS_SCL_LCNT_OFFSET 0x00000018 -#define I2C_IC_SS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_LCNT_RESET 0x0000002f +#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) +#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) // ----------------------------------------------------------------------------- // Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can @@ -505,17 +579,17 @@ // programming is important to ensure the correct operation of // DW_apb_i2c. The lower byte must be programmed first, and then // the upper byte is programmed. -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x002f -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) #define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_FS_SCL_HCNT // Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register -#define I2C_IC_FS_SCL_HCNT_OFFSET 0x0000001c -#define I2C_IC_FS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_HCNT_RESET 0x00000006 +#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) +#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT // Description : This register must be set before any I2C bus transaction can @@ -537,17 +611,17 @@ // programming is important to ensure the correct operation of the // DW_apb_i2c. The lower byte must be programmed first. Then the // upper byte is programmed. -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x0006 -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) #define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_FS_SCL_LCNT // Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register -#define I2C_IC_FS_SCL_LCNT_OFFSET 0x00000020 -#define I2C_IC_FS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_LCNT_RESET 0x0000000d +#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) +#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can @@ -571,10 +645,10 @@ // DW_apb_i2c. The lower byte must be programmed first. Then the // upper byte is programmed. If the value is less than 8 then the // count value gets changed to 8. -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x000d -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) #define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_INTR_STAT @@ -584,24 +658,9 @@ // IC_INTR_MASK register. These bits are cleared by reading the // matching interrupt clear register. The unmasked raw versions of // these bits are available in the IC_RAW_INTR_STAT register. -#define I2C_IC_INTR_STAT_OFFSET 0x0000002c -#define I2C_IC_INTR_STAT_BITS 0x00003fff -#define I2C_IC_INTR_STAT_RESET 0x00000000 -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD -// Description : See IC_RAW_INTR_STAT for a detailed description of -// R_MASTER_ON_HOLD bit. -// -// Reset value: 0x0 -// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive -// 0x1 -> R_MASTER_ON_HOLD interrupt is active -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS 0x00002000 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) +#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_INTR_STAT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RESTART_DET // Description : See IC_RAW_INTR_STAT for a detailed description of @@ -610,13 +669,13 @@ // Reset value: 0x0 // 0x0 -> R_RESTART_DET interrupt is inactive // 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS 0x00001000 -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12 -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) #define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_GEN_CALL // Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL @@ -625,13 +684,13 @@ // Reset value: 0x0 // 0x0 -> R_GEN_CALL interrupt is inactive // 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0 -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS 0x00000800 -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11 -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) #define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_START_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET @@ -640,13 +699,13 @@ // Reset value: 0x0 // 0x0 -> R_START_DET interrupt is inactive // 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_START_DET_BITS 0x00000400 -#define I2C_IC_INTR_STAT_R_START_DET_MSB 10 -#define I2C_IC_INTR_STAT_R_START_DET_LSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) #define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_STOP_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET @@ -655,13 +714,13 @@ // Reset value: 0x0 // 0x0 -> R_STOP_DET interrupt is inactive // 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS 0x00000200 -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB 9 -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) #define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_ACTIVITY // Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY @@ -670,13 +729,13 @@ // Reset value: 0x0 // 0x0 -> R_ACTIVITY interrupt is inactive // 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0 -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS 0x00000100 -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8 -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) #define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_DONE // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE @@ -685,13 +744,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_DONE interrupt is inactive // 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS 0x00000080 -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB 7 -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) #define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_ABRT // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT @@ -700,13 +759,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_ABRT interrupt is inactive // 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS 0x00000040 -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6 -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) #define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RD_REQ // Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ @@ -715,13 +774,13 @@ // Reset value: 0x0 // 0x0 -> R_RD_REQ interrupt is inactive // 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS 0x00000020 -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB 5 -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) #define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_EMPTY // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY @@ -730,13 +789,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_EMPTY interrupt is inactive // 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) #define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER @@ -745,13 +804,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_OVER interrupt is inactive // 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS 0x00000008 -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB 3 -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) #define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_FULL // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL @@ -760,13 +819,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_FULL interrupt is inactive // 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS 0x00000004 -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB 2 -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) #define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER @@ -775,13 +834,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_OVER interrupt is inactive // 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS 0x00000002 -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB 1 -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) #define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_UNDER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER @@ -790,13 +849,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS 0x00000001 -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) #define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_INTR_MASK // Description : I2C Interrupt Mask Register. @@ -804,24 +863,9 @@ // These bits mask their corresponding interrupt status bits. This // register is active low; a value of 0 masks the interrupt, // whereas a value of 1 unmasks the interrupt. -#define I2C_IC_INTR_MASK_OFFSET 0x00000030 -#define I2C_IC_INTR_MASK_BITS 0x00003fff -#define I2C_IC_INTR_MASK_RESET 0x000008ff -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY -// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD -// interrupt in IC_INTR_STAT register. -// -// Reset value: 0x0 -// 0x0 -> MASTER_ON_HOLD interrupt is masked -// 0x1 -> MASTER_ON_HOLD interrupt is unmasked -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET 0x0 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS 0x00002000 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB 13 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB 13 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO" -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) +#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) +#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RESTART_DET // Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT @@ -830,13 +874,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is masked // 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS 0x00001000 -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12 -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) #define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_GEN_CALL // Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT @@ -845,13 +889,13 @@ // Reset value: 0x1 // 0x0 -> GEN_CALL interrupt is masked // 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1 -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS 0x00000800 -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11 -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) #define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_START_DET // Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT @@ -860,13 +904,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is masked // 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_START_DET_BITS 0x00000400 -#define I2C_IC_INTR_MASK_M_START_DET_MSB 10 -#define I2C_IC_INTR_MASK_M_START_DET_LSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) #define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_STOP_DET // Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT @@ -875,13 +919,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is masked // 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS 0x00000200 -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB 9 -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) #define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_ACTIVITY // Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT @@ -890,13 +934,13 @@ // Reset value: 0x0 // 0x0 -> ACTIVITY interrupt is masked // 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0 -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS 0x00000100 -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8 -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) #define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_DONE // Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT @@ -905,13 +949,13 @@ // Reset value: 0x1 // 0x0 -> RX_DONE interrupt is masked // 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS 0x00000080 -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB 7 -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) #define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_ABRT // Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT @@ -920,13 +964,13 @@ // Reset value: 0x1 // 0x0 -> TX_ABORT interrupt is masked // 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS 0x00000040 -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6 -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) #define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RD_REQ // Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. @@ -934,13 +978,13 @@ // Reset value: 0x1 // 0x0 -> RD_REQ interrupt is masked // 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS 0x00000020 -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB 5 -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) #define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_EMPTY // Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT @@ -949,13 +993,13 @@ // Reset value: 0x1 // 0x0 -> TX_EMPTY interrupt is masked // 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) #define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_OVER // Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT @@ -964,13 +1008,13 @@ // Reset value: 0x1 // 0x0 -> TX_OVER interrupt is masked // 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS 0x00000008 -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB 3 -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) #define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_FULL // Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT @@ -979,13 +1023,13 @@ // Reset value: 0x1 // 0x0 -> RX_FULL interrupt is masked // 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS 0x00000004 -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB 2 -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) #define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_OVER // Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT @@ -994,13 +1038,13 @@ // Reset value: 0x1 // 0x0 -> RX_OVER interrupt is masked // 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS 0x00000002 -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB 1 -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) #define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_UNDER // Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT @@ -1009,38 +1053,22 @@ // Reset value: 0x1 // 0x0 -> RX_UNDER interrupt is masked // 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS 0x00000001 -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0 -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) #define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) // ============================================================================= // Register : I2C_IC_RAW_INTR_STAT // Description : I2C Raw Interrupt Status Register // // Unlike the IC_INTR_STAT register, these bits are not masked so // they always show the true status of the DW_apb_i2c. -#define I2C_IC_RAW_INTR_STAT_OFFSET 0x00000034 -#define I2C_IC_RAW_INTR_STAT_BITS 0x00003fff -#define I2C_IC_RAW_INTR_STAT_RESET 0x00000000 -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD -// Description : Indicates whether master is holding the bus and TX FIFO is -// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and -// IC_EMPTYFIFO_HOLD_MASTER_EN=1. -// -// Reset value: 0x0 -// 0x0 -> MASTER_ON_HOLD interrupt is inactive -// 0x1 -> MASTER_ON_HOLD interrupt is active -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS 0x00002000 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) +#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RESTART_DET // Description : Indicates whether a RESTART condition has occurred on the I2C @@ -1057,13 +1085,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is inactive // 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS 0x00001000 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) #define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_GEN_CALL // Description : Set only when a General Call address is received and it is @@ -1075,13 +1103,13 @@ // Reset value: 0x0 // 0x0 -> GEN_CALL interrupt is inactive // 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS 0x00000800 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) #define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_START_DET // Description : Indicates whether a START or RESTART condition has occurred on @@ -1091,13 +1119,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is inactive // 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS 0x00000400 -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB 10 -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) #define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_STOP_DET // Description : Indicates whether a STOP condition has occurred on the I2C @@ -1120,13 +1148,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is inactive // 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS 0x00000200 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) #define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_ACTIVITY // Description : This bit captures DW_apb_i2c activity and stays set until it is @@ -1140,13 +1168,13 @@ // Reset value: 0x0 // 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive // 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS 0x00000100 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB 8 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) #define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_DONE // Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit @@ -1157,13 +1185,13 @@ // Reset value: 0x0 // 0x0 -> RX_DONE interrupt is inactive // 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS 0x00000080 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) #define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_ABRT // Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is @@ -1183,13 +1211,13 @@ // Reset value: 0x0 // 0x0 -> TX_ABRT interrupt is inactive // 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS 0x00000040 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) #define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RD_REQ // Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and @@ -1205,13 +1233,13 @@ // Reset value: 0x0 // 0x0 -> RD_REQ interrupt is inactive // 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS 0x00000020 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) #define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY // Description : The behavior of the TX_EMPTY interrupt status differs based on @@ -1233,13 +1261,13 @@ // Reset value: 0x0. // 0x0 -> TX_EMPTY interrupt is inactive // 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) #define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_OVER // Description : Set during transmit if the transmit buffer is filled to @@ -1252,13 +1280,13 @@ // Reset value: 0x0 // 0x0 -> TX_OVER interrupt is inactive // 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS 0x00000008 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) #define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_FULL // Description : Set when the receive buffer reaches or goes above the RX_TL @@ -1272,13 +1300,13 @@ // Reset value: 0x0 // 0x0 -> RX_FULL interrupt is inactive // 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS 0x00000004 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) #define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_OVER // Description : Set if the receive buffer is completely filled to @@ -1296,13 +1324,13 @@ // Reset value: 0x0 // 0x0 -> RX_OVER interrupt is inactive // 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS 0x00000002 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) #define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_UNDER // Description : Set if the processor attempts to read the receive buffer when @@ -1314,19 +1342,19 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS 0x00000001 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) #define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_RX_TL // Description : I2C Receive FIFO Threshold Register -#define I2C_IC_RX_TL_OFFSET 0x00000038 -#define I2C_IC_RX_TL_BITS 0x000000ff -#define I2C_IC_RX_TL_RESET 0x00000000 +#define I2C_IC_RX_TL_OFFSET _u(0x00000038) +#define I2C_IC_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RX_TL_RX_TL // Description : Receive FIFO Threshold Level. @@ -1339,17 +1367,17 @@ // the actual value set will be the maximum depth of the buffer. A // value of 0 sets the threshold for 1 entry, and a value of 255 // sets the threshold for 256 entries. -#define I2C_IC_RX_TL_RX_TL_RESET 0x00 -#define I2C_IC_RX_TL_RX_TL_BITS 0x000000ff -#define I2C_IC_RX_TL_RX_TL_MSB 7 -#define I2C_IC_RX_TL_RX_TL_LSB 0 +#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) +#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RX_TL_MSB _u(7) +#define I2C_IC_RX_TL_RX_TL_LSB _u(0) #define I2C_IC_RX_TL_RX_TL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_TX_TL // Description : I2C Transmit FIFO Threshold Register -#define I2C_IC_TX_TL_OFFSET 0x0000003c -#define I2C_IC_TX_TL_BITS 0x000000ff -#define I2C_IC_TX_TL_RESET 0x00000000 +#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) +#define I2C_IC_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_TL_TX_TL // Description : Transmit FIFO Threshold Level. @@ -1362,17 +1390,17 @@ // maximum depth of the buffer. A value of 0 sets the threshold // for 0 entries, and a value of 255 sets the threshold for 255 // entries. -#define I2C_IC_TX_TL_TX_TL_RESET 0x00 -#define I2C_IC_TX_TL_TX_TL_BITS 0x000000ff -#define I2C_IC_TX_TL_TX_TL_MSB 7 -#define I2C_IC_TX_TL_TX_TL_LSB 0 +#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) +#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_TX_TL_MSB _u(7) +#define I2C_IC_TX_TL_TX_TL_LSB _u(0) #define I2C_IC_TX_TL_TX_TL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_CLR_INTR // Description : Clear Combined and Individual Interrupt Register -#define I2C_IC_CLR_INTR_OFFSET 0x00000040 -#define I2C_IC_CLR_INTR_BITS 0x00000001 -#define I2C_IC_CLR_INTR_RESET 0x00000000 +#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) +#define I2C_IC_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_INTR_CLR_INTR // Description : Read this register to clear the combined interrupt, all @@ -1382,85 +1410,85 @@ // register for an exception to clearing IC_TX_ABRT_SOURCE. // // Reset value: 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_BITS 0x00000001 -#define I2C_IC_CLR_INTR_CLR_INTR_MSB 0 -#define I2C_IC_CLR_INTR_CLR_INTR_LSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) +#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) #define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_UNDER // Description : Clear RX_UNDER Interrupt Register -#define I2C_IC_CLR_RX_UNDER_OFFSET 0x00000044 -#define I2C_IC_CLR_RX_UNDER_BITS 0x00000001 -#define I2C_IC_CLR_RX_UNDER_RESET 0x00000000 +#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) +#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER // Description : Read this register to clear the RX_UNDER interrupt (bit 0) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS 0x00000001 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) #define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_OVER // Description : Clear RX_OVER Interrupt Register -#define I2C_IC_CLR_RX_OVER_OFFSET 0x00000048 -#define I2C_IC_CLR_RX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_RX_OVER_RESET 0x00000000 +#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) +#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER // Description : Read this register to clear the RX_OVER interrupt (bit 1) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) #define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_TX_OVER // Description : Clear TX_OVER Interrupt Register -#define I2C_IC_CLR_TX_OVER_OFFSET 0x0000004c -#define I2C_IC_CLR_TX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_TX_OVER_RESET 0x00000000 +#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) +#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER // Description : Read this register to clear the TX_OVER interrupt (bit 3) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) #define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RD_REQ // Description : Clear RD_REQ Interrupt Register -#define I2C_IC_CLR_RD_REQ_OFFSET 0x00000050 -#define I2C_IC_CLR_RD_REQ_BITS 0x00000001 -#define I2C_IC_CLR_RD_REQ_RESET 0x00000000 +#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) +#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ // Description : Read this register to clear the RD_REQ interrupt (bit 5) of the // IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS 0x00000001 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) #define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_TX_ABRT // Description : Clear TX_ABRT Interrupt Register -#define I2C_IC_CLR_TX_ABRT_OFFSET 0x00000054 -#define I2C_IC_CLR_TX_ABRT_BITS 0x00000001 -#define I2C_IC_CLR_TX_ABRT_RESET 0x00000000 +#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) +#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT // Description : Read this register to clear the TX_ABRT interrupt (bit 6) of @@ -1471,34 +1499,34 @@ // IC_TX_ABRT_SOURCE. // // Reset value: 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS 0x00000001 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) #define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_DONE // Description : Clear RX_DONE Interrupt Register -#define I2C_IC_CLR_RX_DONE_OFFSET 0x00000058 -#define I2C_IC_CLR_RX_DONE_BITS 0x00000001 -#define I2C_IC_CLR_RX_DONE_RESET 0x00000000 +#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) +#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE // Description : Read this register to clear the RX_DONE interrupt (bit 7) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS 0x00000001 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) #define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_ACTIVITY // Description : Clear ACTIVITY Interrupt Register -#define I2C_IC_CLR_ACTIVITY_OFFSET 0x0000005c -#define I2C_IC_CLR_ACTIVITY_BITS 0x00000001 -#define I2C_IC_CLR_ACTIVITY_RESET 0x00000000 +#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) +#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY // Description : Reading this register clears the ACTIVITY interrupt if the I2C @@ -1510,68 +1538,68 @@ // of the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS 0x00000001 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) #define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_STOP_DET // Description : Clear STOP_DET Interrupt Register -#define I2C_IC_CLR_STOP_DET_OFFSET 0x00000060 -#define I2C_IC_CLR_STOP_DET_BITS 0x00000001 -#define I2C_IC_CLR_STOP_DET_RESET 0x00000000 +#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) +#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET // Description : Read this register to clear the STOP_DET interrupt (bit 9) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS 0x00000001 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) #define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_START_DET // Description : Clear START_DET Interrupt Register -#define I2C_IC_CLR_START_DET_OFFSET 0x00000064 -#define I2C_IC_CLR_START_DET_BITS 0x00000001 -#define I2C_IC_CLR_START_DET_RESET 0x00000000 +#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) +#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_START_DET_CLR_START_DET // Description : Read this register to clear the START_DET interrupt (bit 10) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS 0x00000001 -#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) #define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_GEN_CALL // Description : Clear GEN_CALL Interrupt Register -#define I2C_IC_CLR_GEN_CALL_OFFSET 0x00000068 -#define I2C_IC_CLR_GEN_CALL_BITS 0x00000001 -#define I2C_IC_CLR_GEN_CALL_RESET 0x00000000 +#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) +#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL // Description : Read this register to clear the GEN_CALL interrupt (bit 11) of // IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS 0x00000001 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) #define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" // ============================================================================= // Register : I2C_IC_ENABLE // Description : I2C Enable Register -#define I2C_IC_ENABLE_OFFSET 0x0000006c -#define I2C_IC_ENABLE_BITS 0x00000007 -#define I2C_IC_ENABLE_RESET 0x00000000 +#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) +#define I2C_IC_ENABLE_BITS _u(0x00000007) +#define I2C_IC_ENABLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_TX_CMD_BLOCK // Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C @@ -1585,13 +1613,13 @@ // value: IC_TX_CMD_BLOCK_DEFAULT // 0x0 -> Tx Command execution not blocked // 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS 0x00000004 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) #define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED 0x0 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED 0x1 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ABORT // Description : When set, the controller initiates the transfer abort. - 0: @@ -1611,13 +1639,13 @@ // Reset value: 0x0 // 0x0 -> ABORT operation not in progress // 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET 0x0 -#define I2C_IC_ENABLE_ABORT_BITS 0x00000002 -#define I2C_IC_ENABLE_ABORT_MSB 1 -#define I2C_IC_ENABLE_ABORT_LSB 1 +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) #define I2C_IC_ENABLE_ABORT_ACCESS "RW" -#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE 0x0 -#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ENABLE // Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables @@ -1645,13 +1673,13 @@ // Reset value: 0x0 // 0x0 -> I2C is disabled // 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET 0x0 -#define I2C_IC_ENABLE_ENABLE_BITS 0x00000001 -#define I2C_IC_ENABLE_ENABLE_MSB 0 -#define I2C_IC_ENABLE_ENABLE_LSB 0 +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) #define I2C_IC_ENABLE_ENABLE_ACCESS "RW" -#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED 0x0 -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_STATUS // Description : I2C Status Register @@ -1665,9 +1693,9 @@ // register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set // to 0 When the master or slave state machines goes to idle and // ic_en=0: - Bits 5 and 6 are set to 0 -#define I2C_IC_STATUS_OFFSET 0x00000070 -#define I2C_IC_STATUS_BITS 0x0000007f -#define I2C_IC_STATUS_RESET 0x00000006 +#define I2C_IC_STATUS_OFFSET _u(0x00000070) +#define I2C_IC_STATUS_BITS _u(0x0000007f) +#define I2C_IC_STATUS_RESET _u(0x00000006) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_SLV_ACTIVITY // Description : Slave FSM Activity Status. When the Slave Finite State Machine @@ -1677,13 +1705,13 @@ // DW_apb_i2c is Active Reset value: 0x0 // 0x0 -> Slave is idle // 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS 0x00000040 -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB 6 -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) #define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE 0x0 -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_MST_ACTIVITY // Description : Master FSM Activity Status. When the Master Finite State @@ -1696,13 +1724,13 @@ // Reset value: 0x0 // 0x0 -> Master is idle // 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_MST_ACTIVITY_BITS 0x00000020 -#define I2C_IC_STATUS_MST_ACTIVITY_MSB 5 -#define I2C_IC_STATUS_MST_ACTIVITY_LSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) #define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE 0x0 -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFF // Description : Receive FIFO Completely Full. When the receive FIFO is @@ -1712,13 +1740,13 @@ // 0x0 // 0x0 -> Rx FIFO not full // 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET 0x0 -#define I2C_IC_STATUS_RFF_BITS 0x00000010 -#define I2C_IC_STATUS_RFF_MSB 4 -#define I2C_IC_STATUS_RFF_LSB 4 +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) #define I2C_IC_STATUS_RFF_ACCESS "RO" -#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL 0x0 -#define I2C_IC_STATUS_RFF_VALUE_FULL 0x1 +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFNE // Description : Receive FIFO Not Empty. This bit is set when the receive FIFO @@ -1727,13 +1755,13 @@ // not empty Reset value: 0x0 // 0x0 -> Rx FIFO is empty // 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET 0x0 -#define I2C_IC_STATUS_RFNE_BITS 0x00000008 -#define I2C_IC_STATUS_RFNE_MSB 3 -#define I2C_IC_STATUS_RFNE_LSB 3 +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) #define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY 0x0 -#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY 0x1 +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFE // Description : Transmit FIFO Completely Empty. When the transmit FIFO is @@ -1743,13 +1771,13 @@ // Transmit FIFO is empty Reset value: 0x1 // 0x0 -> Tx FIFO not empty // 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET 0x1 -#define I2C_IC_STATUS_TFE_BITS 0x00000004 -#define I2C_IC_STATUS_TFE_MSB 2 -#define I2C_IC_STATUS_TFE_LSB 2 +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) #define I2C_IC_STATUS_TFE_ACCESS "RO" -#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY 0x0 -#define I2C_IC_STATUS_TFE_VALUE_EMPTY 0x1 +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFNF // Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one @@ -1758,25 +1786,25 @@ // value: 0x1 // 0x0 -> Tx FIFO is full // 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET 0x1 -#define I2C_IC_STATUS_TFNF_BITS 0x00000002 -#define I2C_IC_STATUS_TFNF_MSB 1 -#define I2C_IC_STATUS_TFNF_LSB 1 +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) #define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL 0x0 -#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL 0x1 +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_ACTIVITY // Description : I2C Activity Status. Reset value: 0x0 // 0x0 -> I2C is idle // 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_ACTIVITY_BITS 0x00000001 -#define I2C_IC_STATUS_ACTIVITY_MSB 0 -#define I2C_IC_STATUS_ACTIVITY_LSB 0 +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) #define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_TXFLR // Description : I2C Transmit FIFO Level Register This register contains the @@ -1786,19 +1814,19 @@ // register - The slave bulk transmit mode is aborted The register // increments whenever data is placed into the transmit FIFO and // decrements when data is taken from the transmit FIFO. -#define I2C_IC_TXFLR_OFFSET 0x00000074 -#define I2C_IC_TXFLR_BITS 0x0000001f -#define I2C_IC_TXFLR_RESET 0x00000000 +#define I2C_IC_TXFLR_OFFSET _u(0x00000074) +#define I2C_IC_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TXFLR_TXFLR // Description : Transmit FIFO Level. Contains the number of valid data entries // in the transmit FIFO. // // Reset value: 0x0 -#define I2C_IC_TXFLR_TXFLR_RESET 0x00 -#define I2C_IC_TXFLR_TXFLR_BITS 0x0000001f -#define I2C_IC_TXFLR_TXFLR_MSB 4 -#define I2C_IC_TXFLR_TXFLR_LSB 0 +#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) +#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_TXFLR_MSB _u(4) +#define I2C_IC_TXFLR_TXFLR_LSB _u(0) #define I2C_IC_TXFLR_TXFLR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_RXFLR @@ -1809,19 +1837,19 @@ // IC_TX_ABRT_SOURCE The register increments whenever data is // placed into the receive FIFO and decrements when data is taken // from the receive FIFO. -#define I2C_IC_RXFLR_OFFSET 0x00000078 -#define I2C_IC_RXFLR_BITS 0x0000001f -#define I2C_IC_RXFLR_RESET 0x00000000 +#define I2C_IC_RXFLR_OFFSET _u(0x00000078) +#define I2C_IC_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RXFLR_RXFLR // Description : Receive FIFO Level. Contains the number of valid data entries // in the receive FIFO. // // Reset value: 0x0 -#define I2C_IC_RXFLR_RXFLR_RESET 0x00 -#define I2C_IC_RXFLR_RXFLR_BITS 0x0000001f -#define I2C_IC_RXFLR_RXFLR_MSB 4 -#define I2C_IC_RXFLR_RXFLR_LSB 0 +#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) +#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RXFLR_MSB _u(4) +#define I2C_IC_RXFLR_RXFLR_LSB _u(0) #define I2C_IC_RXFLR_RXFLR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_SDA_HOLD @@ -1839,27 +1867,27 @@ // // The values in this register are in units of ic_clk period. The // value programmed in IC_SDA_TX_HOLD must be greater than the -// minimum hold time in each mode one cycle in master mode, seven -// cycles in slave mode for the value to be implemented. +// minimum hold time in each mode (one cycle in master mode, seven +// cycles in slave mode) for the value to be implemented. // // The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) // cannot exceed at any time the duration of the low part of scl. // Therefore the programmed value cannot be larger than // N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of // the scl period measured in ic_clk cycles. -#define I2C_IC_SDA_HOLD_OFFSET 0x0000007c -#define I2C_IC_SDA_HOLD_BITS 0x00ffffff -#define I2C_IC_SDA_HOLD_RESET 0x00000001 +#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) +#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) +#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD // Description : Sets the required SDA hold time in units of ic_clk period, when // DW_apb_i2c acts as a receiver. // // Reset value: IC_DEFAULT_SDA_HOLD[23:16]. -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x00 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS 0x00ff0000 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) #define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD @@ -1867,10 +1895,10 @@ // DW_apb_i2c acts as a transmitter. // // Reset value: IC_DEFAULT_SDA_HOLD[15:0]. -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x0001 -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS 0x0000ffff -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15 -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) #define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" // ============================================================================= // Register : I2C_IC_TX_ABRT_SOURCE @@ -1889,9 +1917,9 @@ // register. If the source of the ABRT_SBYTE_NORSTRT is not fixed // before attempting to clear this bit, Bit 9 clears for one cycle // and is then re-asserted. -#define I2C_IC_TX_ABRT_SOURCE_OFFSET 0x00000080 -#define I2C_IC_TX_ABRT_SOURCE_BITS 0xff81ffff -#define I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000 +#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) +#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT // Description : This field indicates the number of Tx FIFO Data Commands which @@ -1901,10 +1929,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x000 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS 0xff800000 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) #define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT @@ -1916,13 +1944,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> Transfer abort detected by master- scenario not present // 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS 0x00010000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) #define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX // Description : 1: When the processor side responds to a slave mode request for @@ -1935,13 +1963,13 @@ // 0x0 -> Slave trying to transmit to remote master in read mode- // scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS 0x00008000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST // Description : This field indicates that a Slave has lost the bus while @@ -1959,13 +1987,13 @@ // 0x0 -> Slave lost arbitration to remote master- scenario not // present // 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS 0x00004000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO // Description : This field specifies that the Slave has received a read command @@ -1979,13 +2007,13 @@ // command- scenario not present // 0x1 -> Slave flushes existing data in TX-FIFO upon getting read // command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS 0x00002000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST // Description : This field specifies that the Master has lost arbitration, or @@ -1998,13 +2026,13 @@ // 0x0 -> Master or Slave-Transmitter lost arbitration- scenario // not present // 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS 0x00001000 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS // Description : This field indicates that the User tries to initiate a Master @@ -2016,13 +2044,13 @@ // 0x0 -> User initiating master operation when MASTER disabled- // scenario not present // 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS 0x00000800 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT // Description : This field indicates that the restart is disabled @@ -2036,13 +2064,13 @@ // RESTART disabled // 0x1 -> Master trying to read in 10Bit addressing mode when // RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS 0x00000400 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT // Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be @@ -2063,13 +2091,13 @@ // 0x0 -> User trying to send START byte when RESTART disabled- // scenario not present // 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS 0x00000200 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT // Description : This field indicates that the restart is disabled @@ -2083,13 +2111,13 @@ // disabled- scenario not present // 0x1 -> User trying to switch Master to HS mode when RESTART // disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS 0x00000100 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET // Description : This field indicates that the Master has sent a START Byte and @@ -2100,13 +2128,13 @@ // Role of DW_apb_i2c: Master // 0x0 -> ACK detected for START byte- scenario not present // 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS 0x00000080 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET // Description : This field indicates that the Master is in High Speed mode and @@ -2117,13 +2145,13 @@ // Role of DW_apb_i2c: Master // 0x0 -> HS Master code ACKed in HS Mode- scenario not present // 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS 0x00000040 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ // Description : This field indicates that DW_apb_i2c in the master mode has @@ -2136,13 +2164,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL is followed by read from bus-scenario not present // 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS 0x00000020 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK // Description : This field indicates that DW_apb_i2c in master mode has sent a @@ -2154,13 +2182,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL not ACKed by any slave-scenario not present // 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS 0x00000010 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK // Description : This field indicates the master-mode only bit. When the master @@ -2174,13 +2202,13 @@ // 0x0 -> Transmitted data non-ACKed by addressed slave-scenario // not present // 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS 0x00000008 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2192,13 +2220,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS 0x00000004 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2210,13 +2238,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS 0x00000002 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK // Description : This field indicates that the Master is in 7-bit addressing @@ -2228,13 +2256,13 @@ // 0x0 -> This abort is not generated // 0x1 -> This abort is generated because of NOACK for 7-bit // address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS 0x00000001 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_SLV_DATA_NACK_ONLY // Description : Generate Slave Data NACK Register @@ -2251,9 +2279,9 @@ // IC_STATUS[6] is a register read-back location for the internal // slv_activity signal; the user should poll this before writing // the ic_slv_data_nack_only bit. -#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x00000084 -#define I2C_IC_SLV_DATA_NACK_ONLY_BITS 0x00000001 -#define I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000 +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK // Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c @@ -2268,13 +2296,13 @@ // value: 0x0 // 0x0 -> Slave receiver generates NACK normally // 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS 0x00000001 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) #define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED 0x0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED 0x1 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_CR // Description : DMA Control Register @@ -2282,41 +2310,41 @@ // The register is used to enable the DMA Controller interface // operation. There is a separate bit for transmit and receive. // This can be programmed regardless of the state of IC_ENABLE. -#define I2C_IC_DMA_CR_OFFSET 0x00000088 -#define I2C_IC_DMA_CR_BITS 0x00000003 -#define I2C_IC_DMA_CR_RESET 0x00000000 +#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) +#define I2C_IC_DMA_CR_BITS _u(0x00000003) +#define I2C_IC_DMA_CR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_TDMAE // Description : Transmit DMA Enable. This bit enables/disables the transmit // FIFO DMA channel. Reset value: 0x0 // 0x0 -> transmit FIFO DMA channel disabled // 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET 0x0 -#define I2C_IC_DMA_CR_TDMAE_BITS 0x00000002 -#define I2C_IC_DMA_CR_TDMAE_MSB 1 -#define I2C_IC_DMA_CR_TDMAE_LSB 1 +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) #define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED 0x0 -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED 0x1 +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_RDMAE // Description : Receive DMA Enable. This bit enables/disables the receive FIFO // DMA channel. Reset value: 0x0 // 0x0 -> Receive FIFO DMA channel disabled // 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET 0x0 -#define I2C_IC_DMA_CR_RDMAE_BITS 0x00000001 -#define I2C_IC_DMA_CR_RDMAE_MSB 0 -#define I2C_IC_DMA_CR_RDMAE_LSB 0 +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) #define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED 0x0 -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED 0x1 +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_TDLR // Description : DMA Transmit Data Level Register -#define I2C_IC_DMA_TDLR_OFFSET 0x0000008c -#define I2C_IC_DMA_TDLR_BITS 0x0000000f -#define I2C_IC_DMA_TDLR_RESET 0x00000000 +#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) +#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_TDLR_DMATDL // Description : Transmit Data Level. This bit field controls the level at which @@ -2326,17 +2354,17 @@ // equal to or below this field value, and TDMAE = 1. // // Reset value: 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_RESET 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_BITS 0x0000000f -#define I2C_IC_DMA_TDLR_DMATDL_MSB 3 -#define I2C_IC_DMA_TDLR_DMATDL_LSB 0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) +#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) +#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) #define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_DMA_RDLR // Description : I2C Receive Data Level Register -#define I2C_IC_DMA_RDLR_OFFSET 0x00000090 -#define I2C_IC_DMA_RDLR_BITS 0x0000000f -#define I2C_IC_DMA_RDLR_RESET 0x00000000 +#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) +#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_RDLR_DMARDL // Description : Receive Data Level. This bit field controls the level at which @@ -2348,10 +2376,10 @@ // are present in the receive FIFO. // // Reset value: 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_RESET 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_BITS 0x0000000f -#define I2C_IC_DMA_RDLR_DMARDL_MSB 3 -#define I2C_IC_DMA_RDLR_DMARDL_LSB 0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) +#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) +#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) #define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SDA_SETUP @@ -2372,19 +2400,19 @@ // 10 ic_clk periods of setup time, they should program a value of // 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c // when operating as a slave transmitter. -#define I2C_IC_SDA_SETUP_OFFSET 0x00000094 -#define I2C_IC_SDA_SETUP_BITS 0x000000ff -#define I2C_IC_SDA_SETUP_RESET 0x00000064 +#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) +#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_SETUP_SDA_SETUP // Description : SDA Setup. It is recommended that if the required delay is // 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP // should be programmed to a value of 11. IC_SDA_SETUP must be // programmed with a minimum value of 2. -#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64 -#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS 0x000000ff -#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7 -#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0 +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) #define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" // ============================================================================= // Register : I2C_IC_ACK_GENERAL_CALL @@ -2395,9 +2423,9 @@ // // This register is applicable only when the DW_apb_i2c is in // slave mode. -#define I2C_IC_ACK_GENERAL_CALL_OFFSET 0x00000098 -#define I2C_IC_ACK_GENERAL_CALL_BITS 0x00000001 -#define I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) +#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL // Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK @@ -2406,13 +2434,13 @@ // ic_data_oe). // 0x0 -> Generate NACK for a General Call // 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS 0x00000001 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) #define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED 0x0 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED 0x1 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_ENABLE_STATUS // Description : I2C Enable Status Register @@ -2430,9 +2458,9 @@ // Note: When IC_ENABLE[0] has been set to 0, a delay occurs for // bit 0 to be read as 0 because disabling the DW_apb_i2c depends // on I2C bus activities. -#define I2C_IC_ENABLE_STATUS_OFFSET 0x0000009c -#define I2C_IC_ENABLE_STATUS_BITS 0x00000007 -#define I2C_IC_ENABLE_STATUS_RESET 0x00000000 +#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) +#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) +#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST // Description : Slave Received Data Lost. This bit indicates if a @@ -2459,13 +2487,13 @@ // Reset value: 0x0 // 0x0 -> Slave RX Data is not lost // 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS 0x00000004 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) #define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE 0x1 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY // Description : Slave Disabled While Busy (Transmit, Receive). This bit @@ -2502,13 +2530,13 @@ // Reset value: 0x0 // 0x0 -> Slave is disabled when it is idle // 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS 0x00000002 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) #define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE 0x1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_IC_EN // Description : ic_en Status. This bit always reflects the value driven on the @@ -2521,13 +2549,13 @@ // Reset value: 0x0 // 0x0 -> I2C disabled // 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS 0x00000001 -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB 0 -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) #define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED 0x0 -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_FS_SPKLEN // Description : I2C SS, FS or FM+ spike suppression limit @@ -2538,9 +2566,9 @@ // FM+ modes. The relevant I2C requirement is tSP (table 4) as // detailed in the I2C Bus Specification. This register must be // programmed with a minimum value of 1. -#define I2C_IC_FS_SPKLEN_OFFSET 0x000000a0 -#define I2C_IC_FS_SPKLEN_BITS 0x000000ff -#define I2C_IC_FS_SPKLEN_RESET 0x00000007 +#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) +#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN // Description : This register must be set before any I2C bus transaction can @@ -2553,27 +2581,27 @@ // The minimum valid value is 1; hardware prevents values less // than this being written, and if attempted results in 1 being // set. or more information, refer to 'Spike Suppression'. -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x07 -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS 0x000000ff -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7 -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) #define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" // ============================================================================= // Register : I2C_IC_CLR_RESTART_DET // Description : Clear RESTART_DET Interrupt Register -#define I2C_IC_CLR_RESTART_DET_OFFSET 0x000000a8 -#define I2C_IC_CLR_RESTART_DET_BITS 0x00000001 -#define I2C_IC_CLR_RESTART_DET_RESET 0x00000000 +#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) +#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET // Description : Read this register to clear the RESTART_DET interrupt (bit 12) // of IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS 0x00000001 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) #define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_PARAM_1 @@ -2584,102 +2612,102 @@ // that contains encoded information about the component's // parameter settings. Fields shown below are the settings for // those parameters -#define I2C_IC_COMP_PARAM_1_OFFSET 0x000000f4 -#define I2C_IC_COMP_PARAM_1_BITS 0x00ffffff -#define I2C_IC_COMP_PARAM_1_RESET 0x00000000 +#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) +#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) +#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH // Description : TX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x00 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS 0x00ff0000 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) #define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH // Description : RX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x00 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS 0x0000ff00 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) #define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS // Description : Encoded parameters not visible -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS 0x00000080 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) #define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_HAS_DMA // Description : DMA handshaking signals are enabled -#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS 0x00000040 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) #define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_INTR_IO // Description : COMBINED Interrupt outputs -#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS 0x00000020 -#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5 -#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) #define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES // Description : Programmable count values for each mode. -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS 0x00000010 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) #define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE // Description : MAX SPEED MODE = FAST MODE -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS 0x0000000c -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3 -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) #define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH // Description : APB data bus width is 32 bits -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS 0x00000003 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) #define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_VERSION // Description : I2C Component Version Register -#define I2C_IC_COMP_VERSION_OFFSET 0x000000f8 -#define I2C_IC_COMP_VERSION_BITS 0xffffffff -#define I2C_IC_COMP_VERSION_RESET 0x3230312a +#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) +#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION // Description : None -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230312a -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS 0xffffffff -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31 -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_TYPE // Description : I2C Component Type Register -#define I2C_IC_COMP_TYPE_OFFSET 0x000000fc -#define I2C_IC_COMP_TYPE_BITS 0xffffffff -#define I2C_IC_COMP_TYPE_RESET 0x44570140 +#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) +#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE // Description : Designware Component Type number = 0x44_57_01_40. This assigned // unique hex value is constant and is derived from the two ASCII // letters 'DW' followed by a 16-bit unsigned number. -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS 0xffffffff -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31 -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_I2C_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h index f7b15610c3a..26f139e36b3 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h @@ -14,111 +14,111 @@ // ============================================================================= // Register : IO_BANK0_GPIO0_STATUS // Description : GPIO status -#define IO_BANK0_GPIO0_STATUS_OFFSET 0x00000000 -#define IO_BANK0_GPIO0_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO0_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) +#define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO0_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO0_CTRL_OFFSET 0x00000004 -#define IO_BANK0_GPIO0_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO0_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) +#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -127,15 +127,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -143,15 +143,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -166,129 +166,129 @@ // 0x07 -> pio1_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK 0x00 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 0x05 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 0x06 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 0x07 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO1_STATUS // Description : GPIO status -#define IO_BANK0_GPIO1_STATUS_OFFSET 0x00000008 -#define IO_BANK0_GPIO1_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO1_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) +#define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO1_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO1_CTRL_OFFSET 0x0000000c -#define IO_BANK0_GPIO1_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO1_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) +#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -297,15 +297,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -313,15 +313,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -336,129 +336,129 @@ // 0x07 -> pio1_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS 0x00 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 0x05 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 0x06 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 0x07 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO2_STATUS // Description : GPIO status -#define IO_BANK0_GPIO2_STATUS_OFFSET 0x00000010 -#define IO_BANK0_GPIO2_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO2_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) +#define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO2_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO2_CTRL_OFFSET 0x00000014 -#define IO_BANK0_GPIO2_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO2_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) +#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -467,15 +467,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -483,15 +483,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -506,129 +506,129 @@ // 0x07 -> pio1_2 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI 0x00 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 0x05 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 0x06 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 0x07 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO3_STATUS // Description : GPIO status -#define IO_BANK0_GPIO3_STATUS_OFFSET 0x00000018 -#define IO_BANK0_GPIO3_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO3_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) +#define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO3_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO3_CTRL_OFFSET 0x0000001c -#define IO_BANK0_GPIO3_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO3_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) +#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -637,15 +637,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -653,15 +653,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -676,129 +676,129 @@ // 0x07 -> pio1_3 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO 0x00 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 0x05 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 0x06 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 0x07 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO4_STATUS // Description : GPIO status -#define IO_BANK0_GPIO4_STATUS_OFFSET 0x00000020 -#define IO_BANK0_GPIO4_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO4_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) +#define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO4_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO4_CTRL_OFFSET 0x00000024 -#define IO_BANK0_GPIO4_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO4_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) +#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -807,15 +807,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -823,15 +823,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -845,128 +845,128 @@ // 0x07 -> pio1_4 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 0x05 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 0x06 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 0x07 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO5_STATUS // Description : GPIO status -#define IO_BANK0_GPIO5_STATUS_OFFSET 0x00000028 -#define IO_BANK0_GPIO5_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO5_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) +#define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO5_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO5_CTRL_OFFSET 0x0000002c -#define IO_BANK0_GPIO5_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO5_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) +#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -975,15 +975,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -991,15 +991,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1013,128 +1013,128 @@ // 0x07 -> pio1_5 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 0x05 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 0x06 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 0x07 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO6_STATUS // Description : GPIO status -#define IO_BANK0_GPIO6_STATUS_OFFSET 0x00000030 -#define IO_BANK0_GPIO6_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO6_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) +#define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO6_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO6_CTRL_OFFSET 0x00000034 -#define IO_BANK0_GPIO6_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO6_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) +#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1143,15 +1143,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1159,15 +1159,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1182,129 +1182,129 @@ // 0x08 -> usb_muxing_extphy_softcon // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 0x05 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 0x06 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 0x07 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON 0x08 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO7_STATUS // Description : GPIO status -#define IO_BANK0_GPIO7_STATUS_OFFSET 0x00000038 -#define IO_BANK0_GPIO7_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO7_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) +#define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO7_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO7_CTRL_OFFSET 0x0000003c -#define IO_BANK0_GPIO7_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO7_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) +#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1313,15 +1313,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1329,15 +1329,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1352,129 +1352,129 @@ // 0x08 -> usb_muxing_extphy_oe_n // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 0x05 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 0x06 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 0x07 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N 0x08 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO8_STATUS // Description : GPIO status -#define IO_BANK0_GPIO8_STATUS_OFFSET 0x00000040 -#define IO_BANK0_GPIO8_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO8_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) +#define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO8_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO8_CTRL_OFFSET 0x00000044 -#define IO_BANK0_GPIO8_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO8_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) +#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1483,15 +1483,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1499,15 +1499,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1522,129 +1522,129 @@ // 0x08 -> usb_muxing_extphy_rcv // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 0x05 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 0x06 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 0x07 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV 0x08 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO9_STATUS // Description : GPIO status -#define IO_BANK0_GPIO9_STATUS_OFFSET 0x00000048 -#define IO_BANK0_GPIO9_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO9_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) +#define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO9_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO9_CTRL_OFFSET 0x0000004c -#define IO_BANK0_GPIO9_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO9_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) +#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1653,15 +1653,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1669,15 +1669,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1692,129 +1692,129 @@ // 0x08 -> usb_muxing_extphy_vp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 0x05 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 0x06 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 0x07 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP 0x08 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO10_STATUS // Description : GPIO status -#define IO_BANK0_GPIO10_STATUS_OFFSET 0x00000050 -#define IO_BANK0_GPIO10_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO10_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) +#define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO10_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO10_CTRL_OFFSET 0x00000054 -#define IO_BANK0_GPIO10_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO10_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) +#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1823,15 +1823,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1839,15 +1839,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1862,129 +1862,129 @@ // 0x08 -> usb_muxing_extphy_vm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 0x05 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 0x06 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 0x07 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM 0x08 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO11_STATUS // Description : GPIO status -#define IO_BANK0_GPIO11_STATUS_OFFSET 0x00000058 -#define IO_BANK0_GPIO11_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO11_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) +#define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO11_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO11_CTRL_OFFSET 0x0000005c -#define IO_BANK0_GPIO11_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO11_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) +#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1993,15 +1993,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2009,15 +2009,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2032,129 +2032,129 @@ // 0x08 -> usb_muxing_extphy_suspnd // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 0x05 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 0x06 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 0x07 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND 0x08 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO12_STATUS // Description : GPIO status -#define IO_BANK0_GPIO12_STATUS_OFFSET 0x00000060 -#define IO_BANK0_GPIO12_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO12_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) +#define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO12_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO12_CTRL_OFFSET 0x00000064 -#define IO_BANK0_GPIO12_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO12_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) +#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2163,15 +2163,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2179,15 +2179,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2202,129 +2202,129 @@ // 0x08 -> usb_muxing_extphy_speed // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 0x05 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 0x06 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 0x07 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED 0x08 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO13_STATUS // Description : GPIO status -#define IO_BANK0_GPIO13_STATUS_OFFSET 0x00000068 -#define IO_BANK0_GPIO13_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO13_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) +#define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO13_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO13_CTRL_OFFSET 0x0000006c -#define IO_BANK0_GPIO13_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO13_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) +#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2333,15 +2333,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2349,15 +2349,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2372,129 +2372,129 @@ // 0x08 -> usb_muxing_extphy_vpo // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 0x05 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 0x06 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 0x07 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO 0x08 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO14_STATUS // Description : GPIO status -#define IO_BANK0_GPIO14_STATUS_OFFSET 0x00000070 -#define IO_BANK0_GPIO14_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO14_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) +#define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO14_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO14_CTRL_OFFSET 0x00000074 -#define IO_BANK0_GPIO14_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO14_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) +#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2503,15 +2503,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2519,15 +2519,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2542,129 +2542,129 @@ // 0x08 -> usb_muxing_extphy_vmo // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 0x04 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 0x05 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 0x06 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 0x07 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO 0x08 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO15_STATUS // Description : GPIO status -#define IO_BANK0_GPIO15_STATUS_OFFSET 0x00000078 -#define IO_BANK0_GPIO15_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO15_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) +#define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO15_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO15_CTRL_OFFSET 0x0000007c -#define IO_BANK0_GPIO15_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO15_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) +#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2673,15 +2673,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2689,15 +2689,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2712,129 +2712,129 @@ // 0x08 -> usb_muxing_digital_dp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 0x04 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 0x05 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 0x06 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 0x07 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP 0x08 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO16_STATUS // Description : GPIO status -#define IO_BANK0_GPIO16_STATUS_OFFSET 0x00000080 -#define IO_BANK0_GPIO16_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO16_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) +#define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO16_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO16_CTRL_OFFSET 0x00000084 -#define IO_BANK0_GPIO16_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO16_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) +#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2843,15 +2843,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2859,15 +2859,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2882,129 +2882,129 @@ // 0x08 -> usb_muxing_digital_dm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 0x05 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 0x06 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 0x07 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM 0x08 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO17_STATUS // Description : GPIO status -#define IO_BANK0_GPIO17_STATUS_OFFSET 0x00000088 -#define IO_BANK0_GPIO17_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO17_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) +#define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO17_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO17_CTRL_OFFSET 0x0000008c -#define IO_BANK0_GPIO17_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO17_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) +#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3013,15 +3013,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3029,15 +3029,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3051,128 +3051,128 @@ // 0x07 -> pio1_17 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 0x05 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 0x06 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 0x07 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO18_STATUS // Description : GPIO status -#define IO_BANK0_GPIO18_STATUS_OFFSET 0x00000090 -#define IO_BANK0_GPIO18_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO18_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) +#define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO18_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO18_CTRL_OFFSET 0x00000094 -#define IO_BANK0_GPIO18_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO18_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) +#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3181,15 +3181,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3197,15 +3197,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3219,128 +3219,128 @@ // 0x07 -> pio1_18 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 0x05 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 0x06 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 0x07 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO19_STATUS // Description : GPIO status -#define IO_BANK0_GPIO19_STATUS_OFFSET 0x00000098 -#define IO_BANK0_GPIO19_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO19_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) +#define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO19_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO19_CTRL_OFFSET 0x0000009c -#define IO_BANK0_GPIO19_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO19_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) +#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3349,15 +3349,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3365,15 +3365,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3387,128 +3387,128 @@ // 0x07 -> pio1_19 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 0x05 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 0x06 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 0x07 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO20_STATUS // Description : GPIO status -#define IO_BANK0_GPIO20_STATUS_OFFSET 0x000000a0 -#define IO_BANK0_GPIO20_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO20_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) +#define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO20_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO20_CTRL_OFFSET 0x000000a4 -#define IO_BANK0_GPIO20_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO20_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) +#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3517,15 +3517,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3533,15 +3533,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3556,129 +3556,129 @@ // 0x08 -> clocks_gpin_0 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 0x05 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 0x06 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 0x07 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 0x08 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO21_STATUS // Description : GPIO status -#define IO_BANK0_GPIO21_STATUS_OFFSET 0x000000a8 -#define IO_BANK0_GPIO21_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO21_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) +#define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO21_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO21_CTRL_OFFSET 0x000000ac -#define IO_BANK0_GPIO21_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO21_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) +#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3687,15 +3687,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3703,15 +3703,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3726,129 +3726,129 @@ // 0x08 -> clocks_gpout_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 0x05 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 0x06 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 0x07 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 0x08 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO22_STATUS // Description : GPIO status -#define IO_BANK0_GPIO22_STATUS_OFFSET 0x000000b0 -#define IO_BANK0_GPIO22_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO22_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) +#define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO22_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO22_CTRL_OFFSET 0x000000b4 -#define IO_BANK0_GPIO22_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO22_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) +#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3857,15 +3857,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3873,15 +3873,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3896,129 +3896,129 @@ // 0x08 -> clocks_gpin_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 0x05 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 0x06 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 0x07 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 0x08 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO23_STATUS // Description : GPIO status -#define IO_BANK0_GPIO23_STATUS_OFFSET 0x000000b8 -#define IO_BANK0_GPIO23_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO23_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) +#define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO23_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO23_CTRL_OFFSET 0x000000bc -#define IO_BANK0_GPIO23_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO23_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) +#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4027,15 +4027,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4043,15 +4043,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4066,129 +4066,129 @@ // 0x08 -> clocks_gpout_1 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 0x05 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 0x06 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 0x07 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 0x08 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO24_STATUS // Description : GPIO status -#define IO_BANK0_GPIO24_STATUS_OFFSET 0x000000c0 -#define IO_BANK0_GPIO24_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO24_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) +#define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO24_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO24_CTRL_OFFSET 0x000000c4 -#define IO_BANK0_GPIO24_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO24_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) +#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4197,15 +4197,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4213,15 +4213,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4236,129 +4236,129 @@ // 0x08 -> clocks_gpout_2 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 0x05 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 0x06 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 0x07 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 0x08 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO25_STATUS // Description : GPIO status -#define IO_BANK0_GPIO25_STATUS_OFFSET 0x000000c8 -#define IO_BANK0_GPIO25_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO25_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) +#define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO25_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO25_CTRL_OFFSET 0x000000cc -#define IO_BANK0_GPIO25_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO25_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) +#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4367,15 +4367,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4383,15 +4383,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4406,129 +4406,129 @@ // 0x08 -> clocks_gpout_3 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 0x05 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 0x06 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 0x07 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 0x08 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO26_STATUS // Description : GPIO status -#define IO_BANK0_GPIO26_STATUS_OFFSET 0x000000d0 -#define IO_BANK0_GPIO26_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO26_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) +#define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO26_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO26_CTRL_OFFSET 0x000000d4 -#define IO_BANK0_GPIO26_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO26_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) +#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4537,15 +4537,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4553,15 +4553,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4575,128 +4575,128 @@ // 0x07 -> pio1_26 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 0x05 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 0x06 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 0x07 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO27_STATUS // Description : GPIO status -#define IO_BANK0_GPIO27_STATUS_OFFSET 0x000000d8 -#define IO_BANK0_GPIO27_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO27_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) +#define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO27_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO27_CTRL_OFFSET 0x000000dc -#define IO_BANK0_GPIO27_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO27_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) +#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4705,15 +4705,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4721,15 +4721,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4743,128 +4743,128 @@ // 0x07 -> pio1_27 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 0x05 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 0x06 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 0x07 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO28_STATUS // Description : GPIO status -#define IO_BANK0_GPIO28_STATUS_OFFSET 0x000000e0 -#define IO_BANK0_GPIO28_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO28_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) +#define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO28_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO28_CTRL_OFFSET 0x000000e4 -#define IO_BANK0_GPIO28_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO28_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) +#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4873,15 +4873,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4889,15 +4889,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4911,128 +4911,128 @@ // 0x07 -> pio1_28 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 0x05 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 0x06 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 0x07 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO29_STATUS // Description : GPIO status -#define IO_BANK0_GPIO29_STATUS_OFFSET 0x000000e8 -#define IO_BANK0_GPIO29_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO29_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) +#define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO29_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO29_CTRL_OFFSET 0x000000ec -#define IO_BANK0_GPIO29_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO29_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) +#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -5041,15 +5041,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -5057,15 +5057,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -5079,9859 +5079,9859 @@ // 0x07 -> pio1_29 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 0x05 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 0x06 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 0x07 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_INTR0 // Description : Raw Interrupts -#define IO_BANK0_INTR0_OFFSET 0x000000f0 -#define IO_BANK0_INTR0_BITS 0xffffffff -#define IO_BANK0_INTR0_RESET 0x00000000 +#define IO_BANK0_INTR0_OFFSET _u(0x000000f0) +#define IO_BANK0_INTR0_BITS _u(0xffffffff) +#define IO_BANK0_INTR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR1 // Description : Raw Interrupts -#define IO_BANK0_INTR1_OFFSET 0x000000f4 -#define IO_BANK0_INTR1_BITS 0xffffffff -#define IO_BANK0_INTR1_RESET 0x00000000 +#define IO_BANK0_INTR1_OFFSET _u(0x000000f4) +#define IO_BANK0_INTR1_BITS _u(0xffffffff) +#define IO_BANK0_INTR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR2 // Description : Raw Interrupts -#define IO_BANK0_INTR2_OFFSET 0x000000f8 -#define IO_BANK0_INTR2_BITS 0xffffffff -#define IO_BANK0_INTR2_RESET 0x00000000 +#define IO_BANK0_INTR2_OFFSET _u(0x000000f8) +#define IO_BANK0_INTR2_BITS _u(0xffffffff) +#define IO_BANK0_INTR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR3 // Description : Raw Interrupts -#define IO_BANK0_INTR3_OFFSET 0x000000fc -#define IO_BANK0_INTR3_BITS 0x00ffffff -#define IO_BANK0_INTR3_RESET 0x00000000 +#define IO_BANK0_INTR3_OFFSET _u(0x000000fc) +#define IO_BANK0_INTR3_BITS _u(0x00ffffff) +#define IO_BANK0_INTR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTE0 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE0_OFFSET 0x00000100 -#define IO_BANK0_PROC0_INTE0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE1 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE1_OFFSET 0x00000104 -#define IO_BANK0_PROC0_INTE1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104) +#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE2 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE2_OFFSET 0x00000108 -#define IO_BANK0_PROC0_INTE2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108) +#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE3 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE3_OFFSET 0x0000010c -#define IO_BANK0_PROC0_INTE3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTE3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c) +#define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF0 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF0_OFFSET 0x00000110 -#define IO_BANK0_PROC0_INTF0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110) +#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF1 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF1_OFFSET 0x00000114 -#define IO_BANK0_PROC0_INTF1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114) +#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF2 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF2_OFFSET 0x00000118 -#define IO_BANK0_PROC0_INTF2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118) +#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF3 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF3_OFFSET 0x0000011c -#define IO_BANK0_PROC0_INTF3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTF3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c) +#define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTS0 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS0_OFFSET 0x00000120 -#define IO_BANK0_PROC0_INTS0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120) +#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS1 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS1_OFFSET 0x00000124 -#define IO_BANK0_PROC0_INTS1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124) +#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS2 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS2_OFFSET 0x00000128 -#define IO_BANK0_PROC0_INTS2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128) +#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS3 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS3_OFFSET 0x0000012c -#define IO_BANK0_PROC0_INTS3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTS3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c) +#define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTE0 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE0_OFFSET 0x00000130 -#define IO_BANK0_PROC1_INTE0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130) +#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE1 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE1_OFFSET 0x00000134 -#define IO_BANK0_PROC1_INTE1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134) +#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE2 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE2_OFFSET 0x00000138 -#define IO_BANK0_PROC1_INTE2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138) +#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE3 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE3_OFFSET 0x0000013c -#define IO_BANK0_PROC1_INTE3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTE3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c) +#define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF0 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF0_OFFSET 0x00000140 -#define IO_BANK0_PROC1_INTF0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140) +#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF1 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF1_OFFSET 0x00000144 -#define IO_BANK0_PROC1_INTF1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144) +#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF2 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF2_OFFSET 0x00000148 -#define IO_BANK0_PROC1_INTF2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148) +#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF3 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF3_OFFSET 0x0000014c -#define IO_BANK0_PROC1_INTF3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTF3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c) +#define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTS0 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS0_OFFSET 0x00000150 -#define IO_BANK0_PROC1_INTS0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150) +#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS1 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS1_OFFSET 0x00000154 -#define IO_BANK0_PROC1_INTS1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154) +#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS2 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS2_OFFSET 0x00000158 -#define IO_BANK0_PROC1_INTS2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158) +#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS3 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS3_OFFSET 0x0000015c -#define IO_BANK0_PROC1_INTS3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTS3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c) +#define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE0 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET 0x00000160 -#define IO_BANK0_DORMANT_WAKE_INTE0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160) +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE1 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET 0x00000164 -#define IO_BANK0_DORMANT_WAKE_INTE1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164) +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE2 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET 0x00000168 -#define IO_BANK0_DORMANT_WAKE_INTE2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168) +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE3 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET 0x0000016c -#define IO_BANK0_DORMANT_WAKE_INTE3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTE3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c) +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF0 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET 0x00000170 -#define IO_BANK0_DORMANT_WAKE_INTF0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170) +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF1 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET 0x00000174 -#define IO_BANK0_DORMANT_WAKE_INTF1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174) +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF2 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET 0x00000178 -#define IO_BANK0_DORMANT_WAKE_INTF2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178) +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF3 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET 0x0000017c -#define IO_BANK0_DORMANT_WAKE_INTF3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTF3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c) +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS0 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET 0x00000180 -#define IO_BANK0_DORMANT_WAKE_INTS0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180) +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS1 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET 0x00000184 -#define IO_BANK0_DORMANT_WAKE_INTS1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184) +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS2 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET 0x00000188 -#define IO_BANK0_DORMANT_WAKE_INTS2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188) +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS3 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET 0x0000018c -#define IO_BANK0_DORMANT_WAKE_INTS3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTS3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c) +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_IO_BANK0_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h index 0c7c88d5329..7c381b7a51b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h @@ -14,111 +14,111 @@ // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET 0x00000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET 0x00000004 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -127,15 +127,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -143,15 +143,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -159,122 +159,122 @@ // 0x00 -> xip_sclk // 0x05 -> sio_30 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK 0x00 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 0x05 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET 0x00000008 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET 0x0000000c -#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -283,15 +283,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -299,15 +299,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -315,122 +315,122 @@ // 0x00 -> xip_ss_n // 0x05 -> sio_31 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N 0x00 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 0x05 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET 0x00000010 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET 0x00000014 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -439,15 +439,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -455,15 +455,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -471,122 +471,122 @@ // 0x00 -> xip_sd0 // 0x05 -> sio_32 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 0x00 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 0x05 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET 0x00000018 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET 0x0000001c -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -595,15 +595,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -611,15 +611,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -627,122 +627,122 @@ // 0x00 -> xip_sd1 // 0x05 -> sio_33 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 0x00 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 0x05 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET 0x00000020 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET 0x00000024 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -751,15 +751,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -767,15 +767,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -783,122 +783,122 @@ // 0x00 -> xip_sd2 // 0x05 -> sio_34 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 0x00 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 0x05 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET 0x00000028 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET 0x0000002c -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -907,15 +907,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -923,15 +923,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -939,1993 +939,1993 @@ // 0x00 -> xip_sd3 // 0x05 -> sio_35 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 0x00 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 0x05 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_INTR // Description : Raw Interrupts -#define IO_QSPI_INTR_OFFSET 0x00000030 -#define IO_QSPI_INTR_BITS 0x00ffffff -#define IO_QSPI_INTR_RESET 0x00000000 +#define IO_QSPI_INTR_OFFSET _u(0x00000030) +#define IO_QSPI_INTR_BITS _u(0x00ffffff) +#define IO_QSPI_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_PROC0_INTE // Description : Interrupt Enable for proc0 -#define IO_QSPI_PROC0_INTE_OFFSET 0x00000034 -#define IO_QSPI_PROC0_INTE_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTE_RESET 0x00000000 +#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034) +#define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC0_INTF // Description : Interrupt Force for proc0 -#define IO_QSPI_PROC0_INTF_OFFSET 0x00000038 -#define IO_QSPI_PROC0_INTF_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTF_RESET 0x00000000 +#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038) +#define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC0_INTS // Description : Interrupt status after masking & forcing for proc0 -#define IO_QSPI_PROC0_INTS_OFFSET 0x0000003c -#define IO_QSPI_PROC0_INTS_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTS_RESET 0x00000000 +#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c) +#define IO_QSPI_PROC0_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_PROC1_INTE // Description : Interrupt Enable for proc1 -#define IO_QSPI_PROC1_INTE_OFFSET 0x00000040 -#define IO_QSPI_PROC1_INTE_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTE_RESET 0x00000000 +#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040) +#define IO_QSPI_PROC1_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC1_INTF // Description : Interrupt Force for proc1 -#define IO_QSPI_PROC1_INTF_OFFSET 0x00000044 -#define IO_QSPI_PROC1_INTF_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTF_RESET 0x00000000 +#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044) +#define IO_QSPI_PROC1_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC1_INTS // Description : Interrupt status after masking & forcing for proc1 -#define IO_QSPI_PROC1_INTS_OFFSET 0x00000048 -#define IO_QSPI_PROC1_INTS_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTS_RESET 0x00000000 +#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048) +#define IO_QSPI_PROC1_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTE // Description : Interrupt Enable for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET 0x0000004c -#define IO_QSPI_DORMANT_WAKE_INTE_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTE_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c) +#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTF // Description : Interrupt Force for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET 0x00000050 -#define IO_QSPI_DORMANT_WAKE_INTF_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTF_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050) +#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTS // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET 0x00000054 -#define IO_QSPI_DORMANT_WAKE_INTS_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTS_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054) +#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_IO_QSPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h index fac8e8b55bc..cef5ab0a1fc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h @@ -15,17 +15,17 @@ // Register : M0PLUS_SYST_CSR // Description : Use the SysTick Control and Status Register to enable the // SysTick features. -#define M0PLUS_SYST_CSR_OFFSET 0x0000e010 -#define M0PLUS_SYST_CSR_BITS 0x00010007 -#define M0PLUS_SYST_CSR_RESET 0x00000000 +#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010) +#define M0PLUS_SYST_CSR_BITS _u(0x00010007) +#define M0PLUS_SYST_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_COUNTFLAG // Description : Returns 1 if timer counted to 0 since last time this was read. // Clears on read by application or debugger. -#define M0PLUS_SYST_CSR_COUNTFLAG_RESET 0x0 -#define M0PLUS_SYST_CSR_COUNTFLAG_BITS 0x00010000 -#define M0PLUS_SYST_CSR_COUNTFLAG_MSB 16 -#define M0PLUS_SYST_CSR_COUNTFLAG_LSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0) +#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) +#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16) +#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16) #define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_CLKSOURCE @@ -34,10 +34,10 @@ // Selects the SysTick timer clock source: // 0 = External reference clock. // 1 = Processor clock. -#define M0PLUS_SYST_CSR_CLKSOURCE_RESET 0x0 -#define M0PLUS_SYST_CSR_CLKSOURCE_BITS 0x00000004 -#define M0PLUS_SYST_CSR_CLKSOURCE_MSB 2 -#define M0PLUS_SYST_CSR_CLKSOURCE_LSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0) +#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) +#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2) +#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2) #define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_TICKINT @@ -46,20 +46,20 @@ // request. // 1 = Counting down to zero to asserts the SysTick exception // request. -#define M0PLUS_SYST_CSR_TICKINT_RESET 0x0 -#define M0PLUS_SYST_CSR_TICKINT_BITS 0x00000002 -#define M0PLUS_SYST_CSR_TICKINT_MSB 1 -#define M0PLUS_SYST_CSR_TICKINT_LSB 1 +#define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0) +#define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002) +#define M0PLUS_SYST_CSR_TICKINT_MSB _u(1) +#define M0PLUS_SYST_CSR_TICKINT_LSB _u(1) #define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_ENABLE // Description : Enable SysTick counter: // 0 = Counter disabled. // 1 = Counter enabled. -#define M0PLUS_SYST_CSR_ENABLE_RESET 0x0 -#define M0PLUS_SYST_CSR_ENABLE_BITS 0x00000001 -#define M0PLUS_SYST_CSR_ENABLE_MSB 0 -#define M0PLUS_SYST_CSR_ENABLE_LSB 0 +#define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0) +#define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001) +#define M0PLUS_SYST_CSR_ENABLE_MSB _u(0) +#define M0PLUS_SYST_CSR_ENABLE_LSB _u(0) #define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_RVR @@ -73,72 +73,72 @@ // clock cycles, use a RELOAD value of N-1. For example, if the // SysTick interrupt is required every 100 clock pulses, set // RELOAD to 99. -#define M0PLUS_SYST_RVR_OFFSET 0x0000e014 -#define M0PLUS_SYST_RVR_BITS 0x00ffffff -#define M0PLUS_SYST_RVR_RESET 0x00000000 +#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014) +#define M0PLUS_SYST_RVR_BITS _u(0x00ffffff) +#define M0PLUS_SYST_RVR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_RVR_RELOAD // Description : Value to load into the SysTick Current Value Register when the // counter reaches 0. -#define M0PLUS_SYST_RVR_RELOAD_RESET 0x000000 -#define M0PLUS_SYST_RVR_RELOAD_BITS 0x00ffffff -#define M0PLUS_SYST_RVR_RELOAD_MSB 23 -#define M0PLUS_SYST_RVR_RELOAD_LSB 0 +#define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000) +#define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff) +#define M0PLUS_SYST_RVR_RELOAD_MSB _u(23) +#define M0PLUS_SYST_RVR_RELOAD_LSB _u(0) #define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_CVR // Description : Use the SysTick Current Value Register to find the current // value in the register. The reset value of this register is // UNKNOWN. -#define M0PLUS_SYST_CVR_OFFSET 0x0000e018 -#define M0PLUS_SYST_CVR_BITS 0x00ffffff -#define M0PLUS_SYST_CVR_RESET 0x00000000 +#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018) +#define M0PLUS_SYST_CVR_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CVR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CVR_CURRENT // Description : Reads return the current value of the SysTick counter. This // register is write-clear. Writing to it with any value clears // the register to 0. Clearing this register also clears the // COUNTFLAG bit of the SysTick Control and Status Register. -#define M0PLUS_SYST_CVR_CURRENT_RESET 0x000000 -#define M0PLUS_SYST_CVR_CURRENT_BITS 0x00ffffff -#define M0PLUS_SYST_CVR_CURRENT_MSB 23 -#define M0PLUS_SYST_CVR_CURRENT_LSB 0 +#define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000) +#define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CVR_CURRENT_MSB _u(23) +#define M0PLUS_SYST_CVR_CURRENT_LSB _u(0) #define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_CALIB // Description : Use the SysTick Calibration Value Register to enable software // to scale to any required speed using divide and multiply. -#define M0PLUS_SYST_CALIB_OFFSET 0x0000e01c -#define M0PLUS_SYST_CALIB_BITS 0xc0ffffff -#define M0PLUS_SYST_CALIB_RESET 0x00000000 +#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c) +#define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff) +#define M0PLUS_SYST_CALIB_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_NOREF // Description : If reads as 1, the Reference clock is not provided - the // CLKSOURCE bit of the SysTick Control and Status register will // be forced to 1 and cannot be cleared to 0. -#define M0PLUS_SYST_CALIB_NOREF_RESET 0x0 -#define M0PLUS_SYST_CALIB_NOREF_BITS 0x80000000 -#define M0PLUS_SYST_CALIB_NOREF_MSB 31 -#define M0PLUS_SYST_CALIB_NOREF_LSB 31 +#define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0) +#define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000) +#define M0PLUS_SYST_CALIB_NOREF_MSB _u(31) +#define M0PLUS_SYST_CALIB_NOREF_LSB _u(31) #define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_SKEW // Description : If reads as 1, the calibration value for 10ms is inexact (due // to clock frequency). -#define M0PLUS_SYST_CALIB_SKEW_RESET 0x0 -#define M0PLUS_SYST_CALIB_SKEW_BITS 0x40000000 -#define M0PLUS_SYST_CALIB_SKEW_MSB 30 -#define M0PLUS_SYST_CALIB_SKEW_LSB 30 +#define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0) +#define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000) +#define M0PLUS_SYST_CALIB_SKEW_MSB _u(30) +#define M0PLUS_SYST_CALIB_SKEW_LSB _u(30) #define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_TENMS // Description : An optional Reload value to be used for 10ms (100Hz) timing, // subject to system clock skew errors. If the value reads as 0, // the calibration value is not known. -#define M0PLUS_SYST_CALIB_TENMS_RESET 0x000000 -#define M0PLUS_SYST_CALIB_TENMS_BITS 0x00ffffff -#define M0PLUS_SYST_CALIB_TENMS_MSB 23 -#define M0PLUS_SYST_CALIB_TENMS_LSB 0 +#define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000) +#define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CALIB_TENMS_MSB _u(23) +#define M0PLUS_SYST_CALIB_TENMS_LSB _u(0) #define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" // ============================================================================= // Register : M0PLUS_NVIC_ISER @@ -149,9 +149,9 @@ // enabled, asserting its interrupt signal changes the interrupt // state to pending, but the NVIC never activates the interrupt, // regardless of its priority. -#define M0PLUS_NVIC_ISER_OFFSET 0x0000e100 -#define M0PLUS_NVIC_ISER_BITS 0xffffffff -#define M0PLUS_NVIC_ISER_RESET 0x00000000 +#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100) +#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ISER_SETENA // Description : Interrupt set-enable bits. @@ -161,18 +161,18 @@ // Read: // 0 = Interrupt disabled. // 1 = Interrupt enabled. -#define M0PLUS_NVIC_ISER_SETENA_RESET 0x00000000 -#define M0PLUS_NVIC_ISER_SETENA_BITS 0xffffffff -#define M0PLUS_NVIC_ISER_SETENA_MSB 31 -#define M0PLUS_NVIC_ISER_SETENA_LSB 0 +#define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000) +#define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISER_SETENA_MSB _u(31) +#define M0PLUS_NVIC_ISER_SETENA_LSB _u(0) #define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ICER // Description : Use the Interrupt Clear-Enable Registers to disable interrupts // and determine which interrupts are currently enabled. -#define M0PLUS_NVIC_ICER_OFFSET 0x0000e180 -#define M0PLUS_NVIC_ICER_BITS 0xffffffff -#define M0PLUS_NVIC_ICER_RESET 0x00000000 +#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180) +#define M0PLUS_NVIC_ICER_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ICER_CLRENA // Description : Interrupt clear-enable bits. @@ -182,18 +182,18 @@ // Read: // 0 = Interrupt disabled. // 1 = Interrupt enabled. -#define M0PLUS_NVIC_ICER_CLRENA_RESET 0x00000000 -#define M0PLUS_NVIC_ICER_CLRENA_BITS 0xffffffff -#define M0PLUS_NVIC_ICER_CLRENA_MSB 31 -#define M0PLUS_NVIC_ICER_CLRENA_LSB 0 +#define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000) +#define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31) +#define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0) #define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ISPR // Description : The NVIC_ISPR forces interrupts into the pending state, and // shows which interrupts are pending. -#define M0PLUS_NVIC_ISPR_OFFSET 0x0000e200 -#define M0PLUS_NVIC_ISPR_BITS 0xffffffff -#define M0PLUS_NVIC_ISPR_RESET 0x00000000 +#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200) +#define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ISPR_SETPEND // Description : Interrupt set-pending bits. @@ -207,19 +207,19 @@ // An interrupt that is pending has no effect. // A disabled interrupt sets the state of that interrupt to // pending. -#define M0PLUS_NVIC_ISPR_SETPEND_RESET 0x00000000 -#define M0PLUS_NVIC_ISPR_SETPEND_BITS 0xffffffff -#define M0PLUS_NVIC_ISPR_SETPEND_MSB 31 -#define M0PLUS_NVIC_ISPR_SETPEND_LSB 0 +#define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000) +#define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31) +#define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0) #define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ICPR // Description : Use the Interrupt Clear-Pending Register to clear pending // interrupts and determine which interrupts are currently // pending. -#define M0PLUS_NVIC_ICPR_OFFSET 0x0000e280 -#define M0PLUS_NVIC_ICPR_BITS 0xffffffff -#define M0PLUS_NVIC_ICPR_RESET 0x00000000 +#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280) +#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ICPR_CLRPEND // Description : Interrupt clear-pending bits. @@ -229,10 +229,10 @@ // Read: // 0 = Interrupt is not pending. // 1 = Interrupt is pending. -#define M0PLUS_NVIC_ICPR_CLRPEND_RESET 0x00000000 -#define M0PLUS_NVIC_ICPR_CLRPEND_BITS 0xffffffff -#define M0PLUS_NVIC_ICPR_CLRPEND_MSB 31 -#define M0PLUS_NVIC_ICPR_CLRPEND_LSB 0 +#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000) +#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31) +#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0) #define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR0 @@ -242,371 +242,371 @@ // Note: Writing 1 to an NVIC_ICPR bit does not affect the active // state of the corresponding interrupt. // These registers are only word-accessible -#define M0PLUS_NVIC_IPR0_OFFSET 0x0000e400 -#define M0PLUS_NVIC_IPR0_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR0_RESET 0x00000000 +#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400) +#define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_3 // Description : Priority of interrupt 3 -#define M0PLUS_NVIC_IPR0_IP_3_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_3_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR0_IP_3_MSB 31 -#define M0PLUS_NVIC_IPR0_IP_3_LSB 30 +#define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31) +#define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30) #define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_2 // Description : Priority of interrupt 2 -#define M0PLUS_NVIC_IPR0_IP_2_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_2_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR0_IP_2_MSB 23 -#define M0PLUS_NVIC_IPR0_IP_2_LSB 22 +#define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23) +#define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22) #define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_1 // Description : Priority of interrupt 1 -#define M0PLUS_NVIC_IPR0_IP_1_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_1_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR0_IP_1_MSB 15 -#define M0PLUS_NVIC_IPR0_IP_1_LSB 14 +#define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15) +#define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14) #define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_0 // Description : Priority of interrupt 0 -#define M0PLUS_NVIC_IPR0_IP_0_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_0_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR0_IP_0_MSB 7 -#define M0PLUS_NVIC_IPR0_IP_0_LSB 6 +#define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7) +#define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6) #define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR1 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR1_OFFSET 0x0000e404 -#define M0PLUS_NVIC_IPR1_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR1_RESET 0x00000000 +#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404) +#define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_7 // Description : Priority of interrupt 7 -#define M0PLUS_NVIC_IPR1_IP_7_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_7_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR1_IP_7_MSB 31 -#define M0PLUS_NVIC_IPR1_IP_7_LSB 30 +#define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31) +#define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30) #define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_6 // Description : Priority of interrupt 6 -#define M0PLUS_NVIC_IPR1_IP_6_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_6_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR1_IP_6_MSB 23 -#define M0PLUS_NVIC_IPR1_IP_6_LSB 22 +#define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23) +#define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22) #define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_5 // Description : Priority of interrupt 5 -#define M0PLUS_NVIC_IPR1_IP_5_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_5_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR1_IP_5_MSB 15 -#define M0PLUS_NVIC_IPR1_IP_5_LSB 14 +#define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15) +#define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14) #define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_4 // Description : Priority of interrupt 4 -#define M0PLUS_NVIC_IPR1_IP_4_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_4_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR1_IP_4_MSB 7 -#define M0PLUS_NVIC_IPR1_IP_4_LSB 6 +#define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7) +#define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6) #define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR2 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR2_OFFSET 0x0000e408 -#define M0PLUS_NVIC_IPR2_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR2_RESET 0x00000000 +#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408) +#define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_11 // Description : Priority of interrupt 11 -#define M0PLUS_NVIC_IPR2_IP_11_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_11_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR2_IP_11_MSB 31 -#define M0PLUS_NVIC_IPR2_IP_11_LSB 30 +#define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31) +#define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30) #define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_10 // Description : Priority of interrupt 10 -#define M0PLUS_NVIC_IPR2_IP_10_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_10_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR2_IP_10_MSB 23 -#define M0PLUS_NVIC_IPR2_IP_10_LSB 22 +#define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23) +#define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22) #define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_9 // Description : Priority of interrupt 9 -#define M0PLUS_NVIC_IPR2_IP_9_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_9_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR2_IP_9_MSB 15 -#define M0PLUS_NVIC_IPR2_IP_9_LSB 14 +#define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15) +#define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14) #define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_8 // Description : Priority of interrupt 8 -#define M0PLUS_NVIC_IPR2_IP_8_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_8_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR2_IP_8_MSB 7 -#define M0PLUS_NVIC_IPR2_IP_8_LSB 6 +#define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7) +#define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6) #define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR3 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR3_OFFSET 0x0000e40c -#define M0PLUS_NVIC_IPR3_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR3_RESET 0x00000000 +#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c) +#define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_15 // Description : Priority of interrupt 15 -#define M0PLUS_NVIC_IPR3_IP_15_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_15_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR3_IP_15_MSB 31 -#define M0PLUS_NVIC_IPR3_IP_15_LSB 30 +#define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31) +#define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30) #define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_14 // Description : Priority of interrupt 14 -#define M0PLUS_NVIC_IPR3_IP_14_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_14_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR3_IP_14_MSB 23 -#define M0PLUS_NVIC_IPR3_IP_14_LSB 22 +#define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23) +#define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22) #define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_13 // Description : Priority of interrupt 13 -#define M0PLUS_NVIC_IPR3_IP_13_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_13_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR3_IP_13_MSB 15 -#define M0PLUS_NVIC_IPR3_IP_13_LSB 14 +#define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15) +#define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14) #define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_12 // Description : Priority of interrupt 12 -#define M0PLUS_NVIC_IPR3_IP_12_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_12_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR3_IP_12_MSB 7 -#define M0PLUS_NVIC_IPR3_IP_12_LSB 6 +#define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7) +#define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6) #define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR4 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR4_OFFSET 0x0000e410 -#define M0PLUS_NVIC_IPR4_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR4_RESET 0x00000000 +#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410) +#define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR4_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_19 // Description : Priority of interrupt 19 -#define M0PLUS_NVIC_IPR4_IP_19_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_19_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR4_IP_19_MSB 31 -#define M0PLUS_NVIC_IPR4_IP_19_LSB 30 +#define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31) +#define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30) #define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_18 // Description : Priority of interrupt 18 -#define M0PLUS_NVIC_IPR4_IP_18_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_18_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR4_IP_18_MSB 23 -#define M0PLUS_NVIC_IPR4_IP_18_LSB 22 +#define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23) +#define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22) #define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_17 // Description : Priority of interrupt 17 -#define M0PLUS_NVIC_IPR4_IP_17_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_17_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR4_IP_17_MSB 15 -#define M0PLUS_NVIC_IPR4_IP_17_LSB 14 +#define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15) +#define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14) #define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_16 // Description : Priority of interrupt 16 -#define M0PLUS_NVIC_IPR4_IP_16_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_16_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR4_IP_16_MSB 7 -#define M0PLUS_NVIC_IPR4_IP_16_LSB 6 +#define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7) +#define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6) #define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR5 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR5_OFFSET 0x0000e414 -#define M0PLUS_NVIC_IPR5_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR5_RESET 0x00000000 +#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414) +#define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR5_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_23 // Description : Priority of interrupt 23 -#define M0PLUS_NVIC_IPR5_IP_23_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_23_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR5_IP_23_MSB 31 -#define M0PLUS_NVIC_IPR5_IP_23_LSB 30 +#define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31) +#define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30) #define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_22 // Description : Priority of interrupt 22 -#define M0PLUS_NVIC_IPR5_IP_22_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_22_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR5_IP_22_MSB 23 -#define M0PLUS_NVIC_IPR5_IP_22_LSB 22 +#define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23) +#define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22) #define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_21 // Description : Priority of interrupt 21 -#define M0PLUS_NVIC_IPR5_IP_21_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_21_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR5_IP_21_MSB 15 -#define M0PLUS_NVIC_IPR5_IP_21_LSB 14 +#define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15) +#define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14) #define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_20 // Description : Priority of interrupt 20 -#define M0PLUS_NVIC_IPR5_IP_20_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_20_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR5_IP_20_MSB 7 -#define M0PLUS_NVIC_IPR5_IP_20_LSB 6 +#define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7) +#define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6) #define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR6 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR6_OFFSET 0x0000e418 -#define M0PLUS_NVIC_IPR6_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR6_RESET 0x00000000 +#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418) +#define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR6_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_27 // Description : Priority of interrupt 27 -#define M0PLUS_NVIC_IPR6_IP_27_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_27_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR6_IP_27_MSB 31 -#define M0PLUS_NVIC_IPR6_IP_27_LSB 30 +#define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31) +#define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30) #define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_26 // Description : Priority of interrupt 26 -#define M0PLUS_NVIC_IPR6_IP_26_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_26_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR6_IP_26_MSB 23 -#define M0PLUS_NVIC_IPR6_IP_26_LSB 22 +#define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23) +#define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22) #define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_25 // Description : Priority of interrupt 25 -#define M0PLUS_NVIC_IPR6_IP_25_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_25_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR6_IP_25_MSB 15 -#define M0PLUS_NVIC_IPR6_IP_25_LSB 14 +#define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15) +#define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14) #define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_24 // Description : Priority of interrupt 24 -#define M0PLUS_NVIC_IPR6_IP_24_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_24_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR6_IP_24_MSB 7 -#define M0PLUS_NVIC_IPR6_IP_24_LSB 6 +#define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7) +#define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6) #define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR7 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR7_OFFSET 0x0000e41c -#define M0PLUS_NVIC_IPR7_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR7_RESET 0x00000000 +#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c) +#define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR7_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_31 // Description : Priority of interrupt 31 -#define M0PLUS_NVIC_IPR7_IP_31_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_31_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR7_IP_31_MSB 31 -#define M0PLUS_NVIC_IPR7_IP_31_LSB 30 +#define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31) +#define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30) #define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_30 // Description : Priority of interrupt 30 -#define M0PLUS_NVIC_IPR7_IP_30_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_30_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR7_IP_30_MSB 23 -#define M0PLUS_NVIC_IPR7_IP_30_LSB 22 +#define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23) +#define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22) #define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_29 // Description : Priority of interrupt 29 -#define M0PLUS_NVIC_IPR7_IP_29_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_29_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR7_IP_29_MSB 15 -#define M0PLUS_NVIC_IPR7_IP_29_LSB 14 +#define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15) +#define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14) #define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_28 // Description : Priority of interrupt 28 -#define M0PLUS_NVIC_IPR7_IP_28_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_28_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR7_IP_28_MSB 7 -#define M0PLUS_NVIC_IPR7_IP_28_LSB 6 +#define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7) +#define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6) #define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" // ============================================================================= // Register : M0PLUS_CPUID // Description : Read the CPU ID Base Register to determine: the ID number of // the processor core, the version number of the processor core, // the implementation details of the processor core. -#define M0PLUS_CPUID_OFFSET 0x0000ed00 -#define M0PLUS_CPUID_BITS 0xffffffff -#define M0PLUS_CPUID_RESET 0x410cc601 +#define M0PLUS_CPUID_OFFSET _u(0x0000ed00) +#define M0PLUS_CPUID_BITS _u(0xffffffff) +#define M0PLUS_CPUID_RESET _u(0x410cc601) // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_IMPLEMENTER // Description : Implementor code: 0x41 = ARM -#define M0PLUS_CPUID_IMPLEMENTER_RESET 0x41 -#define M0PLUS_CPUID_IMPLEMENTER_BITS 0xff000000 -#define M0PLUS_CPUID_IMPLEMENTER_MSB 31 -#define M0PLUS_CPUID_IMPLEMENTER_LSB 24 +#define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41) +#define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000) +#define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31) +#define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24) #define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_VARIANT // Description : Major revision number n in the rnpm revision status: // 0x0 = Revision 0. -#define M0PLUS_CPUID_VARIANT_RESET 0x0 -#define M0PLUS_CPUID_VARIANT_BITS 0x00f00000 -#define M0PLUS_CPUID_VARIANT_MSB 23 -#define M0PLUS_CPUID_VARIANT_LSB 20 +#define M0PLUS_CPUID_VARIANT_RESET _u(0x0) +#define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000) +#define M0PLUS_CPUID_VARIANT_MSB _u(23) +#define M0PLUS_CPUID_VARIANT_LSB _u(20) #define M0PLUS_CPUID_VARIANT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_ARCHITECTURE // Description : Constant that defines the architecture of the processor: // 0xC = ARMv6-M architecture. -#define M0PLUS_CPUID_ARCHITECTURE_RESET 0xc -#define M0PLUS_CPUID_ARCHITECTURE_BITS 0x000f0000 -#define M0PLUS_CPUID_ARCHITECTURE_MSB 19 -#define M0PLUS_CPUID_ARCHITECTURE_LSB 16 +#define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc) +#define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000) +#define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19) +#define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16) #define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_PARTNO // Description : Number of processor within family: 0xC60 = Cortex-M0+ -#define M0PLUS_CPUID_PARTNO_RESET 0xc60 -#define M0PLUS_CPUID_PARTNO_BITS 0x0000fff0 -#define M0PLUS_CPUID_PARTNO_MSB 15 -#define M0PLUS_CPUID_PARTNO_LSB 4 +#define M0PLUS_CPUID_PARTNO_RESET _u(0xc60) +#define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0) +#define M0PLUS_CPUID_PARTNO_MSB _u(15) +#define M0PLUS_CPUID_PARTNO_LSB _u(4) #define M0PLUS_CPUID_PARTNO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_REVISION // Description : Minor revision number m in the rnpm revision status: // 0x1 = Patch 1. -#define M0PLUS_CPUID_REVISION_RESET 0x1 -#define M0PLUS_CPUID_REVISION_BITS 0x0000000f -#define M0PLUS_CPUID_REVISION_MSB 3 -#define M0PLUS_CPUID_REVISION_LSB 0 +#define M0PLUS_CPUID_REVISION_RESET _u(0x1) +#define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f) +#define M0PLUS_CPUID_REVISION_MSB _u(3) +#define M0PLUS_CPUID_REVISION_LSB _u(0) #define M0PLUS_CPUID_REVISION_ACCESS "RO" // ============================================================================= // Register : M0PLUS_ICSR @@ -615,9 +615,9 @@ // set or clear a pending SysTick, check for pending exceptions, // check the vector number of the highest priority pended // exception, check the vector number of the active exception. -#define M0PLUS_ICSR_OFFSET 0x0000ed04 -#define M0PLUS_ICSR_BITS 0x9edff1ff -#define M0PLUS_ICSR_RESET 0x00000000 +#define M0PLUS_ICSR_OFFSET _u(0x0000ed04) +#define M0PLUS_ICSR_BITS _u(0x9edff1ff) +#define M0PLUS_ICSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_NMIPENDSET // Description : Setting this bit will activate an NMI. Since NMI is the highest @@ -638,10 +638,10 @@ // exception handler returns 1 only if the // NMI signal is reasserted while the processor is executing that // handler. -#define M0PLUS_ICSR_NMIPENDSET_RESET 0x0 -#define M0PLUS_ICSR_NMIPENDSET_BITS 0x80000000 -#define M0PLUS_ICSR_NMIPENDSET_MSB 31 -#define M0PLUS_ICSR_NMIPENDSET_LSB 31 +#define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0) +#define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000) +#define M0PLUS_ICSR_NMIPENDSET_MSB _u(31) +#define M0PLUS_ICSR_NMIPENDSET_LSB _u(31) #define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSVSET @@ -654,10 +654,10 @@ // 1 = PendSV exception is pending. // Writing 1 to this bit is the only way to set the PendSV // exception state to pending. -#define M0PLUS_ICSR_PENDSVSET_RESET 0x0 -#define M0PLUS_ICSR_PENDSVSET_BITS 0x10000000 -#define M0PLUS_ICSR_PENDSVSET_MSB 28 -#define M0PLUS_ICSR_PENDSVSET_LSB 28 +#define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000) +#define M0PLUS_ICSR_PENDSVSET_MSB _u(28) +#define M0PLUS_ICSR_PENDSVSET_LSB _u(28) #define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSVCLR @@ -665,10 +665,10 @@ // Write: // 0 = No effect. // 1 = Removes the pending state from the PendSV exception. -#define M0PLUS_ICSR_PENDSVCLR_RESET 0x0 -#define M0PLUS_ICSR_PENDSVCLR_BITS 0x08000000 -#define M0PLUS_ICSR_PENDSVCLR_MSB 27 -#define M0PLUS_ICSR_PENDSVCLR_LSB 27 +#define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000) +#define M0PLUS_ICSR_PENDSVCLR_MSB _u(27) +#define M0PLUS_ICSR_PENDSVCLR_LSB _u(27) #define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSTSET @@ -679,10 +679,10 @@ // Read: // 0 = SysTick exception is not pending. // 1 = SysTick exception is pending. -#define M0PLUS_ICSR_PENDSTSET_RESET 0x0 -#define M0PLUS_ICSR_PENDSTSET_BITS 0x04000000 -#define M0PLUS_ICSR_PENDSTSET_MSB 26 -#define M0PLUS_ICSR_PENDSTSET_LSB 26 +#define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000) +#define M0PLUS_ICSR_PENDSTSET_MSB _u(26) +#define M0PLUS_ICSR_PENDSTSET_LSB _u(26) #define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSTCLR @@ -691,10 +691,10 @@ // 0 = No effect. // 1 = Removes the pending state from the SysTick exception. // This bit is WO. On a register read its value is Unknown. -#define M0PLUS_ICSR_PENDSTCLR_RESET 0x0 -#define M0PLUS_ICSR_PENDSTCLR_BITS 0x02000000 -#define M0PLUS_ICSR_PENDSTCLR_MSB 25 -#define M0PLUS_ICSR_PENDSTCLR_LSB 25 +#define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000) +#define M0PLUS_ICSR_PENDSTCLR_MSB _u(25) +#define M0PLUS_ICSR_PENDSTCLR_LSB _u(25) #define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_ISRPREEMPT @@ -702,18 +702,18 @@ // indicates that a pending interrupt is to be taken in the next // running cycle. If C_MASKINTS is clear in the Debug Halting // Control and Status Register, the interrupt is serviced. -#define M0PLUS_ICSR_ISRPREEMPT_RESET 0x0 -#define M0PLUS_ICSR_ISRPREEMPT_BITS 0x00800000 -#define M0PLUS_ICSR_ISRPREEMPT_MSB 23 -#define M0PLUS_ICSR_ISRPREEMPT_LSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0) +#define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000) +#define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23) +#define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23) #define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_ISRPENDING // Description : External interrupt pending flag -#define M0PLUS_ICSR_ISRPENDING_RESET 0x0 -#define M0PLUS_ICSR_ISRPENDING_BITS 0x00400000 -#define M0PLUS_ICSR_ISRPENDING_MSB 22 -#define M0PLUS_ICSR_ISRPENDING_LSB 22 +#define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0) +#define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000) +#define M0PLUS_ICSR_ISRPENDING_MSB _u(22) +#define M0PLUS_ICSR_ISRPENDING_LSB _u(22) #define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_VECTPENDING @@ -722,61 +722,61 @@ // state includes the effect of memory-mapped enable and mask // registers. It does not include the PRIMASK special-purpose // register qualifier. -#define M0PLUS_ICSR_VECTPENDING_RESET 0x000 -#define M0PLUS_ICSR_VECTPENDING_BITS 0x001ff000 -#define M0PLUS_ICSR_VECTPENDING_MSB 20 -#define M0PLUS_ICSR_VECTPENDING_LSB 12 +#define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000) +#define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000) +#define M0PLUS_ICSR_VECTPENDING_MSB _u(20) +#define M0PLUS_ICSR_VECTPENDING_LSB _u(12) #define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_VECTACTIVE // Description : Active exception number field. Reset clears the VECTACTIVE // field. -#define M0PLUS_ICSR_VECTACTIVE_RESET 0x000 -#define M0PLUS_ICSR_VECTACTIVE_BITS 0x000001ff -#define M0PLUS_ICSR_VECTACTIVE_MSB 8 -#define M0PLUS_ICSR_VECTACTIVE_LSB 0 +#define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000) +#define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff) +#define M0PLUS_ICSR_VECTACTIVE_MSB _u(8) +#define M0PLUS_ICSR_VECTACTIVE_LSB _u(0) #define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" // ============================================================================= // Register : M0PLUS_VTOR // Description : The VTOR holds the vector table offset address. -#define M0PLUS_VTOR_OFFSET 0x0000ed08 -#define M0PLUS_VTOR_BITS 0xffffff00 -#define M0PLUS_VTOR_RESET 0x00000000 +#define M0PLUS_VTOR_OFFSET _u(0x0000ed08) +#define M0PLUS_VTOR_BITS _u(0xffffff00) +#define M0PLUS_VTOR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_VTOR_TBLOFF // Description : Bits [31:8] of the indicate the vector table offset address. -#define M0PLUS_VTOR_TBLOFF_RESET 0x000000 -#define M0PLUS_VTOR_TBLOFF_BITS 0xffffff00 -#define M0PLUS_VTOR_TBLOFF_MSB 31 -#define M0PLUS_VTOR_TBLOFF_LSB 8 +#define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000) +#define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00) +#define M0PLUS_VTOR_TBLOFF_MSB _u(31) +#define M0PLUS_VTOR_TBLOFF_LSB _u(8) #define M0PLUS_VTOR_TBLOFF_ACCESS "RW" // ============================================================================= // Register : M0PLUS_AIRCR // Description : Use the Application Interrupt and Reset Control Register to: // determine data endianness, clear all active state information // from debug halt mode, request a system reset. -#define M0PLUS_AIRCR_OFFSET 0x0000ed0c -#define M0PLUS_AIRCR_BITS 0xffff8006 -#define M0PLUS_AIRCR_RESET 0x00000000 +#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c) +#define M0PLUS_AIRCR_BITS _u(0xffff8006) +#define M0PLUS_AIRCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_VECTKEY // Description : Register key: // Reads as Unknown // On writes, write 0x05FA to VECTKEY, otherwise the write is // ignored. -#define M0PLUS_AIRCR_VECTKEY_RESET 0x0000 -#define M0PLUS_AIRCR_VECTKEY_BITS 0xffff0000 -#define M0PLUS_AIRCR_VECTKEY_MSB 31 -#define M0PLUS_AIRCR_VECTKEY_LSB 16 +#define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000) +#define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000) +#define M0PLUS_AIRCR_VECTKEY_MSB _u(31) +#define M0PLUS_AIRCR_VECTKEY_LSB _u(16) #define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_ENDIANESS // Description : Data endianness implemented: // 0 = Little-endian. -#define M0PLUS_AIRCR_ENDIANESS_RESET 0x0 -#define M0PLUS_AIRCR_ENDIANESS_BITS 0x00008000 -#define M0PLUS_AIRCR_ENDIANESS_MSB 15 -#define M0PLUS_AIRCR_ENDIANESS_LSB 15 +#define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0) +#define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000) +#define M0PLUS_AIRCR_ENDIANESS_MSB _u(15) +#define M0PLUS_AIRCR_ENDIANESS_LSB _u(15) #define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_SYSRESETREQ @@ -786,10 +786,10 @@ // for debug. The C_HALT bit in the DHCSR is cleared as a result // of the system reset requested. The debugger does not lose // contact with the device. -#define M0PLUS_AIRCR_SYSRESETREQ_RESET 0x0 -#define M0PLUS_AIRCR_SYSRESETREQ_BITS 0x00000004 -#define M0PLUS_AIRCR_SYSRESETREQ_MSB 2 -#define M0PLUS_AIRCR_SYSRESETREQ_LSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0) +#define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004) +#define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2) +#define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2) #define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_VECTCLRACTIVE @@ -799,10 +799,10 @@ // exception status of the processor, forces a return to Thread // mode, forces an IPSR of 0. A debugger must re-initialize the // stack. -#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET 0x0 -#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS 0x00000002 -#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB 1 -#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0) +#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) +#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1) +#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1) #define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SCR @@ -810,9 +810,9 @@ // power-management functions: signal to the system when the // processor can enter a low power state, control how the // processor enters and exits low power states. -#define M0PLUS_SCR_OFFSET 0x0000ed10 -#define M0PLUS_SCR_BITS 0x00000016 -#define M0PLUS_SCR_RESET 0x00000000 +#define M0PLUS_SCR_OFFSET _u(0x0000ed10) +#define M0PLUS_SCR_BITS _u(0x00000016) +#define M0PLUS_SCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SEVONPEND // Description : Send Event on Pending bit: @@ -826,10 +826,10 @@ // and affects the next WFE. // The processor also wakes up on execution of an SEV instruction // or an external event. -#define M0PLUS_SCR_SEVONPEND_RESET 0x0 -#define M0PLUS_SCR_SEVONPEND_BITS 0x00000010 -#define M0PLUS_SCR_SEVONPEND_MSB 4 -#define M0PLUS_SCR_SEVONPEND_LSB 4 +#define M0PLUS_SCR_SEVONPEND_RESET _u(0x0) +#define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010) +#define M0PLUS_SCR_SEVONPEND_MSB _u(4) +#define M0PLUS_SCR_SEVONPEND_LSB _u(4) #define M0PLUS_SCR_SEVONPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SLEEPDEEP @@ -837,10 +837,10 @@ // low power mode: // 0 = Sleep. // 1 = Deep sleep. -#define M0PLUS_SCR_SLEEPDEEP_RESET 0x0 -#define M0PLUS_SCR_SLEEPDEEP_BITS 0x00000004 -#define M0PLUS_SCR_SLEEPDEEP_MSB 2 -#define M0PLUS_SCR_SLEEPDEEP_LSB 2 +#define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0) +#define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004) +#define M0PLUS_SCR_SLEEPDEEP_MSB _u(2) +#define M0PLUS_SCR_SLEEPDEEP_LSB _u(2) #define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SLEEPONEXIT @@ -851,19 +851,19 @@ // mode. // Setting this bit to 1 enables an interrupt driven application // to avoid returning to an empty main application. -#define M0PLUS_SCR_SLEEPONEXIT_RESET 0x0 -#define M0PLUS_SCR_SLEEPONEXIT_BITS 0x00000002 -#define M0PLUS_SCR_SLEEPONEXIT_MSB 1 -#define M0PLUS_SCR_SLEEPONEXIT_LSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0) +#define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002) +#define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1) +#define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1) #define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" // ============================================================================= // Register : M0PLUS_CCR // Description : The Configuration and Control Register permanently enables // stack alignment and causes unaligned accesses to result in a // Hard Fault. -#define M0PLUS_CCR_OFFSET 0x0000ed14 -#define M0PLUS_CCR_BITS 0x00000208 -#define M0PLUS_CCR_RESET 0x00000000 +#define M0PLUS_CCR_OFFSET _u(0x0000ed14) +#define M0PLUS_CCR_BITS _u(0x00000208) +#define M0PLUS_CCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_CCR_STKALIGN // Description : Always reads as one, indicates 8-byte stack alignment on @@ -871,19 +871,19 @@ // of the stacked PSR to indicate the stack alignment. On return // from the exception it uses this stacked bit to restore the // correct stack alignment. -#define M0PLUS_CCR_STKALIGN_RESET 0x0 -#define M0PLUS_CCR_STKALIGN_BITS 0x00000200 -#define M0PLUS_CCR_STKALIGN_MSB 9 -#define M0PLUS_CCR_STKALIGN_LSB 9 +#define M0PLUS_CCR_STKALIGN_RESET _u(0x0) +#define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200) +#define M0PLUS_CCR_STKALIGN_MSB _u(9) +#define M0PLUS_CCR_STKALIGN_LSB _u(9) #define M0PLUS_CCR_STKALIGN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CCR_UNALIGN_TRP // Description : Always reads as one, indicates that all unaligned accesses // generate a HardFault. -#define M0PLUS_CCR_UNALIGN_TRP_RESET 0x0 -#define M0PLUS_CCR_UNALIGN_TRP_BITS 0x00000008 -#define M0PLUS_CCR_UNALIGN_TRP_MSB 3 -#define M0PLUS_CCR_UNALIGN_TRP_LSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0) +#define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008) +#define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3) +#define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3) #define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" // ============================================================================= // Register : M0PLUS_SHPR2 @@ -891,16 +891,16 @@ // can have their priority set to any of the priority levels. Use // the System Handler Priority Register 2 to set the priority of // SVCall. -#define M0PLUS_SHPR2_OFFSET 0x0000ed1c -#define M0PLUS_SHPR2_BITS 0xc0000000 -#define M0PLUS_SHPR2_RESET 0x00000000 +#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c) +#define M0PLUS_SHPR2_BITS _u(0xc0000000) +#define M0PLUS_SHPR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR2_PRI_11 // Description : Priority of system handler 11, SVCall -#define M0PLUS_SHPR2_PRI_11_RESET 0x0 -#define M0PLUS_SHPR2_PRI_11_BITS 0xc0000000 -#define M0PLUS_SHPR2_PRI_11_MSB 31 -#define M0PLUS_SHPR2_PRI_11_LSB 30 +#define M0PLUS_SHPR2_PRI_11_RESET _u(0x0) +#define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000) +#define M0PLUS_SHPR2_PRI_11_MSB _u(31) +#define M0PLUS_SHPR2_PRI_11_LSB _u(30) #define M0PLUS_SHPR2_PRI_11_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SHPR3 @@ -908,73 +908,73 @@ // can have their priority set to any of the priority levels. Use // the System Handler Priority Register 3 to set the priority of // PendSV and SysTick. -#define M0PLUS_SHPR3_OFFSET 0x0000ed20 -#define M0PLUS_SHPR3_BITS 0xc0c00000 -#define M0PLUS_SHPR3_RESET 0x00000000 +#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20) +#define M0PLUS_SHPR3_BITS _u(0xc0c00000) +#define M0PLUS_SHPR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR3_PRI_15 // Description : Priority of system handler 15, SysTick -#define M0PLUS_SHPR3_PRI_15_RESET 0x0 -#define M0PLUS_SHPR3_PRI_15_BITS 0xc0000000 -#define M0PLUS_SHPR3_PRI_15_MSB 31 -#define M0PLUS_SHPR3_PRI_15_LSB 30 +#define M0PLUS_SHPR3_PRI_15_RESET _u(0x0) +#define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000) +#define M0PLUS_SHPR3_PRI_15_MSB _u(31) +#define M0PLUS_SHPR3_PRI_15_LSB _u(30) #define M0PLUS_SHPR3_PRI_15_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR3_PRI_14 // Description : Priority of system handler 14, PendSV -#define M0PLUS_SHPR3_PRI_14_RESET 0x0 -#define M0PLUS_SHPR3_PRI_14_BITS 0x00c00000 -#define M0PLUS_SHPR3_PRI_14_MSB 23 -#define M0PLUS_SHPR3_PRI_14_LSB 22 +#define M0PLUS_SHPR3_PRI_14_RESET _u(0x0) +#define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000) +#define M0PLUS_SHPR3_PRI_14_MSB _u(23) +#define M0PLUS_SHPR3_PRI_14_LSB _u(22) #define M0PLUS_SHPR3_PRI_14_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SHCSR // Description : Use the System Handler Control and State Register to determine // or clear the pending status of SVCall. -#define M0PLUS_SHCSR_OFFSET 0x0000ed24 -#define M0PLUS_SHCSR_BITS 0x00008000 -#define M0PLUS_SHCSR_RESET 0x00000000 +#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24) +#define M0PLUS_SHCSR_BITS _u(0x00008000) +#define M0PLUS_SHCSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHCSR_SVCALLPENDED // Description : Reads as 1 if SVCall is Pending. Write 1 to set pending // SVCall, write 0 to clear pending SVCall. -#define M0PLUS_SHCSR_SVCALLPENDED_RESET 0x0 -#define M0PLUS_SHCSR_SVCALLPENDED_BITS 0x00008000 -#define M0PLUS_SHCSR_SVCALLPENDED_MSB 15 -#define M0PLUS_SHCSR_SVCALLPENDED_LSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0) +#define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000) +#define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15) +#define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15) #define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_TYPE // Description : Read the MPU Type Register to determine if the processor // implements an MPU, and how many regions the MPU supports. -#define M0PLUS_MPU_TYPE_OFFSET 0x0000ed90 -#define M0PLUS_MPU_TYPE_BITS 0x00ffff01 -#define M0PLUS_MPU_TYPE_RESET 0x00000800 +#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90) +#define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01) +#define M0PLUS_MPU_TYPE_RESET _u(0x00000800) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_IREGION // Description : Instruction region. Reads as zero as ARMv6-M only supports a // unified MPU. -#define M0PLUS_MPU_TYPE_IREGION_RESET 0x00 -#define M0PLUS_MPU_TYPE_IREGION_BITS 0x00ff0000 -#define M0PLUS_MPU_TYPE_IREGION_MSB 23 -#define M0PLUS_MPU_TYPE_IREGION_LSB 16 +#define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00) +#define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000) +#define M0PLUS_MPU_TYPE_IREGION_MSB _u(23) +#define M0PLUS_MPU_TYPE_IREGION_LSB _u(16) #define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_DREGION // Description : Number of regions supported by the MPU. -#define M0PLUS_MPU_TYPE_DREGION_RESET 0x08 -#define M0PLUS_MPU_TYPE_DREGION_BITS 0x0000ff00 -#define M0PLUS_MPU_TYPE_DREGION_MSB 15 -#define M0PLUS_MPU_TYPE_DREGION_LSB 8 +#define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08) +#define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00) +#define M0PLUS_MPU_TYPE_DREGION_MSB _u(15) +#define M0PLUS_MPU_TYPE_DREGION_LSB _u(8) #define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_SEPARATE // Description : Indicates support for separate instruction and data address // maps. Reads as 0 as ARMv6-M only supports a unified MPU. -#define M0PLUS_MPU_TYPE_SEPARATE_RESET 0x0 -#define M0PLUS_MPU_TYPE_SEPARATE_BITS 0x00000001 -#define M0PLUS_MPU_TYPE_SEPARATE_MSB 0 -#define M0PLUS_MPU_TYPE_SEPARATE_LSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0) +#define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001) +#define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0) +#define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0) #define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" // ============================================================================= // Register : M0PLUS_MPU_CTRL @@ -982,9 +982,9 @@ // to control whether the default memory map is enabled as a // background region for privileged accesses, and whether the MPU // is enabled for HardFaults and NMIs. -#define M0PLUS_MPU_CTRL_OFFSET 0x0000ed94 -#define M0PLUS_MPU_CTRL_BITS 0x00000007 -#define M0PLUS_MPU_CTRL_RESET 0x00000000 +#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94) +#define M0PLUS_MPU_CTRL_BITS _u(0x00000007) +#define M0PLUS_MPU_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_PRIVDEFENA // Description : Controls whether the default memory map is enabled as a @@ -998,10 +998,10 @@ // When enabled, the background region acts as if it is region // number -1. Any region that is defined and enabled has priority // over this default map. -#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET 0x0 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS 0x00000004 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB 2 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2) #define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_HFNMIENA @@ -1012,10 +1012,10 @@ // 0 = MPU is disabled during HardFault and NMI handlers, // regardless of the value of the ENABLE bit. // 1 = the MPU is enabled during HardFault and NMI handlers. -#define M0PLUS_MPU_CTRL_HFNMIENA_RESET 0x0 -#define M0PLUS_MPU_CTRL_HFNMIENA_BITS 0x00000002 -#define M0PLUS_MPU_CTRL_HFNMIENA_MSB 1 -#define M0PLUS_MPU_CTRL_HFNMIENA_LSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) +#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1) +#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1) #define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_ENABLE @@ -1023,28 +1023,28 @@ // unprivileged accesses use the default memory map. // 0 = MPU disabled. // 1 = MPU enabled. -#define M0PLUS_MPU_CTRL_ENABLE_RESET 0x0 -#define M0PLUS_MPU_CTRL_ENABLE_BITS 0x00000001 -#define M0PLUS_MPU_CTRL_ENABLE_MSB 0 -#define M0PLUS_MPU_CTRL_ENABLE_LSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001) +#define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0) +#define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0) #define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RNR // Description : Use the MPU Region Number Register to select the region // currently accessed by MPU_RBAR and MPU_RASR. -#define M0PLUS_MPU_RNR_OFFSET 0x0000ed98 -#define M0PLUS_MPU_RNR_BITS 0x0000000f -#define M0PLUS_MPU_RNR_RESET 0x00000000 +#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98) +#define M0PLUS_MPU_RNR_BITS _u(0x0000000f) +#define M0PLUS_MPU_RNR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RNR_REGION // Description : Indicates the MPU region referenced by the MPU_RBAR and // MPU_RASR registers. // The MPU supports 8 memory regions, so the permitted values of // this field are 0-7. -#define M0PLUS_MPU_RNR_REGION_RESET 0x0 -#define M0PLUS_MPU_RNR_REGION_BITS 0x0000000f -#define M0PLUS_MPU_RNR_REGION_MSB 3 -#define M0PLUS_MPU_RNR_REGION_LSB 0 +#define M0PLUS_MPU_RNR_REGION_RESET _u(0x0) +#define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f) +#define M0PLUS_MPU_RNR_REGION_MSB _u(3) +#define M0PLUS_MPU_RNR_REGION_LSB _u(0) #define M0PLUS_MPU_RNR_REGION_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RBAR @@ -1052,16 +1052,16 @@ // address of the region identified by MPU_RNR. Write to update // the base address of said region or that of a specified region, // with whose number MPU_RNR will also be updated. -#define M0PLUS_MPU_RBAR_OFFSET 0x0000ed9c -#define M0PLUS_MPU_RBAR_BITS 0xffffff1f -#define M0PLUS_MPU_RBAR_RESET 0x00000000 +#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c) +#define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f) +#define M0PLUS_MPU_RBAR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_ADDR // Description : Base address of the region. -#define M0PLUS_MPU_RBAR_ADDR_RESET 0x000000 -#define M0PLUS_MPU_RBAR_ADDR_BITS 0xffffff00 -#define M0PLUS_MPU_RBAR_ADDR_MSB 31 -#define M0PLUS_MPU_RBAR_ADDR_LSB 8 +#define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000) +#define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00) +#define M0PLUS_MPU_RBAR_ADDR_MSB _u(31) +#define M0PLUS_MPU_RBAR_ADDR_LSB _u(8) #define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_VALID @@ -1079,29 +1079,29 @@ // Updates the base address for the region specified in the REGION // field. // Always reads as zero. -#define M0PLUS_MPU_RBAR_VALID_RESET 0x0 -#define M0PLUS_MPU_RBAR_VALID_BITS 0x00000010 -#define M0PLUS_MPU_RBAR_VALID_MSB 4 -#define M0PLUS_MPU_RBAR_VALID_LSB 4 +#define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0) +#define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010) +#define M0PLUS_MPU_RBAR_VALID_MSB _u(4) +#define M0PLUS_MPU_RBAR_VALID_LSB _u(4) #define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_REGION // Description : On writes, specifies the number of the region whose base // address to update provided VALID is set written as 1. On reads, // returns bits [3:0] of MPU_RNR. -#define M0PLUS_MPU_RBAR_REGION_RESET 0x0 -#define M0PLUS_MPU_RBAR_REGION_BITS 0x0000000f -#define M0PLUS_MPU_RBAR_REGION_MSB 3 -#define M0PLUS_MPU_RBAR_REGION_LSB 0 +#define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0) +#define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f) +#define M0PLUS_MPU_RBAR_REGION_MSB _u(3) +#define M0PLUS_MPU_RBAR_REGION_LSB _u(0) #define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RASR // Description : Use the MPU Region Attribute and Size Register to define the // size, access behaviour and memory type of the region identified // by MPU_RNR, and enable that region. -#define M0PLUS_MPU_RASR_OFFSET 0x0000eda0 -#define M0PLUS_MPU_RASR_BITS 0xffffff3f -#define M0PLUS_MPU_RASR_RESET 0x00000000 +#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0) +#define M0PLUS_MPU_RASR_BITS _u(0xffffff3f) +#define M0PLUS_MPU_RASR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_ATTRS // Description : The MPU Region Attribute field. Use to define the region @@ -1113,37 +1113,37 @@ // 18 = S: Shareable bit // 17 = C: Cacheable bit // 16 = B: Bufferable bit -#define M0PLUS_MPU_RASR_ATTRS_RESET 0x0000 -#define M0PLUS_MPU_RASR_ATTRS_BITS 0xffff0000 -#define M0PLUS_MPU_RASR_ATTRS_MSB 31 -#define M0PLUS_MPU_RASR_ATTRS_LSB 16 +#define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000) +#define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000) +#define M0PLUS_MPU_RASR_ATTRS_MSB _u(31) +#define M0PLUS_MPU_RASR_ATTRS_LSB _u(16) #define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_SRD // Description : Subregion Disable. For regions of 256 bytes or larger, each bit // of this field controls whether one of the eight equal // subregions is enabled. -#define M0PLUS_MPU_RASR_SRD_RESET 0x00 -#define M0PLUS_MPU_RASR_SRD_BITS 0x0000ff00 -#define M0PLUS_MPU_RASR_SRD_MSB 15 -#define M0PLUS_MPU_RASR_SRD_LSB 8 +#define M0PLUS_MPU_RASR_SRD_RESET _u(0x00) +#define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00) +#define M0PLUS_MPU_RASR_SRD_MSB _u(15) +#define M0PLUS_MPU_RASR_SRD_LSB _u(8) #define M0PLUS_MPU_RASR_SRD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_SIZE // Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). // The minimum permitted value is 7 (b00111) = 256Bytes -#define M0PLUS_MPU_RASR_SIZE_RESET 0x00 -#define M0PLUS_MPU_RASR_SIZE_BITS 0x0000003e -#define M0PLUS_MPU_RASR_SIZE_MSB 5 -#define M0PLUS_MPU_RASR_SIZE_LSB 1 +#define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00) +#define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e) +#define M0PLUS_MPU_RASR_SIZE_MSB _u(5) +#define M0PLUS_MPU_RASR_SIZE_LSB _u(1) #define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_ENABLE // Description : Enables the region. -#define M0PLUS_MPU_RASR_ENABLE_RESET 0x0 -#define M0PLUS_MPU_RASR_ENABLE_BITS 0x00000001 -#define M0PLUS_MPU_RASR_ENABLE_MSB 0 -#define M0PLUS_MPU_RASR_ENABLE_LSB 0 +#define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0) +#define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001) +#define M0PLUS_MPU_RASR_ENABLE_MSB _u(0) +#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_M0PLUS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h index 92242bd44d5..06102ac97b5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h @@ -16,36 +16,36 @@ // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x00000000 -#define PADS_BANK0_VOLTAGE_SELECT_BITS 0x00000001 -#define PADS_BANK0_VOLTAGE_SELECT_RESET 0x00000000 -#define PADS_BANK0_VOLTAGE_SELECT_MSB 0 -#define PADS_BANK0_VOLTAGE_SELECT_LSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) #define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 0x0 -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 0x1 +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= // Register : PADS_BANK0_GPIO0 // Description : Pad control register -#define PADS_BANK0_GPIO0_OFFSET 0x00000004 -#define PADS_BANK0_GPIO0_BITS 0x000000ff -#define PADS_BANK0_GPIO0_RESET 0x00000056 +#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) +#define PADS_BANK0_GPIO0_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO0_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO0_OD_RESET 0x0 -#define PADS_BANK0_GPIO0_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO0_OD_MSB 7 -#define PADS_BANK0_GPIO0_OD_LSB 7 +#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO0_OD_MSB _u(7) +#define PADS_BANK0_GPIO0_OD_LSB _u(7) #define PADS_BANK0_GPIO0_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_IE // Description : Input enable -#define PADS_BANK0_GPIO0_IE_RESET 0x1 -#define PADS_BANK0_GPIO0_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO0_IE_MSB 6 -#define PADS_BANK0_GPIO0_IE_LSB 6 +#define PADS_BANK0_GPIO0_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO0_IE_MSB _u(6) +#define PADS_BANK0_GPIO0_IE_LSB _u(6) #define PADS_BANK0_GPIO0_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_DRIVE @@ -54,69 +54,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO0_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO0_DRIVE_MSB 5 -#define PADS_BANK0_GPIO0_DRIVE_LSB 4 +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO0_PUE_RESET 0x0 -#define PADS_BANK0_GPIO0_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO0_PUE_MSB 3 -#define PADS_BANK0_GPIO0_PUE_LSB 3 +#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO0_PUE_MSB _u(3) +#define PADS_BANK0_GPIO0_PUE_LSB _u(3) #define PADS_BANK0_GPIO0_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO0_PDE_RESET 0x1 -#define PADS_BANK0_GPIO0_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO0_PDE_MSB 2 -#define PADS_BANK0_GPIO0_PDE_LSB 2 +#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO0_PDE_MSB _u(2) +#define PADS_BANK0_GPIO0_PDE_LSB _u(2) #define PADS_BANK0_GPIO0_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO0_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO0_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO0_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO0_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO0_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO0_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO0_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO0_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO1 // Description : Pad control register -#define PADS_BANK0_GPIO1_OFFSET 0x00000008 -#define PADS_BANK0_GPIO1_BITS 0x000000ff -#define PADS_BANK0_GPIO1_RESET 0x00000056 +#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) +#define PADS_BANK0_GPIO1_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO1_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO1_OD_RESET 0x0 -#define PADS_BANK0_GPIO1_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO1_OD_MSB 7 -#define PADS_BANK0_GPIO1_OD_LSB 7 +#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO1_OD_MSB _u(7) +#define PADS_BANK0_GPIO1_OD_LSB _u(7) #define PADS_BANK0_GPIO1_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_IE // Description : Input enable -#define PADS_BANK0_GPIO1_IE_RESET 0x1 -#define PADS_BANK0_GPIO1_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO1_IE_MSB 6 -#define PADS_BANK0_GPIO1_IE_LSB 6 +#define PADS_BANK0_GPIO1_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO1_IE_MSB _u(6) +#define PADS_BANK0_GPIO1_IE_LSB _u(6) #define PADS_BANK0_GPIO1_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_DRIVE @@ -125,69 +125,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO1_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO1_DRIVE_MSB 5 -#define PADS_BANK0_GPIO1_DRIVE_LSB 4 +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO1_PUE_RESET 0x0 -#define PADS_BANK0_GPIO1_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO1_PUE_MSB 3 -#define PADS_BANK0_GPIO1_PUE_LSB 3 +#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO1_PUE_MSB _u(3) +#define PADS_BANK0_GPIO1_PUE_LSB _u(3) #define PADS_BANK0_GPIO1_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO1_PDE_RESET 0x1 -#define PADS_BANK0_GPIO1_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO1_PDE_MSB 2 -#define PADS_BANK0_GPIO1_PDE_LSB 2 +#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO1_PDE_MSB _u(2) +#define PADS_BANK0_GPIO1_PDE_LSB _u(2) #define PADS_BANK0_GPIO1_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO1_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO1_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO1_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO1_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO1_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO1_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO1_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO1_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO2 // Description : Pad control register -#define PADS_BANK0_GPIO2_OFFSET 0x0000000c -#define PADS_BANK0_GPIO2_BITS 0x000000ff -#define PADS_BANK0_GPIO2_RESET 0x00000056 +#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) +#define PADS_BANK0_GPIO2_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO2_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO2_OD_RESET 0x0 -#define PADS_BANK0_GPIO2_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO2_OD_MSB 7 -#define PADS_BANK0_GPIO2_OD_LSB 7 +#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO2_OD_MSB _u(7) +#define PADS_BANK0_GPIO2_OD_LSB _u(7) #define PADS_BANK0_GPIO2_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_IE // Description : Input enable -#define PADS_BANK0_GPIO2_IE_RESET 0x1 -#define PADS_BANK0_GPIO2_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO2_IE_MSB 6 -#define PADS_BANK0_GPIO2_IE_LSB 6 +#define PADS_BANK0_GPIO2_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO2_IE_MSB _u(6) +#define PADS_BANK0_GPIO2_IE_LSB _u(6) #define PADS_BANK0_GPIO2_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_DRIVE @@ -196,69 +196,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO2_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO2_DRIVE_MSB 5 -#define PADS_BANK0_GPIO2_DRIVE_LSB 4 +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO2_PUE_RESET 0x0 -#define PADS_BANK0_GPIO2_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO2_PUE_MSB 3 -#define PADS_BANK0_GPIO2_PUE_LSB 3 +#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO2_PUE_MSB _u(3) +#define PADS_BANK0_GPIO2_PUE_LSB _u(3) #define PADS_BANK0_GPIO2_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO2_PDE_RESET 0x1 -#define PADS_BANK0_GPIO2_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO2_PDE_MSB 2 -#define PADS_BANK0_GPIO2_PDE_LSB 2 +#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO2_PDE_MSB _u(2) +#define PADS_BANK0_GPIO2_PDE_LSB _u(2) #define PADS_BANK0_GPIO2_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO2_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO2_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO2_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO2_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO2_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO2_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO2_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO2_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO3 // Description : Pad control register -#define PADS_BANK0_GPIO3_OFFSET 0x00000010 -#define PADS_BANK0_GPIO3_BITS 0x000000ff -#define PADS_BANK0_GPIO3_RESET 0x00000056 +#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) +#define PADS_BANK0_GPIO3_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO3_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO3_OD_RESET 0x0 -#define PADS_BANK0_GPIO3_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO3_OD_MSB 7 -#define PADS_BANK0_GPIO3_OD_LSB 7 +#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO3_OD_MSB _u(7) +#define PADS_BANK0_GPIO3_OD_LSB _u(7) #define PADS_BANK0_GPIO3_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_IE // Description : Input enable -#define PADS_BANK0_GPIO3_IE_RESET 0x1 -#define PADS_BANK0_GPIO3_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO3_IE_MSB 6 -#define PADS_BANK0_GPIO3_IE_LSB 6 +#define PADS_BANK0_GPIO3_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO3_IE_MSB _u(6) +#define PADS_BANK0_GPIO3_IE_LSB _u(6) #define PADS_BANK0_GPIO3_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_DRIVE @@ -267,69 +267,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO3_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO3_DRIVE_MSB 5 -#define PADS_BANK0_GPIO3_DRIVE_LSB 4 +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO3_PUE_RESET 0x0 -#define PADS_BANK0_GPIO3_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO3_PUE_MSB 3 -#define PADS_BANK0_GPIO3_PUE_LSB 3 +#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO3_PUE_MSB _u(3) +#define PADS_BANK0_GPIO3_PUE_LSB _u(3) #define PADS_BANK0_GPIO3_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO3_PDE_RESET 0x1 -#define PADS_BANK0_GPIO3_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO3_PDE_MSB 2 -#define PADS_BANK0_GPIO3_PDE_LSB 2 +#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO3_PDE_MSB _u(2) +#define PADS_BANK0_GPIO3_PDE_LSB _u(2) #define PADS_BANK0_GPIO3_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO3_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO3_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO3_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO3_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO3_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO3_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO3_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO3_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO4 // Description : Pad control register -#define PADS_BANK0_GPIO4_OFFSET 0x00000014 -#define PADS_BANK0_GPIO4_BITS 0x000000ff -#define PADS_BANK0_GPIO4_RESET 0x00000056 +#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) +#define PADS_BANK0_GPIO4_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO4_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO4_OD_RESET 0x0 -#define PADS_BANK0_GPIO4_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO4_OD_MSB 7 -#define PADS_BANK0_GPIO4_OD_LSB 7 +#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO4_OD_MSB _u(7) +#define PADS_BANK0_GPIO4_OD_LSB _u(7) #define PADS_BANK0_GPIO4_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_IE // Description : Input enable -#define PADS_BANK0_GPIO4_IE_RESET 0x1 -#define PADS_BANK0_GPIO4_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO4_IE_MSB 6 -#define PADS_BANK0_GPIO4_IE_LSB 6 +#define PADS_BANK0_GPIO4_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO4_IE_MSB _u(6) +#define PADS_BANK0_GPIO4_IE_LSB _u(6) #define PADS_BANK0_GPIO4_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_DRIVE @@ -338,69 +338,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO4_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO4_DRIVE_MSB 5 -#define PADS_BANK0_GPIO4_DRIVE_LSB 4 +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO4_PUE_RESET 0x0 -#define PADS_BANK0_GPIO4_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO4_PUE_MSB 3 -#define PADS_BANK0_GPIO4_PUE_LSB 3 +#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO4_PUE_MSB _u(3) +#define PADS_BANK0_GPIO4_PUE_LSB _u(3) #define PADS_BANK0_GPIO4_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO4_PDE_RESET 0x1 -#define PADS_BANK0_GPIO4_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO4_PDE_MSB 2 -#define PADS_BANK0_GPIO4_PDE_LSB 2 +#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO4_PDE_MSB _u(2) +#define PADS_BANK0_GPIO4_PDE_LSB _u(2) #define PADS_BANK0_GPIO4_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO4_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO4_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO4_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO4_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO4_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO4_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO4_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO4_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO5 // Description : Pad control register -#define PADS_BANK0_GPIO5_OFFSET 0x00000018 -#define PADS_BANK0_GPIO5_BITS 0x000000ff -#define PADS_BANK0_GPIO5_RESET 0x00000056 +#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) +#define PADS_BANK0_GPIO5_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO5_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO5_OD_RESET 0x0 -#define PADS_BANK0_GPIO5_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO5_OD_MSB 7 -#define PADS_BANK0_GPIO5_OD_LSB 7 +#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO5_OD_MSB _u(7) +#define PADS_BANK0_GPIO5_OD_LSB _u(7) #define PADS_BANK0_GPIO5_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_IE // Description : Input enable -#define PADS_BANK0_GPIO5_IE_RESET 0x1 -#define PADS_BANK0_GPIO5_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO5_IE_MSB 6 -#define PADS_BANK0_GPIO5_IE_LSB 6 +#define PADS_BANK0_GPIO5_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO5_IE_MSB _u(6) +#define PADS_BANK0_GPIO5_IE_LSB _u(6) #define PADS_BANK0_GPIO5_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_DRIVE @@ -409,69 +409,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO5_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO5_DRIVE_MSB 5 -#define PADS_BANK0_GPIO5_DRIVE_LSB 4 +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO5_PUE_RESET 0x0 -#define PADS_BANK0_GPIO5_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO5_PUE_MSB 3 -#define PADS_BANK0_GPIO5_PUE_LSB 3 +#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO5_PUE_MSB _u(3) +#define PADS_BANK0_GPIO5_PUE_LSB _u(3) #define PADS_BANK0_GPIO5_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO5_PDE_RESET 0x1 -#define PADS_BANK0_GPIO5_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO5_PDE_MSB 2 -#define PADS_BANK0_GPIO5_PDE_LSB 2 +#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO5_PDE_MSB _u(2) +#define PADS_BANK0_GPIO5_PDE_LSB _u(2) #define PADS_BANK0_GPIO5_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO5_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO5_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO5_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO5_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO5_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO5_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO5_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO5_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO6 // Description : Pad control register -#define PADS_BANK0_GPIO6_OFFSET 0x0000001c -#define PADS_BANK0_GPIO6_BITS 0x000000ff -#define PADS_BANK0_GPIO6_RESET 0x00000056 +#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) +#define PADS_BANK0_GPIO6_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO6_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO6_OD_RESET 0x0 -#define PADS_BANK0_GPIO6_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO6_OD_MSB 7 -#define PADS_BANK0_GPIO6_OD_LSB 7 +#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO6_OD_MSB _u(7) +#define PADS_BANK0_GPIO6_OD_LSB _u(7) #define PADS_BANK0_GPIO6_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_IE // Description : Input enable -#define PADS_BANK0_GPIO6_IE_RESET 0x1 -#define PADS_BANK0_GPIO6_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO6_IE_MSB 6 -#define PADS_BANK0_GPIO6_IE_LSB 6 +#define PADS_BANK0_GPIO6_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO6_IE_MSB _u(6) +#define PADS_BANK0_GPIO6_IE_LSB _u(6) #define PADS_BANK0_GPIO6_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_DRIVE @@ -480,69 +480,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO6_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO6_DRIVE_MSB 5 -#define PADS_BANK0_GPIO6_DRIVE_LSB 4 +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO6_PUE_RESET 0x0 -#define PADS_BANK0_GPIO6_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO6_PUE_MSB 3 -#define PADS_BANK0_GPIO6_PUE_LSB 3 +#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO6_PUE_MSB _u(3) +#define PADS_BANK0_GPIO6_PUE_LSB _u(3) #define PADS_BANK0_GPIO6_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO6_PDE_RESET 0x1 -#define PADS_BANK0_GPIO6_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO6_PDE_MSB 2 -#define PADS_BANK0_GPIO6_PDE_LSB 2 +#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO6_PDE_MSB _u(2) +#define PADS_BANK0_GPIO6_PDE_LSB _u(2) #define PADS_BANK0_GPIO6_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO6_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO6_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO6_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO6_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO6_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO6_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO6_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO6_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO7 // Description : Pad control register -#define PADS_BANK0_GPIO7_OFFSET 0x00000020 -#define PADS_BANK0_GPIO7_BITS 0x000000ff -#define PADS_BANK0_GPIO7_RESET 0x00000056 +#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) +#define PADS_BANK0_GPIO7_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO7_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO7_OD_RESET 0x0 -#define PADS_BANK0_GPIO7_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO7_OD_MSB 7 -#define PADS_BANK0_GPIO7_OD_LSB 7 +#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO7_OD_MSB _u(7) +#define PADS_BANK0_GPIO7_OD_LSB _u(7) #define PADS_BANK0_GPIO7_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_IE // Description : Input enable -#define PADS_BANK0_GPIO7_IE_RESET 0x1 -#define PADS_BANK0_GPIO7_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO7_IE_MSB 6 -#define PADS_BANK0_GPIO7_IE_LSB 6 +#define PADS_BANK0_GPIO7_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO7_IE_MSB _u(6) +#define PADS_BANK0_GPIO7_IE_LSB _u(6) #define PADS_BANK0_GPIO7_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_DRIVE @@ -551,69 +551,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO7_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO7_DRIVE_MSB 5 -#define PADS_BANK0_GPIO7_DRIVE_LSB 4 +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO7_PUE_RESET 0x0 -#define PADS_BANK0_GPIO7_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO7_PUE_MSB 3 -#define PADS_BANK0_GPIO7_PUE_LSB 3 +#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO7_PUE_MSB _u(3) +#define PADS_BANK0_GPIO7_PUE_LSB _u(3) #define PADS_BANK0_GPIO7_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO7_PDE_RESET 0x1 -#define PADS_BANK0_GPIO7_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO7_PDE_MSB 2 -#define PADS_BANK0_GPIO7_PDE_LSB 2 +#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO7_PDE_MSB _u(2) +#define PADS_BANK0_GPIO7_PDE_LSB _u(2) #define PADS_BANK0_GPIO7_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO7_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO7_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO7_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO7_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO7_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO7_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO7_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO7_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO8 // Description : Pad control register -#define PADS_BANK0_GPIO8_OFFSET 0x00000024 -#define PADS_BANK0_GPIO8_BITS 0x000000ff -#define PADS_BANK0_GPIO8_RESET 0x00000056 +#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) +#define PADS_BANK0_GPIO8_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO8_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO8_OD_RESET 0x0 -#define PADS_BANK0_GPIO8_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO8_OD_MSB 7 -#define PADS_BANK0_GPIO8_OD_LSB 7 +#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO8_OD_MSB _u(7) +#define PADS_BANK0_GPIO8_OD_LSB _u(7) #define PADS_BANK0_GPIO8_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_IE // Description : Input enable -#define PADS_BANK0_GPIO8_IE_RESET 0x1 -#define PADS_BANK0_GPIO8_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO8_IE_MSB 6 -#define PADS_BANK0_GPIO8_IE_LSB 6 +#define PADS_BANK0_GPIO8_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO8_IE_MSB _u(6) +#define PADS_BANK0_GPIO8_IE_LSB _u(6) #define PADS_BANK0_GPIO8_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_DRIVE @@ -622,69 +622,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO8_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO8_DRIVE_MSB 5 -#define PADS_BANK0_GPIO8_DRIVE_LSB 4 +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO8_PUE_RESET 0x0 -#define PADS_BANK0_GPIO8_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO8_PUE_MSB 3 -#define PADS_BANK0_GPIO8_PUE_LSB 3 +#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO8_PUE_MSB _u(3) +#define PADS_BANK0_GPIO8_PUE_LSB _u(3) #define PADS_BANK0_GPIO8_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO8_PDE_RESET 0x1 -#define PADS_BANK0_GPIO8_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO8_PDE_MSB 2 -#define PADS_BANK0_GPIO8_PDE_LSB 2 +#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO8_PDE_MSB _u(2) +#define PADS_BANK0_GPIO8_PDE_LSB _u(2) #define PADS_BANK0_GPIO8_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO8_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO8_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO8_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO8_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO8_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO8_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO8_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO8_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO9 // Description : Pad control register -#define PADS_BANK0_GPIO9_OFFSET 0x00000028 -#define PADS_BANK0_GPIO9_BITS 0x000000ff -#define PADS_BANK0_GPIO9_RESET 0x00000056 +#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) +#define PADS_BANK0_GPIO9_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO9_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO9_OD_RESET 0x0 -#define PADS_BANK0_GPIO9_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO9_OD_MSB 7 -#define PADS_BANK0_GPIO9_OD_LSB 7 +#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO9_OD_MSB _u(7) +#define PADS_BANK0_GPIO9_OD_LSB _u(7) #define PADS_BANK0_GPIO9_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_IE // Description : Input enable -#define PADS_BANK0_GPIO9_IE_RESET 0x1 -#define PADS_BANK0_GPIO9_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO9_IE_MSB 6 -#define PADS_BANK0_GPIO9_IE_LSB 6 +#define PADS_BANK0_GPIO9_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO9_IE_MSB _u(6) +#define PADS_BANK0_GPIO9_IE_LSB _u(6) #define PADS_BANK0_GPIO9_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_DRIVE @@ -693,69 +693,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO9_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO9_DRIVE_MSB 5 -#define PADS_BANK0_GPIO9_DRIVE_LSB 4 +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO9_PUE_RESET 0x0 -#define PADS_BANK0_GPIO9_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO9_PUE_MSB 3 -#define PADS_BANK0_GPIO9_PUE_LSB 3 +#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO9_PUE_MSB _u(3) +#define PADS_BANK0_GPIO9_PUE_LSB _u(3) #define PADS_BANK0_GPIO9_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO9_PDE_RESET 0x1 -#define PADS_BANK0_GPIO9_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO9_PDE_MSB 2 -#define PADS_BANK0_GPIO9_PDE_LSB 2 +#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO9_PDE_MSB _u(2) +#define PADS_BANK0_GPIO9_PDE_LSB _u(2) #define PADS_BANK0_GPIO9_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO9_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO9_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO9_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO9_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO9_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO9_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO9_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO9_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO10 // Description : Pad control register -#define PADS_BANK0_GPIO10_OFFSET 0x0000002c -#define PADS_BANK0_GPIO10_BITS 0x000000ff -#define PADS_BANK0_GPIO10_RESET 0x00000056 +#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) +#define PADS_BANK0_GPIO10_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO10_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO10_OD_RESET 0x0 -#define PADS_BANK0_GPIO10_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO10_OD_MSB 7 -#define PADS_BANK0_GPIO10_OD_LSB 7 +#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO10_OD_MSB _u(7) +#define PADS_BANK0_GPIO10_OD_LSB _u(7) #define PADS_BANK0_GPIO10_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_IE // Description : Input enable -#define PADS_BANK0_GPIO10_IE_RESET 0x1 -#define PADS_BANK0_GPIO10_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO10_IE_MSB 6 -#define PADS_BANK0_GPIO10_IE_LSB 6 +#define PADS_BANK0_GPIO10_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO10_IE_MSB _u(6) +#define PADS_BANK0_GPIO10_IE_LSB _u(6) #define PADS_BANK0_GPIO10_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_DRIVE @@ -764,69 +764,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO10_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO10_DRIVE_MSB 5 -#define PADS_BANK0_GPIO10_DRIVE_LSB 4 +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO10_PUE_RESET 0x0 -#define PADS_BANK0_GPIO10_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO10_PUE_MSB 3 -#define PADS_BANK0_GPIO10_PUE_LSB 3 +#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO10_PUE_MSB _u(3) +#define PADS_BANK0_GPIO10_PUE_LSB _u(3) #define PADS_BANK0_GPIO10_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO10_PDE_RESET 0x1 -#define PADS_BANK0_GPIO10_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO10_PDE_MSB 2 -#define PADS_BANK0_GPIO10_PDE_LSB 2 +#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO10_PDE_MSB _u(2) +#define PADS_BANK0_GPIO10_PDE_LSB _u(2) #define PADS_BANK0_GPIO10_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO10_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO10_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO10_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO10_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO10_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO10_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO10_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO10_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO11 // Description : Pad control register -#define PADS_BANK0_GPIO11_OFFSET 0x00000030 -#define PADS_BANK0_GPIO11_BITS 0x000000ff -#define PADS_BANK0_GPIO11_RESET 0x00000056 +#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) +#define PADS_BANK0_GPIO11_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO11_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO11_OD_RESET 0x0 -#define PADS_BANK0_GPIO11_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO11_OD_MSB 7 -#define PADS_BANK0_GPIO11_OD_LSB 7 +#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO11_OD_MSB _u(7) +#define PADS_BANK0_GPIO11_OD_LSB _u(7) #define PADS_BANK0_GPIO11_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_IE // Description : Input enable -#define PADS_BANK0_GPIO11_IE_RESET 0x1 -#define PADS_BANK0_GPIO11_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO11_IE_MSB 6 -#define PADS_BANK0_GPIO11_IE_LSB 6 +#define PADS_BANK0_GPIO11_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO11_IE_MSB _u(6) +#define PADS_BANK0_GPIO11_IE_LSB _u(6) #define PADS_BANK0_GPIO11_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_DRIVE @@ -835,69 +835,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO11_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO11_DRIVE_MSB 5 -#define PADS_BANK0_GPIO11_DRIVE_LSB 4 +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO11_PUE_RESET 0x0 -#define PADS_BANK0_GPIO11_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO11_PUE_MSB 3 -#define PADS_BANK0_GPIO11_PUE_LSB 3 +#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO11_PUE_MSB _u(3) +#define PADS_BANK0_GPIO11_PUE_LSB _u(3) #define PADS_BANK0_GPIO11_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO11_PDE_RESET 0x1 -#define PADS_BANK0_GPIO11_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO11_PDE_MSB 2 -#define PADS_BANK0_GPIO11_PDE_LSB 2 +#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO11_PDE_MSB _u(2) +#define PADS_BANK0_GPIO11_PDE_LSB _u(2) #define PADS_BANK0_GPIO11_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO11_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO11_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO11_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO11_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO11_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO11_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO11_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO11_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO12 // Description : Pad control register -#define PADS_BANK0_GPIO12_OFFSET 0x00000034 -#define PADS_BANK0_GPIO12_BITS 0x000000ff -#define PADS_BANK0_GPIO12_RESET 0x00000056 +#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) +#define PADS_BANK0_GPIO12_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO12_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO12_OD_RESET 0x0 -#define PADS_BANK0_GPIO12_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO12_OD_MSB 7 -#define PADS_BANK0_GPIO12_OD_LSB 7 +#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO12_OD_MSB _u(7) +#define PADS_BANK0_GPIO12_OD_LSB _u(7) #define PADS_BANK0_GPIO12_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_IE // Description : Input enable -#define PADS_BANK0_GPIO12_IE_RESET 0x1 -#define PADS_BANK0_GPIO12_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO12_IE_MSB 6 -#define PADS_BANK0_GPIO12_IE_LSB 6 +#define PADS_BANK0_GPIO12_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO12_IE_MSB _u(6) +#define PADS_BANK0_GPIO12_IE_LSB _u(6) #define PADS_BANK0_GPIO12_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_DRIVE @@ -906,69 +906,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO12_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO12_DRIVE_MSB 5 -#define PADS_BANK0_GPIO12_DRIVE_LSB 4 +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO12_PUE_RESET 0x0 -#define PADS_BANK0_GPIO12_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO12_PUE_MSB 3 -#define PADS_BANK0_GPIO12_PUE_LSB 3 +#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO12_PUE_MSB _u(3) +#define PADS_BANK0_GPIO12_PUE_LSB _u(3) #define PADS_BANK0_GPIO12_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO12_PDE_RESET 0x1 -#define PADS_BANK0_GPIO12_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO12_PDE_MSB 2 -#define PADS_BANK0_GPIO12_PDE_LSB 2 +#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO12_PDE_MSB _u(2) +#define PADS_BANK0_GPIO12_PDE_LSB _u(2) #define PADS_BANK0_GPIO12_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO12_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO12_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO12_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO12_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO12_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO12_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO12_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO12_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO13 // Description : Pad control register -#define PADS_BANK0_GPIO13_OFFSET 0x00000038 -#define PADS_BANK0_GPIO13_BITS 0x000000ff -#define PADS_BANK0_GPIO13_RESET 0x00000056 +#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) +#define PADS_BANK0_GPIO13_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO13_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO13_OD_RESET 0x0 -#define PADS_BANK0_GPIO13_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO13_OD_MSB 7 -#define PADS_BANK0_GPIO13_OD_LSB 7 +#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO13_OD_MSB _u(7) +#define PADS_BANK0_GPIO13_OD_LSB _u(7) #define PADS_BANK0_GPIO13_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_IE // Description : Input enable -#define PADS_BANK0_GPIO13_IE_RESET 0x1 -#define PADS_BANK0_GPIO13_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO13_IE_MSB 6 -#define PADS_BANK0_GPIO13_IE_LSB 6 +#define PADS_BANK0_GPIO13_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO13_IE_MSB _u(6) +#define PADS_BANK0_GPIO13_IE_LSB _u(6) #define PADS_BANK0_GPIO13_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_DRIVE @@ -977,69 +977,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO13_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO13_DRIVE_MSB 5 -#define PADS_BANK0_GPIO13_DRIVE_LSB 4 +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO13_PUE_RESET 0x0 -#define PADS_BANK0_GPIO13_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO13_PUE_MSB 3 -#define PADS_BANK0_GPIO13_PUE_LSB 3 +#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO13_PUE_MSB _u(3) +#define PADS_BANK0_GPIO13_PUE_LSB _u(3) #define PADS_BANK0_GPIO13_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO13_PDE_RESET 0x1 -#define PADS_BANK0_GPIO13_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO13_PDE_MSB 2 -#define PADS_BANK0_GPIO13_PDE_LSB 2 +#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO13_PDE_MSB _u(2) +#define PADS_BANK0_GPIO13_PDE_LSB _u(2) #define PADS_BANK0_GPIO13_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO13_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO13_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO13_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO13_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO13_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO13_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO13_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO13_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO14 // Description : Pad control register -#define PADS_BANK0_GPIO14_OFFSET 0x0000003c -#define PADS_BANK0_GPIO14_BITS 0x000000ff -#define PADS_BANK0_GPIO14_RESET 0x00000056 +#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) +#define PADS_BANK0_GPIO14_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO14_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO14_OD_RESET 0x0 -#define PADS_BANK0_GPIO14_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO14_OD_MSB 7 -#define PADS_BANK0_GPIO14_OD_LSB 7 +#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO14_OD_MSB _u(7) +#define PADS_BANK0_GPIO14_OD_LSB _u(7) #define PADS_BANK0_GPIO14_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_IE // Description : Input enable -#define PADS_BANK0_GPIO14_IE_RESET 0x1 -#define PADS_BANK0_GPIO14_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO14_IE_MSB 6 -#define PADS_BANK0_GPIO14_IE_LSB 6 +#define PADS_BANK0_GPIO14_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO14_IE_MSB _u(6) +#define PADS_BANK0_GPIO14_IE_LSB _u(6) #define PADS_BANK0_GPIO14_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_DRIVE @@ -1048,69 +1048,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO14_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO14_DRIVE_MSB 5 -#define PADS_BANK0_GPIO14_DRIVE_LSB 4 +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO14_PUE_RESET 0x0 -#define PADS_BANK0_GPIO14_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO14_PUE_MSB 3 -#define PADS_BANK0_GPIO14_PUE_LSB 3 +#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO14_PUE_MSB _u(3) +#define PADS_BANK0_GPIO14_PUE_LSB _u(3) #define PADS_BANK0_GPIO14_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO14_PDE_RESET 0x1 -#define PADS_BANK0_GPIO14_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO14_PDE_MSB 2 -#define PADS_BANK0_GPIO14_PDE_LSB 2 +#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO14_PDE_MSB _u(2) +#define PADS_BANK0_GPIO14_PDE_LSB _u(2) #define PADS_BANK0_GPIO14_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO14_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO14_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO14_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO14_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO14_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO14_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO14_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO14_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO15 // Description : Pad control register -#define PADS_BANK0_GPIO15_OFFSET 0x00000040 -#define PADS_BANK0_GPIO15_BITS 0x000000ff -#define PADS_BANK0_GPIO15_RESET 0x00000056 +#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) +#define PADS_BANK0_GPIO15_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO15_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO15_OD_RESET 0x0 -#define PADS_BANK0_GPIO15_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO15_OD_MSB 7 -#define PADS_BANK0_GPIO15_OD_LSB 7 +#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO15_OD_MSB _u(7) +#define PADS_BANK0_GPIO15_OD_LSB _u(7) #define PADS_BANK0_GPIO15_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_IE // Description : Input enable -#define PADS_BANK0_GPIO15_IE_RESET 0x1 -#define PADS_BANK0_GPIO15_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO15_IE_MSB 6 -#define PADS_BANK0_GPIO15_IE_LSB 6 +#define PADS_BANK0_GPIO15_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO15_IE_MSB _u(6) +#define PADS_BANK0_GPIO15_IE_LSB _u(6) #define PADS_BANK0_GPIO15_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_DRIVE @@ -1119,69 +1119,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO15_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO15_DRIVE_MSB 5 -#define PADS_BANK0_GPIO15_DRIVE_LSB 4 +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO15_PUE_RESET 0x0 -#define PADS_BANK0_GPIO15_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO15_PUE_MSB 3 -#define PADS_BANK0_GPIO15_PUE_LSB 3 +#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO15_PUE_MSB _u(3) +#define PADS_BANK0_GPIO15_PUE_LSB _u(3) #define PADS_BANK0_GPIO15_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO15_PDE_RESET 0x1 -#define PADS_BANK0_GPIO15_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO15_PDE_MSB 2 -#define PADS_BANK0_GPIO15_PDE_LSB 2 +#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO15_PDE_MSB _u(2) +#define PADS_BANK0_GPIO15_PDE_LSB _u(2) #define PADS_BANK0_GPIO15_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO15_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO15_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO15_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO15_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO15_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO15_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO15_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO15_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO16 // Description : Pad control register -#define PADS_BANK0_GPIO16_OFFSET 0x00000044 -#define PADS_BANK0_GPIO16_BITS 0x000000ff -#define PADS_BANK0_GPIO16_RESET 0x00000056 +#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) +#define PADS_BANK0_GPIO16_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO16_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO16_OD_RESET 0x0 -#define PADS_BANK0_GPIO16_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO16_OD_MSB 7 -#define PADS_BANK0_GPIO16_OD_LSB 7 +#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO16_OD_MSB _u(7) +#define PADS_BANK0_GPIO16_OD_LSB _u(7) #define PADS_BANK0_GPIO16_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_IE // Description : Input enable -#define PADS_BANK0_GPIO16_IE_RESET 0x1 -#define PADS_BANK0_GPIO16_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO16_IE_MSB 6 -#define PADS_BANK0_GPIO16_IE_LSB 6 +#define PADS_BANK0_GPIO16_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO16_IE_MSB _u(6) +#define PADS_BANK0_GPIO16_IE_LSB _u(6) #define PADS_BANK0_GPIO16_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_DRIVE @@ -1190,69 +1190,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO16_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO16_DRIVE_MSB 5 -#define PADS_BANK0_GPIO16_DRIVE_LSB 4 +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO16_PUE_RESET 0x0 -#define PADS_BANK0_GPIO16_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO16_PUE_MSB 3 -#define PADS_BANK0_GPIO16_PUE_LSB 3 +#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO16_PUE_MSB _u(3) +#define PADS_BANK0_GPIO16_PUE_LSB _u(3) #define PADS_BANK0_GPIO16_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO16_PDE_RESET 0x1 -#define PADS_BANK0_GPIO16_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO16_PDE_MSB 2 -#define PADS_BANK0_GPIO16_PDE_LSB 2 +#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO16_PDE_MSB _u(2) +#define PADS_BANK0_GPIO16_PDE_LSB _u(2) #define PADS_BANK0_GPIO16_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO16_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO16_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO16_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO16_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO16_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO16_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO16_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO16_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO17 // Description : Pad control register -#define PADS_BANK0_GPIO17_OFFSET 0x00000048 -#define PADS_BANK0_GPIO17_BITS 0x000000ff -#define PADS_BANK0_GPIO17_RESET 0x00000056 +#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) +#define PADS_BANK0_GPIO17_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO17_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO17_OD_RESET 0x0 -#define PADS_BANK0_GPIO17_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO17_OD_MSB 7 -#define PADS_BANK0_GPIO17_OD_LSB 7 +#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO17_OD_MSB _u(7) +#define PADS_BANK0_GPIO17_OD_LSB _u(7) #define PADS_BANK0_GPIO17_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_IE // Description : Input enable -#define PADS_BANK0_GPIO17_IE_RESET 0x1 -#define PADS_BANK0_GPIO17_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO17_IE_MSB 6 -#define PADS_BANK0_GPIO17_IE_LSB 6 +#define PADS_BANK0_GPIO17_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO17_IE_MSB _u(6) +#define PADS_BANK0_GPIO17_IE_LSB _u(6) #define PADS_BANK0_GPIO17_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_DRIVE @@ -1261,69 +1261,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO17_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO17_DRIVE_MSB 5 -#define PADS_BANK0_GPIO17_DRIVE_LSB 4 +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO17_PUE_RESET 0x0 -#define PADS_BANK0_GPIO17_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO17_PUE_MSB 3 -#define PADS_BANK0_GPIO17_PUE_LSB 3 +#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO17_PUE_MSB _u(3) +#define PADS_BANK0_GPIO17_PUE_LSB _u(3) #define PADS_BANK0_GPIO17_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO17_PDE_RESET 0x1 -#define PADS_BANK0_GPIO17_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO17_PDE_MSB 2 -#define PADS_BANK0_GPIO17_PDE_LSB 2 +#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO17_PDE_MSB _u(2) +#define PADS_BANK0_GPIO17_PDE_LSB _u(2) #define PADS_BANK0_GPIO17_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO17_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO17_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO17_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO17_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO17_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO17_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO17_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO17_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO18 // Description : Pad control register -#define PADS_BANK0_GPIO18_OFFSET 0x0000004c -#define PADS_BANK0_GPIO18_BITS 0x000000ff -#define PADS_BANK0_GPIO18_RESET 0x00000056 +#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) +#define PADS_BANK0_GPIO18_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO18_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO18_OD_RESET 0x0 -#define PADS_BANK0_GPIO18_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO18_OD_MSB 7 -#define PADS_BANK0_GPIO18_OD_LSB 7 +#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO18_OD_MSB _u(7) +#define PADS_BANK0_GPIO18_OD_LSB _u(7) #define PADS_BANK0_GPIO18_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_IE // Description : Input enable -#define PADS_BANK0_GPIO18_IE_RESET 0x1 -#define PADS_BANK0_GPIO18_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO18_IE_MSB 6 -#define PADS_BANK0_GPIO18_IE_LSB 6 +#define PADS_BANK0_GPIO18_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO18_IE_MSB _u(6) +#define PADS_BANK0_GPIO18_IE_LSB _u(6) #define PADS_BANK0_GPIO18_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_DRIVE @@ -1332,69 +1332,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO18_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO18_DRIVE_MSB 5 -#define PADS_BANK0_GPIO18_DRIVE_LSB 4 +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO18_PUE_RESET 0x0 -#define PADS_BANK0_GPIO18_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO18_PUE_MSB 3 -#define PADS_BANK0_GPIO18_PUE_LSB 3 +#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO18_PUE_MSB _u(3) +#define PADS_BANK0_GPIO18_PUE_LSB _u(3) #define PADS_BANK0_GPIO18_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO18_PDE_RESET 0x1 -#define PADS_BANK0_GPIO18_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO18_PDE_MSB 2 -#define PADS_BANK0_GPIO18_PDE_LSB 2 +#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO18_PDE_MSB _u(2) +#define PADS_BANK0_GPIO18_PDE_LSB _u(2) #define PADS_BANK0_GPIO18_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO18_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO18_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO18_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO18_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO18_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO18_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO18_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO18_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO19 // Description : Pad control register -#define PADS_BANK0_GPIO19_OFFSET 0x00000050 -#define PADS_BANK0_GPIO19_BITS 0x000000ff -#define PADS_BANK0_GPIO19_RESET 0x00000056 +#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) +#define PADS_BANK0_GPIO19_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO19_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO19_OD_RESET 0x0 -#define PADS_BANK0_GPIO19_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO19_OD_MSB 7 -#define PADS_BANK0_GPIO19_OD_LSB 7 +#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO19_OD_MSB _u(7) +#define PADS_BANK0_GPIO19_OD_LSB _u(7) #define PADS_BANK0_GPIO19_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_IE // Description : Input enable -#define PADS_BANK0_GPIO19_IE_RESET 0x1 -#define PADS_BANK0_GPIO19_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO19_IE_MSB 6 -#define PADS_BANK0_GPIO19_IE_LSB 6 +#define PADS_BANK0_GPIO19_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO19_IE_MSB _u(6) +#define PADS_BANK0_GPIO19_IE_LSB _u(6) #define PADS_BANK0_GPIO19_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_DRIVE @@ -1403,69 +1403,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO19_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO19_DRIVE_MSB 5 -#define PADS_BANK0_GPIO19_DRIVE_LSB 4 +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO19_PUE_RESET 0x0 -#define PADS_BANK0_GPIO19_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO19_PUE_MSB 3 -#define PADS_BANK0_GPIO19_PUE_LSB 3 +#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO19_PUE_MSB _u(3) +#define PADS_BANK0_GPIO19_PUE_LSB _u(3) #define PADS_BANK0_GPIO19_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO19_PDE_RESET 0x1 -#define PADS_BANK0_GPIO19_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO19_PDE_MSB 2 -#define PADS_BANK0_GPIO19_PDE_LSB 2 +#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO19_PDE_MSB _u(2) +#define PADS_BANK0_GPIO19_PDE_LSB _u(2) #define PADS_BANK0_GPIO19_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO19_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO19_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO19_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO19_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO19_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO19_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO19_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO19_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO20 // Description : Pad control register -#define PADS_BANK0_GPIO20_OFFSET 0x00000054 -#define PADS_BANK0_GPIO20_BITS 0x000000ff -#define PADS_BANK0_GPIO20_RESET 0x00000056 +#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) +#define PADS_BANK0_GPIO20_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO20_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO20_OD_RESET 0x0 -#define PADS_BANK0_GPIO20_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO20_OD_MSB 7 -#define PADS_BANK0_GPIO20_OD_LSB 7 +#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO20_OD_MSB _u(7) +#define PADS_BANK0_GPIO20_OD_LSB _u(7) #define PADS_BANK0_GPIO20_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_IE // Description : Input enable -#define PADS_BANK0_GPIO20_IE_RESET 0x1 -#define PADS_BANK0_GPIO20_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO20_IE_MSB 6 -#define PADS_BANK0_GPIO20_IE_LSB 6 +#define PADS_BANK0_GPIO20_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO20_IE_MSB _u(6) +#define PADS_BANK0_GPIO20_IE_LSB _u(6) #define PADS_BANK0_GPIO20_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_DRIVE @@ -1474,69 +1474,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO20_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO20_DRIVE_MSB 5 -#define PADS_BANK0_GPIO20_DRIVE_LSB 4 +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO20_PUE_RESET 0x0 -#define PADS_BANK0_GPIO20_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO20_PUE_MSB 3 -#define PADS_BANK0_GPIO20_PUE_LSB 3 +#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO20_PUE_MSB _u(3) +#define PADS_BANK0_GPIO20_PUE_LSB _u(3) #define PADS_BANK0_GPIO20_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO20_PDE_RESET 0x1 -#define PADS_BANK0_GPIO20_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO20_PDE_MSB 2 -#define PADS_BANK0_GPIO20_PDE_LSB 2 +#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO20_PDE_MSB _u(2) +#define PADS_BANK0_GPIO20_PDE_LSB _u(2) #define PADS_BANK0_GPIO20_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO20_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO20_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO20_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO20_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO20_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO20_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO20_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO20_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO21 // Description : Pad control register -#define PADS_BANK0_GPIO21_OFFSET 0x00000058 -#define PADS_BANK0_GPIO21_BITS 0x000000ff -#define PADS_BANK0_GPIO21_RESET 0x00000056 +#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) +#define PADS_BANK0_GPIO21_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO21_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO21_OD_RESET 0x0 -#define PADS_BANK0_GPIO21_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO21_OD_MSB 7 -#define PADS_BANK0_GPIO21_OD_LSB 7 +#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO21_OD_MSB _u(7) +#define PADS_BANK0_GPIO21_OD_LSB _u(7) #define PADS_BANK0_GPIO21_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_IE // Description : Input enable -#define PADS_BANK0_GPIO21_IE_RESET 0x1 -#define PADS_BANK0_GPIO21_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO21_IE_MSB 6 -#define PADS_BANK0_GPIO21_IE_LSB 6 +#define PADS_BANK0_GPIO21_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO21_IE_MSB _u(6) +#define PADS_BANK0_GPIO21_IE_LSB _u(6) #define PADS_BANK0_GPIO21_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_DRIVE @@ -1545,69 +1545,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO21_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO21_DRIVE_MSB 5 -#define PADS_BANK0_GPIO21_DRIVE_LSB 4 +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO21_PUE_RESET 0x0 -#define PADS_BANK0_GPIO21_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO21_PUE_MSB 3 -#define PADS_BANK0_GPIO21_PUE_LSB 3 +#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO21_PUE_MSB _u(3) +#define PADS_BANK0_GPIO21_PUE_LSB _u(3) #define PADS_BANK0_GPIO21_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO21_PDE_RESET 0x1 -#define PADS_BANK0_GPIO21_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO21_PDE_MSB 2 -#define PADS_BANK0_GPIO21_PDE_LSB 2 +#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO21_PDE_MSB _u(2) +#define PADS_BANK0_GPIO21_PDE_LSB _u(2) #define PADS_BANK0_GPIO21_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO21_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO21_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO21_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO21_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO21_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO21_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO21_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO21_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO22 // Description : Pad control register -#define PADS_BANK0_GPIO22_OFFSET 0x0000005c -#define PADS_BANK0_GPIO22_BITS 0x000000ff -#define PADS_BANK0_GPIO22_RESET 0x00000056 +#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) +#define PADS_BANK0_GPIO22_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO22_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO22_OD_RESET 0x0 -#define PADS_BANK0_GPIO22_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO22_OD_MSB 7 -#define PADS_BANK0_GPIO22_OD_LSB 7 +#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO22_OD_MSB _u(7) +#define PADS_BANK0_GPIO22_OD_LSB _u(7) #define PADS_BANK0_GPIO22_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_IE // Description : Input enable -#define PADS_BANK0_GPIO22_IE_RESET 0x1 -#define PADS_BANK0_GPIO22_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO22_IE_MSB 6 -#define PADS_BANK0_GPIO22_IE_LSB 6 +#define PADS_BANK0_GPIO22_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO22_IE_MSB _u(6) +#define PADS_BANK0_GPIO22_IE_LSB _u(6) #define PADS_BANK0_GPIO22_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_DRIVE @@ -1616,69 +1616,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO22_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO22_DRIVE_MSB 5 -#define PADS_BANK0_GPIO22_DRIVE_LSB 4 +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO22_PUE_RESET 0x0 -#define PADS_BANK0_GPIO22_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO22_PUE_MSB 3 -#define PADS_BANK0_GPIO22_PUE_LSB 3 +#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO22_PUE_MSB _u(3) +#define PADS_BANK0_GPIO22_PUE_LSB _u(3) #define PADS_BANK0_GPIO22_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO22_PDE_RESET 0x1 -#define PADS_BANK0_GPIO22_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO22_PDE_MSB 2 -#define PADS_BANK0_GPIO22_PDE_LSB 2 +#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO22_PDE_MSB _u(2) +#define PADS_BANK0_GPIO22_PDE_LSB _u(2) #define PADS_BANK0_GPIO22_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO22_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO22_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO22_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO22_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO22_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO22_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO22_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO22_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO23 // Description : Pad control register -#define PADS_BANK0_GPIO23_OFFSET 0x00000060 -#define PADS_BANK0_GPIO23_BITS 0x000000ff -#define PADS_BANK0_GPIO23_RESET 0x00000056 +#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) +#define PADS_BANK0_GPIO23_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO23_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO23_OD_RESET 0x0 -#define PADS_BANK0_GPIO23_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO23_OD_MSB 7 -#define PADS_BANK0_GPIO23_OD_LSB 7 +#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO23_OD_MSB _u(7) +#define PADS_BANK0_GPIO23_OD_LSB _u(7) #define PADS_BANK0_GPIO23_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_IE // Description : Input enable -#define PADS_BANK0_GPIO23_IE_RESET 0x1 -#define PADS_BANK0_GPIO23_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO23_IE_MSB 6 -#define PADS_BANK0_GPIO23_IE_LSB 6 +#define PADS_BANK0_GPIO23_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO23_IE_MSB _u(6) +#define PADS_BANK0_GPIO23_IE_LSB _u(6) #define PADS_BANK0_GPIO23_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_DRIVE @@ -1687,69 +1687,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO23_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO23_DRIVE_MSB 5 -#define PADS_BANK0_GPIO23_DRIVE_LSB 4 +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO23_PUE_RESET 0x0 -#define PADS_BANK0_GPIO23_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO23_PUE_MSB 3 -#define PADS_BANK0_GPIO23_PUE_LSB 3 +#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO23_PUE_MSB _u(3) +#define PADS_BANK0_GPIO23_PUE_LSB _u(3) #define PADS_BANK0_GPIO23_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO23_PDE_RESET 0x1 -#define PADS_BANK0_GPIO23_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO23_PDE_MSB 2 -#define PADS_BANK0_GPIO23_PDE_LSB 2 +#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO23_PDE_MSB _u(2) +#define PADS_BANK0_GPIO23_PDE_LSB _u(2) #define PADS_BANK0_GPIO23_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO23_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO23_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO23_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO23_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO23_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO23_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO23_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO23_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO24 // Description : Pad control register -#define PADS_BANK0_GPIO24_OFFSET 0x00000064 -#define PADS_BANK0_GPIO24_BITS 0x000000ff -#define PADS_BANK0_GPIO24_RESET 0x00000056 +#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) +#define PADS_BANK0_GPIO24_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO24_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO24_OD_RESET 0x0 -#define PADS_BANK0_GPIO24_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO24_OD_MSB 7 -#define PADS_BANK0_GPIO24_OD_LSB 7 +#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO24_OD_MSB _u(7) +#define PADS_BANK0_GPIO24_OD_LSB _u(7) #define PADS_BANK0_GPIO24_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_IE // Description : Input enable -#define PADS_BANK0_GPIO24_IE_RESET 0x1 -#define PADS_BANK0_GPIO24_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO24_IE_MSB 6 -#define PADS_BANK0_GPIO24_IE_LSB 6 +#define PADS_BANK0_GPIO24_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO24_IE_MSB _u(6) +#define PADS_BANK0_GPIO24_IE_LSB _u(6) #define PADS_BANK0_GPIO24_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_DRIVE @@ -1758,69 +1758,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO24_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO24_DRIVE_MSB 5 -#define PADS_BANK0_GPIO24_DRIVE_LSB 4 +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO24_PUE_RESET 0x0 -#define PADS_BANK0_GPIO24_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO24_PUE_MSB 3 -#define PADS_BANK0_GPIO24_PUE_LSB 3 +#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO24_PUE_MSB _u(3) +#define PADS_BANK0_GPIO24_PUE_LSB _u(3) #define PADS_BANK0_GPIO24_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO24_PDE_RESET 0x1 -#define PADS_BANK0_GPIO24_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO24_PDE_MSB 2 -#define PADS_BANK0_GPIO24_PDE_LSB 2 +#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO24_PDE_MSB _u(2) +#define PADS_BANK0_GPIO24_PDE_LSB _u(2) #define PADS_BANK0_GPIO24_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO24_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO24_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO24_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO24_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO24_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO24_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO24_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO24_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO25 // Description : Pad control register -#define PADS_BANK0_GPIO25_OFFSET 0x00000068 -#define PADS_BANK0_GPIO25_BITS 0x000000ff -#define PADS_BANK0_GPIO25_RESET 0x00000056 +#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) +#define PADS_BANK0_GPIO25_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO25_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO25_OD_RESET 0x0 -#define PADS_BANK0_GPIO25_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO25_OD_MSB 7 -#define PADS_BANK0_GPIO25_OD_LSB 7 +#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO25_OD_MSB _u(7) +#define PADS_BANK0_GPIO25_OD_LSB _u(7) #define PADS_BANK0_GPIO25_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_IE // Description : Input enable -#define PADS_BANK0_GPIO25_IE_RESET 0x1 -#define PADS_BANK0_GPIO25_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO25_IE_MSB 6 -#define PADS_BANK0_GPIO25_IE_LSB 6 +#define PADS_BANK0_GPIO25_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO25_IE_MSB _u(6) +#define PADS_BANK0_GPIO25_IE_LSB _u(6) #define PADS_BANK0_GPIO25_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_DRIVE @@ -1829,69 +1829,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO25_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO25_DRIVE_MSB 5 -#define PADS_BANK0_GPIO25_DRIVE_LSB 4 +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO25_PUE_RESET 0x0 -#define PADS_BANK0_GPIO25_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO25_PUE_MSB 3 -#define PADS_BANK0_GPIO25_PUE_LSB 3 +#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO25_PUE_MSB _u(3) +#define PADS_BANK0_GPIO25_PUE_LSB _u(3) #define PADS_BANK0_GPIO25_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO25_PDE_RESET 0x1 -#define PADS_BANK0_GPIO25_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO25_PDE_MSB 2 -#define PADS_BANK0_GPIO25_PDE_LSB 2 +#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO25_PDE_MSB _u(2) +#define PADS_BANK0_GPIO25_PDE_LSB _u(2) #define PADS_BANK0_GPIO25_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO25_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO25_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO25_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO25_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO25_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO25_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO25_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO25_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO26 // Description : Pad control register -#define PADS_BANK0_GPIO26_OFFSET 0x0000006c -#define PADS_BANK0_GPIO26_BITS 0x000000ff -#define PADS_BANK0_GPIO26_RESET 0x00000056 +#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) +#define PADS_BANK0_GPIO26_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO26_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO26_OD_RESET 0x0 -#define PADS_BANK0_GPIO26_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO26_OD_MSB 7 -#define PADS_BANK0_GPIO26_OD_LSB 7 +#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO26_OD_MSB _u(7) +#define PADS_BANK0_GPIO26_OD_LSB _u(7) #define PADS_BANK0_GPIO26_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_IE // Description : Input enable -#define PADS_BANK0_GPIO26_IE_RESET 0x1 -#define PADS_BANK0_GPIO26_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO26_IE_MSB 6 -#define PADS_BANK0_GPIO26_IE_LSB 6 +#define PADS_BANK0_GPIO26_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO26_IE_MSB _u(6) +#define PADS_BANK0_GPIO26_IE_LSB _u(6) #define PADS_BANK0_GPIO26_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_DRIVE @@ -1900,69 +1900,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO26_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO26_DRIVE_MSB 5 -#define PADS_BANK0_GPIO26_DRIVE_LSB 4 +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO26_PUE_RESET 0x0 -#define PADS_BANK0_GPIO26_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO26_PUE_MSB 3 -#define PADS_BANK0_GPIO26_PUE_LSB 3 +#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO26_PUE_MSB _u(3) +#define PADS_BANK0_GPIO26_PUE_LSB _u(3) #define PADS_BANK0_GPIO26_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO26_PDE_RESET 0x1 -#define PADS_BANK0_GPIO26_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO26_PDE_MSB 2 -#define PADS_BANK0_GPIO26_PDE_LSB 2 +#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO26_PDE_MSB _u(2) +#define PADS_BANK0_GPIO26_PDE_LSB _u(2) #define PADS_BANK0_GPIO26_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO26_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO26_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO26_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO26_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO26_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO26_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO26_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO26_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO27 // Description : Pad control register -#define PADS_BANK0_GPIO27_OFFSET 0x00000070 -#define PADS_BANK0_GPIO27_BITS 0x000000ff -#define PADS_BANK0_GPIO27_RESET 0x00000056 +#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) +#define PADS_BANK0_GPIO27_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO27_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO27_OD_RESET 0x0 -#define PADS_BANK0_GPIO27_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO27_OD_MSB 7 -#define PADS_BANK0_GPIO27_OD_LSB 7 +#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO27_OD_MSB _u(7) +#define PADS_BANK0_GPIO27_OD_LSB _u(7) #define PADS_BANK0_GPIO27_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_IE // Description : Input enable -#define PADS_BANK0_GPIO27_IE_RESET 0x1 -#define PADS_BANK0_GPIO27_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO27_IE_MSB 6 -#define PADS_BANK0_GPIO27_IE_LSB 6 +#define PADS_BANK0_GPIO27_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO27_IE_MSB _u(6) +#define PADS_BANK0_GPIO27_IE_LSB _u(6) #define PADS_BANK0_GPIO27_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_DRIVE @@ -1971,69 +1971,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO27_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO27_DRIVE_MSB 5 -#define PADS_BANK0_GPIO27_DRIVE_LSB 4 +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO27_PUE_RESET 0x0 -#define PADS_BANK0_GPIO27_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO27_PUE_MSB 3 -#define PADS_BANK0_GPIO27_PUE_LSB 3 +#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO27_PUE_MSB _u(3) +#define PADS_BANK0_GPIO27_PUE_LSB _u(3) #define PADS_BANK0_GPIO27_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO27_PDE_RESET 0x1 -#define PADS_BANK0_GPIO27_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO27_PDE_MSB 2 -#define PADS_BANK0_GPIO27_PDE_LSB 2 +#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO27_PDE_MSB _u(2) +#define PADS_BANK0_GPIO27_PDE_LSB _u(2) #define PADS_BANK0_GPIO27_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO27_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO27_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO27_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO27_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO27_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO27_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO27_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO27_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO28 // Description : Pad control register -#define PADS_BANK0_GPIO28_OFFSET 0x00000074 -#define PADS_BANK0_GPIO28_BITS 0x000000ff -#define PADS_BANK0_GPIO28_RESET 0x00000056 +#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) +#define PADS_BANK0_GPIO28_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO28_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO28_OD_RESET 0x0 -#define PADS_BANK0_GPIO28_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO28_OD_MSB 7 -#define PADS_BANK0_GPIO28_OD_LSB 7 +#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO28_OD_MSB _u(7) +#define PADS_BANK0_GPIO28_OD_LSB _u(7) #define PADS_BANK0_GPIO28_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_IE // Description : Input enable -#define PADS_BANK0_GPIO28_IE_RESET 0x1 -#define PADS_BANK0_GPIO28_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO28_IE_MSB 6 -#define PADS_BANK0_GPIO28_IE_LSB 6 +#define PADS_BANK0_GPIO28_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO28_IE_MSB _u(6) +#define PADS_BANK0_GPIO28_IE_LSB _u(6) #define PADS_BANK0_GPIO28_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_DRIVE @@ -2042,69 +2042,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO28_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO28_DRIVE_MSB 5 -#define PADS_BANK0_GPIO28_DRIVE_LSB 4 +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO28_PUE_RESET 0x0 -#define PADS_BANK0_GPIO28_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO28_PUE_MSB 3 -#define PADS_BANK0_GPIO28_PUE_LSB 3 +#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO28_PUE_MSB _u(3) +#define PADS_BANK0_GPIO28_PUE_LSB _u(3) #define PADS_BANK0_GPIO28_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO28_PDE_RESET 0x1 -#define PADS_BANK0_GPIO28_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO28_PDE_MSB 2 -#define PADS_BANK0_GPIO28_PDE_LSB 2 +#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO28_PDE_MSB _u(2) +#define PADS_BANK0_GPIO28_PDE_LSB _u(2) #define PADS_BANK0_GPIO28_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO28_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO28_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO28_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO28_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO28_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO28_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO28_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO28_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO29 // Description : Pad control register -#define PADS_BANK0_GPIO29_OFFSET 0x00000078 -#define PADS_BANK0_GPIO29_BITS 0x000000ff -#define PADS_BANK0_GPIO29_RESET 0x00000056 +#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) +#define PADS_BANK0_GPIO29_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO29_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO29_OD_RESET 0x0 -#define PADS_BANK0_GPIO29_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO29_OD_MSB 7 -#define PADS_BANK0_GPIO29_OD_LSB 7 +#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO29_OD_MSB _u(7) +#define PADS_BANK0_GPIO29_OD_LSB _u(7) #define PADS_BANK0_GPIO29_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_IE // Description : Input enable -#define PADS_BANK0_GPIO29_IE_RESET 0x1 -#define PADS_BANK0_GPIO29_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO29_IE_MSB 6 -#define PADS_BANK0_GPIO29_IE_LSB 6 +#define PADS_BANK0_GPIO29_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO29_IE_MSB _u(6) +#define PADS_BANK0_GPIO29_IE_LSB _u(6) #define PADS_BANK0_GPIO29_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_DRIVE @@ -2113,69 +2113,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO29_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO29_DRIVE_MSB 5 -#define PADS_BANK0_GPIO29_DRIVE_LSB 4 +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO29_PUE_RESET 0x0 -#define PADS_BANK0_GPIO29_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO29_PUE_MSB 3 -#define PADS_BANK0_GPIO29_PUE_LSB 3 +#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO29_PUE_MSB _u(3) +#define PADS_BANK0_GPIO29_PUE_LSB _u(3) #define PADS_BANK0_GPIO29_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO29_PDE_RESET 0x1 -#define PADS_BANK0_GPIO29_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO29_PDE_MSB 2 -#define PADS_BANK0_GPIO29_PDE_LSB 2 +#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO29_PDE_MSB _u(2) +#define PADS_BANK0_GPIO29_PDE_LSB _u(2) #define PADS_BANK0_GPIO29_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO29_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO29_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO29_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO29_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO29_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO29_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO29_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO29_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_SWCLK // Description : Pad control register -#define PADS_BANK0_SWCLK_OFFSET 0x0000007c -#define PADS_BANK0_SWCLK_BITS 0x000000ff -#define PADS_BANK0_SWCLK_RESET 0x000000da +#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c) +#define PADS_BANK0_SWCLK_BITS _u(0x000000ff) +#define PADS_BANK0_SWCLK_RESET _u(0x000000da) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_SWCLK_OD_RESET 0x1 -#define PADS_BANK0_SWCLK_OD_BITS 0x00000080 -#define PADS_BANK0_SWCLK_OD_MSB 7 -#define PADS_BANK0_SWCLK_OD_LSB 7 +#define PADS_BANK0_SWCLK_OD_RESET _u(0x1) +#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWCLK_OD_MSB _u(7) +#define PADS_BANK0_SWCLK_OD_LSB _u(7) #define PADS_BANK0_SWCLK_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_IE // Description : Input enable -#define PADS_BANK0_SWCLK_IE_RESET 0x1 -#define PADS_BANK0_SWCLK_IE_BITS 0x00000040 -#define PADS_BANK0_SWCLK_IE_MSB 6 -#define PADS_BANK0_SWCLK_IE_LSB 6 +#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWCLK_IE_MSB _u(6) +#define PADS_BANK0_SWCLK_IE_LSB _u(6) #define PADS_BANK0_SWCLK_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_DRIVE @@ -2184,69 +2184,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET 0x1 -#define PADS_BANK0_SWCLK_DRIVE_BITS 0x00000030 -#define PADS_BANK0_SWCLK_DRIVE_MSB 5 -#define PADS_BANK0_SWCLK_DRIVE_LSB 4 +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) #define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PUE // Description : Pull up enable -#define PADS_BANK0_SWCLK_PUE_RESET 0x1 -#define PADS_BANK0_SWCLK_PUE_BITS 0x00000008 -#define PADS_BANK0_SWCLK_PUE_MSB 3 -#define PADS_BANK0_SWCLK_PUE_LSB 3 +#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWCLK_PUE_MSB _u(3) +#define PADS_BANK0_SWCLK_PUE_LSB _u(3) #define PADS_BANK0_SWCLK_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PDE // Description : Pull down enable -#define PADS_BANK0_SWCLK_PDE_RESET 0x0 -#define PADS_BANK0_SWCLK_PDE_BITS 0x00000004 -#define PADS_BANK0_SWCLK_PDE_MSB 2 -#define PADS_BANK0_SWCLK_PDE_LSB 2 +#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) +#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWCLK_PDE_MSB _u(2) +#define PADS_BANK0_SWCLK_PDE_LSB _u(2) #define PADS_BANK0_SWCLK_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_SWCLK_SCHMITT_RESET 0x1 -#define PADS_BANK0_SWCLK_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_SWCLK_SCHMITT_MSB 1 -#define PADS_BANK0_SWCLK_SCHMITT_LSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) #define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWCLK_SLEWFAST_RESET 0x0 -#define PADS_BANK0_SWCLK_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_SWCLK_SLEWFAST_MSB 0 -#define PADS_BANK0_SWCLK_SLEWFAST_LSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_SWD // Description : Pad control register -#define PADS_BANK0_SWD_OFFSET 0x00000080 -#define PADS_BANK0_SWD_BITS 0x000000ff -#define PADS_BANK0_SWD_RESET 0x0000005a +#define PADS_BANK0_SWD_OFFSET _u(0x00000080) +#define PADS_BANK0_SWD_BITS _u(0x000000ff) +#define PADS_BANK0_SWD_RESET _u(0x0000005a) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_SWD_OD_RESET 0x0 -#define PADS_BANK0_SWD_OD_BITS 0x00000080 -#define PADS_BANK0_SWD_OD_MSB 7 -#define PADS_BANK0_SWD_OD_LSB 7 +#define PADS_BANK0_SWD_OD_RESET _u(0x0) +#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWD_OD_MSB _u(7) +#define PADS_BANK0_SWD_OD_LSB _u(7) #define PADS_BANK0_SWD_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_IE // Description : Input enable -#define PADS_BANK0_SWD_IE_RESET 0x1 -#define PADS_BANK0_SWD_IE_BITS 0x00000040 -#define PADS_BANK0_SWD_IE_MSB 6 -#define PADS_BANK0_SWD_IE_LSB 6 +#define PADS_BANK0_SWD_IE_RESET _u(0x1) +#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWD_IE_MSB _u(6) +#define PADS_BANK0_SWD_IE_LSB _u(6) #define PADS_BANK0_SWD_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_DRIVE @@ -2255,46 +2255,46 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET 0x1 -#define PADS_BANK0_SWD_DRIVE_BITS 0x00000030 -#define PADS_BANK0_SWD_DRIVE_MSB 5 -#define PADS_BANK0_SWD_DRIVE_LSB 4 +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) #define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_SWD_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PUE // Description : Pull up enable -#define PADS_BANK0_SWD_PUE_RESET 0x1 -#define PADS_BANK0_SWD_PUE_BITS 0x00000008 -#define PADS_BANK0_SWD_PUE_MSB 3 -#define PADS_BANK0_SWD_PUE_LSB 3 +#define PADS_BANK0_SWD_PUE_RESET _u(0x1) +#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWD_PUE_MSB _u(3) +#define PADS_BANK0_SWD_PUE_LSB _u(3) #define PADS_BANK0_SWD_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PDE // Description : Pull down enable -#define PADS_BANK0_SWD_PDE_RESET 0x0 -#define PADS_BANK0_SWD_PDE_BITS 0x00000004 -#define PADS_BANK0_SWD_PDE_MSB 2 -#define PADS_BANK0_SWD_PDE_LSB 2 +#define PADS_BANK0_SWD_PDE_RESET _u(0x0) +#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWD_PDE_MSB _u(2) +#define PADS_BANK0_SWD_PDE_LSB _u(2) #define PADS_BANK0_SWD_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_SWD_SCHMITT_RESET 0x1 -#define PADS_BANK0_SWD_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_SWD_SCHMITT_MSB 1 -#define PADS_BANK0_SWD_SCHMITT_LSB 1 +#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) #define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWD_SLEWFAST_RESET 0x0 -#define PADS_BANK0_SWD_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_SWD_SLEWFAST_MSB 0 -#define PADS_BANK0_SWD_SLEWFAST_LSB 0 +#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PADS_BANK0_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h index 7aba5e856a3..b3a09e9001f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h @@ -16,36 +16,36 @@ // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000 -#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001 -#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000 -#define PADS_QSPI_VOLTAGE_SELECT_MSB 0 -#define PADS_QSPI_VOLTAGE_SELECT_LSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) #define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0 -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1 +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SCLK // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056 +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE @@ -54,69 +54,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD0 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE @@ -125,69 +125,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD1 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c -#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) +#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE @@ -196,69 +196,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD2 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010 -#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) +#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE @@ -267,69 +267,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD3 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014 -#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) +#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE @@ -338,69 +338,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SS // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018 -#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) +#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE @@ -409,46 +409,46 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PADS_QSPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h index 503aa094098..b231882ac89 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h @@ -14,323 +14,388 @@ // ============================================================================= // Register : PIO_CTRL // Description : PIO control register -#define PIO_CTRL_OFFSET 0x00000000 -#define PIO_CTRL_BITS 0x00000fff -#define PIO_CTRL_RESET 0x00000000 +#define PIO_CTRL_OFFSET _u(0x00000000) +#define PIO_CTRL_BITS _u(0x00000fff) +#define PIO_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_CTRL_CLKDIV_RESTART -// Description : Force clock dividers to restart their count and clear -// fractional -// accumulators. Restart multiple dividers to synchronise them. -#define PIO_CTRL_CLKDIV_RESTART_RESET 0x0 -#define PIO_CTRL_CLKDIV_RESTART_BITS 0x00000f00 -#define PIO_CTRL_CLKDIV_RESTART_MSB 11 -#define PIO_CTRL_CLKDIV_RESTART_LSB 8 +// Description : Restart a state machine's clock divider from an initial phase +// of 0. Clock dividers are free-running, so once started, their +// output (including fractional jitter) is completely determined +// by the integer/fractional divisor configured in SMx_CLKDIV. +// This means that, if multiple clock dividers with the same +// divisor are restarted simultaneously, by writing multiple 1 +// bits to this field, the execution clocks of those state +// machines will run in precise lockstep. +// +// Note that setting/clearing SM_ENABLE does not stop the clock +// divider from running, so once multiple state machines' clocks +// are synchronised, it is safe to disable/reenable a state +// machine, whilst keeping the clock dividers in sync. +// +// Note also that CLKDIV_RESTART can be written to whilst the +// state machine is running, and this is useful to resynchronise +// clock dividers after the divisors (SMx_CLKDIV) have been +// changed on-the-fly. +#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) +#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) +#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) #define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PIO_CTRL_SM_RESTART -// Description : Clear internal SM state which is otherwise difficult to access -// (e.g. shift counters). Self-clearing. -#define PIO_CTRL_SM_RESTART_RESET 0x0 -#define PIO_CTRL_SM_RESTART_BITS 0x000000f0 -#define PIO_CTRL_SM_RESTART_MSB 7 -#define PIO_CTRL_SM_RESTART_LSB 4 +// Description : Write 1 to instantly clear internal SM state which may be +// otherwise difficult to access and will affect future execution. +// +// Specifically, the following are cleared: input and output shift +// counters; the contents of the input shift register; the delay +// counter; the waiting-on-IRQ state; any stalled instruction +// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left +// asserted due to OUT_STICKY. +#define PIO_CTRL_SM_RESTART_RESET _u(0x0) +#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) +#define PIO_CTRL_SM_RESTART_MSB _u(7) +#define PIO_CTRL_SM_RESTART_LSB _u(4) #define PIO_CTRL_SM_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PIO_CTRL_SM_ENABLE -// Description : Enable state machine -#define PIO_CTRL_SM_ENABLE_RESET 0x0 -#define PIO_CTRL_SM_ENABLE_BITS 0x0000000f -#define PIO_CTRL_SM_ENABLE_MSB 3 -#define PIO_CTRL_SM_ENABLE_LSB 0 +// Description : Enable/disable each of the four state machines by writing 1/0 +// to each of these four bits. When disabled, a state machine will +// cease executing instructions, except those written directly to +// SMx_INSTR by the system. Multiple bits can be set/cleared at +// once to run/halt multiple state machines simultaneously. +#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) +#define PIO_CTRL_SM_ENABLE_MSB _u(3) +#define PIO_CTRL_SM_ENABLE_LSB _u(0) #define PIO_CTRL_SM_ENABLE_ACCESS "RW" // ============================================================================= // Register : PIO_FSTAT // Description : FIFO status register -#define PIO_FSTAT_OFFSET 0x00000004 -#define PIO_FSTAT_BITS 0x0f0f0f0f -#define PIO_FSTAT_RESET 0x0f000f00 +#define PIO_FSTAT_OFFSET _u(0x00000004) +#define PIO_FSTAT_BITS _u(0x0f0f0f0f) +#define PIO_FSTAT_RESET _u(0x0f000f00) // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_TXEMPTY // Description : State machine TX FIFO is empty -#define PIO_FSTAT_TXEMPTY_RESET 0xf -#define PIO_FSTAT_TXEMPTY_BITS 0x0f000000 -#define PIO_FSTAT_TXEMPTY_MSB 27 -#define PIO_FSTAT_TXEMPTY_LSB 24 +#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) +#define PIO_FSTAT_TXEMPTY_MSB _u(27) +#define PIO_FSTAT_TXEMPTY_LSB _u(24) #define PIO_FSTAT_TXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_TXFULL // Description : State machine TX FIFO is full -#define PIO_FSTAT_TXFULL_RESET 0x0 -#define PIO_FSTAT_TXFULL_BITS 0x000f0000 -#define PIO_FSTAT_TXFULL_MSB 19 -#define PIO_FSTAT_TXFULL_LSB 16 +#define PIO_FSTAT_TXFULL_RESET _u(0x0) +#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) +#define PIO_FSTAT_TXFULL_MSB _u(19) +#define PIO_FSTAT_TXFULL_LSB _u(16) #define PIO_FSTAT_TXFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_RXEMPTY // Description : State machine RX FIFO is empty -#define PIO_FSTAT_RXEMPTY_RESET 0xf -#define PIO_FSTAT_RXEMPTY_BITS 0x00000f00 -#define PIO_FSTAT_RXEMPTY_MSB 11 -#define PIO_FSTAT_RXEMPTY_LSB 8 +#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) +#define PIO_FSTAT_RXEMPTY_MSB _u(11) +#define PIO_FSTAT_RXEMPTY_LSB _u(8) #define PIO_FSTAT_RXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_RXFULL // Description : State machine RX FIFO is full -#define PIO_FSTAT_RXFULL_RESET 0x0 -#define PIO_FSTAT_RXFULL_BITS 0x0000000f -#define PIO_FSTAT_RXFULL_MSB 3 -#define PIO_FSTAT_RXFULL_LSB 0 +#define PIO_FSTAT_RXFULL_RESET _u(0x0) +#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) +#define PIO_FSTAT_RXFULL_MSB _u(3) +#define PIO_FSTAT_RXFULL_LSB _u(0) #define PIO_FSTAT_RXFULL_ACCESS "RO" // ============================================================================= // Register : PIO_FDEBUG // Description : FIFO debug register -#define PIO_FDEBUG_OFFSET 0x00000008 -#define PIO_FDEBUG_BITS 0x0f0f0f0f -#define PIO_FDEBUG_RESET 0x00000000 +#define PIO_FDEBUG_OFFSET _u(0x00000008) +#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) +#define PIO_FDEBUG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_TXSTALL -// Description : State machine has stalled on empty TX FIFO. Write 1 to clear. -#define PIO_FDEBUG_TXSTALL_RESET 0x0 -#define PIO_FDEBUG_TXSTALL_BITS 0x0f000000 -#define PIO_FDEBUG_TXSTALL_MSB 27 -#define PIO_FDEBUG_TXSTALL_LSB 24 +// Description : State machine has stalled on empty TX FIFO during a blocking +// PULL, or an OUT with autopull enabled. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) +#define PIO_FDEBUG_TXSTALL_MSB _u(27) +#define PIO_FDEBUG_TXSTALL_LSB _u(24) #define PIO_FDEBUG_TXSTALL_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_TXOVER -// Description : TX FIFO overflow has occurred. Write 1 to clear. -#define PIO_FDEBUG_TXOVER_RESET 0x0 -#define PIO_FDEBUG_TXOVER_BITS 0x000f0000 -#define PIO_FDEBUG_TXOVER_MSB 19 -#define PIO_FDEBUG_TXOVER_LSB 16 +// Description : TX FIFO overflow (i.e. write-on-full by the system) has +// occurred. Write 1 to clear. Note that write-on-full does not +// alter the state or contents of the FIFO in any way, but the +// data that the system attempted to write is dropped, so if this +// flag is set, your software has quite likely dropped some data +// on the floor. +#define PIO_FDEBUG_TXOVER_RESET _u(0x0) +#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) +#define PIO_FDEBUG_TXOVER_MSB _u(19) +#define PIO_FDEBUG_TXOVER_LSB _u(16) #define PIO_FDEBUG_TXOVER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_RXUNDER -// Description : RX FIFO underflow has occurred. Write 1 to clear. -#define PIO_FDEBUG_RXUNDER_RESET 0x0 -#define PIO_FDEBUG_RXUNDER_BITS 0x00000f00 -#define PIO_FDEBUG_RXUNDER_MSB 11 -#define PIO_FDEBUG_RXUNDER_LSB 8 +// Description : RX FIFO underflow (i.e. read-on-empty by the system) has +// occurred. Write 1 to clear. Note that read-on-empty does not +// perturb the state of the FIFO in any way, but the data returned +// by reading from an empty FIFO is undefined, so this flag +// generally only becomes set due to some kind of software error. +#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) +#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) +#define PIO_FDEBUG_RXUNDER_MSB _u(11) +#define PIO_FDEBUG_RXUNDER_LSB _u(8) #define PIO_FDEBUG_RXUNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_RXSTALL -// Description : State machine has stalled on full RX FIFO. Write 1 to clear. -#define PIO_FDEBUG_RXSTALL_RESET 0x0 -#define PIO_FDEBUG_RXSTALL_BITS 0x0000000f -#define PIO_FDEBUG_RXSTALL_MSB 3 -#define PIO_FDEBUG_RXSTALL_LSB 0 +// Description : State machine has stalled on full RX FIFO during a blocking +// PUSH, or an IN with autopush enabled. This flag is also set +// when a nonblocking PUSH to a full FIFO took place, in which +// case the state machine has dropped data. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) +#define PIO_FDEBUG_RXSTALL_MSB _u(3) +#define PIO_FDEBUG_RXSTALL_LSB _u(0) #define PIO_FDEBUG_RXSTALL_ACCESS "WC" // ============================================================================= // Register : PIO_FLEVEL // Description : FIFO levels -#define PIO_FLEVEL_OFFSET 0x0000000c -#define PIO_FLEVEL_BITS 0xffffffff -#define PIO_FLEVEL_RESET 0x00000000 +#define PIO_FLEVEL_OFFSET _u(0x0000000c) +#define PIO_FLEVEL_BITS _u(0xffffffff) +#define PIO_FLEVEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX3 // Description : None -#define PIO_FLEVEL_RX3_RESET 0x0 -#define PIO_FLEVEL_RX3_BITS 0xf0000000 -#define PIO_FLEVEL_RX3_MSB 31 -#define PIO_FLEVEL_RX3_LSB 28 +#define PIO_FLEVEL_RX3_RESET _u(0x0) +#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) +#define PIO_FLEVEL_RX3_MSB _u(31) +#define PIO_FLEVEL_RX3_LSB _u(28) #define PIO_FLEVEL_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX3 // Description : None -#define PIO_FLEVEL_TX3_RESET 0x0 -#define PIO_FLEVEL_TX3_BITS 0x0f000000 -#define PIO_FLEVEL_TX3_MSB 27 -#define PIO_FLEVEL_TX3_LSB 24 +#define PIO_FLEVEL_TX3_RESET _u(0x0) +#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) +#define PIO_FLEVEL_TX3_MSB _u(27) +#define PIO_FLEVEL_TX3_LSB _u(24) #define PIO_FLEVEL_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX2 // Description : None -#define PIO_FLEVEL_RX2_RESET 0x0 -#define PIO_FLEVEL_RX2_BITS 0x00f00000 -#define PIO_FLEVEL_RX2_MSB 23 -#define PIO_FLEVEL_RX2_LSB 20 +#define PIO_FLEVEL_RX2_RESET _u(0x0) +#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) +#define PIO_FLEVEL_RX2_MSB _u(23) +#define PIO_FLEVEL_RX2_LSB _u(20) #define PIO_FLEVEL_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX2 // Description : None -#define PIO_FLEVEL_TX2_RESET 0x0 -#define PIO_FLEVEL_TX2_BITS 0x000f0000 -#define PIO_FLEVEL_TX2_MSB 19 -#define PIO_FLEVEL_TX2_LSB 16 +#define PIO_FLEVEL_TX2_RESET _u(0x0) +#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) +#define PIO_FLEVEL_TX2_MSB _u(19) +#define PIO_FLEVEL_TX2_LSB _u(16) #define PIO_FLEVEL_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX1 // Description : None -#define PIO_FLEVEL_RX1_RESET 0x0 -#define PIO_FLEVEL_RX1_BITS 0x0000f000 -#define PIO_FLEVEL_RX1_MSB 15 -#define PIO_FLEVEL_RX1_LSB 12 +#define PIO_FLEVEL_RX1_RESET _u(0x0) +#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) +#define PIO_FLEVEL_RX1_MSB _u(15) +#define PIO_FLEVEL_RX1_LSB _u(12) #define PIO_FLEVEL_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX1 // Description : None -#define PIO_FLEVEL_TX1_RESET 0x0 -#define PIO_FLEVEL_TX1_BITS 0x00000f00 -#define PIO_FLEVEL_TX1_MSB 11 -#define PIO_FLEVEL_TX1_LSB 8 +#define PIO_FLEVEL_TX1_RESET _u(0x0) +#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) +#define PIO_FLEVEL_TX1_MSB _u(11) +#define PIO_FLEVEL_TX1_LSB _u(8) #define PIO_FLEVEL_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX0 // Description : None -#define PIO_FLEVEL_RX0_RESET 0x0 -#define PIO_FLEVEL_RX0_BITS 0x000000f0 -#define PIO_FLEVEL_RX0_MSB 7 -#define PIO_FLEVEL_RX0_LSB 4 +#define PIO_FLEVEL_RX0_RESET _u(0x0) +#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) +#define PIO_FLEVEL_RX0_MSB _u(7) +#define PIO_FLEVEL_RX0_LSB _u(4) #define PIO_FLEVEL_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX0 // Description : None -#define PIO_FLEVEL_TX0_RESET 0x0 -#define PIO_FLEVEL_TX0_BITS 0x0000000f -#define PIO_FLEVEL_TX0_MSB 3 -#define PIO_FLEVEL_TX0_LSB 0 +#define PIO_FLEVEL_TX0_RESET _u(0x0) +#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) +#define PIO_FLEVEL_TX0_MSB _u(3) +#define PIO_FLEVEL_TX0_LSB _u(0) #define PIO_FLEVEL_TX0_ACCESS "RO" // ============================================================================= // Register : PIO_TXF0 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF0_OFFSET 0x00000010 -#define PIO_TXF0_BITS 0xffffffff -#define PIO_TXF0_RESET 0x00000000 -#define PIO_TXF0_MSB 31 -#define PIO_TXF0_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF0_OFFSET _u(0x00000010) +#define PIO_TXF0_BITS _u(0xffffffff) +#define PIO_TXF0_RESET _u(0x00000000) +#define PIO_TXF0_MSB _u(31) +#define PIO_TXF0_LSB _u(0) #define PIO_TXF0_ACCESS "WF" // ============================================================================= // Register : PIO_TXF1 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF1_OFFSET 0x00000014 -#define PIO_TXF1_BITS 0xffffffff -#define PIO_TXF1_RESET 0x00000000 -#define PIO_TXF1_MSB 31 -#define PIO_TXF1_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF1_OFFSET _u(0x00000014) +#define PIO_TXF1_BITS _u(0xffffffff) +#define PIO_TXF1_RESET _u(0x00000000) +#define PIO_TXF1_MSB _u(31) +#define PIO_TXF1_LSB _u(0) #define PIO_TXF1_ACCESS "WF" // ============================================================================= // Register : PIO_TXF2 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF2_OFFSET 0x00000018 -#define PIO_TXF2_BITS 0xffffffff -#define PIO_TXF2_RESET 0x00000000 -#define PIO_TXF2_MSB 31 -#define PIO_TXF2_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF2_OFFSET _u(0x00000018) +#define PIO_TXF2_BITS _u(0xffffffff) +#define PIO_TXF2_RESET _u(0x00000000) +#define PIO_TXF2_MSB _u(31) +#define PIO_TXF2_LSB _u(0) #define PIO_TXF2_ACCESS "WF" // ============================================================================= // Register : PIO_TXF3 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF3_OFFSET 0x0000001c -#define PIO_TXF3_BITS 0xffffffff -#define PIO_TXF3_RESET 0x00000000 -#define PIO_TXF3_MSB 31 -#define PIO_TXF3_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF3_OFFSET _u(0x0000001c) +#define PIO_TXF3_BITS _u(0xffffffff) +#define PIO_TXF3_RESET _u(0x00000000) +#define PIO_TXF3_MSB _u(31) +#define PIO_TXF3_LSB _u(0) #define PIO_TXF3_ACCESS "WF" // ============================================================================= // Register : PIO_RXF0 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF0_OFFSET 0x00000020 -#define PIO_RXF0_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF0_OFFSET _u(0x00000020) +#define PIO_RXF0_BITS _u(0xffffffff) #define PIO_RXF0_RESET "-" -#define PIO_RXF0_MSB 31 -#define PIO_RXF0_LSB 0 +#define PIO_RXF0_MSB _u(31) +#define PIO_RXF0_LSB _u(0) #define PIO_RXF0_ACCESS "RF" // ============================================================================= // Register : PIO_RXF1 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF1_OFFSET 0x00000024 -#define PIO_RXF1_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF1_OFFSET _u(0x00000024) +#define PIO_RXF1_BITS _u(0xffffffff) #define PIO_RXF1_RESET "-" -#define PIO_RXF1_MSB 31 -#define PIO_RXF1_LSB 0 +#define PIO_RXF1_MSB _u(31) +#define PIO_RXF1_LSB _u(0) #define PIO_RXF1_ACCESS "RF" // ============================================================================= // Register : PIO_RXF2 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF2_OFFSET 0x00000028 -#define PIO_RXF2_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF2_OFFSET _u(0x00000028) +#define PIO_RXF2_BITS _u(0xffffffff) #define PIO_RXF2_RESET "-" -#define PIO_RXF2_MSB 31 -#define PIO_RXF2_LSB 0 +#define PIO_RXF2_MSB _u(31) +#define PIO_RXF2_LSB _u(0) #define PIO_RXF2_ACCESS "RF" // ============================================================================= // Register : PIO_RXF3 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF3_OFFSET 0x0000002c -#define PIO_RXF3_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF3_OFFSET _u(0x0000002c) +#define PIO_RXF3_BITS _u(0xffffffff) #define PIO_RXF3_RESET "-" -#define PIO_RXF3_MSB 31 -#define PIO_RXF3_LSB 0 +#define PIO_RXF3_MSB _u(31) +#define PIO_RXF3_LSB _u(0) #define PIO_RXF3_ACCESS "RF" // ============================================================================= // Register : PIO_IRQ -// Description : Interrupt request register. Write 1 to clear -#define PIO_IRQ_OFFSET 0x00000030 -#define PIO_IRQ_BITS 0x000000ff -#define PIO_IRQ_RESET 0x00000000 -#define PIO_IRQ_MSB 7 -#define PIO_IRQ_LSB 0 +// Description : State machine IRQ flags register. Write 1 to clear. There are 8 +// state machine IRQ flags, which can be set, cleared, and waited +// on by the state machines. There's no fixed association between +// flags and state machines -- any state machine can use any flag. +// +// Any of the 8 flags can be used for timing synchronisation +// between state machines, using IRQ and WAIT instructions. The +// lower four of these flags are also routed out to system-level +// interrupt requests, alongside FIFO status interrupts -- see +// e.g. IRQ0_INTE. +#define PIO_IRQ_OFFSET _u(0x00000030) +#define PIO_IRQ_BITS _u(0x000000ff) +#define PIO_IRQ_RESET _u(0x00000000) +#define PIO_IRQ_MSB _u(7) +#define PIO_IRQ_LSB _u(0) #define PIO_IRQ_ACCESS "WC" // ============================================================================= // Register : PIO_IRQ_FORCE // Description : Writing a 1 to each of these bits will forcibly assert the -// corresponding IRQ. -// Note this is different to the INTF register: writing here -// affects PIO internal -// state. INTF just asserts the processor-facing IRQ signal for -// testing ISRs, -// and is not visible to the state machines. -#define PIO_IRQ_FORCE_OFFSET 0x00000034 -#define PIO_IRQ_FORCE_BITS 0x000000ff -#define PIO_IRQ_FORCE_RESET 0x00000000 -#define PIO_IRQ_FORCE_MSB 7 -#define PIO_IRQ_FORCE_LSB 0 +// corresponding IRQ. Note this is different to the INTF register: +// writing here affects PIO internal state. INTF just asserts the +// processor-facing IRQ signal for testing ISRs, and is not +// visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) +#define PIO_IRQ_FORCE_BITS _u(0x000000ff) +#define PIO_IRQ_FORCE_RESET _u(0x00000000) +#define PIO_IRQ_FORCE_MSB _u(7) +#define PIO_IRQ_FORCE_LSB _u(0) #define PIO_IRQ_FORCE_ACCESS "WF" // ============================================================================= // Register : PIO_INPUT_SYNC_BYPASS // Description : There is a 2-flipflop synchronizer on each GPIO input, which -// protects -// PIO logic from metastabilities. This increases input delay, and -// for fast -// synchronous IO (e.g. SPI) these synchronizers may need to be -// bypassed. -// Each bit in this register corresponds to one GPIO. +// protects PIO logic from metastabilities. This increases input +// delay, and for fast synchronous IO (e.g. SPI) these +// synchronizers may need to be bypassed. Each bit in this +// register corresponds to one GPIO. // 0 -> input is synchronized (default) // 1 -> synchronizer is bypassed // If in doubt, leave this register as all zeroes. -#define PIO_INPUT_SYNC_BYPASS_OFFSET 0x00000038 -#define PIO_INPUT_SYNC_BYPASS_BITS 0xffffffff -#define PIO_INPUT_SYNC_BYPASS_RESET 0x00000000 -#define PIO_INPUT_SYNC_BYPASS_MSB 31 -#define PIO_INPUT_SYNC_BYPASS_LSB 0 +#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) +#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) +#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) +#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) +#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) #define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" // ============================================================================= // Register : PIO_DBG_PADOUT // Description : Read to sample the pad output values PIO is currently driving -// to the GPIOs. -#define PIO_DBG_PADOUT_OFFSET 0x0000003c -#define PIO_DBG_PADOUT_BITS 0xffffffff -#define PIO_DBG_PADOUT_RESET 0x00000000 -#define PIO_DBG_PADOUT_MSB 31 -#define PIO_DBG_PADOUT_LSB 0 +// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most +// significant bits are hardwired to 0. +#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) +#define PIO_DBG_PADOUT_BITS _u(0xffffffff) +#define PIO_DBG_PADOUT_RESET _u(0x00000000) +#define PIO_DBG_PADOUT_MSB _u(31) +#define PIO_DBG_PADOUT_LSB _u(0) #define PIO_DBG_PADOUT_ACCESS "RO" // ============================================================================= // Register : PIO_DBG_PADOE // Description : Read to sample the pad output enables (direction) PIO is -// currently driving to the GPIOs. -#define PIO_DBG_PADOE_OFFSET 0x00000040 -#define PIO_DBG_PADOE_BITS 0xffffffff -#define PIO_DBG_PADOE_RESET 0x00000000 -#define PIO_DBG_PADOE_MSB 31 -#define PIO_DBG_PADOE_LSB 0 +// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, +// so the two most significant bits are hardwired to 0. +#define PIO_DBG_PADOE_OFFSET _u(0x00000040) +#define PIO_DBG_PADOE_BITS _u(0xffffffff) +#define PIO_DBG_PADOE_RESET _u(0x00000000) +#define PIO_DBG_PADOE_MSB _u(31) +#define PIO_DBG_PADOE_LSB _u(0) #define PIO_DBG_PADOE_ACCESS "RO" // ============================================================================= // Register : PIO_DBG_CFGINFO @@ -338,26 +403,26 @@ // chip products. // These should be provided in the chip datasheet, but are also // exposed here. -#define PIO_DBG_CFGINFO_OFFSET 0x00000044 -#define PIO_DBG_CFGINFO_BITS 0x003f0f3f -#define PIO_DBG_CFGINFO_RESET 0x00000000 +#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) +#define PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) +#define PIO_DBG_CFGINFO_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_IMEM_SIZE // Description : The size of the instruction memory, measured in units of one // instruction #define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" -#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS 0x003f0000 -#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB 21 -#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB 16 +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) #define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_SM_COUNT // Description : The number of state machines this PIO instance is equipped // with. #define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" -#define PIO_DBG_CFGINFO_SM_COUNT_BITS 0x00000f00 -#define PIO_DBG_CFGINFO_SM_COUNT_MSB 11 -#define PIO_DBG_CFGINFO_SM_COUNT_LSB 8 +#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) +#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) +#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) #define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_FIFO_DEPTH @@ -365,373 +430,377 @@ // Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double // this depth. #define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" -#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS 0x0000003f -#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB 5 -#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB 0 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) #define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" // ============================================================================= // Register : PIO_INSTR_MEM0 // Description : Write-only access to instruction memory location 0 -#define PIO_INSTR_MEM0_OFFSET 0x00000048 -#define PIO_INSTR_MEM0_BITS 0x0000ffff -#define PIO_INSTR_MEM0_RESET 0x00000000 -#define PIO_INSTR_MEM0_MSB 15 -#define PIO_INSTR_MEM0_LSB 0 +#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) +#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM0_RESET _u(0x00000000) +#define PIO_INSTR_MEM0_MSB _u(15) +#define PIO_INSTR_MEM0_LSB _u(0) #define PIO_INSTR_MEM0_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM1 // Description : Write-only access to instruction memory location 1 -#define PIO_INSTR_MEM1_OFFSET 0x0000004c -#define PIO_INSTR_MEM1_BITS 0x0000ffff -#define PIO_INSTR_MEM1_RESET 0x00000000 -#define PIO_INSTR_MEM1_MSB 15 -#define PIO_INSTR_MEM1_LSB 0 +#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) +#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM1_RESET _u(0x00000000) +#define PIO_INSTR_MEM1_MSB _u(15) +#define PIO_INSTR_MEM1_LSB _u(0) #define PIO_INSTR_MEM1_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM2 // Description : Write-only access to instruction memory location 2 -#define PIO_INSTR_MEM2_OFFSET 0x00000050 -#define PIO_INSTR_MEM2_BITS 0x0000ffff -#define PIO_INSTR_MEM2_RESET 0x00000000 -#define PIO_INSTR_MEM2_MSB 15 -#define PIO_INSTR_MEM2_LSB 0 +#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) +#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM2_RESET _u(0x00000000) +#define PIO_INSTR_MEM2_MSB _u(15) +#define PIO_INSTR_MEM2_LSB _u(0) #define PIO_INSTR_MEM2_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM3 // Description : Write-only access to instruction memory location 3 -#define PIO_INSTR_MEM3_OFFSET 0x00000054 -#define PIO_INSTR_MEM3_BITS 0x0000ffff -#define PIO_INSTR_MEM3_RESET 0x00000000 -#define PIO_INSTR_MEM3_MSB 15 -#define PIO_INSTR_MEM3_LSB 0 +#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) +#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM3_RESET _u(0x00000000) +#define PIO_INSTR_MEM3_MSB _u(15) +#define PIO_INSTR_MEM3_LSB _u(0) #define PIO_INSTR_MEM3_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM4 // Description : Write-only access to instruction memory location 4 -#define PIO_INSTR_MEM4_OFFSET 0x00000058 -#define PIO_INSTR_MEM4_BITS 0x0000ffff -#define PIO_INSTR_MEM4_RESET 0x00000000 -#define PIO_INSTR_MEM4_MSB 15 -#define PIO_INSTR_MEM4_LSB 0 +#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) +#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM4_RESET _u(0x00000000) +#define PIO_INSTR_MEM4_MSB _u(15) +#define PIO_INSTR_MEM4_LSB _u(0) #define PIO_INSTR_MEM4_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM5 // Description : Write-only access to instruction memory location 5 -#define PIO_INSTR_MEM5_OFFSET 0x0000005c -#define PIO_INSTR_MEM5_BITS 0x0000ffff -#define PIO_INSTR_MEM5_RESET 0x00000000 -#define PIO_INSTR_MEM5_MSB 15 -#define PIO_INSTR_MEM5_LSB 0 +#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) +#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM5_RESET _u(0x00000000) +#define PIO_INSTR_MEM5_MSB _u(15) +#define PIO_INSTR_MEM5_LSB _u(0) #define PIO_INSTR_MEM5_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM6 // Description : Write-only access to instruction memory location 6 -#define PIO_INSTR_MEM6_OFFSET 0x00000060 -#define PIO_INSTR_MEM6_BITS 0x0000ffff -#define PIO_INSTR_MEM6_RESET 0x00000000 -#define PIO_INSTR_MEM6_MSB 15 -#define PIO_INSTR_MEM6_LSB 0 +#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) +#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM6_RESET _u(0x00000000) +#define PIO_INSTR_MEM6_MSB _u(15) +#define PIO_INSTR_MEM6_LSB _u(0) #define PIO_INSTR_MEM6_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM7 // Description : Write-only access to instruction memory location 7 -#define PIO_INSTR_MEM7_OFFSET 0x00000064 -#define PIO_INSTR_MEM7_BITS 0x0000ffff -#define PIO_INSTR_MEM7_RESET 0x00000000 -#define PIO_INSTR_MEM7_MSB 15 -#define PIO_INSTR_MEM7_LSB 0 +#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) +#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM7_RESET _u(0x00000000) +#define PIO_INSTR_MEM7_MSB _u(15) +#define PIO_INSTR_MEM7_LSB _u(0) #define PIO_INSTR_MEM7_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM8 // Description : Write-only access to instruction memory location 8 -#define PIO_INSTR_MEM8_OFFSET 0x00000068 -#define PIO_INSTR_MEM8_BITS 0x0000ffff -#define PIO_INSTR_MEM8_RESET 0x00000000 -#define PIO_INSTR_MEM8_MSB 15 -#define PIO_INSTR_MEM8_LSB 0 +#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) +#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM8_RESET _u(0x00000000) +#define PIO_INSTR_MEM8_MSB _u(15) +#define PIO_INSTR_MEM8_LSB _u(0) #define PIO_INSTR_MEM8_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM9 // Description : Write-only access to instruction memory location 9 -#define PIO_INSTR_MEM9_OFFSET 0x0000006c -#define PIO_INSTR_MEM9_BITS 0x0000ffff -#define PIO_INSTR_MEM9_RESET 0x00000000 -#define PIO_INSTR_MEM9_MSB 15 -#define PIO_INSTR_MEM9_LSB 0 +#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) +#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM9_RESET _u(0x00000000) +#define PIO_INSTR_MEM9_MSB _u(15) +#define PIO_INSTR_MEM9_LSB _u(0) #define PIO_INSTR_MEM9_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM10 // Description : Write-only access to instruction memory location 10 -#define PIO_INSTR_MEM10_OFFSET 0x00000070 -#define PIO_INSTR_MEM10_BITS 0x0000ffff -#define PIO_INSTR_MEM10_RESET 0x00000000 -#define PIO_INSTR_MEM10_MSB 15 -#define PIO_INSTR_MEM10_LSB 0 +#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) +#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM10_RESET _u(0x00000000) +#define PIO_INSTR_MEM10_MSB _u(15) +#define PIO_INSTR_MEM10_LSB _u(0) #define PIO_INSTR_MEM10_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM11 // Description : Write-only access to instruction memory location 11 -#define PIO_INSTR_MEM11_OFFSET 0x00000074 -#define PIO_INSTR_MEM11_BITS 0x0000ffff -#define PIO_INSTR_MEM11_RESET 0x00000000 -#define PIO_INSTR_MEM11_MSB 15 -#define PIO_INSTR_MEM11_LSB 0 +#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) +#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM11_RESET _u(0x00000000) +#define PIO_INSTR_MEM11_MSB _u(15) +#define PIO_INSTR_MEM11_LSB _u(0) #define PIO_INSTR_MEM11_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM12 // Description : Write-only access to instruction memory location 12 -#define PIO_INSTR_MEM12_OFFSET 0x00000078 -#define PIO_INSTR_MEM12_BITS 0x0000ffff -#define PIO_INSTR_MEM12_RESET 0x00000000 -#define PIO_INSTR_MEM12_MSB 15 -#define PIO_INSTR_MEM12_LSB 0 +#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) +#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM12_RESET _u(0x00000000) +#define PIO_INSTR_MEM12_MSB _u(15) +#define PIO_INSTR_MEM12_LSB _u(0) #define PIO_INSTR_MEM12_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM13 // Description : Write-only access to instruction memory location 13 -#define PIO_INSTR_MEM13_OFFSET 0x0000007c -#define PIO_INSTR_MEM13_BITS 0x0000ffff -#define PIO_INSTR_MEM13_RESET 0x00000000 -#define PIO_INSTR_MEM13_MSB 15 -#define PIO_INSTR_MEM13_LSB 0 +#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) +#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM13_RESET _u(0x00000000) +#define PIO_INSTR_MEM13_MSB _u(15) +#define PIO_INSTR_MEM13_LSB _u(0) #define PIO_INSTR_MEM13_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM14 // Description : Write-only access to instruction memory location 14 -#define PIO_INSTR_MEM14_OFFSET 0x00000080 -#define PIO_INSTR_MEM14_BITS 0x0000ffff -#define PIO_INSTR_MEM14_RESET 0x00000000 -#define PIO_INSTR_MEM14_MSB 15 -#define PIO_INSTR_MEM14_LSB 0 +#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) +#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM14_RESET _u(0x00000000) +#define PIO_INSTR_MEM14_MSB _u(15) +#define PIO_INSTR_MEM14_LSB _u(0) #define PIO_INSTR_MEM14_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM15 // Description : Write-only access to instruction memory location 15 -#define PIO_INSTR_MEM15_OFFSET 0x00000084 -#define PIO_INSTR_MEM15_BITS 0x0000ffff -#define PIO_INSTR_MEM15_RESET 0x00000000 -#define PIO_INSTR_MEM15_MSB 15 -#define PIO_INSTR_MEM15_LSB 0 +#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) +#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM15_RESET _u(0x00000000) +#define PIO_INSTR_MEM15_MSB _u(15) +#define PIO_INSTR_MEM15_LSB _u(0) #define PIO_INSTR_MEM15_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM16 // Description : Write-only access to instruction memory location 16 -#define PIO_INSTR_MEM16_OFFSET 0x00000088 -#define PIO_INSTR_MEM16_BITS 0x0000ffff -#define PIO_INSTR_MEM16_RESET 0x00000000 -#define PIO_INSTR_MEM16_MSB 15 -#define PIO_INSTR_MEM16_LSB 0 +#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) +#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM16_RESET _u(0x00000000) +#define PIO_INSTR_MEM16_MSB _u(15) +#define PIO_INSTR_MEM16_LSB _u(0) #define PIO_INSTR_MEM16_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM17 // Description : Write-only access to instruction memory location 17 -#define PIO_INSTR_MEM17_OFFSET 0x0000008c -#define PIO_INSTR_MEM17_BITS 0x0000ffff -#define PIO_INSTR_MEM17_RESET 0x00000000 -#define PIO_INSTR_MEM17_MSB 15 -#define PIO_INSTR_MEM17_LSB 0 +#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) +#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM17_RESET _u(0x00000000) +#define PIO_INSTR_MEM17_MSB _u(15) +#define PIO_INSTR_MEM17_LSB _u(0) #define PIO_INSTR_MEM17_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM18 // Description : Write-only access to instruction memory location 18 -#define PIO_INSTR_MEM18_OFFSET 0x00000090 -#define PIO_INSTR_MEM18_BITS 0x0000ffff -#define PIO_INSTR_MEM18_RESET 0x00000000 -#define PIO_INSTR_MEM18_MSB 15 -#define PIO_INSTR_MEM18_LSB 0 +#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) +#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM18_RESET _u(0x00000000) +#define PIO_INSTR_MEM18_MSB _u(15) +#define PIO_INSTR_MEM18_LSB _u(0) #define PIO_INSTR_MEM18_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM19 // Description : Write-only access to instruction memory location 19 -#define PIO_INSTR_MEM19_OFFSET 0x00000094 -#define PIO_INSTR_MEM19_BITS 0x0000ffff -#define PIO_INSTR_MEM19_RESET 0x00000000 -#define PIO_INSTR_MEM19_MSB 15 -#define PIO_INSTR_MEM19_LSB 0 +#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) +#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM19_RESET _u(0x00000000) +#define PIO_INSTR_MEM19_MSB _u(15) +#define PIO_INSTR_MEM19_LSB _u(0) #define PIO_INSTR_MEM19_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM20 // Description : Write-only access to instruction memory location 20 -#define PIO_INSTR_MEM20_OFFSET 0x00000098 -#define PIO_INSTR_MEM20_BITS 0x0000ffff -#define PIO_INSTR_MEM20_RESET 0x00000000 -#define PIO_INSTR_MEM20_MSB 15 -#define PIO_INSTR_MEM20_LSB 0 +#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) +#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM20_RESET _u(0x00000000) +#define PIO_INSTR_MEM20_MSB _u(15) +#define PIO_INSTR_MEM20_LSB _u(0) #define PIO_INSTR_MEM20_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM21 // Description : Write-only access to instruction memory location 21 -#define PIO_INSTR_MEM21_OFFSET 0x0000009c -#define PIO_INSTR_MEM21_BITS 0x0000ffff -#define PIO_INSTR_MEM21_RESET 0x00000000 -#define PIO_INSTR_MEM21_MSB 15 -#define PIO_INSTR_MEM21_LSB 0 +#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) +#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM21_RESET _u(0x00000000) +#define PIO_INSTR_MEM21_MSB _u(15) +#define PIO_INSTR_MEM21_LSB _u(0) #define PIO_INSTR_MEM21_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM22 // Description : Write-only access to instruction memory location 22 -#define PIO_INSTR_MEM22_OFFSET 0x000000a0 -#define PIO_INSTR_MEM22_BITS 0x0000ffff -#define PIO_INSTR_MEM22_RESET 0x00000000 -#define PIO_INSTR_MEM22_MSB 15 -#define PIO_INSTR_MEM22_LSB 0 +#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) +#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM22_RESET _u(0x00000000) +#define PIO_INSTR_MEM22_MSB _u(15) +#define PIO_INSTR_MEM22_LSB _u(0) #define PIO_INSTR_MEM22_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM23 // Description : Write-only access to instruction memory location 23 -#define PIO_INSTR_MEM23_OFFSET 0x000000a4 -#define PIO_INSTR_MEM23_BITS 0x0000ffff -#define PIO_INSTR_MEM23_RESET 0x00000000 -#define PIO_INSTR_MEM23_MSB 15 -#define PIO_INSTR_MEM23_LSB 0 +#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) +#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM23_RESET _u(0x00000000) +#define PIO_INSTR_MEM23_MSB _u(15) +#define PIO_INSTR_MEM23_LSB _u(0) #define PIO_INSTR_MEM23_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM24 // Description : Write-only access to instruction memory location 24 -#define PIO_INSTR_MEM24_OFFSET 0x000000a8 -#define PIO_INSTR_MEM24_BITS 0x0000ffff -#define PIO_INSTR_MEM24_RESET 0x00000000 -#define PIO_INSTR_MEM24_MSB 15 -#define PIO_INSTR_MEM24_LSB 0 +#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) +#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM24_RESET _u(0x00000000) +#define PIO_INSTR_MEM24_MSB _u(15) +#define PIO_INSTR_MEM24_LSB _u(0) #define PIO_INSTR_MEM24_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM25 // Description : Write-only access to instruction memory location 25 -#define PIO_INSTR_MEM25_OFFSET 0x000000ac -#define PIO_INSTR_MEM25_BITS 0x0000ffff -#define PIO_INSTR_MEM25_RESET 0x00000000 -#define PIO_INSTR_MEM25_MSB 15 -#define PIO_INSTR_MEM25_LSB 0 +#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) +#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM25_RESET _u(0x00000000) +#define PIO_INSTR_MEM25_MSB _u(15) +#define PIO_INSTR_MEM25_LSB _u(0) #define PIO_INSTR_MEM25_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM26 // Description : Write-only access to instruction memory location 26 -#define PIO_INSTR_MEM26_OFFSET 0x000000b0 -#define PIO_INSTR_MEM26_BITS 0x0000ffff -#define PIO_INSTR_MEM26_RESET 0x00000000 -#define PIO_INSTR_MEM26_MSB 15 -#define PIO_INSTR_MEM26_LSB 0 +#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) +#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM26_RESET _u(0x00000000) +#define PIO_INSTR_MEM26_MSB _u(15) +#define PIO_INSTR_MEM26_LSB _u(0) #define PIO_INSTR_MEM26_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM27 // Description : Write-only access to instruction memory location 27 -#define PIO_INSTR_MEM27_OFFSET 0x000000b4 -#define PIO_INSTR_MEM27_BITS 0x0000ffff -#define PIO_INSTR_MEM27_RESET 0x00000000 -#define PIO_INSTR_MEM27_MSB 15 -#define PIO_INSTR_MEM27_LSB 0 +#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) +#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM27_RESET _u(0x00000000) +#define PIO_INSTR_MEM27_MSB _u(15) +#define PIO_INSTR_MEM27_LSB _u(0) #define PIO_INSTR_MEM27_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM28 // Description : Write-only access to instruction memory location 28 -#define PIO_INSTR_MEM28_OFFSET 0x000000b8 -#define PIO_INSTR_MEM28_BITS 0x0000ffff -#define PIO_INSTR_MEM28_RESET 0x00000000 -#define PIO_INSTR_MEM28_MSB 15 -#define PIO_INSTR_MEM28_LSB 0 +#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) +#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM28_RESET _u(0x00000000) +#define PIO_INSTR_MEM28_MSB _u(15) +#define PIO_INSTR_MEM28_LSB _u(0) #define PIO_INSTR_MEM28_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM29 // Description : Write-only access to instruction memory location 29 -#define PIO_INSTR_MEM29_OFFSET 0x000000bc -#define PIO_INSTR_MEM29_BITS 0x0000ffff -#define PIO_INSTR_MEM29_RESET 0x00000000 -#define PIO_INSTR_MEM29_MSB 15 -#define PIO_INSTR_MEM29_LSB 0 +#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) +#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM29_RESET _u(0x00000000) +#define PIO_INSTR_MEM29_MSB _u(15) +#define PIO_INSTR_MEM29_LSB _u(0) #define PIO_INSTR_MEM29_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM30 // Description : Write-only access to instruction memory location 30 -#define PIO_INSTR_MEM30_OFFSET 0x000000c0 -#define PIO_INSTR_MEM30_BITS 0x0000ffff -#define PIO_INSTR_MEM30_RESET 0x00000000 -#define PIO_INSTR_MEM30_MSB 15 -#define PIO_INSTR_MEM30_LSB 0 +#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) +#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM30_RESET _u(0x00000000) +#define PIO_INSTR_MEM30_MSB _u(15) +#define PIO_INSTR_MEM30_LSB _u(0) #define PIO_INSTR_MEM30_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM31 // Description : Write-only access to instruction memory location 31 -#define PIO_INSTR_MEM31_OFFSET 0x000000c4 -#define PIO_INSTR_MEM31_BITS 0x0000ffff -#define PIO_INSTR_MEM31_RESET 0x00000000 -#define PIO_INSTR_MEM31_MSB 15 -#define PIO_INSTR_MEM31_LSB 0 +#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) +#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM31_RESET _u(0x00000000) +#define PIO_INSTR_MEM31_MSB _u(15) +#define PIO_INSTR_MEM31_LSB _u(0) #define PIO_INSTR_MEM31_ACCESS "WO" // ============================================================================= // Register : PIO_SM0_CLKDIV -// Description : Clock divider register for state machine 0 +// Description : Clock divisor register for state machine 0 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM0_CLKDIV_OFFSET 0x000000c8 -#define PIO_SM0_CLKDIV_BITS 0xffffff00 -#define PIO_SM0_CLKDIV_RESET 0x00010000 +#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) +#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM0_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM0_CLKDIV_INT_RESET 0x0001 -#define PIO_SM0_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM0_CLKDIV_INT_MSB 31 -#define PIO_SM0_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM0_CLKDIV_INT_MSB _u(31) +#define PIO_SM0_CLKDIV_INT_LSB _u(16) #define PIO_SM0_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM0_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM0_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM0_CLKDIV_FRAC_MSB 15 -#define PIO_SM0_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) #define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_EXECCTRL // Description : Execution/behavioural settings for state machine 0 -#define PIO_SM0_EXECCTRL_OFFSET 0x000000cc -#define PIO_SM0_EXECCTRL_BITS 0xffffff9f -#define PIO_SM0_EXECCTRL_RESET 0x0001f000 +#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) +#define PIO_SM0_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM0_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM0_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM0_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM0_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM0_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM0_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM0_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM0_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN @@ -742,18 +811,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_WRAP_TOP @@ -761,46 +830,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM0_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM0_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM0_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM0_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 0 -#define PIO_SM0_SHIFTCTRL_OFFSET 0x000000d0 -#define PIO_SM0_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM0_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) +#define PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -808,10 +877,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_FJOIN_TX @@ -820,222 +889,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_ADDR // Description : Current instruction address of state machine 0 -#define PIO_SM0_ADDR_OFFSET 0x000000d4 -#define PIO_SM0_ADDR_BITS 0x0000001f -#define PIO_SM0_ADDR_RESET 0x00000000 -#define PIO_SM0_ADDR_MSB 4 -#define PIO_SM0_ADDR_LSB 0 +#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) +#define PIO_SM0_ADDR_BITS _u(0x0000001f) +#define PIO_SM0_ADDR_RESET _u(0x00000000) +#define PIO_SM0_ADDR_MSB _u(4) +#define PIO_SM0_ADDR_LSB _u(0) #define PIO_SM0_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM0_INSTR -// Description : Instruction currently being executed by state machine 0 +// Description : Read to see the instruction currently addressed by state +// machine 0's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM0_INSTR_OFFSET 0x000000d8 -#define PIO_SM0_INSTR_BITS 0x0000ffff +#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) +#define PIO_SM0_INSTR_BITS _u(0x0000ffff) #define PIO_SM0_INSTR_RESET "-" -#define PIO_SM0_INSTR_MSB 15 -#define PIO_SM0_INSTR_LSB 0 +#define PIO_SM0_INSTR_MSB _u(15) +#define PIO_SM0_INSTR_LSB _u(0) #define PIO_SM0_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_PINCTRL // Description : State machine pin control -#define PIO_SM0_PINCTRL_OFFSET 0x000000dc -#define PIO_SM0_PINCTRL_BITS 0xffffffff -#define PIO_SM0_PINCTRL_RESET 0x14000000 +#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) +#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM0_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM0_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM0_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM0_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM0_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM0_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM0_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM0_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM0_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM0_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM0_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM0_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM0_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM0_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM0_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM0_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM0_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM0_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_CLKDIV -// Description : Clock divider register for state machine 1 +// Description : Clock divisor register for state machine 1 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM1_CLKDIV_OFFSET 0x000000e0 -#define PIO_SM1_CLKDIV_BITS 0xffffff00 -#define PIO_SM1_CLKDIV_RESET 0x00010000 +#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) +#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM1_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM1_CLKDIV_INT_RESET 0x0001 -#define PIO_SM1_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM1_CLKDIV_INT_MSB 31 -#define PIO_SM1_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM1_CLKDIV_INT_MSB _u(31) +#define PIO_SM1_CLKDIV_INT_LSB _u(16) #define PIO_SM1_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM1_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM1_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM1_CLKDIV_FRAC_MSB 15 -#define PIO_SM1_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) #define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_EXECCTRL // Description : Execution/behavioural settings for state machine 1 -#define PIO_SM1_EXECCTRL_OFFSET 0x000000e4 -#define PIO_SM1_EXECCTRL_BITS 0xffffff9f -#define PIO_SM1_EXECCTRL_RESET 0x0001f000 +#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) +#define PIO_SM1_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM1_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM1_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM1_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM1_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM1_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM1_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM1_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM1_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN @@ -1046,18 +1142,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_WRAP_TOP @@ -1065,46 +1161,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM1_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM1_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM1_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM1_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 1 -#define PIO_SM1_SHIFTCTRL_OFFSET 0x000000e8 -#define PIO_SM1_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM1_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) +#define PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1112,10 +1208,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_FJOIN_TX @@ -1124,222 +1220,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_ADDR // Description : Current instruction address of state machine 1 -#define PIO_SM1_ADDR_OFFSET 0x000000ec -#define PIO_SM1_ADDR_BITS 0x0000001f -#define PIO_SM1_ADDR_RESET 0x00000000 -#define PIO_SM1_ADDR_MSB 4 -#define PIO_SM1_ADDR_LSB 0 +#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) +#define PIO_SM1_ADDR_BITS _u(0x0000001f) +#define PIO_SM1_ADDR_RESET _u(0x00000000) +#define PIO_SM1_ADDR_MSB _u(4) +#define PIO_SM1_ADDR_LSB _u(0) #define PIO_SM1_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM1_INSTR -// Description : Instruction currently being executed by state machine 1 +// Description : Read to see the instruction currently addressed by state +// machine 1's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM1_INSTR_OFFSET 0x000000f0 -#define PIO_SM1_INSTR_BITS 0x0000ffff +#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) +#define PIO_SM1_INSTR_BITS _u(0x0000ffff) #define PIO_SM1_INSTR_RESET "-" -#define PIO_SM1_INSTR_MSB 15 -#define PIO_SM1_INSTR_LSB 0 +#define PIO_SM1_INSTR_MSB _u(15) +#define PIO_SM1_INSTR_LSB _u(0) #define PIO_SM1_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_PINCTRL // Description : State machine pin control -#define PIO_SM1_PINCTRL_OFFSET 0x000000f4 -#define PIO_SM1_PINCTRL_BITS 0xffffffff -#define PIO_SM1_PINCTRL_RESET 0x14000000 +#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) +#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM1_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM1_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM1_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM1_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM1_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM1_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM1_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM1_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM1_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM1_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM1_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM1_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM1_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM1_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM1_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM1_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM1_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM1_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_CLKDIV -// Description : Clock divider register for state machine 2 +// Description : Clock divisor register for state machine 2 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM2_CLKDIV_OFFSET 0x000000f8 -#define PIO_SM2_CLKDIV_BITS 0xffffff00 -#define PIO_SM2_CLKDIV_RESET 0x00010000 +#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) +#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM2_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM2_CLKDIV_INT_RESET 0x0001 -#define PIO_SM2_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM2_CLKDIV_INT_MSB 31 -#define PIO_SM2_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM2_CLKDIV_INT_MSB _u(31) +#define PIO_SM2_CLKDIV_INT_LSB _u(16) #define PIO_SM2_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM2_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM2_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM2_CLKDIV_FRAC_MSB 15 -#define PIO_SM2_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) #define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_EXECCTRL // Description : Execution/behavioural settings for state machine 2 -#define PIO_SM2_EXECCTRL_OFFSET 0x000000fc -#define PIO_SM2_EXECCTRL_BITS 0xffffff9f -#define PIO_SM2_EXECCTRL_RESET 0x0001f000 +#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) +#define PIO_SM2_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM2_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM2_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM2_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM2_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM2_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM2_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM2_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM2_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN @@ -1350,18 +1473,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_WRAP_TOP @@ -1369,46 +1492,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM2_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM2_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM2_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM2_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 2 -#define PIO_SM2_SHIFTCTRL_OFFSET 0x00000100 -#define PIO_SM2_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM2_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) +#define PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1416,10 +1539,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_FJOIN_TX @@ -1428,222 +1551,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_ADDR // Description : Current instruction address of state machine 2 -#define PIO_SM2_ADDR_OFFSET 0x00000104 -#define PIO_SM2_ADDR_BITS 0x0000001f -#define PIO_SM2_ADDR_RESET 0x00000000 -#define PIO_SM2_ADDR_MSB 4 -#define PIO_SM2_ADDR_LSB 0 +#define PIO_SM2_ADDR_OFFSET _u(0x00000104) +#define PIO_SM2_ADDR_BITS _u(0x0000001f) +#define PIO_SM2_ADDR_RESET _u(0x00000000) +#define PIO_SM2_ADDR_MSB _u(4) +#define PIO_SM2_ADDR_LSB _u(0) #define PIO_SM2_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM2_INSTR -// Description : Instruction currently being executed by state machine 2 +// Description : Read to see the instruction currently addressed by state +// machine 2's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM2_INSTR_OFFSET 0x00000108 -#define PIO_SM2_INSTR_BITS 0x0000ffff +#define PIO_SM2_INSTR_OFFSET _u(0x00000108) +#define PIO_SM2_INSTR_BITS _u(0x0000ffff) #define PIO_SM2_INSTR_RESET "-" -#define PIO_SM2_INSTR_MSB 15 -#define PIO_SM2_INSTR_LSB 0 +#define PIO_SM2_INSTR_MSB _u(15) +#define PIO_SM2_INSTR_LSB _u(0) #define PIO_SM2_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_PINCTRL // Description : State machine pin control -#define PIO_SM2_PINCTRL_OFFSET 0x0000010c -#define PIO_SM2_PINCTRL_BITS 0xffffffff -#define PIO_SM2_PINCTRL_RESET 0x14000000 +#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) +#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM2_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM2_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM2_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM2_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM2_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM2_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM2_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM2_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM2_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM2_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM2_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM2_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM2_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM2_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM2_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM2_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM2_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM2_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_CLKDIV -// Description : Clock divider register for state machine 3 +// Description : Clock divisor register for state machine 3 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM3_CLKDIV_OFFSET 0x00000110 -#define PIO_SM3_CLKDIV_BITS 0xffffff00 -#define PIO_SM3_CLKDIV_RESET 0x00010000 +#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) +#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM3_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM3_CLKDIV_INT_RESET 0x0001 -#define PIO_SM3_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM3_CLKDIV_INT_MSB 31 -#define PIO_SM3_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM3_CLKDIV_INT_MSB _u(31) +#define PIO_SM3_CLKDIV_INT_LSB _u(16) #define PIO_SM3_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM3_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM3_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM3_CLKDIV_FRAC_MSB 15 -#define PIO_SM3_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) #define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_EXECCTRL // Description : Execution/behavioural settings for state machine 3 -#define PIO_SM3_EXECCTRL_OFFSET 0x00000114 -#define PIO_SM3_EXECCTRL_BITS 0xffffff9f -#define PIO_SM3_EXECCTRL_RESET 0x0001f000 +#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) +#define PIO_SM3_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM3_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM3_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM3_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM3_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM3_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM3_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM3_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM3_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN @@ -1654,18 +1804,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_WRAP_TOP @@ -1673,46 +1823,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM3_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM3_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM3_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM3_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 3 -#define PIO_SM3_SHIFTCTRL_OFFSET 0x00000118 -#define PIO_SM3_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM3_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) +#define PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1720,10 +1870,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_FJOIN_TX @@ -1732,860 +1882,883 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_ADDR // Description : Current instruction address of state machine 3 -#define PIO_SM3_ADDR_OFFSET 0x0000011c -#define PIO_SM3_ADDR_BITS 0x0000001f -#define PIO_SM3_ADDR_RESET 0x00000000 -#define PIO_SM3_ADDR_MSB 4 -#define PIO_SM3_ADDR_LSB 0 +#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) +#define PIO_SM3_ADDR_BITS _u(0x0000001f) +#define PIO_SM3_ADDR_RESET _u(0x00000000) +#define PIO_SM3_ADDR_MSB _u(4) +#define PIO_SM3_ADDR_LSB _u(0) #define PIO_SM3_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM3_INSTR -// Description : Instruction currently being executed by state machine 3 +// Description : Read to see the instruction currently addressed by state +// machine 3's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM3_INSTR_OFFSET 0x00000120 -#define PIO_SM3_INSTR_BITS 0x0000ffff +#define PIO_SM3_INSTR_OFFSET _u(0x00000120) +#define PIO_SM3_INSTR_BITS _u(0x0000ffff) #define PIO_SM3_INSTR_RESET "-" -#define PIO_SM3_INSTR_MSB 15 -#define PIO_SM3_INSTR_LSB 0 +#define PIO_SM3_INSTR_MSB _u(15) +#define PIO_SM3_INSTR_LSB _u(0) #define PIO_SM3_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_PINCTRL // Description : State machine pin control -#define PIO_SM3_PINCTRL_OFFSET 0x00000124 -#define PIO_SM3_PINCTRL_BITS 0xffffffff -#define PIO_SM3_PINCTRL_RESET 0x14000000 +#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) +#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM3_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM3_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM3_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM3_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM3_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM3_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM3_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM3_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM3_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM3_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM3_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM3_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM3_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM3_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM3_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM3_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM3_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM3_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_INTR // Description : Raw Interrupts -#define PIO_INTR_OFFSET 0x00000128 -#define PIO_INTR_BITS 0x00000fff -#define PIO_INTR_RESET 0x00000000 +#define PIO_INTR_OFFSET _u(0x00000128) +#define PIO_INTR_BITS _u(0x00000fff) +#define PIO_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3 // Description : None -#define PIO_INTR_SM3_RESET 0x0 -#define PIO_INTR_SM3_BITS 0x00000800 -#define PIO_INTR_SM3_MSB 11 -#define PIO_INTR_SM3_LSB 11 +#define PIO_INTR_SM3_RESET _u(0x0) +#define PIO_INTR_SM3_BITS _u(0x00000800) +#define PIO_INTR_SM3_MSB _u(11) +#define PIO_INTR_SM3_LSB _u(11) #define PIO_INTR_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2 // Description : None -#define PIO_INTR_SM2_RESET 0x0 -#define PIO_INTR_SM2_BITS 0x00000400 -#define PIO_INTR_SM2_MSB 10 -#define PIO_INTR_SM2_LSB 10 +#define PIO_INTR_SM2_RESET _u(0x0) +#define PIO_INTR_SM2_BITS _u(0x00000400) +#define PIO_INTR_SM2_MSB _u(10) +#define PIO_INTR_SM2_LSB _u(10) #define PIO_INTR_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1 // Description : None -#define PIO_INTR_SM1_RESET 0x0 -#define PIO_INTR_SM1_BITS 0x00000200 -#define PIO_INTR_SM1_MSB 9 -#define PIO_INTR_SM1_LSB 9 +#define PIO_INTR_SM1_RESET _u(0x0) +#define PIO_INTR_SM1_BITS _u(0x00000200) +#define PIO_INTR_SM1_MSB _u(9) +#define PIO_INTR_SM1_LSB _u(9) #define PIO_INTR_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0 // Description : None -#define PIO_INTR_SM0_RESET 0x0 -#define PIO_INTR_SM0_BITS 0x00000100 -#define PIO_INTR_SM0_MSB 8 -#define PIO_INTR_SM0_LSB 8 +#define PIO_INTR_SM0_RESET _u(0x0) +#define PIO_INTR_SM0_BITS _u(0x00000100) +#define PIO_INTR_SM0_MSB _u(8) +#define PIO_INTR_SM0_LSB _u(8) #define PIO_INTR_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_TXNFULL // Description : None -#define PIO_INTR_SM3_TXNFULL_RESET 0x0 -#define PIO_INTR_SM3_TXNFULL_BITS 0x00000080 -#define PIO_INTR_SM3_TXNFULL_MSB 7 -#define PIO_INTR_SM3_TXNFULL_LSB 7 +#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_INTR_SM3_TXNFULL_MSB _u(7) +#define PIO_INTR_SM3_TXNFULL_LSB _u(7) #define PIO_INTR_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_TXNFULL // Description : None -#define PIO_INTR_SM2_TXNFULL_RESET 0x0 -#define PIO_INTR_SM2_TXNFULL_BITS 0x00000040 -#define PIO_INTR_SM2_TXNFULL_MSB 6 -#define PIO_INTR_SM2_TXNFULL_LSB 6 +#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_INTR_SM2_TXNFULL_MSB _u(6) +#define PIO_INTR_SM2_TXNFULL_LSB _u(6) #define PIO_INTR_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_TXNFULL // Description : None -#define PIO_INTR_SM1_TXNFULL_RESET 0x0 -#define PIO_INTR_SM1_TXNFULL_BITS 0x00000020 -#define PIO_INTR_SM1_TXNFULL_MSB 5 -#define PIO_INTR_SM1_TXNFULL_LSB 5 +#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_INTR_SM1_TXNFULL_MSB _u(5) +#define PIO_INTR_SM1_TXNFULL_LSB _u(5) #define PIO_INTR_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_TXNFULL // Description : None -#define PIO_INTR_SM0_TXNFULL_RESET 0x0 -#define PIO_INTR_SM0_TXNFULL_BITS 0x00000010 -#define PIO_INTR_SM0_TXNFULL_MSB 4 -#define PIO_INTR_SM0_TXNFULL_LSB 4 +#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_INTR_SM0_TXNFULL_MSB _u(4) +#define PIO_INTR_SM0_TXNFULL_LSB _u(4) #define PIO_INTR_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_RXNEMPTY // Description : None -#define PIO_INTR_SM3_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_INTR_SM3_RXNEMPTY_MSB 3 -#define PIO_INTR_SM3_RXNEMPTY_LSB 3 +#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_RXNEMPTY // Description : None -#define PIO_INTR_SM2_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_INTR_SM2_RXNEMPTY_MSB 2 -#define PIO_INTR_SM2_RXNEMPTY_LSB 2 +#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_RXNEMPTY // Description : None -#define PIO_INTR_SM1_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_INTR_SM1_RXNEMPTY_MSB 1 -#define PIO_INTR_SM1_RXNEMPTY_LSB 1 +#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_RXNEMPTY // Description : None -#define PIO_INTR_SM0_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_INTR_SM0_RXNEMPTY_MSB 0 -#define PIO_INTR_SM0_RXNEMPTY_LSB 0 +#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) #define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PIO_IRQ0_INTE // Description : Interrupt Enable for irq0 -#define PIO_IRQ0_INTE_OFFSET 0x0000012c -#define PIO_IRQ0_INTE_BITS 0x00000fff -#define PIO_IRQ0_INTE_RESET 0x00000000 +#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c) +#define PIO_IRQ0_INTE_BITS _u(0x00000fff) +#define PIO_IRQ0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3 // Description : None -#define PIO_IRQ0_INTE_SM3_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTE_SM3_MSB 11 -#define PIO_IRQ0_INTE_SM3_LSB 11 +#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTE_SM3_MSB _u(11) +#define PIO_IRQ0_INTE_SM3_LSB _u(11) #define PIO_IRQ0_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2 // Description : None -#define PIO_IRQ0_INTE_SM2_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTE_SM2_MSB 10 -#define PIO_IRQ0_INTE_SM2_LSB 10 +#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTE_SM2_MSB _u(10) +#define PIO_IRQ0_INTE_SM2_LSB _u(10) #define PIO_IRQ0_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1 // Description : None -#define PIO_IRQ0_INTE_SM1_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTE_SM1_MSB 9 -#define PIO_IRQ0_INTE_SM1_LSB 9 +#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTE_SM1_MSB _u(9) +#define PIO_IRQ0_INTE_SM1_LSB _u(9) #define PIO_IRQ0_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0 // Description : None -#define PIO_IRQ0_INTE_SM0_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTE_SM0_MSB 8 -#define PIO_IRQ0_INTE_SM0_LSB 8 +#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTE_SM0_MSB _u(8) +#define PIO_IRQ0_INTE_SM0_LSB _u(8) #define PIO_IRQ0_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ0_INTF // Description : Interrupt Force for irq0 -#define PIO_IRQ0_INTF_OFFSET 0x00000130 -#define PIO_IRQ0_INTF_BITS 0x00000fff -#define PIO_IRQ0_INTF_RESET 0x00000000 +#define PIO_IRQ0_INTF_OFFSET _u(0x00000130) +#define PIO_IRQ0_INTF_BITS _u(0x00000fff) +#define PIO_IRQ0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3 // Description : None -#define PIO_IRQ0_INTF_SM3_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTF_SM3_MSB 11 -#define PIO_IRQ0_INTF_SM3_LSB 11 +#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTF_SM3_MSB _u(11) +#define PIO_IRQ0_INTF_SM3_LSB _u(11) #define PIO_IRQ0_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2 // Description : None -#define PIO_IRQ0_INTF_SM2_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTF_SM2_MSB 10 -#define PIO_IRQ0_INTF_SM2_LSB 10 +#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTF_SM2_MSB _u(10) +#define PIO_IRQ0_INTF_SM2_LSB _u(10) #define PIO_IRQ0_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1 // Description : None -#define PIO_IRQ0_INTF_SM1_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTF_SM1_MSB 9 -#define PIO_IRQ0_INTF_SM1_LSB 9 +#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTF_SM1_MSB _u(9) +#define PIO_IRQ0_INTF_SM1_LSB _u(9) #define PIO_IRQ0_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0 // Description : None -#define PIO_IRQ0_INTF_SM0_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTF_SM0_MSB 8 -#define PIO_IRQ0_INTF_SM0_LSB 8 +#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTF_SM0_MSB _u(8) +#define PIO_IRQ0_INTF_SM0_LSB _u(8) #define PIO_IRQ0_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ0_INTS // Description : Interrupt status after masking & forcing for irq0 -#define PIO_IRQ0_INTS_OFFSET 0x00000134 -#define PIO_IRQ0_INTS_BITS 0x00000fff -#define PIO_IRQ0_INTS_RESET 0x00000000 +#define PIO_IRQ0_INTS_OFFSET _u(0x00000134) +#define PIO_IRQ0_INTS_BITS _u(0x00000fff) +#define PIO_IRQ0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3 // Description : None -#define PIO_IRQ0_INTS_SM3_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTS_SM3_MSB 11 -#define PIO_IRQ0_INTS_SM3_LSB 11 +#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTS_SM3_MSB _u(11) +#define PIO_IRQ0_INTS_SM3_LSB _u(11) #define PIO_IRQ0_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2 // Description : None -#define PIO_IRQ0_INTS_SM2_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTS_SM2_MSB 10 -#define PIO_IRQ0_INTS_SM2_LSB 10 +#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTS_SM2_MSB _u(10) +#define PIO_IRQ0_INTS_SM2_LSB _u(10) #define PIO_IRQ0_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1 // Description : None -#define PIO_IRQ0_INTS_SM1_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTS_SM1_MSB 9 -#define PIO_IRQ0_INTS_SM1_LSB 9 +#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTS_SM1_MSB _u(9) +#define PIO_IRQ0_INTS_SM1_LSB _u(9) #define PIO_IRQ0_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0 // Description : None -#define PIO_IRQ0_INTS_SM0_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTS_SM0_MSB 8 -#define PIO_IRQ0_INTS_SM0_LSB 8 +#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTS_SM0_MSB _u(8) +#define PIO_IRQ0_INTS_SM0_LSB _u(8) #define PIO_IRQ0_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PIO_IRQ1_INTE // Description : Interrupt Enable for irq1 -#define PIO_IRQ1_INTE_OFFSET 0x00000138 -#define PIO_IRQ1_INTE_BITS 0x00000fff -#define PIO_IRQ1_INTE_RESET 0x00000000 +#define PIO_IRQ1_INTE_OFFSET _u(0x00000138) +#define PIO_IRQ1_INTE_BITS _u(0x00000fff) +#define PIO_IRQ1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3 // Description : None -#define PIO_IRQ1_INTE_SM3_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTE_SM3_MSB 11 -#define PIO_IRQ1_INTE_SM3_LSB 11 +#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTE_SM3_MSB _u(11) +#define PIO_IRQ1_INTE_SM3_LSB _u(11) #define PIO_IRQ1_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2 // Description : None -#define PIO_IRQ1_INTE_SM2_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTE_SM2_MSB 10 -#define PIO_IRQ1_INTE_SM2_LSB 10 +#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTE_SM2_MSB _u(10) +#define PIO_IRQ1_INTE_SM2_LSB _u(10) #define PIO_IRQ1_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1 // Description : None -#define PIO_IRQ1_INTE_SM1_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTE_SM1_MSB 9 -#define PIO_IRQ1_INTE_SM1_LSB 9 +#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTE_SM1_MSB _u(9) +#define PIO_IRQ1_INTE_SM1_LSB _u(9) #define PIO_IRQ1_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0 // Description : None -#define PIO_IRQ1_INTE_SM0_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTE_SM0_MSB 8 -#define PIO_IRQ1_INTE_SM0_LSB 8 +#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTE_SM0_MSB _u(8) +#define PIO_IRQ1_INTE_SM0_LSB _u(8) #define PIO_IRQ1_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ1_INTF // Description : Interrupt Force for irq1 -#define PIO_IRQ1_INTF_OFFSET 0x0000013c -#define PIO_IRQ1_INTF_BITS 0x00000fff -#define PIO_IRQ1_INTF_RESET 0x00000000 +#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c) +#define PIO_IRQ1_INTF_BITS _u(0x00000fff) +#define PIO_IRQ1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3 // Description : None -#define PIO_IRQ1_INTF_SM3_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTF_SM3_MSB 11 -#define PIO_IRQ1_INTF_SM3_LSB 11 +#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTF_SM3_MSB _u(11) +#define PIO_IRQ1_INTF_SM3_LSB _u(11) #define PIO_IRQ1_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2 // Description : None -#define PIO_IRQ1_INTF_SM2_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTF_SM2_MSB 10 -#define PIO_IRQ1_INTF_SM2_LSB 10 +#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTF_SM2_MSB _u(10) +#define PIO_IRQ1_INTF_SM2_LSB _u(10) #define PIO_IRQ1_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1 // Description : None -#define PIO_IRQ1_INTF_SM1_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTF_SM1_MSB 9 -#define PIO_IRQ1_INTF_SM1_LSB 9 +#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTF_SM1_MSB _u(9) +#define PIO_IRQ1_INTF_SM1_LSB _u(9) #define PIO_IRQ1_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0 // Description : None -#define PIO_IRQ1_INTF_SM0_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTF_SM0_MSB 8 -#define PIO_IRQ1_INTF_SM0_LSB 8 +#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTF_SM0_MSB _u(8) +#define PIO_IRQ1_INTF_SM0_LSB _u(8) #define PIO_IRQ1_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ1_INTS // Description : Interrupt status after masking & forcing for irq1 -#define PIO_IRQ1_INTS_OFFSET 0x00000140 -#define PIO_IRQ1_INTS_BITS 0x00000fff -#define PIO_IRQ1_INTS_RESET 0x00000000 +#define PIO_IRQ1_INTS_OFFSET _u(0x00000140) +#define PIO_IRQ1_INTS_BITS _u(0x00000fff) +#define PIO_IRQ1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3 // Description : None -#define PIO_IRQ1_INTS_SM3_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTS_SM3_MSB 11 -#define PIO_IRQ1_INTS_SM3_LSB 11 +#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTS_SM3_MSB _u(11) +#define PIO_IRQ1_INTS_SM3_LSB _u(11) #define PIO_IRQ1_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2 // Description : None -#define PIO_IRQ1_INTS_SM2_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTS_SM2_MSB 10 -#define PIO_IRQ1_INTS_SM2_LSB 10 +#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTS_SM2_MSB _u(10) +#define PIO_IRQ1_INTS_SM2_LSB _u(10) #define PIO_IRQ1_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1 // Description : None -#define PIO_IRQ1_INTS_SM1_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTS_SM1_MSB 9 -#define PIO_IRQ1_INTS_SM1_LSB 9 +#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTS_SM1_MSB _u(9) +#define PIO_IRQ1_INTS_SM1_LSB _u(9) #define PIO_IRQ1_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0 // Description : None -#define PIO_IRQ1_INTS_SM0_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTS_SM0_MSB 8 -#define PIO_IRQ1_INTS_SM0_LSB 8 +#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTS_SM0_MSB _u(8) +#define PIO_IRQ1_INTS_SM0_LSB _u(8) #define PIO_IRQ1_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PIO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h index 6a21d5603fc..a0f5ad0efcd 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h @@ -18,16 +18,16 @@ // Reference clock frequency min=5MHz, max=800MHz // Feedback divider min=16, max=320 // VCO frequency min=400MHz, max=1600MHz -#define PLL_CS_OFFSET 0x00000000 -#define PLL_CS_BITS 0x8000013f -#define PLL_CS_RESET 0x00000001 +#define PLL_CS_OFFSET _u(0x00000000) +#define PLL_CS_BITS _u(0x8000013f) +#define PLL_CS_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : PLL_CS_LOCK // Description : PLL is locked -#define PLL_CS_LOCK_RESET 0x0 -#define PLL_CS_LOCK_BITS 0x80000000 -#define PLL_CS_LOCK_MSB 31 -#define PLL_CS_LOCK_LSB 31 +#define PLL_CS_LOCK_RESET _u(0x0) +#define PLL_CS_LOCK_BITS _u(0x80000000) +#define PLL_CS_LOCK_MSB _u(31) +#define PLL_CS_LOCK_LSB _u(31) #define PLL_CS_LOCK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PLL_CS_BYPASS @@ -35,10 +35,10 @@ // VCO. The VCO continues to run so the user can switch between // the reference clock and the divided VCO but the output will // glitch when doing so. -#define PLL_CS_BYPASS_RESET 0x0 -#define PLL_CS_BYPASS_BITS 0x00000100 -#define PLL_CS_BYPASS_MSB 8 -#define PLL_CS_BYPASS_LSB 8 +#define PLL_CS_BYPASS_RESET _u(0x0) +#define PLL_CS_BYPASS_BITS _u(0x00000100) +#define PLL_CS_BYPASS_MSB _u(8) +#define PLL_CS_BYPASS_LSB _u(8) #define PLL_CS_BYPASS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_CS_REFDIV @@ -46,65 +46,65 @@ // Behaviour is undefined for div=0. // PLL output will be unpredictable during refdiv changes, wait // for lock=1 before using it. -#define PLL_CS_REFDIV_RESET 0x01 -#define PLL_CS_REFDIV_BITS 0x0000003f -#define PLL_CS_REFDIV_MSB 5 -#define PLL_CS_REFDIV_LSB 0 +#define PLL_CS_REFDIV_RESET _u(0x01) +#define PLL_CS_REFDIV_BITS _u(0x0000003f) +#define PLL_CS_REFDIV_MSB _u(5) +#define PLL_CS_REFDIV_LSB _u(0) #define PLL_CS_REFDIV_ACCESS "RW" // ============================================================================= // Register : PLL_PWR // Description : Controls the PLL power modes. -#define PLL_PWR_OFFSET 0x00000004 -#define PLL_PWR_BITS 0x0000002d -#define PLL_PWR_RESET 0x0000002d +#define PLL_PWR_OFFSET _u(0x00000004) +#define PLL_PWR_BITS _u(0x0000002d) +#define PLL_PWR_RESET _u(0x0000002d) // ----------------------------------------------------------------------------- // Field : PLL_PWR_VCOPD // Description : PLL VCO powerdown // To save power set high when PLL output not required or // bypass=1. -#define PLL_PWR_VCOPD_RESET 0x1 -#define PLL_PWR_VCOPD_BITS 0x00000020 -#define PLL_PWR_VCOPD_MSB 5 -#define PLL_PWR_VCOPD_LSB 5 +#define PLL_PWR_VCOPD_RESET _u(0x1) +#define PLL_PWR_VCOPD_BITS _u(0x00000020) +#define PLL_PWR_VCOPD_MSB _u(5) +#define PLL_PWR_VCOPD_LSB _u(5) #define PLL_PWR_VCOPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_POSTDIVPD // Description : PLL post divider powerdown // To save power set high when PLL output not required or // bypass=1. -#define PLL_PWR_POSTDIVPD_RESET 0x1 -#define PLL_PWR_POSTDIVPD_BITS 0x00000008 -#define PLL_PWR_POSTDIVPD_MSB 3 -#define PLL_PWR_POSTDIVPD_LSB 3 +#define PLL_PWR_POSTDIVPD_RESET _u(0x1) +#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) +#define PLL_PWR_POSTDIVPD_MSB _u(3) +#define PLL_PWR_POSTDIVPD_LSB _u(3) #define PLL_PWR_POSTDIVPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_DSMPD // Description : PLL DSM powerdown // Nothing is achieved by setting this low. -#define PLL_PWR_DSMPD_RESET 0x1 -#define PLL_PWR_DSMPD_BITS 0x00000004 -#define PLL_PWR_DSMPD_MSB 2 -#define PLL_PWR_DSMPD_LSB 2 +#define PLL_PWR_DSMPD_RESET _u(0x1) +#define PLL_PWR_DSMPD_BITS _u(0x00000004) +#define PLL_PWR_DSMPD_MSB _u(2) +#define PLL_PWR_DSMPD_LSB _u(2) #define PLL_PWR_DSMPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_PD // Description : PLL powerdown // To save power set high when PLL output not required. -#define PLL_PWR_PD_RESET 0x1 -#define PLL_PWR_PD_BITS 0x00000001 -#define PLL_PWR_PD_MSB 0 -#define PLL_PWR_PD_LSB 0 +#define PLL_PWR_PD_RESET _u(0x1) +#define PLL_PWR_PD_BITS _u(0x00000001) +#define PLL_PWR_PD_MSB _u(0) +#define PLL_PWR_PD_LSB _u(0) #define PLL_PWR_PD_ACCESS "RW" // ============================================================================= // Register : PLL_FBDIV_INT // Description : Feedback divisor // (note: this PLL does not support fractional division) // see ctrl reg description for constraints -#define PLL_FBDIV_INT_OFFSET 0x00000008 -#define PLL_FBDIV_INT_BITS 0x00000fff -#define PLL_FBDIV_INT_RESET 0x00000000 -#define PLL_FBDIV_INT_MSB 11 -#define PLL_FBDIV_INT_LSB 0 +#define PLL_FBDIV_INT_OFFSET _u(0x00000008) +#define PLL_FBDIV_INT_BITS _u(0x00000fff) +#define PLL_FBDIV_INT_RESET _u(0x00000000) +#define PLL_FBDIV_INT_MSB _u(11) +#define PLL_FBDIV_INT_LSB _u(0) #define PLL_FBDIV_INT_ACCESS "RW" // ============================================================================= // Register : PLL_PRIM @@ -112,24 +112,24 @@ // (note: this PLL does not have a secondary output) // the primary output is driven from VCO divided by // postdiv1*postdiv2 -#define PLL_PRIM_OFFSET 0x0000000c -#define PLL_PRIM_BITS 0x00077000 -#define PLL_PRIM_RESET 0x00077000 +#define PLL_PRIM_OFFSET _u(0x0000000c) +#define PLL_PRIM_BITS _u(0x00077000) +#define PLL_PRIM_RESET _u(0x00077000) // ----------------------------------------------------------------------------- // Field : PLL_PRIM_POSTDIV1 // Description : divide by 1-7 -#define PLL_PRIM_POSTDIV1_RESET 0x7 -#define PLL_PRIM_POSTDIV1_BITS 0x00070000 -#define PLL_PRIM_POSTDIV1_MSB 18 -#define PLL_PRIM_POSTDIV1_LSB 16 +#define PLL_PRIM_POSTDIV1_RESET _u(0x7) +#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) +#define PLL_PRIM_POSTDIV1_MSB _u(18) +#define PLL_PRIM_POSTDIV1_LSB _u(16) #define PLL_PRIM_POSTDIV1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PRIM_POSTDIV2 // Description : divide by 1-7 -#define PLL_PRIM_POSTDIV2_RESET 0x7 -#define PLL_PRIM_POSTDIV2_BITS 0x00007000 -#define PLL_PRIM_POSTDIV2_MSB 14 -#define PLL_PRIM_POSTDIV2_LSB 12 +#define PLL_PRIM_POSTDIV2_RESET _u(0x7) +#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) +#define PLL_PRIM_POSTDIV2_MSB _u(14) +#define PLL_PRIM_POSTDIV2_LSB _u(12) #define PLL_PRIM_POSTDIV2_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PLL_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h index dacf36394ed..8810ae8bbb1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h @@ -14,571 +14,571 @@ // ============================================================================= // Register : PSM_FRCE_ON // Description : Force block out of reset (i.e. power it on) -#define PSM_FRCE_ON_OFFSET 0x00000000 -#define PSM_FRCE_ON_BITS 0x0001ffff -#define PSM_FRCE_ON_RESET 0x00000000 +#define PSM_FRCE_ON_OFFSET _u(0x00000000) +#define PSM_FRCE_ON_BITS _u(0x0001ffff) +#define PSM_FRCE_ON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC1 // Description : None -#define PSM_FRCE_ON_PROC1_RESET 0x0 -#define PSM_FRCE_ON_PROC1_BITS 0x00010000 -#define PSM_FRCE_ON_PROC1_MSB 16 -#define PSM_FRCE_ON_PROC1_LSB 16 +#define PSM_FRCE_ON_PROC1_RESET _u(0x0) +#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) +#define PSM_FRCE_ON_PROC1_MSB _u(16) +#define PSM_FRCE_ON_PROC1_LSB _u(16) #define PSM_FRCE_ON_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC0 // Description : None -#define PSM_FRCE_ON_PROC0_RESET 0x0 -#define PSM_FRCE_ON_PROC0_BITS 0x00008000 -#define PSM_FRCE_ON_PROC0_MSB 15 -#define PSM_FRCE_ON_PROC0_LSB 15 +#define PSM_FRCE_ON_PROC0_RESET _u(0x0) +#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) +#define PSM_FRCE_ON_PROC0_MSB _u(15) +#define PSM_FRCE_ON_PROC0_LSB _u(15) #define PSM_FRCE_ON_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SIO // Description : None -#define PSM_FRCE_ON_SIO_RESET 0x0 -#define PSM_FRCE_ON_SIO_BITS 0x00004000 -#define PSM_FRCE_ON_SIO_MSB 14 -#define PSM_FRCE_ON_SIO_LSB 14 +#define PSM_FRCE_ON_SIO_RESET _u(0x0) +#define PSM_FRCE_ON_SIO_BITS _u(0x00004000) +#define PSM_FRCE_ON_SIO_MSB _u(14) +#define PSM_FRCE_ON_SIO_LSB _u(14) #define PSM_FRCE_ON_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET // Description : None -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XIP // Description : None -#define PSM_FRCE_ON_XIP_RESET 0x0 -#define PSM_FRCE_ON_XIP_BITS 0x00001000 -#define PSM_FRCE_ON_XIP_MSB 12 -#define PSM_FRCE_ON_XIP_LSB 12 +#define PSM_FRCE_ON_XIP_RESET _u(0x0) +#define PSM_FRCE_ON_XIP_BITS _u(0x00001000) +#define PSM_FRCE_ON_XIP_MSB _u(12) +#define PSM_FRCE_ON_XIP_LSB _u(12) #define PSM_FRCE_ON_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM5 // Description : None -#define PSM_FRCE_ON_SRAM5_RESET 0x0 -#define PSM_FRCE_ON_SRAM5_BITS 0x00000800 -#define PSM_FRCE_ON_SRAM5_MSB 11 -#define PSM_FRCE_ON_SRAM5_LSB 11 +#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) +#define PSM_FRCE_ON_SRAM5_MSB _u(11) +#define PSM_FRCE_ON_SRAM5_LSB _u(11) #define PSM_FRCE_ON_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM4 // Description : None -#define PSM_FRCE_ON_SRAM4_RESET 0x0 -#define PSM_FRCE_ON_SRAM4_BITS 0x00000400 -#define PSM_FRCE_ON_SRAM4_MSB 10 -#define PSM_FRCE_ON_SRAM4_LSB 10 +#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) +#define PSM_FRCE_ON_SRAM4_MSB _u(10) +#define PSM_FRCE_ON_SRAM4_LSB _u(10) #define PSM_FRCE_ON_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM3 // Description : None -#define PSM_FRCE_ON_SRAM3_RESET 0x0 -#define PSM_FRCE_ON_SRAM3_BITS 0x00000200 -#define PSM_FRCE_ON_SRAM3_MSB 9 -#define PSM_FRCE_ON_SRAM3_LSB 9 +#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) +#define PSM_FRCE_ON_SRAM3_MSB _u(9) +#define PSM_FRCE_ON_SRAM3_LSB _u(9) #define PSM_FRCE_ON_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM2 // Description : None -#define PSM_FRCE_ON_SRAM2_RESET 0x0 -#define PSM_FRCE_ON_SRAM2_BITS 0x00000100 -#define PSM_FRCE_ON_SRAM2_MSB 8 -#define PSM_FRCE_ON_SRAM2_LSB 8 +#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) +#define PSM_FRCE_ON_SRAM2_MSB _u(8) +#define PSM_FRCE_ON_SRAM2_LSB _u(8) #define PSM_FRCE_ON_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM1 // Description : None -#define PSM_FRCE_ON_SRAM1_RESET 0x0 -#define PSM_FRCE_ON_SRAM1_BITS 0x00000080 -#define PSM_FRCE_ON_SRAM1_MSB 7 -#define PSM_FRCE_ON_SRAM1_LSB 7 +#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) +#define PSM_FRCE_ON_SRAM1_MSB _u(7) +#define PSM_FRCE_ON_SRAM1_LSB _u(7) #define PSM_FRCE_ON_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM0 // Description : None -#define PSM_FRCE_ON_SRAM0_RESET 0x0 -#define PSM_FRCE_ON_SRAM0_BITS 0x00000040 -#define PSM_FRCE_ON_SRAM0_MSB 6 -#define PSM_FRCE_ON_SRAM0_LSB 6 +#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) +#define PSM_FRCE_ON_SRAM0_MSB _u(6) +#define PSM_FRCE_ON_SRAM0_LSB _u(6) #define PSM_FRCE_ON_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROM // Description : None -#define PSM_FRCE_ON_ROM_RESET 0x0 -#define PSM_FRCE_ON_ROM_BITS 0x00000020 -#define PSM_FRCE_ON_ROM_MSB 5 -#define PSM_FRCE_ON_ROM_LSB 5 +#define PSM_FRCE_ON_ROM_RESET _u(0x0) +#define PSM_FRCE_ON_ROM_BITS _u(0x00000020) +#define PSM_FRCE_ON_ROM_MSB _u(5) +#define PSM_FRCE_ON_ROM_LSB _u(5) #define PSM_FRCE_ON_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_BUSFABRIC // Description : None -#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0 -#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010 -#define PSM_FRCE_ON_BUSFABRIC_MSB 4 -#define PSM_FRCE_ON_BUSFABRIC_LSB 4 +#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) +#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) +#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4) #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_RESETS // Description : None -#define PSM_FRCE_ON_RESETS_RESET 0x0 -#define PSM_FRCE_ON_RESETS_BITS 0x00000008 -#define PSM_FRCE_ON_RESETS_MSB 3 -#define PSM_FRCE_ON_RESETS_LSB 3 +#define PSM_FRCE_ON_RESETS_RESET _u(0x0) +#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) +#define PSM_FRCE_ON_RESETS_MSB _u(3) +#define PSM_FRCE_ON_RESETS_LSB _u(3) #define PSM_FRCE_ON_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_CLOCKS // Description : None -#define PSM_FRCE_ON_CLOCKS_RESET 0x0 -#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004 -#define PSM_FRCE_ON_CLOCKS_MSB 2 -#define PSM_FRCE_ON_CLOCKS_LSB 2 +#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) +#define PSM_FRCE_ON_CLOCKS_MSB _u(2) +#define PSM_FRCE_ON_CLOCKS_LSB _u(2) #define PSM_FRCE_ON_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XOSC // Description : None -#define PSM_FRCE_ON_XOSC_RESET 0x0 -#define PSM_FRCE_ON_XOSC_BITS 0x00000002 -#define PSM_FRCE_ON_XOSC_MSB 1 -#define PSM_FRCE_ON_XOSC_LSB 1 +#define PSM_FRCE_ON_XOSC_RESET _u(0x0) +#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) +#define PSM_FRCE_ON_XOSC_MSB _u(1) +#define PSM_FRCE_ON_XOSC_LSB _u(1) #define PSM_FRCE_ON_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROSC // Description : None -#define PSM_FRCE_ON_ROSC_RESET 0x0 -#define PSM_FRCE_ON_ROSC_BITS 0x00000001 -#define PSM_FRCE_ON_ROSC_MSB 0 -#define PSM_FRCE_ON_ROSC_LSB 0 +#define PSM_FRCE_ON_ROSC_RESET _u(0x0) +#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) +#define PSM_FRCE_ON_ROSC_MSB _u(0) +#define PSM_FRCE_ON_ROSC_LSB _u(0) #define PSM_FRCE_ON_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_FRCE_OFF // Description : Force into reset (i.e. power it off) -#define PSM_FRCE_OFF_OFFSET 0x00000004 -#define PSM_FRCE_OFF_BITS 0x0001ffff -#define PSM_FRCE_OFF_RESET 0x00000000 +#define PSM_FRCE_OFF_OFFSET _u(0x00000004) +#define PSM_FRCE_OFF_BITS _u(0x0001ffff) +#define PSM_FRCE_OFF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC1 // Description : None -#define PSM_FRCE_OFF_PROC1_RESET 0x0 -#define PSM_FRCE_OFF_PROC1_BITS 0x00010000 -#define PSM_FRCE_OFF_PROC1_MSB 16 -#define PSM_FRCE_OFF_PROC1_LSB 16 +#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) +#define PSM_FRCE_OFF_PROC1_MSB _u(16) +#define PSM_FRCE_OFF_PROC1_LSB _u(16) #define PSM_FRCE_OFF_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC0 // Description : None -#define PSM_FRCE_OFF_PROC0_RESET 0x0 -#define PSM_FRCE_OFF_PROC0_BITS 0x00008000 -#define PSM_FRCE_OFF_PROC0_MSB 15 -#define PSM_FRCE_OFF_PROC0_LSB 15 +#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) +#define PSM_FRCE_OFF_PROC0_MSB _u(15) +#define PSM_FRCE_OFF_PROC0_LSB _u(15) #define PSM_FRCE_OFF_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SIO // Description : None -#define PSM_FRCE_OFF_SIO_RESET 0x0 -#define PSM_FRCE_OFF_SIO_BITS 0x00004000 -#define PSM_FRCE_OFF_SIO_MSB 14 -#define PSM_FRCE_OFF_SIO_LSB 14 +#define PSM_FRCE_OFF_SIO_RESET _u(0x0) +#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) +#define PSM_FRCE_OFF_SIO_MSB _u(14) +#define PSM_FRCE_OFF_SIO_LSB _u(14) #define PSM_FRCE_OFF_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET // Description : None -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XIP // Description : None -#define PSM_FRCE_OFF_XIP_RESET 0x0 -#define PSM_FRCE_OFF_XIP_BITS 0x00001000 -#define PSM_FRCE_OFF_XIP_MSB 12 -#define PSM_FRCE_OFF_XIP_LSB 12 +#define PSM_FRCE_OFF_XIP_RESET _u(0x0) +#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) +#define PSM_FRCE_OFF_XIP_MSB _u(12) +#define PSM_FRCE_OFF_XIP_LSB _u(12) #define PSM_FRCE_OFF_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM5 // Description : None -#define PSM_FRCE_OFF_SRAM5_RESET 0x0 -#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800 -#define PSM_FRCE_OFF_SRAM5_MSB 11 -#define PSM_FRCE_OFF_SRAM5_LSB 11 +#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) +#define PSM_FRCE_OFF_SRAM5_MSB _u(11) +#define PSM_FRCE_OFF_SRAM5_LSB _u(11) #define PSM_FRCE_OFF_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM4 // Description : None -#define PSM_FRCE_OFF_SRAM4_RESET 0x0 -#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400 -#define PSM_FRCE_OFF_SRAM4_MSB 10 -#define PSM_FRCE_OFF_SRAM4_LSB 10 +#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) +#define PSM_FRCE_OFF_SRAM4_MSB _u(10) +#define PSM_FRCE_OFF_SRAM4_LSB _u(10) #define PSM_FRCE_OFF_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM3 // Description : None -#define PSM_FRCE_OFF_SRAM3_RESET 0x0 -#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200 -#define PSM_FRCE_OFF_SRAM3_MSB 9 -#define PSM_FRCE_OFF_SRAM3_LSB 9 +#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) +#define PSM_FRCE_OFF_SRAM3_MSB _u(9) +#define PSM_FRCE_OFF_SRAM3_LSB _u(9) #define PSM_FRCE_OFF_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM2 // Description : None -#define PSM_FRCE_OFF_SRAM2_RESET 0x0 -#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100 -#define PSM_FRCE_OFF_SRAM2_MSB 8 -#define PSM_FRCE_OFF_SRAM2_LSB 8 +#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) +#define PSM_FRCE_OFF_SRAM2_MSB _u(8) +#define PSM_FRCE_OFF_SRAM2_LSB _u(8) #define PSM_FRCE_OFF_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM1 // Description : None -#define PSM_FRCE_OFF_SRAM1_RESET 0x0 -#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080 -#define PSM_FRCE_OFF_SRAM1_MSB 7 -#define PSM_FRCE_OFF_SRAM1_LSB 7 +#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) +#define PSM_FRCE_OFF_SRAM1_MSB _u(7) +#define PSM_FRCE_OFF_SRAM1_LSB _u(7) #define PSM_FRCE_OFF_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM0 // Description : None -#define PSM_FRCE_OFF_SRAM0_RESET 0x0 -#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040 -#define PSM_FRCE_OFF_SRAM0_MSB 6 -#define PSM_FRCE_OFF_SRAM0_LSB 6 +#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) +#define PSM_FRCE_OFF_SRAM0_MSB _u(6) +#define PSM_FRCE_OFF_SRAM0_LSB _u(6) #define PSM_FRCE_OFF_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROM // Description : None -#define PSM_FRCE_OFF_ROM_RESET 0x0 -#define PSM_FRCE_OFF_ROM_BITS 0x00000020 -#define PSM_FRCE_OFF_ROM_MSB 5 -#define PSM_FRCE_OFF_ROM_LSB 5 +#define PSM_FRCE_OFF_ROM_RESET _u(0x0) +#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) +#define PSM_FRCE_OFF_ROM_MSB _u(5) +#define PSM_FRCE_OFF_ROM_LSB _u(5) #define PSM_FRCE_OFF_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_BUSFABRIC // Description : None -#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0 -#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010 -#define PSM_FRCE_OFF_BUSFABRIC_MSB 4 -#define PSM_FRCE_OFF_BUSFABRIC_LSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) +#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) +#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4) #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_RESETS // Description : None -#define PSM_FRCE_OFF_RESETS_RESET 0x0 -#define PSM_FRCE_OFF_RESETS_BITS 0x00000008 -#define PSM_FRCE_OFF_RESETS_MSB 3 -#define PSM_FRCE_OFF_RESETS_LSB 3 +#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) +#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) +#define PSM_FRCE_OFF_RESETS_MSB _u(3) +#define PSM_FRCE_OFF_RESETS_LSB _u(3) #define PSM_FRCE_OFF_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_CLOCKS // Description : None -#define PSM_FRCE_OFF_CLOCKS_RESET 0x0 -#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004 -#define PSM_FRCE_OFF_CLOCKS_MSB 2 -#define PSM_FRCE_OFF_CLOCKS_LSB 2 +#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) +#define PSM_FRCE_OFF_CLOCKS_MSB _u(2) +#define PSM_FRCE_OFF_CLOCKS_LSB _u(2) #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XOSC // Description : None -#define PSM_FRCE_OFF_XOSC_RESET 0x0 -#define PSM_FRCE_OFF_XOSC_BITS 0x00000002 -#define PSM_FRCE_OFF_XOSC_MSB 1 -#define PSM_FRCE_OFF_XOSC_LSB 1 +#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) +#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) +#define PSM_FRCE_OFF_XOSC_MSB _u(1) +#define PSM_FRCE_OFF_XOSC_LSB _u(1) #define PSM_FRCE_OFF_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROSC // Description : None -#define PSM_FRCE_OFF_ROSC_RESET 0x0 -#define PSM_FRCE_OFF_ROSC_BITS 0x00000001 -#define PSM_FRCE_OFF_ROSC_MSB 0 -#define PSM_FRCE_OFF_ROSC_LSB 0 +#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) +#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) +#define PSM_FRCE_OFF_ROSC_MSB _u(0) +#define PSM_FRCE_OFF_ROSC_LSB _u(0) #define PSM_FRCE_OFF_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_WDSEL // Description : Set to 1 if this peripheral should be reset when the watchdog // fires. -#define PSM_WDSEL_OFFSET 0x00000008 -#define PSM_WDSEL_BITS 0x0001ffff -#define PSM_WDSEL_RESET 0x00000000 +#define PSM_WDSEL_OFFSET _u(0x00000008) +#define PSM_WDSEL_BITS _u(0x0001ffff) +#define PSM_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC1 // Description : None -#define PSM_WDSEL_PROC1_RESET 0x0 -#define PSM_WDSEL_PROC1_BITS 0x00010000 -#define PSM_WDSEL_PROC1_MSB 16 -#define PSM_WDSEL_PROC1_LSB 16 +#define PSM_WDSEL_PROC1_RESET _u(0x0) +#define PSM_WDSEL_PROC1_BITS _u(0x00010000) +#define PSM_WDSEL_PROC1_MSB _u(16) +#define PSM_WDSEL_PROC1_LSB _u(16) #define PSM_WDSEL_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC0 // Description : None -#define PSM_WDSEL_PROC0_RESET 0x0 -#define PSM_WDSEL_PROC0_BITS 0x00008000 -#define PSM_WDSEL_PROC0_MSB 15 -#define PSM_WDSEL_PROC0_LSB 15 +#define PSM_WDSEL_PROC0_RESET _u(0x0) +#define PSM_WDSEL_PROC0_BITS _u(0x00008000) +#define PSM_WDSEL_PROC0_MSB _u(15) +#define PSM_WDSEL_PROC0_LSB _u(15) #define PSM_WDSEL_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SIO // Description : None -#define PSM_WDSEL_SIO_RESET 0x0 -#define PSM_WDSEL_SIO_BITS 0x00004000 -#define PSM_WDSEL_SIO_MSB 14 -#define PSM_WDSEL_SIO_LSB 14 +#define PSM_WDSEL_SIO_RESET _u(0x0) +#define PSM_WDSEL_SIO_BITS _u(0x00004000) +#define PSM_WDSEL_SIO_MSB _u(14) +#define PSM_WDSEL_SIO_LSB _u(14) #define PSM_WDSEL_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_VREG_AND_CHIP_RESET // Description : None -#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XIP // Description : None -#define PSM_WDSEL_XIP_RESET 0x0 -#define PSM_WDSEL_XIP_BITS 0x00001000 -#define PSM_WDSEL_XIP_MSB 12 -#define PSM_WDSEL_XIP_LSB 12 +#define PSM_WDSEL_XIP_RESET _u(0x0) +#define PSM_WDSEL_XIP_BITS _u(0x00001000) +#define PSM_WDSEL_XIP_MSB _u(12) +#define PSM_WDSEL_XIP_LSB _u(12) #define PSM_WDSEL_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM5 // Description : None -#define PSM_WDSEL_SRAM5_RESET 0x0 -#define PSM_WDSEL_SRAM5_BITS 0x00000800 -#define PSM_WDSEL_SRAM5_MSB 11 -#define PSM_WDSEL_SRAM5_LSB 11 +#define PSM_WDSEL_SRAM5_RESET _u(0x0) +#define PSM_WDSEL_SRAM5_BITS _u(0x00000800) +#define PSM_WDSEL_SRAM5_MSB _u(11) +#define PSM_WDSEL_SRAM5_LSB _u(11) #define PSM_WDSEL_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM4 // Description : None -#define PSM_WDSEL_SRAM4_RESET 0x0 -#define PSM_WDSEL_SRAM4_BITS 0x00000400 -#define PSM_WDSEL_SRAM4_MSB 10 -#define PSM_WDSEL_SRAM4_LSB 10 +#define PSM_WDSEL_SRAM4_RESET _u(0x0) +#define PSM_WDSEL_SRAM4_BITS _u(0x00000400) +#define PSM_WDSEL_SRAM4_MSB _u(10) +#define PSM_WDSEL_SRAM4_LSB _u(10) #define PSM_WDSEL_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM3 // Description : None -#define PSM_WDSEL_SRAM3_RESET 0x0 -#define PSM_WDSEL_SRAM3_BITS 0x00000200 -#define PSM_WDSEL_SRAM3_MSB 9 -#define PSM_WDSEL_SRAM3_LSB 9 +#define PSM_WDSEL_SRAM3_RESET _u(0x0) +#define PSM_WDSEL_SRAM3_BITS _u(0x00000200) +#define PSM_WDSEL_SRAM3_MSB _u(9) +#define PSM_WDSEL_SRAM3_LSB _u(9) #define PSM_WDSEL_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM2 // Description : None -#define PSM_WDSEL_SRAM2_RESET 0x0 -#define PSM_WDSEL_SRAM2_BITS 0x00000100 -#define PSM_WDSEL_SRAM2_MSB 8 -#define PSM_WDSEL_SRAM2_LSB 8 +#define PSM_WDSEL_SRAM2_RESET _u(0x0) +#define PSM_WDSEL_SRAM2_BITS _u(0x00000100) +#define PSM_WDSEL_SRAM2_MSB _u(8) +#define PSM_WDSEL_SRAM2_LSB _u(8) #define PSM_WDSEL_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM1 // Description : None -#define PSM_WDSEL_SRAM1_RESET 0x0 -#define PSM_WDSEL_SRAM1_BITS 0x00000080 -#define PSM_WDSEL_SRAM1_MSB 7 -#define PSM_WDSEL_SRAM1_LSB 7 +#define PSM_WDSEL_SRAM1_RESET _u(0x0) +#define PSM_WDSEL_SRAM1_BITS _u(0x00000080) +#define PSM_WDSEL_SRAM1_MSB _u(7) +#define PSM_WDSEL_SRAM1_LSB _u(7) #define PSM_WDSEL_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM0 // Description : None -#define PSM_WDSEL_SRAM0_RESET 0x0 -#define PSM_WDSEL_SRAM0_BITS 0x00000040 -#define PSM_WDSEL_SRAM0_MSB 6 -#define PSM_WDSEL_SRAM0_LSB 6 +#define PSM_WDSEL_SRAM0_RESET _u(0x0) +#define PSM_WDSEL_SRAM0_BITS _u(0x00000040) +#define PSM_WDSEL_SRAM0_MSB _u(6) +#define PSM_WDSEL_SRAM0_LSB _u(6) #define PSM_WDSEL_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROM // Description : None -#define PSM_WDSEL_ROM_RESET 0x0 -#define PSM_WDSEL_ROM_BITS 0x00000020 -#define PSM_WDSEL_ROM_MSB 5 -#define PSM_WDSEL_ROM_LSB 5 +#define PSM_WDSEL_ROM_RESET _u(0x0) +#define PSM_WDSEL_ROM_BITS _u(0x00000020) +#define PSM_WDSEL_ROM_MSB _u(5) +#define PSM_WDSEL_ROM_LSB _u(5) #define PSM_WDSEL_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_BUSFABRIC // Description : None -#define PSM_WDSEL_BUSFABRIC_RESET 0x0 -#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010 -#define PSM_WDSEL_BUSFABRIC_MSB 4 -#define PSM_WDSEL_BUSFABRIC_LSB 4 +#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) +#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) +#define PSM_WDSEL_BUSFABRIC_MSB _u(4) +#define PSM_WDSEL_BUSFABRIC_LSB _u(4) #define PSM_WDSEL_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_RESETS // Description : None -#define PSM_WDSEL_RESETS_RESET 0x0 -#define PSM_WDSEL_RESETS_BITS 0x00000008 -#define PSM_WDSEL_RESETS_MSB 3 -#define PSM_WDSEL_RESETS_LSB 3 +#define PSM_WDSEL_RESETS_RESET _u(0x0) +#define PSM_WDSEL_RESETS_BITS _u(0x00000008) +#define PSM_WDSEL_RESETS_MSB _u(3) +#define PSM_WDSEL_RESETS_LSB _u(3) #define PSM_WDSEL_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_CLOCKS // Description : None -#define PSM_WDSEL_CLOCKS_RESET 0x0 -#define PSM_WDSEL_CLOCKS_BITS 0x00000004 -#define PSM_WDSEL_CLOCKS_MSB 2 -#define PSM_WDSEL_CLOCKS_LSB 2 +#define PSM_WDSEL_CLOCKS_RESET _u(0x0) +#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) +#define PSM_WDSEL_CLOCKS_MSB _u(2) +#define PSM_WDSEL_CLOCKS_LSB _u(2) #define PSM_WDSEL_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XOSC // Description : None -#define PSM_WDSEL_XOSC_RESET 0x0 -#define PSM_WDSEL_XOSC_BITS 0x00000002 -#define PSM_WDSEL_XOSC_MSB 1 -#define PSM_WDSEL_XOSC_LSB 1 +#define PSM_WDSEL_XOSC_RESET _u(0x0) +#define PSM_WDSEL_XOSC_BITS _u(0x00000002) +#define PSM_WDSEL_XOSC_MSB _u(1) +#define PSM_WDSEL_XOSC_LSB _u(1) #define PSM_WDSEL_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROSC // Description : None -#define PSM_WDSEL_ROSC_RESET 0x0 -#define PSM_WDSEL_ROSC_BITS 0x00000001 -#define PSM_WDSEL_ROSC_MSB 0 -#define PSM_WDSEL_ROSC_LSB 0 +#define PSM_WDSEL_ROSC_RESET _u(0x0) +#define PSM_WDSEL_ROSC_BITS _u(0x00000001) +#define PSM_WDSEL_ROSC_MSB _u(0) +#define PSM_WDSEL_ROSC_LSB _u(0) #define PSM_WDSEL_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_DONE // Description : Indicates the peripheral's registers are ready to access. -#define PSM_DONE_OFFSET 0x0000000c -#define PSM_DONE_BITS 0x0001ffff -#define PSM_DONE_RESET 0x00000000 +#define PSM_DONE_OFFSET _u(0x0000000c) +#define PSM_DONE_BITS _u(0x0001ffff) +#define PSM_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC1 // Description : None -#define PSM_DONE_PROC1_RESET 0x0 -#define PSM_DONE_PROC1_BITS 0x00010000 -#define PSM_DONE_PROC1_MSB 16 -#define PSM_DONE_PROC1_LSB 16 +#define PSM_DONE_PROC1_RESET _u(0x0) +#define PSM_DONE_PROC1_BITS _u(0x00010000) +#define PSM_DONE_PROC1_MSB _u(16) +#define PSM_DONE_PROC1_LSB _u(16) #define PSM_DONE_PROC1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC0 // Description : None -#define PSM_DONE_PROC0_RESET 0x0 -#define PSM_DONE_PROC0_BITS 0x00008000 -#define PSM_DONE_PROC0_MSB 15 -#define PSM_DONE_PROC0_LSB 15 +#define PSM_DONE_PROC0_RESET _u(0x0) +#define PSM_DONE_PROC0_BITS _u(0x00008000) +#define PSM_DONE_PROC0_MSB _u(15) +#define PSM_DONE_PROC0_LSB _u(15) #define PSM_DONE_PROC0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SIO // Description : None -#define PSM_DONE_SIO_RESET 0x0 -#define PSM_DONE_SIO_BITS 0x00004000 -#define PSM_DONE_SIO_MSB 14 -#define PSM_DONE_SIO_LSB 14 +#define PSM_DONE_SIO_RESET _u(0x0) +#define PSM_DONE_SIO_BITS _u(0x00004000) +#define PSM_DONE_SIO_MSB _u(14) +#define PSM_DONE_SIO_LSB _u(14) #define PSM_DONE_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_VREG_AND_CHIP_RESET // Description : None -#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XIP // Description : None -#define PSM_DONE_XIP_RESET 0x0 -#define PSM_DONE_XIP_BITS 0x00001000 -#define PSM_DONE_XIP_MSB 12 -#define PSM_DONE_XIP_LSB 12 +#define PSM_DONE_XIP_RESET _u(0x0) +#define PSM_DONE_XIP_BITS _u(0x00001000) +#define PSM_DONE_XIP_MSB _u(12) +#define PSM_DONE_XIP_LSB _u(12) #define PSM_DONE_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM5 // Description : None -#define PSM_DONE_SRAM5_RESET 0x0 -#define PSM_DONE_SRAM5_BITS 0x00000800 -#define PSM_DONE_SRAM5_MSB 11 -#define PSM_DONE_SRAM5_LSB 11 +#define PSM_DONE_SRAM5_RESET _u(0x0) +#define PSM_DONE_SRAM5_BITS _u(0x00000800) +#define PSM_DONE_SRAM5_MSB _u(11) +#define PSM_DONE_SRAM5_LSB _u(11) #define PSM_DONE_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM4 // Description : None -#define PSM_DONE_SRAM4_RESET 0x0 -#define PSM_DONE_SRAM4_BITS 0x00000400 -#define PSM_DONE_SRAM4_MSB 10 -#define PSM_DONE_SRAM4_LSB 10 +#define PSM_DONE_SRAM4_RESET _u(0x0) +#define PSM_DONE_SRAM4_BITS _u(0x00000400) +#define PSM_DONE_SRAM4_MSB _u(10) +#define PSM_DONE_SRAM4_LSB _u(10) #define PSM_DONE_SRAM4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM3 // Description : None -#define PSM_DONE_SRAM3_RESET 0x0 -#define PSM_DONE_SRAM3_BITS 0x00000200 -#define PSM_DONE_SRAM3_MSB 9 -#define PSM_DONE_SRAM3_LSB 9 +#define PSM_DONE_SRAM3_RESET _u(0x0) +#define PSM_DONE_SRAM3_BITS _u(0x00000200) +#define PSM_DONE_SRAM3_MSB _u(9) +#define PSM_DONE_SRAM3_LSB _u(9) #define PSM_DONE_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM2 // Description : None -#define PSM_DONE_SRAM2_RESET 0x0 -#define PSM_DONE_SRAM2_BITS 0x00000100 -#define PSM_DONE_SRAM2_MSB 8 -#define PSM_DONE_SRAM2_LSB 8 +#define PSM_DONE_SRAM2_RESET _u(0x0) +#define PSM_DONE_SRAM2_BITS _u(0x00000100) +#define PSM_DONE_SRAM2_MSB _u(8) +#define PSM_DONE_SRAM2_LSB _u(8) #define PSM_DONE_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM1 // Description : None -#define PSM_DONE_SRAM1_RESET 0x0 -#define PSM_DONE_SRAM1_BITS 0x00000080 -#define PSM_DONE_SRAM1_MSB 7 -#define PSM_DONE_SRAM1_LSB 7 +#define PSM_DONE_SRAM1_RESET _u(0x0) +#define PSM_DONE_SRAM1_BITS _u(0x00000080) +#define PSM_DONE_SRAM1_MSB _u(7) +#define PSM_DONE_SRAM1_LSB _u(7) #define PSM_DONE_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM0 // Description : None -#define PSM_DONE_SRAM0_RESET 0x0 -#define PSM_DONE_SRAM0_BITS 0x00000040 -#define PSM_DONE_SRAM0_MSB 6 -#define PSM_DONE_SRAM0_LSB 6 +#define PSM_DONE_SRAM0_RESET _u(0x0) +#define PSM_DONE_SRAM0_BITS _u(0x00000040) +#define PSM_DONE_SRAM0_MSB _u(6) +#define PSM_DONE_SRAM0_LSB _u(6) #define PSM_DONE_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROM // Description : None -#define PSM_DONE_ROM_RESET 0x0 -#define PSM_DONE_ROM_BITS 0x00000020 -#define PSM_DONE_ROM_MSB 5 -#define PSM_DONE_ROM_LSB 5 +#define PSM_DONE_ROM_RESET _u(0x0) +#define PSM_DONE_ROM_BITS _u(0x00000020) +#define PSM_DONE_ROM_MSB _u(5) +#define PSM_DONE_ROM_LSB _u(5) #define PSM_DONE_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_BUSFABRIC // Description : None -#define PSM_DONE_BUSFABRIC_RESET 0x0 -#define PSM_DONE_BUSFABRIC_BITS 0x00000010 -#define PSM_DONE_BUSFABRIC_MSB 4 -#define PSM_DONE_BUSFABRIC_LSB 4 +#define PSM_DONE_BUSFABRIC_RESET _u(0x0) +#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) +#define PSM_DONE_BUSFABRIC_MSB _u(4) +#define PSM_DONE_BUSFABRIC_LSB _u(4) #define PSM_DONE_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_RESETS // Description : None -#define PSM_DONE_RESETS_RESET 0x0 -#define PSM_DONE_RESETS_BITS 0x00000008 -#define PSM_DONE_RESETS_MSB 3 -#define PSM_DONE_RESETS_LSB 3 +#define PSM_DONE_RESETS_RESET _u(0x0) +#define PSM_DONE_RESETS_BITS _u(0x00000008) +#define PSM_DONE_RESETS_MSB _u(3) +#define PSM_DONE_RESETS_LSB _u(3) #define PSM_DONE_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_CLOCKS // Description : None -#define PSM_DONE_CLOCKS_RESET 0x0 -#define PSM_DONE_CLOCKS_BITS 0x00000004 -#define PSM_DONE_CLOCKS_MSB 2 -#define PSM_DONE_CLOCKS_LSB 2 +#define PSM_DONE_CLOCKS_RESET _u(0x0) +#define PSM_DONE_CLOCKS_BITS _u(0x00000004) +#define PSM_DONE_CLOCKS_MSB _u(2) +#define PSM_DONE_CLOCKS_LSB _u(2) #define PSM_DONE_CLOCKS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XOSC // Description : None -#define PSM_DONE_XOSC_RESET 0x0 -#define PSM_DONE_XOSC_BITS 0x00000002 -#define PSM_DONE_XOSC_MSB 1 -#define PSM_DONE_XOSC_LSB 1 +#define PSM_DONE_XOSC_RESET _u(0x0) +#define PSM_DONE_XOSC_BITS _u(0x00000002) +#define PSM_DONE_XOSC_MSB _u(1) +#define PSM_DONE_XOSC_LSB _u(1) #define PSM_DONE_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROSC // Description : None -#define PSM_DONE_ROSC_RESET 0x0 -#define PSM_DONE_ROSC_BITS 0x00000001 -#define PSM_DONE_ROSC_MSB 0 -#define PSM_DONE_ROSC_LSB 0 +#define PSM_DONE_ROSC_RESET _u(0x0) +#define PSM_DONE_ROSC_BITS _u(0x00000001) +#define PSM_DONE_ROSC_MSB _u(0) +#define PSM_DONE_ROSC_LSB _u(0) #define PSM_DONE_ROSC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PSM_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h index 01e2e5c21fc..a853597877e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : PWM_CH0_CSR // Description : Control and status register -#define PWM_CH0_CSR_OFFSET 0x00000000 -#define PWM_CH0_CSR_BITS 0x000000ff -#define PWM_CH0_CSR_RESET 0x00000000 +#define PWM_CH0_CSR_OFFSET _u(0x00000000) +#define PWM_CH0_CSR_BITS _u(0x000000ff) +#define PWM_CH0_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -24,10 +24,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH0_CSR_PH_ADV_RESET 0x0 -#define PWM_CH0_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH0_CSR_PH_ADV_MSB 7 -#define PWM_CH0_CSR_PH_ADV_LSB 7 +#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH0_CSR_PH_ADV_MSB _u(7) +#define PWM_CH0_CSR_PH_ADV_LSB _u(7) #define PWM_CH0_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_RET @@ -35,10 +35,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH0_CSR_PH_RET_RESET 0x0 -#define PWM_CH0_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH0_CSR_PH_RET_MSB 6 -#define PWM_CH0_CSR_PH_RET_LSB 6 +#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH0_CSR_PH_RET_MSB _u(6) +#define PWM_CH0_CSR_PH_RET_LSB _u(6) #define PWM_CH0_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE @@ -48,117 +48,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH0_CSR_DIVMODE_RESET 0x0 -#define PWM_CH0_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH0_CSR_DIVMODE_MSB 5 -#define PWM_CH0_CSR_DIVMODE_LSB 4 +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) #define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_B_INV // Description : Invert output B -#define PWM_CH0_CSR_B_INV_RESET 0x0 -#define PWM_CH0_CSR_B_INV_BITS 0x00000008 -#define PWM_CH0_CSR_B_INV_MSB 3 -#define PWM_CH0_CSR_B_INV_LSB 3 +#define PWM_CH0_CSR_B_INV_RESET _u(0x0) +#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH0_CSR_B_INV_MSB _u(3) +#define PWM_CH0_CSR_B_INV_LSB _u(3) #define PWM_CH0_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_A_INV // Description : Invert output A -#define PWM_CH0_CSR_A_INV_RESET 0x0 -#define PWM_CH0_CSR_A_INV_BITS 0x00000004 -#define PWM_CH0_CSR_A_INV_MSB 2 -#define PWM_CH0_CSR_A_INV_LSB 2 +#define PWM_CH0_CSR_A_INV_RESET _u(0x0) +#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH0_CSR_A_INV_MSB _u(2) +#define PWM_CH0_CSR_A_INV_LSB _u(2) #define PWM_CH0_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH0_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH0_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH0_CSR_PH_CORRECT_MSB 1 -#define PWM_CH0_CSR_PH_CORRECT_LSB 1 +#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH0_CSR_EN_RESET 0x0 -#define PWM_CH0_CSR_EN_BITS 0x00000001 -#define PWM_CH0_CSR_EN_MSB 0 -#define PWM_CH0_CSR_EN_LSB 0 +#define PWM_CH0_CSR_EN_RESET _u(0x0) +#define PWM_CH0_CSR_EN_BITS _u(0x00000001) +#define PWM_CH0_CSR_EN_MSB _u(0) +#define PWM_CH0_CSR_EN_LSB _u(0) #define PWM_CH0_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH0_DIV_OFFSET 0x00000004 -#define PWM_CH0_DIV_BITS 0x00000fff -#define PWM_CH0_DIV_RESET 0x00000010 +#define PWM_CH0_DIV_OFFSET _u(0x00000004) +#define PWM_CH0_DIV_BITS _u(0x00000fff) +#define PWM_CH0_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_INT // Description : None -#define PWM_CH0_DIV_INT_RESET 0x01 -#define PWM_CH0_DIV_INT_BITS 0x00000ff0 -#define PWM_CH0_DIV_INT_MSB 11 -#define PWM_CH0_DIV_INT_LSB 4 +#define PWM_CH0_DIV_INT_RESET _u(0x01) +#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH0_DIV_INT_MSB _u(11) +#define PWM_CH0_DIV_INT_LSB _u(4) #define PWM_CH0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_FRAC // Description : None -#define PWM_CH0_DIV_FRAC_RESET 0x0 -#define PWM_CH0_DIV_FRAC_BITS 0x0000000f -#define PWM_CH0_DIV_FRAC_MSB 3 -#define PWM_CH0_DIV_FRAC_LSB 0 +#define PWM_CH0_DIV_FRAC_RESET _u(0x0) +#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH0_DIV_FRAC_MSB _u(3) +#define PWM_CH0_DIV_FRAC_LSB _u(0) #define PWM_CH0_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_CTR // Description : Direct access to the PWM counter -#define PWM_CH0_CTR_OFFSET 0x00000008 -#define PWM_CH0_CTR_BITS 0x0000ffff -#define PWM_CH0_CTR_RESET 0x00000000 -#define PWM_CH0_CTR_MSB 15 -#define PWM_CH0_CTR_LSB 0 +#define PWM_CH0_CTR_OFFSET _u(0x00000008) +#define PWM_CH0_CTR_BITS _u(0x0000ffff) +#define PWM_CH0_CTR_RESET _u(0x00000000) +#define PWM_CH0_CTR_MSB _u(15) +#define PWM_CH0_CTR_LSB _u(0) #define PWM_CH0_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_CC // Description : Counter compare values -#define PWM_CH0_CC_OFFSET 0x0000000c -#define PWM_CH0_CC_BITS 0xffffffff -#define PWM_CH0_CC_RESET 0x00000000 +#define PWM_CH0_CC_OFFSET _u(0x0000000c) +#define PWM_CH0_CC_BITS _u(0xffffffff) +#define PWM_CH0_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_B // Description : None -#define PWM_CH0_CC_B_RESET 0x0000 -#define PWM_CH0_CC_B_BITS 0xffff0000 -#define PWM_CH0_CC_B_MSB 31 -#define PWM_CH0_CC_B_LSB 16 +#define PWM_CH0_CC_B_RESET _u(0x0000) +#define PWM_CH0_CC_B_BITS _u(0xffff0000) +#define PWM_CH0_CC_B_MSB _u(31) +#define PWM_CH0_CC_B_LSB _u(16) #define PWM_CH0_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_A // Description : None -#define PWM_CH0_CC_A_RESET 0x0000 -#define PWM_CH0_CC_A_BITS 0x0000ffff -#define PWM_CH0_CC_A_MSB 15 -#define PWM_CH0_CC_A_LSB 0 +#define PWM_CH0_CC_A_RESET _u(0x0000) +#define PWM_CH0_CC_A_BITS _u(0x0000ffff) +#define PWM_CH0_CC_A_MSB _u(15) +#define PWM_CH0_CC_A_LSB _u(0) #define PWM_CH0_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_TOP // Description : Counter wrap value -#define PWM_CH0_TOP_OFFSET 0x00000010 -#define PWM_CH0_TOP_BITS 0x0000ffff -#define PWM_CH0_TOP_RESET 0x0000ffff -#define PWM_CH0_TOP_MSB 15 -#define PWM_CH0_TOP_LSB 0 +#define PWM_CH0_TOP_OFFSET _u(0x00000010) +#define PWM_CH0_TOP_BITS _u(0x0000ffff) +#define PWM_CH0_TOP_RESET _u(0x0000ffff) +#define PWM_CH0_TOP_MSB _u(15) +#define PWM_CH0_TOP_LSB _u(0) #define PWM_CH0_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CSR // Description : Control and status register -#define PWM_CH1_CSR_OFFSET 0x00000014 -#define PWM_CH1_CSR_BITS 0x000000ff -#define PWM_CH1_CSR_RESET 0x00000000 +#define PWM_CH1_CSR_OFFSET _u(0x00000014) +#define PWM_CH1_CSR_BITS _u(0x000000ff) +#define PWM_CH1_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -166,10 +166,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH1_CSR_PH_ADV_RESET 0x0 -#define PWM_CH1_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH1_CSR_PH_ADV_MSB 7 -#define PWM_CH1_CSR_PH_ADV_LSB 7 +#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH1_CSR_PH_ADV_MSB _u(7) +#define PWM_CH1_CSR_PH_ADV_LSB _u(7) #define PWM_CH1_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_RET @@ -177,10 +177,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH1_CSR_PH_RET_RESET 0x0 -#define PWM_CH1_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH1_CSR_PH_RET_MSB 6 -#define PWM_CH1_CSR_PH_RET_LSB 6 +#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH1_CSR_PH_RET_MSB _u(6) +#define PWM_CH1_CSR_PH_RET_LSB _u(6) #define PWM_CH1_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE @@ -190,117 +190,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH1_CSR_DIVMODE_RESET 0x0 -#define PWM_CH1_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH1_CSR_DIVMODE_MSB 5 -#define PWM_CH1_CSR_DIVMODE_LSB 4 +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) #define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_B_INV // Description : Invert output B -#define PWM_CH1_CSR_B_INV_RESET 0x0 -#define PWM_CH1_CSR_B_INV_BITS 0x00000008 -#define PWM_CH1_CSR_B_INV_MSB 3 -#define PWM_CH1_CSR_B_INV_LSB 3 +#define PWM_CH1_CSR_B_INV_RESET _u(0x0) +#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH1_CSR_B_INV_MSB _u(3) +#define PWM_CH1_CSR_B_INV_LSB _u(3) #define PWM_CH1_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_A_INV // Description : Invert output A -#define PWM_CH1_CSR_A_INV_RESET 0x0 -#define PWM_CH1_CSR_A_INV_BITS 0x00000004 -#define PWM_CH1_CSR_A_INV_MSB 2 -#define PWM_CH1_CSR_A_INV_LSB 2 +#define PWM_CH1_CSR_A_INV_RESET _u(0x0) +#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH1_CSR_A_INV_MSB _u(2) +#define PWM_CH1_CSR_A_INV_LSB _u(2) #define PWM_CH1_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH1_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH1_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH1_CSR_PH_CORRECT_MSB 1 -#define PWM_CH1_CSR_PH_CORRECT_LSB 1 +#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH1_CSR_EN_RESET 0x0 -#define PWM_CH1_CSR_EN_BITS 0x00000001 -#define PWM_CH1_CSR_EN_MSB 0 -#define PWM_CH1_CSR_EN_LSB 0 +#define PWM_CH1_CSR_EN_RESET _u(0x0) +#define PWM_CH1_CSR_EN_BITS _u(0x00000001) +#define PWM_CH1_CSR_EN_MSB _u(0) +#define PWM_CH1_CSR_EN_LSB _u(0) #define PWM_CH1_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH1_DIV_OFFSET 0x00000018 -#define PWM_CH1_DIV_BITS 0x00000fff -#define PWM_CH1_DIV_RESET 0x00000010 +#define PWM_CH1_DIV_OFFSET _u(0x00000018) +#define PWM_CH1_DIV_BITS _u(0x00000fff) +#define PWM_CH1_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_INT // Description : None -#define PWM_CH1_DIV_INT_RESET 0x01 -#define PWM_CH1_DIV_INT_BITS 0x00000ff0 -#define PWM_CH1_DIV_INT_MSB 11 -#define PWM_CH1_DIV_INT_LSB 4 +#define PWM_CH1_DIV_INT_RESET _u(0x01) +#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH1_DIV_INT_MSB _u(11) +#define PWM_CH1_DIV_INT_LSB _u(4) #define PWM_CH1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_FRAC // Description : None -#define PWM_CH1_DIV_FRAC_RESET 0x0 -#define PWM_CH1_DIV_FRAC_BITS 0x0000000f -#define PWM_CH1_DIV_FRAC_MSB 3 -#define PWM_CH1_DIV_FRAC_LSB 0 +#define PWM_CH1_DIV_FRAC_RESET _u(0x0) +#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH1_DIV_FRAC_MSB _u(3) +#define PWM_CH1_DIV_FRAC_LSB _u(0) #define PWM_CH1_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CTR // Description : Direct access to the PWM counter -#define PWM_CH1_CTR_OFFSET 0x0000001c -#define PWM_CH1_CTR_BITS 0x0000ffff -#define PWM_CH1_CTR_RESET 0x00000000 -#define PWM_CH1_CTR_MSB 15 -#define PWM_CH1_CTR_LSB 0 +#define PWM_CH1_CTR_OFFSET _u(0x0000001c) +#define PWM_CH1_CTR_BITS _u(0x0000ffff) +#define PWM_CH1_CTR_RESET _u(0x00000000) +#define PWM_CH1_CTR_MSB _u(15) +#define PWM_CH1_CTR_LSB _u(0) #define PWM_CH1_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CC // Description : Counter compare values -#define PWM_CH1_CC_OFFSET 0x00000020 -#define PWM_CH1_CC_BITS 0xffffffff -#define PWM_CH1_CC_RESET 0x00000000 +#define PWM_CH1_CC_OFFSET _u(0x00000020) +#define PWM_CH1_CC_BITS _u(0xffffffff) +#define PWM_CH1_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_B // Description : None -#define PWM_CH1_CC_B_RESET 0x0000 -#define PWM_CH1_CC_B_BITS 0xffff0000 -#define PWM_CH1_CC_B_MSB 31 -#define PWM_CH1_CC_B_LSB 16 +#define PWM_CH1_CC_B_RESET _u(0x0000) +#define PWM_CH1_CC_B_BITS _u(0xffff0000) +#define PWM_CH1_CC_B_MSB _u(31) +#define PWM_CH1_CC_B_LSB _u(16) #define PWM_CH1_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_A // Description : None -#define PWM_CH1_CC_A_RESET 0x0000 -#define PWM_CH1_CC_A_BITS 0x0000ffff -#define PWM_CH1_CC_A_MSB 15 -#define PWM_CH1_CC_A_LSB 0 +#define PWM_CH1_CC_A_RESET _u(0x0000) +#define PWM_CH1_CC_A_BITS _u(0x0000ffff) +#define PWM_CH1_CC_A_MSB _u(15) +#define PWM_CH1_CC_A_LSB _u(0) #define PWM_CH1_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_TOP // Description : Counter wrap value -#define PWM_CH1_TOP_OFFSET 0x00000024 -#define PWM_CH1_TOP_BITS 0x0000ffff -#define PWM_CH1_TOP_RESET 0x0000ffff -#define PWM_CH1_TOP_MSB 15 -#define PWM_CH1_TOP_LSB 0 +#define PWM_CH1_TOP_OFFSET _u(0x00000024) +#define PWM_CH1_TOP_BITS _u(0x0000ffff) +#define PWM_CH1_TOP_RESET _u(0x0000ffff) +#define PWM_CH1_TOP_MSB _u(15) +#define PWM_CH1_TOP_LSB _u(0) #define PWM_CH1_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CSR // Description : Control and status register -#define PWM_CH2_CSR_OFFSET 0x00000028 -#define PWM_CH2_CSR_BITS 0x000000ff -#define PWM_CH2_CSR_RESET 0x00000000 +#define PWM_CH2_CSR_OFFSET _u(0x00000028) +#define PWM_CH2_CSR_BITS _u(0x000000ff) +#define PWM_CH2_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -308,10 +308,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH2_CSR_PH_ADV_RESET 0x0 -#define PWM_CH2_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH2_CSR_PH_ADV_MSB 7 -#define PWM_CH2_CSR_PH_ADV_LSB 7 +#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH2_CSR_PH_ADV_MSB _u(7) +#define PWM_CH2_CSR_PH_ADV_LSB _u(7) #define PWM_CH2_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_RET @@ -319,10 +319,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH2_CSR_PH_RET_RESET 0x0 -#define PWM_CH2_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH2_CSR_PH_RET_MSB 6 -#define PWM_CH2_CSR_PH_RET_LSB 6 +#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH2_CSR_PH_RET_MSB _u(6) +#define PWM_CH2_CSR_PH_RET_LSB _u(6) #define PWM_CH2_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE @@ -332,117 +332,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH2_CSR_DIVMODE_RESET 0x0 -#define PWM_CH2_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH2_CSR_DIVMODE_MSB 5 -#define PWM_CH2_CSR_DIVMODE_LSB 4 +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) #define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_B_INV // Description : Invert output B -#define PWM_CH2_CSR_B_INV_RESET 0x0 -#define PWM_CH2_CSR_B_INV_BITS 0x00000008 -#define PWM_CH2_CSR_B_INV_MSB 3 -#define PWM_CH2_CSR_B_INV_LSB 3 +#define PWM_CH2_CSR_B_INV_RESET _u(0x0) +#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH2_CSR_B_INV_MSB _u(3) +#define PWM_CH2_CSR_B_INV_LSB _u(3) #define PWM_CH2_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_A_INV // Description : Invert output A -#define PWM_CH2_CSR_A_INV_RESET 0x0 -#define PWM_CH2_CSR_A_INV_BITS 0x00000004 -#define PWM_CH2_CSR_A_INV_MSB 2 -#define PWM_CH2_CSR_A_INV_LSB 2 +#define PWM_CH2_CSR_A_INV_RESET _u(0x0) +#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH2_CSR_A_INV_MSB _u(2) +#define PWM_CH2_CSR_A_INV_LSB _u(2) #define PWM_CH2_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH2_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH2_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH2_CSR_PH_CORRECT_MSB 1 -#define PWM_CH2_CSR_PH_CORRECT_LSB 1 +#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH2_CSR_EN_RESET 0x0 -#define PWM_CH2_CSR_EN_BITS 0x00000001 -#define PWM_CH2_CSR_EN_MSB 0 -#define PWM_CH2_CSR_EN_LSB 0 +#define PWM_CH2_CSR_EN_RESET _u(0x0) +#define PWM_CH2_CSR_EN_BITS _u(0x00000001) +#define PWM_CH2_CSR_EN_MSB _u(0) +#define PWM_CH2_CSR_EN_LSB _u(0) #define PWM_CH2_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH2_DIV_OFFSET 0x0000002c -#define PWM_CH2_DIV_BITS 0x00000fff -#define PWM_CH2_DIV_RESET 0x00000010 +#define PWM_CH2_DIV_OFFSET _u(0x0000002c) +#define PWM_CH2_DIV_BITS _u(0x00000fff) +#define PWM_CH2_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_INT // Description : None -#define PWM_CH2_DIV_INT_RESET 0x01 -#define PWM_CH2_DIV_INT_BITS 0x00000ff0 -#define PWM_CH2_DIV_INT_MSB 11 -#define PWM_CH2_DIV_INT_LSB 4 +#define PWM_CH2_DIV_INT_RESET _u(0x01) +#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH2_DIV_INT_MSB _u(11) +#define PWM_CH2_DIV_INT_LSB _u(4) #define PWM_CH2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_FRAC // Description : None -#define PWM_CH2_DIV_FRAC_RESET 0x0 -#define PWM_CH2_DIV_FRAC_BITS 0x0000000f -#define PWM_CH2_DIV_FRAC_MSB 3 -#define PWM_CH2_DIV_FRAC_LSB 0 +#define PWM_CH2_DIV_FRAC_RESET _u(0x0) +#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH2_DIV_FRAC_MSB _u(3) +#define PWM_CH2_DIV_FRAC_LSB _u(0) #define PWM_CH2_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CTR // Description : Direct access to the PWM counter -#define PWM_CH2_CTR_OFFSET 0x00000030 -#define PWM_CH2_CTR_BITS 0x0000ffff -#define PWM_CH2_CTR_RESET 0x00000000 -#define PWM_CH2_CTR_MSB 15 -#define PWM_CH2_CTR_LSB 0 +#define PWM_CH2_CTR_OFFSET _u(0x00000030) +#define PWM_CH2_CTR_BITS _u(0x0000ffff) +#define PWM_CH2_CTR_RESET _u(0x00000000) +#define PWM_CH2_CTR_MSB _u(15) +#define PWM_CH2_CTR_LSB _u(0) #define PWM_CH2_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CC // Description : Counter compare values -#define PWM_CH2_CC_OFFSET 0x00000034 -#define PWM_CH2_CC_BITS 0xffffffff -#define PWM_CH2_CC_RESET 0x00000000 +#define PWM_CH2_CC_OFFSET _u(0x00000034) +#define PWM_CH2_CC_BITS _u(0xffffffff) +#define PWM_CH2_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_B // Description : None -#define PWM_CH2_CC_B_RESET 0x0000 -#define PWM_CH2_CC_B_BITS 0xffff0000 -#define PWM_CH2_CC_B_MSB 31 -#define PWM_CH2_CC_B_LSB 16 +#define PWM_CH2_CC_B_RESET _u(0x0000) +#define PWM_CH2_CC_B_BITS _u(0xffff0000) +#define PWM_CH2_CC_B_MSB _u(31) +#define PWM_CH2_CC_B_LSB _u(16) #define PWM_CH2_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_A // Description : None -#define PWM_CH2_CC_A_RESET 0x0000 -#define PWM_CH2_CC_A_BITS 0x0000ffff -#define PWM_CH2_CC_A_MSB 15 -#define PWM_CH2_CC_A_LSB 0 +#define PWM_CH2_CC_A_RESET _u(0x0000) +#define PWM_CH2_CC_A_BITS _u(0x0000ffff) +#define PWM_CH2_CC_A_MSB _u(15) +#define PWM_CH2_CC_A_LSB _u(0) #define PWM_CH2_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_TOP // Description : Counter wrap value -#define PWM_CH2_TOP_OFFSET 0x00000038 -#define PWM_CH2_TOP_BITS 0x0000ffff -#define PWM_CH2_TOP_RESET 0x0000ffff -#define PWM_CH2_TOP_MSB 15 -#define PWM_CH2_TOP_LSB 0 +#define PWM_CH2_TOP_OFFSET _u(0x00000038) +#define PWM_CH2_TOP_BITS _u(0x0000ffff) +#define PWM_CH2_TOP_RESET _u(0x0000ffff) +#define PWM_CH2_TOP_MSB _u(15) +#define PWM_CH2_TOP_LSB _u(0) #define PWM_CH2_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CSR // Description : Control and status register -#define PWM_CH3_CSR_OFFSET 0x0000003c -#define PWM_CH3_CSR_BITS 0x000000ff -#define PWM_CH3_CSR_RESET 0x00000000 +#define PWM_CH3_CSR_OFFSET _u(0x0000003c) +#define PWM_CH3_CSR_BITS _u(0x000000ff) +#define PWM_CH3_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -450,10 +450,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH3_CSR_PH_ADV_RESET 0x0 -#define PWM_CH3_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH3_CSR_PH_ADV_MSB 7 -#define PWM_CH3_CSR_PH_ADV_LSB 7 +#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH3_CSR_PH_ADV_MSB _u(7) +#define PWM_CH3_CSR_PH_ADV_LSB _u(7) #define PWM_CH3_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_RET @@ -461,10 +461,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH3_CSR_PH_RET_RESET 0x0 -#define PWM_CH3_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH3_CSR_PH_RET_MSB 6 -#define PWM_CH3_CSR_PH_RET_LSB 6 +#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH3_CSR_PH_RET_MSB _u(6) +#define PWM_CH3_CSR_PH_RET_LSB _u(6) #define PWM_CH3_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE @@ -474,117 +474,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH3_CSR_DIVMODE_RESET 0x0 -#define PWM_CH3_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH3_CSR_DIVMODE_MSB 5 -#define PWM_CH3_CSR_DIVMODE_LSB 4 +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) #define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_B_INV // Description : Invert output B -#define PWM_CH3_CSR_B_INV_RESET 0x0 -#define PWM_CH3_CSR_B_INV_BITS 0x00000008 -#define PWM_CH3_CSR_B_INV_MSB 3 -#define PWM_CH3_CSR_B_INV_LSB 3 +#define PWM_CH3_CSR_B_INV_RESET _u(0x0) +#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH3_CSR_B_INV_MSB _u(3) +#define PWM_CH3_CSR_B_INV_LSB _u(3) #define PWM_CH3_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_A_INV // Description : Invert output A -#define PWM_CH3_CSR_A_INV_RESET 0x0 -#define PWM_CH3_CSR_A_INV_BITS 0x00000004 -#define PWM_CH3_CSR_A_INV_MSB 2 -#define PWM_CH3_CSR_A_INV_LSB 2 +#define PWM_CH3_CSR_A_INV_RESET _u(0x0) +#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH3_CSR_A_INV_MSB _u(2) +#define PWM_CH3_CSR_A_INV_LSB _u(2) #define PWM_CH3_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH3_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH3_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH3_CSR_PH_CORRECT_MSB 1 -#define PWM_CH3_CSR_PH_CORRECT_LSB 1 +#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH3_CSR_EN_RESET 0x0 -#define PWM_CH3_CSR_EN_BITS 0x00000001 -#define PWM_CH3_CSR_EN_MSB 0 -#define PWM_CH3_CSR_EN_LSB 0 +#define PWM_CH3_CSR_EN_RESET _u(0x0) +#define PWM_CH3_CSR_EN_BITS _u(0x00000001) +#define PWM_CH3_CSR_EN_MSB _u(0) +#define PWM_CH3_CSR_EN_LSB _u(0) #define PWM_CH3_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH3_DIV_OFFSET 0x00000040 -#define PWM_CH3_DIV_BITS 0x00000fff -#define PWM_CH3_DIV_RESET 0x00000010 +#define PWM_CH3_DIV_OFFSET _u(0x00000040) +#define PWM_CH3_DIV_BITS _u(0x00000fff) +#define PWM_CH3_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_INT // Description : None -#define PWM_CH3_DIV_INT_RESET 0x01 -#define PWM_CH3_DIV_INT_BITS 0x00000ff0 -#define PWM_CH3_DIV_INT_MSB 11 -#define PWM_CH3_DIV_INT_LSB 4 +#define PWM_CH3_DIV_INT_RESET _u(0x01) +#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH3_DIV_INT_MSB _u(11) +#define PWM_CH3_DIV_INT_LSB _u(4) #define PWM_CH3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_FRAC // Description : None -#define PWM_CH3_DIV_FRAC_RESET 0x0 -#define PWM_CH3_DIV_FRAC_BITS 0x0000000f -#define PWM_CH3_DIV_FRAC_MSB 3 -#define PWM_CH3_DIV_FRAC_LSB 0 +#define PWM_CH3_DIV_FRAC_RESET _u(0x0) +#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH3_DIV_FRAC_MSB _u(3) +#define PWM_CH3_DIV_FRAC_LSB _u(0) #define PWM_CH3_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CTR // Description : Direct access to the PWM counter -#define PWM_CH3_CTR_OFFSET 0x00000044 -#define PWM_CH3_CTR_BITS 0x0000ffff -#define PWM_CH3_CTR_RESET 0x00000000 -#define PWM_CH3_CTR_MSB 15 -#define PWM_CH3_CTR_LSB 0 +#define PWM_CH3_CTR_OFFSET _u(0x00000044) +#define PWM_CH3_CTR_BITS _u(0x0000ffff) +#define PWM_CH3_CTR_RESET _u(0x00000000) +#define PWM_CH3_CTR_MSB _u(15) +#define PWM_CH3_CTR_LSB _u(0) #define PWM_CH3_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CC // Description : Counter compare values -#define PWM_CH3_CC_OFFSET 0x00000048 -#define PWM_CH3_CC_BITS 0xffffffff -#define PWM_CH3_CC_RESET 0x00000000 +#define PWM_CH3_CC_OFFSET _u(0x00000048) +#define PWM_CH3_CC_BITS _u(0xffffffff) +#define PWM_CH3_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_B // Description : None -#define PWM_CH3_CC_B_RESET 0x0000 -#define PWM_CH3_CC_B_BITS 0xffff0000 -#define PWM_CH3_CC_B_MSB 31 -#define PWM_CH3_CC_B_LSB 16 +#define PWM_CH3_CC_B_RESET _u(0x0000) +#define PWM_CH3_CC_B_BITS _u(0xffff0000) +#define PWM_CH3_CC_B_MSB _u(31) +#define PWM_CH3_CC_B_LSB _u(16) #define PWM_CH3_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_A // Description : None -#define PWM_CH3_CC_A_RESET 0x0000 -#define PWM_CH3_CC_A_BITS 0x0000ffff -#define PWM_CH3_CC_A_MSB 15 -#define PWM_CH3_CC_A_LSB 0 +#define PWM_CH3_CC_A_RESET _u(0x0000) +#define PWM_CH3_CC_A_BITS _u(0x0000ffff) +#define PWM_CH3_CC_A_MSB _u(15) +#define PWM_CH3_CC_A_LSB _u(0) #define PWM_CH3_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_TOP // Description : Counter wrap value -#define PWM_CH3_TOP_OFFSET 0x0000004c -#define PWM_CH3_TOP_BITS 0x0000ffff -#define PWM_CH3_TOP_RESET 0x0000ffff -#define PWM_CH3_TOP_MSB 15 -#define PWM_CH3_TOP_LSB 0 +#define PWM_CH3_TOP_OFFSET _u(0x0000004c) +#define PWM_CH3_TOP_BITS _u(0x0000ffff) +#define PWM_CH3_TOP_RESET _u(0x0000ffff) +#define PWM_CH3_TOP_MSB _u(15) +#define PWM_CH3_TOP_LSB _u(0) #define PWM_CH3_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CSR // Description : Control and status register -#define PWM_CH4_CSR_OFFSET 0x00000050 -#define PWM_CH4_CSR_BITS 0x000000ff -#define PWM_CH4_CSR_RESET 0x00000000 +#define PWM_CH4_CSR_OFFSET _u(0x00000050) +#define PWM_CH4_CSR_BITS _u(0x000000ff) +#define PWM_CH4_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -592,10 +592,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH4_CSR_PH_ADV_RESET 0x0 -#define PWM_CH4_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH4_CSR_PH_ADV_MSB 7 -#define PWM_CH4_CSR_PH_ADV_LSB 7 +#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH4_CSR_PH_ADV_MSB _u(7) +#define PWM_CH4_CSR_PH_ADV_LSB _u(7) #define PWM_CH4_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_RET @@ -603,10 +603,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH4_CSR_PH_RET_RESET 0x0 -#define PWM_CH4_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH4_CSR_PH_RET_MSB 6 -#define PWM_CH4_CSR_PH_RET_LSB 6 +#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH4_CSR_PH_RET_MSB _u(6) +#define PWM_CH4_CSR_PH_RET_LSB _u(6) #define PWM_CH4_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE @@ -616,117 +616,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH4_CSR_DIVMODE_RESET 0x0 -#define PWM_CH4_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH4_CSR_DIVMODE_MSB 5 -#define PWM_CH4_CSR_DIVMODE_LSB 4 +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) #define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_B_INV // Description : Invert output B -#define PWM_CH4_CSR_B_INV_RESET 0x0 -#define PWM_CH4_CSR_B_INV_BITS 0x00000008 -#define PWM_CH4_CSR_B_INV_MSB 3 -#define PWM_CH4_CSR_B_INV_LSB 3 +#define PWM_CH4_CSR_B_INV_RESET _u(0x0) +#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH4_CSR_B_INV_MSB _u(3) +#define PWM_CH4_CSR_B_INV_LSB _u(3) #define PWM_CH4_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_A_INV // Description : Invert output A -#define PWM_CH4_CSR_A_INV_RESET 0x0 -#define PWM_CH4_CSR_A_INV_BITS 0x00000004 -#define PWM_CH4_CSR_A_INV_MSB 2 -#define PWM_CH4_CSR_A_INV_LSB 2 +#define PWM_CH4_CSR_A_INV_RESET _u(0x0) +#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH4_CSR_A_INV_MSB _u(2) +#define PWM_CH4_CSR_A_INV_LSB _u(2) #define PWM_CH4_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH4_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH4_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH4_CSR_PH_CORRECT_MSB 1 -#define PWM_CH4_CSR_PH_CORRECT_LSB 1 +#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH4_CSR_EN_RESET 0x0 -#define PWM_CH4_CSR_EN_BITS 0x00000001 -#define PWM_CH4_CSR_EN_MSB 0 -#define PWM_CH4_CSR_EN_LSB 0 +#define PWM_CH4_CSR_EN_RESET _u(0x0) +#define PWM_CH4_CSR_EN_BITS _u(0x00000001) +#define PWM_CH4_CSR_EN_MSB _u(0) +#define PWM_CH4_CSR_EN_LSB _u(0) #define PWM_CH4_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH4_DIV_OFFSET 0x00000054 -#define PWM_CH4_DIV_BITS 0x00000fff -#define PWM_CH4_DIV_RESET 0x00000010 +#define PWM_CH4_DIV_OFFSET _u(0x00000054) +#define PWM_CH4_DIV_BITS _u(0x00000fff) +#define PWM_CH4_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_INT // Description : None -#define PWM_CH4_DIV_INT_RESET 0x01 -#define PWM_CH4_DIV_INT_BITS 0x00000ff0 -#define PWM_CH4_DIV_INT_MSB 11 -#define PWM_CH4_DIV_INT_LSB 4 +#define PWM_CH4_DIV_INT_RESET _u(0x01) +#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH4_DIV_INT_MSB _u(11) +#define PWM_CH4_DIV_INT_LSB _u(4) #define PWM_CH4_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_FRAC // Description : None -#define PWM_CH4_DIV_FRAC_RESET 0x0 -#define PWM_CH4_DIV_FRAC_BITS 0x0000000f -#define PWM_CH4_DIV_FRAC_MSB 3 -#define PWM_CH4_DIV_FRAC_LSB 0 +#define PWM_CH4_DIV_FRAC_RESET _u(0x0) +#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH4_DIV_FRAC_MSB _u(3) +#define PWM_CH4_DIV_FRAC_LSB _u(0) #define PWM_CH4_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CTR // Description : Direct access to the PWM counter -#define PWM_CH4_CTR_OFFSET 0x00000058 -#define PWM_CH4_CTR_BITS 0x0000ffff -#define PWM_CH4_CTR_RESET 0x00000000 -#define PWM_CH4_CTR_MSB 15 -#define PWM_CH4_CTR_LSB 0 +#define PWM_CH4_CTR_OFFSET _u(0x00000058) +#define PWM_CH4_CTR_BITS _u(0x0000ffff) +#define PWM_CH4_CTR_RESET _u(0x00000000) +#define PWM_CH4_CTR_MSB _u(15) +#define PWM_CH4_CTR_LSB _u(0) #define PWM_CH4_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CC // Description : Counter compare values -#define PWM_CH4_CC_OFFSET 0x0000005c -#define PWM_CH4_CC_BITS 0xffffffff -#define PWM_CH4_CC_RESET 0x00000000 +#define PWM_CH4_CC_OFFSET _u(0x0000005c) +#define PWM_CH4_CC_BITS _u(0xffffffff) +#define PWM_CH4_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_B // Description : None -#define PWM_CH4_CC_B_RESET 0x0000 -#define PWM_CH4_CC_B_BITS 0xffff0000 -#define PWM_CH4_CC_B_MSB 31 -#define PWM_CH4_CC_B_LSB 16 +#define PWM_CH4_CC_B_RESET _u(0x0000) +#define PWM_CH4_CC_B_BITS _u(0xffff0000) +#define PWM_CH4_CC_B_MSB _u(31) +#define PWM_CH4_CC_B_LSB _u(16) #define PWM_CH4_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_A // Description : None -#define PWM_CH4_CC_A_RESET 0x0000 -#define PWM_CH4_CC_A_BITS 0x0000ffff -#define PWM_CH4_CC_A_MSB 15 -#define PWM_CH4_CC_A_LSB 0 +#define PWM_CH4_CC_A_RESET _u(0x0000) +#define PWM_CH4_CC_A_BITS _u(0x0000ffff) +#define PWM_CH4_CC_A_MSB _u(15) +#define PWM_CH4_CC_A_LSB _u(0) #define PWM_CH4_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_TOP // Description : Counter wrap value -#define PWM_CH4_TOP_OFFSET 0x00000060 -#define PWM_CH4_TOP_BITS 0x0000ffff -#define PWM_CH4_TOP_RESET 0x0000ffff -#define PWM_CH4_TOP_MSB 15 -#define PWM_CH4_TOP_LSB 0 +#define PWM_CH4_TOP_OFFSET _u(0x00000060) +#define PWM_CH4_TOP_BITS _u(0x0000ffff) +#define PWM_CH4_TOP_RESET _u(0x0000ffff) +#define PWM_CH4_TOP_MSB _u(15) +#define PWM_CH4_TOP_LSB _u(0) #define PWM_CH4_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CSR // Description : Control and status register -#define PWM_CH5_CSR_OFFSET 0x00000064 -#define PWM_CH5_CSR_BITS 0x000000ff -#define PWM_CH5_CSR_RESET 0x00000000 +#define PWM_CH5_CSR_OFFSET _u(0x00000064) +#define PWM_CH5_CSR_BITS _u(0x000000ff) +#define PWM_CH5_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -734,10 +734,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH5_CSR_PH_ADV_RESET 0x0 -#define PWM_CH5_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH5_CSR_PH_ADV_MSB 7 -#define PWM_CH5_CSR_PH_ADV_LSB 7 +#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH5_CSR_PH_ADV_MSB _u(7) +#define PWM_CH5_CSR_PH_ADV_LSB _u(7) #define PWM_CH5_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_RET @@ -745,10 +745,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH5_CSR_PH_RET_RESET 0x0 -#define PWM_CH5_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH5_CSR_PH_RET_MSB 6 -#define PWM_CH5_CSR_PH_RET_LSB 6 +#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH5_CSR_PH_RET_MSB _u(6) +#define PWM_CH5_CSR_PH_RET_LSB _u(6) #define PWM_CH5_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE @@ -758,117 +758,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH5_CSR_DIVMODE_RESET 0x0 -#define PWM_CH5_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH5_CSR_DIVMODE_MSB 5 -#define PWM_CH5_CSR_DIVMODE_LSB 4 +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) #define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_B_INV // Description : Invert output B -#define PWM_CH5_CSR_B_INV_RESET 0x0 -#define PWM_CH5_CSR_B_INV_BITS 0x00000008 -#define PWM_CH5_CSR_B_INV_MSB 3 -#define PWM_CH5_CSR_B_INV_LSB 3 +#define PWM_CH5_CSR_B_INV_RESET _u(0x0) +#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH5_CSR_B_INV_MSB _u(3) +#define PWM_CH5_CSR_B_INV_LSB _u(3) #define PWM_CH5_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_A_INV // Description : Invert output A -#define PWM_CH5_CSR_A_INV_RESET 0x0 -#define PWM_CH5_CSR_A_INV_BITS 0x00000004 -#define PWM_CH5_CSR_A_INV_MSB 2 -#define PWM_CH5_CSR_A_INV_LSB 2 +#define PWM_CH5_CSR_A_INV_RESET _u(0x0) +#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH5_CSR_A_INV_MSB _u(2) +#define PWM_CH5_CSR_A_INV_LSB _u(2) #define PWM_CH5_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH5_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH5_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH5_CSR_PH_CORRECT_MSB 1 -#define PWM_CH5_CSR_PH_CORRECT_LSB 1 +#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH5_CSR_EN_RESET 0x0 -#define PWM_CH5_CSR_EN_BITS 0x00000001 -#define PWM_CH5_CSR_EN_MSB 0 -#define PWM_CH5_CSR_EN_LSB 0 +#define PWM_CH5_CSR_EN_RESET _u(0x0) +#define PWM_CH5_CSR_EN_BITS _u(0x00000001) +#define PWM_CH5_CSR_EN_MSB _u(0) +#define PWM_CH5_CSR_EN_LSB _u(0) #define PWM_CH5_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH5_DIV_OFFSET 0x00000068 -#define PWM_CH5_DIV_BITS 0x00000fff -#define PWM_CH5_DIV_RESET 0x00000010 +#define PWM_CH5_DIV_OFFSET _u(0x00000068) +#define PWM_CH5_DIV_BITS _u(0x00000fff) +#define PWM_CH5_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_INT // Description : None -#define PWM_CH5_DIV_INT_RESET 0x01 -#define PWM_CH5_DIV_INT_BITS 0x00000ff0 -#define PWM_CH5_DIV_INT_MSB 11 -#define PWM_CH5_DIV_INT_LSB 4 +#define PWM_CH5_DIV_INT_RESET _u(0x01) +#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH5_DIV_INT_MSB _u(11) +#define PWM_CH5_DIV_INT_LSB _u(4) #define PWM_CH5_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_FRAC // Description : None -#define PWM_CH5_DIV_FRAC_RESET 0x0 -#define PWM_CH5_DIV_FRAC_BITS 0x0000000f -#define PWM_CH5_DIV_FRAC_MSB 3 -#define PWM_CH5_DIV_FRAC_LSB 0 +#define PWM_CH5_DIV_FRAC_RESET _u(0x0) +#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH5_DIV_FRAC_MSB _u(3) +#define PWM_CH5_DIV_FRAC_LSB _u(0) #define PWM_CH5_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CTR // Description : Direct access to the PWM counter -#define PWM_CH5_CTR_OFFSET 0x0000006c -#define PWM_CH5_CTR_BITS 0x0000ffff -#define PWM_CH5_CTR_RESET 0x00000000 -#define PWM_CH5_CTR_MSB 15 -#define PWM_CH5_CTR_LSB 0 +#define PWM_CH5_CTR_OFFSET _u(0x0000006c) +#define PWM_CH5_CTR_BITS _u(0x0000ffff) +#define PWM_CH5_CTR_RESET _u(0x00000000) +#define PWM_CH5_CTR_MSB _u(15) +#define PWM_CH5_CTR_LSB _u(0) #define PWM_CH5_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CC // Description : Counter compare values -#define PWM_CH5_CC_OFFSET 0x00000070 -#define PWM_CH5_CC_BITS 0xffffffff -#define PWM_CH5_CC_RESET 0x00000000 +#define PWM_CH5_CC_OFFSET _u(0x00000070) +#define PWM_CH5_CC_BITS _u(0xffffffff) +#define PWM_CH5_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_B // Description : None -#define PWM_CH5_CC_B_RESET 0x0000 -#define PWM_CH5_CC_B_BITS 0xffff0000 -#define PWM_CH5_CC_B_MSB 31 -#define PWM_CH5_CC_B_LSB 16 +#define PWM_CH5_CC_B_RESET _u(0x0000) +#define PWM_CH5_CC_B_BITS _u(0xffff0000) +#define PWM_CH5_CC_B_MSB _u(31) +#define PWM_CH5_CC_B_LSB _u(16) #define PWM_CH5_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_A // Description : None -#define PWM_CH5_CC_A_RESET 0x0000 -#define PWM_CH5_CC_A_BITS 0x0000ffff -#define PWM_CH5_CC_A_MSB 15 -#define PWM_CH5_CC_A_LSB 0 +#define PWM_CH5_CC_A_RESET _u(0x0000) +#define PWM_CH5_CC_A_BITS _u(0x0000ffff) +#define PWM_CH5_CC_A_MSB _u(15) +#define PWM_CH5_CC_A_LSB _u(0) #define PWM_CH5_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_TOP // Description : Counter wrap value -#define PWM_CH5_TOP_OFFSET 0x00000074 -#define PWM_CH5_TOP_BITS 0x0000ffff -#define PWM_CH5_TOP_RESET 0x0000ffff -#define PWM_CH5_TOP_MSB 15 -#define PWM_CH5_TOP_LSB 0 +#define PWM_CH5_TOP_OFFSET _u(0x00000074) +#define PWM_CH5_TOP_BITS _u(0x0000ffff) +#define PWM_CH5_TOP_RESET _u(0x0000ffff) +#define PWM_CH5_TOP_MSB _u(15) +#define PWM_CH5_TOP_LSB _u(0) #define PWM_CH5_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CSR // Description : Control and status register -#define PWM_CH6_CSR_OFFSET 0x00000078 -#define PWM_CH6_CSR_BITS 0x000000ff -#define PWM_CH6_CSR_RESET 0x00000000 +#define PWM_CH6_CSR_OFFSET _u(0x00000078) +#define PWM_CH6_CSR_BITS _u(0x000000ff) +#define PWM_CH6_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -876,10 +876,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH6_CSR_PH_ADV_RESET 0x0 -#define PWM_CH6_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH6_CSR_PH_ADV_MSB 7 -#define PWM_CH6_CSR_PH_ADV_LSB 7 +#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH6_CSR_PH_ADV_MSB _u(7) +#define PWM_CH6_CSR_PH_ADV_LSB _u(7) #define PWM_CH6_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_RET @@ -887,10 +887,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH6_CSR_PH_RET_RESET 0x0 -#define PWM_CH6_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH6_CSR_PH_RET_MSB 6 -#define PWM_CH6_CSR_PH_RET_LSB 6 +#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH6_CSR_PH_RET_MSB _u(6) +#define PWM_CH6_CSR_PH_RET_LSB _u(6) #define PWM_CH6_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE @@ -900,117 +900,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH6_CSR_DIVMODE_RESET 0x0 -#define PWM_CH6_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH6_CSR_DIVMODE_MSB 5 -#define PWM_CH6_CSR_DIVMODE_LSB 4 +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) #define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_B_INV // Description : Invert output B -#define PWM_CH6_CSR_B_INV_RESET 0x0 -#define PWM_CH6_CSR_B_INV_BITS 0x00000008 -#define PWM_CH6_CSR_B_INV_MSB 3 -#define PWM_CH6_CSR_B_INV_LSB 3 +#define PWM_CH6_CSR_B_INV_RESET _u(0x0) +#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH6_CSR_B_INV_MSB _u(3) +#define PWM_CH6_CSR_B_INV_LSB _u(3) #define PWM_CH6_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_A_INV // Description : Invert output A -#define PWM_CH6_CSR_A_INV_RESET 0x0 -#define PWM_CH6_CSR_A_INV_BITS 0x00000004 -#define PWM_CH6_CSR_A_INV_MSB 2 -#define PWM_CH6_CSR_A_INV_LSB 2 +#define PWM_CH6_CSR_A_INV_RESET _u(0x0) +#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH6_CSR_A_INV_MSB _u(2) +#define PWM_CH6_CSR_A_INV_LSB _u(2) #define PWM_CH6_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH6_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH6_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH6_CSR_PH_CORRECT_MSB 1 -#define PWM_CH6_CSR_PH_CORRECT_LSB 1 +#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH6_CSR_EN_RESET 0x0 -#define PWM_CH6_CSR_EN_BITS 0x00000001 -#define PWM_CH6_CSR_EN_MSB 0 -#define PWM_CH6_CSR_EN_LSB 0 +#define PWM_CH6_CSR_EN_RESET _u(0x0) +#define PWM_CH6_CSR_EN_BITS _u(0x00000001) +#define PWM_CH6_CSR_EN_MSB _u(0) +#define PWM_CH6_CSR_EN_LSB _u(0) #define PWM_CH6_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH6_DIV_OFFSET 0x0000007c -#define PWM_CH6_DIV_BITS 0x00000fff -#define PWM_CH6_DIV_RESET 0x00000010 +#define PWM_CH6_DIV_OFFSET _u(0x0000007c) +#define PWM_CH6_DIV_BITS _u(0x00000fff) +#define PWM_CH6_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_INT // Description : None -#define PWM_CH6_DIV_INT_RESET 0x01 -#define PWM_CH6_DIV_INT_BITS 0x00000ff0 -#define PWM_CH6_DIV_INT_MSB 11 -#define PWM_CH6_DIV_INT_LSB 4 +#define PWM_CH6_DIV_INT_RESET _u(0x01) +#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH6_DIV_INT_MSB _u(11) +#define PWM_CH6_DIV_INT_LSB _u(4) #define PWM_CH6_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_FRAC // Description : None -#define PWM_CH6_DIV_FRAC_RESET 0x0 -#define PWM_CH6_DIV_FRAC_BITS 0x0000000f -#define PWM_CH6_DIV_FRAC_MSB 3 -#define PWM_CH6_DIV_FRAC_LSB 0 +#define PWM_CH6_DIV_FRAC_RESET _u(0x0) +#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH6_DIV_FRAC_MSB _u(3) +#define PWM_CH6_DIV_FRAC_LSB _u(0) #define PWM_CH6_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CTR // Description : Direct access to the PWM counter -#define PWM_CH6_CTR_OFFSET 0x00000080 -#define PWM_CH6_CTR_BITS 0x0000ffff -#define PWM_CH6_CTR_RESET 0x00000000 -#define PWM_CH6_CTR_MSB 15 -#define PWM_CH6_CTR_LSB 0 +#define PWM_CH6_CTR_OFFSET _u(0x00000080) +#define PWM_CH6_CTR_BITS _u(0x0000ffff) +#define PWM_CH6_CTR_RESET _u(0x00000000) +#define PWM_CH6_CTR_MSB _u(15) +#define PWM_CH6_CTR_LSB _u(0) #define PWM_CH6_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CC // Description : Counter compare values -#define PWM_CH6_CC_OFFSET 0x00000084 -#define PWM_CH6_CC_BITS 0xffffffff -#define PWM_CH6_CC_RESET 0x00000000 +#define PWM_CH6_CC_OFFSET _u(0x00000084) +#define PWM_CH6_CC_BITS _u(0xffffffff) +#define PWM_CH6_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_B // Description : None -#define PWM_CH6_CC_B_RESET 0x0000 -#define PWM_CH6_CC_B_BITS 0xffff0000 -#define PWM_CH6_CC_B_MSB 31 -#define PWM_CH6_CC_B_LSB 16 +#define PWM_CH6_CC_B_RESET _u(0x0000) +#define PWM_CH6_CC_B_BITS _u(0xffff0000) +#define PWM_CH6_CC_B_MSB _u(31) +#define PWM_CH6_CC_B_LSB _u(16) #define PWM_CH6_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_A // Description : None -#define PWM_CH6_CC_A_RESET 0x0000 -#define PWM_CH6_CC_A_BITS 0x0000ffff -#define PWM_CH6_CC_A_MSB 15 -#define PWM_CH6_CC_A_LSB 0 +#define PWM_CH6_CC_A_RESET _u(0x0000) +#define PWM_CH6_CC_A_BITS _u(0x0000ffff) +#define PWM_CH6_CC_A_MSB _u(15) +#define PWM_CH6_CC_A_LSB _u(0) #define PWM_CH6_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_TOP // Description : Counter wrap value -#define PWM_CH6_TOP_OFFSET 0x00000088 -#define PWM_CH6_TOP_BITS 0x0000ffff -#define PWM_CH6_TOP_RESET 0x0000ffff -#define PWM_CH6_TOP_MSB 15 -#define PWM_CH6_TOP_LSB 0 +#define PWM_CH6_TOP_OFFSET _u(0x00000088) +#define PWM_CH6_TOP_BITS _u(0x0000ffff) +#define PWM_CH6_TOP_RESET _u(0x0000ffff) +#define PWM_CH6_TOP_MSB _u(15) +#define PWM_CH6_TOP_LSB _u(0) #define PWM_CH6_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CSR // Description : Control and status register -#define PWM_CH7_CSR_OFFSET 0x0000008c -#define PWM_CH7_CSR_BITS 0x000000ff -#define PWM_CH7_CSR_RESET 0x00000000 +#define PWM_CH7_CSR_OFFSET _u(0x0000008c) +#define PWM_CH7_CSR_BITS _u(0x000000ff) +#define PWM_CH7_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -1018,10 +1018,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH7_CSR_PH_ADV_RESET 0x0 -#define PWM_CH7_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH7_CSR_PH_ADV_MSB 7 -#define PWM_CH7_CSR_PH_ADV_LSB 7 +#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH7_CSR_PH_ADV_MSB _u(7) +#define PWM_CH7_CSR_PH_ADV_LSB _u(7) #define PWM_CH7_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_RET @@ -1029,10 +1029,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH7_CSR_PH_RET_RESET 0x0 -#define PWM_CH7_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH7_CSR_PH_RET_MSB 6 -#define PWM_CH7_CSR_PH_RET_LSB 6 +#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH7_CSR_PH_RET_MSB _u(6) +#define PWM_CH7_CSR_PH_RET_LSB _u(6) #define PWM_CH7_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE @@ -1042,110 +1042,110 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH7_CSR_DIVMODE_RESET 0x0 -#define PWM_CH7_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH7_CSR_DIVMODE_MSB 5 -#define PWM_CH7_CSR_DIVMODE_LSB 4 +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) #define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_B_INV // Description : Invert output B -#define PWM_CH7_CSR_B_INV_RESET 0x0 -#define PWM_CH7_CSR_B_INV_BITS 0x00000008 -#define PWM_CH7_CSR_B_INV_MSB 3 -#define PWM_CH7_CSR_B_INV_LSB 3 +#define PWM_CH7_CSR_B_INV_RESET _u(0x0) +#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH7_CSR_B_INV_MSB _u(3) +#define PWM_CH7_CSR_B_INV_LSB _u(3) #define PWM_CH7_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_A_INV // Description : Invert output A -#define PWM_CH7_CSR_A_INV_RESET 0x0 -#define PWM_CH7_CSR_A_INV_BITS 0x00000004 -#define PWM_CH7_CSR_A_INV_MSB 2 -#define PWM_CH7_CSR_A_INV_LSB 2 +#define PWM_CH7_CSR_A_INV_RESET _u(0x0) +#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH7_CSR_A_INV_MSB _u(2) +#define PWM_CH7_CSR_A_INV_LSB _u(2) #define PWM_CH7_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH7_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH7_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH7_CSR_PH_CORRECT_MSB 1 -#define PWM_CH7_CSR_PH_CORRECT_LSB 1 +#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH7_CSR_EN_RESET 0x0 -#define PWM_CH7_CSR_EN_BITS 0x00000001 -#define PWM_CH7_CSR_EN_MSB 0 -#define PWM_CH7_CSR_EN_LSB 0 +#define PWM_CH7_CSR_EN_RESET _u(0x0) +#define PWM_CH7_CSR_EN_BITS _u(0x00000001) +#define PWM_CH7_CSR_EN_MSB _u(0) +#define PWM_CH7_CSR_EN_LSB _u(0) #define PWM_CH7_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH7_DIV_OFFSET 0x00000090 -#define PWM_CH7_DIV_BITS 0x00000fff -#define PWM_CH7_DIV_RESET 0x00000010 +#define PWM_CH7_DIV_OFFSET _u(0x00000090) +#define PWM_CH7_DIV_BITS _u(0x00000fff) +#define PWM_CH7_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_INT // Description : None -#define PWM_CH7_DIV_INT_RESET 0x01 -#define PWM_CH7_DIV_INT_BITS 0x00000ff0 -#define PWM_CH7_DIV_INT_MSB 11 -#define PWM_CH7_DIV_INT_LSB 4 +#define PWM_CH7_DIV_INT_RESET _u(0x01) +#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH7_DIV_INT_MSB _u(11) +#define PWM_CH7_DIV_INT_LSB _u(4) #define PWM_CH7_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_FRAC // Description : None -#define PWM_CH7_DIV_FRAC_RESET 0x0 -#define PWM_CH7_DIV_FRAC_BITS 0x0000000f -#define PWM_CH7_DIV_FRAC_MSB 3 -#define PWM_CH7_DIV_FRAC_LSB 0 +#define PWM_CH7_DIV_FRAC_RESET _u(0x0) +#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH7_DIV_FRAC_MSB _u(3) +#define PWM_CH7_DIV_FRAC_LSB _u(0) #define PWM_CH7_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CTR // Description : Direct access to the PWM counter -#define PWM_CH7_CTR_OFFSET 0x00000094 -#define PWM_CH7_CTR_BITS 0x0000ffff -#define PWM_CH7_CTR_RESET 0x00000000 -#define PWM_CH7_CTR_MSB 15 -#define PWM_CH7_CTR_LSB 0 +#define PWM_CH7_CTR_OFFSET _u(0x00000094) +#define PWM_CH7_CTR_BITS _u(0x0000ffff) +#define PWM_CH7_CTR_RESET _u(0x00000000) +#define PWM_CH7_CTR_MSB _u(15) +#define PWM_CH7_CTR_LSB _u(0) #define PWM_CH7_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CC // Description : Counter compare values -#define PWM_CH7_CC_OFFSET 0x00000098 -#define PWM_CH7_CC_BITS 0xffffffff -#define PWM_CH7_CC_RESET 0x00000000 +#define PWM_CH7_CC_OFFSET _u(0x00000098) +#define PWM_CH7_CC_BITS _u(0xffffffff) +#define PWM_CH7_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_B // Description : None -#define PWM_CH7_CC_B_RESET 0x0000 -#define PWM_CH7_CC_B_BITS 0xffff0000 -#define PWM_CH7_CC_B_MSB 31 -#define PWM_CH7_CC_B_LSB 16 +#define PWM_CH7_CC_B_RESET _u(0x0000) +#define PWM_CH7_CC_B_BITS _u(0xffff0000) +#define PWM_CH7_CC_B_MSB _u(31) +#define PWM_CH7_CC_B_LSB _u(16) #define PWM_CH7_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_A // Description : None -#define PWM_CH7_CC_A_RESET 0x0000 -#define PWM_CH7_CC_A_BITS 0x0000ffff -#define PWM_CH7_CC_A_MSB 15 -#define PWM_CH7_CC_A_LSB 0 +#define PWM_CH7_CC_A_RESET _u(0x0000) +#define PWM_CH7_CC_A_BITS _u(0x0000ffff) +#define PWM_CH7_CC_A_MSB _u(15) +#define PWM_CH7_CC_A_LSB _u(0) #define PWM_CH7_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_TOP // Description : Counter wrap value -#define PWM_CH7_TOP_OFFSET 0x0000009c -#define PWM_CH7_TOP_BITS 0x0000ffff -#define PWM_CH7_TOP_RESET 0x0000ffff -#define PWM_CH7_TOP_MSB 15 -#define PWM_CH7_TOP_LSB 0 +#define PWM_CH7_TOP_OFFSET _u(0x0000009c) +#define PWM_CH7_TOP_BITS _u(0x0000ffff) +#define PWM_CH7_TOP_RESET _u(0x0000ffff) +#define PWM_CH7_TOP_MSB _u(15) +#define PWM_CH7_TOP_LSB _u(0) #define PWM_CH7_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_EN @@ -1154,352 +1154,352 @@ // or disabled simultaneously, so they can run in perfect sync. // For each channel, there is only one physical EN register bit, // which can be accessed through here or CHx_CSR. -#define PWM_EN_OFFSET 0x000000a0 -#define PWM_EN_BITS 0x000000ff -#define PWM_EN_RESET 0x00000000 +#define PWM_EN_OFFSET _u(0x000000a0) +#define PWM_EN_BITS _u(0x000000ff) +#define PWM_EN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_EN_CH7 // Description : None -#define PWM_EN_CH7_RESET 0x0 -#define PWM_EN_CH7_BITS 0x00000080 -#define PWM_EN_CH7_MSB 7 -#define PWM_EN_CH7_LSB 7 +#define PWM_EN_CH7_RESET _u(0x0) +#define PWM_EN_CH7_BITS _u(0x00000080) +#define PWM_EN_CH7_MSB _u(7) +#define PWM_EN_CH7_LSB _u(7) #define PWM_EN_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH6 // Description : None -#define PWM_EN_CH6_RESET 0x0 -#define PWM_EN_CH6_BITS 0x00000040 -#define PWM_EN_CH6_MSB 6 -#define PWM_EN_CH6_LSB 6 +#define PWM_EN_CH6_RESET _u(0x0) +#define PWM_EN_CH6_BITS _u(0x00000040) +#define PWM_EN_CH6_MSB _u(6) +#define PWM_EN_CH6_LSB _u(6) #define PWM_EN_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH5 // Description : None -#define PWM_EN_CH5_RESET 0x0 -#define PWM_EN_CH5_BITS 0x00000020 -#define PWM_EN_CH5_MSB 5 -#define PWM_EN_CH5_LSB 5 +#define PWM_EN_CH5_RESET _u(0x0) +#define PWM_EN_CH5_BITS _u(0x00000020) +#define PWM_EN_CH5_MSB _u(5) +#define PWM_EN_CH5_LSB _u(5) #define PWM_EN_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH4 // Description : None -#define PWM_EN_CH4_RESET 0x0 -#define PWM_EN_CH4_BITS 0x00000010 -#define PWM_EN_CH4_MSB 4 -#define PWM_EN_CH4_LSB 4 +#define PWM_EN_CH4_RESET _u(0x0) +#define PWM_EN_CH4_BITS _u(0x00000010) +#define PWM_EN_CH4_MSB _u(4) +#define PWM_EN_CH4_LSB _u(4) #define PWM_EN_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH3 // Description : None -#define PWM_EN_CH3_RESET 0x0 -#define PWM_EN_CH3_BITS 0x00000008 -#define PWM_EN_CH3_MSB 3 -#define PWM_EN_CH3_LSB 3 +#define PWM_EN_CH3_RESET _u(0x0) +#define PWM_EN_CH3_BITS _u(0x00000008) +#define PWM_EN_CH3_MSB _u(3) +#define PWM_EN_CH3_LSB _u(3) #define PWM_EN_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH2 // Description : None -#define PWM_EN_CH2_RESET 0x0 -#define PWM_EN_CH2_BITS 0x00000004 -#define PWM_EN_CH2_MSB 2 -#define PWM_EN_CH2_LSB 2 +#define PWM_EN_CH2_RESET _u(0x0) +#define PWM_EN_CH2_BITS _u(0x00000004) +#define PWM_EN_CH2_MSB _u(2) +#define PWM_EN_CH2_LSB _u(2) #define PWM_EN_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH1 // Description : None -#define PWM_EN_CH1_RESET 0x0 -#define PWM_EN_CH1_BITS 0x00000002 -#define PWM_EN_CH1_MSB 1 -#define PWM_EN_CH1_LSB 1 +#define PWM_EN_CH1_RESET _u(0x0) +#define PWM_EN_CH1_BITS _u(0x00000002) +#define PWM_EN_CH1_MSB _u(1) +#define PWM_EN_CH1_LSB _u(1) #define PWM_EN_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH0 // Description : None -#define PWM_EN_CH0_RESET 0x0 -#define PWM_EN_CH0_BITS 0x00000001 -#define PWM_EN_CH0_MSB 0 -#define PWM_EN_CH0_LSB 0 +#define PWM_EN_CH0_RESET _u(0x0) +#define PWM_EN_CH0_BITS _u(0x00000001) +#define PWM_EN_CH0_MSB _u(0) +#define PWM_EN_CH0_LSB _u(0) #define PWM_EN_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTR // Description : Raw Interrupts -#define PWM_INTR_OFFSET 0x000000a4 -#define PWM_INTR_BITS 0x000000ff -#define PWM_INTR_RESET 0x00000000 +#define PWM_INTR_OFFSET _u(0x000000a4) +#define PWM_INTR_BITS _u(0x000000ff) +#define PWM_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH7 // Description : None -#define PWM_INTR_CH7_RESET 0x0 -#define PWM_INTR_CH7_BITS 0x00000080 -#define PWM_INTR_CH7_MSB 7 -#define PWM_INTR_CH7_LSB 7 +#define PWM_INTR_CH7_RESET _u(0x0) +#define PWM_INTR_CH7_BITS _u(0x00000080) +#define PWM_INTR_CH7_MSB _u(7) +#define PWM_INTR_CH7_LSB _u(7) #define PWM_INTR_CH7_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH6 // Description : None -#define PWM_INTR_CH6_RESET 0x0 -#define PWM_INTR_CH6_BITS 0x00000040 -#define PWM_INTR_CH6_MSB 6 -#define PWM_INTR_CH6_LSB 6 +#define PWM_INTR_CH6_RESET _u(0x0) +#define PWM_INTR_CH6_BITS _u(0x00000040) +#define PWM_INTR_CH6_MSB _u(6) +#define PWM_INTR_CH6_LSB _u(6) #define PWM_INTR_CH6_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH5 // Description : None -#define PWM_INTR_CH5_RESET 0x0 -#define PWM_INTR_CH5_BITS 0x00000020 -#define PWM_INTR_CH5_MSB 5 -#define PWM_INTR_CH5_LSB 5 +#define PWM_INTR_CH5_RESET _u(0x0) +#define PWM_INTR_CH5_BITS _u(0x00000020) +#define PWM_INTR_CH5_MSB _u(5) +#define PWM_INTR_CH5_LSB _u(5) #define PWM_INTR_CH5_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH4 // Description : None -#define PWM_INTR_CH4_RESET 0x0 -#define PWM_INTR_CH4_BITS 0x00000010 -#define PWM_INTR_CH4_MSB 4 -#define PWM_INTR_CH4_LSB 4 +#define PWM_INTR_CH4_RESET _u(0x0) +#define PWM_INTR_CH4_BITS _u(0x00000010) +#define PWM_INTR_CH4_MSB _u(4) +#define PWM_INTR_CH4_LSB _u(4) #define PWM_INTR_CH4_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH3 // Description : None -#define PWM_INTR_CH3_RESET 0x0 -#define PWM_INTR_CH3_BITS 0x00000008 -#define PWM_INTR_CH3_MSB 3 -#define PWM_INTR_CH3_LSB 3 +#define PWM_INTR_CH3_RESET _u(0x0) +#define PWM_INTR_CH3_BITS _u(0x00000008) +#define PWM_INTR_CH3_MSB _u(3) +#define PWM_INTR_CH3_LSB _u(3) #define PWM_INTR_CH3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH2 // Description : None -#define PWM_INTR_CH2_RESET 0x0 -#define PWM_INTR_CH2_BITS 0x00000004 -#define PWM_INTR_CH2_MSB 2 -#define PWM_INTR_CH2_LSB 2 +#define PWM_INTR_CH2_RESET _u(0x0) +#define PWM_INTR_CH2_BITS _u(0x00000004) +#define PWM_INTR_CH2_MSB _u(2) +#define PWM_INTR_CH2_LSB _u(2) #define PWM_INTR_CH2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH1 // Description : None -#define PWM_INTR_CH1_RESET 0x0 -#define PWM_INTR_CH1_BITS 0x00000002 -#define PWM_INTR_CH1_MSB 1 -#define PWM_INTR_CH1_LSB 1 +#define PWM_INTR_CH1_RESET _u(0x0) +#define PWM_INTR_CH1_BITS _u(0x00000002) +#define PWM_INTR_CH1_MSB _u(1) +#define PWM_INTR_CH1_LSB _u(1) #define PWM_INTR_CH1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH0 // Description : None -#define PWM_INTR_CH0_RESET 0x0 -#define PWM_INTR_CH0_BITS 0x00000001 -#define PWM_INTR_CH0_MSB 0 -#define PWM_INTR_CH0_LSB 0 +#define PWM_INTR_CH0_RESET _u(0x0) +#define PWM_INTR_CH0_BITS _u(0x00000001) +#define PWM_INTR_CH0_MSB _u(0) +#define PWM_INTR_CH0_LSB _u(0) #define PWM_INTR_CH0_ACCESS "WC" // ============================================================================= // Register : PWM_INTE // Description : Interrupt Enable -#define PWM_INTE_OFFSET 0x000000a8 -#define PWM_INTE_BITS 0x000000ff -#define PWM_INTE_RESET 0x00000000 +#define PWM_INTE_OFFSET _u(0x000000a8) +#define PWM_INTE_BITS _u(0x000000ff) +#define PWM_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH7 // Description : None -#define PWM_INTE_CH7_RESET 0x0 -#define PWM_INTE_CH7_BITS 0x00000080 -#define PWM_INTE_CH7_MSB 7 -#define PWM_INTE_CH7_LSB 7 +#define PWM_INTE_CH7_RESET _u(0x0) +#define PWM_INTE_CH7_BITS _u(0x00000080) +#define PWM_INTE_CH7_MSB _u(7) +#define PWM_INTE_CH7_LSB _u(7) #define PWM_INTE_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH6 // Description : None -#define PWM_INTE_CH6_RESET 0x0 -#define PWM_INTE_CH6_BITS 0x00000040 -#define PWM_INTE_CH6_MSB 6 -#define PWM_INTE_CH6_LSB 6 +#define PWM_INTE_CH6_RESET _u(0x0) +#define PWM_INTE_CH6_BITS _u(0x00000040) +#define PWM_INTE_CH6_MSB _u(6) +#define PWM_INTE_CH6_LSB _u(6) #define PWM_INTE_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH5 // Description : None -#define PWM_INTE_CH5_RESET 0x0 -#define PWM_INTE_CH5_BITS 0x00000020 -#define PWM_INTE_CH5_MSB 5 -#define PWM_INTE_CH5_LSB 5 +#define PWM_INTE_CH5_RESET _u(0x0) +#define PWM_INTE_CH5_BITS _u(0x00000020) +#define PWM_INTE_CH5_MSB _u(5) +#define PWM_INTE_CH5_LSB _u(5) #define PWM_INTE_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH4 // Description : None -#define PWM_INTE_CH4_RESET 0x0 -#define PWM_INTE_CH4_BITS 0x00000010 -#define PWM_INTE_CH4_MSB 4 -#define PWM_INTE_CH4_LSB 4 +#define PWM_INTE_CH4_RESET _u(0x0) +#define PWM_INTE_CH4_BITS _u(0x00000010) +#define PWM_INTE_CH4_MSB _u(4) +#define PWM_INTE_CH4_LSB _u(4) #define PWM_INTE_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH3 // Description : None -#define PWM_INTE_CH3_RESET 0x0 -#define PWM_INTE_CH3_BITS 0x00000008 -#define PWM_INTE_CH3_MSB 3 -#define PWM_INTE_CH3_LSB 3 +#define PWM_INTE_CH3_RESET _u(0x0) +#define PWM_INTE_CH3_BITS _u(0x00000008) +#define PWM_INTE_CH3_MSB _u(3) +#define PWM_INTE_CH3_LSB _u(3) #define PWM_INTE_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH2 // Description : None -#define PWM_INTE_CH2_RESET 0x0 -#define PWM_INTE_CH2_BITS 0x00000004 -#define PWM_INTE_CH2_MSB 2 -#define PWM_INTE_CH2_LSB 2 +#define PWM_INTE_CH2_RESET _u(0x0) +#define PWM_INTE_CH2_BITS _u(0x00000004) +#define PWM_INTE_CH2_MSB _u(2) +#define PWM_INTE_CH2_LSB _u(2) #define PWM_INTE_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH1 // Description : None -#define PWM_INTE_CH1_RESET 0x0 -#define PWM_INTE_CH1_BITS 0x00000002 -#define PWM_INTE_CH1_MSB 1 -#define PWM_INTE_CH1_LSB 1 +#define PWM_INTE_CH1_RESET _u(0x0) +#define PWM_INTE_CH1_BITS _u(0x00000002) +#define PWM_INTE_CH1_MSB _u(1) +#define PWM_INTE_CH1_LSB _u(1) #define PWM_INTE_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH0 // Description : None -#define PWM_INTE_CH0_RESET 0x0 -#define PWM_INTE_CH0_BITS 0x00000001 -#define PWM_INTE_CH0_MSB 0 -#define PWM_INTE_CH0_LSB 0 +#define PWM_INTE_CH0_RESET _u(0x0) +#define PWM_INTE_CH0_BITS _u(0x00000001) +#define PWM_INTE_CH0_MSB _u(0) +#define PWM_INTE_CH0_LSB _u(0) #define PWM_INTE_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTF // Description : Interrupt Force -#define PWM_INTF_OFFSET 0x000000ac -#define PWM_INTF_BITS 0x000000ff -#define PWM_INTF_RESET 0x00000000 +#define PWM_INTF_OFFSET _u(0x000000ac) +#define PWM_INTF_BITS _u(0x000000ff) +#define PWM_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH7 // Description : None -#define PWM_INTF_CH7_RESET 0x0 -#define PWM_INTF_CH7_BITS 0x00000080 -#define PWM_INTF_CH7_MSB 7 -#define PWM_INTF_CH7_LSB 7 +#define PWM_INTF_CH7_RESET _u(0x0) +#define PWM_INTF_CH7_BITS _u(0x00000080) +#define PWM_INTF_CH7_MSB _u(7) +#define PWM_INTF_CH7_LSB _u(7) #define PWM_INTF_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH6 // Description : None -#define PWM_INTF_CH6_RESET 0x0 -#define PWM_INTF_CH6_BITS 0x00000040 -#define PWM_INTF_CH6_MSB 6 -#define PWM_INTF_CH6_LSB 6 +#define PWM_INTF_CH6_RESET _u(0x0) +#define PWM_INTF_CH6_BITS _u(0x00000040) +#define PWM_INTF_CH6_MSB _u(6) +#define PWM_INTF_CH6_LSB _u(6) #define PWM_INTF_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH5 // Description : None -#define PWM_INTF_CH5_RESET 0x0 -#define PWM_INTF_CH5_BITS 0x00000020 -#define PWM_INTF_CH5_MSB 5 -#define PWM_INTF_CH5_LSB 5 +#define PWM_INTF_CH5_RESET _u(0x0) +#define PWM_INTF_CH5_BITS _u(0x00000020) +#define PWM_INTF_CH5_MSB _u(5) +#define PWM_INTF_CH5_LSB _u(5) #define PWM_INTF_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH4 // Description : None -#define PWM_INTF_CH4_RESET 0x0 -#define PWM_INTF_CH4_BITS 0x00000010 -#define PWM_INTF_CH4_MSB 4 -#define PWM_INTF_CH4_LSB 4 +#define PWM_INTF_CH4_RESET _u(0x0) +#define PWM_INTF_CH4_BITS _u(0x00000010) +#define PWM_INTF_CH4_MSB _u(4) +#define PWM_INTF_CH4_LSB _u(4) #define PWM_INTF_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH3 // Description : None -#define PWM_INTF_CH3_RESET 0x0 -#define PWM_INTF_CH3_BITS 0x00000008 -#define PWM_INTF_CH3_MSB 3 -#define PWM_INTF_CH3_LSB 3 +#define PWM_INTF_CH3_RESET _u(0x0) +#define PWM_INTF_CH3_BITS _u(0x00000008) +#define PWM_INTF_CH3_MSB _u(3) +#define PWM_INTF_CH3_LSB _u(3) #define PWM_INTF_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH2 // Description : None -#define PWM_INTF_CH2_RESET 0x0 -#define PWM_INTF_CH2_BITS 0x00000004 -#define PWM_INTF_CH2_MSB 2 -#define PWM_INTF_CH2_LSB 2 +#define PWM_INTF_CH2_RESET _u(0x0) +#define PWM_INTF_CH2_BITS _u(0x00000004) +#define PWM_INTF_CH2_MSB _u(2) +#define PWM_INTF_CH2_LSB _u(2) #define PWM_INTF_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH1 // Description : None -#define PWM_INTF_CH1_RESET 0x0 -#define PWM_INTF_CH1_BITS 0x00000002 -#define PWM_INTF_CH1_MSB 1 -#define PWM_INTF_CH1_LSB 1 +#define PWM_INTF_CH1_RESET _u(0x0) +#define PWM_INTF_CH1_BITS _u(0x00000002) +#define PWM_INTF_CH1_MSB _u(1) +#define PWM_INTF_CH1_LSB _u(1) #define PWM_INTF_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH0 // Description : None -#define PWM_INTF_CH0_RESET 0x0 -#define PWM_INTF_CH0_BITS 0x00000001 -#define PWM_INTF_CH0_MSB 0 -#define PWM_INTF_CH0_LSB 0 +#define PWM_INTF_CH0_RESET _u(0x0) +#define PWM_INTF_CH0_BITS _u(0x00000001) +#define PWM_INTF_CH0_MSB _u(0) +#define PWM_INTF_CH0_LSB _u(0) #define PWM_INTF_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTS // Description : Interrupt status after masking & forcing -#define PWM_INTS_OFFSET 0x000000b0 -#define PWM_INTS_BITS 0x000000ff -#define PWM_INTS_RESET 0x00000000 +#define PWM_INTS_OFFSET _u(0x000000b0) +#define PWM_INTS_BITS _u(0x000000ff) +#define PWM_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH7 // Description : None -#define PWM_INTS_CH7_RESET 0x0 -#define PWM_INTS_CH7_BITS 0x00000080 -#define PWM_INTS_CH7_MSB 7 -#define PWM_INTS_CH7_LSB 7 +#define PWM_INTS_CH7_RESET _u(0x0) +#define PWM_INTS_CH7_BITS _u(0x00000080) +#define PWM_INTS_CH7_MSB _u(7) +#define PWM_INTS_CH7_LSB _u(7) #define PWM_INTS_CH7_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH6 // Description : None -#define PWM_INTS_CH6_RESET 0x0 -#define PWM_INTS_CH6_BITS 0x00000040 -#define PWM_INTS_CH6_MSB 6 -#define PWM_INTS_CH6_LSB 6 +#define PWM_INTS_CH6_RESET _u(0x0) +#define PWM_INTS_CH6_BITS _u(0x00000040) +#define PWM_INTS_CH6_MSB _u(6) +#define PWM_INTS_CH6_LSB _u(6) #define PWM_INTS_CH6_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH5 // Description : None -#define PWM_INTS_CH5_RESET 0x0 -#define PWM_INTS_CH5_BITS 0x00000020 -#define PWM_INTS_CH5_MSB 5 -#define PWM_INTS_CH5_LSB 5 +#define PWM_INTS_CH5_RESET _u(0x0) +#define PWM_INTS_CH5_BITS _u(0x00000020) +#define PWM_INTS_CH5_MSB _u(5) +#define PWM_INTS_CH5_LSB _u(5) #define PWM_INTS_CH5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH4 // Description : None -#define PWM_INTS_CH4_RESET 0x0 -#define PWM_INTS_CH4_BITS 0x00000010 -#define PWM_INTS_CH4_MSB 4 -#define PWM_INTS_CH4_LSB 4 +#define PWM_INTS_CH4_RESET _u(0x0) +#define PWM_INTS_CH4_BITS _u(0x00000010) +#define PWM_INTS_CH4_MSB _u(4) +#define PWM_INTS_CH4_LSB _u(4) #define PWM_INTS_CH4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH3 // Description : None -#define PWM_INTS_CH3_RESET 0x0 -#define PWM_INTS_CH3_BITS 0x00000008 -#define PWM_INTS_CH3_MSB 3 -#define PWM_INTS_CH3_LSB 3 +#define PWM_INTS_CH3_RESET _u(0x0) +#define PWM_INTS_CH3_BITS _u(0x00000008) +#define PWM_INTS_CH3_MSB _u(3) +#define PWM_INTS_CH3_LSB _u(3) #define PWM_INTS_CH3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH2 // Description : None -#define PWM_INTS_CH2_RESET 0x0 -#define PWM_INTS_CH2_BITS 0x00000004 -#define PWM_INTS_CH2_MSB 2 -#define PWM_INTS_CH2_LSB 2 +#define PWM_INTS_CH2_RESET _u(0x0) +#define PWM_INTS_CH2_BITS _u(0x00000004) +#define PWM_INTS_CH2_MSB _u(2) +#define PWM_INTS_CH2_LSB _u(2) #define PWM_INTS_CH2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH1 // Description : None -#define PWM_INTS_CH1_RESET 0x0 -#define PWM_INTS_CH1_BITS 0x00000002 -#define PWM_INTS_CH1_MSB 1 -#define PWM_INTS_CH1_LSB 1 +#define PWM_INTS_CH1_RESET _u(0x0) +#define PWM_INTS_CH1_BITS _u(0x00000002) +#define PWM_INTS_CH1_MSB _u(1) +#define PWM_INTS_CH1_LSB _u(1) #define PWM_INTS_CH1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH0 // Description : None -#define PWM_INTS_CH0_RESET 0x0 -#define PWM_INTS_CH0_BITS 0x00000001 -#define PWM_INTS_CH0_MSB 0 -#define PWM_INTS_CH0_LSB 0 +#define PWM_INTS_CH0_RESET _u(0x0) +#define PWM_INTS_CH0_BITS _u(0x00000001) +#define PWM_INTS_CH0_MSB _u(0) +#define PWM_INTS_CH0_LSB _u(0) #define PWM_INTS_CH0_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PWM_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h index b512350376c..689a358b0f5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h @@ -15,623 +15,623 @@ // Register : RESETS_RESET // Description : Reset control. If a bit is set it means the peripheral is in // reset. 0 means the peripheral's reset is deasserted. -#define RESETS_RESET_OFFSET 0x00000000 -#define RESETS_RESET_BITS 0x01ffffff -#define RESETS_RESET_RESET 0x01ffffff +#define RESETS_RESET_OFFSET _u(0x00000000) +#define RESETS_RESET_BITS _u(0x01ffffff) +#define RESETS_RESET_RESET _u(0x01ffffff) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_USBCTRL // Description : None -#define RESETS_RESET_USBCTRL_RESET 0x1 -#define RESETS_RESET_USBCTRL_BITS 0x01000000 -#define RESETS_RESET_USBCTRL_MSB 24 -#define RESETS_RESET_USBCTRL_LSB 24 +#define RESETS_RESET_USBCTRL_RESET _u(0x1) +#define RESETS_RESET_USBCTRL_BITS _u(0x01000000) +#define RESETS_RESET_USBCTRL_MSB _u(24) +#define RESETS_RESET_USBCTRL_LSB _u(24) #define RESETS_RESET_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART1 // Description : None -#define RESETS_RESET_UART1_RESET 0x1 -#define RESETS_RESET_UART1_BITS 0x00800000 -#define RESETS_RESET_UART1_MSB 23 -#define RESETS_RESET_UART1_LSB 23 +#define RESETS_RESET_UART1_RESET _u(0x1) +#define RESETS_RESET_UART1_BITS _u(0x00800000) +#define RESETS_RESET_UART1_MSB _u(23) +#define RESETS_RESET_UART1_LSB _u(23) #define RESETS_RESET_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART0 // Description : None -#define RESETS_RESET_UART0_RESET 0x1 -#define RESETS_RESET_UART0_BITS 0x00400000 -#define RESETS_RESET_UART0_MSB 22 -#define RESETS_RESET_UART0_LSB 22 +#define RESETS_RESET_UART0_RESET _u(0x1) +#define RESETS_RESET_UART0_BITS _u(0x00400000) +#define RESETS_RESET_UART0_MSB _u(22) +#define RESETS_RESET_UART0_LSB _u(22) #define RESETS_RESET_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TIMER // Description : None -#define RESETS_RESET_TIMER_RESET 0x1 -#define RESETS_RESET_TIMER_BITS 0x00200000 -#define RESETS_RESET_TIMER_MSB 21 -#define RESETS_RESET_TIMER_LSB 21 +#define RESETS_RESET_TIMER_RESET _u(0x1) +#define RESETS_RESET_TIMER_BITS _u(0x00200000) +#define RESETS_RESET_TIMER_MSB _u(21) +#define RESETS_RESET_TIMER_LSB _u(21) #define RESETS_RESET_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TBMAN // Description : None -#define RESETS_RESET_TBMAN_RESET 0x1 -#define RESETS_RESET_TBMAN_BITS 0x00100000 -#define RESETS_RESET_TBMAN_MSB 20 -#define RESETS_RESET_TBMAN_LSB 20 +#define RESETS_RESET_TBMAN_RESET _u(0x1) +#define RESETS_RESET_TBMAN_BITS _u(0x00100000) +#define RESETS_RESET_TBMAN_MSB _u(20) +#define RESETS_RESET_TBMAN_LSB _u(20) #define RESETS_RESET_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSINFO // Description : None -#define RESETS_RESET_SYSINFO_RESET 0x1 -#define RESETS_RESET_SYSINFO_BITS 0x00080000 -#define RESETS_RESET_SYSINFO_MSB 19 -#define RESETS_RESET_SYSINFO_LSB 19 +#define RESETS_RESET_SYSINFO_RESET _u(0x1) +#define RESETS_RESET_SYSINFO_BITS _u(0x00080000) +#define RESETS_RESET_SYSINFO_MSB _u(19) +#define RESETS_RESET_SYSINFO_LSB _u(19) #define RESETS_RESET_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSCFG // Description : None -#define RESETS_RESET_SYSCFG_RESET 0x1 -#define RESETS_RESET_SYSCFG_BITS 0x00040000 -#define RESETS_RESET_SYSCFG_MSB 18 -#define RESETS_RESET_SYSCFG_LSB 18 +#define RESETS_RESET_SYSCFG_RESET _u(0x1) +#define RESETS_RESET_SYSCFG_BITS _u(0x00040000) +#define RESETS_RESET_SYSCFG_MSB _u(18) +#define RESETS_RESET_SYSCFG_LSB _u(18) #define RESETS_RESET_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI1 // Description : None -#define RESETS_RESET_SPI1_RESET 0x1 -#define RESETS_RESET_SPI1_BITS 0x00020000 -#define RESETS_RESET_SPI1_MSB 17 -#define RESETS_RESET_SPI1_LSB 17 +#define RESETS_RESET_SPI1_RESET _u(0x1) +#define RESETS_RESET_SPI1_BITS _u(0x00020000) +#define RESETS_RESET_SPI1_MSB _u(17) +#define RESETS_RESET_SPI1_LSB _u(17) #define RESETS_RESET_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI0 // Description : None -#define RESETS_RESET_SPI0_RESET 0x1 -#define RESETS_RESET_SPI0_BITS 0x00010000 -#define RESETS_RESET_SPI0_MSB 16 -#define RESETS_RESET_SPI0_LSB 16 +#define RESETS_RESET_SPI0_RESET _u(0x1) +#define RESETS_RESET_SPI0_BITS _u(0x00010000) +#define RESETS_RESET_SPI0_MSB _u(16) +#define RESETS_RESET_SPI0_LSB _u(16) #define RESETS_RESET_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_RTC // Description : None -#define RESETS_RESET_RTC_RESET 0x1 -#define RESETS_RESET_RTC_BITS 0x00008000 -#define RESETS_RESET_RTC_MSB 15 -#define RESETS_RESET_RTC_LSB 15 +#define RESETS_RESET_RTC_RESET _u(0x1) +#define RESETS_RESET_RTC_BITS _u(0x00008000) +#define RESETS_RESET_RTC_MSB _u(15) +#define RESETS_RESET_RTC_LSB _u(15) #define RESETS_RESET_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PWM // Description : None -#define RESETS_RESET_PWM_RESET 0x1 -#define RESETS_RESET_PWM_BITS 0x00004000 -#define RESETS_RESET_PWM_MSB 14 -#define RESETS_RESET_PWM_LSB 14 +#define RESETS_RESET_PWM_RESET _u(0x1) +#define RESETS_RESET_PWM_BITS _u(0x00004000) +#define RESETS_RESET_PWM_MSB _u(14) +#define RESETS_RESET_PWM_LSB _u(14) #define RESETS_RESET_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_USB // Description : None -#define RESETS_RESET_PLL_USB_RESET 0x1 -#define RESETS_RESET_PLL_USB_BITS 0x00002000 -#define RESETS_RESET_PLL_USB_MSB 13 -#define RESETS_RESET_PLL_USB_LSB 13 +#define RESETS_RESET_PLL_USB_RESET _u(0x1) +#define RESETS_RESET_PLL_USB_BITS _u(0x00002000) +#define RESETS_RESET_PLL_USB_MSB _u(13) +#define RESETS_RESET_PLL_USB_LSB _u(13) #define RESETS_RESET_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_SYS // Description : None -#define RESETS_RESET_PLL_SYS_RESET 0x1 -#define RESETS_RESET_PLL_SYS_BITS 0x00001000 -#define RESETS_RESET_PLL_SYS_MSB 12 -#define RESETS_RESET_PLL_SYS_LSB 12 +#define RESETS_RESET_PLL_SYS_RESET _u(0x1) +#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) +#define RESETS_RESET_PLL_SYS_MSB _u(12) +#define RESETS_RESET_PLL_SYS_LSB _u(12) #define RESETS_RESET_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO1 // Description : None -#define RESETS_RESET_PIO1_RESET 0x1 -#define RESETS_RESET_PIO1_BITS 0x00000800 -#define RESETS_RESET_PIO1_MSB 11 -#define RESETS_RESET_PIO1_LSB 11 +#define RESETS_RESET_PIO1_RESET _u(0x1) +#define RESETS_RESET_PIO1_BITS _u(0x00000800) +#define RESETS_RESET_PIO1_MSB _u(11) +#define RESETS_RESET_PIO1_LSB _u(11) #define RESETS_RESET_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO0 // Description : None -#define RESETS_RESET_PIO0_RESET 0x1 -#define RESETS_RESET_PIO0_BITS 0x00000400 -#define RESETS_RESET_PIO0_MSB 10 -#define RESETS_RESET_PIO0_LSB 10 +#define RESETS_RESET_PIO0_RESET _u(0x1) +#define RESETS_RESET_PIO0_BITS _u(0x00000400) +#define RESETS_RESET_PIO0_MSB _u(10) +#define RESETS_RESET_PIO0_LSB _u(10) #define RESETS_RESET_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_QSPI // Description : None -#define RESETS_RESET_PADS_QSPI_RESET 0x1 -#define RESETS_RESET_PADS_QSPI_BITS 0x00000200 -#define RESETS_RESET_PADS_QSPI_MSB 9 -#define RESETS_RESET_PADS_QSPI_LSB 9 +#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) +#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_RESET_PADS_QSPI_MSB _u(9) +#define RESETS_RESET_PADS_QSPI_LSB _u(9) #define RESETS_RESET_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_BANK0 // Description : None -#define RESETS_RESET_PADS_BANK0_RESET 0x1 -#define RESETS_RESET_PADS_BANK0_BITS 0x00000100 -#define RESETS_RESET_PADS_BANK0_MSB 8 -#define RESETS_RESET_PADS_BANK0_LSB 8 +#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) +#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_RESET_PADS_BANK0_MSB _u(8) +#define RESETS_RESET_PADS_BANK0_LSB _u(8) #define RESETS_RESET_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_JTAG // Description : None -#define RESETS_RESET_JTAG_RESET 0x1 -#define RESETS_RESET_JTAG_BITS 0x00000080 -#define RESETS_RESET_JTAG_MSB 7 -#define RESETS_RESET_JTAG_LSB 7 +#define RESETS_RESET_JTAG_RESET _u(0x1) +#define RESETS_RESET_JTAG_BITS _u(0x00000080) +#define RESETS_RESET_JTAG_MSB _u(7) +#define RESETS_RESET_JTAG_LSB _u(7) #define RESETS_RESET_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_QSPI // Description : None -#define RESETS_RESET_IO_QSPI_RESET 0x1 -#define RESETS_RESET_IO_QSPI_BITS 0x00000040 -#define RESETS_RESET_IO_QSPI_MSB 6 -#define RESETS_RESET_IO_QSPI_LSB 6 +#define RESETS_RESET_IO_QSPI_RESET _u(0x1) +#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) +#define RESETS_RESET_IO_QSPI_MSB _u(6) +#define RESETS_RESET_IO_QSPI_LSB _u(6) #define RESETS_RESET_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_BANK0 // Description : None -#define RESETS_RESET_IO_BANK0_RESET 0x1 -#define RESETS_RESET_IO_BANK0_BITS 0x00000020 -#define RESETS_RESET_IO_BANK0_MSB 5 -#define RESETS_RESET_IO_BANK0_LSB 5 +#define RESETS_RESET_IO_BANK0_RESET _u(0x1) +#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) +#define RESETS_RESET_IO_BANK0_MSB _u(5) +#define RESETS_RESET_IO_BANK0_LSB _u(5) #define RESETS_RESET_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C1 // Description : None -#define RESETS_RESET_I2C1_RESET 0x1 -#define RESETS_RESET_I2C1_BITS 0x00000010 -#define RESETS_RESET_I2C1_MSB 4 -#define RESETS_RESET_I2C1_LSB 4 +#define RESETS_RESET_I2C1_RESET _u(0x1) +#define RESETS_RESET_I2C1_BITS _u(0x00000010) +#define RESETS_RESET_I2C1_MSB _u(4) +#define RESETS_RESET_I2C1_LSB _u(4) #define RESETS_RESET_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C0 // Description : None -#define RESETS_RESET_I2C0_RESET 0x1 -#define RESETS_RESET_I2C0_BITS 0x00000008 -#define RESETS_RESET_I2C0_MSB 3 -#define RESETS_RESET_I2C0_LSB 3 +#define RESETS_RESET_I2C0_RESET _u(0x1) +#define RESETS_RESET_I2C0_BITS _u(0x00000008) +#define RESETS_RESET_I2C0_MSB _u(3) +#define RESETS_RESET_I2C0_LSB _u(3) #define RESETS_RESET_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DMA // Description : None -#define RESETS_RESET_DMA_RESET 0x1 -#define RESETS_RESET_DMA_BITS 0x00000004 -#define RESETS_RESET_DMA_MSB 2 -#define RESETS_RESET_DMA_LSB 2 +#define RESETS_RESET_DMA_RESET _u(0x1) +#define RESETS_RESET_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DMA_MSB _u(2) +#define RESETS_RESET_DMA_LSB _u(2) #define RESETS_RESET_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_BUSCTRL // Description : None -#define RESETS_RESET_BUSCTRL_RESET 0x1 -#define RESETS_RESET_BUSCTRL_BITS 0x00000002 -#define RESETS_RESET_BUSCTRL_MSB 1 -#define RESETS_RESET_BUSCTRL_LSB 1 +#define RESETS_RESET_BUSCTRL_RESET _u(0x1) +#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_BUSCTRL_MSB _u(1) +#define RESETS_RESET_BUSCTRL_LSB _u(1) #define RESETS_RESET_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_ADC // Description : None -#define RESETS_RESET_ADC_RESET 0x1 -#define RESETS_RESET_ADC_BITS 0x00000001 -#define RESETS_RESET_ADC_MSB 0 -#define RESETS_RESET_ADC_LSB 0 +#define RESETS_RESET_ADC_RESET _u(0x1) +#define RESETS_RESET_ADC_BITS _u(0x00000001) +#define RESETS_RESET_ADC_MSB _u(0) +#define RESETS_RESET_ADC_LSB _u(0) #define RESETS_RESET_ADC_ACCESS "RW" // ============================================================================= // Register : RESETS_WDSEL // Description : Watchdog select. If a bit is set then the watchdog will reset // this peripheral when the watchdog fires. -#define RESETS_WDSEL_OFFSET 0x00000004 -#define RESETS_WDSEL_BITS 0x01ffffff -#define RESETS_WDSEL_RESET 0x00000000 +#define RESETS_WDSEL_OFFSET _u(0x00000004) +#define RESETS_WDSEL_BITS _u(0x01ffffff) +#define RESETS_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_USBCTRL // Description : None -#define RESETS_WDSEL_USBCTRL_RESET 0x0 -#define RESETS_WDSEL_USBCTRL_BITS 0x01000000 -#define RESETS_WDSEL_USBCTRL_MSB 24 -#define RESETS_WDSEL_USBCTRL_LSB 24 +#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) +#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) +#define RESETS_WDSEL_USBCTRL_MSB _u(24) +#define RESETS_WDSEL_USBCTRL_LSB _u(24) #define RESETS_WDSEL_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART1 // Description : None -#define RESETS_WDSEL_UART1_RESET 0x0 -#define RESETS_WDSEL_UART1_BITS 0x00800000 -#define RESETS_WDSEL_UART1_MSB 23 -#define RESETS_WDSEL_UART1_LSB 23 +#define RESETS_WDSEL_UART1_RESET _u(0x0) +#define RESETS_WDSEL_UART1_BITS _u(0x00800000) +#define RESETS_WDSEL_UART1_MSB _u(23) +#define RESETS_WDSEL_UART1_LSB _u(23) #define RESETS_WDSEL_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART0 // Description : None -#define RESETS_WDSEL_UART0_RESET 0x0 -#define RESETS_WDSEL_UART0_BITS 0x00400000 -#define RESETS_WDSEL_UART0_MSB 22 -#define RESETS_WDSEL_UART0_LSB 22 +#define RESETS_WDSEL_UART0_RESET _u(0x0) +#define RESETS_WDSEL_UART0_BITS _u(0x00400000) +#define RESETS_WDSEL_UART0_MSB _u(22) +#define RESETS_WDSEL_UART0_LSB _u(22) #define RESETS_WDSEL_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TIMER // Description : None -#define RESETS_WDSEL_TIMER_RESET 0x0 -#define RESETS_WDSEL_TIMER_BITS 0x00200000 -#define RESETS_WDSEL_TIMER_MSB 21 -#define RESETS_WDSEL_TIMER_LSB 21 +#define RESETS_WDSEL_TIMER_RESET _u(0x0) +#define RESETS_WDSEL_TIMER_BITS _u(0x00200000) +#define RESETS_WDSEL_TIMER_MSB _u(21) +#define RESETS_WDSEL_TIMER_LSB _u(21) #define RESETS_WDSEL_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TBMAN // Description : None -#define RESETS_WDSEL_TBMAN_RESET 0x0 -#define RESETS_WDSEL_TBMAN_BITS 0x00100000 -#define RESETS_WDSEL_TBMAN_MSB 20 -#define RESETS_WDSEL_TBMAN_LSB 20 +#define RESETS_WDSEL_TBMAN_RESET _u(0x0) +#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) +#define RESETS_WDSEL_TBMAN_MSB _u(20) +#define RESETS_WDSEL_TBMAN_LSB _u(20) #define RESETS_WDSEL_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSINFO // Description : None -#define RESETS_WDSEL_SYSINFO_RESET 0x0 -#define RESETS_WDSEL_SYSINFO_BITS 0x00080000 -#define RESETS_WDSEL_SYSINFO_MSB 19 -#define RESETS_WDSEL_SYSINFO_LSB 19 +#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) +#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) +#define RESETS_WDSEL_SYSINFO_MSB _u(19) +#define RESETS_WDSEL_SYSINFO_LSB _u(19) #define RESETS_WDSEL_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSCFG // Description : None -#define RESETS_WDSEL_SYSCFG_RESET 0x0 -#define RESETS_WDSEL_SYSCFG_BITS 0x00040000 -#define RESETS_WDSEL_SYSCFG_MSB 18 -#define RESETS_WDSEL_SYSCFG_LSB 18 +#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) +#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) +#define RESETS_WDSEL_SYSCFG_MSB _u(18) +#define RESETS_WDSEL_SYSCFG_LSB _u(18) #define RESETS_WDSEL_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI1 // Description : None -#define RESETS_WDSEL_SPI1_RESET 0x0 -#define RESETS_WDSEL_SPI1_BITS 0x00020000 -#define RESETS_WDSEL_SPI1_MSB 17 -#define RESETS_WDSEL_SPI1_LSB 17 +#define RESETS_WDSEL_SPI1_RESET _u(0x0) +#define RESETS_WDSEL_SPI1_BITS _u(0x00020000) +#define RESETS_WDSEL_SPI1_MSB _u(17) +#define RESETS_WDSEL_SPI1_LSB _u(17) #define RESETS_WDSEL_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI0 // Description : None -#define RESETS_WDSEL_SPI0_RESET 0x0 -#define RESETS_WDSEL_SPI0_BITS 0x00010000 -#define RESETS_WDSEL_SPI0_MSB 16 -#define RESETS_WDSEL_SPI0_LSB 16 +#define RESETS_WDSEL_SPI0_RESET _u(0x0) +#define RESETS_WDSEL_SPI0_BITS _u(0x00010000) +#define RESETS_WDSEL_SPI0_MSB _u(16) +#define RESETS_WDSEL_SPI0_LSB _u(16) #define RESETS_WDSEL_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_RTC // Description : None -#define RESETS_WDSEL_RTC_RESET 0x0 -#define RESETS_WDSEL_RTC_BITS 0x00008000 -#define RESETS_WDSEL_RTC_MSB 15 -#define RESETS_WDSEL_RTC_LSB 15 +#define RESETS_WDSEL_RTC_RESET _u(0x0) +#define RESETS_WDSEL_RTC_BITS _u(0x00008000) +#define RESETS_WDSEL_RTC_MSB _u(15) +#define RESETS_WDSEL_RTC_LSB _u(15) #define RESETS_WDSEL_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PWM // Description : None -#define RESETS_WDSEL_PWM_RESET 0x0 -#define RESETS_WDSEL_PWM_BITS 0x00004000 -#define RESETS_WDSEL_PWM_MSB 14 -#define RESETS_WDSEL_PWM_LSB 14 +#define RESETS_WDSEL_PWM_RESET _u(0x0) +#define RESETS_WDSEL_PWM_BITS _u(0x00004000) +#define RESETS_WDSEL_PWM_MSB _u(14) +#define RESETS_WDSEL_PWM_LSB _u(14) #define RESETS_WDSEL_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_USB // Description : None -#define RESETS_WDSEL_PLL_USB_RESET 0x0 -#define RESETS_WDSEL_PLL_USB_BITS 0x00002000 -#define RESETS_WDSEL_PLL_USB_MSB 13 -#define RESETS_WDSEL_PLL_USB_LSB 13 +#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) +#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) +#define RESETS_WDSEL_PLL_USB_MSB _u(13) +#define RESETS_WDSEL_PLL_USB_LSB _u(13) #define RESETS_WDSEL_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_SYS // Description : None -#define RESETS_WDSEL_PLL_SYS_RESET 0x0 -#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000 -#define RESETS_WDSEL_PLL_SYS_MSB 12 -#define RESETS_WDSEL_PLL_SYS_LSB 12 +#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) +#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) +#define RESETS_WDSEL_PLL_SYS_MSB _u(12) +#define RESETS_WDSEL_PLL_SYS_LSB _u(12) #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO1 // Description : None -#define RESETS_WDSEL_PIO1_RESET 0x0 -#define RESETS_WDSEL_PIO1_BITS 0x00000800 -#define RESETS_WDSEL_PIO1_MSB 11 -#define RESETS_WDSEL_PIO1_LSB 11 +#define RESETS_WDSEL_PIO1_RESET _u(0x0) +#define RESETS_WDSEL_PIO1_BITS _u(0x00000800) +#define RESETS_WDSEL_PIO1_MSB _u(11) +#define RESETS_WDSEL_PIO1_LSB _u(11) #define RESETS_WDSEL_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO0 // Description : None -#define RESETS_WDSEL_PIO0_RESET 0x0 -#define RESETS_WDSEL_PIO0_BITS 0x00000400 -#define RESETS_WDSEL_PIO0_MSB 10 -#define RESETS_WDSEL_PIO0_LSB 10 +#define RESETS_WDSEL_PIO0_RESET _u(0x0) +#define RESETS_WDSEL_PIO0_BITS _u(0x00000400) +#define RESETS_WDSEL_PIO0_MSB _u(10) +#define RESETS_WDSEL_PIO0_LSB _u(10) #define RESETS_WDSEL_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_QSPI // Description : None -#define RESETS_WDSEL_PADS_QSPI_RESET 0x0 -#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200 -#define RESETS_WDSEL_PADS_QSPI_MSB 9 -#define RESETS_WDSEL_PADS_QSPI_LSB 9 +#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_WDSEL_PADS_QSPI_MSB _u(9) +#define RESETS_WDSEL_PADS_QSPI_LSB _u(9) #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_BANK0 // Description : None -#define RESETS_WDSEL_PADS_BANK0_RESET 0x0 -#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100 -#define RESETS_WDSEL_PADS_BANK0_MSB 8 -#define RESETS_WDSEL_PADS_BANK0_LSB 8 +#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_WDSEL_PADS_BANK0_MSB _u(8) +#define RESETS_WDSEL_PADS_BANK0_LSB _u(8) #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_JTAG // Description : None -#define RESETS_WDSEL_JTAG_RESET 0x0 -#define RESETS_WDSEL_JTAG_BITS 0x00000080 -#define RESETS_WDSEL_JTAG_MSB 7 -#define RESETS_WDSEL_JTAG_LSB 7 +#define RESETS_WDSEL_JTAG_RESET _u(0x0) +#define RESETS_WDSEL_JTAG_BITS _u(0x00000080) +#define RESETS_WDSEL_JTAG_MSB _u(7) +#define RESETS_WDSEL_JTAG_LSB _u(7) #define RESETS_WDSEL_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_QSPI // Description : None -#define RESETS_WDSEL_IO_QSPI_RESET 0x0 -#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040 -#define RESETS_WDSEL_IO_QSPI_MSB 6 -#define RESETS_WDSEL_IO_QSPI_LSB 6 +#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) +#define RESETS_WDSEL_IO_QSPI_MSB _u(6) +#define RESETS_WDSEL_IO_QSPI_LSB _u(6) #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_BANK0 // Description : None -#define RESETS_WDSEL_IO_BANK0_RESET 0x0 -#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020 -#define RESETS_WDSEL_IO_BANK0_MSB 5 -#define RESETS_WDSEL_IO_BANK0_LSB 5 +#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) +#define RESETS_WDSEL_IO_BANK0_MSB _u(5) +#define RESETS_WDSEL_IO_BANK0_LSB _u(5) #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C1 // Description : None -#define RESETS_WDSEL_I2C1_RESET 0x0 -#define RESETS_WDSEL_I2C1_BITS 0x00000010 -#define RESETS_WDSEL_I2C1_MSB 4 -#define RESETS_WDSEL_I2C1_LSB 4 +#define RESETS_WDSEL_I2C1_RESET _u(0x0) +#define RESETS_WDSEL_I2C1_BITS _u(0x00000010) +#define RESETS_WDSEL_I2C1_MSB _u(4) +#define RESETS_WDSEL_I2C1_LSB _u(4) #define RESETS_WDSEL_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C0 // Description : None -#define RESETS_WDSEL_I2C0_RESET 0x0 -#define RESETS_WDSEL_I2C0_BITS 0x00000008 -#define RESETS_WDSEL_I2C0_MSB 3 -#define RESETS_WDSEL_I2C0_LSB 3 +#define RESETS_WDSEL_I2C0_RESET _u(0x0) +#define RESETS_WDSEL_I2C0_BITS _u(0x00000008) +#define RESETS_WDSEL_I2C0_MSB _u(3) +#define RESETS_WDSEL_I2C0_LSB _u(3) #define RESETS_WDSEL_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_DMA // Description : None -#define RESETS_WDSEL_DMA_RESET 0x0 -#define RESETS_WDSEL_DMA_BITS 0x00000004 -#define RESETS_WDSEL_DMA_MSB 2 -#define RESETS_WDSEL_DMA_LSB 2 +#define RESETS_WDSEL_DMA_RESET _u(0x0) +#define RESETS_WDSEL_DMA_BITS _u(0x00000004) +#define RESETS_WDSEL_DMA_MSB _u(2) +#define RESETS_WDSEL_DMA_LSB _u(2) #define RESETS_WDSEL_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_BUSCTRL // Description : None -#define RESETS_WDSEL_BUSCTRL_RESET 0x0 -#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002 -#define RESETS_WDSEL_BUSCTRL_MSB 1 -#define RESETS_WDSEL_BUSCTRL_LSB 1 +#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) +#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) +#define RESETS_WDSEL_BUSCTRL_MSB _u(1) +#define RESETS_WDSEL_BUSCTRL_LSB _u(1) #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_ADC // Description : None -#define RESETS_WDSEL_ADC_RESET 0x0 -#define RESETS_WDSEL_ADC_BITS 0x00000001 -#define RESETS_WDSEL_ADC_MSB 0 -#define RESETS_WDSEL_ADC_LSB 0 +#define RESETS_WDSEL_ADC_RESET _u(0x0) +#define RESETS_WDSEL_ADC_BITS _u(0x00000001) +#define RESETS_WDSEL_ADC_MSB _u(0) +#define RESETS_WDSEL_ADC_LSB _u(0) #define RESETS_WDSEL_ADC_ACCESS "RW" // ============================================================================= // Register : RESETS_RESET_DONE // Description : Reset done. If a bit is set then a reset done signal has been // returned by the peripheral. This indicates that the // peripheral's registers are ready to be accessed. -#define RESETS_RESET_DONE_OFFSET 0x00000008 -#define RESETS_RESET_DONE_BITS 0x01ffffff -#define RESETS_RESET_DONE_RESET 0x00000000 +#define RESETS_RESET_DONE_OFFSET _u(0x00000008) +#define RESETS_RESET_DONE_BITS _u(0x01ffffff) +#define RESETS_RESET_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_USBCTRL // Description : None -#define RESETS_RESET_DONE_USBCTRL_RESET 0x0 -#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000 -#define RESETS_RESET_DONE_USBCTRL_MSB 24 -#define RESETS_RESET_DONE_USBCTRL_LSB 24 +#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) +#define RESETS_RESET_DONE_USBCTRL_MSB _u(24) +#define RESETS_RESET_DONE_USBCTRL_LSB _u(24) #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART1 // Description : None -#define RESETS_RESET_DONE_UART1_RESET 0x0 -#define RESETS_RESET_DONE_UART1_BITS 0x00800000 -#define RESETS_RESET_DONE_UART1_MSB 23 -#define RESETS_RESET_DONE_UART1_LSB 23 +#define RESETS_RESET_DONE_UART1_RESET _u(0x0) +#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) +#define RESETS_RESET_DONE_UART1_MSB _u(23) +#define RESETS_RESET_DONE_UART1_LSB _u(23) #define RESETS_RESET_DONE_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART0 // Description : None -#define RESETS_RESET_DONE_UART0_RESET 0x0 -#define RESETS_RESET_DONE_UART0_BITS 0x00400000 -#define RESETS_RESET_DONE_UART0_MSB 22 -#define RESETS_RESET_DONE_UART0_LSB 22 +#define RESETS_RESET_DONE_UART0_RESET _u(0x0) +#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) +#define RESETS_RESET_DONE_UART0_MSB _u(22) +#define RESETS_RESET_DONE_UART0_LSB _u(22) #define RESETS_RESET_DONE_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TIMER // Description : None -#define RESETS_RESET_DONE_TIMER_RESET 0x0 -#define RESETS_RESET_DONE_TIMER_BITS 0x00200000 -#define RESETS_RESET_DONE_TIMER_MSB 21 -#define RESETS_RESET_DONE_TIMER_LSB 21 +#define RESETS_RESET_DONE_TIMER_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) +#define RESETS_RESET_DONE_TIMER_MSB _u(21) +#define RESETS_RESET_DONE_TIMER_LSB _u(21) #define RESETS_RESET_DONE_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TBMAN // Description : None -#define RESETS_RESET_DONE_TBMAN_RESET 0x0 -#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000 -#define RESETS_RESET_DONE_TBMAN_MSB 20 -#define RESETS_RESET_DONE_TBMAN_LSB 20 +#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) +#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) +#define RESETS_RESET_DONE_TBMAN_MSB _u(20) +#define RESETS_RESET_DONE_TBMAN_LSB _u(20) #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSINFO // Description : None -#define RESETS_RESET_DONE_SYSINFO_RESET 0x0 -#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000 -#define RESETS_RESET_DONE_SYSINFO_MSB 19 -#define RESETS_RESET_DONE_SYSINFO_LSB 19 +#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) +#define RESETS_RESET_DONE_SYSINFO_MSB _u(19) +#define RESETS_RESET_DONE_SYSINFO_LSB _u(19) #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSCFG // Description : None -#define RESETS_RESET_DONE_SYSCFG_RESET 0x0 -#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000 -#define RESETS_RESET_DONE_SYSCFG_MSB 18 -#define RESETS_RESET_DONE_SYSCFG_LSB 18 +#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) +#define RESETS_RESET_DONE_SYSCFG_MSB _u(18) +#define RESETS_RESET_DONE_SYSCFG_LSB _u(18) #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI1 // Description : None -#define RESETS_RESET_DONE_SPI1_RESET 0x0 -#define RESETS_RESET_DONE_SPI1_BITS 0x00020000 -#define RESETS_RESET_DONE_SPI1_MSB 17 -#define RESETS_RESET_DONE_SPI1_LSB 17 +#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) +#define RESETS_RESET_DONE_SPI1_MSB _u(17) +#define RESETS_RESET_DONE_SPI1_LSB _u(17) #define RESETS_RESET_DONE_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI0 // Description : None -#define RESETS_RESET_DONE_SPI0_RESET 0x0 -#define RESETS_RESET_DONE_SPI0_BITS 0x00010000 -#define RESETS_RESET_DONE_SPI0_MSB 16 -#define RESETS_RESET_DONE_SPI0_LSB 16 +#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) +#define RESETS_RESET_DONE_SPI0_MSB _u(16) +#define RESETS_RESET_DONE_SPI0_LSB _u(16) #define RESETS_RESET_DONE_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_RTC // Description : None -#define RESETS_RESET_DONE_RTC_RESET 0x0 -#define RESETS_RESET_DONE_RTC_BITS 0x00008000 -#define RESETS_RESET_DONE_RTC_MSB 15 -#define RESETS_RESET_DONE_RTC_LSB 15 +#define RESETS_RESET_DONE_RTC_RESET _u(0x0) +#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) +#define RESETS_RESET_DONE_RTC_MSB _u(15) +#define RESETS_RESET_DONE_RTC_LSB _u(15) #define RESETS_RESET_DONE_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PWM // Description : None -#define RESETS_RESET_DONE_PWM_RESET 0x0 -#define RESETS_RESET_DONE_PWM_BITS 0x00004000 -#define RESETS_RESET_DONE_PWM_MSB 14 -#define RESETS_RESET_DONE_PWM_LSB 14 +#define RESETS_RESET_DONE_PWM_RESET _u(0x0) +#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) +#define RESETS_RESET_DONE_PWM_MSB _u(14) +#define RESETS_RESET_DONE_PWM_LSB _u(14) #define RESETS_RESET_DONE_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_USB // Description : None -#define RESETS_RESET_DONE_PLL_USB_RESET 0x0 -#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000 -#define RESETS_RESET_DONE_PLL_USB_MSB 13 -#define RESETS_RESET_DONE_PLL_USB_LSB 13 +#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) +#define RESETS_RESET_DONE_PLL_USB_MSB _u(13) +#define RESETS_RESET_DONE_PLL_USB_LSB _u(13) #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_SYS // Description : None -#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0 -#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000 -#define RESETS_RESET_DONE_PLL_SYS_MSB 12 -#define RESETS_RESET_DONE_PLL_SYS_LSB 12 +#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) +#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) +#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12) #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO1 // Description : None -#define RESETS_RESET_DONE_PIO1_RESET 0x0 -#define RESETS_RESET_DONE_PIO1_BITS 0x00000800 -#define RESETS_RESET_DONE_PIO1_MSB 11 -#define RESETS_RESET_DONE_PIO1_LSB 11 +#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) +#define RESETS_RESET_DONE_PIO1_MSB _u(11) +#define RESETS_RESET_DONE_PIO1_LSB _u(11) #define RESETS_RESET_DONE_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO0 // Description : None -#define RESETS_RESET_DONE_PIO0_RESET 0x0 -#define RESETS_RESET_DONE_PIO0_BITS 0x00000400 -#define RESETS_RESET_DONE_PIO0_MSB 10 -#define RESETS_RESET_DONE_PIO0_LSB 10 +#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) +#define RESETS_RESET_DONE_PIO0_MSB _u(10) +#define RESETS_RESET_DONE_PIO0_LSB _u(10) #define RESETS_RESET_DONE_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_QSPI // Description : None -#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0 -#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200 -#define RESETS_RESET_DONE_PADS_QSPI_MSB 9 -#define RESETS_RESET_DONE_PADS_QSPI_LSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) +#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9) #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_BANK0 // Description : None -#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0 -#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100 -#define RESETS_RESET_DONE_PADS_BANK0_MSB 8 -#define RESETS_RESET_DONE_PADS_BANK0_LSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) +#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8) #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_JTAG // Description : None -#define RESETS_RESET_DONE_JTAG_RESET 0x0 -#define RESETS_RESET_DONE_JTAG_BITS 0x00000080 -#define RESETS_RESET_DONE_JTAG_MSB 7 -#define RESETS_RESET_DONE_JTAG_LSB 7 +#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) +#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) +#define RESETS_RESET_DONE_JTAG_MSB _u(7) +#define RESETS_RESET_DONE_JTAG_LSB _u(7) #define RESETS_RESET_DONE_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_QSPI // Description : None -#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0 -#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040 -#define RESETS_RESET_DONE_IO_QSPI_MSB 6 -#define RESETS_RESET_DONE_IO_QSPI_LSB 6 +#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) +#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) +#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6) #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_BANK0 // Description : None -#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0 -#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020 -#define RESETS_RESET_DONE_IO_BANK0_MSB 5 -#define RESETS_RESET_DONE_IO_BANK0_LSB 5 +#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) +#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) +#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5) #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C1 // Description : None -#define RESETS_RESET_DONE_I2C1_RESET 0x0 -#define RESETS_RESET_DONE_I2C1_BITS 0x00000010 -#define RESETS_RESET_DONE_I2C1_MSB 4 -#define RESETS_RESET_DONE_I2C1_LSB 4 +#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) +#define RESETS_RESET_DONE_I2C1_MSB _u(4) +#define RESETS_RESET_DONE_I2C1_LSB _u(4) #define RESETS_RESET_DONE_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C0 // Description : None -#define RESETS_RESET_DONE_I2C0_RESET 0x0 -#define RESETS_RESET_DONE_I2C0_BITS 0x00000008 -#define RESETS_RESET_DONE_I2C0_MSB 3 -#define RESETS_RESET_DONE_I2C0_LSB 3 +#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) +#define RESETS_RESET_DONE_I2C0_MSB _u(3) +#define RESETS_RESET_DONE_I2C0_LSB _u(3) #define RESETS_RESET_DONE_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_DMA // Description : None -#define RESETS_RESET_DONE_DMA_RESET 0x0 -#define RESETS_RESET_DONE_DMA_BITS 0x00000004 -#define RESETS_RESET_DONE_DMA_MSB 2 -#define RESETS_RESET_DONE_DMA_LSB 2 +#define RESETS_RESET_DONE_DMA_RESET _u(0x0) +#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DONE_DMA_MSB _u(2) +#define RESETS_RESET_DONE_DMA_LSB _u(2) #define RESETS_RESET_DONE_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_BUSCTRL // Description : None -#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0 -#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002 -#define RESETS_RESET_DONE_BUSCTRL_MSB 1 -#define RESETS_RESET_DONE_BUSCTRL_LSB 1 +#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_ADC // Description : None -#define RESETS_RESET_DONE_ADC_RESET 0x0 -#define RESETS_RESET_DONE_ADC_BITS 0x00000001 -#define RESETS_RESET_DONE_ADC_MSB 0 -#define RESETS_RESET_DONE_ADC_LSB 0 +#define RESETS_RESET_DONE_ADC_RESET _u(0x0) +#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) +#define RESETS_RESET_DONE_ADC_MSB _u(0) +#define RESETS_RESET_DONE_ADC_LSB _u(0) #define RESETS_RESET_DONE_ADC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_RESETS_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h index 1f9e8ccc5e7..5501e7ef259 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : ROSC_CTRL // Description : Ring Oscillator control -#define ROSC_CTRL_OFFSET 0x00000000 -#define ROSC_CTRL_BITS 0x00ffffff -#define ROSC_CTRL_RESET 0x00000aa0 +#define ROSC_CTRL_OFFSET _u(0x00000000) +#define ROSC_CTRL_BITS _u(0x00ffffff) +#define ROSC_CTRL_RESET _u(0x00000aa0) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_ENABLE // Description : On power-up this field is initialised to ENABLE @@ -28,12 +28,12 @@ // 0xd1e -> DISABLE // 0xfab -> ENABLE #define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS 0x00fff000 -#define ROSC_CTRL_ENABLE_MSB 23 -#define ROSC_CTRL_ENABLE_LSB 12 +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) #define ROSC_CTRL_ENABLE_ACCESS "RW" -#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e -#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_FREQ_RANGE // Description : Controls the number of delay stages in the ROSC ring @@ -51,15 +51,15 @@ // 0xfa5 -> MEDIUM // 0xfa7 -> HIGH // 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0 -#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff -#define ROSC_CTRL_FREQ_RANGE_MSB 11 -#define ROSC_CTRL_FREQ_RANGE_LSB 0 +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) #define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4 -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5 -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7 -#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6 +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) // ============================================================================= // Register : ROSC_FREQA // Description : The FREQA & FREQB registers control the frequency by @@ -72,100 +72,100 @@ // 1 bit set doubles the drive strength // 2 bits set triples drive strength // 3 bits set quadruples drive strength -#define ROSC_FREQA_OFFSET 0x00000004 -#define ROSC_FREQA_BITS 0xffff7777 -#define ROSC_FREQA_RESET 0x00000000 +#define ROSC_FREQA_OFFSET _u(0x00000004) +#define ROSC_FREQA_BITS _u(0xffff7777) +#define ROSC_FREQA_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_PASSWD // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET 0x0000 -#define ROSC_FREQA_PASSWD_BITS 0xffff0000 -#define ROSC_FREQA_PASSWD_MSB 31 -#define ROSC_FREQA_PASSWD_LSB 16 +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) #define ROSC_FREQA_PASSWD_ACCESS "RW" -#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696 +#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS3 // Description : Stage 3 drive strength -#define ROSC_FREQA_DS3_RESET 0x0 -#define ROSC_FREQA_DS3_BITS 0x00007000 -#define ROSC_FREQA_DS3_MSB 14 -#define ROSC_FREQA_DS3_LSB 12 +#define ROSC_FREQA_DS3_RESET _u(0x0) +#define ROSC_FREQA_DS3_BITS _u(0x00007000) +#define ROSC_FREQA_DS3_MSB _u(14) +#define ROSC_FREQA_DS3_LSB _u(12) #define ROSC_FREQA_DS3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS2 // Description : Stage 2 drive strength -#define ROSC_FREQA_DS2_RESET 0x0 -#define ROSC_FREQA_DS2_BITS 0x00000700 -#define ROSC_FREQA_DS2_MSB 10 -#define ROSC_FREQA_DS2_LSB 8 +#define ROSC_FREQA_DS2_RESET _u(0x0) +#define ROSC_FREQA_DS2_BITS _u(0x00000700) +#define ROSC_FREQA_DS2_MSB _u(10) +#define ROSC_FREQA_DS2_LSB _u(8) #define ROSC_FREQA_DS2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS1 // Description : Stage 1 drive strength -#define ROSC_FREQA_DS1_RESET 0x0 -#define ROSC_FREQA_DS1_BITS 0x00000070 -#define ROSC_FREQA_DS1_MSB 6 -#define ROSC_FREQA_DS1_LSB 4 +#define ROSC_FREQA_DS1_RESET _u(0x0) +#define ROSC_FREQA_DS1_BITS _u(0x00000070) +#define ROSC_FREQA_DS1_MSB _u(6) +#define ROSC_FREQA_DS1_LSB _u(4) #define ROSC_FREQA_DS1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS0 // Description : Stage 0 drive strength -#define ROSC_FREQA_DS0_RESET 0x0 -#define ROSC_FREQA_DS0_BITS 0x00000007 -#define ROSC_FREQA_DS0_MSB 2 -#define ROSC_FREQA_DS0_LSB 0 +#define ROSC_FREQA_DS0_RESET _u(0x0) +#define ROSC_FREQA_DS0_BITS _u(0x00000007) +#define ROSC_FREQA_DS0_MSB _u(2) +#define ROSC_FREQA_DS0_LSB _u(0) #define ROSC_FREQA_DS0_ACCESS "RW" // ============================================================================= // Register : ROSC_FREQB // Description : For a detailed description see freqa register -#define ROSC_FREQB_OFFSET 0x00000008 -#define ROSC_FREQB_BITS 0xffff7777 -#define ROSC_FREQB_RESET 0x00000000 +#define ROSC_FREQB_OFFSET _u(0x00000008) +#define ROSC_FREQB_BITS _u(0xffff7777) +#define ROSC_FREQB_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_PASSWD // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET 0x0000 -#define ROSC_FREQB_PASSWD_BITS 0xffff0000 -#define ROSC_FREQB_PASSWD_MSB 31 -#define ROSC_FREQB_PASSWD_LSB 16 +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) #define ROSC_FREQB_PASSWD_ACCESS "RW" -#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696 +#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS7 // Description : Stage 7 drive strength -#define ROSC_FREQB_DS7_RESET 0x0 -#define ROSC_FREQB_DS7_BITS 0x00007000 -#define ROSC_FREQB_DS7_MSB 14 -#define ROSC_FREQB_DS7_LSB 12 +#define ROSC_FREQB_DS7_RESET _u(0x0) +#define ROSC_FREQB_DS7_BITS _u(0x00007000) +#define ROSC_FREQB_DS7_MSB _u(14) +#define ROSC_FREQB_DS7_LSB _u(12) #define ROSC_FREQB_DS7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS6 // Description : Stage 6 drive strength -#define ROSC_FREQB_DS6_RESET 0x0 -#define ROSC_FREQB_DS6_BITS 0x00000700 -#define ROSC_FREQB_DS6_MSB 10 -#define ROSC_FREQB_DS6_LSB 8 +#define ROSC_FREQB_DS6_RESET _u(0x0) +#define ROSC_FREQB_DS6_BITS _u(0x00000700) +#define ROSC_FREQB_DS6_MSB _u(10) +#define ROSC_FREQB_DS6_LSB _u(8) #define ROSC_FREQB_DS6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS5 // Description : Stage 5 drive strength -#define ROSC_FREQB_DS5_RESET 0x0 -#define ROSC_FREQB_DS5_BITS 0x00000070 -#define ROSC_FREQB_DS5_MSB 6 -#define ROSC_FREQB_DS5_LSB 4 +#define ROSC_FREQB_DS5_RESET _u(0x0) +#define ROSC_FREQB_DS5_BITS _u(0x00000070) +#define ROSC_FREQB_DS5_MSB _u(6) +#define ROSC_FREQB_DS5_LSB _u(4) #define ROSC_FREQB_DS5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS4 // Description : Stage 4 drive strength -#define ROSC_FREQB_DS4_RESET 0x0 -#define ROSC_FREQB_DS4_BITS 0x00000007 -#define ROSC_FREQB_DS4_MSB 2 -#define ROSC_FREQB_DS4_LSB 0 +#define ROSC_FREQB_DS4_RESET _u(0x0) +#define ROSC_FREQB_DS4_BITS _u(0x00000007) +#define ROSC_FREQB_DS4_MSB _u(2) +#define ROSC_FREQB_DS4_LSB _u(0) #define ROSC_FREQB_DS4_ACCESS "RW" // ============================================================================= // Register : ROSC_DORMANT @@ -176,124 +176,124 @@ // Warning: setup the irq before selecting dormant mode // 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET 0x0000000c -#define ROSC_DORMANT_BITS 0xffffffff +#define ROSC_DORMANT_OFFSET _u(0x0000000c) +#define ROSC_DORMANT_BITS _u(0xffffffff) #define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB 31 -#define ROSC_DORMANT_LSB 0 +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) #define ROSC_DORMANT_ACCESS "RW" -#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61 -#define ROSC_DORMANT_VALUE_WAKE 0x77616b65 +#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : ROSC_DIV // Description : Controls the output divider // set to 0xaa0 + div where // div = 0 divides by 32 // div = 1-31 divides by div -// any other value sets div=0 and therefore divides by 32 +// any other value sets div=31 // this register resets to div=16 // 0xaa0 -> PASS -#define ROSC_DIV_OFFSET 0x00000010 -#define ROSC_DIV_BITS 0x00000fff +#define ROSC_DIV_OFFSET _u(0x00000010) +#define ROSC_DIV_BITS _u(0x00000fff) #define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB 11 -#define ROSC_DIV_LSB 0 +#define ROSC_DIV_MSB _u(11) +#define ROSC_DIV_LSB _u(0) #define ROSC_DIV_ACCESS "RW" -#define ROSC_DIV_VALUE_PASS 0xaa0 +#define ROSC_DIV_VALUE_PASS _u(0xaa0) // ============================================================================= // Register : ROSC_PHASE // Description : Controls the phase shifted output -#define ROSC_PHASE_OFFSET 0x00000014 -#define ROSC_PHASE_BITS 0x00000fff -#define ROSC_PHASE_RESET 0x00000008 +#define ROSC_PHASE_OFFSET _u(0x00000014) +#define ROSC_PHASE_BITS _u(0x00000fff) +#define ROSC_PHASE_RESET _u(0x00000008) // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_PASSWD -// Description : set to 0xaa0 +// Description : set to 0xaa // any other value enables the output with shift=0 -#define ROSC_PHASE_PASSWD_RESET 0x00 -#define ROSC_PHASE_PASSWD_BITS 0x00000ff0 -#define ROSC_PHASE_PASSWD_MSB 11 -#define ROSC_PHASE_PASSWD_LSB 4 +#define ROSC_PHASE_PASSWD_RESET _u(0x00) +#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) +#define ROSC_PHASE_PASSWD_MSB _u(11) +#define ROSC_PHASE_PASSWD_LSB _u(4) #define ROSC_PHASE_PASSWD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_ENABLE // Description : enable the phase-shifted output // this can be changed on-the-fly -#define ROSC_PHASE_ENABLE_RESET 0x1 -#define ROSC_PHASE_ENABLE_BITS 0x00000008 -#define ROSC_PHASE_ENABLE_MSB 3 -#define ROSC_PHASE_ENABLE_LSB 3 +#define ROSC_PHASE_ENABLE_RESET _u(0x1) +#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) +#define ROSC_PHASE_ENABLE_MSB _u(3) +#define ROSC_PHASE_ENABLE_LSB _u(3) #define ROSC_PHASE_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_FLIP // Description : invert the phase-shifted output // this is ignored when div=1 -#define ROSC_PHASE_FLIP_RESET 0x0 -#define ROSC_PHASE_FLIP_BITS 0x00000004 -#define ROSC_PHASE_FLIP_MSB 2 -#define ROSC_PHASE_FLIP_LSB 2 +#define ROSC_PHASE_FLIP_RESET _u(0x0) +#define ROSC_PHASE_FLIP_BITS _u(0x00000004) +#define ROSC_PHASE_FLIP_MSB _u(2) +#define ROSC_PHASE_FLIP_LSB _u(2) #define ROSC_PHASE_FLIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_SHIFT // Description : phase shift the phase-shifted output by SHIFT input clocks // this can be changed on-the-fly // must be set to 0 before setting div=1 -#define ROSC_PHASE_SHIFT_RESET 0x0 -#define ROSC_PHASE_SHIFT_BITS 0x00000003 -#define ROSC_PHASE_SHIFT_MSB 1 -#define ROSC_PHASE_SHIFT_LSB 0 +#define ROSC_PHASE_SHIFT_RESET _u(0x0) +#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) +#define ROSC_PHASE_SHIFT_MSB _u(1) +#define ROSC_PHASE_SHIFT_LSB _u(0) #define ROSC_PHASE_SHIFT_ACCESS "RW" // ============================================================================= // Register : ROSC_STATUS // Description : Ring Oscillator Status -#define ROSC_STATUS_OFFSET 0x00000018 -#define ROSC_STATUS_BITS 0x81011000 -#define ROSC_STATUS_RESET 0x00000000 +#define ROSC_STATUS_OFFSET _u(0x00000018) +#define ROSC_STATUS_BITS _u(0x81011000) +#define ROSC_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_STABLE // Description : Oscillator is running and stable -#define ROSC_STATUS_STABLE_RESET 0x0 -#define ROSC_STATUS_STABLE_BITS 0x80000000 -#define ROSC_STATUS_STABLE_MSB 31 -#define ROSC_STATUS_STABLE_LSB 31 +#define ROSC_STATUS_STABLE_RESET _u(0x0) +#define ROSC_STATUS_STABLE_BITS _u(0x80000000) +#define ROSC_STATUS_STABLE_MSB _u(31) +#define ROSC_STATUS_STABLE_LSB _u(31) #define ROSC_STATUS_STABLE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_BADWRITE // Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT -#define ROSC_STATUS_BADWRITE_RESET 0x0 -#define ROSC_STATUS_BADWRITE_BITS 0x01000000 -#define ROSC_STATUS_BADWRITE_MSB 24 -#define ROSC_STATUS_BADWRITE_LSB 24 +// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT +#define ROSC_STATUS_BADWRITE_RESET _u(0x0) +#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define ROSC_STATUS_BADWRITE_MSB _u(24) +#define ROSC_STATUS_BADWRITE_LSB _u(24) #define ROSC_STATUS_BADWRITE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_DIV_RUNNING // Description : post-divider is running // this resets to 0 but transitions to 1 during chip startup #define ROSC_STATUS_DIV_RUNNING_RESET "-" -#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000 -#define ROSC_STATUS_DIV_RUNNING_MSB 16 -#define ROSC_STATUS_DIV_RUNNING_LSB 16 +#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) +#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) #define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_ENABLED // Description : Oscillator is enabled but not necessarily running and stable // this resets to 0 but transitions to 1 during chip startup #define ROSC_STATUS_ENABLED_RESET "-" -#define ROSC_STATUS_ENABLED_BITS 0x00001000 -#define ROSC_STATUS_ENABLED_MSB 12 -#define ROSC_STATUS_ENABLED_LSB 12 +#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) +#define ROSC_STATUS_ENABLED_MSB _u(12) +#define ROSC_STATUS_ENABLED_LSB _u(12) #define ROSC_STATUS_ENABLED_ACCESS "RO" // ============================================================================= // Register : ROSC_RANDOMBIT // Description : This just reads the state of the oscillator output so // randomness is compromised if the ring oscillator is stopped or // run at a harmonic of the bus frequency -#define ROSC_RANDOMBIT_OFFSET 0x0000001c -#define ROSC_RANDOMBIT_BITS 0x00000001 -#define ROSC_RANDOMBIT_RESET 0x00000001 -#define ROSC_RANDOMBIT_MSB 0 -#define ROSC_RANDOMBIT_LSB 0 +#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c) +#define ROSC_RANDOMBIT_BITS _u(0x00000001) +#define ROSC_RANDOMBIT_RESET _u(0x00000001) +#define ROSC_RANDOMBIT_MSB _u(0) +#define ROSC_RANDOMBIT_LSB _u(0) #define ROSC_RANDOMBIT_ACCESS "RO" // ============================================================================= // Register : ROSC_COUNT @@ -302,11 +302,11 @@ // To start the counter write a non-zero value. // Can be used for short software pauses when setting up time // sensitive hardware. -#define ROSC_COUNT_OFFSET 0x00000020 -#define ROSC_COUNT_BITS 0x000000ff -#define ROSC_COUNT_RESET 0x00000000 -#define ROSC_COUNT_MSB 7 -#define ROSC_COUNT_LSB 0 +#define ROSC_COUNT_OFFSET _u(0x00000020) +#define ROSC_COUNT_BITS _u(0x000000ff) +#define ROSC_COUNT_RESET _u(0x00000000) +#define ROSC_COUNT_MSB _u(7) +#define ROSC_COUNT_LSB _u(0) #define ROSC_COUNT_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_ROSC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h index 1287d9023b7..7d62c9d7353 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h @@ -15,384 +15,384 @@ // Register : RTC_CLKDIV_M1 // Description : Divider minus 1 for the 1 second counter. Safe to change the // value when RTC is not enabled. -#define RTC_CLKDIV_M1_OFFSET 0x00000000 -#define RTC_CLKDIV_M1_BITS 0x0000ffff -#define RTC_CLKDIV_M1_RESET 0x00000000 -#define RTC_CLKDIV_M1_MSB 15 -#define RTC_CLKDIV_M1_LSB 0 +#define RTC_CLKDIV_M1_OFFSET _u(0x00000000) +#define RTC_CLKDIV_M1_BITS _u(0x0000ffff) +#define RTC_CLKDIV_M1_RESET _u(0x00000000) +#define RTC_CLKDIV_M1_MSB _u(15) +#define RTC_CLKDIV_M1_LSB _u(0) #define RTC_CLKDIV_M1_ACCESS "RW" // ============================================================================= // Register : RTC_SETUP_0 // Description : RTC setup register 0 -#define RTC_SETUP_0_OFFSET 0x00000004 -#define RTC_SETUP_0_BITS 0x00ffff1f -#define RTC_SETUP_0_RESET 0x00000000 +#define RTC_SETUP_0_OFFSET _u(0x00000004) +#define RTC_SETUP_0_BITS _u(0x00ffff1f) +#define RTC_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_YEAR // Description : Year -#define RTC_SETUP_0_YEAR_RESET 0x000 -#define RTC_SETUP_0_YEAR_BITS 0x00fff000 -#define RTC_SETUP_0_YEAR_MSB 23 -#define RTC_SETUP_0_YEAR_LSB 12 +#define RTC_SETUP_0_YEAR_RESET _u(0x000) +#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000) +#define RTC_SETUP_0_YEAR_MSB _u(23) +#define RTC_SETUP_0_YEAR_LSB _u(12) #define RTC_SETUP_0_YEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_MONTH // Description : Month (1..12) -#define RTC_SETUP_0_MONTH_RESET 0x0 -#define RTC_SETUP_0_MONTH_BITS 0x00000f00 -#define RTC_SETUP_0_MONTH_MSB 11 -#define RTC_SETUP_0_MONTH_LSB 8 +#define RTC_SETUP_0_MONTH_RESET _u(0x0) +#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00) +#define RTC_SETUP_0_MONTH_MSB _u(11) +#define RTC_SETUP_0_MONTH_LSB _u(8) #define RTC_SETUP_0_MONTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_DAY // Description : Day of the month (1..31) -#define RTC_SETUP_0_DAY_RESET 0x00 -#define RTC_SETUP_0_DAY_BITS 0x0000001f -#define RTC_SETUP_0_DAY_MSB 4 -#define RTC_SETUP_0_DAY_LSB 0 +#define RTC_SETUP_0_DAY_RESET _u(0x00) +#define RTC_SETUP_0_DAY_BITS _u(0x0000001f) +#define RTC_SETUP_0_DAY_MSB _u(4) +#define RTC_SETUP_0_DAY_LSB _u(0) #define RTC_SETUP_0_DAY_ACCESS "RW" // ============================================================================= // Register : RTC_SETUP_1 // Description : RTC setup register 1 -#define RTC_SETUP_1_OFFSET 0x00000008 -#define RTC_SETUP_1_BITS 0x071f3f3f -#define RTC_SETUP_1_RESET 0x00000000 +#define RTC_SETUP_1_OFFSET _u(0x00000008) +#define RTC_SETUP_1_BITS _u(0x071f3f3f) +#define RTC_SETUP_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_DOTW // Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 -#define RTC_SETUP_1_DOTW_RESET 0x0 -#define RTC_SETUP_1_DOTW_BITS 0x07000000 -#define RTC_SETUP_1_DOTW_MSB 26 -#define RTC_SETUP_1_DOTW_LSB 24 +#define RTC_SETUP_1_DOTW_RESET _u(0x0) +#define RTC_SETUP_1_DOTW_BITS _u(0x07000000) +#define RTC_SETUP_1_DOTW_MSB _u(26) +#define RTC_SETUP_1_DOTW_LSB _u(24) #define RTC_SETUP_1_DOTW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_HOUR // Description : Hours -#define RTC_SETUP_1_HOUR_RESET 0x00 -#define RTC_SETUP_1_HOUR_BITS 0x001f0000 -#define RTC_SETUP_1_HOUR_MSB 20 -#define RTC_SETUP_1_HOUR_LSB 16 +#define RTC_SETUP_1_HOUR_RESET _u(0x00) +#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000) +#define RTC_SETUP_1_HOUR_MSB _u(20) +#define RTC_SETUP_1_HOUR_LSB _u(16) #define RTC_SETUP_1_HOUR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_MIN // Description : Minutes -#define RTC_SETUP_1_MIN_RESET 0x00 -#define RTC_SETUP_1_MIN_BITS 0x00003f00 -#define RTC_SETUP_1_MIN_MSB 13 -#define RTC_SETUP_1_MIN_LSB 8 +#define RTC_SETUP_1_MIN_RESET _u(0x00) +#define RTC_SETUP_1_MIN_BITS _u(0x00003f00) +#define RTC_SETUP_1_MIN_MSB _u(13) +#define RTC_SETUP_1_MIN_LSB _u(8) #define RTC_SETUP_1_MIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_SEC // Description : Seconds -#define RTC_SETUP_1_SEC_RESET 0x00 -#define RTC_SETUP_1_SEC_BITS 0x0000003f -#define RTC_SETUP_1_SEC_MSB 5 -#define RTC_SETUP_1_SEC_LSB 0 +#define RTC_SETUP_1_SEC_RESET _u(0x00) +#define RTC_SETUP_1_SEC_BITS _u(0x0000003f) +#define RTC_SETUP_1_SEC_MSB _u(5) +#define RTC_SETUP_1_SEC_LSB _u(0) #define RTC_SETUP_1_SEC_ACCESS "RW" // ============================================================================= // Register : RTC_CTRL // Description : RTC Control and status -#define RTC_CTRL_OFFSET 0x0000000c -#define RTC_CTRL_BITS 0x00000113 -#define RTC_CTRL_RESET 0x00000000 +#define RTC_CTRL_OFFSET _u(0x0000000c) +#define RTC_CTRL_BITS _u(0x00000113) +#define RTC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_CTRL_FORCE_NOTLEAPYEAR // Description : If set, leapyear is forced off. // Useful for years divisible by 100 but not by 400 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8) #define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_LOAD // Description : Load RTC -#define RTC_CTRL_LOAD_RESET 0x0 -#define RTC_CTRL_LOAD_BITS 0x00000010 -#define RTC_CTRL_LOAD_MSB 4 -#define RTC_CTRL_LOAD_LSB 4 +#define RTC_CTRL_LOAD_RESET _u(0x0) +#define RTC_CTRL_LOAD_BITS _u(0x00000010) +#define RTC_CTRL_LOAD_MSB _u(4) +#define RTC_CTRL_LOAD_LSB _u(4) #define RTC_CTRL_LOAD_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_RTC_ACTIVE // Description : RTC enabled (running) #define RTC_CTRL_RTC_ACTIVE_RESET "-" -#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002 -#define RTC_CTRL_RTC_ACTIVE_MSB 1 -#define RTC_CTRL_RTC_ACTIVE_LSB 1 +#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002) +#define RTC_CTRL_RTC_ACTIVE_MSB _u(1) +#define RTC_CTRL_RTC_ACTIVE_LSB _u(1) #define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_RTC_ENABLE // Description : Enable RTC -#define RTC_CTRL_RTC_ENABLE_RESET 0x0 -#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001 -#define RTC_CTRL_RTC_ENABLE_MSB 0 -#define RTC_CTRL_RTC_ENABLE_LSB 0 +#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0) +#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001) +#define RTC_CTRL_RTC_ENABLE_MSB _u(0) +#define RTC_CTRL_RTC_ENABLE_LSB _u(0) #define RTC_CTRL_RTC_ENABLE_ACCESS "RW" // ============================================================================= // Register : RTC_IRQ_SETUP_0 // Description : Interrupt setup register 0 -#define RTC_IRQ_SETUP_0_OFFSET 0x00000010 -#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f -#define RTC_IRQ_SETUP_0_RESET 0x00000000 +#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010) +#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f) +#define RTC_IRQ_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE // Description : None #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000 -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29 -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29) #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ENA // Description : Global match enable. Don't change any other value while this // one is enabled -#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000 -#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28 -#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000) +#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28) +#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28) #define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_YEAR_ENA // Description : Enable year matching -#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000 -#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26 -#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000) +#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26) +#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26) #define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MONTH_ENA // Description : Enable month matching -#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000 -#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25 -#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000) +#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25) +#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25) #define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_DAY_ENA // Description : Enable day matching -#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000 -#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24 -#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000) +#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24) +#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24) #define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_YEAR // Description : Year -#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000 -#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000 -#define RTC_IRQ_SETUP_0_YEAR_MSB 23 -#define RTC_IRQ_SETUP_0_YEAR_LSB 12 +#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000) +#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000) +#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23) +#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12) #define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MONTH // Description : Month (1..12) -#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0 -#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00 -#define RTC_IRQ_SETUP_0_MONTH_MSB 11 -#define RTC_IRQ_SETUP_0_MONTH_LSB 8 +#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00) +#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11) +#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8) #define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_DAY // Description : Day of the month (1..31) -#define RTC_IRQ_SETUP_0_DAY_RESET 0x00 -#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f -#define RTC_IRQ_SETUP_0_DAY_MSB 4 -#define RTC_IRQ_SETUP_0_DAY_LSB 0 +#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00) +#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f) +#define RTC_IRQ_SETUP_0_DAY_MSB _u(4) +#define RTC_IRQ_SETUP_0_DAY_LSB _u(0) #define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" // ============================================================================= // Register : RTC_IRQ_SETUP_1 // Description : Interrupt setup register 1 -#define RTC_IRQ_SETUP_1_OFFSET 0x00000014 -#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f -#define RTC_IRQ_SETUP_1_RESET 0x00000000 +#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014) +#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f) +#define RTC_IRQ_SETUP_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_DOTW_ENA // Description : Enable day of the week matching -#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000 -#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31 -#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000) +#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31) +#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31) #define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_HOUR_ENA // Description : Enable hour matching -#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000 -#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30 -#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000) +#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30) +#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30) #define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_MIN_ENA // Description : Enable minute matching -#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000 -#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29 -#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000) +#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29) +#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29) #define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_SEC_ENA // Description : Enable second matching -#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000 -#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28 -#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000) +#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28) +#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28) #define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_DOTW // Description : Day of the week -#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0 -#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000 -#define RTC_IRQ_SETUP_1_DOTW_MSB 26 -#define RTC_IRQ_SETUP_1_DOTW_LSB 24 +#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000) +#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26) +#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24) #define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_HOUR // Description : Hours -#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00 -#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000 -#define RTC_IRQ_SETUP_1_HOUR_MSB 20 -#define RTC_IRQ_SETUP_1_HOUR_LSB 16 +#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000) +#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20) +#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16) #define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_MIN // Description : Minutes -#define RTC_IRQ_SETUP_1_MIN_RESET 0x00 -#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00 -#define RTC_IRQ_SETUP_1_MIN_MSB 13 -#define RTC_IRQ_SETUP_1_MIN_LSB 8 +#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00) +#define RTC_IRQ_SETUP_1_MIN_MSB _u(13) +#define RTC_IRQ_SETUP_1_MIN_LSB _u(8) #define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_SEC // Description : Seconds -#define RTC_IRQ_SETUP_1_SEC_RESET 0x00 -#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f -#define RTC_IRQ_SETUP_1_SEC_MSB 5 -#define RTC_IRQ_SETUP_1_SEC_LSB 0 +#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f) +#define RTC_IRQ_SETUP_1_SEC_MSB _u(5) +#define RTC_IRQ_SETUP_1_SEC_LSB _u(0) #define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" // ============================================================================= // Register : RTC_RTC_1 // Description : RTC register 1. -#define RTC_RTC_1_OFFSET 0x00000018 -#define RTC_RTC_1_BITS 0x00ffff1f -#define RTC_RTC_1_RESET 0x00000000 +#define RTC_RTC_1_OFFSET _u(0x00000018) +#define RTC_RTC_1_BITS _u(0x00ffff1f) +#define RTC_RTC_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_YEAR // Description : Year #define RTC_RTC_1_YEAR_RESET "-" -#define RTC_RTC_1_YEAR_BITS 0x00fff000 -#define RTC_RTC_1_YEAR_MSB 23 -#define RTC_RTC_1_YEAR_LSB 12 +#define RTC_RTC_1_YEAR_BITS _u(0x00fff000) +#define RTC_RTC_1_YEAR_MSB _u(23) +#define RTC_RTC_1_YEAR_LSB _u(12) #define RTC_RTC_1_YEAR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_MONTH // Description : Month (1..12) #define RTC_RTC_1_MONTH_RESET "-" -#define RTC_RTC_1_MONTH_BITS 0x00000f00 -#define RTC_RTC_1_MONTH_MSB 11 -#define RTC_RTC_1_MONTH_LSB 8 +#define RTC_RTC_1_MONTH_BITS _u(0x00000f00) +#define RTC_RTC_1_MONTH_MSB _u(11) +#define RTC_RTC_1_MONTH_LSB _u(8) #define RTC_RTC_1_MONTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_DAY // Description : Day of the month (1..31) #define RTC_RTC_1_DAY_RESET "-" -#define RTC_RTC_1_DAY_BITS 0x0000001f -#define RTC_RTC_1_DAY_MSB 4 -#define RTC_RTC_1_DAY_LSB 0 +#define RTC_RTC_1_DAY_BITS _u(0x0000001f) +#define RTC_RTC_1_DAY_MSB _u(4) +#define RTC_RTC_1_DAY_LSB _u(0) #define RTC_RTC_1_DAY_ACCESS "RO" // ============================================================================= // Register : RTC_RTC_0 // Description : RTC register 0 // Read this before RTC 1! -#define RTC_RTC_0_OFFSET 0x0000001c -#define RTC_RTC_0_BITS 0x071f3f3f -#define RTC_RTC_0_RESET 0x00000000 +#define RTC_RTC_0_OFFSET _u(0x0000001c) +#define RTC_RTC_0_BITS _u(0x071f3f3f) +#define RTC_RTC_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_DOTW // Description : Day of the week #define RTC_RTC_0_DOTW_RESET "-" -#define RTC_RTC_0_DOTW_BITS 0x07000000 -#define RTC_RTC_0_DOTW_MSB 26 -#define RTC_RTC_0_DOTW_LSB 24 +#define RTC_RTC_0_DOTW_BITS _u(0x07000000) +#define RTC_RTC_0_DOTW_MSB _u(26) +#define RTC_RTC_0_DOTW_LSB _u(24) #define RTC_RTC_0_DOTW_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_HOUR // Description : Hours #define RTC_RTC_0_HOUR_RESET "-" -#define RTC_RTC_0_HOUR_BITS 0x001f0000 -#define RTC_RTC_0_HOUR_MSB 20 -#define RTC_RTC_0_HOUR_LSB 16 +#define RTC_RTC_0_HOUR_BITS _u(0x001f0000) +#define RTC_RTC_0_HOUR_MSB _u(20) +#define RTC_RTC_0_HOUR_LSB _u(16) #define RTC_RTC_0_HOUR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_MIN // Description : Minutes #define RTC_RTC_0_MIN_RESET "-" -#define RTC_RTC_0_MIN_BITS 0x00003f00 -#define RTC_RTC_0_MIN_MSB 13 -#define RTC_RTC_0_MIN_LSB 8 +#define RTC_RTC_0_MIN_BITS _u(0x00003f00) +#define RTC_RTC_0_MIN_MSB _u(13) +#define RTC_RTC_0_MIN_LSB _u(8) #define RTC_RTC_0_MIN_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_SEC // Description : Seconds #define RTC_RTC_0_SEC_RESET "-" -#define RTC_RTC_0_SEC_BITS 0x0000003f -#define RTC_RTC_0_SEC_MSB 5 -#define RTC_RTC_0_SEC_LSB 0 +#define RTC_RTC_0_SEC_BITS _u(0x0000003f) +#define RTC_RTC_0_SEC_MSB _u(5) +#define RTC_RTC_0_SEC_LSB _u(0) #define RTC_RTC_0_SEC_ACCESS "RF" // ============================================================================= // Register : RTC_INTR // Description : Raw Interrupts -#define RTC_INTR_OFFSET 0x00000020 -#define RTC_INTR_BITS 0x00000001 -#define RTC_INTR_RESET 0x00000000 +#define RTC_INTR_OFFSET _u(0x00000020) +#define RTC_INTR_BITS _u(0x00000001) +#define RTC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTR_RTC // Description : None -#define RTC_INTR_RTC_RESET 0x0 -#define RTC_INTR_RTC_BITS 0x00000001 -#define RTC_INTR_RTC_MSB 0 -#define RTC_INTR_RTC_LSB 0 +#define RTC_INTR_RTC_RESET _u(0x0) +#define RTC_INTR_RTC_BITS _u(0x00000001) +#define RTC_INTR_RTC_MSB _u(0) +#define RTC_INTR_RTC_LSB _u(0) #define RTC_INTR_RTC_ACCESS "RO" // ============================================================================= // Register : RTC_INTE // Description : Interrupt Enable -#define RTC_INTE_OFFSET 0x00000024 -#define RTC_INTE_BITS 0x00000001 -#define RTC_INTE_RESET 0x00000000 +#define RTC_INTE_OFFSET _u(0x00000024) +#define RTC_INTE_BITS _u(0x00000001) +#define RTC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTE_RTC // Description : None -#define RTC_INTE_RTC_RESET 0x0 -#define RTC_INTE_RTC_BITS 0x00000001 -#define RTC_INTE_RTC_MSB 0 -#define RTC_INTE_RTC_LSB 0 +#define RTC_INTE_RTC_RESET _u(0x0) +#define RTC_INTE_RTC_BITS _u(0x00000001) +#define RTC_INTE_RTC_MSB _u(0) +#define RTC_INTE_RTC_LSB _u(0) #define RTC_INTE_RTC_ACCESS "RW" // ============================================================================= // Register : RTC_INTF // Description : Interrupt Force -#define RTC_INTF_OFFSET 0x00000028 -#define RTC_INTF_BITS 0x00000001 -#define RTC_INTF_RESET 0x00000000 +#define RTC_INTF_OFFSET _u(0x00000028) +#define RTC_INTF_BITS _u(0x00000001) +#define RTC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTF_RTC // Description : None -#define RTC_INTF_RTC_RESET 0x0 -#define RTC_INTF_RTC_BITS 0x00000001 -#define RTC_INTF_RTC_MSB 0 -#define RTC_INTF_RTC_LSB 0 +#define RTC_INTF_RTC_RESET _u(0x0) +#define RTC_INTF_RTC_BITS _u(0x00000001) +#define RTC_INTF_RTC_MSB _u(0) +#define RTC_INTF_RTC_LSB _u(0) #define RTC_INTF_RTC_ACCESS "RW" // ============================================================================= // Register : RTC_INTS // Description : Interrupt status after masking & forcing -#define RTC_INTS_OFFSET 0x0000002c -#define RTC_INTS_BITS 0x00000001 -#define RTC_INTS_RESET 0x00000000 +#define RTC_INTS_OFFSET _u(0x0000002c) +#define RTC_INTS_BITS _u(0x00000001) +#define RTC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTS_RTC // Description : None -#define RTC_INTS_RTC_RESET 0x0 -#define RTC_INTS_RTC_BITS 0x00000001 -#define RTC_INTS_RTC_MSB 0 -#define RTC_INTS_RTC_LSB 0 +#define RTC_INTS_RTC_RESET _u(0x0) +#define RTC_INTS_RTC_BITS _u(0x00000001) +#define RTC_INTS_RTC_MSB _u(0) +#define RTC_INTS_RTC_LSB _u(0) #define RTC_INTS_RTC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_RTC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h index 4480d76f08e..f6415339774 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h @@ -18,32 +18,32 @@ // Description : Processor core identifier // Value is 0 when read from processor core 0, and 1 when read // from processor core 1. -#define SIO_CPUID_OFFSET 0x00000000 -#define SIO_CPUID_BITS 0xffffffff +#define SIO_CPUID_OFFSET _u(0x00000000) +#define SIO_CPUID_BITS _u(0xffffffff) #define SIO_CPUID_RESET "-" -#define SIO_CPUID_MSB 31 -#define SIO_CPUID_LSB 0 +#define SIO_CPUID_MSB _u(31) +#define SIO_CPUID_LSB _u(0) #define SIO_CPUID_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_IN // Description : Input value for GPIO pins // Input value for GPIO0...29 -#define SIO_GPIO_IN_OFFSET 0x00000004 -#define SIO_GPIO_IN_BITS 0x3fffffff -#define SIO_GPIO_IN_RESET 0x00000000 -#define SIO_GPIO_IN_MSB 29 -#define SIO_GPIO_IN_LSB 0 +#define SIO_GPIO_IN_OFFSET _u(0x00000004) +#define SIO_GPIO_IN_BITS _u(0x3fffffff) +#define SIO_GPIO_IN_RESET _u(0x00000000) +#define SIO_GPIO_IN_MSB _u(29) +#define SIO_GPIO_IN_LSB _u(0) #define SIO_GPIO_IN_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_HI_IN // Description : Input value for QSPI pins // Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, // SD3 -#define SIO_GPIO_HI_IN_OFFSET 0x00000008 -#define SIO_GPIO_HI_IN_BITS 0x0000003f -#define SIO_GPIO_HI_IN_RESET 0x00000000 -#define SIO_GPIO_HI_IN_MSB 5 -#define SIO_GPIO_HI_IN_LSB 0 +#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) +#define SIO_GPIO_HI_IN_BITS _u(0x0000003f) +#define SIO_GPIO_HI_IN_RESET _u(0x00000000) +#define SIO_GPIO_HI_IN_MSB _u(5) +#define SIO_GPIO_HI_IN_LSB _u(0) #define SIO_GPIO_HI_IN_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_OUT @@ -56,44 +56,44 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_OUT_OFFSET 0x00000010 -#define SIO_GPIO_OUT_BITS 0x3fffffff -#define SIO_GPIO_OUT_RESET 0x00000000 -#define SIO_GPIO_OUT_MSB 29 -#define SIO_GPIO_OUT_LSB 0 +#define SIO_GPIO_OUT_OFFSET _u(0x00000010) +#define SIO_GPIO_OUT_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_RESET _u(0x00000000) +#define SIO_GPIO_OUT_MSB _u(29) +#define SIO_GPIO_OUT_LSB _u(0) #define SIO_GPIO_OUT_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_OUT_SET // Description : GPIO output value set // Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` -#define SIO_GPIO_OUT_SET_OFFSET 0x00000014 -#define SIO_GPIO_OUT_SET_BITS 0x3fffffff -#define SIO_GPIO_OUT_SET_RESET 0x00000000 -#define SIO_GPIO_OUT_SET_MSB 29 -#define SIO_GPIO_OUT_SET_LSB 0 -#define SIO_GPIO_OUT_SET_ACCESS "RW" +#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014) +#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_OUT_SET_MSB _u(29) +#define SIO_GPIO_OUT_SET_LSB _u(0) +#define SIO_GPIO_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_CLR // Description : GPIO output value clear // Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= // ~wdata` -#define SIO_GPIO_OUT_CLR_OFFSET 0x00000018 -#define SIO_GPIO_OUT_CLR_BITS 0x3fffffff -#define SIO_GPIO_OUT_CLR_RESET 0x00000000 -#define SIO_GPIO_OUT_CLR_MSB 29 -#define SIO_GPIO_OUT_CLR_LSB 0 -#define SIO_GPIO_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018) +#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_CLR_MSB _u(29) +#define SIO_GPIO_OUT_CLR_LSB _u(0) +#define SIO_GPIO_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_XOR // Description : GPIO output value XOR // Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= // wdata` -#define SIO_GPIO_OUT_XOR_OFFSET 0x0000001c -#define SIO_GPIO_OUT_XOR_BITS 0x3fffffff -#define SIO_GPIO_OUT_XOR_RESET 0x00000000 -#define SIO_GPIO_OUT_XOR_MSB 29 -#define SIO_GPIO_OUT_XOR_LSB 0 -#define SIO_GPIO_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c) +#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_XOR_MSB _u(29) +#define SIO_GPIO_OUT_XOR_LSB _u(0) +#define SIO_GPIO_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE // Description : GPIO output enable @@ -104,44 +104,44 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_OE_OFFSET 0x00000020 -#define SIO_GPIO_OE_BITS 0x3fffffff -#define SIO_GPIO_OE_RESET 0x00000000 -#define SIO_GPIO_OE_MSB 29 -#define SIO_GPIO_OE_LSB 0 +#define SIO_GPIO_OE_OFFSET _u(0x00000020) +#define SIO_GPIO_OE_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_RESET _u(0x00000000) +#define SIO_GPIO_OE_MSB _u(29) +#define SIO_GPIO_OE_LSB _u(0) #define SIO_GPIO_OE_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_OE_SET // Description : GPIO output enable set // Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` -#define SIO_GPIO_OE_SET_OFFSET 0x00000024 -#define SIO_GPIO_OE_SET_BITS 0x3fffffff -#define SIO_GPIO_OE_SET_RESET 0x00000000 -#define SIO_GPIO_OE_SET_MSB 29 -#define SIO_GPIO_OE_SET_LSB 0 -#define SIO_GPIO_OE_SET_ACCESS "RW" +#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024) +#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_OE_SET_MSB _u(29) +#define SIO_GPIO_OE_SET_LSB _u(0) +#define SIO_GPIO_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_CLR // Description : GPIO output enable clear // Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= // ~wdata` -#define SIO_GPIO_OE_CLR_OFFSET 0x00000028 -#define SIO_GPIO_OE_CLR_BITS 0x3fffffff -#define SIO_GPIO_OE_CLR_RESET 0x00000000 -#define SIO_GPIO_OE_CLR_MSB 29 -#define SIO_GPIO_OE_CLR_LSB 0 -#define SIO_GPIO_OE_CLR_ACCESS "RW" +#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028) +#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OE_CLR_MSB _u(29) +#define SIO_GPIO_OE_CLR_LSB _u(0) +#define SIO_GPIO_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_XOR // Description : GPIO output enable XOR // Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= // wdata` -#define SIO_GPIO_OE_XOR_OFFSET 0x0000002c -#define SIO_GPIO_OE_XOR_BITS 0x3fffffff -#define SIO_GPIO_OE_XOR_RESET 0x00000000 -#define SIO_GPIO_OE_XOR_MSB 29 -#define SIO_GPIO_OE_XOR_LSB 0 -#define SIO_GPIO_OE_XOR_ACCESS "RW" +#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c) +#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OE_XOR_MSB _u(29) +#define SIO_GPIO_OE_XOR_LSB _u(0) +#define SIO_GPIO_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT // Description : QSPI output value @@ -153,45 +153,45 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_HI_OUT_OFFSET 0x00000030 -#define SIO_GPIO_HI_OUT_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_MSB 5 -#define SIO_GPIO_HI_OUT_LSB 0 +#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030) +#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_MSB _u(5) +#define SIO_GPIO_HI_OUT_LSB _u(0) #define SIO_GPIO_HI_OUT_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_HI_OUT_SET // Description : QSPI output value set // Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= // wdata` -#define SIO_GPIO_HI_OUT_SET_OFFSET 0x00000034 -#define SIO_GPIO_HI_OUT_SET_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_SET_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_SET_MSB 5 -#define SIO_GPIO_HI_OUT_SET_LSB 0 -#define SIO_GPIO_HI_OUT_SET_ACCESS "RW" +#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034) +#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_SET_MSB _u(5) +#define SIO_GPIO_HI_OUT_SET_LSB _u(0) +#define SIO_GPIO_HI_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_CLR // Description : QSPI output value clear // Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT // &= ~wdata` -#define SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000038 -#define SIO_GPIO_HI_OUT_CLR_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_CLR_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_CLR_MSB 5 -#define SIO_GPIO_HI_OUT_CLR_LSB 0 -#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038) +#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_CLR_MSB _u(5) +#define SIO_GPIO_HI_OUT_CLR_LSB _u(0) +#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_XOR // Description : QSPI output value XOR // Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT // ^= wdata` -#define SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000003c -#define SIO_GPIO_HI_OUT_XOR_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_XOR_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_XOR_MSB 5 -#define SIO_GPIO_HI_OUT_XOR_LSB 0 -#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c) +#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_XOR_MSB _u(5) +#define SIO_GPIO_HI_OUT_XOR_LSB _u(0) +#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE // Description : QSPI output enable @@ -202,45 +202,45 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_HI_OE_OFFSET 0x00000040 -#define SIO_GPIO_HI_OE_BITS 0x0000003f -#define SIO_GPIO_HI_OE_RESET 0x00000000 -#define SIO_GPIO_HI_OE_MSB 5 -#define SIO_GPIO_HI_OE_LSB 0 +#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040) +#define SIO_GPIO_HI_OE_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_MSB _u(5) +#define SIO_GPIO_HI_OE_LSB _u(0) #define SIO_GPIO_HI_OE_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_HI_OE_SET // Description : QSPI output enable set // Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= // wdata` -#define SIO_GPIO_HI_OE_SET_OFFSET 0x00000044 -#define SIO_GPIO_HI_OE_SET_BITS 0x0000003f -#define SIO_GPIO_HI_OE_SET_RESET 0x00000000 -#define SIO_GPIO_HI_OE_SET_MSB 5 -#define SIO_GPIO_HI_OE_SET_LSB 0 -#define SIO_GPIO_HI_OE_SET_ACCESS "RW" +#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044) +#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_SET_MSB _u(5) +#define SIO_GPIO_HI_OE_SET_LSB _u(0) +#define SIO_GPIO_HI_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_CLR // Description : QSPI output enable clear // Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= // ~wdata` -#define SIO_GPIO_HI_OE_CLR_OFFSET 0x00000048 -#define SIO_GPIO_HI_OE_CLR_BITS 0x0000003f -#define SIO_GPIO_HI_OE_CLR_RESET 0x00000000 -#define SIO_GPIO_HI_OE_CLR_MSB 5 -#define SIO_GPIO_HI_OE_CLR_LSB 0 -#define SIO_GPIO_HI_OE_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048) +#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_CLR_MSB _u(5) +#define SIO_GPIO_HI_OE_CLR_LSB _u(0) +#define SIO_GPIO_HI_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_XOR // Description : QSPI output enable XOR // Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE // ^= wdata` -#define SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c -#define SIO_GPIO_HI_OE_XOR_BITS 0x0000003f -#define SIO_GPIO_HI_OE_XOR_RESET 0x00000000 -#define SIO_GPIO_HI_OE_XOR_MSB 5 -#define SIO_GPIO_HI_OE_XOR_LSB 0 -#define SIO_GPIO_HI_OE_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) +#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_XOR_MSB _u(5) +#define SIO_GPIO_HI_OE_XOR_LSB _u(0) +#define SIO_GPIO_HI_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_FIFO_ST // Description : Status register for inter-core FIFOs (mailboxes). @@ -252,73 +252,73 @@ // write side of 1->0 FIFO (TX). // The SIO IRQ for each core is the logical OR of the VLD, WOF and // ROE fields of its FIFO_ST register. -#define SIO_FIFO_ST_OFFSET 0x00000050 -#define SIO_FIFO_ST_BITS 0x0000000f -#define SIO_FIFO_ST_RESET 0x00000002 +#define SIO_FIFO_ST_OFFSET _u(0x00000050) +#define SIO_FIFO_ST_BITS _u(0x0000000f) +#define SIO_FIFO_ST_RESET _u(0x00000002) // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_ROE // Description : Sticky flag indicating the RX FIFO was read when empty. This // read was ignored by the FIFO. -#define SIO_FIFO_ST_ROE_RESET 0x0 -#define SIO_FIFO_ST_ROE_BITS 0x00000008 -#define SIO_FIFO_ST_ROE_MSB 3 -#define SIO_FIFO_ST_ROE_LSB 3 +#define SIO_FIFO_ST_ROE_RESET _u(0x0) +#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) +#define SIO_FIFO_ST_ROE_MSB _u(3) +#define SIO_FIFO_ST_ROE_LSB _u(3) #define SIO_FIFO_ST_ROE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_WOF // Description : Sticky flag indicating the TX FIFO was written when full. This // write was ignored by the FIFO. -#define SIO_FIFO_ST_WOF_RESET 0x0 -#define SIO_FIFO_ST_WOF_BITS 0x00000004 -#define SIO_FIFO_ST_WOF_MSB 2 -#define SIO_FIFO_ST_WOF_LSB 2 +#define SIO_FIFO_ST_WOF_RESET _u(0x0) +#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) +#define SIO_FIFO_ST_WOF_MSB _u(2) +#define SIO_FIFO_ST_WOF_LSB _u(2) #define SIO_FIFO_ST_WOF_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_RDY // Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR // is ready for more data) -#define SIO_FIFO_ST_RDY_RESET 0x1 -#define SIO_FIFO_ST_RDY_BITS 0x00000002 -#define SIO_FIFO_ST_RDY_MSB 1 -#define SIO_FIFO_ST_RDY_LSB 1 +#define SIO_FIFO_ST_RDY_RESET _u(0x1) +#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) +#define SIO_FIFO_ST_RDY_MSB _u(1) +#define SIO_FIFO_ST_RDY_LSB _u(1) #define SIO_FIFO_ST_RDY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_VLD // Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD // is valid) -#define SIO_FIFO_ST_VLD_RESET 0x0 -#define SIO_FIFO_ST_VLD_BITS 0x00000001 -#define SIO_FIFO_ST_VLD_MSB 0 -#define SIO_FIFO_ST_VLD_LSB 0 +#define SIO_FIFO_ST_VLD_RESET _u(0x0) +#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) +#define SIO_FIFO_ST_VLD_MSB _u(0) +#define SIO_FIFO_ST_VLD_LSB _u(0) #define SIO_FIFO_ST_VLD_ACCESS "RO" // ============================================================================= // Register : SIO_FIFO_WR // Description : Write access to this core's TX FIFO -#define SIO_FIFO_WR_OFFSET 0x00000054 -#define SIO_FIFO_WR_BITS 0xffffffff -#define SIO_FIFO_WR_RESET 0x00000000 -#define SIO_FIFO_WR_MSB 31 -#define SIO_FIFO_WR_LSB 0 +#define SIO_FIFO_WR_OFFSET _u(0x00000054) +#define SIO_FIFO_WR_BITS _u(0xffffffff) +#define SIO_FIFO_WR_RESET _u(0x00000000) +#define SIO_FIFO_WR_MSB _u(31) +#define SIO_FIFO_WR_LSB _u(0) #define SIO_FIFO_WR_ACCESS "WF" // ============================================================================= // Register : SIO_FIFO_RD // Description : Read access to this core's RX FIFO -#define SIO_FIFO_RD_OFFSET 0x00000058 -#define SIO_FIFO_RD_BITS 0xffffffff +#define SIO_FIFO_RD_OFFSET _u(0x00000058) +#define SIO_FIFO_RD_BITS _u(0xffffffff) #define SIO_FIFO_RD_RESET "-" -#define SIO_FIFO_RD_MSB 31 -#define SIO_FIFO_RD_LSB 0 +#define SIO_FIFO_RD_MSB _u(31) +#define SIO_FIFO_RD_LSB _u(0) #define SIO_FIFO_RD_ACCESS "RF" // ============================================================================= // Register : SIO_SPINLOCK_ST // Description : Spinlock state // A bitmap containing the state of all 32 spinlocks (1=locked). // Mainly intended for debugging. -#define SIO_SPINLOCK_ST_OFFSET 0x0000005c -#define SIO_SPINLOCK_ST_BITS 0xffffffff -#define SIO_SPINLOCK_ST_RESET 0x00000000 -#define SIO_SPINLOCK_ST_MSB 31 -#define SIO_SPINLOCK_ST_LSB 0 +#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) +#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) +#define SIO_SPINLOCK_ST_RESET _u(0x00000000) +#define SIO_SPINLOCK_ST_MSB _u(31) +#define SIO_SPINLOCK_ST_LSB _u(0) #define SIO_SPINLOCK_ST_ACCESS "RO" // ============================================================================= // Register : SIO_DIV_UDIVIDEND @@ -331,11 +331,11 @@ // The U alias starts an // unsigned calculation, and the S alias starts a signed // calculation. -#define SIO_DIV_UDIVIDEND_OFFSET 0x00000060 -#define SIO_DIV_UDIVIDEND_BITS 0xffffffff -#define SIO_DIV_UDIVIDEND_RESET 0x00000000 -#define SIO_DIV_UDIVIDEND_MSB 31 -#define SIO_DIV_UDIVIDEND_LSB 0 +#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060) +#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_UDIVIDEND_MSB _u(31) +#define SIO_DIV_UDIVIDEND_LSB _u(0) #define SIO_DIV_UDIVIDEND_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_UDIVISOR @@ -348,33 +348,33 @@ // The U alias starts an // unsigned calculation, and the S alias starts a signed // calculation. -#define SIO_DIV_UDIVISOR_OFFSET 0x00000064 -#define SIO_DIV_UDIVISOR_BITS 0xffffffff -#define SIO_DIV_UDIVISOR_RESET 0x00000000 -#define SIO_DIV_UDIVISOR_MSB 31 -#define SIO_DIV_UDIVISOR_LSB 0 +#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064) +#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_UDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_UDIVISOR_MSB _u(31) +#define SIO_DIV_UDIVISOR_LSB _u(0) #define SIO_DIV_UDIVISOR_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_SDIVIDEND // Description : Divider signed dividend // The same as UDIVIDEND, but starts a signed calculation, rather // than unsigned. -#define SIO_DIV_SDIVIDEND_OFFSET 0x00000068 -#define SIO_DIV_SDIVIDEND_BITS 0xffffffff -#define SIO_DIV_SDIVIDEND_RESET 0x00000000 -#define SIO_DIV_SDIVIDEND_MSB 31 -#define SIO_DIV_SDIVIDEND_LSB 0 +#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068) +#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_SDIVIDEND_MSB _u(31) +#define SIO_DIV_SDIVIDEND_LSB _u(0) #define SIO_DIV_SDIVIDEND_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_SDIVISOR // Description : Divider signed divisor // The same as UDIVISOR, but starts a signed calculation, rather // than unsigned. -#define SIO_DIV_SDIVISOR_OFFSET 0x0000006c -#define SIO_DIV_SDIVISOR_BITS 0xffffffff -#define SIO_DIV_SDIVISOR_RESET 0x00000000 -#define SIO_DIV_SDIVISOR_MSB 31 -#define SIO_DIV_SDIVISOR_LSB 0 +#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c) +#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_SDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_SDIVISOR_MSB _u(31) +#define SIO_DIV_SDIVISOR_LSB _u(0) #define SIO_DIV_SDIVISOR_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_QUOTIENT @@ -390,11 +390,11 @@ // Reading from QUOTIENT clears the CSR_DIRTY flag, so should read // results in the order // REMAINDER, QUOTIENT if CSR_DIRTY is used. -#define SIO_DIV_QUOTIENT_OFFSET 0x00000070 -#define SIO_DIV_QUOTIENT_BITS 0xffffffff -#define SIO_DIV_QUOTIENT_RESET 0x00000000 -#define SIO_DIV_QUOTIENT_MSB 31 -#define SIO_DIV_QUOTIENT_LSB 0 +#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070) +#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff) +#define SIO_DIV_QUOTIENT_RESET _u(0x00000000) +#define SIO_DIV_QUOTIENT_MSB _u(31) +#define SIO_DIV_QUOTIENT_LSB _u(0) #define SIO_DIV_QUOTIENT_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_REMAINDER @@ -407,18 +407,18 @@ // save/restore purposes. This halts any // in-progress calculation and sets the CSR_READY and CSR_DIRTY // flags. -#define SIO_DIV_REMAINDER_OFFSET 0x00000074 -#define SIO_DIV_REMAINDER_BITS 0xffffffff -#define SIO_DIV_REMAINDER_RESET 0x00000000 -#define SIO_DIV_REMAINDER_MSB 31 -#define SIO_DIV_REMAINDER_LSB 0 +#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074) +#define SIO_DIV_REMAINDER_BITS _u(0xffffffff) +#define SIO_DIV_REMAINDER_RESET _u(0x00000000) +#define SIO_DIV_REMAINDER_MSB _u(31) +#define SIO_DIV_REMAINDER_LSB _u(0) #define SIO_DIV_REMAINDER_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_CSR // Description : Control and status register for divider. -#define SIO_DIV_CSR_OFFSET 0x00000078 -#define SIO_DIV_CSR_BITS 0x00000003 -#define SIO_DIV_CSR_RESET 0x00000001 +#define SIO_DIV_CSR_OFFSET _u(0x00000078) +#define SIO_DIV_CSR_BITS _u(0x00000003) +#define SIO_DIV_CSR_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : SIO_DIV_CSR_DIRTY // Description : Changes to 1 when any register is written, and back to 0 when @@ -429,10 +429,10 @@ // read QUOTIENT only, // or REMAINDER and then QUOTIENT, to prevent data loss on context // switch. -#define SIO_DIV_CSR_DIRTY_RESET 0x0 -#define SIO_DIV_CSR_DIRTY_BITS 0x00000002 -#define SIO_DIV_CSR_DIRTY_MSB 1 -#define SIO_DIV_CSR_DIRTY_LSB 1 +#define SIO_DIV_CSR_DIRTY_RESET _u(0x0) +#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002) +#define SIO_DIV_CSR_DIRTY_MSB _u(1) +#define SIO_DIV_CSR_DIRTY_LSB _u(1) #define SIO_DIV_CSR_DIRTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_DIV_CSR_READY @@ -443,142 +443,142 @@ // Writing to a result register will immediately terminate any // in-progress calculation // and set the READY and DIRTY flags. -#define SIO_DIV_CSR_READY_RESET 0x1 -#define SIO_DIV_CSR_READY_BITS 0x00000001 -#define SIO_DIV_CSR_READY_MSB 0 -#define SIO_DIV_CSR_READY_LSB 0 +#define SIO_DIV_CSR_READY_RESET _u(0x1) +#define SIO_DIV_CSR_READY_BITS _u(0x00000001) +#define SIO_DIV_CSR_READY_MSB _u(0) +#define SIO_DIV_CSR_READY_LSB _u(0) #define SIO_DIV_CSR_READY_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_ACCUM0 // Description : Read/write access to accumulator 0 -#define SIO_INTERP0_ACCUM0_OFFSET 0x00000080 -#define SIO_INTERP0_ACCUM0_BITS 0xffffffff -#define SIO_INTERP0_ACCUM0_RESET 0x00000000 -#define SIO_INTERP0_ACCUM0_MSB 31 -#define SIO_INTERP0_ACCUM0_LSB 0 +#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) +#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_MSB _u(31) +#define SIO_INTERP0_ACCUM0_LSB _u(0) #define SIO_INTERP0_ACCUM0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM1 // Description : Read/write access to accumulator 1 -#define SIO_INTERP0_ACCUM1_OFFSET 0x00000084 -#define SIO_INTERP0_ACCUM1_BITS 0xffffffff -#define SIO_INTERP0_ACCUM1_RESET 0x00000000 -#define SIO_INTERP0_ACCUM1_MSB 31 -#define SIO_INTERP0_ACCUM1_LSB 0 +#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) +#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_MSB _u(31) +#define SIO_INTERP0_ACCUM1_LSB _u(0) #define SIO_INTERP0_ACCUM1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE0 // Description : Read/write access to BASE0 register. -#define SIO_INTERP0_BASE0_OFFSET 0x00000088 -#define SIO_INTERP0_BASE0_BITS 0xffffffff -#define SIO_INTERP0_BASE0_RESET 0x00000000 -#define SIO_INTERP0_BASE0_MSB 31 -#define SIO_INTERP0_BASE0_LSB 0 +#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) +#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE0_MSB _u(31) +#define SIO_INTERP0_BASE0_LSB _u(0) #define SIO_INTERP0_BASE0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE1 // Description : Read/write access to BASE1 register. -#define SIO_INTERP0_BASE1_OFFSET 0x0000008c -#define SIO_INTERP0_BASE1_BITS 0xffffffff -#define SIO_INTERP0_BASE1_RESET 0x00000000 -#define SIO_INTERP0_BASE1_MSB 31 -#define SIO_INTERP0_BASE1_LSB 0 +#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) +#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE1_RESET _u(0x00000000) +#define SIO_INTERP0_BASE1_MSB _u(31) +#define SIO_INTERP0_BASE1_LSB _u(0) #define SIO_INTERP0_BASE1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE2 // Description : Read/write access to BASE2 register. -#define SIO_INTERP0_BASE2_OFFSET 0x00000090 -#define SIO_INTERP0_BASE2_BITS 0xffffffff -#define SIO_INTERP0_BASE2_RESET 0x00000000 -#define SIO_INTERP0_BASE2_MSB 31 -#define SIO_INTERP0_BASE2_LSB 0 +#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) +#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE2_RESET _u(0x00000000) +#define SIO_INTERP0_BASE2_MSB _u(31) +#define SIO_INTERP0_BASE2_LSB _u(0) #define SIO_INTERP0_BASE2_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_POP_LANE0 // Description : Read LANE0 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP0_POP_LANE0_OFFSET 0x00000094 -#define SIO_INTERP0_POP_LANE0_BITS 0xffffffff -#define SIO_INTERP0_POP_LANE0_RESET 0x00000000 -#define SIO_INTERP0_POP_LANE0_MSB 31 -#define SIO_INTERP0_POP_LANE0_LSB 0 +#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) +#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE0_MSB _u(31) +#define SIO_INTERP0_POP_LANE0_LSB _u(0) #define SIO_INTERP0_POP_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_POP_LANE1 // Description : Read LANE1 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP0_POP_LANE1_OFFSET 0x00000098 -#define SIO_INTERP0_POP_LANE1_BITS 0xffffffff -#define SIO_INTERP0_POP_LANE1_RESET 0x00000000 -#define SIO_INTERP0_POP_LANE1_MSB 31 -#define SIO_INTERP0_POP_LANE1_LSB 0 +#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) +#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE1_MSB _u(31) +#define SIO_INTERP0_POP_LANE1_LSB _u(0) #define SIO_INTERP0_POP_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_POP_FULL // Description : Read FULL result, and simultaneously write lane results to both // accumulators (POP). -#define SIO_INTERP0_POP_FULL_OFFSET 0x0000009c -#define SIO_INTERP0_POP_FULL_BITS 0xffffffff -#define SIO_INTERP0_POP_FULL_RESET 0x00000000 -#define SIO_INTERP0_POP_FULL_MSB 31 -#define SIO_INTERP0_POP_FULL_LSB 0 +#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) +#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_POP_FULL_MSB _u(31) +#define SIO_INTERP0_POP_FULL_LSB _u(0) #define SIO_INTERP0_POP_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_LANE0 // Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0 -#define SIO_INTERP0_PEEK_LANE0_BITS 0xffffffff -#define SIO_INTERP0_PEEK_LANE0_RESET 0x00000000 -#define SIO_INTERP0_PEEK_LANE0_MSB 31 -#define SIO_INTERP0_PEEK_LANE0_LSB 0 +#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) +#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) #define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_LANE1 // Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4 -#define SIO_INTERP0_PEEK_LANE1_BITS 0xffffffff -#define SIO_INTERP0_PEEK_LANE1_RESET 0x00000000 -#define SIO_INTERP0_PEEK_LANE1_MSB 31 -#define SIO_INTERP0_PEEK_LANE1_LSB 0 +#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) +#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) #define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_FULL // Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8 -#define SIO_INTERP0_PEEK_FULL_BITS 0xffffffff -#define SIO_INTERP0_PEEK_FULL_RESET 0x00000000 -#define SIO_INTERP0_PEEK_FULL_MSB 31 -#define SIO_INTERP0_PEEK_FULL_LSB 0 +#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) +#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_FULL_MSB _u(31) +#define SIO_INTERP0_PEEK_FULL_LSB _u(0) #define SIO_INTERP0_PEEK_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_CTRL_LANE0 // Description : Control register for lane 0 -#define SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac -#define SIO_INTERP0_CTRL_LANE0_BITS 0x03bfffff -#define SIO_INTERP0_CTRL_LANE0_RESET 0x00000000 +#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) +#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) +#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF // Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS 0x02000000 -#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB 25 -#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) #define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF1 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS 0x01000000 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB 24 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) #define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF0 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS 0x00800000 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB 23 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) #define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_BLEND @@ -594,10 +594,10 @@ // (BASE2 + lane 0 shift+mask) // LANE1 SIGNED flag controls whether the interpolation is signed // or unsigned. -#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS 0x00200000 -#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB 21 -#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) #define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB @@ -606,28 +606,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB 20 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE0 result. This does not // affect FULL result. -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB 18 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB 17 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT @@ -635,10 +635,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB 16 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_SIGNED @@ -646,44 +646,44 @@ // sign-extended to 32 bits // before adding to BASE0, and LANE0 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS 0x00008000 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB 15 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) #define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB 14 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB 9 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS 0x0000001f -#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB 4 -#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) #define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_CTRL_LANE1 // Description : Control register for lane 1 -#define SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0 -#define SIO_INTERP0_CTRL_LANE1_BITS 0x001fffff -#define SIO_INTERP0_CTRL_LANE1_RESET 0x00000000 +#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) +#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB // Description : ORed into bits 29:28 of the lane result presented to the @@ -691,28 +691,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB 20 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE1 result. This does not // affect FULL result. -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB 18 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB 17 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT @@ -720,10 +720,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB 16 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_SIGNED @@ -731,59 +731,59 @@ // sign-extended to 32 bits // before adding to BASE1, and LANE1 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS 0x00008000 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB 15 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) #define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB 14 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB 9 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS 0x0000001f -#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB 4 -#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) #define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM0_ADD // Description : Values written here are atomically added to ACCUM0 // Reading yields lane 0's raw shift and mask value (BASE0 not // added). -#define SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4 -#define SIO_INTERP0_ACCUM0_ADD_BITS 0x00ffffff -#define SIO_INTERP0_ACCUM0_ADD_RESET 0x00000000 -#define SIO_INTERP0_ACCUM0_ADD_MSB 23 -#define SIO_INTERP0_ACCUM0_ADD_LSB 0 +#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) +#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) #define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM1_ADD // Description : Values written here are atomically added to ACCUM1 // Reading yields lane 1's raw shift and mask value (BASE1 not // added). -#define SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8 -#define SIO_INTERP0_ACCUM1_ADD_BITS 0x00ffffff -#define SIO_INTERP0_ACCUM1_ADD_RESET 0x00000000 -#define SIO_INTERP0_ACCUM1_ADD_MSB 23 -#define SIO_INTERP0_ACCUM1_ADD_LSB 0 +#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) +#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) #define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE_1AND0 @@ -791,143 +791,143 @@ // simultaneously. // Each half is sign-extended to 32 bits if that lane's SIGNED // flag is set. -#define SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc -#define SIO_INTERP0_BASE_1AND0_BITS 0xffffffff -#define SIO_INTERP0_BASE_1AND0_RESET 0x00000000 -#define SIO_INTERP0_BASE_1AND0_MSB 31 -#define SIO_INTERP0_BASE_1AND0_LSB 0 +#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) +#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE_1AND0_MSB _u(31) +#define SIO_INTERP0_BASE_1AND0_LSB _u(0) #define SIO_INTERP0_BASE_1AND0_ACCESS "WO" // ============================================================================= // Register : SIO_INTERP1_ACCUM0 // Description : Read/write access to accumulator 0 -#define SIO_INTERP1_ACCUM0_OFFSET 0x000000c0 -#define SIO_INTERP1_ACCUM0_BITS 0xffffffff -#define SIO_INTERP1_ACCUM0_RESET 0x00000000 -#define SIO_INTERP1_ACCUM0_MSB 31 -#define SIO_INTERP1_ACCUM0_LSB 0 +#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) +#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_MSB _u(31) +#define SIO_INTERP1_ACCUM0_LSB _u(0) #define SIO_INTERP1_ACCUM0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM1 // Description : Read/write access to accumulator 1 -#define SIO_INTERP1_ACCUM1_OFFSET 0x000000c4 -#define SIO_INTERP1_ACCUM1_BITS 0xffffffff -#define SIO_INTERP1_ACCUM1_RESET 0x00000000 -#define SIO_INTERP1_ACCUM1_MSB 31 -#define SIO_INTERP1_ACCUM1_LSB 0 +#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) +#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_MSB _u(31) +#define SIO_INTERP1_ACCUM1_LSB _u(0) #define SIO_INTERP1_ACCUM1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE0 // Description : Read/write access to BASE0 register. -#define SIO_INTERP1_BASE0_OFFSET 0x000000c8 -#define SIO_INTERP1_BASE0_BITS 0xffffffff -#define SIO_INTERP1_BASE0_RESET 0x00000000 -#define SIO_INTERP1_BASE0_MSB 31 -#define SIO_INTERP1_BASE0_LSB 0 +#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) +#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE0_MSB _u(31) +#define SIO_INTERP1_BASE0_LSB _u(0) #define SIO_INTERP1_BASE0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE1 // Description : Read/write access to BASE1 register. -#define SIO_INTERP1_BASE1_OFFSET 0x000000cc -#define SIO_INTERP1_BASE1_BITS 0xffffffff -#define SIO_INTERP1_BASE1_RESET 0x00000000 -#define SIO_INTERP1_BASE1_MSB 31 -#define SIO_INTERP1_BASE1_LSB 0 +#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) +#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE1_RESET _u(0x00000000) +#define SIO_INTERP1_BASE1_MSB _u(31) +#define SIO_INTERP1_BASE1_LSB _u(0) #define SIO_INTERP1_BASE1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE2 // Description : Read/write access to BASE2 register. -#define SIO_INTERP1_BASE2_OFFSET 0x000000d0 -#define SIO_INTERP1_BASE2_BITS 0xffffffff -#define SIO_INTERP1_BASE2_RESET 0x00000000 -#define SIO_INTERP1_BASE2_MSB 31 -#define SIO_INTERP1_BASE2_LSB 0 +#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) +#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE2_RESET _u(0x00000000) +#define SIO_INTERP1_BASE2_MSB _u(31) +#define SIO_INTERP1_BASE2_LSB _u(0) #define SIO_INTERP1_BASE2_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_POP_LANE0 // Description : Read LANE0 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4 -#define SIO_INTERP1_POP_LANE0_BITS 0xffffffff -#define SIO_INTERP1_POP_LANE0_RESET 0x00000000 -#define SIO_INTERP1_POP_LANE0_MSB 31 -#define SIO_INTERP1_POP_LANE0_LSB 0 +#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) +#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE0_MSB _u(31) +#define SIO_INTERP1_POP_LANE0_LSB _u(0) #define SIO_INTERP1_POP_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_POP_LANE1 // Description : Read LANE1 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8 -#define SIO_INTERP1_POP_LANE1_BITS 0xffffffff -#define SIO_INTERP1_POP_LANE1_RESET 0x00000000 -#define SIO_INTERP1_POP_LANE1_MSB 31 -#define SIO_INTERP1_POP_LANE1_LSB 0 +#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) +#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE1_MSB _u(31) +#define SIO_INTERP1_POP_LANE1_LSB _u(0) #define SIO_INTERP1_POP_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_POP_FULL // Description : Read FULL result, and simultaneously write lane results to both // accumulators (POP). -#define SIO_INTERP1_POP_FULL_OFFSET 0x000000dc -#define SIO_INTERP1_POP_FULL_BITS 0xffffffff -#define SIO_INTERP1_POP_FULL_RESET 0x00000000 -#define SIO_INTERP1_POP_FULL_MSB 31 -#define SIO_INTERP1_POP_FULL_LSB 0 +#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) +#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_POP_FULL_MSB _u(31) +#define SIO_INTERP1_POP_FULL_LSB _u(0) #define SIO_INTERP1_POP_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_LANE0 // Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0 -#define SIO_INTERP1_PEEK_LANE0_BITS 0xffffffff -#define SIO_INTERP1_PEEK_LANE0_RESET 0x00000000 -#define SIO_INTERP1_PEEK_LANE0_MSB 31 -#define SIO_INTERP1_PEEK_LANE0_LSB 0 +#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) +#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) #define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_LANE1 // Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4 -#define SIO_INTERP1_PEEK_LANE1_BITS 0xffffffff -#define SIO_INTERP1_PEEK_LANE1_RESET 0x00000000 -#define SIO_INTERP1_PEEK_LANE1_MSB 31 -#define SIO_INTERP1_PEEK_LANE1_LSB 0 +#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) +#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) #define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_FULL // Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8 -#define SIO_INTERP1_PEEK_FULL_BITS 0xffffffff -#define SIO_INTERP1_PEEK_FULL_RESET 0x00000000 -#define SIO_INTERP1_PEEK_FULL_MSB 31 -#define SIO_INTERP1_PEEK_FULL_LSB 0 +#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) +#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_FULL_MSB _u(31) +#define SIO_INTERP1_PEEK_FULL_LSB _u(0) #define SIO_INTERP1_PEEK_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_CTRL_LANE0 // Description : Control register for lane 0 -#define SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec -#define SIO_INTERP1_CTRL_LANE0_BITS 0x03dfffff -#define SIO_INTERP1_CTRL_LANE0_RESET 0x00000000 +#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) +#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) +#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF // Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS 0x02000000 -#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB 25 -#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) #define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF1 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS 0x01000000 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB 24 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) #define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF0 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS 0x00800000 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB 23 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) #define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CLAMP @@ -937,10 +937,10 @@ // BASE0 and an upper bound of BASE1. // - Signedness of these comparisons is determined by // LANE0_CTRL_SIGNED -#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS 0x00400000 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB 22 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) #define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB @@ -949,28 +949,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB 20 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE0 result. This does not // affect FULL result. -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB 18 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB 17 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT @@ -978,10 +978,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB 16 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_SIGNED @@ -989,44 +989,44 @@ // sign-extended to 32 bits // before adding to BASE0, and LANE0 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS 0x00008000 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB 15 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) #define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB 14 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB 9 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS 0x0000001f -#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB 4 -#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) #define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_CTRL_LANE1 // Description : Control register for lane 1 -#define SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0 -#define SIO_INTERP1_CTRL_LANE1_BITS 0x001fffff -#define SIO_INTERP1_CTRL_LANE1_RESET 0x00000000 +#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) +#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB // Description : ORed into bits 29:28 of the lane result presented to the @@ -1034,28 +1034,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB 20 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE1 result. This does not // affect FULL result. -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB 18 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB 17 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT @@ -1063,10 +1063,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB 16 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_SIGNED @@ -1074,59 +1074,59 @@ // sign-extended to 32 bits // before adding to BASE1, and LANE1 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS 0x00008000 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB 15 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) #define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB 14 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB 9 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS 0x0000001f -#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB 4 -#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) #define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM0_ADD // Description : Values written here are atomically added to ACCUM0 // Reading yields lane 0's raw shift and mask value (BASE0 not // added). -#define SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4 -#define SIO_INTERP1_ACCUM0_ADD_BITS 0x00ffffff -#define SIO_INTERP1_ACCUM0_ADD_RESET 0x00000000 -#define SIO_INTERP1_ACCUM0_ADD_MSB 23 -#define SIO_INTERP1_ACCUM0_ADD_LSB 0 +#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) +#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) #define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM1_ADD // Description : Values written here are atomically added to ACCUM1 // Reading yields lane 1's raw shift and mask value (BASE1 not // added). -#define SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8 -#define SIO_INTERP1_ACCUM1_ADD_BITS 0x00ffffff -#define SIO_INTERP1_ACCUM1_ADD_RESET 0x00000000 -#define SIO_INTERP1_ACCUM1_ADD_MSB 23 -#define SIO_INTERP1_ACCUM1_ADD_LSB 0 +#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) +#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) #define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE_1AND0 @@ -1134,11 +1134,11 @@ // simultaneously. // Each half is sign-extended to 32 bits if that lane's SIGNED // flag is set. -#define SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc -#define SIO_INTERP1_BASE_1AND0_BITS 0xffffffff -#define SIO_INTERP1_BASE_1AND0_RESET 0x00000000 -#define SIO_INTERP1_BASE_1AND0_MSB 31 -#define SIO_INTERP1_BASE_1AND0_LSB 0 +#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) +#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE_1AND0_MSB _u(31) +#define SIO_INTERP1_BASE_1AND0_LSB _u(0) #define SIO_INTERP1_BASE_1AND0_ACCESS "WO" // ============================================================================= // Register : SIO_SPINLOCK0 @@ -1150,12 +1150,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK0_OFFSET 0x00000100 -#define SIO_SPINLOCK0_BITS 0xffffffff -#define SIO_SPINLOCK0_RESET 0x00000000 -#define SIO_SPINLOCK0_MSB 31 -#define SIO_SPINLOCK0_LSB 0 -#define SIO_SPINLOCK0_ACCESS "RO" +#define SIO_SPINLOCK0_OFFSET _u(0x00000100) +#define SIO_SPINLOCK0_BITS _u(0xffffffff) +#define SIO_SPINLOCK0_RESET _u(0x00000000) +#define SIO_SPINLOCK0_MSB _u(31) +#define SIO_SPINLOCK0_LSB _u(0) +#define SIO_SPINLOCK0_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK1 // Description : Reading from a spinlock address will: @@ -1166,12 +1166,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK1_OFFSET 0x00000104 -#define SIO_SPINLOCK1_BITS 0xffffffff -#define SIO_SPINLOCK1_RESET 0x00000000 -#define SIO_SPINLOCK1_MSB 31 -#define SIO_SPINLOCK1_LSB 0 -#define SIO_SPINLOCK1_ACCESS "RO" +#define SIO_SPINLOCK1_OFFSET _u(0x00000104) +#define SIO_SPINLOCK1_BITS _u(0xffffffff) +#define SIO_SPINLOCK1_RESET _u(0x00000000) +#define SIO_SPINLOCK1_MSB _u(31) +#define SIO_SPINLOCK1_LSB _u(0) +#define SIO_SPINLOCK1_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK2 // Description : Reading from a spinlock address will: @@ -1182,12 +1182,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK2_OFFSET 0x00000108 -#define SIO_SPINLOCK2_BITS 0xffffffff -#define SIO_SPINLOCK2_RESET 0x00000000 -#define SIO_SPINLOCK2_MSB 31 -#define SIO_SPINLOCK2_LSB 0 -#define SIO_SPINLOCK2_ACCESS "RO" +#define SIO_SPINLOCK2_OFFSET _u(0x00000108) +#define SIO_SPINLOCK2_BITS _u(0xffffffff) +#define SIO_SPINLOCK2_RESET _u(0x00000000) +#define SIO_SPINLOCK2_MSB _u(31) +#define SIO_SPINLOCK2_LSB _u(0) +#define SIO_SPINLOCK2_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK3 // Description : Reading from a spinlock address will: @@ -1198,12 +1198,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK3_OFFSET 0x0000010c -#define SIO_SPINLOCK3_BITS 0xffffffff -#define SIO_SPINLOCK3_RESET 0x00000000 -#define SIO_SPINLOCK3_MSB 31 -#define SIO_SPINLOCK3_LSB 0 -#define SIO_SPINLOCK3_ACCESS "RO" +#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) +#define SIO_SPINLOCK3_BITS _u(0xffffffff) +#define SIO_SPINLOCK3_RESET _u(0x00000000) +#define SIO_SPINLOCK3_MSB _u(31) +#define SIO_SPINLOCK3_LSB _u(0) +#define SIO_SPINLOCK3_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK4 // Description : Reading from a spinlock address will: @@ -1214,12 +1214,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK4_OFFSET 0x00000110 -#define SIO_SPINLOCK4_BITS 0xffffffff -#define SIO_SPINLOCK4_RESET 0x00000000 -#define SIO_SPINLOCK4_MSB 31 -#define SIO_SPINLOCK4_LSB 0 -#define SIO_SPINLOCK4_ACCESS "RO" +#define SIO_SPINLOCK4_OFFSET _u(0x00000110) +#define SIO_SPINLOCK4_BITS _u(0xffffffff) +#define SIO_SPINLOCK4_RESET _u(0x00000000) +#define SIO_SPINLOCK4_MSB _u(31) +#define SIO_SPINLOCK4_LSB _u(0) +#define SIO_SPINLOCK4_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK5 // Description : Reading from a spinlock address will: @@ -1230,12 +1230,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK5_OFFSET 0x00000114 -#define SIO_SPINLOCK5_BITS 0xffffffff -#define SIO_SPINLOCK5_RESET 0x00000000 -#define SIO_SPINLOCK5_MSB 31 -#define SIO_SPINLOCK5_LSB 0 -#define SIO_SPINLOCK5_ACCESS "RO" +#define SIO_SPINLOCK5_OFFSET _u(0x00000114) +#define SIO_SPINLOCK5_BITS _u(0xffffffff) +#define SIO_SPINLOCK5_RESET _u(0x00000000) +#define SIO_SPINLOCK5_MSB _u(31) +#define SIO_SPINLOCK5_LSB _u(0) +#define SIO_SPINLOCK5_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK6 // Description : Reading from a spinlock address will: @@ -1246,12 +1246,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK6_OFFSET 0x00000118 -#define SIO_SPINLOCK6_BITS 0xffffffff -#define SIO_SPINLOCK6_RESET 0x00000000 -#define SIO_SPINLOCK6_MSB 31 -#define SIO_SPINLOCK6_LSB 0 -#define SIO_SPINLOCK6_ACCESS "RO" +#define SIO_SPINLOCK6_OFFSET _u(0x00000118) +#define SIO_SPINLOCK6_BITS _u(0xffffffff) +#define SIO_SPINLOCK6_RESET _u(0x00000000) +#define SIO_SPINLOCK6_MSB _u(31) +#define SIO_SPINLOCK6_LSB _u(0) +#define SIO_SPINLOCK6_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK7 // Description : Reading from a spinlock address will: @@ -1262,12 +1262,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK7_OFFSET 0x0000011c -#define SIO_SPINLOCK7_BITS 0xffffffff -#define SIO_SPINLOCK7_RESET 0x00000000 -#define SIO_SPINLOCK7_MSB 31 -#define SIO_SPINLOCK7_LSB 0 -#define SIO_SPINLOCK7_ACCESS "RO" +#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) +#define SIO_SPINLOCK7_BITS _u(0xffffffff) +#define SIO_SPINLOCK7_RESET _u(0x00000000) +#define SIO_SPINLOCK7_MSB _u(31) +#define SIO_SPINLOCK7_LSB _u(0) +#define SIO_SPINLOCK7_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK8 // Description : Reading from a spinlock address will: @@ -1278,12 +1278,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK8_OFFSET 0x00000120 -#define SIO_SPINLOCK8_BITS 0xffffffff -#define SIO_SPINLOCK8_RESET 0x00000000 -#define SIO_SPINLOCK8_MSB 31 -#define SIO_SPINLOCK8_LSB 0 -#define SIO_SPINLOCK8_ACCESS "RO" +#define SIO_SPINLOCK8_OFFSET _u(0x00000120) +#define SIO_SPINLOCK8_BITS _u(0xffffffff) +#define SIO_SPINLOCK8_RESET _u(0x00000000) +#define SIO_SPINLOCK8_MSB _u(31) +#define SIO_SPINLOCK8_LSB _u(0) +#define SIO_SPINLOCK8_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK9 // Description : Reading from a spinlock address will: @@ -1294,12 +1294,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK9_OFFSET 0x00000124 -#define SIO_SPINLOCK9_BITS 0xffffffff -#define SIO_SPINLOCK9_RESET 0x00000000 -#define SIO_SPINLOCK9_MSB 31 -#define SIO_SPINLOCK9_LSB 0 -#define SIO_SPINLOCK9_ACCESS "RO" +#define SIO_SPINLOCK9_OFFSET _u(0x00000124) +#define SIO_SPINLOCK9_BITS _u(0xffffffff) +#define SIO_SPINLOCK9_RESET _u(0x00000000) +#define SIO_SPINLOCK9_MSB _u(31) +#define SIO_SPINLOCK9_LSB _u(0) +#define SIO_SPINLOCK9_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK10 // Description : Reading from a spinlock address will: @@ -1310,12 +1310,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK10_OFFSET 0x00000128 -#define SIO_SPINLOCK10_BITS 0xffffffff -#define SIO_SPINLOCK10_RESET 0x00000000 -#define SIO_SPINLOCK10_MSB 31 -#define SIO_SPINLOCK10_LSB 0 -#define SIO_SPINLOCK10_ACCESS "RO" +#define SIO_SPINLOCK10_OFFSET _u(0x00000128) +#define SIO_SPINLOCK10_BITS _u(0xffffffff) +#define SIO_SPINLOCK10_RESET _u(0x00000000) +#define SIO_SPINLOCK10_MSB _u(31) +#define SIO_SPINLOCK10_LSB _u(0) +#define SIO_SPINLOCK10_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK11 // Description : Reading from a spinlock address will: @@ -1326,12 +1326,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK11_OFFSET 0x0000012c -#define SIO_SPINLOCK11_BITS 0xffffffff -#define SIO_SPINLOCK11_RESET 0x00000000 -#define SIO_SPINLOCK11_MSB 31 -#define SIO_SPINLOCK11_LSB 0 -#define SIO_SPINLOCK11_ACCESS "RO" +#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) +#define SIO_SPINLOCK11_BITS _u(0xffffffff) +#define SIO_SPINLOCK11_RESET _u(0x00000000) +#define SIO_SPINLOCK11_MSB _u(31) +#define SIO_SPINLOCK11_LSB _u(0) +#define SIO_SPINLOCK11_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK12 // Description : Reading from a spinlock address will: @@ -1342,12 +1342,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK12_OFFSET 0x00000130 -#define SIO_SPINLOCK12_BITS 0xffffffff -#define SIO_SPINLOCK12_RESET 0x00000000 -#define SIO_SPINLOCK12_MSB 31 -#define SIO_SPINLOCK12_LSB 0 -#define SIO_SPINLOCK12_ACCESS "RO" +#define SIO_SPINLOCK12_OFFSET _u(0x00000130) +#define SIO_SPINLOCK12_BITS _u(0xffffffff) +#define SIO_SPINLOCK12_RESET _u(0x00000000) +#define SIO_SPINLOCK12_MSB _u(31) +#define SIO_SPINLOCK12_LSB _u(0) +#define SIO_SPINLOCK12_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK13 // Description : Reading from a spinlock address will: @@ -1358,12 +1358,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK13_OFFSET 0x00000134 -#define SIO_SPINLOCK13_BITS 0xffffffff -#define SIO_SPINLOCK13_RESET 0x00000000 -#define SIO_SPINLOCK13_MSB 31 -#define SIO_SPINLOCK13_LSB 0 -#define SIO_SPINLOCK13_ACCESS "RO" +#define SIO_SPINLOCK13_OFFSET _u(0x00000134) +#define SIO_SPINLOCK13_BITS _u(0xffffffff) +#define SIO_SPINLOCK13_RESET _u(0x00000000) +#define SIO_SPINLOCK13_MSB _u(31) +#define SIO_SPINLOCK13_LSB _u(0) +#define SIO_SPINLOCK13_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK14 // Description : Reading from a spinlock address will: @@ -1374,12 +1374,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK14_OFFSET 0x00000138 -#define SIO_SPINLOCK14_BITS 0xffffffff -#define SIO_SPINLOCK14_RESET 0x00000000 -#define SIO_SPINLOCK14_MSB 31 -#define SIO_SPINLOCK14_LSB 0 -#define SIO_SPINLOCK14_ACCESS "RO" +#define SIO_SPINLOCK14_OFFSET _u(0x00000138) +#define SIO_SPINLOCK14_BITS _u(0xffffffff) +#define SIO_SPINLOCK14_RESET _u(0x00000000) +#define SIO_SPINLOCK14_MSB _u(31) +#define SIO_SPINLOCK14_LSB _u(0) +#define SIO_SPINLOCK14_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK15 // Description : Reading from a spinlock address will: @@ -1390,12 +1390,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK15_OFFSET 0x0000013c -#define SIO_SPINLOCK15_BITS 0xffffffff -#define SIO_SPINLOCK15_RESET 0x00000000 -#define SIO_SPINLOCK15_MSB 31 -#define SIO_SPINLOCK15_LSB 0 -#define SIO_SPINLOCK15_ACCESS "RO" +#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) +#define SIO_SPINLOCK15_BITS _u(0xffffffff) +#define SIO_SPINLOCK15_RESET _u(0x00000000) +#define SIO_SPINLOCK15_MSB _u(31) +#define SIO_SPINLOCK15_LSB _u(0) +#define SIO_SPINLOCK15_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK16 // Description : Reading from a spinlock address will: @@ -1406,12 +1406,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK16_OFFSET 0x00000140 -#define SIO_SPINLOCK16_BITS 0xffffffff -#define SIO_SPINLOCK16_RESET 0x00000000 -#define SIO_SPINLOCK16_MSB 31 -#define SIO_SPINLOCK16_LSB 0 -#define SIO_SPINLOCK16_ACCESS "RO" +#define SIO_SPINLOCK16_OFFSET _u(0x00000140) +#define SIO_SPINLOCK16_BITS _u(0xffffffff) +#define SIO_SPINLOCK16_RESET _u(0x00000000) +#define SIO_SPINLOCK16_MSB _u(31) +#define SIO_SPINLOCK16_LSB _u(0) +#define SIO_SPINLOCK16_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK17 // Description : Reading from a spinlock address will: @@ -1422,12 +1422,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK17_OFFSET 0x00000144 -#define SIO_SPINLOCK17_BITS 0xffffffff -#define SIO_SPINLOCK17_RESET 0x00000000 -#define SIO_SPINLOCK17_MSB 31 -#define SIO_SPINLOCK17_LSB 0 -#define SIO_SPINLOCK17_ACCESS "RO" +#define SIO_SPINLOCK17_OFFSET _u(0x00000144) +#define SIO_SPINLOCK17_BITS _u(0xffffffff) +#define SIO_SPINLOCK17_RESET _u(0x00000000) +#define SIO_SPINLOCK17_MSB _u(31) +#define SIO_SPINLOCK17_LSB _u(0) +#define SIO_SPINLOCK17_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK18 // Description : Reading from a spinlock address will: @@ -1438,12 +1438,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK18_OFFSET 0x00000148 -#define SIO_SPINLOCK18_BITS 0xffffffff -#define SIO_SPINLOCK18_RESET 0x00000000 -#define SIO_SPINLOCK18_MSB 31 -#define SIO_SPINLOCK18_LSB 0 -#define SIO_SPINLOCK18_ACCESS "RO" +#define SIO_SPINLOCK18_OFFSET _u(0x00000148) +#define SIO_SPINLOCK18_BITS _u(0xffffffff) +#define SIO_SPINLOCK18_RESET _u(0x00000000) +#define SIO_SPINLOCK18_MSB _u(31) +#define SIO_SPINLOCK18_LSB _u(0) +#define SIO_SPINLOCK18_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK19 // Description : Reading from a spinlock address will: @@ -1454,12 +1454,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK19_OFFSET 0x0000014c -#define SIO_SPINLOCK19_BITS 0xffffffff -#define SIO_SPINLOCK19_RESET 0x00000000 -#define SIO_SPINLOCK19_MSB 31 -#define SIO_SPINLOCK19_LSB 0 -#define SIO_SPINLOCK19_ACCESS "RO" +#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) +#define SIO_SPINLOCK19_BITS _u(0xffffffff) +#define SIO_SPINLOCK19_RESET _u(0x00000000) +#define SIO_SPINLOCK19_MSB _u(31) +#define SIO_SPINLOCK19_LSB _u(0) +#define SIO_SPINLOCK19_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK20 // Description : Reading from a spinlock address will: @@ -1470,12 +1470,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK20_OFFSET 0x00000150 -#define SIO_SPINLOCK20_BITS 0xffffffff -#define SIO_SPINLOCK20_RESET 0x00000000 -#define SIO_SPINLOCK20_MSB 31 -#define SIO_SPINLOCK20_LSB 0 -#define SIO_SPINLOCK20_ACCESS "RO" +#define SIO_SPINLOCK20_OFFSET _u(0x00000150) +#define SIO_SPINLOCK20_BITS _u(0xffffffff) +#define SIO_SPINLOCK20_RESET _u(0x00000000) +#define SIO_SPINLOCK20_MSB _u(31) +#define SIO_SPINLOCK20_LSB _u(0) +#define SIO_SPINLOCK20_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK21 // Description : Reading from a spinlock address will: @@ -1486,12 +1486,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK21_OFFSET 0x00000154 -#define SIO_SPINLOCK21_BITS 0xffffffff -#define SIO_SPINLOCK21_RESET 0x00000000 -#define SIO_SPINLOCK21_MSB 31 -#define SIO_SPINLOCK21_LSB 0 -#define SIO_SPINLOCK21_ACCESS "RO" +#define SIO_SPINLOCK21_OFFSET _u(0x00000154) +#define SIO_SPINLOCK21_BITS _u(0xffffffff) +#define SIO_SPINLOCK21_RESET _u(0x00000000) +#define SIO_SPINLOCK21_MSB _u(31) +#define SIO_SPINLOCK21_LSB _u(0) +#define SIO_SPINLOCK21_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK22 // Description : Reading from a spinlock address will: @@ -1502,12 +1502,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK22_OFFSET 0x00000158 -#define SIO_SPINLOCK22_BITS 0xffffffff -#define SIO_SPINLOCK22_RESET 0x00000000 -#define SIO_SPINLOCK22_MSB 31 -#define SIO_SPINLOCK22_LSB 0 -#define SIO_SPINLOCK22_ACCESS "RO" +#define SIO_SPINLOCK22_OFFSET _u(0x00000158) +#define SIO_SPINLOCK22_BITS _u(0xffffffff) +#define SIO_SPINLOCK22_RESET _u(0x00000000) +#define SIO_SPINLOCK22_MSB _u(31) +#define SIO_SPINLOCK22_LSB _u(0) +#define SIO_SPINLOCK22_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK23 // Description : Reading from a spinlock address will: @@ -1518,12 +1518,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK23_OFFSET 0x0000015c -#define SIO_SPINLOCK23_BITS 0xffffffff -#define SIO_SPINLOCK23_RESET 0x00000000 -#define SIO_SPINLOCK23_MSB 31 -#define SIO_SPINLOCK23_LSB 0 -#define SIO_SPINLOCK23_ACCESS "RO" +#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) +#define SIO_SPINLOCK23_BITS _u(0xffffffff) +#define SIO_SPINLOCK23_RESET _u(0x00000000) +#define SIO_SPINLOCK23_MSB _u(31) +#define SIO_SPINLOCK23_LSB _u(0) +#define SIO_SPINLOCK23_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK24 // Description : Reading from a spinlock address will: @@ -1534,12 +1534,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK24_OFFSET 0x00000160 -#define SIO_SPINLOCK24_BITS 0xffffffff -#define SIO_SPINLOCK24_RESET 0x00000000 -#define SIO_SPINLOCK24_MSB 31 -#define SIO_SPINLOCK24_LSB 0 -#define SIO_SPINLOCK24_ACCESS "RO" +#define SIO_SPINLOCK24_OFFSET _u(0x00000160) +#define SIO_SPINLOCK24_BITS _u(0xffffffff) +#define SIO_SPINLOCK24_RESET _u(0x00000000) +#define SIO_SPINLOCK24_MSB _u(31) +#define SIO_SPINLOCK24_LSB _u(0) +#define SIO_SPINLOCK24_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK25 // Description : Reading from a spinlock address will: @@ -1550,12 +1550,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK25_OFFSET 0x00000164 -#define SIO_SPINLOCK25_BITS 0xffffffff -#define SIO_SPINLOCK25_RESET 0x00000000 -#define SIO_SPINLOCK25_MSB 31 -#define SIO_SPINLOCK25_LSB 0 -#define SIO_SPINLOCK25_ACCESS "RO" +#define SIO_SPINLOCK25_OFFSET _u(0x00000164) +#define SIO_SPINLOCK25_BITS _u(0xffffffff) +#define SIO_SPINLOCK25_RESET _u(0x00000000) +#define SIO_SPINLOCK25_MSB _u(31) +#define SIO_SPINLOCK25_LSB _u(0) +#define SIO_SPINLOCK25_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK26 // Description : Reading from a spinlock address will: @@ -1566,12 +1566,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK26_OFFSET 0x00000168 -#define SIO_SPINLOCK26_BITS 0xffffffff -#define SIO_SPINLOCK26_RESET 0x00000000 -#define SIO_SPINLOCK26_MSB 31 -#define SIO_SPINLOCK26_LSB 0 -#define SIO_SPINLOCK26_ACCESS "RO" +#define SIO_SPINLOCK26_OFFSET _u(0x00000168) +#define SIO_SPINLOCK26_BITS _u(0xffffffff) +#define SIO_SPINLOCK26_RESET _u(0x00000000) +#define SIO_SPINLOCK26_MSB _u(31) +#define SIO_SPINLOCK26_LSB _u(0) +#define SIO_SPINLOCK26_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK27 // Description : Reading from a spinlock address will: @@ -1582,12 +1582,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK27_OFFSET 0x0000016c -#define SIO_SPINLOCK27_BITS 0xffffffff -#define SIO_SPINLOCK27_RESET 0x00000000 -#define SIO_SPINLOCK27_MSB 31 -#define SIO_SPINLOCK27_LSB 0 -#define SIO_SPINLOCK27_ACCESS "RO" +#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) +#define SIO_SPINLOCK27_BITS _u(0xffffffff) +#define SIO_SPINLOCK27_RESET _u(0x00000000) +#define SIO_SPINLOCK27_MSB _u(31) +#define SIO_SPINLOCK27_LSB _u(0) +#define SIO_SPINLOCK27_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK28 // Description : Reading from a spinlock address will: @@ -1598,12 +1598,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK28_OFFSET 0x00000170 -#define SIO_SPINLOCK28_BITS 0xffffffff -#define SIO_SPINLOCK28_RESET 0x00000000 -#define SIO_SPINLOCK28_MSB 31 -#define SIO_SPINLOCK28_LSB 0 -#define SIO_SPINLOCK28_ACCESS "RO" +#define SIO_SPINLOCK28_OFFSET _u(0x00000170) +#define SIO_SPINLOCK28_BITS _u(0xffffffff) +#define SIO_SPINLOCK28_RESET _u(0x00000000) +#define SIO_SPINLOCK28_MSB _u(31) +#define SIO_SPINLOCK28_LSB _u(0) +#define SIO_SPINLOCK28_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK29 // Description : Reading from a spinlock address will: @@ -1614,12 +1614,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK29_OFFSET 0x00000174 -#define SIO_SPINLOCK29_BITS 0xffffffff -#define SIO_SPINLOCK29_RESET 0x00000000 -#define SIO_SPINLOCK29_MSB 31 -#define SIO_SPINLOCK29_LSB 0 -#define SIO_SPINLOCK29_ACCESS "RO" +#define SIO_SPINLOCK29_OFFSET _u(0x00000174) +#define SIO_SPINLOCK29_BITS _u(0xffffffff) +#define SIO_SPINLOCK29_RESET _u(0x00000000) +#define SIO_SPINLOCK29_MSB _u(31) +#define SIO_SPINLOCK29_LSB _u(0) +#define SIO_SPINLOCK29_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK30 // Description : Reading from a spinlock address will: @@ -1630,12 +1630,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK30_OFFSET 0x00000178 -#define SIO_SPINLOCK30_BITS 0xffffffff -#define SIO_SPINLOCK30_RESET 0x00000000 -#define SIO_SPINLOCK30_MSB 31 -#define SIO_SPINLOCK30_LSB 0 -#define SIO_SPINLOCK30_ACCESS "RO" +#define SIO_SPINLOCK30_OFFSET _u(0x00000178) +#define SIO_SPINLOCK30_BITS _u(0xffffffff) +#define SIO_SPINLOCK30_RESET _u(0x00000000) +#define SIO_SPINLOCK30_MSB _u(31) +#define SIO_SPINLOCK30_LSB _u(0) +#define SIO_SPINLOCK30_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK31 // Description : Reading from a spinlock address will: @@ -1646,11 +1646,11 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK31_OFFSET 0x0000017c -#define SIO_SPINLOCK31_BITS 0xffffffff -#define SIO_SPINLOCK31_RESET 0x00000000 -#define SIO_SPINLOCK31_MSB 31 -#define SIO_SPINLOCK31_LSB 0 -#define SIO_SPINLOCK31_ACCESS "RO" +#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) +#define SIO_SPINLOCK31_BITS _u(0xffffffff) +#define SIO_SPINLOCK31_RESET _u(0x00000000) +#define SIO_SPINLOCK31_MSB _u(31) +#define SIO_SPINLOCK31_LSB _u(0) +#define SIO_SPINLOCK31_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SIO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h index 9670b830971..816e150249a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : SPI_SSPCR0 // Description : Control register 0, SSPCR0 on page 3-4 -#define SPI_SSPCR0_OFFSET 0x00000000 -#define SPI_SSPCR0_BITS 0x0000ffff -#define SPI_SSPCR0_RESET 0x00000000 +#define SPI_SSPCR0_OFFSET _u(0x00000000) +#define SPI_SSPCR0_BITS _u(0x0000ffff) +#define SPI_SSPCR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SCR // Description : Serial clock rate. The value SCR is used to generate the @@ -24,38 +24,38 @@ // rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even // value from 2-254, programmed through the SSPCPSR register and // SCR is a value from 0-255. -#define SPI_SSPCR0_SCR_RESET 0x00 -#define SPI_SSPCR0_SCR_BITS 0x0000ff00 -#define SPI_SSPCR0_SCR_MSB 15 -#define SPI_SSPCR0_SCR_LSB 8 +#define SPI_SSPCR0_SCR_RESET _u(0x00) +#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) +#define SPI_SSPCR0_SCR_MSB _u(15) +#define SPI_SSPCR0_SCR_LSB _u(8) #define SPI_SSPCR0_SCR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SPH // Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. // See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPH_RESET 0x0 -#define SPI_SSPCR0_SPH_BITS 0x00000080 -#define SPI_SSPCR0_SPH_MSB 7 -#define SPI_SSPCR0_SPH_LSB 7 +#define SPI_SSPCR0_SPH_RESET _u(0x0) +#define SPI_SSPCR0_SPH_BITS _u(0x00000080) +#define SPI_SSPCR0_SPH_MSB _u(7) +#define SPI_SSPCR0_SPH_LSB _u(7) #define SPI_SSPCR0_SPH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SPO // Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format // only. See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPO_RESET 0x0 -#define SPI_SSPCR0_SPO_BITS 0x00000040 -#define SPI_SSPCR0_SPO_MSB 6 -#define SPI_SSPCR0_SPO_LSB 6 +#define SPI_SSPCR0_SPO_RESET _u(0x0) +#define SPI_SSPCR0_SPO_BITS _u(0x00000040) +#define SPI_SSPCR0_SPO_MSB _u(6) +#define SPI_SSPCR0_SPO_LSB _u(6) #define SPI_SSPCR0_SPO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_FRF // Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous // serial frame format. 10 National Microwire frame format. 11 // Reserved, undefined operation. -#define SPI_SSPCR0_FRF_RESET 0x0 -#define SPI_SSPCR0_FRF_BITS 0x00000030 -#define SPI_SSPCR0_FRF_MSB 5 -#define SPI_SSPCR0_FRF_LSB 4 +#define SPI_SSPCR0_FRF_RESET _u(0x0) +#define SPI_SSPCR0_FRF_BITS _u(0x00000030) +#define SPI_SSPCR0_FRF_MSB _u(5) +#define SPI_SSPCR0_FRF_LSB _u(4) #define SPI_SSPCR0_FRF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_DSS @@ -65,17 +65,17 @@ // 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit // data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. // 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. -#define SPI_SSPCR0_DSS_RESET 0x0 -#define SPI_SSPCR0_DSS_BITS 0x0000000f -#define SPI_SSPCR0_DSS_MSB 3 -#define SPI_SSPCR0_DSS_LSB 0 +#define SPI_SSPCR0_DSS_RESET _u(0x0) +#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) +#define SPI_SSPCR0_DSS_MSB _u(3) +#define SPI_SSPCR0_DSS_LSB _u(0) #define SPI_SSPCR0_DSS_ACCESS "RW" // ============================================================================= // Register : SPI_SSPCR1 // Description : Control register 1, SSPCR1 on page 3-5 -#define SPI_SSPCR1_OFFSET 0x00000004 -#define SPI_SSPCR1_BITS 0x0000000f -#define SPI_SSPCR1_RESET 0x00000000 +#define SPI_SSPCR1_OFFSET _u(0x00000004) +#define SPI_SSPCR1_BITS _u(0x0000000f) +#define SPI_SSPCR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_SOD // Description : Slave-mode output disable. This bit is relevant only in the @@ -88,45 +88,45 @@ // not supposed to drive the SSPTXD line: 0 SSP can drive the // SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD // output in slave mode. -#define SPI_SSPCR1_SOD_RESET 0x0 -#define SPI_SSPCR1_SOD_BITS 0x00000008 -#define SPI_SSPCR1_SOD_MSB 3 -#define SPI_SSPCR1_SOD_LSB 3 +#define SPI_SSPCR1_SOD_RESET _u(0x0) +#define SPI_SSPCR1_SOD_BITS _u(0x00000008) +#define SPI_SSPCR1_SOD_MSB _u(3) +#define SPI_SSPCR1_SOD_LSB _u(3) #define SPI_SSPCR1_SOD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_MS // Description : Master or slave mode select. This bit can be modified only when // the PrimeCell SSP is disabled, SSE=0: 0 Device configured as // master, default. 1 Device configured as slave. -#define SPI_SSPCR1_MS_RESET 0x0 -#define SPI_SSPCR1_MS_BITS 0x00000004 -#define SPI_SSPCR1_MS_MSB 2 -#define SPI_SSPCR1_MS_LSB 2 +#define SPI_SSPCR1_MS_RESET _u(0x0) +#define SPI_SSPCR1_MS_BITS _u(0x00000004) +#define SPI_SSPCR1_MS_MSB _u(2) +#define SPI_SSPCR1_MS_LSB _u(2) #define SPI_SSPCR1_MS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_SSE // Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP // operation enabled. -#define SPI_SSPCR1_SSE_RESET 0x0 -#define SPI_SSPCR1_SSE_BITS 0x00000002 -#define SPI_SSPCR1_SSE_MSB 1 -#define SPI_SSPCR1_SSE_LSB 1 +#define SPI_SSPCR1_SSE_RESET _u(0x0) +#define SPI_SSPCR1_SSE_BITS _u(0x00000002) +#define SPI_SSPCR1_SSE_MSB _u(1) +#define SPI_SSPCR1_SSE_LSB _u(1) #define SPI_SSPCR1_SSE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_LBM // Description : Loop back mode: 0 Normal serial port operation enabled. 1 // Output of transmit serial shifter is connected to input of // receive serial shifter internally. -#define SPI_SSPCR1_LBM_RESET 0x0 -#define SPI_SSPCR1_LBM_BITS 0x00000001 -#define SPI_SSPCR1_LBM_MSB 0 -#define SPI_SSPCR1_LBM_LSB 0 +#define SPI_SSPCR1_LBM_RESET _u(0x0) +#define SPI_SSPCR1_LBM_BITS _u(0x00000001) +#define SPI_SSPCR1_LBM_MSB _u(0) +#define SPI_SSPCR1_LBM_LSB _u(0) #define SPI_SSPCR1_LBM_ACCESS "RW" // ============================================================================= // Register : SPI_SSPDR // Description : Data register, SSPDR on page 3-6 -#define SPI_SSPDR_OFFSET 0x00000008 -#define SPI_SSPDR_BITS 0x0000ffff +#define SPI_SSPDR_OFFSET _u(0x00000008) +#define SPI_SSPDR_BITS _u(0x0000ffff) #define SPI_SSPDR_RESET "-" // ----------------------------------------------------------------------------- // Field : SPI_SSPDR_DATA @@ -136,103 +136,103 @@ // bits at the top are ignored by transmit logic. The receive // logic automatically right-justifies. #define SPI_SSPDR_DATA_RESET "-" -#define SPI_SSPDR_DATA_BITS 0x0000ffff -#define SPI_SSPDR_DATA_MSB 15 -#define SPI_SSPDR_DATA_LSB 0 +#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) +#define SPI_SSPDR_DATA_MSB _u(15) +#define SPI_SSPDR_DATA_LSB _u(0) #define SPI_SSPDR_DATA_ACCESS "RWF" // ============================================================================= // Register : SPI_SSPSR // Description : Status register, SSPSR on page 3-7 -#define SPI_SSPSR_OFFSET 0x0000000c -#define SPI_SSPSR_BITS 0x0000001f -#define SPI_SSPSR_RESET 0x00000003 +#define SPI_SSPSR_OFFSET _u(0x0000000c) +#define SPI_SSPSR_BITS _u(0x0000001f) +#define SPI_SSPSR_RESET _u(0x00000003) // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_BSY // Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently // transmitting and/or receiving a frame or the transmit FIFO is // not empty. -#define SPI_SSPSR_BSY_RESET 0x0 -#define SPI_SSPSR_BSY_BITS 0x00000010 -#define SPI_SSPSR_BSY_MSB 4 -#define SPI_SSPSR_BSY_LSB 4 +#define SPI_SSPSR_BSY_RESET _u(0x0) +#define SPI_SSPSR_BSY_BITS _u(0x00000010) +#define SPI_SSPSR_BSY_MSB _u(4) +#define SPI_SSPSR_BSY_LSB _u(4) #define SPI_SSPSR_BSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_RFF // Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive // FIFO is full. -#define SPI_SSPSR_RFF_RESET 0x0 -#define SPI_SSPSR_RFF_BITS 0x00000008 -#define SPI_SSPSR_RFF_MSB 3 -#define SPI_SSPSR_RFF_LSB 3 +#define SPI_SSPSR_RFF_RESET _u(0x0) +#define SPI_SSPSR_RFF_BITS _u(0x00000008) +#define SPI_SSPSR_RFF_MSB _u(3) +#define SPI_SSPSR_RFF_LSB _u(3) #define SPI_SSPSR_RFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_RNE // Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive // FIFO is not empty. -#define SPI_SSPSR_RNE_RESET 0x0 -#define SPI_SSPSR_RNE_BITS 0x00000004 -#define SPI_SSPSR_RNE_MSB 2 -#define SPI_SSPSR_RNE_LSB 2 +#define SPI_SSPSR_RNE_RESET _u(0x0) +#define SPI_SSPSR_RNE_BITS _u(0x00000004) +#define SPI_SSPSR_RNE_MSB _u(2) +#define SPI_SSPSR_RNE_LSB _u(2) #define SPI_SSPSR_RNE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_TNF // Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit // FIFO is not full. -#define SPI_SSPSR_TNF_RESET 0x1 -#define SPI_SSPSR_TNF_BITS 0x00000002 -#define SPI_SSPSR_TNF_MSB 1 -#define SPI_SSPSR_TNF_LSB 1 +#define SPI_SSPSR_TNF_RESET _u(0x1) +#define SPI_SSPSR_TNF_BITS _u(0x00000002) +#define SPI_SSPSR_TNF_MSB _u(1) +#define SPI_SSPSR_TNF_LSB _u(1) #define SPI_SSPSR_TNF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_TFE // Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 // Transmit FIFO is empty. -#define SPI_SSPSR_TFE_RESET 0x1 -#define SPI_SSPSR_TFE_BITS 0x00000001 -#define SPI_SSPSR_TFE_MSB 0 -#define SPI_SSPSR_TFE_LSB 0 +#define SPI_SSPSR_TFE_RESET _u(0x1) +#define SPI_SSPSR_TFE_BITS _u(0x00000001) +#define SPI_SSPSR_TFE_MSB _u(0) +#define SPI_SSPSR_TFE_LSB _u(0) #define SPI_SSPSR_TFE_ACCESS "RO" // ============================================================================= // Register : SPI_SSPCPSR // Description : Clock prescale register, SSPCPSR on page 3-8 -#define SPI_SSPCPSR_OFFSET 0x00000010 -#define SPI_SSPCPSR_BITS 0x000000ff -#define SPI_SSPCPSR_RESET 0x00000000 +#define SPI_SSPCPSR_OFFSET _u(0x00000010) +#define SPI_SSPCPSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCPSR_CPSDVSR // Description : Clock prescale divisor. Must be an even number from 2-254, // depending on the frequency of SSPCLK. The least significant bit // always returns zero on reads. -#define SPI_SSPCPSR_CPSDVSR_RESET 0x00 -#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff -#define SPI_SSPCPSR_CPSDVSR_MSB 7 -#define SPI_SSPCPSR_CPSDVSR_LSB 0 +#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) +#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) +#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) #define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" // ============================================================================= // Register : SPI_SSPIMSC // Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 -#define SPI_SSPIMSC_OFFSET 0x00000014 -#define SPI_SSPIMSC_BITS 0x0000000f -#define SPI_SSPIMSC_RESET 0x00000000 +#define SPI_SSPIMSC_OFFSET _u(0x00000014) +#define SPI_SSPIMSC_BITS _u(0x0000000f) +#define SPI_SSPIMSC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_TXIM // Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or // less condition interrupt is masked. 1 Transmit FIFO half empty // or less condition interrupt is not masked. -#define SPI_SSPIMSC_TXIM_RESET 0x0 -#define SPI_SSPIMSC_TXIM_BITS 0x00000008 -#define SPI_SSPIMSC_TXIM_MSB 3 -#define SPI_SSPIMSC_TXIM_LSB 3 +#define SPI_SSPIMSC_TXIM_RESET _u(0x0) +#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) +#define SPI_SSPIMSC_TXIM_MSB _u(3) +#define SPI_SSPIMSC_TXIM_LSB _u(3) #define SPI_SSPIMSC_TXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RXIM // Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less // condition interrupt is masked. 1 Receive FIFO half full or less // condition interrupt is not masked. -#define SPI_SSPIMSC_RXIM_RESET 0x0 -#define SPI_SSPIMSC_RXIM_BITS 0x00000004 -#define SPI_SSPIMSC_RXIM_MSB 2 -#define SPI_SSPIMSC_RXIM_LSB 2 +#define SPI_SSPIMSC_RXIM_RESET _u(0x0) +#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) +#define SPI_SSPIMSC_RXIM_MSB _u(2) +#define SPI_SSPIMSC_RXIM_LSB _u(2) #define SPI_SSPIMSC_RXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RTIM @@ -240,282 +240,282 @@ // read prior to timeout period interrupt is masked. 1 Receive // FIFO not empty and no read prior to timeout period interrupt is // not masked. -#define SPI_SSPIMSC_RTIM_RESET 0x0 -#define SPI_SSPIMSC_RTIM_BITS 0x00000002 -#define SPI_SSPIMSC_RTIM_MSB 1 -#define SPI_SSPIMSC_RTIM_LSB 1 +#define SPI_SSPIMSC_RTIM_RESET _u(0x0) +#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) +#define SPI_SSPIMSC_RTIM_MSB _u(1) +#define SPI_SSPIMSC_RTIM_LSB _u(1) #define SPI_SSPIMSC_RTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RORIM // Description : Receive overrun interrupt mask: 0 Receive FIFO written to while // full condition interrupt is masked. 1 Receive FIFO written to // while full condition interrupt is not masked. -#define SPI_SSPIMSC_RORIM_RESET 0x0 -#define SPI_SSPIMSC_RORIM_BITS 0x00000001 -#define SPI_SSPIMSC_RORIM_MSB 0 -#define SPI_SSPIMSC_RORIM_LSB 0 +#define SPI_SSPIMSC_RORIM_RESET _u(0x0) +#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) +#define SPI_SSPIMSC_RORIM_MSB _u(0) +#define SPI_SSPIMSC_RORIM_LSB _u(0) #define SPI_SSPIMSC_RORIM_ACCESS "RW" // ============================================================================= // Register : SPI_SSPRIS // Description : Raw interrupt status register, SSPRIS on page 3-10 -#define SPI_SSPRIS_OFFSET 0x00000018 -#define SPI_SSPRIS_BITS 0x0000000f -#define SPI_SSPRIS_RESET 0x00000008 +#define SPI_SSPRIS_OFFSET _u(0x00000018) +#define SPI_SSPRIS_BITS _u(0x0000000f) +#define SPI_SSPRIS_RESET _u(0x00000008) // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_TXRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPTXINTR interrupt -#define SPI_SSPRIS_TXRIS_RESET 0x1 -#define SPI_SSPRIS_TXRIS_BITS 0x00000008 -#define SPI_SSPRIS_TXRIS_MSB 3 -#define SPI_SSPRIS_TXRIS_LSB 3 +#define SPI_SSPRIS_TXRIS_RESET _u(0x1) +#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) +#define SPI_SSPRIS_TXRIS_MSB _u(3) +#define SPI_SSPRIS_TXRIS_LSB _u(3) #define SPI_SSPRIS_TXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RXRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRXINTR interrupt -#define SPI_SSPRIS_RXRIS_RESET 0x0 -#define SPI_SSPRIS_RXRIS_BITS 0x00000004 -#define SPI_SSPRIS_RXRIS_MSB 2 -#define SPI_SSPRIS_RXRIS_LSB 2 +#define SPI_SSPRIS_RXRIS_RESET _u(0x0) +#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) +#define SPI_SSPRIS_RXRIS_MSB _u(2) +#define SPI_SSPRIS_RXRIS_LSB _u(2) #define SPI_SSPRIS_RXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RTRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRTINTR interrupt -#define SPI_SSPRIS_RTRIS_RESET 0x0 -#define SPI_SSPRIS_RTRIS_BITS 0x00000002 -#define SPI_SSPRIS_RTRIS_MSB 1 -#define SPI_SSPRIS_RTRIS_LSB 1 +#define SPI_SSPRIS_RTRIS_RESET _u(0x0) +#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) +#define SPI_SSPRIS_RTRIS_MSB _u(1) +#define SPI_SSPRIS_RTRIS_LSB _u(1) #define SPI_SSPRIS_RTRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RORRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRORINTR interrupt -#define SPI_SSPRIS_RORRIS_RESET 0x0 -#define SPI_SSPRIS_RORRIS_BITS 0x00000001 -#define SPI_SSPRIS_RORRIS_MSB 0 -#define SPI_SSPRIS_RORRIS_LSB 0 +#define SPI_SSPRIS_RORRIS_RESET _u(0x0) +#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) +#define SPI_SSPRIS_RORRIS_MSB _u(0) +#define SPI_SSPRIS_RORRIS_LSB _u(0) #define SPI_SSPRIS_RORRIS_ACCESS "RO" // ============================================================================= // Register : SPI_SSPMIS // Description : Masked interrupt status register, SSPMIS on page 3-11 -#define SPI_SSPMIS_OFFSET 0x0000001c -#define SPI_SSPMIS_BITS 0x0000000f -#define SPI_SSPMIS_RESET 0x00000000 +#define SPI_SSPMIS_OFFSET _u(0x0000001c) +#define SPI_SSPMIS_BITS _u(0x0000000f) +#define SPI_SSPMIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_TXMIS // Description : Gives the transmit FIFO masked interrupt state, after masking, // of the SSPTXINTR interrupt -#define SPI_SSPMIS_TXMIS_RESET 0x0 -#define SPI_SSPMIS_TXMIS_BITS 0x00000008 -#define SPI_SSPMIS_TXMIS_MSB 3 -#define SPI_SSPMIS_TXMIS_LSB 3 +#define SPI_SSPMIS_TXMIS_RESET _u(0x0) +#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) +#define SPI_SSPMIS_TXMIS_MSB _u(3) +#define SPI_SSPMIS_TXMIS_LSB _u(3) #define SPI_SSPMIS_TXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RXMIS // Description : Gives the receive FIFO masked interrupt state, after masking, // of the SSPRXINTR interrupt -#define SPI_SSPMIS_RXMIS_RESET 0x0 -#define SPI_SSPMIS_RXMIS_BITS 0x00000004 -#define SPI_SSPMIS_RXMIS_MSB 2 -#define SPI_SSPMIS_RXMIS_LSB 2 +#define SPI_SSPMIS_RXMIS_RESET _u(0x0) +#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) +#define SPI_SSPMIS_RXMIS_MSB _u(2) +#define SPI_SSPMIS_RXMIS_LSB _u(2) #define SPI_SSPMIS_RXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RTMIS // Description : Gives the receive timeout masked interrupt state, after // masking, of the SSPRTINTR interrupt -#define SPI_SSPMIS_RTMIS_RESET 0x0 -#define SPI_SSPMIS_RTMIS_BITS 0x00000002 -#define SPI_SSPMIS_RTMIS_MSB 1 -#define SPI_SSPMIS_RTMIS_LSB 1 +#define SPI_SSPMIS_RTMIS_RESET _u(0x0) +#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) +#define SPI_SSPMIS_RTMIS_MSB _u(1) +#define SPI_SSPMIS_RTMIS_LSB _u(1) #define SPI_SSPMIS_RTMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RORMIS // Description : Gives the receive over run masked interrupt status, after // masking, of the SSPRORINTR interrupt -#define SPI_SSPMIS_RORMIS_RESET 0x0 -#define SPI_SSPMIS_RORMIS_BITS 0x00000001 -#define SPI_SSPMIS_RORMIS_MSB 0 -#define SPI_SSPMIS_RORMIS_LSB 0 +#define SPI_SSPMIS_RORMIS_RESET _u(0x0) +#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) +#define SPI_SSPMIS_RORMIS_MSB _u(0) +#define SPI_SSPMIS_RORMIS_LSB _u(0) #define SPI_SSPMIS_RORMIS_ACCESS "RO" // ============================================================================= // Register : SPI_SSPICR // Description : Interrupt clear register, SSPICR on page 3-11 -#define SPI_SSPICR_OFFSET 0x00000020 -#define SPI_SSPICR_BITS 0x00000003 -#define SPI_SSPICR_RESET 0x00000000 +#define SPI_SSPICR_OFFSET _u(0x00000020) +#define SPI_SSPICR_BITS _u(0x00000003) +#define SPI_SSPICR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPICR_RTIC // Description : Clears the SSPRTINTR interrupt -#define SPI_SSPICR_RTIC_RESET 0x0 -#define SPI_SSPICR_RTIC_BITS 0x00000002 -#define SPI_SSPICR_RTIC_MSB 1 -#define SPI_SSPICR_RTIC_LSB 1 +#define SPI_SSPICR_RTIC_RESET _u(0x0) +#define SPI_SSPICR_RTIC_BITS _u(0x00000002) +#define SPI_SSPICR_RTIC_MSB _u(1) +#define SPI_SSPICR_RTIC_LSB _u(1) #define SPI_SSPICR_RTIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SPI_SSPICR_RORIC // Description : Clears the SSPRORINTR interrupt -#define SPI_SSPICR_RORIC_RESET 0x0 -#define SPI_SSPICR_RORIC_BITS 0x00000001 -#define SPI_SSPICR_RORIC_MSB 0 -#define SPI_SSPICR_RORIC_LSB 0 +#define SPI_SSPICR_RORIC_RESET _u(0x0) +#define SPI_SSPICR_RORIC_BITS _u(0x00000001) +#define SPI_SSPICR_RORIC_MSB _u(0) +#define SPI_SSPICR_RORIC_LSB _u(0) #define SPI_SSPICR_RORIC_ACCESS "WC" // ============================================================================= // Register : SPI_SSPDMACR // Description : DMA control register, SSPDMACR on page 3-12 -#define SPI_SSPDMACR_OFFSET 0x00000024 -#define SPI_SSPDMACR_BITS 0x00000003 -#define SPI_SSPDMACR_RESET 0x00000000 +#define SPI_SSPDMACR_OFFSET _u(0x00000024) +#define SPI_SSPDMACR_BITS _u(0x00000003) +#define SPI_SSPDMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPDMACR_TXDMAE // Description : Transmit DMA Enable. If this bit is set to 1, DMA for the // transmit FIFO is enabled. -#define SPI_SSPDMACR_TXDMAE_RESET 0x0 -#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002 -#define SPI_SSPDMACR_TXDMAE_MSB 1 -#define SPI_SSPDMACR_TXDMAE_LSB 1 +#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) +#define SPI_SSPDMACR_TXDMAE_MSB _u(1) +#define SPI_SSPDMACR_TXDMAE_LSB _u(1) #define SPI_SSPDMACR_TXDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPDMACR_RXDMAE // Description : Receive DMA Enable. If this bit is set to 1, DMA for the // receive FIFO is enabled. -#define SPI_SSPDMACR_RXDMAE_RESET 0x0 -#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001 -#define SPI_SSPDMACR_RXDMAE_MSB 0 -#define SPI_SSPDMACR_RXDMAE_LSB 0 +#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) +#define SPI_SSPDMACR_RXDMAE_MSB _u(0) +#define SPI_SSPDMACR_RXDMAE_LSB _u(0) #define SPI_SSPDMACR_RXDMAE_ACCESS "RW" // ============================================================================= // Register : SPI_SSPPERIPHID0 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0 -#define SPI_SSPPERIPHID0_BITS 0x000000ff -#define SPI_SSPPERIPHID0_RESET 0x00000022 +#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) +#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_RESET _u(0x00000022) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID0_PARTNUMBER0 // Description : These bits read back as 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff -#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7 -#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) #define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID1 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4 -#define SPI_SSPPERIPHID1_BITS 0x000000ff -#define SPI_SSPPERIPHID1_RESET 0x00000010 +#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) +#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID1_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID1_DESIGNER0 // Description : These bits read back as 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0 -#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7 -#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) +#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) +#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) #define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID1_PARTNUMBER1 // Description : These bits read back as 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f -#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3 -#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) #define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID2 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8 -#define SPI_SSPPERIPHID2_BITS 0x000000ff -#define SPI_SSPPERIPHID2_RESET 0x00000034 +#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) +#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID2_RESET _u(0x00000034) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID2_REVISION // Description : These bits return the peripheral revision -#define SPI_SSPPERIPHID2_REVISION_RESET 0x3 -#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0 -#define SPI_SSPPERIPHID2_REVISION_MSB 7 -#define SPI_SSPPERIPHID2_REVISION_LSB 4 +#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) +#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) +#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) #define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID2_DESIGNER1 // Description : These bits read back as 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f -#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3 -#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) +#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) +#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) #define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID3 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID3_OFFSET 0x00000fec -#define SPI_SSPPERIPHID3_BITS 0x000000ff -#define SPI_SSPPERIPHID3_RESET 0x00000000 +#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) +#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID3_CONFIGURATION // Description : These bits read back as 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff -#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7 -#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) #define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID0 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID0_OFFSET 0x00000ff0 -#define SPI_SSPPCELLID0_BITS 0x000000ff -#define SPI_SSPPCELLID0_RESET 0x0000000d +#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) +#define SPI_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID0_SSPPCELLID0 // Description : These bits read back as 0x0D -#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d -#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff -#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7 -#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0 +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) #define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID1 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID1_OFFSET 0x00000ff4 -#define SPI_SSPPCELLID1_BITS 0x000000ff -#define SPI_SSPPCELLID1_RESET 0x000000f0 +#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) +#define SPI_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_RESET _u(0x000000f0) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID1_SSPPCELLID1 // Description : These bits read back as 0xF0 -#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0 -#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff -#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7 -#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) #define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID2 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID2_OFFSET 0x00000ff8 -#define SPI_SSPPCELLID2_BITS 0x000000ff -#define SPI_SSPPCELLID2_RESET 0x00000005 +#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) +#define SPI_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID2_SSPPCELLID2 // Description : These bits read back as 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff -#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7 -#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) #define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID3 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID3_OFFSET 0x00000ffc -#define SPI_SSPPCELLID3_BITS 0x000000ff -#define SPI_SSPPCELLID3_RESET 0x000000b1 +#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) +#define SPI_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID3_SSPPCELLID3 // Description : These bits read back as 0xB1 -#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1 -#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff -#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7 -#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_SPI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h index 04eeccaf507..67fddc0a4ec 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h @@ -74,16 +74,16 @@ // ============================================================================= // Register : SSI_CTRLR0 // Description : Control register 0 -#define SSI_CTRLR0_OFFSET 0x00000000 -#define SSI_CTRLR0_BITS 0x017fffff -#define SSI_CTRLR0_RESET 0x00000000 +#define SSI_CTRLR0_OFFSET _u(0x00000000) +#define SSI_CTRLR0_BITS _u(0x017fffff) +#define SSI_CTRLR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SSTE // Description : Slave select toggle enable -#define SSI_CTRLR0_SSTE_RESET 0x0 -#define SSI_CTRLR0_SSTE_BITS 0x01000000 -#define SSI_CTRLR0_SSTE_MSB 24 -#define SSI_CTRLR0_SSTE_LSB 24 +#define SSI_CTRLR0_SSTE_RESET _u(0x0) +#define SSI_CTRLR0_SSTE_BITS _u(0x01000000) +#define SSI_CTRLR0_SSTE_MSB _u(24) +#define SSI_CTRLR0_SSTE_LSB _u(24) #define SSI_CTRLR0_SSTE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SPI_FRF @@ -92,47 +92,47 @@ // full-duplex // 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex // 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex -#define SSI_CTRLR0_SPI_FRF_RESET 0x0 -#define SSI_CTRLR0_SPI_FRF_BITS 0x00600000 -#define SSI_CTRLR0_SPI_FRF_MSB 22 -#define SSI_CTRLR0_SPI_FRF_LSB 21 +#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) +#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) +#define SSI_CTRLR0_SPI_FRF_MSB _u(22) +#define SSI_CTRLR0_SPI_FRF_LSB _u(21) #define SSI_CTRLR0_SPI_FRF_ACCESS "RW" -#define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0 -#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1 -#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 +#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) +#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1) +#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_DFS_32 // Description : Data frame size in 32b transfer mode // Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_DFS_32_RESET 0x00 -#define SSI_CTRLR0_DFS_32_BITS 0x001f0000 -#define SSI_CTRLR0_DFS_32_MSB 20 -#define SSI_CTRLR0_DFS_32_LSB 16 +#define SSI_CTRLR0_DFS_32_RESET _u(0x00) +#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000) +#define SSI_CTRLR0_DFS_32_MSB _u(20) +#define SSI_CTRLR0_DFS_32_LSB _u(16) #define SSI_CTRLR0_DFS_32_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_CFS // Description : Control frame size // Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_CFS_RESET 0x0 -#define SSI_CTRLR0_CFS_BITS 0x0000f000 -#define SSI_CTRLR0_CFS_MSB 15 -#define SSI_CTRLR0_CFS_LSB 12 +#define SSI_CTRLR0_CFS_RESET _u(0x0) +#define SSI_CTRLR0_CFS_BITS _u(0x0000f000) +#define SSI_CTRLR0_CFS_MSB _u(15) +#define SSI_CTRLR0_CFS_LSB _u(12) #define SSI_CTRLR0_CFS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SRL // Description : Shift register loop (test mode) -#define SSI_CTRLR0_SRL_RESET 0x0 -#define SSI_CTRLR0_SRL_BITS 0x00000800 -#define SSI_CTRLR0_SRL_MSB 11 -#define SSI_CTRLR0_SRL_LSB 11 +#define SSI_CTRLR0_SRL_RESET _u(0x0) +#define SSI_CTRLR0_SRL_BITS _u(0x00000800) +#define SSI_CTRLR0_SRL_MSB _u(11) +#define SSI_CTRLR0_SRL_LSB _u(11) #define SSI_CTRLR0_SRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SLV_OE // Description : Slave output enable -#define SSI_CTRLR0_SLV_OE_RESET 0x0 -#define SSI_CTRLR0_SLV_OE_BITS 0x00000400 -#define SSI_CTRLR0_SLV_OE_MSB 10 -#define SSI_CTRLR0_SLV_OE_LSB 10 +#define SSI_CTRLR0_SLV_OE_RESET _u(0x0) +#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400) +#define SSI_CTRLR0_SLV_OE_MSB _u(10) +#define SSI_CTRLR0_SLV_OE_LSB _u(10) #define SSI_CTRLR0_SLV_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_TMOD @@ -142,104 +142,104 @@ // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) // 0x3 -> EEPROM read mode (TX then RX; RX starts after control // data TX'd) -#define SSI_CTRLR0_TMOD_RESET 0x0 -#define SSI_CTRLR0_TMOD_BITS 0x00000300 -#define SSI_CTRLR0_TMOD_MSB 9 -#define SSI_CTRLR0_TMOD_LSB 8 +#define SSI_CTRLR0_TMOD_RESET _u(0x0) +#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) +#define SSI_CTRLR0_TMOD_MSB _u(9) +#define SSI_CTRLR0_TMOD_LSB _u(8) #define SSI_CTRLR0_TMOD_ACCESS "RW" -#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 -#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1 -#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2 -#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) +#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPOL // Description : Serial clock polarity -#define SSI_CTRLR0_SCPOL_RESET 0x0 -#define SSI_CTRLR0_SCPOL_BITS 0x00000080 -#define SSI_CTRLR0_SCPOL_MSB 7 -#define SSI_CTRLR0_SCPOL_LSB 7 +#define SSI_CTRLR0_SCPOL_RESET _u(0x0) +#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080) +#define SSI_CTRLR0_SCPOL_MSB _u(7) +#define SSI_CTRLR0_SCPOL_LSB _u(7) #define SSI_CTRLR0_SCPOL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPH // Description : Serial clock phase -#define SSI_CTRLR0_SCPH_RESET 0x0 -#define SSI_CTRLR0_SCPH_BITS 0x00000040 -#define SSI_CTRLR0_SCPH_MSB 6 -#define SSI_CTRLR0_SCPH_LSB 6 +#define SSI_CTRLR0_SCPH_RESET _u(0x0) +#define SSI_CTRLR0_SCPH_BITS _u(0x00000040) +#define SSI_CTRLR0_SCPH_MSB _u(6) +#define SSI_CTRLR0_SCPH_LSB _u(6) #define SSI_CTRLR0_SCPH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_FRF // Description : Frame format -#define SSI_CTRLR0_FRF_RESET 0x0 -#define SSI_CTRLR0_FRF_BITS 0x00000030 -#define SSI_CTRLR0_FRF_MSB 5 -#define SSI_CTRLR0_FRF_LSB 4 +#define SSI_CTRLR0_FRF_RESET _u(0x0) +#define SSI_CTRLR0_FRF_BITS _u(0x00000030) +#define SSI_CTRLR0_FRF_MSB _u(5) +#define SSI_CTRLR0_FRF_LSB _u(4) #define SSI_CTRLR0_FRF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_DFS // Description : Data frame size -#define SSI_CTRLR0_DFS_RESET 0x0 -#define SSI_CTRLR0_DFS_BITS 0x0000000f -#define SSI_CTRLR0_DFS_MSB 3 -#define SSI_CTRLR0_DFS_LSB 0 +#define SSI_CTRLR0_DFS_RESET _u(0x0) +#define SSI_CTRLR0_DFS_BITS _u(0x0000000f) +#define SSI_CTRLR0_DFS_MSB _u(3) +#define SSI_CTRLR0_DFS_LSB _u(0) #define SSI_CTRLR0_DFS_ACCESS "RW" // ============================================================================= // Register : SSI_CTRLR1 // Description : Master Control register 1 -#define SSI_CTRLR1_OFFSET 0x00000004 -#define SSI_CTRLR1_BITS 0x0000ffff -#define SSI_CTRLR1_RESET 0x00000000 +#define SSI_CTRLR1_OFFSET _u(0x00000004) +#define SSI_CTRLR1_BITS _u(0x0000ffff) +#define SSI_CTRLR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR1_NDF // Description : Number of data frames -#define SSI_CTRLR1_NDF_RESET 0x0000 -#define SSI_CTRLR1_NDF_BITS 0x0000ffff -#define SSI_CTRLR1_NDF_MSB 15 -#define SSI_CTRLR1_NDF_LSB 0 +#define SSI_CTRLR1_NDF_RESET _u(0x0000) +#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff) +#define SSI_CTRLR1_NDF_MSB _u(15) +#define SSI_CTRLR1_NDF_LSB _u(0) #define SSI_CTRLR1_NDF_ACCESS "RW" // ============================================================================= // Register : SSI_SSIENR // Description : SSI Enable -#define SSI_SSIENR_OFFSET 0x00000008 -#define SSI_SSIENR_BITS 0x00000001 -#define SSI_SSIENR_RESET 0x00000000 +#define SSI_SSIENR_OFFSET _u(0x00000008) +#define SSI_SSIENR_BITS _u(0x00000001) +#define SSI_SSIENR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_SSIENR_SSI_EN // Description : SSI enable -#define SSI_SSIENR_SSI_EN_RESET 0x0 -#define SSI_SSIENR_SSI_EN_BITS 0x00000001 -#define SSI_SSIENR_SSI_EN_MSB 0 -#define SSI_SSIENR_SSI_EN_LSB 0 +#define SSI_SSIENR_SSI_EN_RESET _u(0x0) +#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001) +#define SSI_SSIENR_SSI_EN_MSB _u(0) +#define SSI_SSIENR_SSI_EN_LSB _u(0) #define SSI_SSIENR_SSI_EN_ACCESS "RW" // ============================================================================= // Register : SSI_MWCR // Description : Microwire Control -#define SSI_MWCR_OFFSET 0x0000000c -#define SSI_MWCR_BITS 0x00000007 -#define SSI_MWCR_RESET 0x00000000 +#define SSI_MWCR_OFFSET _u(0x0000000c) +#define SSI_MWCR_BITS _u(0x00000007) +#define SSI_MWCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MHS // Description : Microwire handshaking -#define SSI_MWCR_MHS_RESET 0x0 -#define SSI_MWCR_MHS_BITS 0x00000004 -#define SSI_MWCR_MHS_MSB 2 -#define SSI_MWCR_MHS_LSB 2 +#define SSI_MWCR_MHS_RESET _u(0x0) +#define SSI_MWCR_MHS_BITS _u(0x00000004) +#define SSI_MWCR_MHS_MSB _u(2) +#define SSI_MWCR_MHS_LSB _u(2) #define SSI_MWCR_MHS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MDD // Description : Microwire control -#define SSI_MWCR_MDD_RESET 0x0 -#define SSI_MWCR_MDD_BITS 0x00000002 -#define SSI_MWCR_MDD_MSB 1 -#define SSI_MWCR_MDD_LSB 1 +#define SSI_MWCR_MDD_RESET _u(0x0) +#define SSI_MWCR_MDD_BITS _u(0x00000002) +#define SSI_MWCR_MDD_MSB _u(1) +#define SSI_MWCR_MDD_LSB _u(1) #define SSI_MWCR_MDD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MWMOD // Description : Microwire transfer mode -#define SSI_MWCR_MWMOD_RESET 0x0 -#define SSI_MWCR_MWMOD_BITS 0x00000001 -#define SSI_MWCR_MWMOD_MSB 0 -#define SSI_MWCR_MWMOD_LSB 0 +#define SSI_MWCR_MWMOD_RESET _u(0x0) +#define SSI_MWCR_MWMOD_BITS _u(0x00000001) +#define SSI_MWCR_MWMOD_MSB _u(0) +#define SSI_MWCR_MWMOD_LSB _u(0) #define SSI_MWCR_MWMOD_ACCESS "RW" // ============================================================================= // Register : SSI_SER @@ -247,509 +247,509 @@ // For each bit: // 0 -> slave not selected // 1 -> slave selected -#define SSI_SER_OFFSET 0x00000010 -#define SSI_SER_BITS 0x00000001 -#define SSI_SER_RESET 0x00000000 -#define SSI_SER_MSB 0 -#define SSI_SER_LSB 0 +#define SSI_SER_OFFSET _u(0x00000010) +#define SSI_SER_BITS _u(0x00000001) +#define SSI_SER_RESET _u(0x00000000) +#define SSI_SER_MSB _u(0) +#define SSI_SER_LSB _u(0) #define SSI_SER_ACCESS "RW" // ============================================================================= // Register : SSI_BAUDR // Description : Baud rate -#define SSI_BAUDR_OFFSET 0x00000014 -#define SSI_BAUDR_BITS 0x0000ffff -#define SSI_BAUDR_RESET 0x00000000 +#define SSI_BAUDR_OFFSET _u(0x00000014) +#define SSI_BAUDR_BITS _u(0x0000ffff) +#define SSI_BAUDR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_BAUDR_SCKDV // Description : SSI clock divider -#define SSI_BAUDR_SCKDV_RESET 0x0000 -#define SSI_BAUDR_SCKDV_BITS 0x0000ffff -#define SSI_BAUDR_SCKDV_MSB 15 -#define SSI_BAUDR_SCKDV_LSB 0 +#define SSI_BAUDR_SCKDV_RESET _u(0x0000) +#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff) +#define SSI_BAUDR_SCKDV_MSB _u(15) +#define SSI_BAUDR_SCKDV_LSB _u(0) #define SSI_BAUDR_SCKDV_ACCESS "RW" // ============================================================================= // Register : SSI_TXFTLR // Description : TX FIFO threshold level -#define SSI_TXFTLR_OFFSET 0x00000018 -#define SSI_TXFTLR_BITS 0x000000ff -#define SSI_TXFTLR_RESET 0x00000000 +#define SSI_TXFTLR_OFFSET _u(0x00000018) +#define SSI_TXFTLR_BITS _u(0x000000ff) +#define SSI_TXFTLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXFTLR_TFT // Description : Transmit FIFO threshold -#define SSI_TXFTLR_TFT_RESET 0x00 -#define SSI_TXFTLR_TFT_BITS 0x000000ff -#define SSI_TXFTLR_TFT_MSB 7 -#define SSI_TXFTLR_TFT_LSB 0 +#define SSI_TXFTLR_TFT_RESET _u(0x00) +#define SSI_TXFTLR_TFT_BITS _u(0x000000ff) +#define SSI_TXFTLR_TFT_MSB _u(7) +#define SSI_TXFTLR_TFT_LSB _u(0) #define SSI_TXFTLR_TFT_ACCESS "RW" // ============================================================================= // Register : SSI_RXFTLR // Description : RX FIFO threshold level -#define SSI_RXFTLR_OFFSET 0x0000001c -#define SSI_RXFTLR_BITS 0x000000ff -#define SSI_RXFTLR_RESET 0x00000000 +#define SSI_RXFTLR_OFFSET _u(0x0000001c) +#define SSI_RXFTLR_BITS _u(0x000000ff) +#define SSI_RXFTLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RXFTLR_RFT // Description : Receive FIFO threshold -#define SSI_RXFTLR_RFT_RESET 0x00 -#define SSI_RXFTLR_RFT_BITS 0x000000ff -#define SSI_RXFTLR_RFT_MSB 7 -#define SSI_RXFTLR_RFT_LSB 0 +#define SSI_RXFTLR_RFT_RESET _u(0x00) +#define SSI_RXFTLR_RFT_BITS _u(0x000000ff) +#define SSI_RXFTLR_RFT_MSB _u(7) +#define SSI_RXFTLR_RFT_LSB _u(0) #define SSI_RXFTLR_RFT_ACCESS "RW" // ============================================================================= // Register : SSI_TXFLR // Description : TX FIFO level -#define SSI_TXFLR_OFFSET 0x00000020 -#define SSI_TXFLR_BITS 0x000000ff -#define SSI_TXFLR_RESET 0x00000000 +#define SSI_TXFLR_OFFSET _u(0x00000020) +#define SSI_TXFLR_BITS _u(0x000000ff) +#define SSI_TXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXFLR_TFTFL // Description : Transmit FIFO level -#define SSI_TXFLR_TFTFL_RESET 0x00 -#define SSI_TXFLR_TFTFL_BITS 0x000000ff -#define SSI_TXFLR_TFTFL_MSB 7 -#define SSI_TXFLR_TFTFL_LSB 0 +#define SSI_TXFLR_TFTFL_RESET _u(0x00) +#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff) +#define SSI_TXFLR_TFTFL_MSB _u(7) +#define SSI_TXFLR_TFTFL_LSB _u(0) #define SSI_TXFLR_TFTFL_ACCESS "RO" // ============================================================================= // Register : SSI_RXFLR // Description : RX FIFO level -#define SSI_RXFLR_OFFSET 0x00000024 -#define SSI_RXFLR_BITS 0x000000ff -#define SSI_RXFLR_RESET 0x00000000 +#define SSI_RXFLR_OFFSET _u(0x00000024) +#define SSI_RXFLR_BITS _u(0x000000ff) +#define SSI_RXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RXFLR_RXTFL // Description : Receive FIFO level -#define SSI_RXFLR_RXTFL_RESET 0x00 -#define SSI_RXFLR_RXTFL_BITS 0x000000ff -#define SSI_RXFLR_RXTFL_MSB 7 -#define SSI_RXFLR_RXTFL_LSB 0 +#define SSI_RXFLR_RXTFL_RESET _u(0x00) +#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff) +#define SSI_RXFLR_RXTFL_MSB _u(7) +#define SSI_RXFLR_RXTFL_LSB _u(0) #define SSI_RXFLR_RXTFL_ACCESS "RO" // ============================================================================= // Register : SSI_SR // Description : Status register -#define SSI_SR_OFFSET 0x00000028 -#define SSI_SR_BITS 0x0000007f -#define SSI_SR_RESET 0x00000000 +#define SSI_SR_OFFSET _u(0x00000028) +#define SSI_SR_BITS _u(0x0000007f) +#define SSI_SR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_SR_DCOL // Description : Data collision error -#define SSI_SR_DCOL_RESET 0x0 -#define SSI_SR_DCOL_BITS 0x00000040 -#define SSI_SR_DCOL_MSB 6 -#define SSI_SR_DCOL_LSB 6 +#define SSI_SR_DCOL_RESET _u(0x0) +#define SSI_SR_DCOL_BITS _u(0x00000040) +#define SSI_SR_DCOL_MSB _u(6) +#define SSI_SR_DCOL_LSB _u(6) #define SSI_SR_DCOL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TXE // Description : Transmission error -#define SSI_SR_TXE_RESET 0x0 -#define SSI_SR_TXE_BITS 0x00000020 -#define SSI_SR_TXE_MSB 5 -#define SSI_SR_TXE_LSB 5 +#define SSI_SR_TXE_RESET _u(0x0) +#define SSI_SR_TXE_BITS _u(0x00000020) +#define SSI_SR_TXE_MSB _u(5) +#define SSI_SR_TXE_LSB _u(5) #define SSI_SR_TXE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_RFF // Description : Receive FIFO full -#define SSI_SR_RFF_RESET 0x0 -#define SSI_SR_RFF_BITS 0x00000010 -#define SSI_SR_RFF_MSB 4 -#define SSI_SR_RFF_LSB 4 +#define SSI_SR_RFF_RESET _u(0x0) +#define SSI_SR_RFF_BITS _u(0x00000010) +#define SSI_SR_RFF_MSB _u(4) +#define SSI_SR_RFF_LSB _u(4) #define SSI_SR_RFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_RFNE // Description : Receive FIFO not empty -#define SSI_SR_RFNE_RESET 0x0 -#define SSI_SR_RFNE_BITS 0x00000008 -#define SSI_SR_RFNE_MSB 3 -#define SSI_SR_RFNE_LSB 3 +#define SSI_SR_RFNE_RESET _u(0x0) +#define SSI_SR_RFNE_BITS _u(0x00000008) +#define SSI_SR_RFNE_MSB _u(3) +#define SSI_SR_RFNE_LSB _u(3) #define SSI_SR_RFNE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TFE // Description : Transmit FIFO empty -#define SSI_SR_TFE_RESET 0x0 -#define SSI_SR_TFE_BITS 0x00000004 -#define SSI_SR_TFE_MSB 2 -#define SSI_SR_TFE_LSB 2 +#define SSI_SR_TFE_RESET _u(0x0) +#define SSI_SR_TFE_BITS _u(0x00000004) +#define SSI_SR_TFE_MSB _u(2) +#define SSI_SR_TFE_LSB _u(2) #define SSI_SR_TFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TFNF // Description : Transmit FIFO not full -#define SSI_SR_TFNF_RESET 0x0 -#define SSI_SR_TFNF_BITS 0x00000002 -#define SSI_SR_TFNF_MSB 1 -#define SSI_SR_TFNF_LSB 1 +#define SSI_SR_TFNF_RESET _u(0x0) +#define SSI_SR_TFNF_BITS _u(0x00000002) +#define SSI_SR_TFNF_MSB _u(1) +#define SSI_SR_TFNF_LSB _u(1) #define SSI_SR_TFNF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_BUSY // Description : SSI busy flag -#define SSI_SR_BUSY_RESET 0x0 -#define SSI_SR_BUSY_BITS 0x00000001 -#define SSI_SR_BUSY_MSB 0 -#define SSI_SR_BUSY_LSB 0 +#define SSI_SR_BUSY_RESET _u(0x0) +#define SSI_SR_BUSY_BITS _u(0x00000001) +#define SSI_SR_BUSY_MSB _u(0) +#define SSI_SR_BUSY_LSB _u(0) #define SSI_SR_BUSY_ACCESS "RO" // ============================================================================= // Register : SSI_IMR // Description : Interrupt mask -#define SSI_IMR_OFFSET 0x0000002c -#define SSI_IMR_BITS 0x0000003f -#define SSI_IMR_RESET 0x00000000 +#define SSI_IMR_OFFSET _u(0x0000002c) +#define SSI_IMR_BITS _u(0x0000003f) +#define SSI_IMR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_IMR_MSTIM // Description : Multi-master contention interrupt mask -#define SSI_IMR_MSTIM_RESET 0x0 -#define SSI_IMR_MSTIM_BITS 0x00000020 -#define SSI_IMR_MSTIM_MSB 5 -#define SSI_IMR_MSTIM_LSB 5 +#define SSI_IMR_MSTIM_RESET _u(0x0) +#define SSI_IMR_MSTIM_BITS _u(0x00000020) +#define SSI_IMR_MSTIM_MSB _u(5) +#define SSI_IMR_MSTIM_LSB _u(5) #define SSI_IMR_MSTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXFIM // Description : Receive FIFO full interrupt mask -#define SSI_IMR_RXFIM_RESET 0x0 -#define SSI_IMR_RXFIM_BITS 0x00000010 -#define SSI_IMR_RXFIM_MSB 4 -#define SSI_IMR_RXFIM_LSB 4 +#define SSI_IMR_RXFIM_RESET _u(0x0) +#define SSI_IMR_RXFIM_BITS _u(0x00000010) +#define SSI_IMR_RXFIM_MSB _u(4) +#define SSI_IMR_RXFIM_LSB _u(4) #define SSI_IMR_RXFIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXOIM // Description : Receive FIFO overflow interrupt mask -#define SSI_IMR_RXOIM_RESET 0x0 -#define SSI_IMR_RXOIM_BITS 0x00000008 -#define SSI_IMR_RXOIM_MSB 3 -#define SSI_IMR_RXOIM_LSB 3 +#define SSI_IMR_RXOIM_RESET _u(0x0) +#define SSI_IMR_RXOIM_BITS _u(0x00000008) +#define SSI_IMR_RXOIM_MSB _u(3) +#define SSI_IMR_RXOIM_LSB _u(3) #define SSI_IMR_RXOIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXUIM // Description : Receive FIFO underflow interrupt mask -#define SSI_IMR_RXUIM_RESET 0x0 -#define SSI_IMR_RXUIM_BITS 0x00000004 -#define SSI_IMR_RXUIM_MSB 2 -#define SSI_IMR_RXUIM_LSB 2 +#define SSI_IMR_RXUIM_RESET _u(0x0) +#define SSI_IMR_RXUIM_BITS _u(0x00000004) +#define SSI_IMR_RXUIM_MSB _u(2) +#define SSI_IMR_RXUIM_LSB _u(2) #define SSI_IMR_RXUIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_TXOIM // Description : Transmit FIFO overflow interrupt mask -#define SSI_IMR_TXOIM_RESET 0x0 -#define SSI_IMR_TXOIM_BITS 0x00000002 -#define SSI_IMR_TXOIM_MSB 1 -#define SSI_IMR_TXOIM_LSB 1 +#define SSI_IMR_TXOIM_RESET _u(0x0) +#define SSI_IMR_TXOIM_BITS _u(0x00000002) +#define SSI_IMR_TXOIM_MSB _u(1) +#define SSI_IMR_TXOIM_LSB _u(1) #define SSI_IMR_TXOIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_TXEIM // Description : Transmit FIFO empty interrupt mask -#define SSI_IMR_TXEIM_RESET 0x0 -#define SSI_IMR_TXEIM_BITS 0x00000001 -#define SSI_IMR_TXEIM_MSB 0 -#define SSI_IMR_TXEIM_LSB 0 +#define SSI_IMR_TXEIM_RESET _u(0x0) +#define SSI_IMR_TXEIM_BITS _u(0x00000001) +#define SSI_IMR_TXEIM_MSB _u(0) +#define SSI_IMR_TXEIM_LSB _u(0) #define SSI_IMR_TXEIM_ACCESS "RW" // ============================================================================= // Register : SSI_ISR // Description : Interrupt status -#define SSI_ISR_OFFSET 0x00000030 -#define SSI_ISR_BITS 0x0000003f -#define SSI_ISR_RESET 0x00000000 +#define SSI_ISR_OFFSET _u(0x00000030) +#define SSI_ISR_BITS _u(0x0000003f) +#define SSI_ISR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_ISR_MSTIS // Description : Multi-master contention interrupt status -#define SSI_ISR_MSTIS_RESET 0x0 -#define SSI_ISR_MSTIS_BITS 0x00000020 -#define SSI_ISR_MSTIS_MSB 5 -#define SSI_ISR_MSTIS_LSB 5 +#define SSI_ISR_MSTIS_RESET _u(0x0) +#define SSI_ISR_MSTIS_BITS _u(0x00000020) +#define SSI_ISR_MSTIS_MSB _u(5) +#define SSI_ISR_MSTIS_LSB _u(5) #define SSI_ISR_MSTIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXFIS // Description : Receive FIFO full interrupt status -#define SSI_ISR_RXFIS_RESET 0x0 -#define SSI_ISR_RXFIS_BITS 0x00000010 -#define SSI_ISR_RXFIS_MSB 4 -#define SSI_ISR_RXFIS_LSB 4 +#define SSI_ISR_RXFIS_RESET _u(0x0) +#define SSI_ISR_RXFIS_BITS _u(0x00000010) +#define SSI_ISR_RXFIS_MSB _u(4) +#define SSI_ISR_RXFIS_LSB _u(4) #define SSI_ISR_RXFIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXOIS // Description : Receive FIFO overflow interrupt status -#define SSI_ISR_RXOIS_RESET 0x0 -#define SSI_ISR_RXOIS_BITS 0x00000008 -#define SSI_ISR_RXOIS_MSB 3 -#define SSI_ISR_RXOIS_LSB 3 +#define SSI_ISR_RXOIS_RESET _u(0x0) +#define SSI_ISR_RXOIS_BITS _u(0x00000008) +#define SSI_ISR_RXOIS_MSB _u(3) +#define SSI_ISR_RXOIS_LSB _u(3) #define SSI_ISR_RXOIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXUIS // Description : Receive FIFO underflow interrupt status -#define SSI_ISR_RXUIS_RESET 0x0 -#define SSI_ISR_RXUIS_BITS 0x00000004 -#define SSI_ISR_RXUIS_MSB 2 -#define SSI_ISR_RXUIS_LSB 2 +#define SSI_ISR_RXUIS_RESET _u(0x0) +#define SSI_ISR_RXUIS_BITS _u(0x00000004) +#define SSI_ISR_RXUIS_MSB _u(2) +#define SSI_ISR_RXUIS_LSB _u(2) #define SSI_ISR_RXUIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_TXOIS // Description : Transmit FIFO overflow interrupt status -#define SSI_ISR_TXOIS_RESET 0x0 -#define SSI_ISR_TXOIS_BITS 0x00000002 -#define SSI_ISR_TXOIS_MSB 1 -#define SSI_ISR_TXOIS_LSB 1 +#define SSI_ISR_TXOIS_RESET _u(0x0) +#define SSI_ISR_TXOIS_BITS _u(0x00000002) +#define SSI_ISR_TXOIS_MSB _u(1) +#define SSI_ISR_TXOIS_LSB _u(1) #define SSI_ISR_TXOIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_TXEIS // Description : Transmit FIFO empty interrupt status -#define SSI_ISR_TXEIS_RESET 0x0 -#define SSI_ISR_TXEIS_BITS 0x00000001 -#define SSI_ISR_TXEIS_MSB 0 -#define SSI_ISR_TXEIS_LSB 0 +#define SSI_ISR_TXEIS_RESET _u(0x0) +#define SSI_ISR_TXEIS_BITS _u(0x00000001) +#define SSI_ISR_TXEIS_MSB _u(0) +#define SSI_ISR_TXEIS_LSB _u(0) #define SSI_ISR_TXEIS_ACCESS "RO" // ============================================================================= // Register : SSI_RISR // Description : Raw interrupt status -#define SSI_RISR_OFFSET 0x00000034 -#define SSI_RISR_BITS 0x0000003f -#define SSI_RISR_RESET 0x00000000 +#define SSI_RISR_OFFSET _u(0x00000034) +#define SSI_RISR_BITS _u(0x0000003f) +#define SSI_RISR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RISR_MSTIR // Description : Multi-master contention raw interrupt status -#define SSI_RISR_MSTIR_RESET 0x0 -#define SSI_RISR_MSTIR_BITS 0x00000020 -#define SSI_RISR_MSTIR_MSB 5 -#define SSI_RISR_MSTIR_LSB 5 +#define SSI_RISR_MSTIR_RESET _u(0x0) +#define SSI_RISR_MSTIR_BITS _u(0x00000020) +#define SSI_RISR_MSTIR_MSB _u(5) +#define SSI_RISR_MSTIR_LSB _u(5) #define SSI_RISR_MSTIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXFIR // Description : Receive FIFO full raw interrupt status -#define SSI_RISR_RXFIR_RESET 0x0 -#define SSI_RISR_RXFIR_BITS 0x00000010 -#define SSI_RISR_RXFIR_MSB 4 -#define SSI_RISR_RXFIR_LSB 4 +#define SSI_RISR_RXFIR_RESET _u(0x0) +#define SSI_RISR_RXFIR_BITS _u(0x00000010) +#define SSI_RISR_RXFIR_MSB _u(4) +#define SSI_RISR_RXFIR_LSB _u(4) #define SSI_RISR_RXFIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXOIR // Description : Receive FIFO overflow raw interrupt status -#define SSI_RISR_RXOIR_RESET 0x0 -#define SSI_RISR_RXOIR_BITS 0x00000008 -#define SSI_RISR_RXOIR_MSB 3 -#define SSI_RISR_RXOIR_LSB 3 +#define SSI_RISR_RXOIR_RESET _u(0x0) +#define SSI_RISR_RXOIR_BITS _u(0x00000008) +#define SSI_RISR_RXOIR_MSB _u(3) +#define SSI_RISR_RXOIR_LSB _u(3) #define SSI_RISR_RXOIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXUIR // Description : Receive FIFO underflow raw interrupt status -#define SSI_RISR_RXUIR_RESET 0x0 -#define SSI_RISR_RXUIR_BITS 0x00000004 -#define SSI_RISR_RXUIR_MSB 2 -#define SSI_RISR_RXUIR_LSB 2 +#define SSI_RISR_RXUIR_RESET _u(0x0) +#define SSI_RISR_RXUIR_BITS _u(0x00000004) +#define SSI_RISR_RXUIR_MSB _u(2) +#define SSI_RISR_RXUIR_LSB _u(2) #define SSI_RISR_RXUIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_TXOIR // Description : Transmit FIFO overflow raw interrupt status -#define SSI_RISR_TXOIR_RESET 0x0 -#define SSI_RISR_TXOIR_BITS 0x00000002 -#define SSI_RISR_TXOIR_MSB 1 -#define SSI_RISR_TXOIR_LSB 1 +#define SSI_RISR_TXOIR_RESET _u(0x0) +#define SSI_RISR_TXOIR_BITS _u(0x00000002) +#define SSI_RISR_TXOIR_MSB _u(1) +#define SSI_RISR_TXOIR_LSB _u(1) #define SSI_RISR_TXOIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_TXEIR // Description : Transmit FIFO empty raw interrupt status -#define SSI_RISR_TXEIR_RESET 0x0 -#define SSI_RISR_TXEIR_BITS 0x00000001 -#define SSI_RISR_TXEIR_MSB 0 -#define SSI_RISR_TXEIR_LSB 0 +#define SSI_RISR_TXEIR_RESET _u(0x0) +#define SSI_RISR_TXEIR_BITS _u(0x00000001) +#define SSI_RISR_TXEIR_MSB _u(0) +#define SSI_RISR_TXEIR_LSB _u(0) #define SSI_RISR_TXEIR_ACCESS "RO" // ============================================================================= // Register : SSI_TXOICR // Description : TX FIFO overflow interrupt clear // Clear-on-read transmit FIFO overflow interrupt -#define SSI_TXOICR_OFFSET 0x00000038 -#define SSI_TXOICR_BITS 0x00000001 -#define SSI_TXOICR_RESET 0x00000000 -#define SSI_TXOICR_MSB 0 -#define SSI_TXOICR_LSB 0 +#define SSI_TXOICR_OFFSET _u(0x00000038) +#define SSI_TXOICR_BITS _u(0x00000001) +#define SSI_TXOICR_RESET _u(0x00000000) +#define SSI_TXOICR_MSB _u(0) +#define SSI_TXOICR_LSB _u(0) #define SSI_TXOICR_ACCESS "RO" // ============================================================================= // Register : SSI_RXOICR // Description : RX FIFO overflow interrupt clear // Clear-on-read receive FIFO overflow interrupt -#define SSI_RXOICR_OFFSET 0x0000003c -#define SSI_RXOICR_BITS 0x00000001 -#define SSI_RXOICR_RESET 0x00000000 -#define SSI_RXOICR_MSB 0 -#define SSI_RXOICR_LSB 0 +#define SSI_RXOICR_OFFSET _u(0x0000003c) +#define SSI_RXOICR_BITS _u(0x00000001) +#define SSI_RXOICR_RESET _u(0x00000000) +#define SSI_RXOICR_MSB _u(0) +#define SSI_RXOICR_LSB _u(0) #define SSI_RXOICR_ACCESS "RO" // ============================================================================= // Register : SSI_RXUICR // Description : RX FIFO underflow interrupt clear // Clear-on-read receive FIFO underflow interrupt -#define SSI_RXUICR_OFFSET 0x00000040 -#define SSI_RXUICR_BITS 0x00000001 -#define SSI_RXUICR_RESET 0x00000000 -#define SSI_RXUICR_MSB 0 -#define SSI_RXUICR_LSB 0 +#define SSI_RXUICR_OFFSET _u(0x00000040) +#define SSI_RXUICR_BITS _u(0x00000001) +#define SSI_RXUICR_RESET _u(0x00000000) +#define SSI_RXUICR_MSB _u(0) +#define SSI_RXUICR_LSB _u(0) #define SSI_RXUICR_ACCESS "RO" // ============================================================================= // Register : SSI_MSTICR // Description : Multi-master interrupt clear // Clear-on-read multi-master contention interrupt -#define SSI_MSTICR_OFFSET 0x00000044 -#define SSI_MSTICR_BITS 0x00000001 -#define SSI_MSTICR_RESET 0x00000000 -#define SSI_MSTICR_MSB 0 -#define SSI_MSTICR_LSB 0 +#define SSI_MSTICR_OFFSET _u(0x00000044) +#define SSI_MSTICR_BITS _u(0x00000001) +#define SSI_MSTICR_RESET _u(0x00000000) +#define SSI_MSTICR_MSB _u(0) +#define SSI_MSTICR_LSB _u(0) #define SSI_MSTICR_ACCESS "RO" // ============================================================================= // Register : SSI_ICR // Description : Interrupt clear // Clear-on-read all active interrupts -#define SSI_ICR_OFFSET 0x00000048 -#define SSI_ICR_BITS 0x00000001 -#define SSI_ICR_RESET 0x00000000 -#define SSI_ICR_MSB 0 -#define SSI_ICR_LSB 0 +#define SSI_ICR_OFFSET _u(0x00000048) +#define SSI_ICR_BITS _u(0x00000001) +#define SSI_ICR_RESET _u(0x00000000) +#define SSI_ICR_MSB _u(0) +#define SSI_ICR_LSB _u(0) #define SSI_ICR_ACCESS "RO" // ============================================================================= // Register : SSI_DMACR // Description : DMA control -#define SSI_DMACR_OFFSET 0x0000004c -#define SSI_DMACR_BITS 0x00000003 -#define SSI_DMACR_RESET 0x00000000 +#define SSI_DMACR_OFFSET _u(0x0000004c) +#define SSI_DMACR_BITS _u(0x00000003) +#define SSI_DMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMACR_TDMAE // Description : Transmit DMA enable -#define SSI_DMACR_TDMAE_RESET 0x0 -#define SSI_DMACR_TDMAE_BITS 0x00000002 -#define SSI_DMACR_TDMAE_MSB 1 -#define SSI_DMACR_TDMAE_LSB 1 +#define SSI_DMACR_TDMAE_RESET _u(0x0) +#define SSI_DMACR_TDMAE_BITS _u(0x00000002) +#define SSI_DMACR_TDMAE_MSB _u(1) +#define SSI_DMACR_TDMAE_LSB _u(1) #define SSI_DMACR_TDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_DMACR_RDMAE // Description : Receive DMA enable -#define SSI_DMACR_RDMAE_RESET 0x0 -#define SSI_DMACR_RDMAE_BITS 0x00000001 -#define SSI_DMACR_RDMAE_MSB 0 -#define SSI_DMACR_RDMAE_LSB 0 +#define SSI_DMACR_RDMAE_RESET _u(0x0) +#define SSI_DMACR_RDMAE_BITS _u(0x00000001) +#define SSI_DMACR_RDMAE_MSB _u(0) +#define SSI_DMACR_RDMAE_LSB _u(0) #define SSI_DMACR_RDMAE_ACCESS "RW" // ============================================================================= // Register : SSI_DMATDLR // Description : DMA TX data level -#define SSI_DMATDLR_OFFSET 0x00000050 -#define SSI_DMATDLR_BITS 0x000000ff -#define SSI_DMATDLR_RESET 0x00000000 +#define SSI_DMATDLR_OFFSET _u(0x00000050) +#define SSI_DMATDLR_BITS _u(0x000000ff) +#define SSI_DMATDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMATDLR_DMATDL // Description : Transmit data watermark level -#define SSI_DMATDLR_DMATDL_RESET 0x00 -#define SSI_DMATDLR_DMATDL_BITS 0x000000ff -#define SSI_DMATDLR_DMATDL_MSB 7 -#define SSI_DMATDLR_DMATDL_LSB 0 +#define SSI_DMATDLR_DMATDL_RESET _u(0x00) +#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff) +#define SSI_DMATDLR_DMATDL_MSB _u(7) +#define SSI_DMATDLR_DMATDL_LSB _u(0) #define SSI_DMATDLR_DMATDL_ACCESS "RW" // ============================================================================= // Register : SSI_DMARDLR // Description : DMA RX data level -#define SSI_DMARDLR_OFFSET 0x00000054 -#define SSI_DMARDLR_BITS 0x000000ff -#define SSI_DMARDLR_RESET 0x00000000 +#define SSI_DMARDLR_OFFSET _u(0x00000054) +#define SSI_DMARDLR_BITS _u(0x000000ff) +#define SSI_DMARDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMARDLR_DMARDL // Description : Receive data watermark level (DMARDLR+1) -#define SSI_DMARDLR_DMARDL_RESET 0x00 -#define SSI_DMARDLR_DMARDL_BITS 0x000000ff -#define SSI_DMARDLR_DMARDL_MSB 7 -#define SSI_DMARDLR_DMARDL_LSB 0 +#define SSI_DMARDLR_DMARDL_RESET _u(0x00) +#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff) +#define SSI_DMARDLR_DMARDL_MSB _u(7) +#define SSI_DMARDLR_DMARDL_LSB _u(0) #define SSI_DMARDLR_DMARDL_ACCESS "RW" // ============================================================================= // Register : SSI_IDR // Description : Identification register -#define SSI_IDR_OFFSET 0x00000058 -#define SSI_IDR_BITS 0xffffffff -#define SSI_IDR_RESET 0x51535049 +#define SSI_IDR_OFFSET _u(0x00000058) +#define SSI_IDR_BITS _u(0xffffffff) +#define SSI_IDR_RESET _u(0x51535049) // ----------------------------------------------------------------------------- // Field : SSI_IDR_IDCODE // Description : Peripheral dentification code -#define SSI_IDR_IDCODE_RESET 0x51535049 -#define SSI_IDR_IDCODE_BITS 0xffffffff -#define SSI_IDR_IDCODE_MSB 31 -#define SSI_IDR_IDCODE_LSB 0 +#define SSI_IDR_IDCODE_RESET _u(0x51535049) +#define SSI_IDR_IDCODE_BITS _u(0xffffffff) +#define SSI_IDR_IDCODE_MSB _u(31) +#define SSI_IDR_IDCODE_LSB _u(0) #define SSI_IDR_IDCODE_ACCESS "RO" // ============================================================================= // Register : SSI_SSI_VERSION_ID // Description : Version ID -#define SSI_SSI_VERSION_ID_OFFSET 0x0000005c -#define SSI_SSI_VERSION_ID_BITS 0xffffffff -#define SSI_SSI_VERSION_ID_RESET 0x3430312a +#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c) +#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff) +#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a) // ----------------------------------------------------------------------------- // Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION // Description : SNPS component version (format X.YY) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31 -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0) #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" // ============================================================================= // Register : SSI_DR0 // Description : Data Register 0 (of 36) -#define SSI_DR0_OFFSET 0x00000060 -#define SSI_DR0_BITS 0xffffffff -#define SSI_DR0_RESET 0x00000000 +#define SSI_DR0_OFFSET _u(0x00000060) +#define SSI_DR0_BITS _u(0xffffffff) +#define SSI_DR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DR0_DR // Description : First data register of 36 -#define SSI_DR0_DR_RESET 0x00000000 -#define SSI_DR0_DR_BITS 0xffffffff -#define SSI_DR0_DR_MSB 31 -#define SSI_DR0_DR_LSB 0 +#define SSI_DR0_DR_RESET _u(0x00000000) +#define SSI_DR0_DR_BITS _u(0xffffffff) +#define SSI_DR0_DR_MSB _u(31) +#define SSI_DR0_DR_LSB _u(0) #define SSI_DR0_DR_ACCESS "RW" // ============================================================================= // Register : SSI_RX_SAMPLE_DLY // Description : RX sample delay -#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 -#define SSI_RX_SAMPLE_DLY_BITS 0x000000ff -#define SSI_RX_SAMPLE_DLY_RESET 0x00000000 +#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0) +#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff) +#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RX_SAMPLE_DLY_RSD // Description : RXD sample delay (in SCLK cycles) -#define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00 -#define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff -#define SSI_RX_SAMPLE_DLY_RSD_MSB 7 -#define SSI_RX_SAMPLE_DLY_RSD_LSB 0 +#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00) +#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff) +#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7) +#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0) #define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" // ============================================================================= // Register : SSI_SPI_CTRLR0 // Description : SPI control -#define SSI_SPI_CTRLR0_OFFSET 0x000000f4 -#define SSI_SPI_CTRLR0_BITS 0xff07fb3f -#define SSI_SPI_CTRLR0_RESET 0x03000000 +#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4) +#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f) +#define SSI_SPI_CTRLR0_RESET _u(0x03000000) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_XIP_CMD // Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append // to Address (INST_L = 0-bit) -#define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03 -#define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000 -#define SSI_SPI_CTRLR0_XIP_CMD_MSB 31 -#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 +#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03) +#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000) +#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31) +#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24) #define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_SPI_RXDS_EN // Description : Read data strobe enable -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18) #define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_INST_DDR_EN // Description : Instruction DDR transfer enable -#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000 -#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17 -#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000) +#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17) +#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17) #define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_SPI_DDR_EN // Description : SPI DDR transfer enable -#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16) #define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_WAIT_CYCLES // Description : Wait cycles between control frame transmit and data reception // (in SCLK cycles) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11) #define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_INST_L @@ -758,22 +758,22 @@ // 0x1 -> 4-bit instruction // 0x2 -> 8-bit instruction // 0x3 -> 16-bit instruction -#define SSI_SPI_CTRLR0_INST_L_RESET 0x0 -#define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300 -#define SSI_SPI_CTRLR0_INST_L_MSB 9 -#define SSI_SPI_CTRLR0_INST_L_LSB 8 +#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) +#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) +#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) #define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" -#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 -#define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1 -#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 -#define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3 +#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_ADDR_L // Description : Address length (0b-60b in 4b increments) -#define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0 -#define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c -#define SSI_SPI_CTRLR0_ADDR_L_MSB 5 -#define SSI_SPI_CTRLR0_ADDR_L_LSB 2 +#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c) +#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5) +#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2) #define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_TRANS_TYPE @@ -783,27 +783,27 @@ // specified by FRF // 0x2 -> Command and address both in format specified by FRF // (e.g. Dual-SPI) -#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0 -#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003 -#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1 -#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) #define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0 -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2) // ============================================================================= // Register : SSI_TXD_DRIVE_EDGE // Description : TX drive edge -#define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8 -#define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff -#define SSI_TXD_DRIVE_EDGE_RESET 0x00000000 +#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8) +#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff) +#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXD_DRIVE_EDGE_TDE // Description : TXD drive edge -#define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00 -#define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff -#define SSI_TXD_DRIVE_EDGE_TDE_MSB 7 -#define SSI_TXD_DRIVE_EDGE_TDE_LSB 0 +#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00) +#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff) +#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7) +#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0) #define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SSI_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h index c1bcaf9dc8b..2bf09e26fad 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h @@ -15,38 +15,38 @@ // Register : SYSCFG_PROC0_NMI_MASK // Description : Processor core 0 NMI source mask // Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000 -#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff -#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000 -#define SYSCFG_PROC0_NMI_MASK_MSB 31 -#define SYSCFG_PROC0_NMI_MASK_LSB 0 +#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000) +#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff) +#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000) +#define SYSCFG_PROC0_NMI_MASK_MSB _u(31) +#define SYSCFG_PROC0_NMI_MASK_LSB _u(0) #define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC1_NMI_MASK // Description : Processor core 1 NMI source mask // Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004 -#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff -#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000 -#define SYSCFG_PROC1_NMI_MASK_MSB 31 -#define SYSCFG_PROC1_NMI_MASK_LSB 0 +#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004) +#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff) +#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000) +#define SYSCFG_PROC1_NMI_MASK_MSB _u(31) +#define SYSCFG_PROC1_NMI_MASK_LSB _u(0) #define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC_CONFIG // Description : Configuration for processors -#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008 -#define SYSCFG_PROC_CONFIG_BITS 0xff000003 -#define SYSCFG_PROC_CONFIG_RESET 0x10000000 +#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008) +#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003) +#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID // Description : Configure proc1 DAP instance ID. // Recommend that this is NOT changed until you require debug // access in multi-chip environment // WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28) #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID @@ -54,26 +54,26 @@ // Recommend that this is NOT changed until you require debug // access in multi-chip environment // WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24) #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC1_HALTED // Description : Indication that proc1 has halted -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) #define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC0_HALTED // Description : Indication that proc0 has halted -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) #define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" // ============================================================================= // Register : SYSCFG_PROC_IN_SYNC_BYPASS @@ -86,11 +86,11 @@ // If you're feeling brave, you can bypass to save two cycles of // input // latency. This register applies to GPIO 0...29. -#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c -#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff -#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000 -#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29 -#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c) +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29) +#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0) #define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI @@ -103,155 +103,155 @@ // If you're feeling brave, you can bypass to save two cycles of // input // latency. This register applies to GPIO 30...35 (the QSPI IOs). -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0) #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" // ============================================================================= // Register : SYSCFG_DBGFORCE // Description : Directly control the SWD debug port of either processor -#define SYSCFG_DBGFORCE_OFFSET 0x00000014 -#define SYSCFG_DBGFORCE_BITS 0x000000ff -#define SYSCFG_DBGFORCE_RESET 0x00000066 +#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014) +#define SYSCFG_DBGFORCE_BITS _u(0x000000ff) +#define SYSCFG_DBGFORCE_RESET _u(0x00000066) // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_ATTACH // Description : Attach processor 1 debug port to syscfg controls, and // disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7) #define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWCLK // Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6) #define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWDI // Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020 -#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5 -#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020) +#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5) +#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5) #define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWDO // Description : Observe the value of processor 1 SWDIO output. #define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010 -#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4 -#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010) +#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4) +#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4) #define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_ATTACH // Description : Attach processor 0 debug port to syscfg controls, and // disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3) #define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWCLK // Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2) #define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWDI // Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002 -#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1 -#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002) +#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1) +#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1) #define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWDO // Description : Observe the value of processor 0 SWDIO output. #define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001 -#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0 -#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001) +#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0) +#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0) #define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" // ============================================================================= // Register : SYSCFG_MEMPOWERDOWN // Description : Control power downs to memories. Set high to power down // memories. // Use with extreme caution -#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018 -#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff -#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000 +#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018) +#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff) +#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_ROM // Description : None -#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080 -#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7 -#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) +#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) +#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7) #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_USB // Description : None -#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040 -#define SYSCFG_MEMPOWERDOWN_USB_MSB 6 -#define SYSCFG_MEMPOWERDOWN_USB_LSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) +#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) +#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6) #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM5 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020 -#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5 -#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM4 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010 -#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4 -#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM3 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008 -#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3 -#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM2 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004 -#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2 -#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM1 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002 -#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1 -#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM0 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001 -#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SYSCFG_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h index 7a460374c05..2a46658e2ee 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h @@ -14,64 +14,64 @@ // ============================================================================= // Register : SYSINFO_CHIP_ID // Description : JEDEC JEP-106 compliant chip identifier. -#define SYSINFO_CHIP_ID_OFFSET 0x00000000 -#define SYSINFO_CHIP_ID_BITS 0xffffffff -#define SYSINFO_CHIP_ID_RESET 0x00000000 +#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) +#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) +#define SYSINFO_CHIP_ID_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION // Description : None #define SYSINFO_CHIP_ID_REVISION_RESET "-" -#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000 -#define SYSINFO_CHIP_ID_REVISION_MSB 31 -#define SYSINFO_CHIP_ID_REVISION_LSB 28 +#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) +#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) +#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART // Description : None #define SYSINFO_CHIP_ID_PART_RESET "-" -#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000 -#define SYSINFO_CHIP_ID_PART_MSB 27 -#define SYSINFO_CHIP_ID_PART_LSB 12 +#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) +#define SYSINFO_CHIP_ID_PART_MSB _u(27) +#define SYSINFO_CHIP_ID_PART_LSB _u(12) #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER // Description : None #define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" -#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff -#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11 -#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0 +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0) #define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" // ============================================================================= // Register : SYSINFO_PLATFORM // Description : Platform register. Allows software to know what environment it // is running in. -#define SYSINFO_PLATFORM_OFFSET 0x00000004 -#define SYSINFO_PLATFORM_BITS 0x00000003 -#define SYSINFO_PLATFORM_RESET 0x00000000 +#define SYSINFO_PLATFORM_OFFSET _u(0x00000004) +#define SYSINFO_PLATFORM_BITS _u(0x00000003) +#define SYSINFO_PLATFORM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_ASIC // Description : None -#define SYSINFO_PLATFORM_ASIC_RESET 0x0 -#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002 -#define SYSINFO_PLATFORM_ASIC_MSB 1 -#define SYSINFO_PLATFORM_ASIC_LSB 1 +#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0) +#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) +#define SYSINFO_PLATFORM_ASIC_MSB _u(1) +#define SYSINFO_PLATFORM_ASIC_LSB _u(1) #define SYSINFO_PLATFORM_ASIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_FPGA // Description : None -#define SYSINFO_PLATFORM_FPGA_RESET 0x0 -#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001 -#define SYSINFO_PLATFORM_FPGA_MSB 0 -#define SYSINFO_PLATFORM_FPGA_LSB 0 +#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0) +#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) +#define SYSINFO_PLATFORM_FPGA_MSB _u(0) +#define SYSINFO_PLATFORM_FPGA_LSB _u(0) #define SYSINFO_PLATFORM_FPGA_ACCESS "RO" // ============================================================================= // Register : SYSINFO_GITREF_RP2040 // Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040 -#define SYSINFO_GITREF_RP2040_BITS 0xffffffff +#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040) +#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) #define SYSINFO_GITREF_RP2040_RESET "-" -#define SYSINFO_GITREF_RP2040_MSB 31 -#define SYSINFO_GITREF_RP2040_LSB 0 +#define SYSINFO_GITREF_RP2040_MSB _u(31) +#define SYSINFO_GITREF_RP2040_LSB _u(0) #define SYSINFO_GITREF_RP2040_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_SYSINFO_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h index 6bf9b2959bd..4f8f641321d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h @@ -15,24 +15,24 @@ // ============================================================================= // Register : TBMAN_PLATFORM // Description : Indicates the type of platform in use -#define TBMAN_PLATFORM_OFFSET 0x00000000 -#define TBMAN_PLATFORM_BITS 0x00000003 -#define TBMAN_PLATFORM_RESET 0x00000005 +#define TBMAN_PLATFORM_OFFSET _u(0x00000000) +#define TBMAN_PLATFORM_BITS _u(0x00000003) +#define TBMAN_PLATFORM_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : TBMAN_PLATFORM_FPGA // Description : Indicates the platform is an FPGA -#define TBMAN_PLATFORM_FPGA_RESET 0x0 -#define TBMAN_PLATFORM_FPGA_BITS 0x00000002 -#define TBMAN_PLATFORM_FPGA_MSB 1 -#define TBMAN_PLATFORM_FPGA_LSB 1 +#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) +#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) +#define TBMAN_PLATFORM_FPGA_MSB _u(1) +#define TBMAN_PLATFORM_FPGA_LSB _u(1) #define TBMAN_PLATFORM_FPGA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TBMAN_PLATFORM_ASIC // Description : Indicates the platform is an ASIC -#define TBMAN_PLATFORM_ASIC_RESET 0x1 -#define TBMAN_PLATFORM_ASIC_BITS 0x00000001 -#define TBMAN_PLATFORM_ASIC_MSB 0 -#define TBMAN_PLATFORM_ASIC_LSB 0 +#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) +#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) +#define TBMAN_PLATFORM_ASIC_MSB _u(0) +#define TBMAN_PLATFORM_ASIC_LSB _u(0) #define TBMAN_PLATFORM_ASIC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_TBMAN_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h index a2209b690a9..c3ef0c5a1bf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h @@ -31,40 +31,40 @@ // Register : TIMER_TIMEHW // Description : Write to bits 63:32 of time // always write timelw before timehw -#define TIMER_TIMEHW_OFFSET 0x00000000 -#define TIMER_TIMEHW_BITS 0xffffffff -#define TIMER_TIMEHW_RESET 0x00000000 -#define TIMER_TIMEHW_MSB 31 -#define TIMER_TIMEHW_LSB 0 +#define TIMER_TIMEHW_OFFSET _u(0x00000000) +#define TIMER_TIMEHW_BITS _u(0xffffffff) +#define TIMER_TIMEHW_RESET _u(0x00000000) +#define TIMER_TIMEHW_MSB _u(31) +#define TIMER_TIMEHW_LSB _u(0) #define TIMER_TIMEHW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMELW // Description : Write to bits 31:0 of time // writes do not get copied to time until timehw is written -#define TIMER_TIMELW_OFFSET 0x00000004 -#define TIMER_TIMELW_BITS 0xffffffff -#define TIMER_TIMELW_RESET 0x00000000 -#define TIMER_TIMELW_MSB 31 -#define TIMER_TIMELW_LSB 0 +#define TIMER_TIMELW_OFFSET _u(0x00000004) +#define TIMER_TIMELW_BITS _u(0xffffffff) +#define TIMER_TIMELW_RESET _u(0x00000000) +#define TIMER_TIMELW_MSB _u(31) +#define TIMER_TIMELW_LSB _u(0) #define TIMER_TIMELW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMEHR // Description : Read from bits 63:32 of time // always read timelr before timehr -#define TIMER_TIMEHR_OFFSET 0x00000008 -#define TIMER_TIMEHR_BITS 0xffffffff -#define TIMER_TIMEHR_RESET 0x00000000 -#define TIMER_TIMEHR_MSB 31 -#define TIMER_TIMEHR_LSB 0 +#define TIMER_TIMEHR_OFFSET _u(0x00000008) +#define TIMER_TIMEHR_BITS _u(0xffffffff) +#define TIMER_TIMEHR_RESET _u(0x00000000) +#define TIMER_TIMEHR_MSB _u(31) +#define TIMER_TIMEHR_LSB _u(0) #define TIMER_TIMEHR_ACCESS "RO" // ============================================================================= // Register : TIMER_TIMELR // Description : Read from bits 31:0 of time -#define TIMER_TIMELR_OFFSET 0x0000000c -#define TIMER_TIMELR_BITS 0xffffffff -#define TIMER_TIMELR_RESET 0x00000000 -#define TIMER_TIMELR_MSB 31 -#define TIMER_TIMELR_LSB 0 +#define TIMER_TIMELR_OFFSET _u(0x0000000c) +#define TIMER_TIMELR_BITS _u(0xffffffff) +#define TIMER_TIMELR_RESET _u(0x00000000) +#define TIMER_TIMELR_MSB _u(31) +#define TIMER_TIMELR_LSB _u(0) #define TIMER_TIMELR_ACCESS "RO" // ============================================================================= // Register : TIMER_ALARM0 @@ -72,11 +72,11 @@ // Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM0_OFFSET 0x00000010 -#define TIMER_ALARM0_BITS 0xffffffff -#define TIMER_ALARM0_RESET 0x00000000 -#define TIMER_ALARM0_MSB 31 -#define TIMER_ALARM0_LSB 0 +#define TIMER_ALARM0_OFFSET _u(0x00000010) +#define TIMER_ALARM0_BITS _u(0xffffffff) +#define TIMER_ALARM0_RESET _u(0x00000000) +#define TIMER_ALARM0_MSB _u(31) +#define TIMER_ALARM0_LSB _u(0) #define TIMER_ALARM0_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM1 @@ -84,11 +84,11 @@ // Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM1_OFFSET 0x00000014 -#define TIMER_ALARM1_BITS 0xffffffff -#define TIMER_ALARM1_RESET 0x00000000 -#define TIMER_ALARM1_MSB 31 -#define TIMER_ALARM1_LSB 0 +#define TIMER_ALARM1_OFFSET _u(0x00000014) +#define TIMER_ALARM1_BITS _u(0xffffffff) +#define TIMER_ALARM1_RESET _u(0x00000000) +#define TIMER_ALARM1_MSB _u(31) +#define TIMER_ALARM1_LSB _u(0) #define TIMER_ALARM1_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM2 @@ -96,11 +96,11 @@ // Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM2_OFFSET 0x00000018 -#define TIMER_ALARM2_BITS 0xffffffff -#define TIMER_ALARM2_RESET 0x00000000 -#define TIMER_ALARM2_MSB 31 -#define TIMER_ALARM2_LSB 0 +#define TIMER_ALARM2_OFFSET _u(0x00000018) +#define TIMER_ALARM2_BITS _u(0xffffffff) +#define TIMER_ALARM2_RESET _u(0x00000000) +#define TIMER_ALARM2_MSB _u(31) +#define TIMER_ALARM2_LSB _u(0) #define TIMER_ALARM2_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM3 @@ -108,11 +108,11 @@ // Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM3_OFFSET 0x0000001c -#define TIMER_ALARM3_BITS 0xffffffff -#define TIMER_ALARM3_RESET 0x00000000 -#define TIMER_ALARM3_MSB 31 -#define TIMER_ALARM3_LSB 0 +#define TIMER_ALARM3_OFFSET _u(0x0000001c) +#define TIMER_ALARM3_BITS _u(0xffffffff) +#define TIMER_ALARM3_RESET _u(0x00000000) +#define TIMER_ALARM3_MSB _u(31) +#define TIMER_ALARM3_LSB _u(0) #define TIMER_ALARM3_ACCESS "RW" // ============================================================================= // Register : TIMER_ARMED @@ -120,213 +120,213 @@ // A write to the corresponding ALARMx register arms the alarm. // Alarms automatically disarm upon firing, but writing ones here // will disarm immediately without waiting to fire. -#define TIMER_ARMED_OFFSET 0x00000020 -#define TIMER_ARMED_BITS 0x0000000f -#define TIMER_ARMED_RESET 0x00000000 -#define TIMER_ARMED_MSB 3 -#define TIMER_ARMED_LSB 0 +#define TIMER_ARMED_OFFSET _u(0x00000020) +#define TIMER_ARMED_BITS _u(0x0000000f) +#define TIMER_ARMED_RESET _u(0x00000000) +#define TIMER_ARMED_MSB _u(3) +#define TIMER_ARMED_LSB _u(0) #define TIMER_ARMED_ACCESS "WC" // ============================================================================= // Register : TIMER_TIMERAWH // Description : Raw read from bits 63:32 of time (no side effects) -#define TIMER_TIMERAWH_OFFSET 0x00000024 -#define TIMER_TIMERAWH_BITS 0xffffffff -#define TIMER_TIMERAWH_RESET 0x00000000 -#define TIMER_TIMERAWH_MSB 31 -#define TIMER_TIMERAWH_LSB 0 +#define TIMER_TIMERAWH_OFFSET _u(0x00000024) +#define TIMER_TIMERAWH_BITS _u(0xffffffff) +#define TIMER_TIMERAWH_RESET _u(0x00000000) +#define TIMER_TIMERAWH_MSB _u(31) +#define TIMER_TIMERAWH_LSB _u(0) #define TIMER_TIMERAWH_ACCESS "RO" // ============================================================================= // Register : TIMER_TIMERAWL // Description : Raw read from bits 31:0 of time (no side effects) -#define TIMER_TIMERAWL_OFFSET 0x00000028 -#define TIMER_TIMERAWL_BITS 0xffffffff -#define TIMER_TIMERAWL_RESET 0x00000000 -#define TIMER_TIMERAWL_MSB 31 -#define TIMER_TIMERAWL_LSB 0 +#define TIMER_TIMERAWL_OFFSET _u(0x00000028) +#define TIMER_TIMERAWL_BITS _u(0xffffffff) +#define TIMER_TIMERAWL_RESET _u(0x00000000) +#define TIMER_TIMERAWL_MSB _u(31) +#define TIMER_TIMERAWL_LSB _u(0) #define TIMER_TIMERAWL_ACCESS "RO" // ============================================================================= // Register : TIMER_DBGPAUSE // Description : Set bits high to enable pause when the corresponding debug // ports are active -#define TIMER_DBGPAUSE_OFFSET 0x0000002c -#define TIMER_DBGPAUSE_BITS 0x00000006 -#define TIMER_DBGPAUSE_RESET 0x00000007 +#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) +#define TIMER_DBGPAUSE_BITS _u(0x00000006) +#define TIMER_DBGPAUSE_RESET _u(0x00000007) // ----------------------------------------------------------------------------- // Field : TIMER_DBGPAUSE_DBG1 // Description : Pause when processor 1 is in debug mode -#define TIMER_DBGPAUSE_DBG1_RESET 0x1 -#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004 -#define TIMER_DBGPAUSE_DBG1_MSB 2 -#define TIMER_DBGPAUSE_DBG1_LSB 2 +#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) +#define TIMER_DBGPAUSE_DBG1_MSB _u(2) +#define TIMER_DBGPAUSE_DBG1_LSB _u(2) #define TIMER_DBGPAUSE_DBG1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_DBGPAUSE_DBG0 // Description : Pause when processor 0 is in debug mode -#define TIMER_DBGPAUSE_DBG0_RESET 0x1 -#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002 -#define TIMER_DBGPAUSE_DBG0_MSB 1 -#define TIMER_DBGPAUSE_DBG0_LSB 1 +#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) +#define TIMER_DBGPAUSE_DBG0_MSB _u(1) +#define TIMER_DBGPAUSE_DBG0_LSB _u(1) #define TIMER_DBGPAUSE_DBG0_ACCESS "RW" // ============================================================================= // Register : TIMER_PAUSE // Description : Set high to pause the timer -#define TIMER_PAUSE_OFFSET 0x00000030 -#define TIMER_PAUSE_BITS 0x00000001 -#define TIMER_PAUSE_RESET 0x00000000 -#define TIMER_PAUSE_MSB 0 -#define TIMER_PAUSE_LSB 0 +#define TIMER_PAUSE_OFFSET _u(0x00000030) +#define TIMER_PAUSE_BITS _u(0x00000001) +#define TIMER_PAUSE_RESET _u(0x00000000) +#define TIMER_PAUSE_MSB _u(0) +#define TIMER_PAUSE_LSB _u(0) #define TIMER_PAUSE_ACCESS "RW" // ============================================================================= // Register : TIMER_INTR // Description : Raw Interrupts -#define TIMER_INTR_OFFSET 0x00000034 -#define TIMER_INTR_BITS 0x0000000f -#define TIMER_INTR_RESET 0x00000000 +#define TIMER_INTR_OFFSET _u(0x00000034) +#define TIMER_INTR_BITS _u(0x0000000f) +#define TIMER_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_3 // Description : None -#define TIMER_INTR_ALARM_3_RESET 0x0 -#define TIMER_INTR_ALARM_3_BITS 0x00000008 -#define TIMER_INTR_ALARM_3_MSB 3 -#define TIMER_INTR_ALARM_3_LSB 3 +#define TIMER_INTR_ALARM_3_RESET _u(0x0) +#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTR_ALARM_3_MSB _u(3) +#define TIMER_INTR_ALARM_3_LSB _u(3) #define TIMER_INTR_ALARM_3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_2 // Description : None -#define TIMER_INTR_ALARM_2_RESET 0x0 -#define TIMER_INTR_ALARM_2_BITS 0x00000004 -#define TIMER_INTR_ALARM_2_MSB 2 -#define TIMER_INTR_ALARM_2_LSB 2 +#define TIMER_INTR_ALARM_2_RESET _u(0x0) +#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTR_ALARM_2_MSB _u(2) +#define TIMER_INTR_ALARM_2_LSB _u(2) #define TIMER_INTR_ALARM_2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_1 // Description : None -#define TIMER_INTR_ALARM_1_RESET 0x0 -#define TIMER_INTR_ALARM_1_BITS 0x00000002 -#define TIMER_INTR_ALARM_1_MSB 1 -#define TIMER_INTR_ALARM_1_LSB 1 +#define TIMER_INTR_ALARM_1_RESET _u(0x0) +#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTR_ALARM_1_MSB _u(1) +#define TIMER_INTR_ALARM_1_LSB _u(1) #define TIMER_INTR_ALARM_1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_0 // Description : None -#define TIMER_INTR_ALARM_0_RESET 0x0 -#define TIMER_INTR_ALARM_0_BITS 0x00000001 -#define TIMER_INTR_ALARM_0_MSB 0 -#define TIMER_INTR_ALARM_0_LSB 0 +#define TIMER_INTR_ALARM_0_RESET _u(0x0) +#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTR_ALARM_0_MSB _u(0) +#define TIMER_INTR_ALARM_0_LSB _u(0) #define TIMER_INTR_ALARM_0_ACCESS "WC" // ============================================================================= // Register : TIMER_INTE // Description : Interrupt Enable -#define TIMER_INTE_OFFSET 0x00000038 -#define TIMER_INTE_BITS 0x0000000f -#define TIMER_INTE_RESET 0x00000000 +#define TIMER_INTE_OFFSET _u(0x00000038) +#define TIMER_INTE_BITS _u(0x0000000f) +#define TIMER_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_3 // Description : None -#define TIMER_INTE_ALARM_3_RESET 0x0 -#define TIMER_INTE_ALARM_3_BITS 0x00000008 -#define TIMER_INTE_ALARM_3_MSB 3 -#define TIMER_INTE_ALARM_3_LSB 3 +#define TIMER_INTE_ALARM_3_RESET _u(0x0) +#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTE_ALARM_3_MSB _u(3) +#define TIMER_INTE_ALARM_3_LSB _u(3) #define TIMER_INTE_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_2 // Description : None -#define TIMER_INTE_ALARM_2_RESET 0x0 -#define TIMER_INTE_ALARM_2_BITS 0x00000004 -#define TIMER_INTE_ALARM_2_MSB 2 -#define TIMER_INTE_ALARM_2_LSB 2 +#define TIMER_INTE_ALARM_2_RESET _u(0x0) +#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTE_ALARM_2_MSB _u(2) +#define TIMER_INTE_ALARM_2_LSB _u(2) #define TIMER_INTE_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_1 // Description : None -#define TIMER_INTE_ALARM_1_RESET 0x0 -#define TIMER_INTE_ALARM_1_BITS 0x00000002 -#define TIMER_INTE_ALARM_1_MSB 1 -#define TIMER_INTE_ALARM_1_LSB 1 +#define TIMER_INTE_ALARM_1_RESET _u(0x0) +#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTE_ALARM_1_MSB _u(1) +#define TIMER_INTE_ALARM_1_LSB _u(1) #define TIMER_INTE_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_0 // Description : None -#define TIMER_INTE_ALARM_0_RESET 0x0 -#define TIMER_INTE_ALARM_0_BITS 0x00000001 -#define TIMER_INTE_ALARM_0_MSB 0 -#define TIMER_INTE_ALARM_0_LSB 0 +#define TIMER_INTE_ALARM_0_RESET _u(0x0) +#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTE_ALARM_0_MSB _u(0) +#define TIMER_INTE_ALARM_0_LSB _u(0) #define TIMER_INTE_ALARM_0_ACCESS "RW" // ============================================================================= // Register : TIMER_INTF // Description : Interrupt Force -#define TIMER_INTF_OFFSET 0x0000003c -#define TIMER_INTF_BITS 0x0000000f -#define TIMER_INTF_RESET 0x00000000 +#define TIMER_INTF_OFFSET _u(0x0000003c) +#define TIMER_INTF_BITS _u(0x0000000f) +#define TIMER_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_3 // Description : None -#define TIMER_INTF_ALARM_3_RESET 0x0 -#define TIMER_INTF_ALARM_3_BITS 0x00000008 -#define TIMER_INTF_ALARM_3_MSB 3 -#define TIMER_INTF_ALARM_3_LSB 3 +#define TIMER_INTF_ALARM_3_RESET _u(0x0) +#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTF_ALARM_3_MSB _u(3) +#define TIMER_INTF_ALARM_3_LSB _u(3) #define TIMER_INTF_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_2 // Description : None -#define TIMER_INTF_ALARM_2_RESET 0x0 -#define TIMER_INTF_ALARM_2_BITS 0x00000004 -#define TIMER_INTF_ALARM_2_MSB 2 -#define TIMER_INTF_ALARM_2_LSB 2 +#define TIMER_INTF_ALARM_2_RESET _u(0x0) +#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTF_ALARM_2_MSB _u(2) +#define TIMER_INTF_ALARM_2_LSB _u(2) #define TIMER_INTF_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_1 // Description : None -#define TIMER_INTF_ALARM_1_RESET 0x0 -#define TIMER_INTF_ALARM_1_BITS 0x00000002 -#define TIMER_INTF_ALARM_1_MSB 1 -#define TIMER_INTF_ALARM_1_LSB 1 +#define TIMER_INTF_ALARM_1_RESET _u(0x0) +#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTF_ALARM_1_MSB _u(1) +#define TIMER_INTF_ALARM_1_LSB _u(1) #define TIMER_INTF_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_0 // Description : None -#define TIMER_INTF_ALARM_0_RESET 0x0 -#define TIMER_INTF_ALARM_0_BITS 0x00000001 -#define TIMER_INTF_ALARM_0_MSB 0 -#define TIMER_INTF_ALARM_0_LSB 0 +#define TIMER_INTF_ALARM_0_RESET _u(0x0) +#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTF_ALARM_0_MSB _u(0) +#define TIMER_INTF_ALARM_0_LSB _u(0) #define TIMER_INTF_ALARM_0_ACCESS "RW" // ============================================================================= // Register : TIMER_INTS // Description : Interrupt status after masking & forcing -#define TIMER_INTS_OFFSET 0x00000040 -#define TIMER_INTS_BITS 0x0000000f -#define TIMER_INTS_RESET 0x00000000 +#define TIMER_INTS_OFFSET _u(0x00000040) +#define TIMER_INTS_BITS _u(0x0000000f) +#define TIMER_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_3 // Description : None -#define TIMER_INTS_ALARM_3_RESET 0x0 -#define TIMER_INTS_ALARM_3_BITS 0x00000008 -#define TIMER_INTS_ALARM_3_MSB 3 -#define TIMER_INTS_ALARM_3_LSB 3 +#define TIMER_INTS_ALARM_3_RESET _u(0x0) +#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTS_ALARM_3_MSB _u(3) +#define TIMER_INTS_ALARM_3_LSB _u(3) #define TIMER_INTS_ALARM_3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_2 // Description : None -#define TIMER_INTS_ALARM_2_RESET 0x0 -#define TIMER_INTS_ALARM_2_BITS 0x00000004 -#define TIMER_INTS_ALARM_2_MSB 2 -#define TIMER_INTS_ALARM_2_LSB 2 +#define TIMER_INTS_ALARM_2_RESET _u(0x0) +#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTS_ALARM_2_MSB _u(2) +#define TIMER_INTS_ALARM_2_LSB _u(2) #define TIMER_INTS_ALARM_2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_1 // Description : None -#define TIMER_INTS_ALARM_1_RESET 0x0 -#define TIMER_INTS_ALARM_1_BITS 0x00000002 -#define TIMER_INTS_ALARM_1_MSB 1 -#define TIMER_INTS_ALARM_1_LSB 1 +#define TIMER_INTS_ALARM_1_RESET _u(0x0) +#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTS_ALARM_1_MSB _u(1) +#define TIMER_INTS_ALARM_1_LSB _u(1) #define TIMER_INTS_ALARM_1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_0 // Description : None -#define TIMER_INTS_ALARM_0_RESET 0x0 -#define TIMER_INTS_ALARM_0_BITS 0x00000001 -#define TIMER_INTS_ALARM_0_MSB 0 -#define TIMER_INTS_ALARM_0_LSB 0 +#define TIMER_INTS_ALARM_0_RESET _u(0x0) +#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTS_ALARM_0_MSB _u(0) +#define TIMER_INTS_ALARM_0_LSB _u(0) #define TIMER_INTS_ALARM_0_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_TIMER_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h index 8fde5d19738..409f59821ac 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : UART_UARTDR // Description : Data Register, UARTDR -#define UART_UARTDR_OFFSET 0x00000000 -#define UART_UARTDR_BITS 0x00000fff -#define UART_UARTDR_RESET 0x00000000 +#define UART_UARTDR_OFFSET _u(0x00000000) +#define UART_UARTDR_BITS _u(0x00000fff) +#define UART_UARTDR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTDR_OE // Description : Overrun error. This bit is set to 1 if data is received and the @@ -24,9 +24,9 @@ // is an empty space in the FIFO and a new character can be // written to it. #define UART_UARTDR_OE_RESET "-" -#define UART_UARTDR_OE_BITS 0x00000800 -#define UART_UARTDR_OE_MSB 11 -#define UART_UARTDR_OE_LSB 11 +#define UART_UARTDR_OE_BITS _u(0x00000800) +#define UART_UARTDR_OE_MSB _u(11) +#define UART_UARTDR_OE_LSB _u(11) #define UART_UARTDR_OE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_BE @@ -40,9 +40,9 @@ // goes to a 1 (marking state), and the next valid start bit is // received. #define UART_UARTDR_BE_RESET "-" -#define UART_UARTDR_BE_BITS 0x00000400 -#define UART_UARTDR_BE_MSB 10 -#define UART_UARTDR_BE_LSB 10 +#define UART_UARTDR_BE_BITS _u(0x00000400) +#define UART_UARTDR_BE_MSB _u(10) +#define UART_UARTDR_BE_LSB _u(10) #define UART_UARTDR_BE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_PE @@ -52,9 +52,9 @@ // FIFO mode, this error is associated with the character at the // top of the FIFO. #define UART_UARTDR_PE_RESET "-" -#define UART_UARTDR_PE_BITS 0x00000200 -#define UART_UARTDR_PE_MSB 9 -#define UART_UARTDR_PE_LSB 9 +#define UART_UARTDR_PE_BITS _u(0x00000200) +#define UART_UARTDR_PE_MSB _u(9) +#define UART_UARTDR_PE_LSB _u(9) #define UART_UARTDR_PE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_FE @@ -63,24 +63,24 @@ // 1). In FIFO mode, this error is associated with the character // at the top of the FIFO. #define UART_UARTDR_FE_RESET "-" -#define UART_UARTDR_FE_BITS 0x00000100 -#define UART_UARTDR_FE_MSB 8 -#define UART_UARTDR_FE_LSB 8 +#define UART_UARTDR_FE_BITS _u(0x00000100) +#define UART_UARTDR_FE_MSB _u(8) +#define UART_UARTDR_FE_LSB _u(8) #define UART_UARTDR_FE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_DATA // Description : Receive (read) data character. Transmit (write) data character. #define UART_UARTDR_DATA_RESET "-" -#define UART_UARTDR_DATA_BITS 0x000000ff -#define UART_UARTDR_DATA_MSB 7 -#define UART_UARTDR_DATA_LSB 0 +#define UART_UARTDR_DATA_BITS _u(0x000000ff) +#define UART_UARTDR_DATA_MSB _u(7) +#define UART_UARTDR_DATA_LSB _u(0) #define UART_UARTDR_DATA_ACCESS "RWF" // ============================================================================= // Register : UART_UARTRSR // Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR -#define UART_UARTRSR_OFFSET 0x00000004 -#define UART_UARTRSR_BITS 0x0000000f -#define UART_UARTRSR_RESET 0x00000000 +#define UART_UARTRSR_OFFSET _u(0x00000004) +#define UART_UARTRSR_BITS _u(0x0000000f) +#define UART_UARTRSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_OE // Description : Overrun error. This bit is set to 1 if data is received and the @@ -89,10 +89,10 @@ // written when the FIFO is full, only the contents of the shift // register are overwritten. The CPU must now read the data, to // empty the FIFO. -#define UART_UARTRSR_OE_RESET 0x0 -#define UART_UARTRSR_OE_BITS 0x00000008 -#define UART_UARTRSR_OE_MSB 3 -#define UART_UARTRSR_OE_LSB 3 +#define UART_UARTRSR_OE_RESET _u(0x0) +#define UART_UARTRSR_OE_BITS _u(0x00000008) +#define UART_UARTRSR_OE_MSB _u(3) +#define UART_UARTRSR_OE_LSB _u(3) #define UART_UARTRSR_OE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_BE @@ -106,10 +106,10 @@ // next character is only enabled after the receive data input // goes to a 1 (marking state) and the next valid start bit is // received. -#define UART_UARTRSR_BE_RESET 0x0 -#define UART_UARTRSR_BE_BITS 0x00000004 -#define UART_UARTRSR_BE_MSB 2 -#define UART_UARTRSR_BE_LSB 2 +#define UART_UARTRSR_BE_RESET _u(0x0) +#define UART_UARTRSR_BE_BITS _u(0x00000004) +#define UART_UARTRSR_BE_MSB _u(2) +#define UART_UARTRSR_BE_LSB _u(2) #define UART_UARTRSR_BE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_PE @@ -118,10 +118,10 @@ // EPS and SPS bits in the Line Control Register, UARTLCR_H. This // bit is cleared to 0 by a write to UARTECR. In FIFO mode, this // error is associated with the character at the top of the FIFO. -#define UART_UARTRSR_PE_RESET 0x0 -#define UART_UARTRSR_PE_BITS 0x00000002 -#define UART_UARTRSR_PE_MSB 1 -#define UART_UARTRSR_PE_LSB 1 +#define UART_UARTRSR_PE_RESET _u(0x0) +#define UART_UARTRSR_PE_BITS _u(0x00000002) +#define UART_UARTRSR_PE_MSB _u(1) +#define UART_UARTRSR_PE_LSB _u(1) #define UART_UARTRSR_PE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_FE @@ -130,26 +130,26 @@ // 1). This bit is cleared to 0 by a write to UARTECR. In FIFO // mode, this error is associated with the character at the top of // the FIFO. -#define UART_UARTRSR_FE_RESET 0x0 -#define UART_UARTRSR_FE_BITS 0x00000001 -#define UART_UARTRSR_FE_MSB 0 -#define UART_UARTRSR_FE_LSB 0 +#define UART_UARTRSR_FE_RESET _u(0x0) +#define UART_UARTRSR_FE_BITS _u(0x00000001) +#define UART_UARTRSR_FE_MSB _u(0) +#define UART_UARTRSR_FE_LSB _u(0) #define UART_UARTRSR_FE_ACCESS "WC" // ============================================================================= // Register : UART_UARTFR // Description : Flag Register, UARTFR -#define UART_UARTFR_OFFSET 0x00000018 -#define UART_UARTFR_BITS 0x000001ff -#define UART_UARTFR_RESET 0x00000090 +#define UART_UARTFR_OFFSET _u(0x00000018) +#define UART_UARTFR_BITS _u(0x000001ff) +#define UART_UARTFR_RESET _u(0x00000090) // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RI // Description : Ring indicator. This bit is the complement of the UART ring // indicator, nUARTRI, modem status input. That is, the bit is 1 // when nUARTRI is LOW. #define UART_UARTFR_RI_RESET "-" -#define UART_UARTFR_RI_BITS 0x00000100 -#define UART_UARTFR_RI_MSB 8 -#define UART_UARTFR_RI_LSB 8 +#define UART_UARTFR_RI_BITS _u(0x00000100) +#define UART_UARTFR_RI_MSB _u(8) +#define UART_UARTFR_RI_LSB _u(8) #define UART_UARTFR_RI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_TXFE @@ -159,10 +159,10 @@ // holding register is empty. If the FIFO is enabled, the TXFE bit // is set when the transmit FIFO is empty. This bit does not // indicate if there is data in the transmit shift register. -#define UART_UARTFR_TXFE_RESET 0x1 -#define UART_UARTFR_TXFE_BITS 0x00000080 -#define UART_UARTFR_TXFE_MSB 7 -#define UART_UARTFR_TXFE_LSB 7 +#define UART_UARTFR_TXFE_RESET _u(0x1) +#define UART_UARTFR_TXFE_BITS _u(0x00000080) +#define UART_UARTFR_TXFE_MSB _u(7) +#define UART_UARTFR_TXFE_LSB _u(7) #define UART_UARTFR_TXFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RXFF @@ -171,10 +171,10 @@ // disabled, this bit is set when the receive holding register is // full. If the FIFO is enabled, the RXFF bit is set when the // receive FIFO is full. -#define UART_UARTFR_RXFF_RESET 0x0 -#define UART_UARTFR_RXFF_BITS 0x00000040 -#define UART_UARTFR_RXFF_MSB 6 -#define UART_UARTFR_RXFF_LSB 6 +#define UART_UARTFR_RXFF_RESET _u(0x0) +#define UART_UARTFR_RXFF_BITS _u(0x00000040) +#define UART_UARTFR_RXFF_MSB _u(6) +#define UART_UARTFR_RXFF_LSB _u(6) #define UART_UARTFR_RXFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_TXFF @@ -183,10 +183,10 @@ // disabled, this bit is set when the transmit holding register is // full. If the FIFO is enabled, the TXFF bit is set when the // transmit FIFO is full. -#define UART_UARTFR_TXFF_RESET 0x0 -#define UART_UARTFR_TXFF_BITS 0x00000020 -#define UART_UARTFR_TXFF_MSB 5 -#define UART_UARTFR_TXFF_LSB 5 +#define UART_UARTFR_TXFF_RESET _u(0x0) +#define UART_UARTFR_TXFF_BITS _u(0x00000020) +#define UART_UARTFR_TXFF_MSB _u(5) +#define UART_UARTFR_TXFF_LSB _u(5) #define UART_UARTFR_TXFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RXFE @@ -195,10 +195,10 @@ // disabled, this bit is set when the receive holding register is // empty. If the FIFO is enabled, the RXFE bit is set when the // receive FIFO is empty. -#define UART_UARTFR_RXFE_RESET 0x1 -#define UART_UARTFR_RXFE_BITS 0x00000010 -#define UART_UARTFR_RXFE_MSB 4 -#define UART_UARTFR_RXFE_LSB 4 +#define UART_UARTFR_RXFE_RESET _u(0x1) +#define UART_UARTFR_RXFE_BITS _u(0x00000010) +#define UART_UARTFR_RXFE_MSB _u(4) +#define UART_UARTFR_RXFE_LSB _u(4) #define UART_UARTFR_RXFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_BUSY @@ -207,10 +207,10 @@ // byte, including all the stop bits, has been sent from the shift // register. This bit is set as soon as the transmit FIFO becomes // non-empty, regardless of whether the UART is enabled or not. -#define UART_UARTFR_BUSY_RESET 0x0 -#define UART_UARTFR_BUSY_BITS 0x00000008 -#define UART_UARTFR_BUSY_MSB 3 -#define UART_UARTFR_BUSY_LSB 3 +#define UART_UARTFR_BUSY_RESET _u(0x0) +#define UART_UARTFR_BUSY_BITS _u(0x00000008) +#define UART_UARTFR_BUSY_MSB _u(3) +#define UART_UARTFR_BUSY_LSB _u(3) #define UART_UARTFR_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_DCD @@ -218,9 +218,9 @@ // data carrier detect, nUARTDCD, modem status input. That is, the // bit is 1 when nUARTDCD is LOW. #define UART_UARTFR_DCD_RESET "-" -#define UART_UARTFR_DCD_BITS 0x00000004 -#define UART_UARTFR_DCD_MSB 2 -#define UART_UARTFR_DCD_LSB 2 +#define UART_UARTFR_DCD_BITS _u(0x00000004) +#define UART_UARTFR_DCD_MSB _u(2) +#define UART_UARTFR_DCD_LSB _u(2) #define UART_UARTFR_DCD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_DSR @@ -228,9 +228,9 @@ // ready, nUARTDSR, modem status input. That is, the bit is 1 when // nUARTDSR is LOW. #define UART_UARTFR_DSR_RESET "-" -#define UART_UARTFR_DSR_BITS 0x00000002 -#define UART_UARTFR_DSR_MSB 1 -#define UART_UARTFR_DSR_LSB 1 +#define UART_UARTFR_DSR_BITS _u(0x00000002) +#define UART_UARTFR_DSR_MSB _u(1) +#define UART_UARTFR_DSR_LSB _u(1) #define UART_UARTFR_DSR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_CTS @@ -238,61 +238,61 @@ // send, nUARTCTS, modem status input. That is, the bit is 1 when // nUARTCTS is LOW. #define UART_UARTFR_CTS_RESET "-" -#define UART_UARTFR_CTS_BITS 0x00000001 -#define UART_UARTFR_CTS_MSB 0 -#define UART_UARTFR_CTS_LSB 0 +#define UART_UARTFR_CTS_BITS _u(0x00000001) +#define UART_UARTFR_CTS_MSB _u(0) +#define UART_UARTFR_CTS_LSB _u(0) #define UART_UARTFR_CTS_ACCESS "RO" // ============================================================================= // Register : UART_UARTILPR // Description : IrDA Low-Power Counter Register, UARTILPR -#define UART_UARTILPR_OFFSET 0x00000020 -#define UART_UARTILPR_BITS 0x000000ff -#define UART_UARTILPR_RESET 0x00000000 +#define UART_UARTILPR_OFFSET _u(0x00000020) +#define UART_UARTILPR_BITS _u(0x000000ff) +#define UART_UARTILPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTILPR_ILPDVSR // Description : 8-bit low-power divisor value. These bits are cleared to 0 at // reset. -#define UART_UARTILPR_ILPDVSR_RESET 0x00 -#define UART_UARTILPR_ILPDVSR_BITS 0x000000ff -#define UART_UARTILPR_ILPDVSR_MSB 7 -#define UART_UARTILPR_ILPDVSR_LSB 0 +#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) +#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) +#define UART_UARTILPR_ILPDVSR_MSB _u(7) +#define UART_UARTILPR_ILPDVSR_LSB _u(0) #define UART_UARTILPR_ILPDVSR_ACCESS "RW" // ============================================================================= // Register : UART_UARTIBRD // Description : Integer Baud Rate Register, UARTIBRD -#define UART_UARTIBRD_OFFSET 0x00000024 -#define UART_UARTIBRD_BITS 0x0000ffff -#define UART_UARTIBRD_RESET 0x00000000 +#define UART_UARTIBRD_OFFSET _u(0x00000024) +#define UART_UARTIBRD_BITS _u(0x0000ffff) +#define UART_UARTIBRD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTIBRD_BAUD_DIVINT // Description : The integer baud rate divisor. These bits are cleared to 0 on // reset. -#define UART_UARTIBRD_BAUD_DIVINT_RESET 0x0000 -#define UART_UARTIBRD_BAUD_DIVINT_BITS 0x0000ffff -#define UART_UARTIBRD_BAUD_DIVINT_MSB 15 -#define UART_UARTIBRD_BAUD_DIVINT_LSB 0 +#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) +#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) +#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) +#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) #define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" // ============================================================================= // Register : UART_UARTFBRD // Description : Fractional Baud Rate Register, UARTFBRD -#define UART_UARTFBRD_OFFSET 0x00000028 -#define UART_UARTFBRD_BITS 0x0000003f -#define UART_UARTFBRD_RESET 0x00000000 +#define UART_UARTFBRD_OFFSET _u(0x00000028) +#define UART_UARTFBRD_BITS _u(0x0000003f) +#define UART_UARTFBRD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTFBRD_BAUD_DIVFRAC // Description : The fractional baud rate divisor. These bits are cleared to 0 // on reset. -#define UART_UARTFBRD_BAUD_DIVFRAC_RESET 0x00 -#define UART_UARTFBRD_BAUD_DIVFRAC_BITS 0x0000003f -#define UART_UARTFBRD_BAUD_DIVFRAC_MSB 5 -#define UART_UARTFBRD_BAUD_DIVFRAC_LSB 0 +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) #define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" // ============================================================================= // Register : UART_UARTLCR_H // Description : Line Control Register, UARTLCR_H -#define UART_UARTLCR_H_OFFSET 0x0000002c -#define UART_UARTLCR_H_BITS 0x000000ff -#define UART_UARTLCR_H_RESET 0x00000000 +#define UART_UARTLCR_H_OFFSET _u(0x0000002c) +#define UART_UARTLCR_H_BITS _u(0x000000ff) +#define UART_UARTLCR_H_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_SPS // Description : Stick parity select. 0 = stick parity is disabled 1 = either: * @@ -300,40 +300,40 @@ // checked as a 1 * if the EPS bit is 1 then the parity bit is // transmitted and checked as a 0. This bit has no effect when the // PEN bit disables parity checking and generation. -#define UART_UARTLCR_H_SPS_RESET 0x0 -#define UART_UARTLCR_H_SPS_BITS 0x00000080 -#define UART_UARTLCR_H_SPS_MSB 7 -#define UART_UARTLCR_H_SPS_LSB 7 +#define UART_UARTLCR_H_SPS_RESET _u(0x0) +#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) +#define UART_UARTLCR_H_SPS_MSB _u(7) +#define UART_UARTLCR_H_SPS_LSB _u(7) #define UART_UARTLCR_H_SPS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_WLEN // Description : Word length. These bits indicate the number of data bits // transmitted or received in a frame as follows: b11 = 8 bits b10 // = 7 bits b01 = 6 bits b00 = 5 bits. -#define UART_UARTLCR_H_WLEN_RESET 0x0 -#define UART_UARTLCR_H_WLEN_BITS 0x00000060 -#define UART_UARTLCR_H_WLEN_MSB 6 -#define UART_UARTLCR_H_WLEN_LSB 5 +#define UART_UARTLCR_H_WLEN_RESET _u(0x0) +#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) +#define UART_UARTLCR_H_WLEN_MSB _u(6) +#define UART_UARTLCR_H_WLEN_LSB _u(5) #define UART_UARTLCR_H_WLEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_FEN // Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, // the FIFOs become 1-byte-deep holding registers 1 = transmit and // receive FIFO buffers are enabled (FIFO mode). -#define UART_UARTLCR_H_FEN_RESET 0x0 -#define UART_UARTLCR_H_FEN_BITS 0x00000010 -#define UART_UARTLCR_H_FEN_MSB 4 -#define UART_UARTLCR_H_FEN_LSB 4 +#define UART_UARTLCR_H_FEN_RESET _u(0x0) +#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) +#define UART_UARTLCR_H_FEN_MSB _u(4) +#define UART_UARTLCR_H_FEN_LSB _u(4) #define UART_UARTLCR_H_FEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_STP2 // Description : Two stop bits select. If this bit is set to 1, two stop bits // are transmitted at the end of the frame. The receive logic does // not check for two stop bits being received. -#define UART_UARTLCR_H_STP2_RESET 0x0 -#define UART_UARTLCR_H_STP2_BITS 0x00000008 -#define UART_UARTLCR_H_STP2_MSB 3 -#define UART_UARTLCR_H_STP2_LSB 3 +#define UART_UARTLCR_H_STP2_RESET _u(0x0) +#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) +#define UART_UARTLCR_H_STP2_MSB _u(3) +#define UART_UARTLCR_H_STP2_LSB _u(3) #define UART_UARTLCR_H_STP2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_EPS @@ -344,20 +344,20 @@ // an even number of 1s in the data and parity bits. This bit has // no effect when the PEN bit disables parity checking and // generation. -#define UART_UARTLCR_H_EPS_RESET 0x0 -#define UART_UARTLCR_H_EPS_BITS 0x00000004 -#define UART_UARTLCR_H_EPS_MSB 2 -#define UART_UARTLCR_H_EPS_LSB 2 +#define UART_UARTLCR_H_EPS_RESET _u(0x0) +#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) +#define UART_UARTLCR_H_EPS_MSB _u(2) +#define UART_UARTLCR_H_EPS_LSB _u(2) #define UART_UARTLCR_H_EPS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_PEN // Description : Parity enable: 0 = parity is disabled and no parity bit added // to the data frame 1 = parity checking and generation is // enabled. -#define UART_UARTLCR_H_PEN_RESET 0x0 -#define UART_UARTLCR_H_PEN_BITS 0x00000002 -#define UART_UARTLCR_H_PEN_MSB 1 -#define UART_UARTLCR_H_PEN_LSB 1 +#define UART_UARTLCR_H_PEN_RESET _u(0x0) +#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) +#define UART_UARTLCR_H_PEN_MSB _u(1) +#define UART_UARTLCR_H_PEN_LSB _u(1) #define UART_UARTLCR_H_PEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_BRK @@ -366,46 +366,46 @@ // the current character. For the proper execution of the break // command, the software must set this bit for at least two // complete frames. For normal use, this bit must be cleared to 0. -#define UART_UARTLCR_H_BRK_RESET 0x0 -#define UART_UARTLCR_H_BRK_BITS 0x00000001 -#define UART_UARTLCR_H_BRK_MSB 0 -#define UART_UARTLCR_H_BRK_LSB 0 +#define UART_UARTLCR_H_BRK_RESET _u(0x0) +#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) +#define UART_UARTLCR_H_BRK_MSB _u(0) +#define UART_UARTLCR_H_BRK_LSB _u(0) #define UART_UARTLCR_H_BRK_ACCESS "RW" // ============================================================================= // Register : UART_UARTCR // Description : Control Register, UARTCR -#define UART_UARTCR_OFFSET 0x00000030 -#define UART_UARTCR_BITS 0x0000ff87 -#define UART_UARTCR_RESET 0x00000300 +#define UART_UARTCR_OFFSET _u(0x00000030) +#define UART_UARTCR_BITS _u(0x0000ff87) +#define UART_UARTCR_RESET _u(0x00000300) // ----------------------------------------------------------------------------- // Field : UART_UARTCR_CTSEN // Description : CTS hardware flow control enable. If this bit is set to 1, CTS // hardware flow control is enabled. Data is only transmitted when // the nUARTCTS signal is asserted. -#define UART_UARTCR_CTSEN_RESET 0x0 -#define UART_UARTCR_CTSEN_BITS 0x00008000 -#define UART_UARTCR_CTSEN_MSB 15 -#define UART_UARTCR_CTSEN_LSB 15 +#define UART_UARTCR_CTSEN_RESET _u(0x0) +#define UART_UARTCR_CTSEN_BITS _u(0x00008000) +#define UART_UARTCR_CTSEN_MSB _u(15) +#define UART_UARTCR_CTSEN_LSB _u(15) #define UART_UARTCR_CTSEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RTSEN // Description : RTS hardware flow control enable. If this bit is set to 1, RTS // hardware flow control is enabled. Data is only requested when // there is space in the receive FIFO for it to be received. -#define UART_UARTCR_RTSEN_RESET 0x0 -#define UART_UARTCR_RTSEN_BITS 0x00004000 -#define UART_UARTCR_RTSEN_MSB 14 -#define UART_UARTCR_RTSEN_LSB 14 +#define UART_UARTCR_RTSEN_RESET _u(0x0) +#define UART_UARTCR_RTSEN_BITS _u(0x00004000) +#define UART_UARTCR_RTSEN_MSB _u(14) +#define UART_UARTCR_RTSEN_LSB _u(14) #define UART_UARTCR_RTSEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_OUT2 // Description : This bit is the complement of the UART Out2 (nUARTOut2) modem // status output. That is, when the bit is programmed to a 1, the // output is 0. For DTE this can be used as Ring Indicator (RI). -#define UART_UARTCR_OUT2_RESET 0x0 -#define UART_UARTCR_OUT2_BITS 0x00002000 -#define UART_UARTCR_OUT2_MSB 13 -#define UART_UARTCR_OUT2_LSB 13 +#define UART_UARTCR_OUT2_RESET _u(0x0) +#define UART_UARTCR_OUT2_BITS _u(0x00002000) +#define UART_UARTCR_OUT2_MSB _u(13) +#define UART_UARTCR_OUT2_LSB _u(13) #define UART_UARTCR_OUT2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_OUT1 @@ -413,30 +413,30 @@ // status output. That is, when the bit is programmed to a 1 the // output is 0. For DTE this can be used as Data Carrier Detect // (DCD). -#define UART_UARTCR_OUT1_RESET 0x0 -#define UART_UARTCR_OUT1_BITS 0x00001000 -#define UART_UARTCR_OUT1_MSB 12 -#define UART_UARTCR_OUT1_LSB 12 +#define UART_UARTCR_OUT1_RESET _u(0x0) +#define UART_UARTCR_OUT1_BITS _u(0x00001000) +#define UART_UARTCR_OUT1_MSB _u(12) +#define UART_UARTCR_OUT1_LSB _u(12) #define UART_UARTCR_OUT1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RTS // Description : Request to send. This bit is the complement of the UART request // to send, nUARTRTS, modem status output. That is, when the bit // is programmed to a 1 then nUARTRTS is LOW. -#define UART_UARTCR_RTS_RESET 0x0 -#define UART_UARTCR_RTS_BITS 0x00000800 -#define UART_UARTCR_RTS_MSB 11 -#define UART_UARTCR_RTS_LSB 11 +#define UART_UARTCR_RTS_RESET _u(0x0) +#define UART_UARTCR_RTS_BITS _u(0x00000800) +#define UART_UARTCR_RTS_MSB _u(11) +#define UART_UARTCR_RTS_LSB _u(11) #define UART_UARTCR_RTS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_DTR // Description : Data transmit ready. This bit is the complement of the UART // data transmit ready, nUARTDTR, modem status output. That is, // when the bit is programmed to a 1 then nUARTDTR is LOW. -#define UART_UARTCR_DTR_RESET 0x0 -#define UART_UARTCR_DTR_BITS 0x00000400 -#define UART_UARTCR_DTR_MSB 10 -#define UART_UARTCR_DTR_LSB 10 +#define UART_UARTCR_DTR_RESET _u(0x0) +#define UART_UARTCR_DTR_BITS _u(0x00000400) +#define UART_UARTCR_DTR_MSB _u(10) +#define UART_UARTCR_DTR_LSB _u(10) #define UART_UARTCR_DTR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RXE @@ -445,10 +445,10 @@ // signals or SIR signals depending on the setting of the SIREN // bit. When the UART is disabled in the middle of reception, it // completes the current character before stopping. -#define UART_UARTCR_RXE_RESET 0x1 -#define UART_UARTCR_RXE_BITS 0x00000200 -#define UART_UARTCR_RXE_MSB 9 -#define UART_UARTCR_RXE_LSB 9 +#define UART_UARTCR_RXE_RESET _u(0x1) +#define UART_UARTCR_RXE_BITS _u(0x00000200) +#define UART_UARTCR_RXE_MSB _u(9) +#define UART_UARTCR_RXE_LSB _u(9) #define UART_UARTCR_RXE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_TXE @@ -458,10 +458,10 @@ // SIREN bit. When the UART is disabled in the middle of // transmission, it completes the current character before // stopping. -#define UART_UARTCR_TXE_RESET 0x1 -#define UART_UARTCR_TXE_BITS 0x00000100 -#define UART_UARTCR_TXE_MSB 8 -#define UART_UARTCR_TXE_LSB 8 +#define UART_UARTCR_TXE_RESET _u(0x1) +#define UART_UARTCR_TXE_BITS _u(0x00000100) +#define UART_UARTCR_TXE_MSB _u(8) +#define UART_UARTCR_TXE_LSB _u(8) #define UART_UARTCR_TXE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_LBE @@ -479,10 +479,10 @@ // mode or UART mode, when this bit is set, the modem outputs are // also fed through to the modem inputs. This bit is cleared to 0 // on reset, to disable loopback. -#define UART_UARTCR_LBE_RESET 0x0 -#define UART_UARTCR_LBE_BITS 0x00000080 -#define UART_UARTCR_LBE_MSB 7 -#define UART_UARTCR_LBE_LSB 7 +#define UART_UARTCR_LBE_RESET _u(0x0) +#define UART_UARTCR_LBE_BITS _u(0x00000080) +#define UART_UARTCR_LBE_MSB _u(7) +#define UART_UARTCR_LBE_LSB _u(7) #define UART_UARTCR_LBE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_SIRLP @@ -494,10 +494,10 @@ // the IrLPBaud16 input signal, regardless of the selected bit // rate. Setting this bit uses less power, but might reduce // transmission distances. -#define UART_UARTCR_SIRLP_RESET 0x0 -#define UART_UARTCR_SIRLP_BITS 0x00000004 -#define UART_UARTCR_SIRLP_MSB 2 -#define UART_UARTCR_SIRLP_LSB 2 +#define UART_UARTCR_SIRLP_RESET _u(0x0) +#define UART_UARTCR_SIRLP_BITS _u(0x00000004) +#define UART_UARTCR_SIRLP_MSB _u(2) +#define UART_UARTCR_SIRLP_LSB _u(2) #define UART_UARTCR_SIRLP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_SIREN @@ -508,10 +508,10 @@ // HIGH, in the marking state. Signal transitions on UARTRXD or // modem status inputs have no effect. This bit has no effect if // the UARTEN bit disables the UART. -#define UART_UARTCR_SIREN_RESET 0x0 -#define UART_UARTCR_SIREN_BITS 0x00000002 -#define UART_UARTCR_SIREN_MSB 1 -#define UART_UARTCR_SIREN_LSB 1 +#define UART_UARTCR_SIREN_RESET _u(0x0) +#define UART_UARTCR_SIREN_BITS _u(0x00000002) +#define UART_UARTCR_SIREN_MSB _u(1) +#define UART_UARTCR_SIREN_LSB _u(1) #define UART_UARTCR_SIREN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_UARTEN @@ -520,17 +520,17 @@ // current character before stopping. 1 = the UART is enabled. // Data transmission and reception occurs for either UART signals // or SIR signals depending on the setting of the SIREN bit. -#define UART_UARTCR_UARTEN_RESET 0x0 -#define UART_UARTCR_UARTEN_BITS 0x00000001 -#define UART_UARTCR_UARTEN_MSB 0 -#define UART_UARTCR_UARTEN_LSB 0 +#define UART_UARTCR_UARTEN_RESET _u(0x0) +#define UART_UARTCR_UARTEN_BITS _u(0x00000001) +#define UART_UARTCR_UARTEN_MSB _u(0) +#define UART_UARTCR_UARTEN_LSB _u(0) #define UART_UARTCR_UARTEN_ACCESS "RW" // ============================================================================= // Register : UART_UARTIFLS // Description : Interrupt FIFO Level Select Register, UARTIFLS -#define UART_UARTIFLS_OFFSET 0x00000034 -#define UART_UARTIFLS_BITS 0x0000003f -#define UART_UARTIFLS_RESET 0x00000012 +#define UART_UARTIFLS_OFFSET _u(0x00000034) +#define UART_UARTIFLS_BITS _u(0x0000003f) +#define UART_UARTIFLS_RESET _u(0x00000012) // ----------------------------------------------------------------------------- // Field : UART_UARTIFLS_RXIFLSEL // Description : Receive interrupt FIFO level select. The trigger points for the @@ -539,10 +539,10 @@ // Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes // >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full // b101-b111 = reserved. -#define UART_UARTIFLS_RXIFLSEL_RESET 0x2 -#define UART_UARTIFLS_RXIFLSEL_BITS 0x00000038 -#define UART_UARTIFLS_RXIFLSEL_MSB 5 -#define UART_UARTIFLS_RXIFLSEL_LSB 3 +#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) +#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) +#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) #define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIFLS_TXIFLSEL @@ -552,597 +552,597 @@ // full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit // FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / // 8 full b101-b111 = reserved. -#define UART_UARTIFLS_TXIFLSEL_RESET 0x2 -#define UART_UARTIFLS_TXIFLSEL_BITS 0x00000007 -#define UART_UARTIFLS_TXIFLSEL_MSB 2 -#define UART_UARTIFLS_TXIFLSEL_LSB 0 +#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) +#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) +#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) #define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" // ============================================================================= // Register : UART_UARTIMSC // Description : Interrupt Mask Set/Clear Register, UARTIMSC -#define UART_UARTIMSC_OFFSET 0x00000038 -#define UART_UARTIMSC_BITS 0x000007ff -#define UART_UARTIMSC_RESET 0x00000000 +#define UART_UARTIMSC_OFFSET _u(0x00000038) +#define UART_UARTIMSC_BITS _u(0x000007ff) +#define UART_UARTIMSC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_OEIM // Description : Overrun error interrupt mask. A read returns the current mask // for the UARTOEINTR interrupt. On a write of 1, the mask of the // UARTOEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_OEIM_RESET 0x0 -#define UART_UARTIMSC_OEIM_BITS 0x00000400 -#define UART_UARTIMSC_OEIM_MSB 10 -#define UART_UARTIMSC_OEIM_LSB 10 +#define UART_UARTIMSC_OEIM_RESET _u(0x0) +#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) +#define UART_UARTIMSC_OEIM_MSB _u(10) +#define UART_UARTIMSC_OEIM_LSB _u(10) #define UART_UARTIMSC_OEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_BEIM // Description : Break error interrupt mask. A read returns the current mask for // the UARTBEINTR interrupt. On a write of 1, the mask of the // UARTBEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_BEIM_RESET 0x0 -#define UART_UARTIMSC_BEIM_BITS 0x00000200 -#define UART_UARTIMSC_BEIM_MSB 9 -#define UART_UARTIMSC_BEIM_LSB 9 +#define UART_UARTIMSC_BEIM_RESET _u(0x0) +#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) +#define UART_UARTIMSC_BEIM_MSB _u(9) +#define UART_UARTIMSC_BEIM_LSB _u(9) #define UART_UARTIMSC_BEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_PEIM // Description : Parity error interrupt mask. A read returns the current mask // for the UARTPEINTR interrupt. On a write of 1, the mask of the // UARTPEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_PEIM_RESET 0x0 -#define UART_UARTIMSC_PEIM_BITS 0x00000100 -#define UART_UARTIMSC_PEIM_MSB 8 -#define UART_UARTIMSC_PEIM_LSB 8 +#define UART_UARTIMSC_PEIM_RESET _u(0x0) +#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) +#define UART_UARTIMSC_PEIM_MSB _u(8) +#define UART_UARTIMSC_PEIM_LSB _u(8) #define UART_UARTIMSC_PEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_FEIM // Description : Framing error interrupt mask. A read returns the current mask // for the UARTFEINTR interrupt. On a write of 1, the mask of the // UARTFEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_FEIM_RESET 0x0 -#define UART_UARTIMSC_FEIM_BITS 0x00000080 -#define UART_UARTIMSC_FEIM_MSB 7 -#define UART_UARTIMSC_FEIM_LSB 7 +#define UART_UARTIMSC_FEIM_RESET _u(0x0) +#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) +#define UART_UARTIMSC_FEIM_MSB _u(7) +#define UART_UARTIMSC_FEIM_LSB _u(7) #define UART_UARTIMSC_FEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RTIM // Description : Receive timeout interrupt mask. A read returns the current mask // for the UARTRTINTR interrupt. On a write of 1, the mask of the // UARTRTINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RTIM_RESET 0x0 -#define UART_UARTIMSC_RTIM_BITS 0x00000040 -#define UART_UARTIMSC_RTIM_MSB 6 -#define UART_UARTIMSC_RTIM_LSB 6 +#define UART_UARTIMSC_RTIM_RESET _u(0x0) +#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) +#define UART_UARTIMSC_RTIM_MSB _u(6) +#define UART_UARTIMSC_RTIM_LSB _u(6) #define UART_UARTIMSC_RTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_TXIM // Description : Transmit interrupt mask. A read returns the current mask for // the UARTTXINTR interrupt. On a write of 1, the mask of the // UARTTXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_TXIM_RESET 0x0 -#define UART_UARTIMSC_TXIM_BITS 0x00000020 -#define UART_UARTIMSC_TXIM_MSB 5 -#define UART_UARTIMSC_TXIM_LSB 5 +#define UART_UARTIMSC_TXIM_RESET _u(0x0) +#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) +#define UART_UARTIMSC_TXIM_MSB _u(5) +#define UART_UARTIMSC_TXIM_LSB _u(5) #define UART_UARTIMSC_TXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RXIM // Description : Receive interrupt mask. A read returns the current mask for the // UARTRXINTR interrupt. On a write of 1, the mask of the // UARTRXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RXIM_RESET 0x0 -#define UART_UARTIMSC_RXIM_BITS 0x00000010 -#define UART_UARTIMSC_RXIM_MSB 4 -#define UART_UARTIMSC_RXIM_LSB 4 +#define UART_UARTIMSC_RXIM_RESET _u(0x0) +#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) +#define UART_UARTIMSC_RXIM_MSB _u(4) +#define UART_UARTIMSC_RXIM_LSB _u(4) #define UART_UARTIMSC_RXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_DSRMIM // Description : nUARTDSR modem interrupt mask. A read returns the current mask // for the UARTDSRINTR interrupt. On a write of 1, the mask of the // UARTDSRINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DSRMIM_RESET 0x0 -#define UART_UARTIMSC_DSRMIM_BITS 0x00000008 -#define UART_UARTIMSC_DSRMIM_MSB 3 -#define UART_UARTIMSC_DSRMIM_LSB 3 +#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) +#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) +#define UART_UARTIMSC_DSRMIM_MSB _u(3) +#define UART_UARTIMSC_DSRMIM_LSB _u(3) #define UART_UARTIMSC_DSRMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_DCDMIM // Description : nUARTDCD modem interrupt mask. A read returns the current mask // for the UARTDCDINTR interrupt. On a write of 1, the mask of the // UARTDCDINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DCDMIM_RESET 0x0 -#define UART_UARTIMSC_DCDMIM_BITS 0x00000004 -#define UART_UARTIMSC_DCDMIM_MSB 2 -#define UART_UARTIMSC_DCDMIM_LSB 2 +#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) +#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) +#define UART_UARTIMSC_DCDMIM_MSB _u(2) +#define UART_UARTIMSC_DCDMIM_LSB _u(2) #define UART_UARTIMSC_DCDMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_CTSMIM // Description : nUARTCTS modem interrupt mask. A read returns the current mask // for the UARTCTSINTR interrupt. On a write of 1, the mask of the // UARTCTSINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_CTSMIM_RESET 0x0 -#define UART_UARTIMSC_CTSMIM_BITS 0x00000002 -#define UART_UARTIMSC_CTSMIM_MSB 1 -#define UART_UARTIMSC_CTSMIM_LSB 1 +#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) +#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) +#define UART_UARTIMSC_CTSMIM_MSB _u(1) +#define UART_UARTIMSC_CTSMIM_LSB _u(1) #define UART_UARTIMSC_CTSMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RIMIM // Description : nUARTRI modem interrupt mask. A read returns the current mask // for the UARTRIINTR interrupt. On a write of 1, the mask of the // UARTRIINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RIMIM_RESET 0x0 -#define UART_UARTIMSC_RIMIM_BITS 0x00000001 -#define UART_UARTIMSC_RIMIM_MSB 0 -#define UART_UARTIMSC_RIMIM_LSB 0 +#define UART_UARTIMSC_RIMIM_RESET _u(0x0) +#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) +#define UART_UARTIMSC_RIMIM_MSB _u(0) +#define UART_UARTIMSC_RIMIM_LSB _u(0) #define UART_UARTIMSC_RIMIM_ACCESS "RW" // ============================================================================= // Register : UART_UARTRIS // Description : Raw Interrupt Status Register, UARTRIS -#define UART_UARTRIS_OFFSET 0x0000003c -#define UART_UARTRIS_BITS 0x000007ff -#define UART_UARTRIS_RESET 0x00000000 +#define UART_UARTRIS_OFFSET _u(0x0000003c) +#define UART_UARTRIS_BITS _u(0x000007ff) +#define UART_UARTRIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_OERIS // Description : Overrun error interrupt status. Returns the raw interrupt state // of the UARTOEINTR interrupt. -#define UART_UARTRIS_OERIS_RESET 0x0 -#define UART_UARTRIS_OERIS_BITS 0x00000400 -#define UART_UARTRIS_OERIS_MSB 10 -#define UART_UARTRIS_OERIS_LSB 10 +#define UART_UARTRIS_OERIS_RESET _u(0x0) +#define UART_UARTRIS_OERIS_BITS _u(0x00000400) +#define UART_UARTRIS_OERIS_MSB _u(10) +#define UART_UARTRIS_OERIS_LSB _u(10) #define UART_UARTRIS_OERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_BERIS // Description : Break error interrupt status. Returns the raw interrupt state // of the UARTBEINTR interrupt. -#define UART_UARTRIS_BERIS_RESET 0x0 -#define UART_UARTRIS_BERIS_BITS 0x00000200 -#define UART_UARTRIS_BERIS_MSB 9 -#define UART_UARTRIS_BERIS_LSB 9 +#define UART_UARTRIS_BERIS_RESET _u(0x0) +#define UART_UARTRIS_BERIS_BITS _u(0x00000200) +#define UART_UARTRIS_BERIS_MSB _u(9) +#define UART_UARTRIS_BERIS_LSB _u(9) #define UART_UARTRIS_BERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_PERIS // Description : Parity error interrupt status. Returns the raw interrupt state // of the UARTPEINTR interrupt. -#define UART_UARTRIS_PERIS_RESET 0x0 -#define UART_UARTRIS_PERIS_BITS 0x00000100 -#define UART_UARTRIS_PERIS_MSB 8 -#define UART_UARTRIS_PERIS_LSB 8 +#define UART_UARTRIS_PERIS_RESET _u(0x0) +#define UART_UARTRIS_PERIS_BITS _u(0x00000100) +#define UART_UARTRIS_PERIS_MSB _u(8) +#define UART_UARTRIS_PERIS_LSB _u(8) #define UART_UARTRIS_PERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_FERIS // Description : Framing error interrupt status. Returns the raw interrupt state // of the UARTFEINTR interrupt. -#define UART_UARTRIS_FERIS_RESET 0x0 -#define UART_UARTRIS_FERIS_BITS 0x00000080 -#define UART_UARTRIS_FERIS_MSB 7 -#define UART_UARTRIS_FERIS_LSB 7 +#define UART_UARTRIS_FERIS_RESET _u(0x0) +#define UART_UARTRIS_FERIS_BITS _u(0x00000080) +#define UART_UARTRIS_FERIS_MSB _u(7) +#define UART_UARTRIS_FERIS_LSB _u(7) #define UART_UARTRIS_FERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RTRIS // Description : Receive timeout interrupt status. Returns the raw interrupt // state of the UARTRTINTR interrupt. a -#define UART_UARTRIS_RTRIS_RESET 0x0 -#define UART_UARTRIS_RTRIS_BITS 0x00000040 -#define UART_UARTRIS_RTRIS_MSB 6 -#define UART_UARTRIS_RTRIS_LSB 6 +#define UART_UARTRIS_RTRIS_RESET _u(0x0) +#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) +#define UART_UARTRIS_RTRIS_MSB _u(6) +#define UART_UARTRIS_RTRIS_LSB _u(6) #define UART_UARTRIS_RTRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_TXRIS // Description : Transmit interrupt status. Returns the raw interrupt state of // the UARTTXINTR interrupt. -#define UART_UARTRIS_TXRIS_RESET 0x0 -#define UART_UARTRIS_TXRIS_BITS 0x00000020 -#define UART_UARTRIS_TXRIS_MSB 5 -#define UART_UARTRIS_TXRIS_LSB 5 +#define UART_UARTRIS_TXRIS_RESET _u(0x0) +#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) +#define UART_UARTRIS_TXRIS_MSB _u(5) +#define UART_UARTRIS_TXRIS_LSB _u(5) #define UART_UARTRIS_TXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RXRIS // Description : Receive interrupt status. Returns the raw interrupt state of // the UARTRXINTR interrupt. -#define UART_UARTRIS_RXRIS_RESET 0x0 -#define UART_UARTRIS_RXRIS_BITS 0x00000010 -#define UART_UARTRIS_RXRIS_MSB 4 -#define UART_UARTRIS_RXRIS_LSB 4 +#define UART_UARTRIS_RXRIS_RESET _u(0x0) +#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) +#define UART_UARTRIS_RXRIS_MSB _u(4) +#define UART_UARTRIS_RXRIS_LSB _u(4) #define UART_UARTRIS_RXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_DSRRMIS // Description : nUARTDSR modem interrupt status. Returns the raw interrupt // state of the UARTDSRINTR interrupt. #define UART_UARTRIS_DSRRMIS_RESET "-" -#define UART_UARTRIS_DSRRMIS_BITS 0x00000008 -#define UART_UARTRIS_DSRRMIS_MSB 3 -#define UART_UARTRIS_DSRRMIS_LSB 3 +#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) +#define UART_UARTRIS_DSRRMIS_MSB _u(3) +#define UART_UARTRIS_DSRRMIS_LSB _u(3) #define UART_UARTRIS_DSRRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_DCDRMIS // Description : nUARTDCD modem interrupt status. Returns the raw interrupt // state of the UARTDCDINTR interrupt. #define UART_UARTRIS_DCDRMIS_RESET "-" -#define UART_UARTRIS_DCDRMIS_BITS 0x00000004 -#define UART_UARTRIS_DCDRMIS_MSB 2 -#define UART_UARTRIS_DCDRMIS_LSB 2 +#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) +#define UART_UARTRIS_DCDRMIS_MSB _u(2) +#define UART_UARTRIS_DCDRMIS_LSB _u(2) #define UART_UARTRIS_DCDRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_CTSRMIS // Description : nUARTCTS modem interrupt status. Returns the raw interrupt // state of the UARTCTSINTR interrupt. #define UART_UARTRIS_CTSRMIS_RESET "-" -#define UART_UARTRIS_CTSRMIS_BITS 0x00000002 -#define UART_UARTRIS_CTSRMIS_MSB 1 -#define UART_UARTRIS_CTSRMIS_LSB 1 +#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) +#define UART_UARTRIS_CTSRMIS_MSB _u(1) +#define UART_UARTRIS_CTSRMIS_LSB _u(1) #define UART_UARTRIS_CTSRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RIRMIS // Description : nUARTRI modem interrupt status. Returns the raw interrupt state // of the UARTRIINTR interrupt. #define UART_UARTRIS_RIRMIS_RESET "-" -#define UART_UARTRIS_RIRMIS_BITS 0x00000001 -#define UART_UARTRIS_RIRMIS_MSB 0 -#define UART_UARTRIS_RIRMIS_LSB 0 +#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) +#define UART_UARTRIS_RIRMIS_MSB _u(0) +#define UART_UARTRIS_RIRMIS_LSB _u(0) #define UART_UARTRIS_RIRMIS_ACCESS "RO" // ============================================================================= // Register : UART_UARTMIS // Description : Masked Interrupt Status Register, UARTMIS -#define UART_UARTMIS_OFFSET 0x00000040 -#define UART_UARTMIS_BITS 0x000007ff -#define UART_UARTMIS_RESET 0x00000000 +#define UART_UARTMIS_OFFSET _u(0x00000040) +#define UART_UARTMIS_BITS _u(0x000007ff) +#define UART_UARTMIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_OEMIS // Description : Overrun error masked interrupt status. Returns the masked // interrupt state of the UARTOEINTR interrupt. -#define UART_UARTMIS_OEMIS_RESET 0x0 -#define UART_UARTMIS_OEMIS_BITS 0x00000400 -#define UART_UARTMIS_OEMIS_MSB 10 -#define UART_UARTMIS_OEMIS_LSB 10 +#define UART_UARTMIS_OEMIS_RESET _u(0x0) +#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) +#define UART_UARTMIS_OEMIS_MSB _u(10) +#define UART_UARTMIS_OEMIS_LSB _u(10) #define UART_UARTMIS_OEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_BEMIS // Description : Break error masked interrupt status. Returns the masked // interrupt state of the UARTBEINTR interrupt. -#define UART_UARTMIS_BEMIS_RESET 0x0 -#define UART_UARTMIS_BEMIS_BITS 0x00000200 -#define UART_UARTMIS_BEMIS_MSB 9 -#define UART_UARTMIS_BEMIS_LSB 9 +#define UART_UARTMIS_BEMIS_RESET _u(0x0) +#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) +#define UART_UARTMIS_BEMIS_MSB _u(9) +#define UART_UARTMIS_BEMIS_LSB _u(9) #define UART_UARTMIS_BEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_PEMIS // Description : Parity error masked interrupt status. Returns the masked // interrupt state of the UARTPEINTR interrupt. -#define UART_UARTMIS_PEMIS_RESET 0x0 -#define UART_UARTMIS_PEMIS_BITS 0x00000100 -#define UART_UARTMIS_PEMIS_MSB 8 -#define UART_UARTMIS_PEMIS_LSB 8 +#define UART_UARTMIS_PEMIS_RESET _u(0x0) +#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) +#define UART_UARTMIS_PEMIS_MSB _u(8) +#define UART_UARTMIS_PEMIS_LSB _u(8) #define UART_UARTMIS_PEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_FEMIS // Description : Framing error masked interrupt status. Returns the masked // interrupt state of the UARTFEINTR interrupt. -#define UART_UARTMIS_FEMIS_RESET 0x0 -#define UART_UARTMIS_FEMIS_BITS 0x00000080 -#define UART_UARTMIS_FEMIS_MSB 7 -#define UART_UARTMIS_FEMIS_LSB 7 +#define UART_UARTMIS_FEMIS_RESET _u(0x0) +#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) +#define UART_UARTMIS_FEMIS_MSB _u(7) +#define UART_UARTMIS_FEMIS_LSB _u(7) #define UART_UARTMIS_FEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RTMIS // Description : Receive timeout masked interrupt status. Returns the masked // interrupt state of the UARTRTINTR interrupt. -#define UART_UARTMIS_RTMIS_RESET 0x0 -#define UART_UARTMIS_RTMIS_BITS 0x00000040 -#define UART_UARTMIS_RTMIS_MSB 6 -#define UART_UARTMIS_RTMIS_LSB 6 +#define UART_UARTMIS_RTMIS_RESET _u(0x0) +#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) +#define UART_UARTMIS_RTMIS_MSB _u(6) +#define UART_UARTMIS_RTMIS_LSB _u(6) #define UART_UARTMIS_RTMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_TXMIS // Description : Transmit masked interrupt status. Returns the masked interrupt // state of the UARTTXINTR interrupt. -#define UART_UARTMIS_TXMIS_RESET 0x0 -#define UART_UARTMIS_TXMIS_BITS 0x00000020 -#define UART_UARTMIS_TXMIS_MSB 5 -#define UART_UARTMIS_TXMIS_LSB 5 +#define UART_UARTMIS_TXMIS_RESET _u(0x0) +#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) +#define UART_UARTMIS_TXMIS_MSB _u(5) +#define UART_UARTMIS_TXMIS_LSB _u(5) #define UART_UARTMIS_TXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RXMIS // Description : Receive masked interrupt status. Returns the masked interrupt // state of the UARTRXINTR interrupt. -#define UART_UARTMIS_RXMIS_RESET 0x0 -#define UART_UARTMIS_RXMIS_BITS 0x00000010 -#define UART_UARTMIS_RXMIS_MSB 4 -#define UART_UARTMIS_RXMIS_LSB 4 +#define UART_UARTMIS_RXMIS_RESET _u(0x0) +#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) +#define UART_UARTMIS_RXMIS_MSB _u(4) +#define UART_UARTMIS_RXMIS_LSB _u(4) #define UART_UARTMIS_RXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_DSRMMIS // Description : nUARTDSR modem masked interrupt status. Returns the masked // interrupt state of the UARTDSRINTR interrupt. #define UART_UARTMIS_DSRMMIS_RESET "-" -#define UART_UARTMIS_DSRMMIS_BITS 0x00000008 -#define UART_UARTMIS_DSRMMIS_MSB 3 -#define UART_UARTMIS_DSRMMIS_LSB 3 +#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) +#define UART_UARTMIS_DSRMMIS_MSB _u(3) +#define UART_UARTMIS_DSRMMIS_LSB _u(3) #define UART_UARTMIS_DSRMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_DCDMMIS // Description : nUARTDCD modem masked interrupt status. Returns the masked // interrupt state of the UARTDCDINTR interrupt. #define UART_UARTMIS_DCDMMIS_RESET "-" -#define UART_UARTMIS_DCDMMIS_BITS 0x00000004 -#define UART_UARTMIS_DCDMMIS_MSB 2 -#define UART_UARTMIS_DCDMMIS_LSB 2 +#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) +#define UART_UARTMIS_DCDMMIS_MSB _u(2) +#define UART_UARTMIS_DCDMMIS_LSB _u(2) #define UART_UARTMIS_DCDMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_CTSMMIS // Description : nUARTCTS modem masked interrupt status. Returns the masked // interrupt state of the UARTCTSINTR interrupt. #define UART_UARTMIS_CTSMMIS_RESET "-" -#define UART_UARTMIS_CTSMMIS_BITS 0x00000002 -#define UART_UARTMIS_CTSMMIS_MSB 1 -#define UART_UARTMIS_CTSMMIS_LSB 1 +#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) +#define UART_UARTMIS_CTSMMIS_MSB _u(1) +#define UART_UARTMIS_CTSMMIS_LSB _u(1) #define UART_UARTMIS_CTSMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RIMMIS // Description : nUARTRI modem masked interrupt status. Returns the masked // interrupt state of the UARTRIINTR interrupt. #define UART_UARTMIS_RIMMIS_RESET "-" -#define UART_UARTMIS_RIMMIS_BITS 0x00000001 -#define UART_UARTMIS_RIMMIS_MSB 0 -#define UART_UARTMIS_RIMMIS_LSB 0 +#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) +#define UART_UARTMIS_RIMMIS_MSB _u(0) +#define UART_UARTMIS_RIMMIS_LSB _u(0) #define UART_UARTMIS_RIMMIS_ACCESS "RO" // ============================================================================= // Register : UART_UARTICR // Description : Interrupt Clear Register, UARTICR -#define UART_UARTICR_OFFSET 0x00000044 -#define UART_UARTICR_BITS 0x000007ff -#define UART_UARTICR_RESET 0x00000000 +#define UART_UARTICR_OFFSET _u(0x00000044) +#define UART_UARTICR_BITS _u(0x000007ff) +#define UART_UARTICR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTICR_OEIC // Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. #define UART_UARTICR_OEIC_RESET "-" -#define UART_UARTICR_OEIC_BITS 0x00000400 -#define UART_UARTICR_OEIC_MSB 10 -#define UART_UARTICR_OEIC_LSB 10 +#define UART_UARTICR_OEIC_BITS _u(0x00000400) +#define UART_UARTICR_OEIC_MSB _u(10) +#define UART_UARTICR_OEIC_LSB _u(10) #define UART_UARTICR_OEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_BEIC // Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. #define UART_UARTICR_BEIC_RESET "-" -#define UART_UARTICR_BEIC_BITS 0x00000200 -#define UART_UARTICR_BEIC_MSB 9 -#define UART_UARTICR_BEIC_LSB 9 +#define UART_UARTICR_BEIC_BITS _u(0x00000200) +#define UART_UARTICR_BEIC_MSB _u(9) +#define UART_UARTICR_BEIC_LSB _u(9) #define UART_UARTICR_BEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_PEIC // Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. #define UART_UARTICR_PEIC_RESET "-" -#define UART_UARTICR_PEIC_BITS 0x00000100 -#define UART_UARTICR_PEIC_MSB 8 -#define UART_UARTICR_PEIC_LSB 8 +#define UART_UARTICR_PEIC_BITS _u(0x00000100) +#define UART_UARTICR_PEIC_MSB _u(8) +#define UART_UARTICR_PEIC_LSB _u(8) #define UART_UARTICR_PEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_FEIC // Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. #define UART_UARTICR_FEIC_RESET "-" -#define UART_UARTICR_FEIC_BITS 0x00000080 -#define UART_UARTICR_FEIC_MSB 7 -#define UART_UARTICR_FEIC_LSB 7 +#define UART_UARTICR_FEIC_BITS _u(0x00000080) +#define UART_UARTICR_FEIC_MSB _u(7) +#define UART_UARTICR_FEIC_LSB _u(7) #define UART_UARTICR_FEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RTIC // Description : Receive timeout interrupt clear. Clears the UARTRTINTR // interrupt. #define UART_UARTICR_RTIC_RESET "-" -#define UART_UARTICR_RTIC_BITS 0x00000040 -#define UART_UARTICR_RTIC_MSB 6 -#define UART_UARTICR_RTIC_LSB 6 +#define UART_UARTICR_RTIC_BITS _u(0x00000040) +#define UART_UARTICR_RTIC_MSB _u(6) +#define UART_UARTICR_RTIC_LSB _u(6) #define UART_UARTICR_RTIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_TXIC // Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. #define UART_UARTICR_TXIC_RESET "-" -#define UART_UARTICR_TXIC_BITS 0x00000020 -#define UART_UARTICR_TXIC_MSB 5 -#define UART_UARTICR_TXIC_LSB 5 +#define UART_UARTICR_TXIC_BITS _u(0x00000020) +#define UART_UARTICR_TXIC_MSB _u(5) +#define UART_UARTICR_TXIC_LSB _u(5) #define UART_UARTICR_TXIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RXIC // Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. #define UART_UARTICR_RXIC_RESET "-" -#define UART_UARTICR_RXIC_BITS 0x00000010 -#define UART_UARTICR_RXIC_MSB 4 -#define UART_UARTICR_RXIC_LSB 4 +#define UART_UARTICR_RXIC_BITS _u(0x00000010) +#define UART_UARTICR_RXIC_MSB _u(4) +#define UART_UARTICR_RXIC_LSB _u(4) #define UART_UARTICR_RXIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_DSRMIC // Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR // interrupt. #define UART_UARTICR_DSRMIC_RESET "-" -#define UART_UARTICR_DSRMIC_BITS 0x00000008 -#define UART_UARTICR_DSRMIC_MSB 3 -#define UART_UARTICR_DSRMIC_LSB 3 +#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) +#define UART_UARTICR_DSRMIC_MSB _u(3) +#define UART_UARTICR_DSRMIC_LSB _u(3) #define UART_UARTICR_DSRMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_DCDMIC // Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR // interrupt. #define UART_UARTICR_DCDMIC_RESET "-" -#define UART_UARTICR_DCDMIC_BITS 0x00000004 -#define UART_UARTICR_DCDMIC_MSB 2 -#define UART_UARTICR_DCDMIC_LSB 2 +#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) +#define UART_UARTICR_DCDMIC_MSB _u(2) +#define UART_UARTICR_DCDMIC_LSB _u(2) #define UART_UARTICR_DCDMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_CTSMIC // Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR // interrupt. #define UART_UARTICR_CTSMIC_RESET "-" -#define UART_UARTICR_CTSMIC_BITS 0x00000002 -#define UART_UARTICR_CTSMIC_MSB 1 -#define UART_UARTICR_CTSMIC_LSB 1 +#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) +#define UART_UARTICR_CTSMIC_MSB _u(1) +#define UART_UARTICR_CTSMIC_LSB _u(1) #define UART_UARTICR_CTSMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RIMIC // Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. #define UART_UARTICR_RIMIC_RESET "-" -#define UART_UARTICR_RIMIC_BITS 0x00000001 -#define UART_UARTICR_RIMIC_MSB 0 -#define UART_UARTICR_RIMIC_LSB 0 +#define UART_UARTICR_RIMIC_BITS _u(0x00000001) +#define UART_UARTICR_RIMIC_MSB _u(0) +#define UART_UARTICR_RIMIC_LSB _u(0) #define UART_UARTICR_RIMIC_ACCESS "WC" // ============================================================================= // Register : UART_UARTDMACR // Description : DMA Control Register, UARTDMACR -#define UART_UARTDMACR_OFFSET 0x00000048 -#define UART_UARTDMACR_BITS 0x00000007 -#define UART_UARTDMACR_RESET 0x00000000 +#define UART_UARTDMACR_OFFSET _u(0x00000048) +#define UART_UARTDMACR_BITS _u(0x00000007) +#define UART_UARTDMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_DMAONERR // Description : DMA on error. If this bit is set to 1, the DMA receive request // outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the // UART error interrupt is asserted. -#define UART_UARTDMACR_DMAONERR_RESET 0x0 -#define UART_UARTDMACR_DMAONERR_BITS 0x00000004 -#define UART_UARTDMACR_DMAONERR_MSB 2 -#define UART_UARTDMACR_DMAONERR_LSB 2 +#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) +#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) +#define UART_UARTDMACR_DMAONERR_MSB _u(2) +#define UART_UARTDMACR_DMAONERR_LSB _u(2) #define UART_UARTDMACR_DMAONERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_TXDMAE // Description : Transmit DMA enable. If this bit is set to 1, DMA for the // transmit FIFO is enabled. -#define UART_UARTDMACR_TXDMAE_RESET 0x0 -#define UART_UARTDMACR_TXDMAE_BITS 0x00000002 -#define UART_UARTDMACR_TXDMAE_MSB 1 -#define UART_UARTDMACR_TXDMAE_LSB 1 +#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) +#define UART_UARTDMACR_TXDMAE_MSB _u(1) +#define UART_UARTDMACR_TXDMAE_LSB _u(1) #define UART_UARTDMACR_TXDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_RXDMAE // Description : Receive DMA enable. If this bit is set to 1, DMA for the // receive FIFO is enabled. -#define UART_UARTDMACR_RXDMAE_RESET 0x0 -#define UART_UARTDMACR_RXDMAE_BITS 0x00000001 -#define UART_UARTDMACR_RXDMAE_MSB 0 -#define UART_UARTDMACR_RXDMAE_LSB 0 +#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) +#define UART_UARTDMACR_RXDMAE_MSB _u(0) +#define UART_UARTDMACR_RXDMAE_LSB _u(0) #define UART_UARTDMACR_RXDMAE_ACCESS "RW" // ============================================================================= // Register : UART_UARTPERIPHID0 // Description : UARTPeriphID0 Register -#define UART_UARTPERIPHID0_OFFSET 0x00000fe0 -#define UART_UARTPERIPHID0_BITS 0x000000ff -#define UART_UARTPERIPHID0_RESET 0x00000011 +#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) +#define UART_UARTPERIPHID0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_RESET _u(0x00000011) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID0_PARTNUMBER0 // Description : These bits read back as 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_RESET 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_BITS 0x000000ff -#define UART_UARTPERIPHID0_PARTNUMBER0_MSB 7 -#define UART_UARTPERIPHID0_PARTNUMBER0_LSB 0 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) #define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID1 // Description : UARTPeriphID1 Register -#define UART_UARTPERIPHID1_OFFSET 0x00000fe4 -#define UART_UARTPERIPHID1_BITS 0x000000ff -#define UART_UARTPERIPHID1_RESET 0x00000010 +#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) +#define UART_UARTPERIPHID1_BITS _u(0x000000ff) +#define UART_UARTPERIPHID1_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID1_DESIGNER0 // Description : These bits read back as 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_RESET 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_BITS 0x000000f0 -#define UART_UARTPERIPHID1_DESIGNER0_MSB 7 -#define UART_UARTPERIPHID1_DESIGNER0_LSB 4 +#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) +#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) +#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) #define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID1_PARTNUMBER1 // Description : These bits read back as 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_RESET 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_BITS 0x0000000f -#define UART_UARTPERIPHID1_PARTNUMBER1_MSB 3 -#define UART_UARTPERIPHID1_PARTNUMBER1_LSB 0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) #define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID2 // Description : UARTPeriphID2 Register -#define UART_UARTPERIPHID2_OFFSET 0x00000fe8 -#define UART_UARTPERIPHID2_BITS 0x000000ff -#define UART_UARTPERIPHID2_RESET 0x00000034 +#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) +#define UART_UARTPERIPHID2_BITS _u(0x000000ff) +#define UART_UARTPERIPHID2_RESET _u(0x00000034) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID2_REVISION // Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 // 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 -#define UART_UARTPERIPHID2_REVISION_RESET 0x3 -#define UART_UARTPERIPHID2_REVISION_BITS 0x000000f0 -#define UART_UARTPERIPHID2_REVISION_MSB 7 -#define UART_UARTPERIPHID2_REVISION_LSB 4 +#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) +#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) +#define UART_UARTPERIPHID2_REVISION_MSB _u(7) +#define UART_UARTPERIPHID2_REVISION_LSB _u(4) #define UART_UARTPERIPHID2_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID2_DESIGNER1 // Description : These bits read back as 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_RESET 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_BITS 0x0000000f -#define UART_UARTPERIPHID2_DESIGNER1_MSB 3 -#define UART_UARTPERIPHID2_DESIGNER1_LSB 0 +#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) +#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) +#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) #define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID3 // Description : UARTPeriphID3 Register -#define UART_UARTPERIPHID3_OFFSET 0x00000fec -#define UART_UARTPERIPHID3_BITS 0x000000ff -#define UART_UARTPERIPHID3_RESET 0x00000000 +#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) +#define UART_UARTPERIPHID3_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID3_CONFIGURATION // Description : These bits read back as 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_RESET 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_BITS 0x000000ff -#define UART_UARTPERIPHID3_CONFIGURATION_MSB 7 -#define UART_UARTPERIPHID3_CONFIGURATION_LSB 0 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) +#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) #define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID0 // Description : UARTPCellID0 Register -#define UART_UARTPCELLID0_OFFSET 0x00000ff0 -#define UART_UARTPCELLID0_BITS 0x000000ff -#define UART_UARTPCELLID0_RESET 0x0000000d +#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) +#define UART_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID0_UARTPCELLID0 // Description : These bits read back as 0x0D -#define UART_UARTPCELLID0_UARTPCELLID0_RESET 0x0d -#define UART_UARTPCELLID0_UARTPCELLID0_BITS 0x000000ff -#define UART_UARTPCELLID0_UARTPCELLID0_MSB 7 -#define UART_UARTPCELLID0_UARTPCELLID0_LSB 0 +#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) +#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) +#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) #define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID1 // Description : UARTPCellID1 Register -#define UART_UARTPCELLID1_OFFSET 0x00000ff4 -#define UART_UARTPCELLID1_BITS 0x000000ff -#define UART_UARTPCELLID1_RESET 0x000000f0 +#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) +#define UART_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_RESET _u(0x000000f0) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID1_UARTPCELLID1 // Description : These bits read back as 0xF0 -#define UART_UARTPCELLID1_UARTPCELLID1_RESET 0xf0 -#define UART_UARTPCELLID1_UARTPCELLID1_BITS 0x000000ff -#define UART_UARTPCELLID1_UARTPCELLID1_MSB 7 -#define UART_UARTPCELLID1_UARTPCELLID1_LSB 0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) +#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) +#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) #define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID2 // Description : UARTPCellID2 Register -#define UART_UARTPCELLID2_OFFSET 0x00000ff8 -#define UART_UARTPCELLID2_BITS 0x000000ff -#define UART_UARTPCELLID2_RESET 0x00000005 +#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) +#define UART_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID2_UARTPCELLID2 // Description : These bits read back as 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_RESET 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_BITS 0x000000ff -#define UART_UARTPCELLID2_UARTPCELLID2_MSB 7 -#define UART_UARTPCELLID2_UARTPCELLID2_LSB 0 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) +#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) +#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) #define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID3 // Description : UARTPCellID3 Register -#define UART_UARTPCELLID3_OFFSET 0x00000ffc -#define UART_UARTPCELLID3_BITS 0x000000ff -#define UART_UARTPCELLID3_RESET 0x000000b1 +#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) +#define UART_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID3_UARTPCELLID3 // Description : These bits read back as 0xB1 -#define UART_UARTPCELLID3_UARTPCELLID3_RESET 0xb1 -#define UART_UARTPCELLID3_UARTPCELLID3_BITS 0x000000ff -#define UART_UARTPCELLID3_UARTPCELLID3_MSB 7 -#define UART_UARTPCELLID3_UARTPCELLID3_LSB 0 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) +#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) +#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) #define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_UART_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h index 6693205f964..552cd11a8a5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h @@ -14,881 +14,881 @@ // ============================================================================= // Register : USB_ADDR_ENDP // Description : Device address and endpoint control -#define USB_ADDR_ENDP_OFFSET 0x00000000 -#define USB_ADDR_ENDP_BITS 0x000f007f -#define USB_ADDR_ENDP_RESET 0x00000000 +#define USB_ADDR_ENDP_OFFSET _u(0x00000000) +#define USB_ADDR_ENDP_BITS _u(0x000f007f) +#define USB_ADDR_ENDP_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP_ENDPOINT // Description : Device endpoint to send data to. Only valid for HOST mode. -#define USB_ADDR_ENDP_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP_ADDRESS // Description : In device mode, the address that the device should respond to. // Set in response to a SET_ADDR setup packet from the host. In // host mode set to the address of the device to communicate with. -#define USB_ADDR_ENDP_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP_ADDRESS_MSB 6 -#define USB_ADDR_ENDP_ADDRESS_LSB 0 +#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP1 // Description : Interrupt endpoint 1. Only valid for HOST mode. -#define USB_ADDR_ENDP1_OFFSET 0x00000004 -#define USB_ADDR_ENDP1_BITS 0x060f007f -#define USB_ADDR_ENDP1_RESET 0x00000000 +#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) +#define USB_ADDR_ENDP1_BITS _u(0x060f007f) +#define USB_ADDR_ENDP1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP1_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP1_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP1_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP1_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP1_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP1_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP1_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP1_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_ADDRESS // Description : Device address -#define USB_ADDR_ENDP1_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP1_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP1_ADDRESS_MSB 6 -#define USB_ADDR_ENDP1_ADDRESS_LSB 0 +#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP2 // Description : Interrupt endpoint 2. Only valid for HOST mode. -#define USB_ADDR_ENDP2_OFFSET 0x00000008 -#define USB_ADDR_ENDP2_BITS 0x060f007f -#define USB_ADDR_ENDP2_RESET 0x00000000 +#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) +#define USB_ADDR_ENDP2_BITS _u(0x060f007f) +#define USB_ADDR_ENDP2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP2_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP2_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP2_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP2_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP2_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP2_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP2_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP2_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_ADDRESS // Description : Device address -#define USB_ADDR_ENDP2_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP2_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP2_ADDRESS_MSB 6 -#define USB_ADDR_ENDP2_ADDRESS_LSB 0 +#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP3 // Description : Interrupt endpoint 3. Only valid for HOST mode. -#define USB_ADDR_ENDP3_OFFSET 0x0000000c -#define USB_ADDR_ENDP3_BITS 0x060f007f -#define USB_ADDR_ENDP3_RESET 0x00000000 +#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) +#define USB_ADDR_ENDP3_BITS _u(0x060f007f) +#define USB_ADDR_ENDP3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP3_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP3_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP3_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP3_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP3_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP3_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP3_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP3_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_ADDRESS // Description : Device address -#define USB_ADDR_ENDP3_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP3_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP3_ADDRESS_MSB 6 -#define USB_ADDR_ENDP3_ADDRESS_LSB 0 +#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP4 // Description : Interrupt endpoint 4. Only valid for HOST mode. -#define USB_ADDR_ENDP4_OFFSET 0x00000010 -#define USB_ADDR_ENDP4_BITS 0x060f007f -#define USB_ADDR_ENDP4_RESET 0x00000000 +#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) +#define USB_ADDR_ENDP4_BITS _u(0x060f007f) +#define USB_ADDR_ENDP4_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP4_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP4_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP4_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP4_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP4_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP4_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP4_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP4_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_ADDRESS // Description : Device address -#define USB_ADDR_ENDP4_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP4_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP4_ADDRESS_MSB 6 -#define USB_ADDR_ENDP4_ADDRESS_LSB 0 +#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP5 // Description : Interrupt endpoint 5. Only valid for HOST mode. -#define USB_ADDR_ENDP5_OFFSET 0x00000014 -#define USB_ADDR_ENDP5_BITS 0x060f007f -#define USB_ADDR_ENDP5_RESET 0x00000000 +#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) +#define USB_ADDR_ENDP5_BITS _u(0x060f007f) +#define USB_ADDR_ENDP5_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP5_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP5_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP5_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP5_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP5_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP5_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP5_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP5_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_ADDRESS // Description : Device address -#define USB_ADDR_ENDP5_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP5_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP5_ADDRESS_MSB 6 -#define USB_ADDR_ENDP5_ADDRESS_LSB 0 +#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP6 // Description : Interrupt endpoint 6. Only valid for HOST mode. -#define USB_ADDR_ENDP6_OFFSET 0x00000018 -#define USB_ADDR_ENDP6_BITS 0x060f007f -#define USB_ADDR_ENDP6_RESET 0x00000000 +#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) +#define USB_ADDR_ENDP6_BITS _u(0x060f007f) +#define USB_ADDR_ENDP6_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP6_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP6_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP6_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP6_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP6_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP6_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP6_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP6_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_ADDRESS // Description : Device address -#define USB_ADDR_ENDP6_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP6_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP6_ADDRESS_MSB 6 -#define USB_ADDR_ENDP6_ADDRESS_LSB 0 +#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP7 // Description : Interrupt endpoint 7. Only valid for HOST mode. -#define USB_ADDR_ENDP7_OFFSET 0x0000001c -#define USB_ADDR_ENDP7_BITS 0x060f007f -#define USB_ADDR_ENDP7_RESET 0x00000000 +#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) +#define USB_ADDR_ENDP7_BITS _u(0x060f007f) +#define USB_ADDR_ENDP7_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP7_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP7_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP7_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP7_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP7_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP7_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP7_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP7_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_ADDRESS // Description : Device address -#define USB_ADDR_ENDP7_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP7_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP7_ADDRESS_MSB 6 -#define USB_ADDR_ENDP7_ADDRESS_LSB 0 +#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP8 // Description : Interrupt endpoint 8. Only valid for HOST mode. -#define USB_ADDR_ENDP8_OFFSET 0x00000020 -#define USB_ADDR_ENDP8_BITS 0x060f007f -#define USB_ADDR_ENDP8_RESET 0x00000000 +#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) +#define USB_ADDR_ENDP8_BITS _u(0x060f007f) +#define USB_ADDR_ENDP8_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP8_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP8_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP8_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP8_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP8_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP8_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP8_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP8_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_ADDRESS // Description : Device address -#define USB_ADDR_ENDP8_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP8_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP8_ADDRESS_MSB 6 -#define USB_ADDR_ENDP8_ADDRESS_LSB 0 +#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP9 // Description : Interrupt endpoint 9. Only valid for HOST mode. -#define USB_ADDR_ENDP9_OFFSET 0x00000024 -#define USB_ADDR_ENDP9_BITS 0x060f007f -#define USB_ADDR_ENDP9_RESET 0x00000000 +#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) +#define USB_ADDR_ENDP9_BITS _u(0x060f007f) +#define USB_ADDR_ENDP9_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP9_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP9_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP9_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP9_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP9_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP9_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP9_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP9_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_ADDRESS // Description : Device address -#define USB_ADDR_ENDP9_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP9_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP9_ADDRESS_MSB 6 -#define USB_ADDR_ENDP9_ADDRESS_LSB 0 +#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP10 // Description : Interrupt endpoint 10. Only valid for HOST mode. -#define USB_ADDR_ENDP10_OFFSET 0x00000028 -#define USB_ADDR_ENDP10_BITS 0x060f007f -#define USB_ADDR_ENDP10_RESET 0x00000000 +#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) +#define USB_ADDR_ENDP10_BITS _u(0x060f007f) +#define USB_ADDR_ENDP10_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP10_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP10_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP10_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP10_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP10_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP10_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP10_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP10_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_ADDRESS // Description : Device address -#define USB_ADDR_ENDP10_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP10_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP10_ADDRESS_MSB 6 -#define USB_ADDR_ENDP10_ADDRESS_LSB 0 +#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP11 // Description : Interrupt endpoint 11. Only valid for HOST mode. -#define USB_ADDR_ENDP11_OFFSET 0x0000002c -#define USB_ADDR_ENDP11_BITS 0x060f007f -#define USB_ADDR_ENDP11_RESET 0x00000000 +#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) +#define USB_ADDR_ENDP11_BITS _u(0x060f007f) +#define USB_ADDR_ENDP11_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP11_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP11_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP11_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP11_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP11_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP11_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP11_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP11_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_ADDRESS // Description : Device address -#define USB_ADDR_ENDP11_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP11_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP11_ADDRESS_MSB 6 -#define USB_ADDR_ENDP11_ADDRESS_LSB 0 +#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP12 // Description : Interrupt endpoint 12. Only valid for HOST mode. -#define USB_ADDR_ENDP12_OFFSET 0x00000030 -#define USB_ADDR_ENDP12_BITS 0x060f007f -#define USB_ADDR_ENDP12_RESET 0x00000000 +#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) +#define USB_ADDR_ENDP12_BITS _u(0x060f007f) +#define USB_ADDR_ENDP12_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP12_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP12_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP12_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP12_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP12_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP12_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP12_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP12_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_ADDRESS // Description : Device address -#define USB_ADDR_ENDP12_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP12_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP12_ADDRESS_MSB 6 -#define USB_ADDR_ENDP12_ADDRESS_LSB 0 +#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP13 // Description : Interrupt endpoint 13. Only valid for HOST mode. -#define USB_ADDR_ENDP13_OFFSET 0x00000034 -#define USB_ADDR_ENDP13_BITS 0x060f007f -#define USB_ADDR_ENDP13_RESET 0x00000000 +#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) +#define USB_ADDR_ENDP13_BITS _u(0x060f007f) +#define USB_ADDR_ENDP13_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP13_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP13_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP13_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP13_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP13_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP13_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP13_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP13_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_ADDRESS // Description : Device address -#define USB_ADDR_ENDP13_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP13_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP13_ADDRESS_MSB 6 -#define USB_ADDR_ENDP13_ADDRESS_LSB 0 +#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP14 // Description : Interrupt endpoint 14. Only valid for HOST mode. -#define USB_ADDR_ENDP14_OFFSET 0x00000038 -#define USB_ADDR_ENDP14_BITS 0x060f007f -#define USB_ADDR_ENDP14_RESET 0x00000000 +#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) +#define USB_ADDR_ENDP14_BITS _u(0x060f007f) +#define USB_ADDR_ENDP14_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP14_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP14_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP14_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP14_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP14_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP14_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP14_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP14_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_ADDRESS // Description : Device address -#define USB_ADDR_ENDP14_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP14_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP14_ADDRESS_MSB 6 -#define USB_ADDR_ENDP14_ADDRESS_LSB 0 +#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP15 // Description : Interrupt endpoint 15. Only valid for HOST mode. -#define USB_ADDR_ENDP15_OFFSET 0x0000003c -#define USB_ADDR_ENDP15_BITS 0x060f007f -#define USB_ADDR_ENDP15_RESET 0x00000000 +#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) +#define USB_ADDR_ENDP15_BITS _u(0x060f007f) +#define USB_ADDR_ENDP15_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP15_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP15_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP15_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP15_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP15_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP15_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP15_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP15_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_ADDRESS // Description : Device address -#define USB_ADDR_ENDP15_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP15_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP15_ADDRESS_MSB 6 -#define USB_ADDR_ENDP15_ADDRESS_LSB 0 +#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_MAIN_CTRL // Description : Main control register -#define USB_MAIN_CTRL_OFFSET 0x00000040 -#define USB_MAIN_CTRL_BITS 0x80000003 -#define USB_MAIN_CTRL_RESET 0x00000000 +#define USB_MAIN_CTRL_OFFSET _u(0x00000040) +#define USB_MAIN_CTRL_BITS _u(0x80000003) +#define USB_MAIN_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_SIM_TIMING // Description : Reduced timings for simulation -#define USB_MAIN_CTRL_SIM_TIMING_RESET 0x0 -#define USB_MAIN_CTRL_SIM_TIMING_BITS 0x80000000 -#define USB_MAIN_CTRL_SIM_TIMING_MSB 31 -#define USB_MAIN_CTRL_SIM_TIMING_LSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) +#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) +#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) #define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_HOST_NDEVICE // Description : Device mode = 0, Host mode = 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_RESET 0x0 -#define USB_MAIN_CTRL_HOST_NDEVICE_BITS 0x00000002 -#define USB_MAIN_CTRL_HOST_NDEVICE_MSB 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_LSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) #define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_CONTROLLER_EN // Description : Enable controller -#define USB_MAIN_CTRL_CONTROLLER_EN_RESET 0x0 -#define USB_MAIN_CTRL_CONTROLLER_EN_BITS 0x00000001 -#define USB_MAIN_CTRL_CONTROLLER_EN_MSB 0 -#define USB_MAIN_CTRL_CONTROLLER_EN_LSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) #define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" // ============================================================================= // Register : USB_SOF_WR // Description : Set the SOF (Start of Frame) frame number in the host // controller. The SOF packet is sent every 1ms and the host will // increment the frame number by 1 each time. -#define USB_SOF_WR_OFFSET 0x00000044 -#define USB_SOF_WR_BITS 0x000007ff -#define USB_SOF_WR_RESET 0x00000000 +#define USB_SOF_WR_OFFSET _u(0x00000044) +#define USB_SOF_WR_BITS _u(0x000007ff) +#define USB_SOF_WR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_WR_COUNT // Description : None -#define USB_SOF_WR_COUNT_RESET 0x000 -#define USB_SOF_WR_COUNT_BITS 0x000007ff -#define USB_SOF_WR_COUNT_MSB 10 -#define USB_SOF_WR_COUNT_LSB 0 +#define USB_SOF_WR_COUNT_RESET _u(0x000) +#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) +#define USB_SOF_WR_COUNT_MSB _u(10) +#define USB_SOF_WR_COUNT_LSB _u(0) #define USB_SOF_WR_COUNT_ACCESS "WF" // ============================================================================= // Register : USB_SOF_RD // Description : Read the last SOF (Start of Frame) frame number seen. In device // mode the last SOF received from the host. In host mode the last // SOF sent by the host. -#define USB_SOF_RD_OFFSET 0x00000048 -#define USB_SOF_RD_BITS 0x000007ff -#define USB_SOF_RD_RESET 0x00000000 +#define USB_SOF_RD_OFFSET _u(0x00000048) +#define USB_SOF_RD_BITS _u(0x000007ff) +#define USB_SOF_RD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_RD_COUNT // Description : None -#define USB_SOF_RD_COUNT_RESET 0x000 -#define USB_SOF_RD_COUNT_BITS 0x000007ff -#define USB_SOF_RD_COUNT_MSB 10 -#define USB_SOF_RD_COUNT_LSB 0 +#define USB_SOF_RD_COUNT_RESET _u(0x000) +#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) +#define USB_SOF_RD_COUNT_MSB _u(10) +#define USB_SOF_RD_COUNT_LSB _u(0) #define USB_SOF_RD_COUNT_ACCESS "RO" // ============================================================================= // Register : USB_SIE_CTRL // Description : SIE control register -#define USB_SIE_CTRL_OFFSET 0x0000004c -#define USB_SIE_CTRL_BITS 0xff07bf5f -#define USB_SIE_CTRL_RESET 0x00000000 +#define USB_SIE_CTRL_OFFSET _u(0x0000004c) +#define USB_SIE_CTRL_BITS _u(0xff07bf5f) +#define USB_SIE_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_STALL // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL -#define USB_SIE_CTRL_EP0_INT_STALL_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_STALL_BITS 0x80000000 -#define USB_SIE_CTRL_EP0_INT_STALL_MSB 31 -#define USB_SIE_CTRL_EP0_INT_STALL_LSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) +#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) #define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_DOUBLE_BUF // Description : Device: EP0 single buffered = 0, double buffered = 1 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS 0x40000000 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB 30 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) #define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_1BUF // Description : Device: Set bit in BUFF_STATUS for every buffer completed on // EP0 -#define USB_SIE_CTRL_EP0_INT_1BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_1BUF_BITS 0x20000000 -#define USB_SIE_CTRL_EP0_INT_1BUF_MSB 29 -#define USB_SIE_CTRL_EP0_INT_1BUF_LSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) #define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_2BUF // Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on // EP0 -#define USB_SIE_CTRL_EP0_INT_2BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_2BUF_BITS 0x10000000 -#define USB_SIE_CTRL_EP0_INT_2BUF_MSB 28 -#define USB_SIE_CTRL_EP0_INT_2BUF_LSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) #define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_NAK // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK -#define USB_SIE_CTRL_EP0_INT_NAK_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_NAK_BITS 0x08000000 -#define USB_SIE_CTRL_EP0_INT_NAK_MSB 27 -#define USB_SIE_CTRL_EP0_INT_NAK_LSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) +#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) #define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_EN // Description : Direct bus drive enable -#define USB_SIE_CTRL_DIRECT_EN_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_EN_BITS 0x04000000 -#define USB_SIE_CTRL_DIRECT_EN_MSB 26 -#define USB_SIE_CTRL_DIRECT_EN_LSB 26 +#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) +#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) #define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_DP // Description : Direct control of DP -#define USB_SIE_CTRL_DIRECT_DP_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_DP_BITS 0x02000000 -#define USB_SIE_CTRL_DIRECT_DP_MSB 25 -#define USB_SIE_CTRL_DIRECT_DP_LSB 25 +#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) +#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) #define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_DM // Description : Direct control of DM -#define USB_SIE_CTRL_DIRECT_DM_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_DM_BITS 0x01000000 -#define USB_SIE_CTRL_DIRECT_DM_MSB 24 -#define USB_SIE_CTRL_DIRECT_DM_LSB 24 +#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) +#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) #define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_TRANSCEIVER_PD // Description : Power down bus transceiver -#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET 0x0 -#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS 0x00040000 -#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB 18 -#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) #define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RPU_OPT // Description : Device: Pull-up strength (0=1K2, 1=2k3) -#define USB_SIE_CTRL_RPU_OPT_RESET 0x0 -#define USB_SIE_CTRL_RPU_OPT_BITS 0x00020000 -#define USB_SIE_CTRL_RPU_OPT_MSB 17 -#define USB_SIE_CTRL_RPU_OPT_LSB 17 +#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) +#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) +#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) #define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PULLUP_EN // Description : Device: Enable pull up resistor -#define USB_SIE_CTRL_PULLUP_EN_RESET 0x0 -#define USB_SIE_CTRL_PULLUP_EN_BITS 0x00010000 -#define USB_SIE_CTRL_PULLUP_EN_MSB 16 -#define USB_SIE_CTRL_PULLUP_EN_LSB 16 +#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) +#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) #define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PULLDOWN_EN // Description : Host: Enable pull down resistors -#define USB_SIE_CTRL_PULLDOWN_EN_RESET 0x0 -#define USB_SIE_CTRL_PULLDOWN_EN_BITS 0x00008000 -#define USB_SIE_CTRL_PULLDOWN_EN_MSB 15 -#define USB_SIE_CTRL_PULLDOWN_EN_LSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) +#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) #define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RESET_BUS // Description : Host: Reset bus -#define USB_SIE_CTRL_RESET_BUS_RESET 0x0 -#define USB_SIE_CTRL_RESET_BUS_BITS 0x00002000 -#define USB_SIE_CTRL_RESET_BUS_MSB 13 -#define USB_SIE_CTRL_RESET_BUS_LSB 13 +#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) +#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) +#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) #define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RESUME // Description : Device: Remote wakeup. Device can initiate its own resume after // suspend. -#define USB_SIE_CTRL_RESUME_RESET 0x0 -#define USB_SIE_CTRL_RESUME_BITS 0x00001000 -#define USB_SIE_CTRL_RESUME_MSB 12 -#define USB_SIE_CTRL_RESUME_LSB 12 +#define USB_SIE_CTRL_RESUME_RESET _u(0x0) +#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) +#define USB_SIE_CTRL_RESUME_MSB _u(12) +#define USB_SIE_CTRL_RESUME_LSB _u(12) #define USB_SIE_CTRL_RESUME_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_VBUS_EN // Description : Host: Enable VBUS -#define USB_SIE_CTRL_VBUS_EN_RESET 0x0 -#define USB_SIE_CTRL_VBUS_EN_BITS 0x00000800 -#define USB_SIE_CTRL_VBUS_EN_MSB 11 -#define USB_SIE_CTRL_VBUS_EN_LSB 11 +#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) +#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) +#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) #define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_KEEP_ALIVE_EN // Description : Host: Enable keep alive packet (for low speed bus) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET 0x0 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS 0x00000400 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB 10 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) #define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SOF_EN // Description : Host: Enable SOF generation (for full speed bus) -#define USB_SIE_CTRL_SOF_EN_RESET 0x0 -#define USB_SIE_CTRL_SOF_EN_BITS 0x00000200 -#define USB_SIE_CTRL_SOF_EN_MSB 9 -#define USB_SIE_CTRL_SOF_EN_LSB 9 +#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) +#define USB_SIE_CTRL_SOF_EN_MSB _u(9) +#define USB_SIE_CTRL_SOF_EN_LSB _u(9) #define USB_SIE_CTRL_SOF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SOF_SYNC // Description : Host: Delay packet(s) until after SOF -#define USB_SIE_CTRL_SOF_SYNC_RESET 0x0 -#define USB_SIE_CTRL_SOF_SYNC_BITS 0x00000100 -#define USB_SIE_CTRL_SOF_SYNC_MSB 8 -#define USB_SIE_CTRL_SOF_SYNC_LSB 8 +#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) +#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) #define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PREAMBLE_EN // Description : Host: Preable enable for LS device on FS hub -#define USB_SIE_CTRL_PREAMBLE_EN_RESET 0x0 -#define USB_SIE_CTRL_PREAMBLE_EN_BITS 0x00000040 -#define USB_SIE_CTRL_PREAMBLE_EN_MSB 6 -#define USB_SIE_CTRL_PREAMBLE_EN_LSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) +#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) #define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_STOP_TRANS // Description : Host: Stop transaction -#define USB_SIE_CTRL_STOP_TRANS_RESET 0x0 -#define USB_SIE_CTRL_STOP_TRANS_BITS 0x00000010 -#define USB_SIE_CTRL_STOP_TRANS_MSB 4 -#define USB_SIE_CTRL_STOP_TRANS_LSB 4 +#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) +#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) #define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RECEIVE_DATA // Description : Host: Receive transaction (IN to host) -#define USB_SIE_CTRL_RECEIVE_DATA_RESET 0x0 -#define USB_SIE_CTRL_RECEIVE_DATA_BITS 0x00000008 -#define USB_SIE_CTRL_RECEIVE_DATA_MSB 3 -#define USB_SIE_CTRL_RECEIVE_DATA_LSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) +#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) #define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SEND_DATA // Description : Host: Send transaction (OUT from host) -#define USB_SIE_CTRL_SEND_DATA_RESET 0x0 -#define USB_SIE_CTRL_SEND_DATA_BITS 0x00000004 -#define USB_SIE_CTRL_SEND_DATA_MSB 2 -#define USB_SIE_CTRL_SEND_DATA_LSB 2 +#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) +#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) #define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SEND_SETUP // Description : Host: Send Setup packet -#define USB_SIE_CTRL_SEND_SETUP_RESET 0x0 -#define USB_SIE_CTRL_SEND_SETUP_BITS 0x00000002 -#define USB_SIE_CTRL_SEND_SETUP_MSB 1 -#define USB_SIE_CTRL_SEND_SETUP_LSB 1 +#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) +#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) #define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_START_TRANS // Description : Host: Start transaction -#define USB_SIE_CTRL_START_TRANS_RESET 0x0 -#define USB_SIE_CTRL_START_TRANS_BITS 0x00000001 -#define USB_SIE_CTRL_START_TRANS_MSB 0 -#define USB_SIE_CTRL_START_TRANS_LSB 0 +#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) +#define USB_SIE_CTRL_START_TRANS_MSB _u(0) +#define USB_SIE_CTRL_START_TRANS_LSB _u(0) #define USB_SIE_CTRL_START_TRANS_ACCESS "SC" // ============================================================================= // Register : USB_SIE_STATUS // Description : SIE status register -#define USB_SIE_STATUS_OFFSET 0x00000050 -#define USB_SIE_STATUS_BITS 0xff0f0f1d -#define USB_SIE_STATUS_RESET 0x00000000 +#define USB_SIE_STATUS_OFFSET _u(0x00000050) +#define USB_SIE_STATUS_BITS _u(0xff0f0f1d) +#define USB_SIE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_DATA_SEQ_ERROR // Description : Data Sequence Error. @@ -905,76 +905,76 @@ // conditions: // // * An IN packet from the device has the wrong data PID -#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET 0x0 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS 0x80000000 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB 31 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) #define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_ACK_REC // Description : ACK received. Raised by both host and device. -#define USB_SIE_STATUS_ACK_REC_RESET 0x0 -#define USB_SIE_STATUS_ACK_REC_BITS 0x40000000 -#define USB_SIE_STATUS_ACK_REC_MSB 30 -#define USB_SIE_STATUS_ACK_REC_LSB 30 +#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) +#define USB_SIE_STATUS_ACK_REC_MSB _u(30) +#define USB_SIE_STATUS_ACK_REC_LSB _u(30) #define USB_SIE_STATUS_ACK_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_STALL_REC // Description : Host: STALL received -#define USB_SIE_STATUS_STALL_REC_RESET 0x0 -#define USB_SIE_STATUS_STALL_REC_BITS 0x20000000 -#define USB_SIE_STATUS_STALL_REC_MSB 29 -#define USB_SIE_STATUS_STALL_REC_LSB 29 +#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) +#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) +#define USB_SIE_STATUS_STALL_REC_MSB _u(29) +#define USB_SIE_STATUS_STALL_REC_LSB _u(29) #define USB_SIE_STATUS_STALL_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_NAK_REC // Description : Host: NAK received -#define USB_SIE_STATUS_NAK_REC_RESET 0x0 -#define USB_SIE_STATUS_NAK_REC_BITS 0x10000000 -#define USB_SIE_STATUS_NAK_REC_MSB 28 -#define USB_SIE_STATUS_NAK_REC_LSB 28 +#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) +#define USB_SIE_STATUS_NAK_REC_MSB _u(28) +#define USB_SIE_STATUS_NAK_REC_LSB _u(28) #define USB_SIE_STATUS_NAK_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RX_TIMEOUT // Description : RX timeout is raised by both the host and device if an ACK is // not received in the maximum time specified by the USB spec. -#define USB_SIE_STATUS_RX_TIMEOUT_RESET 0x0 -#define USB_SIE_STATUS_RX_TIMEOUT_BITS 0x08000000 -#define USB_SIE_STATUS_RX_TIMEOUT_MSB 27 -#define USB_SIE_STATUS_RX_TIMEOUT_LSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) +#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) +#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) #define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RX_OVERFLOW // Description : RX overflow is raised by the Serial RX engine if the incoming // data is too fast. -#define USB_SIE_STATUS_RX_OVERFLOW_RESET 0x0 -#define USB_SIE_STATUS_RX_OVERFLOW_BITS 0x04000000 -#define USB_SIE_STATUS_RX_OVERFLOW_MSB 26 -#define USB_SIE_STATUS_RX_OVERFLOW_LSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) +#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) +#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) #define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_BIT_STUFF_ERROR // Description : Bit Stuff Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET 0x0 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS 0x02000000 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB 25 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) #define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_CRC_ERROR // Description : CRC Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_CRC_ERROR_RESET 0x0 -#define USB_SIE_STATUS_CRC_ERROR_BITS 0x01000000 -#define USB_SIE_STATUS_CRC_ERROR_MSB 24 -#define USB_SIE_STATUS_CRC_ERROR_LSB 24 +#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) +#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) #define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_BUS_RESET // Description : Device: bus reset received -#define USB_SIE_STATUS_BUS_RESET_RESET 0x0 -#define USB_SIE_STATUS_BUS_RESET_BITS 0x00080000 -#define USB_SIE_STATUS_BUS_RESET_MSB 19 -#define USB_SIE_STATUS_BUS_RESET_LSB 19 +#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) +#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) +#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) #define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_TRANS_COMPLETE @@ -992,91 +992,91 @@ // `LAST_BUFF` bit is set in the buffer control register * An IN // packet is received with zero length * An OUT packet is sent and // the `LAST_BUFF` bit is set -#define USB_SIE_STATUS_TRANS_COMPLETE_RESET 0x0 -#define USB_SIE_STATUS_TRANS_COMPLETE_BITS 0x00040000 -#define USB_SIE_STATUS_TRANS_COMPLETE_MSB 18 -#define USB_SIE_STATUS_TRANS_COMPLETE_LSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) #define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SETUP_REC // Description : Device: Setup packet received -#define USB_SIE_STATUS_SETUP_REC_RESET 0x0 -#define USB_SIE_STATUS_SETUP_REC_BITS 0x00020000 -#define USB_SIE_STATUS_SETUP_REC_MSB 17 -#define USB_SIE_STATUS_SETUP_REC_LSB 17 +#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) +#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) +#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) #define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_CONNECTED // Description : Device: connected -#define USB_SIE_STATUS_CONNECTED_RESET 0x0 -#define USB_SIE_STATUS_CONNECTED_BITS 0x00010000 -#define USB_SIE_STATUS_CONNECTED_MSB 16 -#define USB_SIE_STATUS_CONNECTED_LSB 16 -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) +#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) +#define USB_SIE_STATUS_CONNECTED_MSB _u(16) +#define USB_SIE_STATUS_CONNECTED_LSB _u(16) +#define USB_SIE_STATUS_CONNECTED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RESUME // Description : Host: Device has initiated a remote resume. Device: host has // initiated a resume. -#define USB_SIE_STATUS_RESUME_RESET 0x0 -#define USB_SIE_STATUS_RESUME_BITS 0x00000800 -#define USB_SIE_STATUS_RESUME_MSB 11 -#define USB_SIE_STATUS_RESUME_LSB 11 +#define USB_SIE_STATUS_RESUME_RESET _u(0x0) +#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) +#define USB_SIE_STATUS_RESUME_MSB _u(11) +#define USB_SIE_STATUS_RESUME_LSB _u(11) #define USB_SIE_STATUS_RESUME_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_VBUS_OVER_CURR // Description : VBUS over current detected -#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET 0x0 -#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS 0x00000400 -#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB 10 -#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) #define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SPEED // Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 -#define USB_SIE_STATUS_SPEED_RESET 0x0 -#define USB_SIE_STATUS_SPEED_BITS 0x00000300 -#define USB_SIE_STATUS_SPEED_MSB 9 -#define USB_SIE_STATUS_SPEED_LSB 8 -#define USB_SIE_STATUS_SPEED_ACCESS "RO" +#define USB_SIE_STATUS_SPEED_RESET _u(0x0) +#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) +#define USB_SIE_STATUS_SPEED_MSB _u(9) +#define USB_SIE_STATUS_SPEED_LSB _u(8) +#define USB_SIE_STATUS_SPEED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SUSPENDED // Description : Bus in suspended state. Valid for device and host. Host and // device will go into suspend if neither Keep Alive / SOF frames // are enabled. -#define USB_SIE_STATUS_SUSPENDED_RESET 0x0 -#define USB_SIE_STATUS_SUSPENDED_BITS 0x00000010 -#define USB_SIE_STATUS_SUSPENDED_MSB 4 -#define USB_SIE_STATUS_SUSPENDED_LSB 4 -#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) +#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) +#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_LINE_STATE // Description : USB bus line state -#define USB_SIE_STATUS_LINE_STATE_RESET 0x0 -#define USB_SIE_STATUS_LINE_STATE_BITS 0x0000000c -#define USB_SIE_STATUS_LINE_STATE_MSB 3 -#define USB_SIE_STATUS_LINE_STATE_LSB 2 +#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) +#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) +#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) +#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) #define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_VBUS_DETECTED // Description : Device: VBUS Detected -#define USB_SIE_STATUS_VBUS_DETECTED_RESET 0x0 -#define USB_SIE_STATUS_VBUS_DETECTED_BITS 0x00000001 -#define USB_SIE_STATUS_VBUS_DETECTED_MSB 0 -#define USB_SIE_STATUS_VBUS_DETECTED_LSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) +#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) #define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" // ============================================================================= // Register : USB_INT_EP_CTRL // Description : interrupt endpoint control register -#define USB_INT_EP_CTRL_OFFSET 0x00000054 -#define USB_INT_EP_CTRL_BITS 0x0000fffe -#define USB_INT_EP_CTRL_RESET 0x00000000 +#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) +#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INT_EP_CTRL_INT_EP_ACTIVE // Description : Host: Enable interrupt endpoint 1 -> 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET 0x0000 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS 0x0000fffe -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB 1 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" // ============================================================================= // Register : USB_BUFF_STATUS @@ -1085,529 +1085,529 @@ // enabled). It is possible for 2 buffers to be completed, so // clearing the buffer status bit may instantly re set it on the // next clock cycle. -#define USB_BUFF_STATUS_OFFSET 0x00000058 -#define USB_BUFF_STATUS_BITS 0xffffffff -#define USB_BUFF_STATUS_RESET 0x00000000 +#define USB_BUFF_STATUS_OFFSET _u(0x00000058) +#define USB_BUFF_STATUS_BITS _u(0xffffffff) +#define USB_BUFF_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_OUT // Description : None -#define USB_BUFF_STATUS_EP15_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP15_OUT_BITS 0x80000000 -#define USB_BUFF_STATUS_EP15_OUT_MSB 31 -#define USB_BUFF_STATUS_EP15_OUT_LSB 31 -#define USB_BUFF_STATUS_EP15_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_IN // Description : None -#define USB_BUFF_STATUS_EP15_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP15_IN_BITS 0x40000000 -#define USB_BUFF_STATUS_EP15_IN_MSB 30 -#define USB_BUFF_STATUS_EP15_IN_LSB 30 -#define USB_BUFF_STATUS_EP15_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_OUT // Description : None -#define USB_BUFF_STATUS_EP14_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP14_OUT_BITS 0x20000000 -#define USB_BUFF_STATUS_EP14_OUT_MSB 29 -#define USB_BUFF_STATUS_EP14_OUT_LSB 29 -#define USB_BUFF_STATUS_EP14_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_IN // Description : None -#define USB_BUFF_STATUS_EP14_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP14_IN_BITS 0x10000000 -#define USB_BUFF_STATUS_EP14_IN_MSB 28 -#define USB_BUFF_STATUS_EP14_IN_LSB 28 -#define USB_BUFF_STATUS_EP14_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_OUT // Description : None -#define USB_BUFF_STATUS_EP13_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP13_OUT_BITS 0x08000000 -#define USB_BUFF_STATUS_EP13_OUT_MSB 27 -#define USB_BUFF_STATUS_EP13_OUT_LSB 27 -#define USB_BUFF_STATUS_EP13_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_IN // Description : None -#define USB_BUFF_STATUS_EP13_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP13_IN_BITS 0x04000000 -#define USB_BUFF_STATUS_EP13_IN_MSB 26 -#define USB_BUFF_STATUS_EP13_IN_LSB 26 -#define USB_BUFF_STATUS_EP13_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_OUT // Description : None -#define USB_BUFF_STATUS_EP12_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP12_OUT_BITS 0x02000000 -#define USB_BUFF_STATUS_EP12_OUT_MSB 25 -#define USB_BUFF_STATUS_EP12_OUT_LSB 25 -#define USB_BUFF_STATUS_EP12_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_IN // Description : None -#define USB_BUFF_STATUS_EP12_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP12_IN_BITS 0x01000000 -#define USB_BUFF_STATUS_EP12_IN_MSB 24 -#define USB_BUFF_STATUS_EP12_IN_LSB 24 -#define USB_BUFF_STATUS_EP12_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_OUT // Description : None -#define USB_BUFF_STATUS_EP11_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP11_OUT_BITS 0x00800000 -#define USB_BUFF_STATUS_EP11_OUT_MSB 23 -#define USB_BUFF_STATUS_EP11_OUT_LSB 23 -#define USB_BUFF_STATUS_EP11_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_IN // Description : None -#define USB_BUFF_STATUS_EP11_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP11_IN_BITS 0x00400000 -#define USB_BUFF_STATUS_EP11_IN_MSB 22 -#define USB_BUFF_STATUS_EP11_IN_LSB 22 -#define USB_BUFF_STATUS_EP11_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_OUT // Description : None -#define USB_BUFF_STATUS_EP10_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP10_OUT_BITS 0x00200000 -#define USB_BUFF_STATUS_EP10_OUT_MSB 21 -#define USB_BUFF_STATUS_EP10_OUT_LSB 21 -#define USB_BUFF_STATUS_EP10_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_IN // Description : None -#define USB_BUFF_STATUS_EP10_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP10_IN_BITS 0x00100000 -#define USB_BUFF_STATUS_EP10_IN_MSB 20 -#define USB_BUFF_STATUS_EP10_IN_LSB 20 -#define USB_BUFF_STATUS_EP10_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_OUT // Description : None -#define USB_BUFF_STATUS_EP9_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP9_OUT_BITS 0x00080000 -#define USB_BUFF_STATUS_EP9_OUT_MSB 19 -#define USB_BUFF_STATUS_EP9_OUT_LSB 19 -#define USB_BUFF_STATUS_EP9_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_IN // Description : None -#define USB_BUFF_STATUS_EP9_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP9_IN_BITS 0x00040000 -#define USB_BUFF_STATUS_EP9_IN_MSB 18 -#define USB_BUFF_STATUS_EP9_IN_LSB 18 -#define USB_BUFF_STATUS_EP9_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_OUT // Description : None -#define USB_BUFF_STATUS_EP8_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP8_OUT_BITS 0x00020000 -#define USB_BUFF_STATUS_EP8_OUT_MSB 17 -#define USB_BUFF_STATUS_EP8_OUT_LSB 17 -#define USB_BUFF_STATUS_EP8_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_IN // Description : None -#define USB_BUFF_STATUS_EP8_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP8_IN_BITS 0x00010000 -#define USB_BUFF_STATUS_EP8_IN_MSB 16 -#define USB_BUFF_STATUS_EP8_IN_LSB 16 -#define USB_BUFF_STATUS_EP8_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_OUT // Description : None -#define USB_BUFF_STATUS_EP7_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP7_OUT_BITS 0x00008000 -#define USB_BUFF_STATUS_EP7_OUT_MSB 15 -#define USB_BUFF_STATUS_EP7_OUT_LSB 15 -#define USB_BUFF_STATUS_EP7_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_IN // Description : None -#define USB_BUFF_STATUS_EP7_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP7_IN_BITS 0x00004000 -#define USB_BUFF_STATUS_EP7_IN_MSB 14 -#define USB_BUFF_STATUS_EP7_IN_LSB 14 -#define USB_BUFF_STATUS_EP7_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_OUT // Description : None -#define USB_BUFF_STATUS_EP6_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP6_OUT_BITS 0x00002000 -#define USB_BUFF_STATUS_EP6_OUT_MSB 13 -#define USB_BUFF_STATUS_EP6_OUT_LSB 13 -#define USB_BUFF_STATUS_EP6_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_IN // Description : None -#define USB_BUFF_STATUS_EP6_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP6_IN_BITS 0x00001000 -#define USB_BUFF_STATUS_EP6_IN_MSB 12 -#define USB_BUFF_STATUS_EP6_IN_LSB 12 -#define USB_BUFF_STATUS_EP6_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_OUT // Description : None -#define USB_BUFF_STATUS_EP5_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP5_OUT_BITS 0x00000800 -#define USB_BUFF_STATUS_EP5_OUT_MSB 11 -#define USB_BUFF_STATUS_EP5_OUT_LSB 11 -#define USB_BUFF_STATUS_EP5_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_IN // Description : None -#define USB_BUFF_STATUS_EP5_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP5_IN_BITS 0x00000400 -#define USB_BUFF_STATUS_EP5_IN_MSB 10 -#define USB_BUFF_STATUS_EP5_IN_LSB 10 -#define USB_BUFF_STATUS_EP5_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_OUT // Description : None -#define USB_BUFF_STATUS_EP4_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP4_OUT_BITS 0x00000200 -#define USB_BUFF_STATUS_EP4_OUT_MSB 9 -#define USB_BUFF_STATUS_EP4_OUT_LSB 9 -#define USB_BUFF_STATUS_EP4_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_IN // Description : None -#define USB_BUFF_STATUS_EP4_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP4_IN_BITS 0x00000100 -#define USB_BUFF_STATUS_EP4_IN_MSB 8 -#define USB_BUFF_STATUS_EP4_IN_LSB 8 -#define USB_BUFF_STATUS_EP4_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_OUT // Description : None -#define USB_BUFF_STATUS_EP3_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP3_OUT_BITS 0x00000080 -#define USB_BUFF_STATUS_EP3_OUT_MSB 7 -#define USB_BUFF_STATUS_EP3_OUT_LSB 7 -#define USB_BUFF_STATUS_EP3_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_IN // Description : None -#define USB_BUFF_STATUS_EP3_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP3_IN_BITS 0x00000040 -#define USB_BUFF_STATUS_EP3_IN_MSB 6 -#define USB_BUFF_STATUS_EP3_IN_LSB 6 -#define USB_BUFF_STATUS_EP3_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_OUT // Description : None -#define USB_BUFF_STATUS_EP2_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP2_OUT_BITS 0x00000020 -#define USB_BUFF_STATUS_EP2_OUT_MSB 5 -#define USB_BUFF_STATUS_EP2_OUT_LSB 5 -#define USB_BUFF_STATUS_EP2_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_IN // Description : None -#define USB_BUFF_STATUS_EP2_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP2_IN_BITS 0x00000010 -#define USB_BUFF_STATUS_EP2_IN_MSB 4 -#define USB_BUFF_STATUS_EP2_IN_LSB 4 -#define USB_BUFF_STATUS_EP2_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_OUT // Description : None -#define USB_BUFF_STATUS_EP1_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP1_OUT_BITS 0x00000008 -#define USB_BUFF_STATUS_EP1_OUT_MSB 3 -#define USB_BUFF_STATUS_EP1_OUT_LSB 3 -#define USB_BUFF_STATUS_EP1_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_IN // Description : None -#define USB_BUFF_STATUS_EP1_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP1_IN_BITS 0x00000004 -#define USB_BUFF_STATUS_EP1_IN_MSB 2 -#define USB_BUFF_STATUS_EP1_IN_LSB 2 -#define USB_BUFF_STATUS_EP1_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_OUT // Description : None -#define USB_BUFF_STATUS_EP0_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP0_OUT_BITS 0x00000002 -#define USB_BUFF_STATUS_EP0_OUT_MSB 1 -#define USB_BUFF_STATUS_EP0_OUT_LSB 1 -#define USB_BUFF_STATUS_EP0_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_IN // Description : None -#define USB_BUFF_STATUS_EP0_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP0_IN_BITS 0x00000001 -#define USB_BUFF_STATUS_EP0_IN_MSB 0 -#define USB_BUFF_STATUS_EP0_IN_LSB 0 -#define USB_BUFF_STATUS_EP0_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_BUFF_CPU_SHOULD_HANDLE // Description : Which of the double buffers should be handled. Only valid if // using an interrupt per buffer (i.e. not per 2 buffers). Not // valid for host interrupt endpoint polling because they are only // single buffered. -#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x0000005c -#define USB_BUFF_CPU_SHOULD_HANDLE_BITS 0xffffffff -#define USB_BUFF_CPU_SHOULD_HANDLE_RESET 0x00000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS 0x80000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB 31 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS 0x40000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB 30 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS 0x20000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB 29 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS 0x10000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB 28 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS 0x08000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB 27 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS 0x04000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB 26 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS 0x02000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB 25 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS 0x01000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB 24 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS 0x00800000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB 23 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS 0x00400000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB 22 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS 0x00200000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB 21 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS 0x00100000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB 20 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS 0x00080000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB 19 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS 0x00040000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB 18 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS 0x00020000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB 17 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS 0x00010000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB 16 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS 0x00008000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB 15 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS 0x00004000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB 14 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS 0x00002000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB 13 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS 0x00001000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB 12 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS 0x00000800 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB 11 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS 0x00000400 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB 10 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS 0x00000200 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB 9 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS 0x00000100 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB 8 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS 0x00000080 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB 7 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS 0x00000040 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB 6 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS 0x00000020 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB 5 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS 0x00000010 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB 4 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS 0x00000008 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB 3 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS 0x00000004 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB 2 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS 0x00000002 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB 1 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS 0x00000001 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB 0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" // ============================================================================= // Register : USB_EP_ABORT @@ -1616,528 +1616,528 @@ // NAK will be sent for every access to the endpoint until this // bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set // when it is safe to modify the buffer control register. -#define USB_EP_ABORT_OFFSET 0x00000060 -#define USB_EP_ABORT_BITS 0xffffffff -#define USB_EP_ABORT_RESET 0x00000000 +#define USB_EP_ABORT_OFFSET _u(0x00000060) +#define USB_EP_ABORT_BITS _u(0xffffffff) +#define USB_EP_ABORT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_OUT // Description : None -#define USB_EP_ABORT_EP15_OUT_RESET 0x0 -#define USB_EP_ABORT_EP15_OUT_BITS 0x80000000 -#define USB_EP_ABORT_EP15_OUT_MSB 31 -#define USB_EP_ABORT_EP15_OUT_LSB 31 +#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_EP15_OUT_LSB _u(31) #define USB_EP_ABORT_EP15_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_IN // Description : None -#define USB_EP_ABORT_EP15_IN_RESET 0x0 -#define USB_EP_ABORT_EP15_IN_BITS 0x40000000 -#define USB_EP_ABORT_EP15_IN_MSB 30 -#define USB_EP_ABORT_EP15_IN_LSB 30 +#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_EP15_IN_LSB _u(30) #define USB_EP_ABORT_EP15_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_OUT // Description : None -#define USB_EP_ABORT_EP14_OUT_RESET 0x0 -#define USB_EP_ABORT_EP14_OUT_BITS 0x20000000 -#define USB_EP_ABORT_EP14_OUT_MSB 29 -#define USB_EP_ABORT_EP14_OUT_LSB 29 +#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_EP14_OUT_LSB _u(29) #define USB_EP_ABORT_EP14_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_IN // Description : None -#define USB_EP_ABORT_EP14_IN_RESET 0x0 -#define USB_EP_ABORT_EP14_IN_BITS 0x10000000 -#define USB_EP_ABORT_EP14_IN_MSB 28 -#define USB_EP_ABORT_EP14_IN_LSB 28 +#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_EP14_IN_LSB _u(28) #define USB_EP_ABORT_EP14_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_OUT // Description : None -#define USB_EP_ABORT_EP13_OUT_RESET 0x0 -#define USB_EP_ABORT_EP13_OUT_BITS 0x08000000 -#define USB_EP_ABORT_EP13_OUT_MSB 27 -#define USB_EP_ABORT_EP13_OUT_LSB 27 +#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_EP13_OUT_LSB _u(27) #define USB_EP_ABORT_EP13_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_IN // Description : None -#define USB_EP_ABORT_EP13_IN_RESET 0x0 -#define USB_EP_ABORT_EP13_IN_BITS 0x04000000 -#define USB_EP_ABORT_EP13_IN_MSB 26 -#define USB_EP_ABORT_EP13_IN_LSB 26 +#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_EP13_IN_LSB _u(26) #define USB_EP_ABORT_EP13_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_OUT // Description : None -#define USB_EP_ABORT_EP12_OUT_RESET 0x0 -#define USB_EP_ABORT_EP12_OUT_BITS 0x02000000 -#define USB_EP_ABORT_EP12_OUT_MSB 25 -#define USB_EP_ABORT_EP12_OUT_LSB 25 +#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_EP12_OUT_LSB _u(25) #define USB_EP_ABORT_EP12_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_IN // Description : None -#define USB_EP_ABORT_EP12_IN_RESET 0x0 -#define USB_EP_ABORT_EP12_IN_BITS 0x01000000 -#define USB_EP_ABORT_EP12_IN_MSB 24 -#define USB_EP_ABORT_EP12_IN_LSB 24 +#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_EP12_IN_LSB _u(24) #define USB_EP_ABORT_EP12_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_OUT // Description : None -#define USB_EP_ABORT_EP11_OUT_RESET 0x0 -#define USB_EP_ABORT_EP11_OUT_BITS 0x00800000 -#define USB_EP_ABORT_EP11_OUT_MSB 23 -#define USB_EP_ABORT_EP11_OUT_LSB 23 +#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_EP11_OUT_LSB _u(23) #define USB_EP_ABORT_EP11_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_IN // Description : None -#define USB_EP_ABORT_EP11_IN_RESET 0x0 -#define USB_EP_ABORT_EP11_IN_BITS 0x00400000 -#define USB_EP_ABORT_EP11_IN_MSB 22 -#define USB_EP_ABORT_EP11_IN_LSB 22 +#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_EP11_IN_LSB _u(22) #define USB_EP_ABORT_EP11_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_OUT // Description : None -#define USB_EP_ABORT_EP10_OUT_RESET 0x0 -#define USB_EP_ABORT_EP10_OUT_BITS 0x00200000 -#define USB_EP_ABORT_EP10_OUT_MSB 21 -#define USB_EP_ABORT_EP10_OUT_LSB 21 +#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_EP10_OUT_LSB _u(21) #define USB_EP_ABORT_EP10_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_IN // Description : None -#define USB_EP_ABORT_EP10_IN_RESET 0x0 -#define USB_EP_ABORT_EP10_IN_BITS 0x00100000 -#define USB_EP_ABORT_EP10_IN_MSB 20 -#define USB_EP_ABORT_EP10_IN_LSB 20 +#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_EP10_IN_LSB _u(20) #define USB_EP_ABORT_EP10_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_OUT // Description : None -#define USB_EP_ABORT_EP9_OUT_RESET 0x0 -#define USB_EP_ABORT_EP9_OUT_BITS 0x00080000 -#define USB_EP_ABORT_EP9_OUT_MSB 19 -#define USB_EP_ABORT_EP9_OUT_LSB 19 +#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_EP9_OUT_LSB _u(19) #define USB_EP_ABORT_EP9_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_IN // Description : None -#define USB_EP_ABORT_EP9_IN_RESET 0x0 -#define USB_EP_ABORT_EP9_IN_BITS 0x00040000 -#define USB_EP_ABORT_EP9_IN_MSB 18 -#define USB_EP_ABORT_EP9_IN_LSB 18 +#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_EP9_IN_LSB _u(18) #define USB_EP_ABORT_EP9_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_OUT // Description : None -#define USB_EP_ABORT_EP8_OUT_RESET 0x0 -#define USB_EP_ABORT_EP8_OUT_BITS 0x00020000 -#define USB_EP_ABORT_EP8_OUT_MSB 17 -#define USB_EP_ABORT_EP8_OUT_LSB 17 +#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_EP8_OUT_LSB _u(17) #define USB_EP_ABORT_EP8_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_IN // Description : None -#define USB_EP_ABORT_EP8_IN_RESET 0x0 -#define USB_EP_ABORT_EP8_IN_BITS 0x00010000 -#define USB_EP_ABORT_EP8_IN_MSB 16 -#define USB_EP_ABORT_EP8_IN_LSB 16 +#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_EP8_IN_LSB _u(16) #define USB_EP_ABORT_EP8_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_OUT // Description : None -#define USB_EP_ABORT_EP7_OUT_RESET 0x0 -#define USB_EP_ABORT_EP7_OUT_BITS 0x00008000 -#define USB_EP_ABORT_EP7_OUT_MSB 15 -#define USB_EP_ABORT_EP7_OUT_LSB 15 +#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_EP7_OUT_LSB _u(15) #define USB_EP_ABORT_EP7_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_IN // Description : None -#define USB_EP_ABORT_EP7_IN_RESET 0x0 -#define USB_EP_ABORT_EP7_IN_BITS 0x00004000 -#define USB_EP_ABORT_EP7_IN_MSB 14 -#define USB_EP_ABORT_EP7_IN_LSB 14 +#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_EP7_IN_LSB _u(14) #define USB_EP_ABORT_EP7_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_OUT // Description : None -#define USB_EP_ABORT_EP6_OUT_RESET 0x0 -#define USB_EP_ABORT_EP6_OUT_BITS 0x00002000 -#define USB_EP_ABORT_EP6_OUT_MSB 13 -#define USB_EP_ABORT_EP6_OUT_LSB 13 +#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_EP6_OUT_LSB _u(13) #define USB_EP_ABORT_EP6_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_IN // Description : None -#define USB_EP_ABORT_EP6_IN_RESET 0x0 -#define USB_EP_ABORT_EP6_IN_BITS 0x00001000 -#define USB_EP_ABORT_EP6_IN_MSB 12 -#define USB_EP_ABORT_EP6_IN_LSB 12 +#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_EP6_IN_LSB _u(12) #define USB_EP_ABORT_EP6_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_OUT // Description : None -#define USB_EP_ABORT_EP5_OUT_RESET 0x0 -#define USB_EP_ABORT_EP5_OUT_BITS 0x00000800 -#define USB_EP_ABORT_EP5_OUT_MSB 11 -#define USB_EP_ABORT_EP5_OUT_LSB 11 +#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_EP5_OUT_LSB _u(11) #define USB_EP_ABORT_EP5_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_IN // Description : None -#define USB_EP_ABORT_EP5_IN_RESET 0x0 -#define USB_EP_ABORT_EP5_IN_BITS 0x00000400 -#define USB_EP_ABORT_EP5_IN_MSB 10 -#define USB_EP_ABORT_EP5_IN_LSB 10 +#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_EP5_IN_LSB _u(10) #define USB_EP_ABORT_EP5_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_OUT // Description : None -#define USB_EP_ABORT_EP4_OUT_RESET 0x0 -#define USB_EP_ABORT_EP4_OUT_BITS 0x00000200 -#define USB_EP_ABORT_EP4_OUT_MSB 9 -#define USB_EP_ABORT_EP4_OUT_LSB 9 +#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_EP4_OUT_LSB _u(9) #define USB_EP_ABORT_EP4_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_IN // Description : None -#define USB_EP_ABORT_EP4_IN_RESET 0x0 -#define USB_EP_ABORT_EP4_IN_BITS 0x00000100 -#define USB_EP_ABORT_EP4_IN_MSB 8 -#define USB_EP_ABORT_EP4_IN_LSB 8 +#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_EP4_IN_LSB _u(8) #define USB_EP_ABORT_EP4_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_OUT // Description : None -#define USB_EP_ABORT_EP3_OUT_RESET 0x0 -#define USB_EP_ABORT_EP3_OUT_BITS 0x00000080 -#define USB_EP_ABORT_EP3_OUT_MSB 7 -#define USB_EP_ABORT_EP3_OUT_LSB 7 +#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_EP3_OUT_LSB _u(7) #define USB_EP_ABORT_EP3_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_IN // Description : None -#define USB_EP_ABORT_EP3_IN_RESET 0x0 -#define USB_EP_ABORT_EP3_IN_BITS 0x00000040 -#define USB_EP_ABORT_EP3_IN_MSB 6 -#define USB_EP_ABORT_EP3_IN_LSB 6 +#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_EP3_IN_LSB _u(6) #define USB_EP_ABORT_EP3_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_OUT // Description : None -#define USB_EP_ABORT_EP2_OUT_RESET 0x0 -#define USB_EP_ABORT_EP2_OUT_BITS 0x00000020 -#define USB_EP_ABORT_EP2_OUT_MSB 5 -#define USB_EP_ABORT_EP2_OUT_LSB 5 +#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_EP2_OUT_LSB _u(5) #define USB_EP_ABORT_EP2_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_IN // Description : None -#define USB_EP_ABORT_EP2_IN_RESET 0x0 -#define USB_EP_ABORT_EP2_IN_BITS 0x00000010 -#define USB_EP_ABORT_EP2_IN_MSB 4 -#define USB_EP_ABORT_EP2_IN_LSB 4 +#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_EP2_IN_LSB _u(4) #define USB_EP_ABORT_EP2_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_OUT // Description : None -#define USB_EP_ABORT_EP1_OUT_RESET 0x0 -#define USB_EP_ABORT_EP1_OUT_BITS 0x00000008 -#define USB_EP_ABORT_EP1_OUT_MSB 3 -#define USB_EP_ABORT_EP1_OUT_LSB 3 +#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_EP1_OUT_LSB _u(3) #define USB_EP_ABORT_EP1_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_IN // Description : None -#define USB_EP_ABORT_EP1_IN_RESET 0x0 -#define USB_EP_ABORT_EP1_IN_BITS 0x00000004 -#define USB_EP_ABORT_EP1_IN_MSB 2 -#define USB_EP_ABORT_EP1_IN_LSB 2 +#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_EP1_IN_LSB _u(2) #define USB_EP_ABORT_EP1_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_OUT // Description : None -#define USB_EP_ABORT_EP0_OUT_RESET 0x0 -#define USB_EP_ABORT_EP0_OUT_BITS 0x00000002 -#define USB_EP_ABORT_EP0_OUT_MSB 1 -#define USB_EP_ABORT_EP0_OUT_LSB 1 +#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_EP0_OUT_LSB _u(1) #define USB_EP_ABORT_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_IN // Description : None -#define USB_EP_ABORT_EP0_IN_RESET 0x0 -#define USB_EP_ABORT_EP0_IN_BITS 0x00000001 -#define USB_EP_ABORT_EP0_IN_MSB 0 -#define USB_EP_ABORT_EP0_IN_LSB 0 +#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_EP0_IN_LSB _u(0) #define USB_EP_ABORT_EP0_IN_ACCESS "RW" // ============================================================================= // Register : USB_EP_ABORT_DONE // Description : Device only: Used in conjunction with `EP_ABORT`. Set once an // endpoint is idle so the programmer knows it is safe to modify // the buffer control register. -#define USB_EP_ABORT_DONE_OFFSET 0x00000064 -#define USB_EP_ABORT_DONE_BITS 0xffffffff -#define USB_EP_ABORT_DONE_RESET 0x00000000 +#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) +#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) +#define USB_EP_ABORT_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_OUT // Description : None -#define USB_EP_ABORT_DONE_EP15_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP15_OUT_BITS 0x80000000 -#define USB_EP_ABORT_DONE_EP15_OUT_MSB 31 -#define USB_EP_ABORT_DONE_EP15_OUT_LSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) #define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_IN // Description : None -#define USB_EP_ABORT_DONE_EP15_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP15_IN_BITS 0x40000000 -#define USB_EP_ABORT_DONE_EP15_IN_MSB 30 -#define USB_EP_ABORT_DONE_EP15_IN_LSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) #define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_OUT // Description : None -#define USB_EP_ABORT_DONE_EP14_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP14_OUT_BITS 0x20000000 -#define USB_EP_ABORT_DONE_EP14_OUT_MSB 29 -#define USB_EP_ABORT_DONE_EP14_OUT_LSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) #define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_IN // Description : None -#define USB_EP_ABORT_DONE_EP14_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP14_IN_BITS 0x10000000 -#define USB_EP_ABORT_DONE_EP14_IN_MSB 28 -#define USB_EP_ABORT_DONE_EP14_IN_LSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) #define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_OUT // Description : None -#define USB_EP_ABORT_DONE_EP13_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP13_OUT_BITS 0x08000000 -#define USB_EP_ABORT_DONE_EP13_OUT_MSB 27 -#define USB_EP_ABORT_DONE_EP13_OUT_LSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) #define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_IN // Description : None -#define USB_EP_ABORT_DONE_EP13_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP13_IN_BITS 0x04000000 -#define USB_EP_ABORT_DONE_EP13_IN_MSB 26 -#define USB_EP_ABORT_DONE_EP13_IN_LSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) #define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_OUT // Description : None -#define USB_EP_ABORT_DONE_EP12_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP12_OUT_BITS 0x02000000 -#define USB_EP_ABORT_DONE_EP12_OUT_MSB 25 -#define USB_EP_ABORT_DONE_EP12_OUT_LSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) #define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_IN // Description : None -#define USB_EP_ABORT_DONE_EP12_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP12_IN_BITS 0x01000000 -#define USB_EP_ABORT_DONE_EP12_IN_MSB 24 -#define USB_EP_ABORT_DONE_EP12_IN_LSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) #define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_OUT // Description : None -#define USB_EP_ABORT_DONE_EP11_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP11_OUT_BITS 0x00800000 -#define USB_EP_ABORT_DONE_EP11_OUT_MSB 23 -#define USB_EP_ABORT_DONE_EP11_OUT_LSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) #define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_IN // Description : None -#define USB_EP_ABORT_DONE_EP11_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP11_IN_BITS 0x00400000 -#define USB_EP_ABORT_DONE_EP11_IN_MSB 22 -#define USB_EP_ABORT_DONE_EP11_IN_LSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) #define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_OUT // Description : None -#define USB_EP_ABORT_DONE_EP10_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP10_OUT_BITS 0x00200000 -#define USB_EP_ABORT_DONE_EP10_OUT_MSB 21 -#define USB_EP_ABORT_DONE_EP10_OUT_LSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) #define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_IN // Description : None -#define USB_EP_ABORT_DONE_EP10_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP10_IN_BITS 0x00100000 -#define USB_EP_ABORT_DONE_EP10_IN_MSB 20 -#define USB_EP_ABORT_DONE_EP10_IN_LSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) #define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_OUT // Description : None -#define USB_EP_ABORT_DONE_EP9_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP9_OUT_BITS 0x00080000 -#define USB_EP_ABORT_DONE_EP9_OUT_MSB 19 -#define USB_EP_ABORT_DONE_EP9_OUT_LSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) #define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_IN // Description : None -#define USB_EP_ABORT_DONE_EP9_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP9_IN_BITS 0x00040000 -#define USB_EP_ABORT_DONE_EP9_IN_MSB 18 -#define USB_EP_ABORT_DONE_EP9_IN_LSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) #define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_OUT // Description : None -#define USB_EP_ABORT_DONE_EP8_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP8_OUT_BITS 0x00020000 -#define USB_EP_ABORT_DONE_EP8_OUT_MSB 17 -#define USB_EP_ABORT_DONE_EP8_OUT_LSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) #define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_IN // Description : None -#define USB_EP_ABORT_DONE_EP8_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP8_IN_BITS 0x00010000 -#define USB_EP_ABORT_DONE_EP8_IN_MSB 16 -#define USB_EP_ABORT_DONE_EP8_IN_LSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) #define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_OUT // Description : None -#define USB_EP_ABORT_DONE_EP7_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP7_OUT_BITS 0x00008000 -#define USB_EP_ABORT_DONE_EP7_OUT_MSB 15 -#define USB_EP_ABORT_DONE_EP7_OUT_LSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) #define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_IN // Description : None -#define USB_EP_ABORT_DONE_EP7_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP7_IN_BITS 0x00004000 -#define USB_EP_ABORT_DONE_EP7_IN_MSB 14 -#define USB_EP_ABORT_DONE_EP7_IN_LSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) #define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_OUT // Description : None -#define USB_EP_ABORT_DONE_EP6_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP6_OUT_BITS 0x00002000 -#define USB_EP_ABORT_DONE_EP6_OUT_MSB 13 -#define USB_EP_ABORT_DONE_EP6_OUT_LSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) #define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_IN // Description : None -#define USB_EP_ABORT_DONE_EP6_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP6_IN_BITS 0x00001000 -#define USB_EP_ABORT_DONE_EP6_IN_MSB 12 -#define USB_EP_ABORT_DONE_EP6_IN_LSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) #define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_OUT // Description : None -#define USB_EP_ABORT_DONE_EP5_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP5_OUT_BITS 0x00000800 -#define USB_EP_ABORT_DONE_EP5_OUT_MSB 11 -#define USB_EP_ABORT_DONE_EP5_OUT_LSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) #define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_IN // Description : None -#define USB_EP_ABORT_DONE_EP5_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP5_IN_BITS 0x00000400 -#define USB_EP_ABORT_DONE_EP5_IN_MSB 10 -#define USB_EP_ABORT_DONE_EP5_IN_LSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) #define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_OUT // Description : None -#define USB_EP_ABORT_DONE_EP4_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP4_OUT_BITS 0x00000200 -#define USB_EP_ABORT_DONE_EP4_OUT_MSB 9 -#define USB_EP_ABORT_DONE_EP4_OUT_LSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) #define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_IN // Description : None -#define USB_EP_ABORT_DONE_EP4_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP4_IN_BITS 0x00000100 -#define USB_EP_ABORT_DONE_EP4_IN_MSB 8 -#define USB_EP_ABORT_DONE_EP4_IN_LSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) #define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_OUT // Description : None -#define USB_EP_ABORT_DONE_EP3_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP3_OUT_BITS 0x00000080 -#define USB_EP_ABORT_DONE_EP3_OUT_MSB 7 -#define USB_EP_ABORT_DONE_EP3_OUT_LSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) #define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_IN // Description : None -#define USB_EP_ABORT_DONE_EP3_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP3_IN_BITS 0x00000040 -#define USB_EP_ABORT_DONE_EP3_IN_MSB 6 -#define USB_EP_ABORT_DONE_EP3_IN_LSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) #define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_OUT // Description : None -#define USB_EP_ABORT_DONE_EP2_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP2_OUT_BITS 0x00000020 -#define USB_EP_ABORT_DONE_EP2_OUT_MSB 5 -#define USB_EP_ABORT_DONE_EP2_OUT_LSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) #define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_IN // Description : None -#define USB_EP_ABORT_DONE_EP2_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP2_IN_BITS 0x00000010 -#define USB_EP_ABORT_DONE_EP2_IN_MSB 4 -#define USB_EP_ABORT_DONE_EP2_IN_LSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) #define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_OUT // Description : None -#define USB_EP_ABORT_DONE_EP1_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP1_OUT_BITS 0x00000008 -#define USB_EP_ABORT_DONE_EP1_OUT_MSB 3 -#define USB_EP_ABORT_DONE_EP1_OUT_LSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) #define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_IN // Description : None -#define USB_EP_ABORT_DONE_EP1_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP1_IN_BITS 0x00000004 -#define USB_EP_ABORT_DONE_EP1_IN_MSB 2 -#define USB_EP_ABORT_DONE_EP1_IN_LSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) #define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_OUT // Description : None -#define USB_EP_ABORT_DONE_EP0_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP0_OUT_BITS 0x00000002 -#define USB_EP_ABORT_DONE_EP0_OUT_MSB 1 -#define USB_EP_ABORT_DONE_EP0_OUT_LSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) #define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_IN // Description : None -#define USB_EP_ABORT_DONE_EP0_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP0_IN_BITS 0x00000001 -#define USB_EP_ABORT_DONE_EP0_IN_MSB 0 -#define USB_EP_ABORT_DONE_EP0_IN_LSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) #define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_EP_STALL_ARM @@ -2146,350 +2146,350 @@ // device controller clears these bits when a SETUP packet is // received because the USB spec requires that a STALL condition // is cleared when a SETUP packet is received. -#define USB_EP_STALL_ARM_OFFSET 0x00000068 -#define USB_EP_STALL_ARM_BITS 0x00000003 -#define USB_EP_STALL_ARM_RESET 0x00000000 +#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) +#define USB_EP_STALL_ARM_BITS _u(0x00000003) +#define USB_EP_STALL_ARM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_OUT // Description : None -#define USB_EP_STALL_ARM_EP0_OUT_RESET 0x0 -#define USB_EP_STALL_ARM_EP0_OUT_BITS 0x00000002 -#define USB_EP_STALL_ARM_EP0_OUT_MSB 1 -#define USB_EP_STALL_ARM_EP0_OUT_LSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) #define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_IN // Description : None -#define USB_EP_STALL_ARM_EP0_IN_RESET 0x0 -#define USB_EP_STALL_ARM_EP0_IN_BITS 0x00000001 -#define USB_EP_STALL_ARM_EP0_IN_MSB 0 -#define USB_EP_STALL_ARM_EP0_IN_LSB 0 +#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) #define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" // ============================================================================= // Register : USB_NAK_POLL // Description : Used by the host controller. Sets the wait time in microseconds // before trying again if the device replies with a NAK. -#define USB_NAK_POLL_OFFSET 0x0000006c -#define USB_NAK_POLL_BITS 0x03ff03ff -#define USB_NAK_POLL_RESET 0x00100010 +#define USB_NAK_POLL_OFFSET _u(0x0000006c) +#define USB_NAK_POLL_BITS _u(0x03ff03ff) +#define USB_NAK_POLL_RESET _u(0x00100010) // ----------------------------------------------------------------------------- // Field : USB_NAK_POLL_DELAY_FS // Description : NAK polling interval for a full speed device -#define USB_NAK_POLL_DELAY_FS_RESET 0x010 -#define USB_NAK_POLL_DELAY_FS_BITS 0x03ff0000 -#define USB_NAK_POLL_DELAY_FS_MSB 25 -#define USB_NAK_POLL_DELAY_FS_LSB 16 +#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) +#define USB_NAK_POLL_DELAY_FS_MSB _u(25) +#define USB_NAK_POLL_DELAY_FS_LSB _u(16) #define USB_NAK_POLL_DELAY_FS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_NAK_POLL_DELAY_LS // Description : NAK polling interval for a low speed device -#define USB_NAK_POLL_DELAY_LS_RESET 0x010 -#define USB_NAK_POLL_DELAY_LS_BITS 0x000003ff -#define USB_NAK_POLL_DELAY_LS_MSB 9 -#define USB_NAK_POLL_DELAY_LS_LSB 0 +#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) +#define USB_NAK_POLL_DELAY_LS_MSB _u(9) +#define USB_NAK_POLL_DELAY_LS_LSB _u(0) #define USB_NAK_POLL_DELAY_LS_ACCESS "RW" // ============================================================================= // Register : USB_EP_STATUS_STALL_NAK // Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` // bits are set. For EP0 this comes from `SIE_CTRL`. For all other // endpoints it comes from the endpoint control register. -#define USB_EP_STATUS_STALL_NAK_OFFSET 0x00000070 -#define USB_EP_STATUS_STALL_NAK_BITS 0xffffffff -#define USB_EP_STATUS_STALL_NAK_RESET 0x00000000 +#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) +#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) +#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS 0x80000000 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB 31 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS 0x40000000 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB 30 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) #define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS 0x20000000 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB 29 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS 0x10000000 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB 28 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) #define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS 0x08000000 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB 27 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS 0x04000000 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB 26 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) #define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS 0x02000000 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB 25 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS 0x01000000 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB 24 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) #define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS 0x00800000 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB 23 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS 0x00400000 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB 22 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) #define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS 0x00200000 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB 21 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS 0x00100000 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB 20 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) #define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS 0x00080000 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB 19 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS 0x00040000 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB 18 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) #define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS 0x00020000 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB 17 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS 0x00010000 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB 16 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) #define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS 0x00008000 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB 15 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS 0x00004000 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB 14 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) #define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS 0x00002000 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB 13 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS 0x00001000 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB 12 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) #define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS 0x00000800 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB 11 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS 0x00000400 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB 10 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) #define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS 0x00000200 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB 9 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS 0x00000100 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB 8 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) #define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS 0x00000080 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB 7 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS 0x00000040 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB 6 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) #define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS 0x00000020 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB 5 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS 0x00000010 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB 4 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) #define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS 0x00000008 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB 3 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS 0x00000004 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB 2 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) #define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS 0x00000002 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB 1 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS 0x00000001 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB 0 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) #define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_USB_MUXING // Description : Where to connect the USB controller. Should be to_phy by // default. -#define USB_USB_MUXING_OFFSET 0x00000074 -#define USB_USB_MUXING_BITS 0x0000000f -#define USB_USB_MUXING_RESET 0x00000000 +#define USB_USB_MUXING_OFFSET _u(0x00000074) +#define USB_USB_MUXING_BITS _u(0x0000000f) +#define USB_USB_MUXING_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_SOFTCON // Description : None -#define USB_USB_MUXING_SOFTCON_RESET 0x0 -#define USB_USB_MUXING_SOFTCON_BITS 0x00000008 -#define USB_USB_MUXING_SOFTCON_MSB 3 -#define USB_USB_MUXING_SOFTCON_LSB 3 +#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) +#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) +#define USB_USB_MUXING_SOFTCON_MSB _u(3) +#define USB_USB_MUXING_SOFTCON_LSB _u(3) #define USB_USB_MUXING_SOFTCON_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_DIGITAL_PAD // Description : None -#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET 0x0 -#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS 0x00000004 -#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB 2 -#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) #define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_EXTPHY // Description : None -#define USB_USB_MUXING_TO_EXTPHY_RESET 0x0 -#define USB_USB_MUXING_TO_EXTPHY_BITS 0x00000002 -#define USB_USB_MUXING_TO_EXTPHY_MSB 1 -#define USB_USB_MUXING_TO_EXTPHY_LSB 1 +#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) +#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) #define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_PHY // Description : None -#define USB_USB_MUXING_TO_PHY_RESET 0x0 -#define USB_USB_MUXING_TO_PHY_BITS 0x00000001 -#define USB_USB_MUXING_TO_PHY_MSB 0 -#define USB_USB_MUXING_TO_PHY_LSB 0 +#define USB_USB_MUXING_TO_PHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) +#define USB_USB_MUXING_TO_PHY_MSB _u(0) +#define USB_USB_MUXING_TO_PHY_LSB _u(0) #define USB_USB_MUXING_TO_PHY_ACCESS "RW" // ============================================================================= // Register : USB_USB_PWR @@ -2497,167 +2497,167 @@ // signals are not hooked up to GPIO. Set the value of the // override and then the override enable to switch over to the // override value. -#define USB_USB_PWR_OFFSET 0x00000078 -#define USB_USB_PWR_BITS 0x0000003f -#define USB_USB_PWR_RESET 0x00000000 +#define USB_USB_PWR_OFFSET _u(0x00000078) +#define USB_USB_PWR_BITS _u(0x0000003f) +#define USB_USB_PWR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT_EN // Description : None -#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET 0x0 -#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS 0x00000020 -#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB 5 -#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) #define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT // Description : None -#define USB_USB_PWR_OVERCURR_DETECT_RESET 0x0 -#define USB_USB_PWR_OVERCURR_DETECT_BITS 0x00000010 -#define USB_USB_PWR_OVERCURR_DETECT_MSB 4 -#define USB_USB_PWR_OVERCURR_DETECT_LSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) +#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) #define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN // Description : None -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS 0x00000008 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB 3 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT // Description : None -#define USB_USB_PWR_VBUS_DETECT_RESET 0x0 -#define USB_USB_PWR_VBUS_DETECT_BITS 0x00000004 -#define USB_USB_PWR_VBUS_DETECT_MSB 2 -#define USB_USB_PWR_VBUS_DETECT_LSB 2 +#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) +#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) #define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN // Description : None -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS 0x00000002 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB 1 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN // Description : None -#define USB_USB_PWR_VBUS_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_EN_BITS 0x00000001 -#define USB_USB_PWR_VBUS_EN_MSB 0 -#define USB_USB_PWR_VBUS_EN_LSB 0 +#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) +#define USB_USB_PWR_VBUS_EN_MSB _u(0) +#define USB_USB_PWR_VBUS_EN_LSB _u(0) #define USB_USB_PWR_VBUS_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT // Description : This register allows for direct control of the USB phy. Use in // conjunction with usbphy_direct_override register to enable each // override bit. -#define USB_USBPHY_DIRECT_OFFSET 0x0000007c -#define USB_USBPHY_DIRECT_BITS 0x007fff77 -#define USB_USBPHY_DIRECT_RESET 0x00000000 +#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) +#define USB_USBPHY_DIRECT_BITS _u(0x007fff77) +#define USB_USBPHY_DIRECT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVV // Description : DM over voltage -#define USB_USBPHY_DIRECT_DM_OVV_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_OVV_BITS 0x00400000 -#define USB_USBPHY_DIRECT_DM_OVV_MSB 22 -#define USB_USBPHY_DIRECT_DM_OVV_LSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) +#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVV // Description : DP over voltage -#define USB_USBPHY_DIRECT_DP_OVV_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_OVV_BITS 0x00200000 -#define USB_USBPHY_DIRECT_DP_OVV_MSB 21 -#define USB_USBPHY_DIRECT_DP_OVV_LSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) +#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVCN // Description : DM overcurrent -#define USB_USBPHY_DIRECT_DM_OVCN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_OVCN_BITS 0x00100000 -#define USB_USBPHY_DIRECT_DM_OVCN_MSB 20 -#define USB_USBPHY_DIRECT_DM_OVCN_LSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) +#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVCN // Description : DP overcurrent -#define USB_USBPHY_DIRECT_DP_OVCN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_OVCN_BITS 0x00080000 -#define USB_USBPHY_DIRECT_DP_OVCN_MSB 19 -#define USB_USBPHY_DIRECT_DP_OVCN_LSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) +#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DM // Description : DPM pin state -#define USB_USBPHY_DIRECT_RX_DM_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DM_BITS 0x00040000 -#define USB_USBPHY_DIRECT_RX_DM_MSB 18 -#define USB_USBPHY_DIRECT_RX_DM_LSB 18 +#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DP // Description : DPP pin state -#define USB_USBPHY_DIRECT_RX_DP_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DP_BITS 0x00020000 -#define USB_USBPHY_DIRECT_RX_DP_MSB 17 -#define USB_USBPHY_DIRECT_RX_DP_LSB 17 +#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DD // Description : Differential RX -#define USB_USBPHY_DIRECT_RX_DD_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DD_BITS 0x00010000 -#define USB_USBPHY_DIRECT_RX_DD_MSB 16 -#define USB_USBPHY_DIRECT_RX_DD_LSB 16 +#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DIFFMODE // Description : TX_DIFFMODE=0: Single ended mode // TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE // ignored) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS 0x00008000 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB 15 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_FSSLEW // Description : TX_FSSLEW=0: Low speed slew rate // TX_FSSLEW=1: Full speed slew rate -#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS 0x00004000 -#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB 14 -#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_PD // Description : TX power down override (if override enable is set). 1 = powered // down. -#define USB_USBPHY_DIRECT_TX_PD_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_PD_BITS 0x00002000 -#define USB_USBPHY_DIRECT_TX_PD_MSB 13 -#define USB_USBPHY_DIRECT_TX_PD_LSB 13 +#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) +#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_PD // Description : RX power down override (if override enable is set). 1 = powered // down. -#define USB_USBPHY_DIRECT_RX_PD_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_PD_BITS 0x00001000 -#define USB_USBPHY_DIRECT_RX_PD_MSB 12 -#define USB_USBPHY_DIRECT_RX_PD_LSB 12 +#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM // Description : Output data. TX_DIFFMODE=1, Ignored // TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. // DPM=TX_DM -#define USB_USBPHY_DIRECT_TX_DM_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DM_BITS 0x00000800 -#define USB_USBPHY_DIRECT_TX_DM_MSB 11 -#define USB_USBPHY_DIRECT_TX_DM_LSB 11 +#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP @@ -2665,20 +2665,20 @@ // TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP // If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. // DPP=TX_DP -#define USB_USBPHY_DIRECT_TX_DP_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DP_BITS 0x00000400 -#define USB_USBPHY_DIRECT_TX_DP_MSB 10 -#define USB_USBPHY_DIRECT_TX_DP_LSB 10 +#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM_OE // Description : Output enable. If TX_DIFFMODE=1, Ignored. // If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - // DPM driving -#define USB_USBPHY_DIRECT_TX_DM_OE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DM_OE_BITS 0x00000200 -#define USB_USBPHY_DIRECT_TX_DM_OE_MSB 9 -#define USB_USBPHY_DIRECT_TX_DM_OE_LSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP_OE @@ -2686,195 +2686,195 @@ // DPP/DPM in Hi-Z state; 1 - DPP/DPM driving // If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - // DPP driving -#define USB_USBPHY_DIRECT_TX_DP_OE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DP_OE_BITS 0x00000100 -#define USB_USBPHY_DIRECT_TX_DP_OE_MSB 8 -#define USB_USBPHY_DIRECT_TX_DP_OE_LSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLDN_EN // Description : DM pull down enable -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS 0x00000040 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB 6 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_EN // Description : DM pull up enable -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS 0x00000020 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB 5 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL // Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - // Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS 0x00000010 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB 4 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLDN_EN // Description : DP pull down enable -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS 0x00000004 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB 2 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_EN // Description : DP pull up enable -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS 0x00000002 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB 1 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL // Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - // Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS 0x00000001 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB 0 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT_OVERRIDE // Description : Override enable for each control in usbphy_direct -#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET 0x00000080 -#define USB_USBPHY_DIRECT_OVERRIDE_BITS 0x00009fff -#define USB_USBPHY_DIRECT_OVERRIDE_RESET 0x00000000 +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) +#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS 0x00008000 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB 15 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS 0x00001000 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB 12 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS 0x00000800 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB 11 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS 0x00000400 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB 10 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS 0x00000200 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB 9 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS 0x00000100 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB 8 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS 0x00000080 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB 7 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS 0x00000040 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB 6 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS 0x00000020 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB 5 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS 0x00000010 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB 4 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS 0x00000008 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB 3 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS 0x00000004 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB 2 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000002 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB 1 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000001 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB 0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_TRIM // Description : Used to adjust trim values of USB phy pull down resistors. -#define USB_USBPHY_TRIM_OFFSET 0x00000084 -#define USB_USBPHY_TRIM_BITS 0x00001f1f -#define USB_USBPHY_TRIM_RESET 0x00001f1f +#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) +#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) +#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM // Description : Value to drive to USB PHY // DM pulldown resistor trim control // Experimental data suggests that the reset value will work, but // this register allows adjustment if required -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET 0x1f -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS 0x00001f00 -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB 12 -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB 8 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM @@ -2882,722 +2882,722 @@ // DP pulldown resistor trim control // Experimental data suggests that the reset value will work, but // this register allows adjustment if required -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET 0x1f -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS 0x0000001f -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB 4 -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB 0 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" // ============================================================================= // Register : USB_INTR // Description : Raw Interrupts -#define USB_INTR_OFFSET 0x0000008c -#define USB_INTR_BITS 0x000fffff -#define USB_INTR_RESET 0x00000000 +#define USB_INTR_OFFSET _u(0x0000008c) +#define USB_INTR_BITS _u(0x000fffff) +#define USB_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTR_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTR_EP_STALL_NAK_RESET 0x0 -#define USB_INTR_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTR_EP_STALL_NAK_MSB 19 -#define USB_INTR_EP_STALL_NAK_LSB 19 +#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTR_EP_STALL_NAK_MSB _u(19) +#define USB_INTR_EP_STALL_NAK_LSB _u(19) #define USB_INTR_EP_STALL_NAK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTR_ABORT_DONE_RESET 0x0 -#define USB_INTR_ABORT_DONE_BITS 0x00040000 -#define USB_INTR_ABORT_DONE_MSB 18 -#define USB_INTR_ABORT_DONE_LSB 18 +#define USB_INTR_ABORT_DONE_RESET _u(0x0) +#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTR_ABORT_DONE_MSB _u(18) +#define USB_INTR_ABORT_DONE_LSB _u(18) #define USB_INTR_ABORT_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTR_DEV_SOF_RESET 0x0 -#define USB_INTR_DEV_SOF_BITS 0x00020000 -#define USB_INTR_DEV_SOF_MSB 17 -#define USB_INTR_DEV_SOF_LSB 17 +#define USB_INTR_DEV_SOF_RESET _u(0x0) +#define USB_INTR_DEV_SOF_BITS _u(0x00020000) +#define USB_INTR_DEV_SOF_MSB _u(17) +#define USB_INTR_DEV_SOF_LSB _u(17) #define USB_INTR_DEV_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTR_SETUP_REQ_RESET 0x0 -#define USB_INTR_SETUP_REQ_BITS 0x00010000 -#define USB_INTR_SETUP_REQ_MSB 16 -#define USB_INTR_SETUP_REQ_LSB 16 +#define USB_INTR_SETUP_REQ_RESET _u(0x0) +#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTR_SETUP_REQ_MSB _u(16) +#define USB_INTR_SETUP_REQ_LSB _u(16) #define USB_INTR_SETUP_REQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTR_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTR_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTR_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTR_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTR_DEV_SUSPEND_RESET 0x0 -#define USB_INTR_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTR_DEV_SUSPEND_MSB 14 -#define USB_INTR_DEV_SUSPEND_LSB 14 +#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTR_DEV_SUSPEND_MSB _u(14) +#define USB_INTR_DEV_SUSPEND_LSB _u(14) #define USB_INTR_DEV_SUSPEND_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTR_DEV_CONN_DIS_RESET 0x0 -#define USB_INTR_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTR_DEV_CONN_DIS_MSB 13 -#define USB_INTR_DEV_CONN_DIS_LSB 13 +#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTR_DEV_CONN_DIS_MSB _u(13) +#define USB_INTR_DEV_CONN_DIS_LSB _u(13) #define USB_INTR_DEV_CONN_DIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTR_BUS_RESET_RESET 0x0 -#define USB_INTR_BUS_RESET_BITS 0x00001000 -#define USB_INTR_BUS_RESET_MSB 12 -#define USB_INTR_BUS_RESET_LSB 12 +#define USB_INTR_BUS_RESET_RESET _u(0x0) +#define USB_INTR_BUS_RESET_BITS _u(0x00001000) +#define USB_INTR_BUS_RESET_MSB _u(12) +#define USB_INTR_BUS_RESET_LSB _u(12) #define USB_INTR_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTR_VBUS_DETECT_RESET 0x0 -#define USB_INTR_VBUS_DETECT_BITS 0x00000800 -#define USB_INTR_VBUS_DETECT_MSB 11 -#define USB_INTR_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTR_VBUS_DETECT_RESET _u(0x0) +#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTR_VBUS_DETECT_MSB _u(11) +#define USB_INTR_VBUS_DETECT_LSB _u(11) #define USB_INTR_VBUS_DETECT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTR_STALL_RESET 0x0 -#define USB_INTR_STALL_BITS 0x00000400 -#define USB_INTR_STALL_MSB 10 -#define USB_INTR_STALL_LSB 10 +#define USB_INTR_STALL_RESET _u(0x0) +#define USB_INTR_STALL_BITS _u(0x00000400) +#define USB_INTR_STALL_MSB _u(10) +#define USB_INTR_STALL_LSB _u(10) #define USB_INTR_STALL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTR_ERROR_CRC_RESET 0x0 -#define USB_INTR_ERROR_CRC_BITS 0x00000200 -#define USB_INTR_ERROR_CRC_MSB 9 -#define USB_INTR_ERROR_CRC_LSB 9 +#define USB_INTR_ERROR_CRC_RESET _u(0x0) +#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTR_ERROR_CRC_MSB _u(9) +#define USB_INTR_ERROR_CRC_LSB _u(9) #define USB_INTR_ERROR_CRC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTR_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTR_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTR_ERROR_BIT_STUFF_MSB 8 -#define USB_INTR_ERROR_BIT_STUFF_LSB 8 +#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTR_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTR_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTR_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTR_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTR_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTR_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTR_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTR_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTR_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTR_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTR_ERROR_DATA_SEQ_MSB 5 -#define USB_INTR_ERROR_DATA_SEQ_LSB 5 +#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTR_BUFF_STATUS_RESET 0x0 -#define USB_INTR_BUFF_STATUS_BITS 0x00000010 -#define USB_INTR_BUFF_STATUS_MSB 4 -#define USB_INTR_BUFF_STATUS_LSB 4 +#define USB_INTR_BUFF_STATUS_RESET _u(0x0) +#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTR_BUFF_STATUS_MSB _u(4) +#define USB_INTR_BUFF_STATUS_LSB _u(4) #define USB_INTR_BUFF_STATUS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTR_TRANS_COMPLETE_RESET 0x0 -#define USB_INTR_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTR_TRANS_COMPLETE_MSB 3 -#define USB_INTR_TRANS_COMPLETE_LSB 3 +#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTR_TRANS_COMPLETE_MSB _u(3) +#define USB_INTR_TRANS_COMPLETE_LSB _u(3) #define USB_INTR_TRANS_COMPLETE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTR_HOST_SOF_RESET 0x0 -#define USB_INTR_HOST_SOF_BITS 0x00000004 -#define USB_INTR_HOST_SOF_MSB 2 -#define USB_INTR_HOST_SOF_LSB 2 +#define USB_INTR_HOST_SOF_RESET _u(0x0) +#define USB_INTR_HOST_SOF_BITS _u(0x00000004) +#define USB_INTR_HOST_SOF_MSB _u(2) +#define USB_INTR_HOST_SOF_LSB _u(2) #define USB_INTR_HOST_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTR_HOST_RESUME_RESET 0x0 -#define USB_INTR_HOST_RESUME_BITS 0x00000002 -#define USB_INTR_HOST_RESUME_MSB 1 -#define USB_INTR_HOST_RESUME_LSB 1 +#define USB_INTR_HOST_RESUME_RESET _u(0x0) +#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTR_HOST_RESUME_MSB _u(1) +#define USB_INTR_HOST_RESUME_LSB _u(1) #define USB_INTR_HOST_RESUME_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTR_HOST_CONN_DIS_RESET 0x0 -#define USB_INTR_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTR_HOST_CONN_DIS_MSB 0 -#define USB_INTR_HOST_CONN_DIS_LSB 0 +#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTR_HOST_CONN_DIS_MSB _u(0) +#define USB_INTR_HOST_CONN_DIS_LSB _u(0) #define USB_INTR_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= // Register : USB_INTE // Description : Interrupt Enable -#define USB_INTE_OFFSET 0x00000090 -#define USB_INTE_BITS 0x000fffff -#define USB_INTE_RESET 0x00000000 +#define USB_INTE_OFFSET _u(0x00000090) +#define USB_INTE_BITS _u(0x000fffff) +#define USB_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTE_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTE_EP_STALL_NAK_RESET 0x0 -#define USB_INTE_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTE_EP_STALL_NAK_MSB 19 -#define USB_INTE_EP_STALL_NAK_LSB 19 +#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTE_EP_STALL_NAK_MSB _u(19) +#define USB_INTE_EP_STALL_NAK_LSB _u(19) #define USB_INTE_EP_STALL_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTE_ABORT_DONE_RESET 0x0 -#define USB_INTE_ABORT_DONE_BITS 0x00040000 -#define USB_INTE_ABORT_DONE_MSB 18 -#define USB_INTE_ABORT_DONE_LSB 18 +#define USB_INTE_ABORT_DONE_RESET _u(0x0) +#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTE_ABORT_DONE_MSB _u(18) +#define USB_INTE_ABORT_DONE_LSB _u(18) #define USB_INTE_ABORT_DONE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTE_DEV_SOF_RESET 0x0 -#define USB_INTE_DEV_SOF_BITS 0x00020000 -#define USB_INTE_DEV_SOF_MSB 17 -#define USB_INTE_DEV_SOF_LSB 17 +#define USB_INTE_DEV_SOF_RESET _u(0x0) +#define USB_INTE_DEV_SOF_BITS _u(0x00020000) +#define USB_INTE_DEV_SOF_MSB _u(17) +#define USB_INTE_DEV_SOF_LSB _u(17) #define USB_INTE_DEV_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTE_SETUP_REQ_RESET 0x0 -#define USB_INTE_SETUP_REQ_BITS 0x00010000 -#define USB_INTE_SETUP_REQ_MSB 16 -#define USB_INTE_SETUP_REQ_LSB 16 +#define USB_INTE_SETUP_REQ_RESET _u(0x0) +#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTE_SETUP_REQ_MSB _u(16) +#define USB_INTE_SETUP_REQ_LSB _u(16) #define USB_INTE_SETUP_REQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTE_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTE_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTE_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTE_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTE_DEV_SUSPEND_RESET 0x0 -#define USB_INTE_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTE_DEV_SUSPEND_MSB 14 -#define USB_INTE_DEV_SUSPEND_LSB 14 +#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTE_DEV_SUSPEND_MSB _u(14) +#define USB_INTE_DEV_SUSPEND_LSB _u(14) #define USB_INTE_DEV_SUSPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTE_DEV_CONN_DIS_RESET 0x0 -#define USB_INTE_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTE_DEV_CONN_DIS_MSB 13 -#define USB_INTE_DEV_CONN_DIS_LSB 13 +#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTE_DEV_CONN_DIS_MSB _u(13) +#define USB_INTE_DEV_CONN_DIS_LSB _u(13) #define USB_INTE_DEV_CONN_DIS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTE_BUS_RESET_RESET 0x0 -#define USB_INTE_BUS_RESET_BITS 0x00001000 -#define USB_INTE_BUS_RESET_MSB 12 -#define USB_INTE_BUS_RESET_LSB 12 +#define USB_INTE_BUS_RESET_RESET _u(0x0) +#define USB_INTE_BUS_RESET_BITS _u(0x00001000) +#define USB_INTE_BUS_RESET_MSB _u(12) +#define USB_INTE_BUS_RESET_LSB _u(12) #define USB_INTE_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTE_VBUS_DETECT_RESET 0x0 -#define USB_INTE_VBUS_DETECT_BITS 0x00000800 -#define USB_INTE_VBUS_DETECT_MSB 11 -#define USB_INTE_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTE_VBUS_DETECT_RESET _u(0x0) +#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTE_VBUS_DETECT_MSB _u(11) +#define USB_INTE_VBUS_DETECT_LSB _u(11) #define USB_INTE_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTE_STALL_RESET 0x0 -#define USB_INTE_STALL_BITS 0x00000400 -#define USB_INTE_STALL_MSB 10 -#define USB_INTE_STALL_LSB 10 +#define USB_INTE_STALL_RESET _u(0x0) +#define USB_INTE_STALL_BITS _u(0x00000400) +#define USB_INTE_STALL_MSB _u(10) +#define USB_INTE_STALL_LSB _u(10) #define USB_INTE_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTE_ERROR_CRC_RESET 0x0 -#define USB_INTE_ERROR_CRC_BITS 0x00000200 -#define USB_INTE_ERROR_CRC_MSB 9 -#define USB_INTE_ERROR_CRC_LSB 9 +#define USB_INTE_ERROR_CRC_RESET _u(0x0) +#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTE_ERROR_CRC_MSB _u(9) +#define USB_INTE_ERROR_CRC_LSB _u(9) #define USB_INTE_ERROR_CRC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTE_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTE_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTE_ERROR_BIT_STUFF_MSB 8 -#define USB_INTE_ERROR_BIT_STUFF_LSB 8 +#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTE_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTE_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTE_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTE_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTE_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTE_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTE_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTE_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTE_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTE_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTE_ERROR_DATA_SEQ_MSB 5 -#define USB_INTE_ERROR_DATA_SEQ_LSB 5 +#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTE_BUFF_STATUS_RESET 0x0 -#define USB_INTE_BUFF_STATUS_BITS 0x00000010 -#define USB_INTE_BUFF_STATUS_MSB 4 -#define USB_INTE_BUFF_STATUS_LSB 4 +#define USB_INTE_BUFF_STATUS_RESET _u(0x0) +#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTE_BUFF_STATUS_MSB _u(4) +#define USB_INTE_BUFF_STATUS_LSB _u(4) #define USB_INTE_BUFF_STATUS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTE_TRANS_COMPLETE_RESET 0x0 -#define USB_INTE_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTE_TRANS_COMPLETE_MSB 3 -#define USB_INTE_TRANS_COMPLETE_LSB 3 +#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTE_TRANS_COMPLETE_MSB _u(3) +#define USB_INTE_TRANS_COMPLETE_LSB _u(3) #define USB_INTE_TRANS_COMPLETE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTE_HOST_SOF_RESET 0x0 -#define USB_INTE_HOST_SOF_BITS 0x00000004 -#define USB_INTE_HOST_SOF_MSB 2 -#define USB_INTE_HOST_SOF_LSB 2 +#define USB_INTE_HOST_SOF_RESET _u(0x0) +#define USB_INTE_HOST_SOF_BITS _u(0x00000004) +#define USB_INTE_HOST_SOF_MSB _u(2) +#define USB_INTE_HOST_SOF_LSB _u(2) #define USB_INTE_HOST_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTE_HOST_RESUME_RESET 0x0 -#define USB_INTE_HOST_RESUME_BITS 0x00000002 -#define USB_INTE_HOST_RESUME_MSB 1 -#define USB_INTE_HOST_RESUME_LSB 1 +#define USB_INTE_HOST_RESUME_RESET _u(0x0) +#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTE_HOST_RESUME_MSB _u(1) +#define USB_INTE_HOST_RESUME_LSB _u(1) #define USB_INTE_HOST_RESUME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTE_HOST_CONN_DIS_RESET 0x0 -#define USB_INTE_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTE_HOST_CONN_DIS_MSB 0 -#define USB_INTE_HOST_CONN_DIS_LSB 0 +#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTE_HOST_CONN_DIS_MSB _u(0) +#define USB_INTE_HOST_CONN_DIS_LSB _u(0) #define USB_INTE_HOST_CONN_DIS_ACCESS "RW" // ============================================================================= // Register : USB_INTF // Description : Interrupt Force -#define USB_INTF_OFFSET 0x00000094 -#define USB_INTF_BITS 0x000fffff -#define USB_INTF_RESET 0x00000000 +#define USB_INTF_OFFSET _u(0x00000094) +#define USB_INTF_BITS _u(0x000fffff) +#define USB_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTF_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTF_EP_STALL_NAK_RESET 0x0 -#define USB_INTF_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTF_EP_STALL_NAK_MSB 19 -#define USB_INTF_EP_STALL_NAK_LSB 19 +#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTF_EP_STALL_NAK_MSB _u(19) +#define USB_INTF_EP_STALL_NAK_LSB _u(19) #define USB_INTF_EP_STALL_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTF_ABORT_DONE_RESET 0x0 -#define USB_INTF_ABORT_DONE_BITS 0x00040000 -#define USB_INTF_ABORT_DONE_MSB 18 -#define USB_INTF_ABORT_DONE_LSB 18 +#define USB_INTF_ABORT_DONE_RESET _u(0x0) +#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTF_ABORT_DONE_MSB _u(18) +#define USB_INTF_ABORT_DONE_LSB _u(18) #define USB_INTF_ABORT_DONE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTF_DEV_SOF_RESET 0x0 -#define USB_INTF_DEV_SOF_BITS 0x00020000 -#define USB_INTF_DEV_SOF_MSB 17 -#define USB_INTF_DEV_SOF_LSB 17 +#define USB_INTF_DEV_SOF_RESET _u(0x0) +#define USB_INTF_DEV_SOF_BITS _u(0x00020000) +#define USB_INTF_DEV_SOF_MSB _u(17) +#define USB_INTF_DEV_SOF_LSB _u(17) #define USB_INTF_DEV_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTF_SETUP_REQ_RESET 0x0 -#define USB_INTF_SETUP_REQ_BITS 0x00010000 -#define USB_INTF_SETUP_REQ_MSB 16 -#define USB_INTF_SETUP_REQ_LSB 16 +#define USB_INTF_SETUP_REQ_RESET _u(0x0) +#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTF_SETUP_REQ_MSB _u(16) +#define USB_INTF_SETUP_REQ_LSB _u(16) #define USB_INTF_SETUP_REQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTF_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTF_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTF_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTF_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTF_DEV_SUSPEND_RESET 0x0 -#define USB_INTF_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTF_DEV_SUSPEND_MSB 14 -#define USB_INTF_DEV_SUSPEND_LSB 14 +#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTF_DEV_SUSPEND_MSB _u(14) +#define USB_INTF_DEV_SUSPEND_LSB _u(14) #define USB_INTF_DEV_SUSPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTF_DEV_CONN_DIS_RESET 0x0 -#define USB_INTF_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTF_DEV_CONN_DIS_MSB 13 -#define USB_INTF_DEV_CONN_DIS_LSB 13 +#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTF_DEV_CONN_DIS_MSB _u(13) +#define USB_INTF_DEV_CONN_DIS_LSB _u(13) #define USB_INTF_DEV_CONN_DIS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTF_BUS_RESET_RESET 0x0 -#define USB_INTF_BUS_RESET_BITS 0x00001000 -#define USB_INTF_BUS_RESET_MSB 12 -#define USB_INTF_BUS_RESET_LSB 12 +#define USB_INTF_BUS_RESET_RESET _u(0x0) +#define USB_INTF_BUS_RESET_BITS _u(0x00001000) +#define USB_INTF_BUS_RESET_MSB _u(12) +#define USB_INTF_BUS_RESET_LSB _u(12) #define USB_INTF_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTF_VBUS_DETECT_RESET 0x0 -#define USB_INTF_VBUS_DETECT_BITS 0x00000800 -#define USB_INTF_VBUS_DETECT_MSB 11 -#define USB_INTF_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTF_VBUS_DETECT_RESET _u(0x0) +#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTF_VBUS_DETECT_MSB _u(11) +#define USB_INTF_VBUS_DETECT_LSB _u(11) #define USB_INTF_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTF_STALL_RESET 0x0 -#define USB_INTF_STALL_BITS 0x00000400 -#define USB_INTF_STALL_MSB 10 -#define USB_INTF_STALL_LSB 10 +#define USB_INTF_STALL_RESET _u(0x0) +#define USB_INTF_STALL_BITS _u(0x00000400) +#define USB_INTF_STALL_MSB _u(10) +#define USB_INTF_STALL_LSB _u(10) #define USB_INTF_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTF_ERROR_CRC_RESET 0x0 -#define USB_INTF_ERROR_CRC_BITS 0x00000200 -#define USB_INTF_ERROR_CRC_MSB 9 -#define USB_INTF_ERROR_CRC_LSB 9 +#define USB_INTF_ERROR_CRC_RESET _u(0x0) +#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTF_ERROR_CRC_MSB _u(9) +#define USB_INTF_ERROR_CRC_LSB _u(9) #define USB_INTF_ERROR_CRC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTF_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTF_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTF_ERROR_BIT_STUFF_MSB 8 -#define USB_INTF_ERROR_BIT_STUFF_LSB 8 +#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTF_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTF_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTF_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTF_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTF_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTF_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTF_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTF_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTF_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTF_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTF_ERROR_DATA_SEQ_MSB 5 -#define USB_INTF_ERROR_DATA_SEQ_LSB 5 +#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTF_BUFF_STATUS_RESET 0x0 -#define USB_INTF_BUFF_STATUS_BITS 0x00000010 -#define USB_INTF_BUFF_STATUS_MSB 4 -#define USB_INTF_BUFF_STATUS_LSB 4 +#define USB_INTF_BUFF_STATUS_RESET _u(0x0) +#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTF_BUFF_STATUS_MSB _u(4) +#define USB_INTF_BUFF_STATUS_LSB _u(4) #define USB_INTF_BUFF_STATUS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTF_TRANS_COMPLETE_RESET 0x0 -#define USB_INTF_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTF_TRANS_COMPLETE_MSB 3 -#define USB_INTF_TRANS_COMPLETE_LSB 3 +#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTF_TRANS_COMPLETE_MSB _u(3) +#define USB_INTF_TRANS_COMPLETE_LSB _u(3) #define USB_INTF_TRANS_COMPLETE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTF_HOST_SOF_RESET 0x0 -#define USB_INTF_HOST_SOF_BITS 0x00000004 -#define USB_INTF_HOST_SOF_MSB 2 -#define USB_INTF_HOST_SOF_LSB 2 +#define USB_INTF_HOST_SOF_RESET _u(0x0) +#define USB_INTF_HOST_SOF_BITS _u(0x00000004) +#define USB_INTF_HOST_SOF_MSB _u(2) +#define USB_INTF_HOST_SOF_LSB _u(2) #define USB_INTF_HOST_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTF_HOST_RESUME_RESET 0x0 -#define USB_INTF_HOST_RESUME_BITS 0x00000002 -#define USB_INTF_HOST_RESUME_MSB 1 -#define USB_INTF_HOST_RESUME_LSB 1 +#define USB_INTF_HOST_RESUME_RESET _u(0x0) +#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTF_HOST_RESUME_MSB _u(1) +#define USB_INTF_HOST_RESUME_LSB _u(1) #define USB_INTF_HOST_RESUME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTF_HOST_CONN_DIS_RESET 0x0 -#define USB_INTF_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTF_HOST_CONN_DIS_MSB 0 -#define USB_INTF_HOST_CONN_DIS_LSB 0 +#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTF_HOST_CONN_DIS_MSB _u(0) +#define USB_INTF_HOST_CONN_DIS_LSB _u(0) #define USB_INTF_HOST_CONN_DIS_ACCESS "RW" // ============================================================================= // Register : USB_INTS // Description : Interrupt status after masking & forcing -#define USB_INTS_OFFSET 0x00000098 -#define USB_INTS_BITS 0x000fffff -#define USB_INTS_RESET 0x00000000 +#define USB_INTS_OFFSET _u(0x00000098) +#define USB_INTS_BITS _u(0x000fffff) +#define USB_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTS_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTS_EP_STALL_NAK_RESET 0x0 -#define USB_INTS_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTS_EP_STALL_NAK_MSB 19 -#define USB_INTS_EP_STALL_NAK_LSB 19 +#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTS_EP_STALL_NAK_MSB _u(19) +#define USB_INTS_EP_STALL_NAK_LSB _u(19) #define USB_INTS_EP_STALL_NAK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTS_ABORT_DONE_RESET 0x0 -#define USB_INTS_ABORT_DONE_BITS 0x00040000 -#define USB_INTS_ABORT_DONE_MSB 18 -#define USB_INTS_ABORT_DONE_LSB 18 +#define USB_INTS_ABORT_DONE_RESET _u(0x0) +#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTS_ABORT_DONE_MSB _u(18) +#define USB_INTS_ABORT_DONE_LSB _u(18) #define USB_INTS_ABORT_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTS_DEV_SOF_RESET 0x0 -#define USB_INTS_DEV_SOF_BITS 0x00020000 -#define USB_INTS_DEV_SOF_MSB 17 -#define USB_INTS_DEV_SOF_LSB 17 +#define USB_INTS_DEV_SOF_RESET _u(0x0) +#define USB_INTS_DEV_SOF_BITS _u(0x00020000) +#define USB_INTS_DEV_SOF_MSB _u(17) +#define USB_INTS_DEV_SOF_LSB _u(17) #define USB_INTS_DEV_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTS_SETUP_REQ_RESET 0x0 -#define USB_INTS_SETUP_REQ_BITS 0x00010000 -#define USB_INTS_SETUP_REQ_MSB 16 -#define USB_INTS_SETUP_REQ_LSB 16 +#define USB_INTS_SETUP_REQ_RESET _u(0x0) +#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTS_SETUP_REQ_MSB _u(16) +#define USB_INTS_SETUP_REQ_LSB _u(16) #define USB_INTS_SETUP_REQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTS_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTS_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTS_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTS_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTS_DEV_SUSPEND_RESET 0x0 -#define USB_INTS_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTS_DEV_SUSPEND_MSB 14 -#define USB_INTS_DEV_SUSPEND_LSB 14 +#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTS_DEV_SUSPEND_MSB _u(14) +#define USB_INTS_DEV_SUSPEND_LSB _u(14) #define USB_INTS_DEV_SUSPEND_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTS_DEV_CONN_DIS_RESET 0x0 -#define USB_INTS_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTS_DEV_CONN_DIS_MSB 13 -#define USB_INTS_DEV_CONN_DIS_LSB 13 +#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTS_DEV_CONN_DIS_MSB _u(13) +#define USB_INTS_DEV_CONN_DIS_LSB _u(13) #define USB_INTS_DEV_CONN_DIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTS_BUS_RESET_RESET 0x0 -#define USB_INTS_BUS_RESET_BITS 0x00001000 -#define USB_INTS_BUS_RESET_MSB 12 -#define USB_INTS_BUS_RESET_LSB 12 +#define USB_INTS_BUS_RESET_RESET _u(0x0) +#define USB_INTS_BUS_RESET_BITS _u(0x00001000) +#define USB_INTS_BUS_RESET_MSB _u(12) +#define USB_INTS_BUS_RESET_LSB _u(12) #define USB_INTS_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTS_VBUS_DETECT_RESET 0x0 -#define USB_INTS_VBUS_DETECT_BITS 0x00000800 -#define USB_INTS_VBUS_DETECT_MSB 11 -#define USB_INTS_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTS_VBUS_DETECT_RESET _u(0x0) +#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTS_VBUS_DETECT_MSB _u(11) +#define USB_INTS_VBUS_DETECT_LSB _u(11) #define USB_INTS_VBUS_DETECT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTS_STALL_RESET 0x0 -#define USB_INTS_STALL_BITS 0x00000400 -#define USB_INTS_STALL_MSB 10 -#define USB_INTS_STALL_LSB 10 +#define USB_INTS_STALL_RESET _u(0x0) +#define USB_INTS_STALL_BITS _u(0x00000400) +#define USB_INTS_STALL_MSB _u(10) +#define USB_INTS_STALL_LSB _u(10) #define USB_INTS_STALL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTS_ERROR_CRC_RESET 0x0 -#define USB_INTS_ERROR_CRC_BITS 0x00000200 -#define USB_INTS_ERROR_CRC_MSB 9 -#define USB_INTS_ERROR_CRC_LSB 9 +#define USB_INTS_ERROR_CRC_RESET _u(0x0) +#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTS_ERROR_CRC_MSB _u(9) +#define USB_INTS_ERROR_CRC_LSB _u(9) #define USB_INTS_ERROR_CRC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTS_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTS_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTS_ERROR_BIT_STUFF_MSB 8 -#define USB_INTS_ERROR_BIT_STUFF_LSB 8 +#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTS_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTS_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTS_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTS_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTS_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTS_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTS_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTS_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTS_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTS_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTS_ERROR_DATA_SEQ_MSB 5 -#define USB_INTS_ERROR_DATA_SEQ_LSB 5 +#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTS_BUFF_STATUS_RESET 0x0 -#define USB_INTS_BUFF_STATUS_BITS 0x00000010 -#define USB_INTS_BUFF_STATUS_MSB 4 -#define USB_INTS_BUFF_STATUS_LSB 4 +#define USB_INTS_BUFF_STATUS_RESET _u(0x0) +#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTS_BUFF_STATUS_MSB _u(4) +#define USB_INTS_BUFF_STATUS_LSB _u(4) #define USB_INTS_BUFF_STATUS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTS_TRANS_COMPLETE_RESET 0x0 -#define USB_INTS_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTS_TRANS_COMPLETE_MSB 3 -#define USB_INTS_TRANS_COMPLETE_LSB 3 +#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTS_TRANS_COMPLETE_MSB _u(3) +#define USB_INTS_TRANS_COMPLETE_LSB _u(3) #define USB_INTS_TRANS_COMPLETE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTS_HOST_SOF_RESET 0x0 -#define USB_INTS_HOST_SOF_BITS 0x00000004 -#define USB_INTS_HOST_SOF_MSB 2 -#define USB_INTS_HOST_SOF_LSB 2 +#define USB_INTS_HOST_SOF_RESET _u(0x0) +#define USB_INTS_HOST_SOF_BITS _u(0x00000004) +#define USB_INTS_HOST_SOF_MSB _u(2) +#define USB_INTS_HOST_SOF_LSB _u(2) #define USB_INTS_HOST_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTS_HOST_RESUME_RESET 0x0 -#define USB_INTS_HOST_RESUME_BITS 0x00000002 -#define USB_INTS_HOST_RESUME_MSB 1 -#define USB_INTS_HOST_RESUME_LSB 1 +#define USB_INTS_HOST_RESUME_RESET _u(0x0) +#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTS_HOST_RESUME_MSB _u(1) +#define USB_INTS_HOST_RESUME_LSB _u(1) #define USB_INTS_HOST_RESUME_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTS_HOST_CONN_DIS_RESET 0x0 -#define USB_INTS_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTS_HOST_CONN_DIS_MSB 0 -#define USB_INTS_HOST_CONN_DIS_LSB 0 +#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTS_HOST_CONN_DIS_MSB _u(0) +#define USB_INTS_HOST_CONN_DIS_LSB _u(0) #define USB_INTS_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_USB_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h new file mode 100644 index 00000000000..fe65ffb1fb9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h @@ -0,0 +1,6807 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB_DEVICE_DPRAM +// Version : 1 +// Bus type : ahbl +// Description : DPRAM layout for USB device. +// ============================================================================= +#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW +// Description : Bytes 0-3 of the SETUP packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH +// Description : Bytes 4-7 of the setup packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h index 34ca1ba5c0f..356ff568ac4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h @@ -15,17 +15,17 @@ // ============================================================================= // Register : VREG_AND_CHIP_RESET_VREG // Description : Voltage regulator control and status -#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000 -#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3 -#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1 +#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000) +#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3) +#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_ROK // Description : regulation status // 0=not in regulation, 1=in regulation -#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0 -#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000 -#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12 -#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000) +#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12) +#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12) #define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_VSEL @@ -41,35 +41,35 @@ // 1101 - 1.20V // 1110 - 1.25V // 1111 - 1.30V -#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb -#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0 -#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7 -#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb) +#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0) +#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7) +#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4) #define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_HIZ // Description : high impedance mode select // 0=not in high impedance mode, 1=in high impedance mode -#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0 -#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002 -#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1 -#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002) +#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1) +#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1) #define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_EN // Description : enable // 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1 -#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001 -#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0 -#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1) +#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001) +#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0) +#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0) #define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" // ============================================================================= // Register : VREG_AND_CHIP_RESET_BOD // Description : brown-out detection control -#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004 -#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1 -#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091 +#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004) +#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1) +#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_BOD_VSEL // Description : threshold select @@ -89,26 +89,26 @@ // 1101 - 1.032V // 1110 - 1.075V // 1111 - 1.118V -#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9 -#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0 -#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7 -#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9) +#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0) +#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7) +#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4) #define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_BOD_EN // Description : enable // 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1 -#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001 -#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0 -#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1) +#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001) +#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0) +#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0) #define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" // ============================================================================= // Register : VREG_AND_CHIP_RESET_CHIP_RESET // Description : Chip reset control and status -#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008 -#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100 -#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008) +#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100) +#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG // Description : This is set by psm_restart from the debugger. @@ -117,35 +117,35 @@ // boot lock-up. // In the safe mode the debugger can repair the boot code, clear // this flag then reboot the processor. -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24) #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART // Description : Last reset was from the debug port -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN // Description : Last reset was from the RUN pin -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR // Description : Last reset was from the power-on reset or brown-out detection // blocks -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h index f415c9c25ec..6a9853d4092 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h @@ -17,210 +17,210 @@ // The rst_wdsel register determines which subsystems are reset // when the watchdog is triggered. // The watchdog can be triggered in software. -#define WATCHDOG_CTRL_OFFSET 0x00000000 -#define WATCHDOG_CTRL_BITS 0xc7ffffff -#define WATCHDOG_CTRL_RESET 0x07000000 +#define WATCHDOG_CTRL_OFFSET _u(0x00000000) +#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) +#define WATCHDOG_CTRL_RESET _u(0x07000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_TRIGGER // Description : Trigger a watchdog reset -#define WATCHDOG_CTRL_TRIGGER_RESET 0x0 -#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000 -#define WATCHDOG_CTRL_TRIGGER_MSB 31 -#define WATCHDOG_CTRL_TRIGGER_LSB 31 +#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) +#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) +#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) #define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_ENABLE // Description : When not enabled the watchdog timer is paused -#define WATCHDOG_CTRL_ENABLE_RESET 0x0 -#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000 -#define WATCHDOG_CTRL_ENABLE_MSB 30 -#define WATCHDOG_CTRL_ENABLE_LSB 30 +#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) +#define WATCHDOG_CTRL_ENABLE_MSB _u(30) +#define WATCHDOG_CTRL_ENABLE_LSB _u(30) #define WATCHDOG_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_DBG1 // Description : Pause the watchdog timer when processor 1 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000 -#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26 -#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) #define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_DBG0 // Description : Pause the watchdog timer when processor 0 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000 -#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25 -#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) #define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_JTAG // Description : Pause the watchdog timer when JTAG is accessing the bus fabric -#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000 -#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24 -#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) #define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_TIME // Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before // a watchdog reset will be triggered -#define WATCHDOG_CTRL_TIME_RESET 0x000000 -#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff -#define WATCHDOG_CTRL_TIME_MSB 23 -#define WATCHDOG_CTRL_TIME_LSB 0 +#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) +#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) +#define WATCHDOG_CTRL_TIME_MSB _u(23) +#define WATCHDOG_CTRL_TIME_LSB _u(0) #define WATCHDOG_CTRL_TIME_ACCESS "RO" // ============================================================================= // Register : WATCHDOG_LOAD // Description : Load the watchdog timer. The maximum setting is 0xffffff which // corresponds to 0xffffff / 2 ticks before triggering a watchdog // reset (see errata RP2040-E1). -#define WATCHDOG_LOAD_OFFSET 0x00000004 -#define WATCHDOG_LOAD_BITS 0x00ffffff -#define WATCHDOG_LOAD_RESET 0x00000000 -#define WATCHDOG_LOAD_MSB 23 -#define WATCHDOG_LOAD_LSB 0 +#define WATCHDOG_LOAD_OFFSET _u(0x00000004) +#define WATCHDOG_LOAD_BITS _u(0x00ffffff) +#define WATCHDOG_LOAD_RESET _u(0x00000000) +#define WATCHDOG_LOAD_MSB _u(23) +#define WATCHDOG_LOAD_LSB _u(0) #define WATCHDOG_LOAD_ACCESS "WF" // ============================================================================= // Register : WATCHDOG_REASON // Description : Logs the reason for the last reset. Both bits are zero for the // case of a hardware reset. -#define WATCHDOG_REASON_OFFSET 0x00000008 -#define WATCHDOG_REASON_BITS 0x00000003 -#define WATCHDOG_REASON_RESET 0x00000000 +#define WATCHDOG_REASON_OFFSET _u(0x00000008) +#define WATCHDOG_REASON_BITS _u(0x00000003) +#define WATCHDOG_REASON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_FORCE // Description : None -#define WATCHDOG_REASON_FORCE_RESET 0x0 -#define WATCHDOG_REASON_FORCE_BITS 0x00000002 -#define WATCHDOG_REASON_FORCE_MSB 1 -#define WATCHDOG_REASON_FORCE_LSB 1 +#define WATCHDOG_REASON_FORCE_RESET _u(0x0) +#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) +#define WATCHDOG_REASON_FORCE_MSB _u(1) +#define WATCHDOG_REASON_FORCE_LSB _u(1) #define WATCHDOG_REASON_FORCE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_TIMER // Description : None -#define WATCHDOG_REASON_TIMER_RESET 0x0 -#define WATCHDOG_REASON_TIMER_BITS 0x00000001 -#define WATCHDOG_REASON_TIMER_MSB 0 -#define WATCHDOG_REASON_TIMER_LSB 0 +#define WATCHDOG_REASON_TIMER_RESET _u(0x0) +#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) +#define WATCHDOG_REASON_TIMER_MSB _u(0) +#define WATCHDOG_REASON_TIMER_LSB _u(0) #define WATCHDOG_REASON_TIMER_ACCESS "RO" // ============================================================================= // Register : WATCHDOG_SCRATCH0 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c -#define WATCHDOG_SCRATCH0_BITS 0xffffffff -#define WATCHDOG_SCRATCH0_RESET 0x00000000 -#define WATCHDOG_SCRATCH0_MSB 31 -#define WATCHDOG_SCRATCH0_LSB 0 +#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) +#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH0_MSB _u(31) +#define WATCHDOG_SCRATCH0_LSB _u(0) #define WATCHDOG_SCRATCH0_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH1 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH1_OFFSET 0x00000010 -#define WATCHDOG_SCRATCH1_BITS 0xffffffff -#define WATCHDOG_SCRATCH1_RESET 0x00000000 -#define WATCHDOG_SCRATCH1_MSB 31 -#define WATCHDOG_SCRATCH1_LSB 0 +#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) +#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH1_MSB _u(31) +#define WATCHDOG_SCRATCH1_LSB _u(0) #define WATCHDOG_SCRATCH1_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH2 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH2_OFFSET 0x00000014 -#define WATCHDOG_SCRATCH2_BITS 0xffffffff -#define WATCHDOG_SCRATCH2_RESET 0x00000000 -#define WATCHDOG_SCRATCH2_MSB 31 -#define WATCHDOG_SCRATCH2_LSB 0 +#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) +#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH2_MSB _u(31) +#define WATCHDOG_SCRATCH2_LSB _u(0) #define WATCHDOG_SCRATCH2_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH3 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH3_OFFSET 0x00000018 -#define WATCHDOG_SCRATCH3_BITS 0xffffffff -#define WATCHDOG_SCRATCH3_RESET 0x00000000 -#define WATCHDOG_SCRATCH3_MSB 31 -#define WATCHDOG_SCRATCH3_LSB 0 +#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) +#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH3_MSB _u(31) +#define WATCHDOG_SCRATCH3_LSB _u(0) #define WATCHDOG_SCRATCH3_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH4 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c -#define WATCHDOG_SCRATCH4_BITS 0xffffffff -#define WATCHDOG_SCRATCH4_RESET 0x00000000 -#define WATCHDOG_SCRATCH4_MSB 31 -#define WATCHDOG_SCRATCH4_LSB 0 +#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) +#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH4_MSB _u(31) +#define WATCHDOG_SCRATCH4_LSB _u(0) #define WATCHDOG_SCRATCH4_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH5 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH5_OFFSET 0x00000020 -#define WATCHDOG_SCRATCH5_BITS 0xffffffff -#define WATCHDOG_SCRATCH5_RESET 0x00000000 -#define WATCHDOG_SCRATCH5_MSB 31 -#define WATCHDOG_SCRATCH5_LSB 0 +#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) +#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH5_MSB _u(31) +#define WATCHDOG_SCRATCH5_LSB _u(0) #define WATCHDOG_SCRATCH5_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH6 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH6_OFFSET 0x00000024 -#define WATCHDOG_SCRATCH6_BITS 0xffffffff -#define WATCHDOG_SCRATCH6_RESET 0x00000000 -#define WATCHDOG_SCRATCH6_MSB 31 -#define WATCHDOG_SCRATCH6_LSB 0 +#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) +#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH6_MSB _u(31) +#define WATCHDOG_SCRATCH6_LSB _u(0) #define WATCHDOG_SCRATCH6_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH7 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH7_OFFSET 0x00000028 -#define WATCHDOG_SCRATCH7_BITS 0xffffffff -#define WATCHDOG_SCRATCH7_RESET 0x00000000 -#define WATCHDOG_SCRATCH7_MSB 31 -#define WATCHDOG_SCRATCH7_LSB 0 +#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) +#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH7_MSB _u(31) +#define WATCHDOG_SCRATCH7_LSB _u(0) #define WATCHDOG_SCRATCH7_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_TICK // Description : Controls the tick generator -#define WATCHDOG_TICK_OFFSET 0x0000002c -#define WATCHDOG_TICK_BITS 0x000fffff -#define WATCHDOG_TICK_RESET 0x00000200 +#define WATCHDOG_TICK_OFFSET _u(0x0000002c) +#define WATCHDOG_TICK_BITS _u(0x000fffff) +#define WATCHDOG_TICK_RESET _u(0x00000200) // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_COUNT // Description : Count down timer: the remaining number clk_tick cycles before // the next tick is generated. #define WATCHDOG_TICK_COUNT_RESET "-" -#define WATCHDOG_TICK_COUNT_BITS 0x000ff800 -#define WATCHDOG_TICK_COUNT_MSB 19 -#define WATCHDOG_TICK_COUNT_LSB 11 +#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800) +#define WATCHDOG_TICK_COUNT_MSB _u(19) +#define WATCHDOG_TICK_COUNT_LSB _u(11) #define WATCHDOG_TICK_COUNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_RUNNING // Description : Is the tick generator running? #define WATCHDOG_TICK_RUNNING_RESET "-" -#define WATCHDOG_TICK_RUNNING_BITS 0x00000400 -#define WATCHDOG_TICK_RUNNING_MSB 10 -#define WATCHDOG_TICK_RUNNING_LSB 10 +#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400) +#define WATCHDOG_TICK_RUNNING_MSB _u(10) +#define WATCHDOG_TICK_RUNNING_LSB _u(10) #define WATCHDOG_TICK_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_ENABLE // Description : start / stop tick generation -#define WATCHDOG_TICK_ENABLE_RESET 0x1 -#define WATCHDOG_TICK_ENABLE_BITS 0x00000200 -#define WATCHDOG_TICK_ENABLE_MSB 9 -#define WATCHDOG_TICK_ENABLE_LSB 9 +#define WATCHDOG_TICK_ENABLE_RESET _u(0x1) +#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200) +#define WATCHDOG_TICK_ENABLE_MSB _u(9) +#define WATCHDOG_TICK_ENABLE_LSB _u(9) #define WATCHDOG_TICK_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_CYCLES // Description : Total number of clk_tick cycles before the next tick. -#define WATCHDOG_TICK_CYCLES_RESET 0x000 -#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff -#define WATCHDOG_TICK_CYCLES_MSB 8 -#define WATCHDOG_TICK_CYCLES_LSB 0 +#define WATCHDOG_TICK_CYCLES_RESET _u(0x000) +#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff) +#define WATCHDOG_TICK_CYCLES_MSB _u(8) +#define WATCHDOG_TICK_CYCLES_LSB _u(0) #define WATCHDOG_TICK_CYCLES_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_WATCHDOG_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h index 59487e46043..3964f67456d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : XIP_CTRL // Description : Cache control -#define XIP_CTRL_OFFSET 0x00000000 -#define XIP_CTRL_BITS 0x0000000b -#define XIP_CTRL_RESET 0x00000003 +#define XIP_CTRL_OFFSET _u(0x00000000) +#define XIP_CTRL_BITS _u(0x0000000b) +#define XIP_CTRL_RESET _u(0x00000003) // ----------------------------------------------------------------------------- // Field : XIP_CTRL_POWER_DOWN // Description : When 1, the cache memories are powered down. They retain state, @@ -26,10 +26,10 @@ // be enabled when powered down. // Cache-as-SRAM accesses will produce a bus error response when // the cache is powered down. -#define XIP_CTRL_POWER_DOWN_RESET 0x0 -#define XIP_CTRL_POWER_DOWN_BITS 0x00000008 -#define XIP_CTRL_POWER_DOWN_MSB 3 -#define XIP_CTRL_POWER_DOWN_LSB 3 +#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) +#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) +#define XIP_CTRL_POWER_DOWN_MSB _u(3) +#define XIP_CTRL_POWER_DOWN_LSB _u(3) #define XIP_CTRL_POWER_DOWN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XIP_CTRL_ERR_BADWRITE @@ -40,10 +40,10 @@ // In either case, writes to the 0x0 alias will deallocate on tag // match, // as usual. -#define XIP_CTRL_ERR_BADWRITE_RESET 0x1 -#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002 -#define XIP_CTRL_ERR_BADWRITE_MSB 1 -#define XIP_CTRL_ERR_BADWRITE_LSB 1 +#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1) +#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002) +#define XIP_CTRL_ERR_BADWRITE_MSB _u(1) +#define XIP_CTRL_ERR_BADWRITE_LSB _u(1) #define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XIP_CTRL_EN @@ -57,10 +57,10 @@ // If the cache is enabled, cache-as-SRAM accesses have no effect // on the // cache data RAM, and will produce a bus error response. -#define XIP_CTRL_EN_RESET 0x1 -#define XIP_CTRL_EN_BITS 0x00000001 -#define XIP_CTRL_EN_MSB 0 -#define XIP_CTRL_EN_LSB 0 +#define XIP_CTRL_EN_RESET _u(0x1) +#define XIP_CTRL_EN_BITS _u(0x00000001) +#define XIP_CTRL_EN_MSB _u(0) +#define XIP_CTRL_EN_LSB _u(0) #define XIP_CTRL_EN_ACCESS "RW" // ============================================================================= // Register : XIP_FLUSH @@ -70,45 +70,45 @@ // contents is not affected by flush or reset.) // Reading will hold the bus (stall the processor) until the flush // completes. Alternatively STAT can be polled until completion. -#define XIP_FLUSH_OFFSET 0x00000004 -#define XIP_FLUSH_BITS 0x00000001 -#define XIP_FLUSH_RESET 0x00000000 -#define XIP_FLUSH_MSB 0 -#define XIP_FLUSH_LSB 0 +#define XIP_FLUSH_OFFSET _u(0x00000004) +#define XIP_FLUSH_BITS _u(0x00000001) +#define XIP_FLUSH_RESET _u(0x00000000) +#define XIP_FLUSH_MSB _u(0) +#define XIP_FLUSH_LSB _u(0) #define XIP_FLUSH_ACCESS "SC" // ============================================================================= // Register : XIP_STAT // Description : Cache Status -#define XIP_STAT_OFFSET 0x00000008 -#define XIP_STAT_BITS 0x00000007 -#define XIP_STAT_RESET 0x00000002 +#define XIP_STAT_OFFSET _u(0x00000008) +#define XIP_STAT_BITS _u(0x00000007) +#define XIP_STAT_RESET _u(0x00000002) // ----------------------------------------------------------------------------- // Field : XIP_STAT_FIFO_FULL // Description : When 1, indicates the XIP streaming FIFO is completely full. // The streaming FIFO is 2 entries deep, so the full and empty // flag allow its level to be ascertained. -#define XIP_STAT_FIFO_FULL_RESET 0x0 -#define XIP_STAT_FIFO_FULL_BITS 0x00000004 -#define XIP_STAT_FIFO_FULL_MSB 2 -#define XIP_STAT_FIFO_FULL_LSB 2 +#define XIP_STAT_FIFO_FULL_RESET _u(0x0) +#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) +#define XIP_STAT_FIFO_FULL_MSB _u(2) +#define XIP_STAT_FIFO_FULL_LSB _u(2) #define XIP_STAT_FIFO_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XIP_STAT_FIFO_EMPTY // Description : When 1, indicates the XIP streaming FIFO is completely empty. -#define XIP_STAT_FIFO_EMPTY_RESET 0x1 -#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002 -#define XIP_STAT_FIFO_EMPTY_MSB 1 -#define XIP_STAT_FIFO_EMPTY_LSB 1 +#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) +#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) +#define XIP_STAT_FIFO_EMPTY_MSB _u(1) +#define XIP_STAT_FIFO_EMPTY_LSB _u(1) #define XIP_STAT_FIFO_EMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XIP_STAT_FLUSH_READY // Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. // The cache is flushed whenever the XIP block is reset, and also // when requested via the FLUSH register. -#define XIP_STAT_FLUSH_READY_RESET 0x0 -#define XIP_STAT_FLUSH_READY_BITS 0x00000001 -#define XIP_STAT_FLUSH_READY_MSB 0 -#define XIP_STAT_FLUSH_READY_LSB 0 +#define XIP_STAT_FLUSH_READY_RESET _u(0x0) +#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001) +#define XIP_STAT_FLUSH_READY_MSB _u(0) +#define XIP_STAT_FLUSH_READY_LSB _u(0) #define XIP_STAT_FLUSH_READY_ACCESS "RO" // ============================================================================= // Register : XIP_CTR_HIT @@ -117,11 +117,11 @@ // hit, // i.e. when an XIP access is serviced directly from cached data. // Write any value to clear. -#define XIP_CTR_HIT_OFFSET 0x0000000c -#define XIP_CTR_HIT_BITS 0xffffffff -#define XIP_CTR_HIT_RESET 0x00000000 -#define XIP_CTR_HIT_MSB 31 -#define XIP_CTR_HIT_LSB 0 +#define XIP_CTR_HIT_OFFSET _u(0x0000000c) +#define XIP_CTR_HIT_BITS _u(0xffffffff) +#define XIP_CTR_HIT_RESET _u(0x00000000) +#define XIP_CTR_HIT_MSB _u(31) +#define XIP_CTR_HIT_LSB _u(0) #define XIP_CTR_HIT_ACCESS "WC" // ============================================================================= // Register : XIP_CTR_ACC @@ -131,11 +131,11 @@ // whether the cache is hit or not. This includes noncacheable // accesses. // Write any value to clear. -#define XIP_CTR_ACC_OFFSET 0x00000010 -#define XIP_CTR_ACC_BITS 0xffffffff -#define XIP_CTR_ACC_RESET 0x00000000 -#define XIP_CTR_ACC_MSB 31 -#define XIP_CTR_ACC_LSB 0 +#define XIP_CTR_ACC_OFFSET _u(0x00000010) +#define XIP_CTR_ACC_BITS _u(0xffffffff) +#define XIP_CTR_ACC_RESET _u(0x00000000) +#define XIP_CTR_ACC_MSB _u(31) +#define XIP_CTR_ACC_LSB _u(0) #define XIP_CTR_ACC_ACCESS "WC" // ============================================================================= // Register : XIP_STREAM_ADDR @@ -145,11 +145,11 @@ // Increments automatically after each flash access. // Write the initial access address here before starting a // streaming read. -#define XIP_STREAM_ADDR_OFFSET 0x00000014 -#define XIP_STREAM_ADDR_BITS 0xfffffffc -#define XIP_STREAM_ADDR_RESET 0x00000000 -#define XIP_STREAM_ADDR_MSB 31 -#define XIP_STREAM_ADDR_LSB 2 +#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) +#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) +#define XIP_STREAM_ADDR_RESET _u(0x00000000) +#define XIP_STREAM_ADDR_MSB _u(31) +#define XIP_STREAM_ADDR_LSB _u(2) #define XIP_STREAM_ADDR_ACCESS "RW" // ============================================================================= // Register : XIP_STREAM_CTR @@ -163,11 +163,11 @@ // in-flight // read, so that a new stream can immediately be started (after // draining the FIFO and reinitialising STREAM_ADDR) -#define XIP_STREAM_CTR_OFFSET 0x00000018 -#define XIP_STREAM_CTR_BITS 0x003fffff -#define XIP_STREAM_CTR_RESET 0x00000000 -#define XIP_STREAM_CTR_MSB 21 -#define XIP_STREAM_CTR_LSB 0 +#define XIP_STREAM_CTR_OFFSET _u(0x00000018) +#define XIP_STREAM_CTR_BITS _u(0x003fffff) +#define XIP_STREAM_CTR_RESET _u(0x00000000) +#define XIP_STREAM_CTR_MSB _u(21) +#define XIP_STREAM_CTR_LSB _u(0) #define XIP_STREAM_CTR_ACCESS "RW" // ============================================================================= // Register : XIP_STREAM_FIFO @@ -177,11 +177,11 @@ // This FIFO can also be accessed via the XIP_AUX slave, to avoid // exposing // the DMA to bus stalls caused by other XIP traffic. -#define XIP_STREAM_FIFO_OFFSET 0x0000001c -#define XIP_STREAM_FIFO_BITS 0xffffffff -#define XIP_STREAM_FIFO_RESET 0x00000000 -#define XIP_STREAM_FIFO_MSB 31 -#define XIP_STREAM_FIFO_LSB 0 +#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) +#define XIP_STREAM_FIFO_BITS _u(0xffffffff) +#define XIP_STREAM_FIFO_RESET _u(0x00000000) +#define XIP_STREAM_FIFO_MSB _u(31) +#define XIP_STREAM_FIFO_LSB _u(0) #define XIP_STREAM_FIFO_ACCESS "RF" // ============================================================================= #endif // HARDWARE_REGS_XIP_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h index 89d036b86b1..ec84d3d9086 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : XOSC_CTRL // Description : Crystal Oscillator Control -#define XOSC_CTRL_OFFSET 0x00000000 -#define XOSC_CTRL_BITS 0x00ffffff -#define XOSC_CTRL_RESET 0x00000000 +#define XOSC_CTRL_OFFSET _u(0x00000000) +#define XOSC_CTRL_BITS _u(0x00ffffff) +#define XOSC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_ENABLE // Description : On power-up this field is initialised to DISABLE and the chip @@ -31,12 +31,12 @@ // 0xd1e -> DISABLE // 0xfab -> ENABLE #define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS 0x00fff000 -#define XOSC_CTRL_ENABLE_MSB 23 -#define XOSC_CTRL_ENABLE_LSB 12 +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) #define XOSC_CTRL_ENABLE_ACCESS "RW" -#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e -#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_FREQ_RANGE // Description : Frequency range. This resets to 0xAA0 and cannot be changed. @@ -45,45 +45,45 @@ // 0xaa2 -> RESERVED_2 // 0xaa3 -> RESERVED_3 #define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff -#define XOSC_CTRL_FREQ_RANGE_MSB 11 -#define XOSC_CTRL_FREQ_RANGE_LSB 0 +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) #define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3 +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3) // ============================================================================= // Register : XOSC_STATUS // Description : Crystal Oscillator Status -#define XOSC_STATUS_OFFSET 0x00000004 -#define XOSC_STATUS_BITS 0x81001003 -#define XOSC_STATUS_RESET 0x00000000 +#define XOSC_STATUS_OFFSET _u(0x00000004) +#define XOSC_STATUS_BITS _u(0x81001003) +#define XOSC_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_STABLE // Description : Oscillator is running and stable -#define XOSC_STATUS_STABLE_RESET 0x0 -#define XOSC_STATUS_STABLE_BITS 0x80000000 -#define XOSC_STATUS_STABLE_MSB 31 -#define XOSC_STATUS_STABLE_LSB 31 +#define XOSC_STATUS_STABLE_RESET _u(0x0) +#define XOSC_STATUS_STABLE_BITS _u(0x80000000) +#define XOSC_STATUS_STABLE_MSB _u(31) +#define XOSC_STATUS_STABLE_LSB _u(31) #define XOSC_STATUS_STABLE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_BADWRITE // Description : An invalid value has been written to CTRL_ENABLE or // CTRL_FREQ_RANGE or DORMANT -#define XOSC_STATUS_BADWRITE_RESET 0x0 -#define XOSC_STATUS_BADWRITE_BITS 0x01000000 -#define XOSC_STATUS_BADWRITE_MSB 24 -#define XOSC_STATUS_BADWRITE_LSB 24 +#define XOSC_STATUS_BADWRITE_RESET _u(0x0) +#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define XOSC_STATUS_BADWRITE_MSB _u(24) +#define XOSC_STATUS_BADWRITE_LSB _u(24) #define XOSC_STATUS_BADWRITE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_ENABLED // Description : Oscillator is enabled but not necessarily running and stable, // resets to 0 #define XOSC_STATUS_ENABLED_RESET "-" -#define XOSC_STATUS_ENABLED_BITS 0x00001000 -#define XOSC_STATUS_ENABLED_MSB 12 -#define XOSC_STATUS_ENABLED_LSB 12 +#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) +#define XOSC_STATUS_ENABLED_MSB _u(12) +#define XOSC_STATUS_ENABLED_LSB _u(12) #define XOSC_STATUS_ENABLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_FREQ_RANGE @@ -93,14 +93,14 @@ // 0x2 -> RESERVED_2 // 0x3 -> RESERVED_3 #define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003 -#define XOSC_STATUS_FREQ_RANGE_MSB 1 -#define XOSC_STATUS_FREQ_RANGE_LSB 0 +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) #define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3 +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3) // ============================================================================= // Register : XOSC_DORMANT // Description : Crystal Oscillator pause control @@ -111,36 +111,37 @@ // WARNING: setup the irq before selecting dormant mode // 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET 0x00000008 -#define XOSC_DORMANT_BITS 0xffffffff +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) #define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB 31 -#define XOSC_DORMANT_LSB 0 +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) #define XOSC_DORMANT_ACCESS "RW" -#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61 -#define XOSC_DORMANT_VALUE_WAKE 0x77616b65 +#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : XOSC_STARTUP // Description : Controls the startup delay -#define XOSC_STARTUP_OFFSET 0x0000000c -#define XOSC_STARTUP_BITS 0x00103fff -#define XOSC_STARTUP_RESET 0x00000000 +#define XOSC_STARTUP_OFFSET _u(0x0000000c) +#define XOSC_STARTUP_BITS _u(0x00103fff) +#define XOSC_STARTUP_RESET _u(0x000000c4) // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_X4 // Description : Multiplies the startup_delay by 4. This is of little value to -// the user given that the delay can be programmed directly -#define XOSC_STARTUP_X4_RESET "-" -#define XOSC_STARTUP_X4_BITS 0x00100000 -#define XOSC_STARTUP_X4_MSB 20 -#define XOSC_STARTUP_X4_LSB 20 +// the user given that the delay can be programmed directly. +#define XOSC_STARTUP_X4_RESET _u(0x0) +#define XOSC_STARTUP_X4_BITS _u(0x00100000) +#define XOSC_STARTUP_X4_MSB _u(20) +#define XOSC_STARTUP_X4_LSB _u(20) #define XOSC_STARTUP_X4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_DELAY -// Description : in multiples of 256*xtal_period -#define XOSC_STARTUP_DELAY_RESET "-" -#define XOSC_STARTUP_DELAY_BITS 0x00003fff -#define XOSC_STARTUP_DELAY_MSB 13 -#define XOSC_STARTUP_DELAY_LSB 0 +// Description : in multiples of 256*xtal_period. The reset value of 0xc4 +// corresponds to approx 50 000 cycles. +#define XOSC_STARTUP_DELAY_RESET _u(0x00c4) +#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) +#define XOSC_STARTUP_DELAY_MSB _u(13) +#define XOSC_STARTUP_DELAY_LSB _u(0) #define XOSC_STARTUP_DELAY_ACCESS "RW" // ============================================================================= // Register : XOSC_COUNT @@ -149,11 +150,11 @@ // To start the counter write a non-zero value. // Can be used for short software pauses when setting up time // sensitive hardware. -#define XOSC_COUNT_OFFSET 0x0000001c -#define XOSC_COUNT_BITS 0x000000ff -#define XOSC_COUNT_RESET 0x00000000 -#define XOSC_COUNT_MSB 7 -#define XOSC_COUNT_LSB 0 +#define XOSC_COUNT_OFFSET _u(0x0000001c) +#define XOSC_COUNT_BITS _u(0x000000ff) +#define XOSC_COUNT_RESET _u(0x00000000) +#define XOSC_COUNT_MSB _u(7) +#define XOSC_COUNT_LSB _u(0) #define XOSC_COUNT_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_XOSC_DEFINED diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd index d5acb9748a9..52da2c076f6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/rp2040.svd @@ -22,6 +22,7 @@ true false 2 + 1 false 26 @@ -1354,7 +1355,8 @@ read-only 0x0008 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT0_SELECTED 0x00000001 @@ -1473,7 +1475,8 @@ read-only 0x0014 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT1_SELECTED 0x00000001 @@ -1592,7 +1595,8 @@ read-only 0x0020 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT2_SELECTED 0x00000001 @@ -1711,7 +1715,8 @@ read-only 0x002c - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT3_SELECTED 0x00000001 @@ -1780,7 +1785,8 @@ read-only 0x0038 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. CLK_REF_SELECTED 0x00000001 @@ -1863,7 +1869,8 @@ read-only 0x0044 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. CLK_SYS_SELECTED 0x00000001 @@ -1926,7 +1933,8 @@ read-only 0x0050 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_PERI_SELECTED 0x00000001 @@ -2013,7 +2021,8 @@ read-only 0x005c - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_USB_SELECTED 0x00000001 @@ -2100,7 +2109,8 @@ read-only 0x0068 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_ADC_SELECTED 0x00000001 @@ -2193,7 +2203,8 @@ read-only 0x0074 - Indicates which src is currently selected (one-hot) + Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_RTC_SELECTED 0x00000001 @@ -22309,18 +22320,18 @@ read-write [20:20] - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly + Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. X4 read-write [13:0] - in multiples of 256*xtal_period + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. DELAY STARTUP - 0x00000000 + 0x000000c4 0x001c @@ -22545,7 +22556,89 @@ read-write [4:0] - Select a performance event for PERFCTR0 + Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + PERFSEL0 @@ -22576,7 +22669,89 @@ read-write [4:0] - Select a performance event for PERFCTR1 + Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + PERFSEL1 @@ -22607,7 +22782,89 @@ read-write [4:0] - Select a performance event for PERFCTR2 + Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + PERFSEL2 @@ -22638,7 +22895,89 @@ read-write [4:0] - Select a performance event for PERFCTR3 + Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + PERFSEL3 @@ -23889,7 +24228,76 @@ registers 0x40044000 - DW_apb_i2c address block + DW_apb_i2c address block\n\n + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n + IC_ULTRA_FAST_MODE ................ 0x0\n + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n + IC_UFM_SCL_LOW_COUNT .............. 0x0008\n + IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n + IC_TX_TL .......................... 0x0\n + IC_TX_CMD_BLOCK ................... 0x1\n + IC_HAS_DMA ........................ 0x1\n + IC_HAS_ASYNC_FIFO ................. 0x0\n + IC_SMBUS_ARP ...................... 0x0\n + IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n + IC_INTR_IO ........................ 0x1\n + IC_MASTER_MODE .................... 0x1\n + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n + IC_INTR_POL ....................... 0x1\n + IC_OPTIONAL_SAR ................... 0x0\n + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n + IC_DEFAULT_SLAVE_ADDR ............. 0x055\n + IC_DEFAULT_HS_SPKLEN .............. 0x1\n + IC_FS_SCL_HIGH_COUNT .............. 0x0006\n + IC_HS_SCL_LOW_COUNT ............... 0x0008\n + IC_DEVICE_ID_VALUE ................ 0x0\n + IC_10BITADDR_MASTER ............... 0x0\n + IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n + IC_DEFAULT_FS_SPKLEN .............. 0x7\n + IC_ADD_ENCODED_PARAMS ............. 0x0\n + IC_DEFAULT_SDA_HOLD ............... 0x000001\n + IC_DEFAULT_SDA_SETUP .............. 0x64\n + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n + IC_CLOCK_PERIOD ................... 100\n + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n + IC_RESTART_EN ..................... 0x1\n + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n + IC_BUS_CLEAR_FEATURE .............. 0x0\n + IC_CAP_LOADING .................... 100\n + IC_FS_SCL_LOW_COUNT ............... 0x000d\n + APB_DATA_WIDTH .................... 32\n + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_SLV_DATA_NACK_ONLY ............. 0x1\n + IC_10BITADDR_SLAVE ................ 0x0\n + IC_CLK_TYPE ....................... 0x0\n + IC_SMBUS_UDID_MSB ................. 0x0\n + IC_SMBUS_SUSPEND_ALERT ............ 0x0\n + IC_HS_SCL_HIGH_COUNT .............. 0x0006\n + IC_SLV_RESTART_DET_EN ............. 0x1\n + IC_SMBUS .......................... 0x0\n + IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n + IC_USE_COUNTS ..................... 0x0\n + IC_RX_BUFFER_DEPTH ................ 16\n + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_RX_FULL_HLD_BUS_EN ............. 0x1\n + IC_SLAVE_DISABLE .................. 0x1\n + IC_RX_TL .......................... 0x0\n + IC_DEVICE_ID ...................... 0x0\n + IC_HC_COUNT_VALUES ................ 0x0\n + I2C_DYNAMIC_TAR_UPDATE ............ 0\n + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n + IC_HS_MASTER_CODE ................. 0x1\n + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n + IC_SS_SCL_HIGH_COUNT .............. 0x0028\n + IC_SS_SCL_LOW_COUNT ............... 0x002f\n + IC_MAX_SPEED_MODE ................. 0x2\n + IC_STAT_FOR_CLK_STRETCH ........... 0x0\n + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n + IC_DEFAULT_UFM_SPKLEN ............. 0x1\n + IC_TX_BUFFER_DEPTH ................ 16 I2C0_IRQ 23 @@ -24334,25 +24742,6 @@ I2C Interrupt Status Register\n\n Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - - read-only - [13:13] - See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n - Reset value: 0x0 - - - R_MASTER_ON_HOLD interrupt is inactive - INACTIVE - 0 - - - R_MASTER_ON_HOLD interrupt is active - ACTIVE - 1 - - - R_MASTER_ON_HOLD - read-only [12:12] @@ -24609,25 +24998,6 @@ I2C Interrupt Mask Register.\n\n These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - - read-only - [13:13] - This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - - - MASTER_ON_HOLD interrupt is masked - ENABLED - 0 - - - MASTER_ON_HOLD interrupt is unmasked - DISABLED - 1 - - - M_MASTER_ON_HOLD_READ_ONLY - read-write [12:12] @@ -24884,25 +25254,6 @@ I2C Raw Interrupt Status Register\n\n Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - - read-only - [13:13] - Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n - Reset value: 0x0 - - - MASTER_ON_HOLD interrupt is inactive - INACTIVE - 0 - - - MASTER_ON_HOLD interrupt is active - ACTIVE - 1 - - - MASTER_ON_HOLD - read-only [12:12] @@ -25592,7 +25943,7 @@ The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n Writes to this register succeed only when IC_ENABLE[0]=0.\n\n - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. @@ -28982,7 +29333,7 @@ set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n - any other value sets div=0 and therefore divides by 32\n + any other value sets div=31\n this register resets to div=16 @@ -29003,7 +29354,7 @@ read-write [11:4] - set to 0xaa0\n + set to 0xaa\n any other value enables the output with shift=0 PASSWD @@ -29046,7 +29397,7 @@ read-write [24:24] - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT oneToClear BADWRITE @@ -29480,28 +29831,28 @@ 0x00000000 - read-only + read-write 0x0010 Alias for channel 0 CTRL register CH0_AL1_CTRL 0x00000000 - read-only + read-write 0x0014 Alias for channel 0 READ_ADDR register CH0_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0018 Alias for channel 0 WRITE_ADDR register CH0_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x001c Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -29510,28 +29861,28 @@ 0x00000000 - read-only + read-write 0x0020 Alias for channel 0 CTRL register CH0_AL2_CTRL 0x00000000 - read-only + read-write 0x0024 Alias for channel 0 TRANS_COUNT register CH0_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0028 Alias for channel 0 READ_ADDR register CH0_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x002c Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -29540,28 +29891,28 @@ 0x00000000 - read-only + read-write 0x0030 Alias for channel 0 CTRL register CH0_AL3_CTRL 0x00000000 - read-only + read-write 0x0034 Alias for channel 0 WRITE_ADDR register CH0_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0038 Alias for channel 0 TRANS_COUNT register CH0_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x003c Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -29765,28 +30116,28 @@ 0x00000800 - read-only + read-write 0x0050 Alias for channel 1 CTRL register CH1_AL1_CTRL 0x00000000 - read-only + read-write 0x0054 Alias for channel 1 READ_ADDR register CH1_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0058 Alias for channel 1 WRITE_ADDR register CH1_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x005c Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -29795,28 +30146,28 @@ 0x00000000 - read-only + read-write 0x0060 Alias for channel 1 CTRL register CH1_AL2_CTRL 0x00000000 - read-only + read-write 0x0064 Alias for channel 1 TRANS_COUNT register CH1_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0068 Alias for channel 1 READ_ADDR register CH1_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x006c Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -29825,28 +30176,28 @@ 0x00000000 - read-only + read-write 0x0070 Alias for channel 1 CTRL register CH1_AL3_CTRL 0x00000000 - read-only + read-write 0x0074 Alias for channel 1 WRITE_ADDR register CH1_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0078 Alias for channel 1 TRANS_COUNT register CH1_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x007c Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30050,28 +30401,28 @@ 0x00001000 - read-only + read-write 0x0090 Alias for channel 2 CTRL register CH2_AL1_CTRL 0x00000000 - read-only + read-write 0x0094 Alias for channel 2 READ_ADDR register CH2_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0098 Alias for channel 2 WRITE_ADDR register CH2_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x009c Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30080,28 +30431,28 @@ 0x00000000 - read-only + read-write 0x00a0 Alias for channel 2 CTRL register CH2_AL2_CTRL 0x00000000 - read-only + read-write 0x00a4 Alias for channel 2 TRANS_COUNT register CH2_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x00a8 Alias for channel 2 READ_ADDR register CH2_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x00ac Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30110,28 +30461,28 @@ 0x00000000 - read-only + read-write 0x00b0 Alias for channel 2 CTRL register CH2_AL3_CTRL 0x00000000 - read-only + read-write 0x00b4 Alias for channel 2 WRITE_ADDR register CH2_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x00b8 Alias for channel 2 TRANS_COUNT register CH2_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x00bc Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30335,28 +30686,28 @@ 0x00001800 - read-only + read-write 0x00d0 Alias for channel 3 CTRL register CH3_AL1_CTRL 0x00000000 - read-only + read-write 0x00d4 Alias for channel 3 READ_ADDR register CH3_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x00d8 Alias for channel 3 WRITE_ADDR register CH3_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x00dc Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30365,28 +30716,28 @@ 0x00000000 - read-only + read-write 0x00e0 Alias for channel 3 CTRL register CH3_AL2_CTRL 0x00000000 - read-only + read-write 0x00e4 Alias for channel 3 TRANS_COUNT register CH3_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x00e8 Alias for channel 3 READ_ADDR register CH3_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x00ec Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30395,28 +30746,28 @@ 0x00000000 - read-only + read-write 0x00f0 Alias for channel 3 CTRL register CH3_AL3_CTRL 0x00000000 - read-only + read-write 0x00f4 Alias for channel 3 WRITE_ADDR register CH3_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x00f8 Alias for channel 3 TRANS_COUNT register CH3_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x00fc Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30620,28 +30971,28 @@ 0x00002000 - read-only + read-write 0x0110 Alias for channel 4 CTRL register CH4_AL1_CTRL 0x00000000 - read-only + read-write 0x0114 Alias for channel 4 READ_ADDR register CH4_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0118 Alias for channel 4 WRITE_ADDR register CH4_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x011c Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30650,28 +31001,28 @@ 0x00000000 - read-only + read-write 0x0120 Alias for channel 4 CTRL register CH4_AL2_CTRL 0x00000000 - read-only + read-write 0x0124 Alias for channel 4 TRANS_COUNT register CH4_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0128 Alias for channel 4 READ_ADDR register CH4_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x012c Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30680,28 +31031,28 @@ 0x00000000 - read-only + read-write 0x0130 Alias for channel 4 CTRL register CH4_AL3_CTRL 0x00000000 - read-only + read-write 0x0134 Alias for channel 4 WRITE_ADDR register CH4_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0138 Alias for channel 4 TRANS_COUNT register CH4_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x013c Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30905,28 +31256,28 @@ 0x00002800 - read-only + read-write 0x0150 Alias for channel 5 CTRL register CH5_AL1_CTRL 0x00000000 - read-only + read-write 0x0154 Alias for channel 5 READ_ADDR register CH5_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0158 Alias for channel 5 WRITE_ADDR register CH5_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x015c Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30935,28 +31286,28 @@ 0x00000000 - read-only + read-write 0x0160 Alias for channel 5 CTRL register CH5_AL2_CTRL 0x00000000 - read-only + read-write 0x0164 Alias for channel 5 TRANS_COUNT register CH5_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0168 Alias for channel 5 READ_ADDR register CH5_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x016c Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -30965,28 +31316,28 @@ 0x00000000 - read-only + read-write 0x0170 Alias for channel 5 CTRL register CH5_AL3_CTRL 0x00000000 - read-only + read-write 0x0174 Alias for channel 5 WRITE_ADDR register CH5_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0178 Alias for channel 5 TRANS_COUNT register CH5_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x017c Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31190,28 +31541,28 @@ 0x00003000 - read-only + read-write 0x0190 Alias for channel 6 CTRL register CH6_AL1_CTRL 0x00000000 - read-only + read-write 0x0194 Alias for channel 6 READ_ADDR register CH6_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0198 Alias for channel 6 WRITE_ADDR register CH6_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x019c Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31220,28 +31571,28 @@ 0x00000000 - read-only + read-write 0x01a0 Alias for channel 6 CTRL register CH6_AL2_CTRL 0x00000000 - read-only + read-write 0x01a4 Alias for channel 6 TRANS_COUNT register CH6_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x01a8 Alias for channel 6 READ_ADDR register CH6_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x01ac Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31250,28 +31601,28 @@ 0x00000000 - read-only + read-write 0x01b0 Alias for channel 6 CTRL register CH6_AL3_CTRL 0x00000000 - read-only + read-write 0x01b4 Alias for channel 6 WRITE_ADDR register CH6_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x01b8 Alias for channel 6 TRANS_COUNT register CH6_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x01bc Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31475,28 +31826,28 @@ 0x00003800 - read-only + read-write 0x01d0 Alias for channel 7 CTRL register CH7_AL1_CTRL 0x00000000 - read-only + read-write 0x01d4 Alias for channel 7 READ_ADDR register CH7_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x01d8 Alias for channel 7 WRITE_ADDR register CH7_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x01dc Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31505,28 +31856,28 @@ 0x00000000 - read-only + read-write 0x01e0 Alias for channel 7 CTRL register CH7_AL2_CTRL 0x00000000 - read-only + read-write 0x01e4 Alias for channel 7 TRANS_COUNT register CH7_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x01e8 Alias for channel 7 READ_ADDR register CH7_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x01ec Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31535,28 +31886,28 @@ 0x00000000 - read-only + read-write 0x01f0 Alias for channel 7 CTRL register CH7_AL3_CTRL 0x00000000 - read-only + read-write 0x01f4 Alias for channel 7 WRITE_ADDR register CH7_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x01f8 Alias for channel 7 TRANS_COUNT register CH7_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x01fc Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31760,28 +32111,28 @@ 0x00004000 - read-only + read-write 0x0210 Alias for channel 8 CTRL register CH8_AL1_CTRL 0x00000000 - read-only + read-write 0x0214 Alias for channel 8 READ_ADDR register CH8_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0218 Alias for channel 8 WRITE_ADDR register CH8_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x021c Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31790,28 +32141,28 @@ 0x00000000 - read-only + read-write 0x0220 Alias for channel 8 CTRL register CH8_AL2_CTRL 0x00000000 - read-only + read-write 0x0224 Alias for channel 8 TRANS_COUNT register CH8_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0228 Alias for channel 8 READ_ADDR register CH8_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x022c Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -31820,28 +32171,28 @@ 0x00000000 - read-only + read-write 0x0230 Alias for channel 8 CTRL register CH8_AL3_CTRL 0x00000000 - read-only + read-write 0x0234 Alias for channel 8 WRITE_ADDR register CH8_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0238 Alias for channel 8 TRANS_COUNT register CH8_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x023c Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32045,28 +32396,28 @@ 0x00004800 - read-only + read-write 0x0250 Alias for channel 9 CTRL register CH9_AL1_CTRL 0x00000000 - read-only + read-write 0x0254 Alias for channel 9 READ_ADDR register CH9_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0258 Alias for channel 9 WRITE_ADDR register CH9_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x025c Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32075,28 +32426,28 @@ 0x00000000 - read-only + read-write 0x0260 Alias for channel 9 CTRL register CH9_AL2_CTRL 0x00000000 - read-only + read-write 0x0264 Alias for channel 9 TRANS_COUNT register CH9_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x0268 Alias for channel 9 READ_ADDR register CH9_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x026c Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32105,28 +32456,28 @@ 0x00000000 - read-only + read-write 0x0270 Alias for channel 9 CTRL register CH9_AL3_CTRL 0x00000000 - read-only + read-write 0x0274 Alias for channel 9 WRITE_ADDR register CH9_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x0278 Alias for channel 9 TRANS_COUNT register CH9_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x027c Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32330,28 +32681,28 @@ 0x00005000 - read-only + read-write 0x0290 Alias for channel 10 CTRL register CH10_AL1_CTRL 0x00000000 - read-only + read-write 0x0294 Alias for channel 10 READ_ADDR register CH10_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x0298 Alias for channel 10 WRITE_ADDR register CH10_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x029c Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32360,28 +32711,28 @@ 0x00000000 - read-only + read-write 0x02a0 Alias for channel 10 CTRL register CH10_AL2_CTRL 0x00000000 - read-only + read-write 0x02a4 Alias for channel 10 TRANS_COUNT register CH10_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x02a8 Alias for channel 10 READ_ADDR register CH10_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x02ac Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32390,28 +32741,28 @@ 0x00000000 - read-only + read-write 0x02b0 Alias for channel 10 CTRL register CH10_AL3_CTRL 0x00000000 - read-only + read-write 0x02b4 Alias for channel 10 WRITE_ADDR register CH10_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x02b8 Alias for channel 10 TRANS_COUNT register CH10_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x02bc Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32615,28 +32966,28 @@ 0x00005800 - read-only + read-write 0x02d0 Alias for channel 11 CTRL register CH11_AL1_CTRL 0x00000000 - read-only + read-write 0x02d4 Alias for channel 11 READ_ADDR register CH11_AL1_READ_ADDR 0x00000000 - read-only + read-write 0x02d8 Alias for channel 11 WRITE_ADDR register CH11_AL1_WRITE_ADDR 0x00000000 - read-only + read-write 0x02dc Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32645,28 +32996,28 @@ 0x00000000 - read-only + read-write 0x02e0 Alias for channel 11 CTRL register CH11_AL2_CTRL 0x00000000 - read-only + read-write 0x02e4 Alias for channel 11 TRANS_COUNT register CH11_AL2_TRANS_COUNT 0x00000000 - read-only + read-write 0x02e8 Alias for channel 11 READ_ADDR register CH11_AL2_READ_ADDR 0x00000000 - read-only + read-write 0x02ec Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -32675,28 +33026,28 @@ 0x00000000 - read-only + read-write 0x02f0 Alias for channel 11 CTRL register CH11_AL3_CTRL 0x00000000 - read-only + read-write 0x02f4 Alias for channel 11 WRITE_ADDR register CH11_AL3_WRITE_ADDR 0x00000000 - read-only + read-write 0x02f8 Alias for channel 11 TRANS_COUNT register CH11_AL3_TRANS_COUNT 0x00000000 - read-only + read-write 0x02fc Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n @@ -33052,8 +33403,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH0_DBG_CTDREQ @@ -33072,8 +33424,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH1_DBG_CTDREQ @@ -33092,8 +33445,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH2_DBG_CTDREQ @@ -33112,8 +33466,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH3_DBG_CTDREQ @@ -33132,8 +33487,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH4_DBG_CTDREQ @@ -33152,8 +33508,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH5_DBG_CTDREQ @@ -33172,8 +33529,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH6_DBG_CTDREQ @@ -33192,8 +33550,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH7_DBG_CTDREQ @@ -33212,8 +33571,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH8_DBG_CTDREQ @@ -33232,8 +33592,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH9_DBG_CTDREQ @@ -33252,8 +33613,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH10_DBG_CTDREQ @@ -33272,8 +33634,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH11_DBG_CTDREQ @@ -33291,6 +33654,5613 @@ 32 1 + + + 0 + 0x0100 + registers + + 0x50100000 + DPRAM layout for USB device. + USBCTRL_DPRAM + + + 0x0000 + Bytes 0-3 of the SETUP packet from the host. + + + read-write + [31:16] + WVALUE + + + read-write + [15:8] + BREQUEST + + + read-write + [7:0] + BMREQUESTTYPE + + + SETUP_PACKET_LOW + 0x00000000 + + + 0x0004 + Bytes 4-7 of the setup packet from the host. + + + read-write + [31:16] + WLENGTH + + + read-write + [15:0] + WINDEX + + + SETUP_PACKET_HIGH + 0x00000000 + + + 0x0008 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP1_IN_CONTROL + 0x00000000 + + + 0x000c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP1_OUT_CONTROL + 0x00000000 + + + 0x0010 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP2_IN_CONTROL + 0x00000000 + + + 0x0014 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP2_OUT_CONTROL + 0x00000000 + + + 0x0018 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP3_IN_CONTROL + 0x00000000 + + + 0x001c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP3_OUT_CONTROL + 0x00000000 + + + 0x0020 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP4_IN_CONTROL + 0x00000000 + + + 0x0024 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP4_OUT_CONTROL + 0x00000000 + + + 0x0028 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP5_IN_CONTROL + 0x00000000 + + + 0x002c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP5_OUT_CONTROL + 0x00000000 + + + 0x0030 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP6_IN_CONTROL + 0x00000000 + + + 0x0034 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP6_OUT_CONTROL + 0x00000000 + + + 0x0038 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP7_IN_CONTROL + 0x00000000 + + + 0x003c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP7_OUT_CONTROL + 0x00000000 + + + 0x0040 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP8_IN_CONTROL + 0x00000000 + + + 0x0044 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP8_OUT_CONTROL + 0x00000000 + + + 0x0048 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP9_IN_CONTROL + 0x00000000 + + + 0x004c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP9_OUT_CONTROL + 0x00000000 + + + 0x0050 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP10_IN_CONTROL + 0x00000000 + + + 0x0054 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP10_OUT_CONTROL + 0x00000000 + + + 0x0058 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP11_IN_CONTROL + 0x00000000 + + + 0x005c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP11_OUT_CONTROL + 0x00000000 + + + 0x0060 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP12_IN_CONTROL + 0x00000000 + + + 0x0064 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP12_OUT_CONTROL + 0x00000000 + + + 0x0068 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP13_IN_CONTROL + 0x00000000 + + + 0x006c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP13_OUT_CONTROL + 0x00000000 + + + 0x0070 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP14_IN_CONTROL + 0x00000000 + + + 0x0074 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP14_OUT_CONTROL + 0x00000000 + + + 0x0078 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP15_IN_CONTROL + 0x00000000 + + + 0x007c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP15_OUT_CONTROL + 0x00000000 + + + 0x0080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP0_IN_BUFFER_CONTROL + 0x00000000 + + + 0x0084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP0_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP1_IN_BUFFER_CONTROL + 0x00000000 + + + 0x008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP1_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP2_IN_BUFFER_CONTROL + 0x00000000 + + + 0x0094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP2_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP3_IN_BUFFER_CONTROL + 0x00000000 + + + 0x009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP3_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP4_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP4_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP5_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP5_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP6_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP6_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP7_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP7_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP8_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP8_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP9_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP9_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP10_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP10_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP11_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP11_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP12_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP12_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP13_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP13_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP14_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP14_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP15_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 0. + LENGTH_0 + + + EP15_OUT_BUFFER_CONTROL + 0x00000000 + + + 32 + 1 + 0 @@ -34103,9 +40073,10 @@ SETUP_REC - read-only + read-write [16:16] Device: connected + oneToClear CONNECTED @@ -34122,15 +40093,17 @@ VBUS_OVER_CURR - read-only + read-write [9:8] Host: device speed. Disconnected = 00, LS = 01, FS = 10 + oneToClear SPEED - read-only + read-write [4:4] Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + oneToClear SUSPENDED @@ -34168,163 +40141,195 @@ Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - read-only + read-write [31:31] + oneToClear EP15_OUT - read-only + read-write [30:30] + oneToClear EP15_IN - read-only + read-write [29:29] + oneToClear EP14_OUT - read-only + read-write [28:28] + oneToClear EP14_IN - read-only + read-write [27:27] + oneToClear EP13_OUT - read-only + read-write [26:26] + oneToClear EP13_IN - read-only + read-write [25:25] + oneToClear EP12_OUT - read-only + read-write [24:24] + oneToClear EP12_IN - read-only + read-write [23:23] + oneToClear EP11_OUT - read-only + read-write [22:22] + oneToClear EP11_IN - read-only + read-write [21:21] + oneToClear EP10_OUT - read-only + read-write [20:20] + oneToClear EP10_IN - read-only + read-write [19:19] + oneToClear EP9_OUT - read-only + read-write [18:18] + oneToClear EP9_IN - read-only + read-write [17:17] + oneToClear EP8_OUT - read-only + read-write [16:16] + oneToClear EP8_IN - read-only + read-write [15:15] + oneToClear EP7_OUT - read-only + read-write [14:14] + oneToClear EP7_IN - read-only + read-write [13:13] + oneToClear EP6_OUT - read-only + read-write [12:12] + oneToClear EP6_IN - read-only + read-write [11:11] + oneToClear EP5_OUT - read-only + read-write [10:10] + oneToClear EP5_IN - read-only + read-write [9:9] + oneToClear EP4_OUT - read-only + read-write [8:8] + oneToClear EP4_IN - read-only + read-write [7:7] + oneToClear EP3_OUT - read-only + read-write [6:6] + oneToClear EP3_IN - read-only + read-write [5:5] + oneToClear EP2_OUT - read-only + read-write [4:4] + oneToClear EP2_IN - read-only + read-write [3:3] + oneToClear EP1_OUT - read-only + read-write [2:2] + oneToClear EP1_IN - read-only + read-write [1:1] + oneToClear EP0_OUT - read-only + read-write [0:0] + oneToClear EP0_IN @@ -35468,7 +41473,7 @@ read-only [11:11] - Source: SIE_STATUS.VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT @@ -35596,7 +41601,7 @@ read-write [11:11] - Source: SIE_STATUS.VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT @@ -35724,7 +41729,7 @@ read-write [11:11] - Source: SIE_STATUS.VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT @@ -35852,7 +41857,7 @@ read-only [11:11] - Source: SIE_STATUS.VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT @@ -35954,23 +41959,24 @@ read-write [11:8] - Force clock dividers to restart their count and clear fractional\n - accumulators. Restart multiple dividers to synchronise them. + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. clear CLKDIV_RESTART read-write [7:4] - Clear internal SM state which is otherwise difficult to access\n - (e.g. shift counters). Self-clearing. + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. clear SM_RESTART read-write [3:0] - Enable state machine + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. SM_ENABLE @@ -36016,28 +42022,28 @@ read-write [27:24] - State machine has stalled on empty TX FIFO. Write 1 to clear. + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. oneToClear TXSTALL read-write [19:16] - TX FIFO overflow has occurred. Write 1 to clear. + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. oneToClear TXOVER read-write [11:8] - RX FIFO underflow has occurred. Write 1 to clear. + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. oneToClear RXUNDER read-write [3:0] - State machine has stalled on full RX FIFO. Write 1 to clear. + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. oneToClear RXSTALL @@ -36096,62 +42102,63 @@ write-only 0x0010 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF0 0x00000000 write-only 0x0014 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF1 0x00000000 write-only 0x0018 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF2 0x00000000 write-only 0x001c - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF3 0x00000000 read-only 0x0020 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF0 0x00000000 read-only 0x0024 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF1 0x00000000 read-only 0x0028 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF2 0x00000000 read-only 0x002c - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF3 0x00000000 0x0030 - Interrupt request register. Write 1 to clear + State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n + Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. read-write @@ -36165,10 +42172,7 @@ 0x0034 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.\n - Note this is different to the INTF register: writing here affects PIO internal\n - state. INTF just asserts the processor-facing IRQ signal for testing ISRs,\n - and is not visible to the state machines. + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. write-only @@ -36182,10 +42186,7 @@ read-write 0x0038 - There is a 2-flipflop synchronizer on each GPIO input, which protects\n - PIO logic from metastabilities. This increases input delay, and for fast\n - synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n - Each bit in this register corresponds to one GPIO.\n + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes. @@ -36195,14 +42196,14 @@ read-only 0x003c - Read to sample the pad output values PIO is currently driving to the GPIOs. + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. DBG_PADOUT 0x00000000 read-only 0x0040 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. DBG_PADOE 0x00000000 @@ -36240,7 +42241,7 @@ Write-only access to instruction memory location 0 - read-write + write-only [15:0] INSTR_MEM0 @@ -36253,7 +42254,7 @@ Write-only access to instruction memory location 1 - read-write + write-only [15:0] INSTR_MEM1 @@ -36266,7 +42267,7 @@ Write-only access to instruction memory location 2 - read-write + write-only [15:0] INSTR_MEM2 @@ -36279,7 +42280,7 @@ Write-only access to instruction memory location 3 - read-write + write-only [15:0] INSTR_MEM3 @@ -36292,7 +42293,7 @@ Write-only access to instruction memory location 4 - read-write + write-only [15:0] INSTR_MEM4 @@ -36305,7 +42306,7 @@ Write-only access to instruction memory location 5 - read-write + write-only [15:0] INSTR_MEM5 @@ -36318,7 +42319,7 @@ Write-only access to instruction memory location 6 - read-write + write-only [15:0] INSTR_MEM6 @@ -36331,7 +42332,7 @@ Write-only access to instruction memory location 7 - read-write + write-only [15:0] INSTR_MEM7 @@ -36344,7 +42345,7 @@ Write-only access to instruction memory location 8 - read-write + write-only [15:0] INSTR_MEM8 @@ -36357,7 +42358,7 @@ Write-only access to instruction memory location 9 - read-write + write-only [15:0] INSTR_MEM9 @@ -36370,7 +42371,7 @@ Write-only access to instruction memory location 10 - read-write + write-only [15:0] INSTR_MEM10 @@ -36383,7 +42384,7 @@ Write-only access to instruction memory location 11 - read-write + write-only [15:0] INSTR_MEM11 @@ -36396,7 +42397,7 @@ Write-only access to instruction memory location 12 - read-write + write-only [15:0] INSTR_MEM12 @@ -36409,7 +42410,7 @@ Write-only access to instruction memory location 13 - read-write + write-only [15:0] INSTR_MEM13 @@ -36422,7 +42423,7 @@ Write-only access to instruction memory location 14 - read-write + write-only [15:0] INSTR_MEM14 @@ -36435,7 +42436,7 @@ Write-only access to instruction memory location 15 - read-write + write-only [15:0] INSTR_MEM15 @@ -36448,7 +42449,7 @@ Write-only access to instruction memory location 16 - read-write + write-only [15:0] INSTR_MEM16 @@ -36461,7 +42462,7 @@ Write-only access to instruction memory location 17 - read-write + write-only [15:0] INSTR_MEM17 @@ -36474,7 +42475,7 @@ Write-only access to instruction memory location 18 - read-write + write-only [15:0] INSTR_MEM18 @@ -36487,7 +42488,7 @@ Write-only access to instruction memory location 19 - read-write + write-only [15:0] INSTR_MEM19 @@ -36500,7 +42501,7 @@ Write-only access to instruction memory location 20 - read-write + write-only [15:0] INSTR_MEM20 @@ -36513,7 +42514,7 @@ Write-only access to instruction memory location 21 - read-write + write-only [15:0] INSTR_MEM21 @@ -36526,7 +42527,7 @@ Write-only access to instruction memory location 22 - read-write + write-only [15:0] INSTR_MEM22 @@ -36539,7 +42540,7 @@ Write-only access to instruction memory location 23 - read-write + write-only [15:0] INSTR_MEM23 @@ -36552,7 +42553,7 @@ Write-only access to instruction memory location 24 - read-write + write-only [15:0] INSTR_MEM24 @@ -36565,7 +42566,7 @@ Write-only access to instruction memory location 25 - read-write + write-only [15:0] INSTR_MEM25 @@ -36578,7 +42579,7 @@ Write-only access to instruction memory location 26 - read-write + write-only [15:0] INSTR_MEM26 @@ -36591,7 +42592,7 @@ Write-only access to instruction memory location 27 - read-write + write-only [15:0] INSTR_MEM27 @@ -36604,7 +42605,7 @@ Write-only access to instruction memory location 28 - read-write + write-only [15:0] INSTR_MEM28 @@ -36617,7 +42618,7 @@ Write-only access to instruction memory location 29 - read-write + write-only [15:0] INSTR_MEM29 @@ -36630,7 +42631,7 @@ Write-only access to instruction memory location 30 - read-write + write-only [15:0] INSTR_MEM30 @@ -36643,7 +42644,7 @@ Write-only access to instruction memory location 31 - read-write + write-only [15:0] INSTR_MEM31 @@ -36653,20 +42654,20 @@ 0x00c8 - Clock divider register for state machine 0\n + Clock divisor register for state machine 0\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] - Effective frequency is sysclk/int.\n - Value of 0 is interpreted as max possible value + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] - Fractional part of clock divider + Fractional part of clock divisor FRAC @@ -36680,22 +42681,19 @@ read-only [31:31] - An instruction written to SMx_INSTR is stalled, and latched by the\n - state machine. Will clear once the instruction completes. + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] - If 1, the delay MSB is used as side-set enable, rather than a\n - side-set data bit. This allows instructions to perform side-set optionally,\n - rather than on every instruction. + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] - Side-set data is asserted to pin OEs instead of pin values + If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR @@ -36789,14 +42787,14 @@ read-write [29:25] - Number of bits shifted out of TXSR before autopull or conditional pull.\n + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] - Number of bits shifted into RXSR before autopush or conditional push.\n + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH @@ -36815,13 +42813,13 @@ read-write [17:17] - Pull automatically when the output shift register is emptied + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] - Push automatically when the input shift register is filled + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH @@ -36843,7 +42841,7 @@ 0x00d8 - Instruction currently being executed by state machine 0\n + Read to see the instruction currently addressed by state machine 0's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. @@ -36862,43 +42860,43 @@ read-write [31:29] - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] - The number of pins asserted by a SET. Max of 5 + The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] - The number of pins asserted by an OUT. Value of 0 -> 32 pins + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] - The virtual pin corresponding to IN bit 0 + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] - The virtual pin corresponding to delay field bit 0 + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] - The virtual pin corresponding to SET bit 0 + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] - The virtual pin corresponding to OUT bit 0 + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE @@ -36907,20 +42905,20 @@ 0x00e0 - Clock divider register for state machine 1\n + Clock divisor register for state machine 1\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] - Effective frequency is sysclk/int.\n - Value of 0 is interpreted as max possible value + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] - Fractional part of clock divider + Fractional part of clock divisor FRAC @@ -36934,22 +42932,19 @@ read-only [31:31] - An instruction written to SMx_INSTR is stalled, and latched by the\n - state machine. Will clear once the instruction completes. + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] - If 1, the delay MSB is used as side-set enable, rather than a\n - side-set data bit. This allows instructions to perform side-set optionally,\n - rather than on every instruction. + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] - Side-set data is asserted to pin OEs instead of pin values + If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR @@ -37043,14 +43038,14 @@ read-write [29:25] - Number of bits shifted out of TXSR before autopull or conditional pull.\n + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] - Number of bits shifted into RXSR before autopush or conditional push.\n + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH @@ -37069,13 +43064,13 @@ read-write [17:17] - Pull automatically when the output shift register is emptied + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] - Push automatically when the input shift register is filled + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH @@ -37097,7 +43092,7 @@ 0x00f0 - Instruction currently being executed by state machine 1\n + Read to see the instruction currently addressed by state machine 1's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. @@ -37116,43 +43111,43 @@ read-write [31:29] - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] - The number of pins asserted by a SET. Max of 5 + The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] - The number of pins asserted by an OUT. Value of 0 -> 32 pins + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] - The virtual pin corresponding to IN bit 0 + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] - The virtual pin corresponding to delay field bit 0 + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] - The virtual pin corresponding to SET bit 0 + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] - The virtual pin corresponding to OUT bit 0 + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE @@ -37161,20 +43156,20 @@ 0x00f8 - Clock divider register for state machine 2\n + Clock divisor register for state machine 2\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] - Effective frequency is sysclk/int.\n - Value of 0 is interpreted as max possible value + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] - Fractional part of clock divider + Fractional part of clock divisor FRAC @@ -37188,22 +43183,19 @@ read-only [31:31] - An instruction written to SMx_INSTR is stalled, and latched by the\n - state machine. Will clear once the instruction completes. + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] - If 1, the delay MSB is used as side-set enable, rather than a\n - side-set data bit. This allows instructions to perform side-set optionally,\n - rather than on every instruction. + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] - Side-set data is asserted to pin OEs instead of pin values + If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR @@ -37297,14 +43289,14 @@ read-write [29:25] - Number of bits shifted out of TXSR before autopull or conditional pull.\n + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] - Number of bits shifted into RXSR before autopush or conditional push.\n + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH @@ -37323,13 +43315,13 @@ read-write [17:17] - Pull automatically when the output shift register is emptied + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] - Push automatically when the input shift register is filled + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH @@ -37351,7 +43343,7 @@ 0x0108 - Instruction currently being executed by state machine 2\n + Read to see the instruction currently addressed by state machine 2's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. @@ -37370,43 +43362,43 @@ read-write [31:29] - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] - The number of pins asserted by a SET. Max of 5 + The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] - The number of pins asserted by an OUT. Value of 0 -> 32 pins + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] - The virtual pin corresponding to IN bit 0 + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] - The virtual pin corresponding to delay field bit 0 + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] - The virtual pin corresponding to SET bit 0 + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] - The virtual pin corresponding to OUT bit 0 + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE @@ -37415,20 +43407,20 @@ 0x0110 - Clock divider register for state machine 3\n + Clock divisor register for state machine 3\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] - Effective frequency is sysclk/int.\n - Value of 0 is interpreted as max possible value + Effective frequency is sysclk/(int + frac/256).\n + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] - Fractional part of clock divider + Fractional part of clock divisor FRAC @@ -37442,22 +43434,19 @@ read-only [31:31] - An instruction written to SMx_INSTR is stalled, and latched by the\n - state machine. Will clear once the instruction completes. + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] - If 1, the delay MSB is used as side-set enable, rather than a\n - side-set data bit. This allows instructions to perform side-set optionally,\n - rather than on every instruction. + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] - Side-set data is asserted to pin OEs instead of pin values + If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR @@ -37551,14 +43540,14 @@ read-write [29:25] - Number of bits shifted out of TXSR before autopull or conditional pull.\n + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] - Number of bits shifted into RXSR before autopush or conditional push.\n + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH @@ -37577,13 +43566,13 @@ read-write [17:17] - Pull automatically when the output shift register is emptied + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] - Push automatically when the input shift register is filled + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH @@ -37605,7 +43594,7 @@ 0x0120 - Instruction currently being executed by state machine 3\n + Read to see the instruction currently addressed by state machine 3's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. @@ -37624,43 +43613,43 @@ read-write [31:29] - The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] - The number of pins asserted by a SET. Max of 5 + The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] - The number of pins asserted by an OUT. Value of 0 -> 32 pins + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] - The virtual pin corresponding to IN bit 0 + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] - The virtual pin corresponding to delay field bit 0 + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] - The virtual pin corresponding to SET bit 0 + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] - The virtual pin corresponding to OUT bit 0 + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE @@ -38237,7 +44226,7 @@ GPIO output value set - read-write + write-only [29:0] Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` GPIO_OUT_SET @@ -38251,7 +44240,7 @@ GPIO output value clear - read-write + write-only [29:0] Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` GPIO_OUT_CLR @@ -38265,7 +44254,7 @@ GPIO output value XOR - read-write + write-only [29:0] Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` GPIO_OUT_XOR @@ -38297,7 +44286,7 @@ GPIO output enable set - read-write + write-only [29:0] Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` GPIO_OE_SET @@ -38311,7 +44300,7 @@ GPIO output enable clear - read-write + write-only [29:0] Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` GPIO_OE_CLR @@ -38325,7 +44314,7 @@ GPIO output enable XOR - read-write + write-only [29:0] Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` GPIO_OE_XOR @@ -38357,7 +44346,7 @@ QSPI output value set - read-write + write-only [5:0] Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` GPIO_HI_OUT_SET @@ -38371,7 +44360,7 @@ QSPI output value clear - read-write + write-only [5:0] Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` GPIO_HI_OUT_CLR @@ -38385,7 +44374,7 @@ QSPI output value XOR - read-write + write-only [5:0] Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` GPIO_HI_OUT_XOR @@ -38417,7 +44406,7 @@ QSPI output enable set - read-write + write-only [5:0] Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` GPIO_HI_OE_SET @@ -38431,7 +44420,7 @@ QSPI output enable clear - read-write + write-only [5:0] Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` GPIO_HI_OE_CLR @@ -38445,7 +44434,7 @@ QSPI output enable XOR - read-write + write-only [5:0] Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` GPIO_HI_OE_XOR @@ -38862,7 +44851,7 @@ 0x00000000 - read-write + write-only 0x00bc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. @@ -39124,7 +45113,7 @@ 0x00000000 - read-write + write-only 0x00fc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. @@ -39132,7 +45121,7 @@ 0x00000000 - read-only + read-write 0x0100 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39144,7 +45133,7 @@ 0x00000000 - read-only + read-write 0x0104 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39156,7 +45145,7 @@ 0x00000000 - read-only + read-write 0x0108 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39168,7 +45157,7 @@ 0x00000000 - read-only + read-write 0x010c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39180,7 +45169,7 @@ 0x00000000 - read-only + read-write 0x0110 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39192,7 +45181,7 @@ 0x00000000 - read-only + read-write 0x0114 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39204,7 +45193,7 @@ 0x00000000 - read-only + read-write 0x0118 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39216,7 +45205,7 @@ 0x00000000 - read-only + read-write 0x011c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39228,7 +45217,7 @@ 0x00000000 - read-only + read-write 0x0120 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39240,7 +45229,7 @@ 0x00000000 - read-only + read-write 0x0124 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39252,7 +45241,7 @@ 0x00000000 - read-only + read-write 0x0128 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39264,7 +45253,7 @@ 0x00000000 - read-only + read-write 0x012c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39276,7 +45265,7 @@ 0x00000000 - read-only + read-write 0x0130 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39288,7 +45277,7 @@ 0x00000000 - read-only + read-write 0x0134 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39300,7 +45289,7 @@ 0x00000000 - read-only + read-write 0x0138 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39312,7 +45301,7 @@ 0x00000000 - read-only + read-write 0x013c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39324,7 +45313,7 @@ 0x00000000 - read-only + read-write 0x0140 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39336,7 +45325,7 @@ 0x00000000 - read-only + read-write 0x0144 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39348,7 +45337,7 @@ 0x00000000 - read-only + read-write 0x0148 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39360,7 +45349,7 @@ 0x00000000 - read-only + read-write 0x014c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39372,7 +45361,7 @@ 0x00000000 - read-only + read-write 0x0150 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39384,7 +45373,7 @@ 0x00000000 - read-only + read-write 0x0154 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39396,7 +45385,7 @@ 0x00000000 - read-only + read-write 0x0158 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39408,7 +45397,7 @@ 0x00000000 - read-only + read-write 0x015c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39420,7 +45409,7 @@ 0x00000000 - read-only + read-write 0x0160 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39432,7 +45421,7 @@ 0x00000000 - read-only + read-write 0x0164 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39444,7 +45433,7 @@ 0x00000000 - read-only + read-write 0x0168 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39456,7 +45445,7 @@ 0x00000000 - read-only + read-write 0x016c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39468,7 +45457,7 @@ 0x00000000 - read-only + read-write 0x0170 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39480,7 +45469,7 @@ 0x00000000 - read-only + read-write 0x0174 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39492,7 +45481,7 @@ 0x00000000 - read-only + read-write 0x0178 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n @@ -39504,7 +45493,7 @@ 0x00000000 - read-only + read-write 0x017c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h index 559b5f17727..c47e9d4539b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h @@ -1,27 +1,90 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_ADC_H #define _HARDWARE_STRUCTS_ADC_H #include "hardware/address_mapped.h" #include "hardware/regs/adc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling + // 0x00007000 [14:12] : AINSEL (0): Select analog mux input + // 0x00000400 [10] : ERR_STICKY (0): Some past ADC conversion encountered an error + // 0x00000200 [9] : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy + // 0x00000100 [8] : READY (0): 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] : START_MANY (0): Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] : START_ONCE (0): Start a single conversion + // 0x00000002 [1] : TS_EN (0): Power on temperature sensor + // 0x00000001 [0] : EN (0): Power on ADC and enable its clock io_rw_32 cs; - io_rw_32 result; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] : RESULT (0) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] : OVER (0): 1 if the FIFO has been overflowed + // 0x00000400 [10] : UNDER (0): 1 if the FIFO has been underflowed + // 0x00000200 [9] : FULL (0) + // 0x00000100 [8] : EMPTY (0) + // 0x00000008 [3] : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result + // 0x00000002 [1] : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] : EN (0): If 1: write result to the FIFO after each conversion io_rw_32 fcs; - io_rw_32 fifo; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] : ERR (0): 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] : VAL (0) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] : INT (0): Integer part of clock divisor + // 0x000000ff [7:0] : FRAC (0): Fractional part of clock divisor io_rw_32 div; - io_rw_32 intr; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level io_rw_32 intf; - io_rw_32 ints; -} adc_hw_t; -check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; #define adc_hw ((adc_hw_t *const)ADC_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h index ce95a7c1984..81118a8f3cd 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h @@ -1,14 +1,25 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_BUS_CTRL_H #define _HARDWARE_STRUCTS_BUS_CTRL_H #include "hardware/address_mapped.h" #include "hardware/regs/busctrl.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + enum bus_ctrl_perf_counter { arbiter_rom_perf_event_access = 19, arbiter_rom_perf_event_access_contested = 18, @@ -33,15 +44,33 @@ enum bus_ctrl_perf_counter { }; typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] : PERFCTR0 (0): Busfabric saturating performance counter 0 + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000001f [4:0] : PERFSEL0 (0x1f): Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] : DMA_W (0): 0 - low priority, 1 - high priority + // 0x00000100 [8] : DMA_R (0): 0 - low priority, 1 - high priority + // 0x00000010 [4] : PROC1 (0): 0 - low priority, 1 - high priority + // 0x00000001 [0] : PROC0 (0): 0 - low priority, 1 - high priority io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels io_ro_32 priority_ack; - struct { - io_rw_32 value; - io_rw_32 sel; - } counter[4]; -} bus_ctrl_hw_t; -check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); + bus_ctrl_perf_hw_t counter[4]; +} bus_ctrl_hw_t; #define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h index 489876d1698..a245dbd48a2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +10,16 @@ #define _HARDWARE_STRUCTS_CLOCKS_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/clocks.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /*! \brief Enumeration identifying a hardware clock * \ingroup hardware_clocks */ @@ -32,41 +41,286 @@ enum clock_index { /// \tag::clock_hw[] typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock + // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock + // 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors + // 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly + // 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator + // 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // Clock divisor, can be changed on-the-fly + // 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16 + // 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor io_rw_32 div; - io_rw_32 selected; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which SRC is currently selected by the glitchless mux (one-hot) + io_ro_32 selected; } clock_hw_t; /// \end::clock_hw[] typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected + // 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only + // 0x00000100 [8] : ENABLE (0): Enable resus + // 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1 + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] : FC0_REF_KHZ (0) io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] : FC0_MIN_KHZ (0) io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff) io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + // 0x00000007 [2:0] : FC0_DELAY (1) io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] : FC0_INTERVAL (0x8) io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + // 0x000000ff [7:0] : FC0_SRC (0) io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] : DIED (0): Test clock stopped during test + // 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] : FAIL (0): Test failed + // 0x00001000 [12] : WAITING (0): Waiting for test clock to start + // 0x00000100 [8] : RUNNING (0): Test running + // 0x00000010 [4] : DONE (0): Test complete + // 0x00000001 [0] : PASS (0): Test passed io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] : KHZ (0) + // 0x0000001f [4:0] : FRAC (0) io_ro_32 result; } fc_hw_t; typedef struct { - clock_hw_t clk[CLK_COUNT]; - struct { - io_rw_32 ctrl; - io_rw_32 status; - } resus; + clock_hw_t clk[CLK_COUNT]; // 10 + + clock_resus_hw_t resus; + fc_hw_t fc0; + + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] : clk_sys_sram3 (1) + // 0x40000000 [30] : clk_sys_sram2 (1) + // 0x20000000 [29] : clk_sys_sram1 (1) + // 0x10000000 [28] : clk_sys_sram0 (1) + // 0x08000000 [27] : clk_sys_spi1 (1) + // 0x04000000 [26] : clk_peri_spi1 (1) + // 0x02000000 [25] : clk_sys_spi0 (1) + // 0x01000000 [24] : clk_peri_spi0 (1) + // 0x00800000 [23] : clk_sys_sio (1) + // 0x00400000 [22] : clk_sys_rtc (1) + // 0x00200000 [21] : clk_rtc_rtc (1) + // 0x00100000 [20] : clk_sys_rosc (1) + // 0x00080000 [19] : clk_sys_rom (1) + // 0x00040000 [18] : clk_sys_resets (1) + // 0x00020000 [17] : clk_sys_pwm (1) + // 0x00010000 [16] : clk_sys_psm (1) + // 0x00008000 [15] : clk_sys_pll_usb (1) + // 0x00004000 [14] : clk_sys_pll_sys (1) + // 0x00002000 [13] : clk_sys_pio1 (1) + // 0x00001000 [12] : clk_sys_pio0 (1) + // 0x00000800 [11] : clk_sys_pads (1) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) + // 0x00000200 [9] : clk_sys_jtag (1) + // 0x00000100 [8] : clk_sys_io (1) + // 0x00000080 [7] : clk_sys_i2c1 (1) + // 0x00000040 [6] : clk_sys_i2c0 (1) + // 0x00000020 [5] : clk_sys_dma (1) + // 0x00000010 [4] : clk_sys_busfabric (1) + // 0x00000008 [3] : clk_sys_busctrl (1) + // 0x00000004 [2] : clk_sys_adc (1) + // 0x00000002 [1] : clk_adc_adc (1) + // 0x00000001 [0] : clk_sys_clocks (1) io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x00004000 [14] : clk_sys_xosc (1) + // 0x00002000 [13] : clk_sys_xip (1) + // 0x00001000 [12] : clk_sys_watchdog (1) + // 0x00000800 [11] : clk_usb_usbctrl (1) + // 0x00000400 [10] : clk_sys_usbctrl (1) + // 0x00000200 [9] : clk_sys_uart1 (1) + // 0x00000100 [8] : clk_peri_uart1 (1) + // 0x00000080 [7] : clk_sys_uart0 (1) + // 0x00000040 [6] : clk_peri_uart0 (1) + // 0x00000020 [5] : clk_sys_timer (1) + // 0x00000010 [4] : clk_sys_tbman (1) + // 0x00000008 [3] : clk_sys_sysinfo (1) + // 0x00000004 [2] : clk_sys_syscfg (1) + // 0x00000002 [1] : clk_sys_sram5 (1) + // 0x00000001 [0] : clk_sys_sram4 (1) io_rw_32 wake_en1; + + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] : clk_sys_sram3 (1) + // 0x40000000 [30] : clk_sys_sram2 (1) + // 0x20000000 [29] : clk_sys_sram1 (1) + // 0x10000000 [28] : clk_sys_sram0 (1) + // 0x08000000 [27] : clk_sys_spi1 (1) + // 0x04000000 [26] : clk_peri_spi1 (1) + // 0x02000000 [25] : clk_sys_spi0 (1) + // 0x01000000 [24] : clk_peri_spi0 (1) + // 0x00800000 [23] : clk_sys_sio (1) + // 0x00400000 [22] : clk_sys_rtc (1) + // 0x00200000 [21] : clk_rtc_rtc (1) + // 0x00100000 [20] : clk_sys_rosc (1) + // 0x00080000 [19] : clk_sys_rom (1) + // 0x00040000 [18] : clk_sys_resets (1) + // 0x00020000 [17] : clk_sys_pwm (1) + // 0x00010000 [16] : clk_sys_psm (1) + // 0x00008000 [15] : clk_sys_pll_usb (1) + // 0x00004000 [14] : clk_sys_pll_sys (1) + // 0x00002000 [13] : clk_sys_pio1 (1) + // 0x00001000 [12] : clk_sys_pio0 (1) + // 0x00000800 [11] : clk_sys_pads (1) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) + // 0x00000200 [9] : clk_sys_jtag (1) + // 0x00000100 [8] : clk_sys_io (1) + // 0x00000080 [7] : clk_sys_i2c1 (1) + // 0x00000040 [6] : clk_sys_i2c0 (1) + // 0x00000020 [5] : clk_sys_dma (1) + // 0x00000010 [4] : clk_sys_busfabric (1) + // 0x00000008 [3] : clk_sys_busctrl (1) + // 0x00000004 [2] : clk_sys_adc (1) + // 0x00000002 [1] : clk_adc_adc (1) + // 0x00000001 [0] : clk_sys_clocks (1) io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x00004000 [14] : clk_sys_xosc (1) + // 0x00002000 [13] : clk_sys_xip (1) + // 0x00001000 [12] : clk_sys_watchdog (1) + // 0x00000800 [11] : clk_usb_usbctrl (1) + // 0x00000400 [10] : clk_sys_usbctrl (1) + // 0x00000200 [9] : clk_sys_uart1 (1) + // 0x00000100 [8] : clk_peri_uart1 (1) + // 0x00000080 [7] : clk_sys_uart0 (1) + // 0x00000040 [6] : clk_peri_uart0 (1) + // 0x00000020 [5] : clk_sys_timer (1) + // 0x00000010 [4] : clk_sys_tbman (1) + // 0x00000008 [3] : clk_sys_sysinfo (1) + // 0x00000004 [2] : clk_sys_syscfg (1) + // 0x00000002 [1] : clk_sys_sram5 (1) + // 0x00000001 [0] : clk_sys_sram4 (1) io_rw_32 sleep_en1; - io_rw_32 enabled0; - io_rw_32 enabled1; - io_rw_32 intr; + + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] : clk_sys_sram3 (0) + // 0x40000000 [30] : clk_sys_sram2 (0) + // 0x20000000 [29] : clk_sys_sram1 (0) + // 0x10000000 [28] : clk_sys_sram0 (0) + // 0x08000000 [27] : clk_sys_spi1 (0) + // 0x04000000 [26] : clk_peri_spi1 (0) + // 0x02000000 [25] : clk_sys_spi0 (0) + // 0x01000000 [24] : clk_peri_spi0 (0) + // 0x00800000 [23] : clk_sys_sio (0) + // 0x00400000 [22] : clk_sys_rtc (0) + // 0x00200000 [21] : clk_rtc_rtc (0) + // 0x00100000 [20] : clk_sys_rosc (0) + // 0x00080000 [19] : clk_sys_rom (0) + // 0x00040000 [18] : clk_sys_resets (0) + // 0x00020000 [17] : clk_sys_pwm (0) + // 0x00010000 [16] : clk_sys_psm (0) + // 0x00008000 [15] : clk_sys_pll_usb (0) + // 0x00004000 [14] : clk_sys_pll_sys (0) + // 0x00002000 [13] : clk_sys_pio1 (0) + // 0x00001000 [12] : clk_sys_pio0 (0) + // 0x00000800 [11] : clk_sys_pads (0) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0) + // 0x00000200 [9] : clk_sys_jtag (0) + // 0x00000100 [8] : clk_sys_io (0) + // 0x00000080 [7] : clk_sys_i2c1 (0) + // 0x00000040 [6] : clk_sys_i2c0 (0) + // 0x00000020 [5] : clk_sys_dma (0) + // 0x00000010 [4] : clk_sys_busfabric (0) + // 0x00000008 [3] : clk_sys_busctrl (0) + // 0x00000004 [2] : clk_sys_adc (0) + // 0x00000002 [1] : clk_adc_adc (0) + // 0x00000001 [0] : clk_sys_clocks (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x00004000 [14] : clk_sys_xosc (0) + // 0x00002000 [13] : clk_sys_xip (0) + // 0x00001000 [12] : clk_sys_watchdog (0) + // 0x00000800 [11] : clk_usb_usbctrl (0) + // 0x00000400 [10] : clk_sys_usbctrl (0) + // 0x00000200 [9] : clk_sys_uart1 (0) + // 0x00000100 [8] : clk_peri_uart1 (0) + // 0x00000080 [7] : clk_sys_uart0 (0) + // 0x00000040 [6] : clk_peri_uart0 (0) + // 0x00000020 [5] : clk_sys_timer (0) + // 0x00000010 [4] : clk_sys_tbman (0) + // 0x00000008 [3] : clk_sys_sysinfo (0) + // 0x00000004 [2] : clk_sys_syscfg (0) + // 0x00000002 [1] : clk_sys_sram5 (0) + // 0x00000001 [0] : clk_sys_sram4 (0) + io_ro_32 enabled1; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] : CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] : CLK_SYS_RESUS (0) io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] : CLK_SYS_RESUS (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : CLK_SYS_RESUS (0) + io_ro_32 ints; } clocks_hw_t; #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) + +static_assert( CLK_COUNT == 10, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h index 06cdf792750..0d206416a36 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,51 +10,185 @@ #define _HARDWARE_STRUCTS_DMA_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/dma.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] : READ_ERROR (0): If 1, the channel received a read bus error + // 0x20000000 [29] : WRITE_ERROR (0): If 1, the channel received a write bus error + // 0x01000000 [24] : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the... + // 0x00800000 [23] : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each... + // 0x00400000 [22] : BSWAP (0): Apply byte-swap transformation to DMA data + // 0x00200000 [21] : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block + // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal + // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO + // 0x00000400 [10] : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses + // 0x000003c0 [9:6] : RING_SIZE (0): Size of address wrap region + // 0x00000020 [5] : INCR_WRITE (0): If 1, the write address increments with each transfer + // 0x00000010 [4] : INCR_READ (0): If 1, the read address increments with each transfer + // 0x0000000c [3:2] : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in... + // 0x00000001 [0] : EN (0): DMA Channel Enable io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register io_rw_32 al3_read_addr_trig; -} dma_channel_hw_t; +} dma_channel_hw_t; typedef struct { - dma_channel_hw_t ch[NUM_DMA_CHANNELS]; - uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12 + + uint32_t _pad0[64]; + + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] : INTR (0): Raw interrupt status for DMA Channels 0 io_ro_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0 io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] : INTF0 (0): Write 1s to force the corresponding bits in INTE0 io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted io_rw_32 ints0; - uint32_t _pad1[1]; + + uint32_t _pad1; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1 io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] : INTF1 (0): Write 1s to force the corresponding bits in INTE0 io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted io_rw_32 ints1; - io_rw_32 timer[4]; - io_wo_32 multi_channel_trigger; + + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + // + // Pacing (X/Y) Fractional Timer + // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend + // 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor + io_rw_32 timer[NUM_DMA_TIMERS]; // 4 + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel + io_rw_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read + // 0x00000400 [10] : OUT_REV (0): If set, the result appears bit-reversed when read + // 0x00000200 [9] : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum + // 0x000001e0 [8:5] : CALC (0) + // 0x0000001e [4:1] : DMACH (0): DMA channel for Sniffer to observe + // 0x00000001 [0] : EN (0): Enable sniffer io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware io_rw_32 sniff_data; - uint32_t _pad2[1]; + + uint32_t _pad2; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] : WAF_LVL (0): Current Write-Address-FIFO fill level + // 0x000000ff [7:0] : TDF_LVL (0): Current Transfer-Data-FIFO fill level io_ro_32 fifo_levels; - io_wo_32 abort; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] : CHAN_ABORT (0): Each bit corresponds to a channel + io_rw_32 abort; } dma_hw_t; typedef struct { struct dma_debug_hw_channel { - io_ro_32 ctrdeq; + io_rw_32 ctrdeq; io_ro_32 tcr; uint32_t pad[14]; } ch[NUM_DMA_CHANNELS]; @@ -61,4 +197,7 @@ typedef struct { #define dma_hw ((dma_hw_t *const)DMA_BASE) #define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) +static_assert( NUM_DMA_TIMERS == 4, ""); +static_assert( NUM_DMA_CHANNELS == 12, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h index 4bc501f2886..43d60863698 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,132 +12,322 @@ #include "hardware/address_mapped.h" #include "hardware/regs/i2c.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether... + // 0x00000200 [9] : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx... + // 0x00000100 [8] : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in... + // 0x00000080 [7] : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is... + // 0x00000040 [6] : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once... + // 0x00000020 [5] : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master + // 0x00000010 [4] : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit... + // 0x00000008 [3] : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c... + // 0x00000006 [2:1] : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant... + // 0x00000001 [0] : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START... + // 0x00000400 [10] : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this... + // 0x000003ff [9:0] : IC_TAR (0x55): This is the target address for any master transaction io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave io_rw_32 sar; + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the... + // 0x00000800 [11] : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive... + // 0x00000400 [10] : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received + // 0x00000200 [9] : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received + // 0x00000100 [8] : CMD (0): This bit controls whether a read or a write is performed + // 0x000000ff [7:0] : DAT (0): This register contains the data to be transmitted or received on the I2C bus io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place... io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place... io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place... io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place... io_rw_32 fs_scl_lcnt; + uint32_t _pad1[2]; - io_rw_32 intr_stat; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit + // 0x00000800 [11] : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit + // 0x00000200 [9] : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register + // 0x00000800 [11] : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register io_rw_32 intr_mask; - io_rw_32 raw_intr_stat; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when... + // 0x00000800 [11] : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged + // 0x00000400 [10] : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface... + // 0x00000200 [9] : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless... + // 0x00000100 [8] : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared + // 0x00000080 [7] : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the... + // 0x00000040 [6] : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the... + // 0x00000020 [5] : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is... + // 0x00000010 [4] : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL... + // 0x00000008 [3] : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the... + // 0x00000004 [2] : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the... + // 0x00000002 [1] : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an... + // 0x00000001 [0] : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] : RX_TL (0): Receive FIFO Threshold Level io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] : TX_TL (0): Transmit FIFO Threshold Level io_rw_32 tx_tl; - io_rw_32 clr_intr; - io_rw_32 clr_rx_under; - io_rw_32 clr_rx_over; - io_rw_32 clr_tx_over; - io_rw_32 clr_rd_req; - io_rw_32 clr_tx_abrt; - io_rw_32 clr_rx_done; - io_rw_32 clr_activity; - io_rw_32 clr_stop_det; - io_rw_32 clr_start_det; - io_rw_32 clr_gen_call; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C Enable Register + // 0x00000004 [2] : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx... + // 0x00000002 [1] : ABORT (0): When set, the controller initiates the transfer abort + // 0x00000001 [0] : ENABLE (0): Controls whether the DW_apb_i2c is enabled io_rw_32 enable; - io_rw_32 status; - io_rw_32 txflr; - io_rw_32 rxflr; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C Status Register + // 0x00000040 [6] : SLV_ACTIVITY (0): Slave FSM Activity Status + // 0x00000020 [5] : MST_ACTIVITY (0): Master FSM Activity Status + // 0x00000010 [4] : RFF (0): Receive FIFO Completely Full + // 0x00000008 [3] : RFNE (0): Receive FIFO Not Empty + // 0x00000004 [2] : TFE (1): Transmit FIFO Completely Empty + // 0x00000002 [1] : TFNF (1): Transmit FIFO Not Full + // 0x00000001 [0] : ACTIVITY (0): I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer + // 0x0000001f [4:0] : TXFLR (0): Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer + // 0x0000001f [4:0] : RXFLR (0): Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... + // 0x0000ffff [15:0] : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... io_rw_32 sda_hold; - io_rw_32 tx_abrt_source; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed... + // 0x00010000 [16] : ABRT_USER_ABRT (0): This is a master-mode-only bit + // 0x00008000 [15] : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be... + // 0x00004000 [14] : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting... + // 0x00002000 [13] : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and... + // 0x00001000 [12] : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if... + // 0x00000800 [11] : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation... + // 0x00000400 [10] : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... + // 0x00000200 [9] : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed... + // 0x00000100 [8] : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... + // 0x00000080 [7] : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START... + // 0x00000040 [6] : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High... + // 0x00000020 [5] : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General... + // 0x00000010 [4] : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General... + // 0x00000008 [3] : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit + // 0x00000004 [2] : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that... + // 0x00000002 [1] : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the... + // 0x00000001 [0] : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] : NACK (0): Generate NACK io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] : TDMAE (0): Transmit DMA Enable + // 0x00000001 [0] : RDMAE (0): Receive DMA Enable io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] : DMATDL (0): Transmit Data Level io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // I2C Receive Data Level Register + // 0x0000000f [3:0] : DMARDL (0): Receive Data Level io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] : SDA_SETUP (0x64): SDA Setup io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] : ACK_GEN_CALL (1): ACK General Call io_rw_32 ack_general_call; - io_rw_32 enable_status; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] : SLV_RX_DATA_LOST (0): Slave Received Data Lost + // 0x00000002 [1] : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] : IC_EN (0): ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to... io_rw_32 fs_spklen; + uint32_t _pad2; - io_rw_32 clr_restart_det; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16 + // 0x0000ff00 [15:8] : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16 + // 0x00000080 [7] : ADD_ENCODED_PARAMS (0): Encoded parameters not visible + // 0x00000040 [6] : HAS_DMA (0): DMA handshaking signals are enabled + // 0x00000020 [5] : INTR_IO (0): COMBINED Interrupt outputs + // 0x00000010 [4] : HC_COUNT_VALUES (0): Programmable count values for each mode + // 0x0000000c [3:2] : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] : APB_DATA_WIDTH (0): APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] : IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; } i2c_hw_t; #define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) #define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) -// List of configuration constants for the Synopsys I2C hardware (you may see -// references to these in I2C register header; these are *fixed* values, -// set at hardware design time): - -// SLAVE_INTERFACE_TYPE .............. 0 -// REG_TIMEOUT_WIDTH ................. 4 -// REG_TIMEOUT_VALUE ................. 8 -// IC_ULTRA_FAST_MODE ................ 0x0 -// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 -// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 -// IC_TX_TL .......................... 0x0 -// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 -// IC_SS_SCL_LOW_COUNT ............... 0x01d6 -// IC_HAS_DMA ........................ 0x1 -// IC_RX_FULL_GEN_NACK ............... 0x0 -// IC_CLOCK_PERIOD ................... 100 -// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 -// IC_SMBUS_ARP ...................... 0x0 -// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 -// IC_INTR_IO ........................ 0x1 -// IC_MASTER_MODE .................... 0x1 -// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0 -// IC_INTR_POL ....................... 0x1 -// IC_OPTIONAL_SAR ................... 0x0 -// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 -// IC_DEFAULT_SLAVE_ADDR ............. 0x055 -// IC_DEFAULT_HS_SPKLEN .............. 0x1 -// IC_FS_SCL_HIGH_COUNT .............. 0x003c -// IC_HS_SCL_LOW_COUNT ............... 0x0010 -// IC_DEVICE_ID_VALUE ................ 0x0 -// IC_10BITADDR_MASTER ............... 0x0 -// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 -// IC_DEFAULT_FS_SPKLEN .............. 0xf -// IC_ADD_ENCODED_PARAMS ............. 0x1 -// IC_DEFAULT_SDA_HOLD ............... 0x000001 -// IC_DEFAULT_SDA_SETUP .............. 0x64 -// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 -// SLVERR_RESP_EN .................... 0 -// IC_RESTART_EN ..................... 0x1 -// IC_TX_CMD_BLOCK ................... 0x1 -// HC_REG_TIMEOUT_VALUE .............. 0 -// IC_BUS_CLEAR_FEATURE .............. 0x1 -// IC_CAP_LOADING .................... 100 -// IC_HAS_ASYNC_FIFO ................. 0x0 -// IC_FS_SCL_LOW_COUNT ............... 0x0082 -// APB_DATA_WIDTH .................... 32 -// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_SLV_DATA_NACK_ONLY ............. 0x1 -// IC_10BITADDR_SLAVE ................ 0x0 -// IC_TX_BUFFER_DEPTH ................ 32 -// IC_DEFAULT_UFM_SPKLEN ............. 0x1 -// IC_CLK_TYPE ....................... 0x0 -// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 -// IC_SMBUS_UDID_MSB ................. 0x0 -// IC_SMBUS_SUSPEND_ALERT ............ 0x0 -// IC_HS_SCL_HIGH_COUNT .............. 0x0006 -// IC_SLV_RESTART_DET_EN ............. 0x1 -// IC_SMBUS .......................... 0x1 -// IC_STAT_FOR_CLK_STRETCH ........... 0x1 -// IC_MAX_SPEED_MODE ................. 0x2 -// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 -// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 -// IC_USE_COUNTS ..................... 0x1 -// IC_RX_BUFFER_DEPTH ................ 32 -// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_RX_FULL_HLD_BUS_EN ............. 0x1 -// IC_SLAVE_DISABLE .................. 0x1 -// IC_RX_TL .......................... 0x0 -// IC_DEVICE_ID ...................... 0x0 -// IC_HC_COUNT_VALUES ................ 0x0 -// I2C_DYNAMIC_TAR_UPDATE ............ 1 -// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff -// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff -// IC_HS_MASTER_CODE ................. 0x1 -// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff -// IC_UFM_SCL_LOW_COUNT .............. 0x0008 -// IC_SMBUS_UDID_HC .................. 0x1 -// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff -// IC_SS_SCL_HIGH_COUNT .............. 0x0190 - #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h index 683750733b6..e96caab2f15 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,68 @@ #define _HARDWARE_STRUCTS_INTERP_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/sio.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + // + // Read/write access to accumulator 0 io_rw_32 accum[2]; + + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + // + // Read/write access to BASE0 register io_rw_32 base[3]; + + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + // + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) io_ro_32 pop[3]; + + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + // + // Read LANE0 result, without altering any internal state (PEEK) io_ro_32 peek[3]; + + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + // + // Control register for lane 0 + // 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core + // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus + // 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP + // 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware + // 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive) + // 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking io_rw_32 ctrl[2]; + + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + // + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0) io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously io_wo_32 base01; } interp_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h index b19800fa7d3..aae74b2a658 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,28 +10,207 @@ #define _HARDWARE_STRUCTS_IOBANK0_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/io_bank0.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // GPIO status + // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied + // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied + // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied + // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied + // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied + // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied + // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied + // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] : IRQOVER (0) + // 0x00030000 [17:16] : INOVER (0) + // 0x00003000 [13:12] : OEOVER (0) + // 0x00000300 [9:8] : OUTOVER (0) + // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table + io_rw_32 ctrl; +} iobank0_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + // + // Interrupt Enable for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 inte[4]; + + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + // + // Interrupt Force for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 intf[4]; - io_rw_32 ints[4]; + + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + // + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) + io_ro_32 ints[4]; } io_irq_ctrl_hw_t; /// \tag::iobank0_hw[] typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[30]; + iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30 + + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + // + // Raw Interrupts + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 intr[4]; + io_irq_ctrl_hw_t proc0_irq_ctrl; + io_irq_ctrl_hw_t proc1_irq_ctrl; + io_irq_ctrl_hw_t dormant_wake_irq_ctrl; } iobank0_hw_t; -/// \end::iobank0_hw[] #define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) +/// \end::iobank0_hw[] + +static_assert( NUM_BANK0_GPIOS == 30, ""); #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h index 48d08a7c92b..2992bfe52b2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,165 @@ #define _HARDWARE_STRUCTS_IOQSPI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/io_qspi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // GPIO status + // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied + // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied + // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied + // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied + // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied + // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied + // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied + // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] : IRQOVER (0) + // 0x00030000 [17:16] : INOVER (0) + // 0x00003000 [13:12] : OEOVER (0) + // 0x00000300 [9:8] : OUTOVER (0) + // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table + io_rw_32 ctrl; +} ioqspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_ctrl_hw_t; + typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[6]; + ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6 + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intr; + + io_qspi_ctrl_hw_t proc0_qspi_ctrl; + + io_qspi_ctrl_hw_t proc1_qspi_ctrl; + + io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl; } ioqspi_hw_t; #define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) +static_assert( NUM_QSPI_GPIOS == 6, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h index 34e5c39e81f..e6472209b42 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,11 +12,47 @@ #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE + // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports + // 0x00ff0000 [23:16] : IREGION (0): Instruction region + // 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU + // 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps io_ro_32 type; + + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL + // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled... + // 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for... + // 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] : ENABLE (0): Enables the MPU io_rw_32 ctrl; + + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR + // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR + // 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers io_rw_32 rnr; + + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR + // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR + // 0xffffff00 [31:8] : ADDR (0): Base address of the region + // 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region... + // 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided... io_rw_32 rbar; + + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR + // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region... + // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field + // 0x0000ff00 [15:8] : SRD (0): Subregion Disable + // 0x0000003e [5:1] : SIZE (0): Indicates the region size + // 0x00000001 [0] : ENABLE (0): Enables the region io_rw_32 rasr; } mpu_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h index 451d7ebc383..8036cd940bc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,38 @@ #define _HARDWARE_STRUCTS_PADS_QSPI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pads_qspi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] : VOLTAGE_SELECT (0) io_rw_32 voltage_select; - io_rw_32 io[6]; + + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + // + // Pad control register + // 0x00000080 [7] : OD (0): Output disable + // 0x00000040 [6] : IE (1): Input enable + // 0x00000030 [5:4] : DRIVE (1): Drive strength + // 0x00000008 [3] : PUE (0): Pull up enable + // 0x00000004 [2] : PDE (1): Pull down enable + // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger + // 0x00000001 [0] : SLEWFAST (0): Slew rate control + io_rw_32 io[NUM_QSPI_GPIOS]; // 6 } pads_qspi_hw_t; #define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) +static_assert( NUM_QSPI_GPIOS == 6, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h index f56dc401150..2c067fa9524 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,38 @@ #define _HARDWARE_STRUCTS_PADSBANK0_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pads_bank0.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] : VOLTAGE_SELECT (0) io_rw_32 voltage_select; - io_rw_32 io[30]; + + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + // + // Pad control register + // 0x00000080 [7] : OD (0): Output disable + // 0x00000040 [6] : IE (1): Input enable + // 0x00000030 [5:4] : DRIVE (1): Drive strength + // 0x00000008 [3] : PUE (0): Pull up enable + // 0x00000004 [2] : PDE (1): Pull down enable + // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger + // 0x00000001 [0] : SLEWFAST (0): Slew rate control + io_rw_32 io[NUM_BANK0_GPIOS]; // 30 } padsbank0_hw_t; -#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) +#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE) + +static_assert( NUM_BANK0_GPIOS == 30, ""); #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h index 176863bb4d8..515e4d1a0bd 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,41 +10,275 @@ #define _HARDWARE_STRUCTS_PIO_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pio.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + +typedef struct pio_sm_hw { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] : FRAC (0): Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine + // 0x40000000 [30] : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,... + // 0x20000000 [29] : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values + // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable + // 0x00040000 [18] : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable + // 0x00020000 [17] : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address + // 0x00000010 [4] : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction + // 0x0000000f [3:0] : STATUS_N (0): Comparison level for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep + // 0x40000000 [30] : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep + // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL... + // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH... + // 0x00080000 [19] : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right + // 0x00040000 [18] : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] : AUTOPULL (0): Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] : AUTOPUSH (0): Push automatically when the input shift register is filled, i + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] : SM0_ADDR (0) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + // 0x0000ffff [15:0] : SM0_INSTR (0) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used... + // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET + // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction + // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus + // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation + // 0x000003e0 [9:5] : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction + // 0x0000001f [4:0] : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV... + io_rw_32 pinctrl; +} pio_sm_hw_t; + typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x00000f00 [11:8] : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0 + // 0x000000f0 [7:4] : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult... + // 0x0000000f [3:0] : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty + // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full + // 0x00000f00 [11:8] : RXEMPTY (0xf): State machine RX FIFO is empty + // 0x0000000f [3:0] : RXFULL (0): State machine RX FIFO is full io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with... + // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i + // 0x00000f00 [11:8] : RXUNDER (0): RX FIFO underflow (i + // 0x0000000f [3:0] : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with... io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] : RX3 (0) + // 0x0f000000 [27:24] : TX3 (0) + // 0x00f00000 [23:20] : RX2 (0) + // 0x000f0000 [19:16] : TX2 (0) + // 0x0000f000 [15:12] : RX1 (0) + // 0x00000f00 [11:8] : TX1 (0) + // 0x000000f0 [7:4] : RX0 (0) + // 0x0000000f [3:0] : TX0 (0) io_ro_32 flevel; - io_wo_32 txf[NUM_PIO_STATE_MACHINES]; - io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; + + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + // + // Direct write access to the TX FIFO for this state machine + io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + // + // Direct read access to the RX FIFO for this state machine + io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] : IRQ (0) io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] : IRQ_FORCE (0) io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities io_rw_32 input_sync_bypass; - io_rw_32 dbg_padout; - io_rw_32 dbg_padoe; - io_rw_32 dbg_cfginfo; - io_wo_32 instr_mem[32]; - struct pio_sm_hw { - io_rw_32 clkdiv; - io_rw_32 execctrl; - io_rw_32 shiftctrl; - io_ro_32 addr; - io_rw_32 instr; - io_rw_32 pinctrl; - } sm[NUM_PIO_STATE_MACHINES]; - io_rw_32 intr; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction + // 0x00000f00 [11:8] : SM_COUNT (0): The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + // + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] : INSTR_MEM0 (0) + io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32 + + pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) + io_ro_32 intr; + + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_ro_32 ints1; } pio_hw_t; #define pio0_hw ((pio_hw_t *const)PIO0_BASE) #define pio1_hw ((pio_hw_t *const)PIO1_BASE) +static_assert( NUM_PIO_STATE_MACHINES == 4, ""); +static_assert( PIO_INSTRUCTION_COUNT == 32, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h index 4d5b5b78ccb..5a506e3e962 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,11 +12,40 @@ #include "hardware/address_mapped.h" #include "hardware/regs/pll.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::pll_hw[] typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] : LOCK (0): PLL is locked + // 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO + // 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] : VCOPD (1): PLL VCO powerdown + // 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown + // 0x00000004 [2] : DSMPD (1): PLL DSM powerdown + // 0x00000001 [0] : PD (1): PLL powerdown io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7 + // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7 io_rw_32 prim; } pll_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h index cc9fb97e07d..cdfb2e38515 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,100 @@ #define _HARDWARE_STRUCTS_PSM_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/psm.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if this peripheral should be reset when the watchdog fires + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 wdsel; - io_rw_32 done; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Indicates the peripheral's registers are ready to access + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) + io_ro_32 done; } psm_hw_t; #define psm_hw ((psm_hw_t *const)PSM_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h index 54995610939..fd9a75ca25b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,26 +10,117 @@ #define _HARDWARE_STRUCTS_PWM_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pwm.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct pwm_slice_hw { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] : PH_RET (0): Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] : DIVMODE (0) + // 0x00000008 [3] : B_INV (0): Invert output B + // 0x00000004 [2] : A_INV (0): Invert output A + // 0x00000002 [1] : PH_CORRECT (0): 1: Enable phase-correct modulation + // 0x00000001 [0] : EN (0): Enable the PWM channel io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] : INT (1) + // 0x0000000f [3:0] : FRAC (0) io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] : CH0_CTR (0) io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] : B (0) + // 0x0000ffff [15:0] : A (0) io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] : CH0_TOP (0xffff) io_rw_32 top; } pwm_slice_hw_t; typedef struct { - pwm_slice_hw_t slice[NUM_PWM_SLICES]; + pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8 + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 intr; + + _REG_(PWM_INTE_OFFSET) // PWM_INTE + // Interrupt Enable + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 inte; + + _REG_(PWM_INTF_OFFSET) // PWM_INTF + // Interrupt Force + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(PWM_INTS_OFFSET) // PWM_INTS + // Interrupt status after masking & forcing + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) + io_ro_32 ints; } pwm_hw_t; #define pwm_hw ((pwm_hw_t *const)PWM_BASE) +static_assert( NUM_PWM_SLICES == 8, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h index a96ddebd7c7..bc1c10c5e38 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h @@ -1,19 +1,113 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_RESETS_H #define _HARDWARE_STRUCTS_RESETS_H #include "hardware/address_mapped.h" #include "hardware/regs/resets.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::resets_hw[] typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // Reset control + // 0x01000000 [24] : usbctrl (1) + // 0x00800000 [23] : uart1 (1) + // 0x00400000 [22] : uart0 (1) + // 0x00200000 [21] : timer (1) + // 0x00100000 [20] : tbman (1) + // 0x00080000 [19] : sysinfo (1) + // 0x00040000 [18] : syscfg (1) + // 0x00020000 [17] : spi1 (1) + // 0x00010000 [16] : spi0 (1) + // 0x00008000 [15] : rtc (1) + // 0x00004000 [14] : pwm (1) + // 0x00002000 [13] : pll_usb (1) + // 0x00001000 [12] : pll_sys (1) + // 0x00000800 [11] : pio1 (1) + // 0x00000400 [10] : pio0 (1) + // 0x00000200 [9] : pads_qspi (1) + // 0x00000100 [8] : pads_bank0 (1) + // 0x00000080 [7] : jtag (1) + // 0x00000040 [6] : io_qspi (1) + // 0x00000020 [5] : io_bank0 (1) + // 0x00000010 [4] : i2c1 (1) + // 0x00000008 [3] : i2c0 (1) + // 0x00000004 [2] : dma (1) + // 0x00000002 [1] : busctrl (1) + // 0x00000001 [0] : adc (1) io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // Watchdog select + // 0x01000000 [24] : usbctrl (0) + // 0x00800000 [23] : uart1 (0) + // 0x00400000 [22] : uart0 (0) + // 0x00200000 [21] : timer (0) + // 0x00100000 [20] : tbman (0) + // 0x00080000 [19] : sysinfo (0) + // 0x00040000 [18] : syscfg (0) + // 0x00020000 [17] : spi1 (0) + // 0x00010000 [16] : spi0 (0) + // 0x00008000 [15] : rtc (0) + // 0x00004000 [14] : pwm (0) + // 0x00002000 [13] : pll_usb (0) + // 0x00001000 [12] : pll_sys (0) + // 0x00000800 [11] : pio1 (0) + // 0x00000400 [10] : pio0 (0) + // 0x00000200 [9] : pads_qspi (0) + // 0x00000100 [8] : pads_bank0 (0) + // 0x00000080 [7] : jtag (0) + // 0x00000040 [6] : io_qspi (0) + // 0x00000020 [5] : io_bank0 (0) + // 0x00000010 [4] : i2c1 (0) + // 0x00000008 [3] : i2c0 (0) + // 0x00000004 [2] : dma (0) + // 0x00000002 [1] : busctrl (0) + // 0x00000001 [0] : adc (0) io_rw_32 wdsel; - io_rw_32 reset_done; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // Reset done + // 0x01000000 [24] : usbctrl (0) + // 0x00800000 [23] : uart1 (0) + // 0x00400000 [22] : uart0 (0) + // 0x00200000 [21] : timer (0) + // 0x00100000 [20] : tbman (0) + // 0x00080000 [19] : sysinfo (0) + // 0x00040000 [18] : syscfg (0) + // 0x00020000 [17] : spi1 (0) + // 0x00010000 [16] : spi0 (0) + // 0x00008000 [15] : rtc (0) + // 0x00004000 [14] : pwm (0) + // 0x00002000 [13] : pll_usb (0) + // 0x00001000 [12] : pll_sys (0) + // 0x00000800 [11] : pio1 (0) + // 0x00000400 [10] : pio0 (0) + // 0x00000200 [9] : pads_qspi (0) + // 0x00000100 [8] : pads_bank0 (0) + // 0x00000080 [7] : jtag (0) + // 0x00000040 [6] : io_qspi (0) + // 0x00000020 [5] : io_bank0 (0) + // 0x00000010 [4] : i2c1 (0) + // 0x00000008 [3] : i2c0 (0) + // 0x00000004 [2] : dma (0) + // 0x00000002 [1] : busctrl (0) + // 0x00000001 [0] : adc (0) + io_ro_32 reset_done; } resets_hw_t; #define resets_hw ((resets_hw_t *const)RESETS_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h index 10543937cf4..114c6029f54 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,20 +10,75 @@ #define _HARDWARE_STRUCTS_ROSC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/rosc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE + // 0x00000fff [11:0] : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings + // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength + // 0x00000700 [10:8] : DS2 (0): Stage 2 drive strength + // 0x00000070 [6:4] : DS1 (0): Stage 1 drive strength + // 0x00000007 [2:0] : DS0 (0): Stage 0 drive strength io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // For a detailed description see freqa register + // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings + // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength + // 0x00000700 [10:8] : DS6 (0): Stage 6 drive strength + // 0x00000070 [6:4] : DS5 (0): Stage 5 drive strength + // 0x00000007 [2:0] : DS4 (0): Stage 4 drive strength io_rw_32 freqb; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x00000fff [11:0] : DIV (0): set to 0xaa0 + div where io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] : PASSWD (0): set to 0xaa + // 0x00000008 [3] : ENABLE (1): enable the phase-shifted output + // 0x00000004 [2] : FLIP (0): invert the phase-shifted output + // 0x00000003 [1:0] : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] : STABLE (0): Oscillator is running and stable + // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or... + // 0x00010000 [16] : DIV_RUNNING (0): post-divider is running + // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable io_rw_32 status; - io_rw_32 randombit; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or... + // 0x00000001 [0] : RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops + // 0x000000ff [7:0] : COUNT (0) io_rw_32 count; - io_rw_32 dftx; } rosc_hw_t; #define rosc_hw ((rosc_hw_t *const)ROSC_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h index 276bd7a2428..794a0e07ad9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,22 +10,103 @@ #define _HARDWARE_STRUCTS_RTC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/rtc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1 + // Divider minus 1 for the 1 second counter + // 0x0000ffff [15:0] : CLKDIV_M1 (0) io_rw_32 clkdiv_m1; + + _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0 + // RTC setup register 0 + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 io_rw_32 setup_0; + + _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1 + // RTC setup register 1 + // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds io_rw_32 setup_1; + + _REG_(RTC_CTRL_OFFSET) // RTC_CTRL + // RTC Control and status + // 0x00000100 [8] : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off + // 0x00000010 [4] : LOAD (0): Load RTC + // 0x00000002 [1] : RTC_ACTIVE (0): RTC enabled (running) + // 0x00000001 [0] : RTC_ENABLE (0): Enable RTC io_rw_32 ctrl; + + _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0 + // Interrupt setup register 0 + // 0x20000000 [29] : MATCH_ACTIVE (0) + // 0x10000000 [28] : MATCH_ENA (0): Global match enable + // 0x04000000 [26] : YEAR_ENA (0): Enable year matching + // 0x02000000 [25] : MONTH_ENA (0): Enable month matching + // 0x01000000 [24] : DAY_ENA (0): Enable day matching + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 io_rw_32 irq_setup_0; + + _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1 + // Interrupt setup register 1 + // 0x80000000 [31] : DOTW_ENA (0): Enable day of the week matching + // 0x40000000 [30] : HOUR_ENA (0): Enable hour matching + // 0x20000000 [29] : MIN_ENA (0): Enable minute matching + // 0x10000000 [28] : SEC_ENA (0): Enable second matching + // 0x07000000 [26:24] : DOTW (0): Day of the week + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds io_rw_32 irq_setup_1; - io_rw_32 rtc_1; - io_rw_32 rtc_0; - io_rw_32 intr; + + _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1 + // RTC register 1 + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 + io_ro_32 rtc_1; + + _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0 + // RTC register 0 + // 0x07000000 [26:24] : DOTW (0): Day of the week + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds + io_ro_32 rtc_0; + + _REG_(RTC_INTR_OFFSET) // RTC_INTR + // Raw Interrupts + // 0x00000001 [0] : RTC (0) + io_ro_32 intr; + + _REG_(RTC_INTE_OFFSET) // RTC_INTE + // Interrupt Enable + // 0x00000001 [0] : RTC (0) io_rw_32 inte; + + _REG_(RTC_INTF_OFFSET) // RTC_INTF + // Interrupt Force + // 0x00000001 [0] : RTC (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(RTC_INTS_OFFSET) // RTC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : RTC (0) + io_ro_32 ints; } rtc_hw_t; #define rtc_hw ((rtc_hw_t *const)RTC_BASE) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h index b48a8725472..42569c7e95a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h @@ -1,22 +1,67 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_SCB_H #define _HARDWARE_STRUCTS_SCB_H #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" -// SCB == System Control Block +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID + // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor... + // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status: + // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor: + // 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status: io_ro_32 cpuid; + + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR + // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending... + // 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI + // 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit + // 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit + // 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit + // 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit + // 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted + // 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag + // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =... + // 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field io_rw_32 icsr; + + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR + // The VTOR holds the vector table offset address + // 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address io_rw_32 vtor; + + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR + // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state... + // 0xffff0000 [31:16] : VECTKEY (0): Register key: + // 0x00008000 [15] : ENDIANESS (0): Data endianness implemented: + // 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be... + // 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions io_rw_32 aircr; + + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR + // System Control Register + // 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit: + // 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode: + // 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode: io_rw_32 scr; - // ... } armv6m_scb_t; #define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h index 400083f81a9..00b7e7e8939 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,51 +13,164 @@ #include "hardware/regs/sio.h" #include "hardware/structs/interp.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO pins + // 0x3fffffff [29:0] : GPIO_IN (0): Input value for GPIO0 io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value for QSPI pins + // 0x0000003f [5:0] : GPIO_HI_IN (0): Input value on QSPI IO in order 0 io_ro_32 gpio_hi_in; - uint32_t _pad; - io_wo_32 gpio_out; + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO output value + // 0x3fffffff [29:0] : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO output value set + // 0x3fffffff [29:0] : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i io_wo_32 gpio_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO output value clear + // 0x3fffffff [29:0] : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO output value XOR + // 0x3fffffff [29:0] : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i io_wo_32 gpio_togl; - io_wo_32 gpio_oe; + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO output enable + // 0x3fffffff [29:0] : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO output enable set + // 0x3fffffff [29:0] : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO output enable clear + // 0x3fffffff [29:0] : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO output enable XOR + // 0x3fffffff [29:0] : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i io_wo_32 gpio_oe_togl; - io_wo_32 gpio_hi_out; + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // QSPI output value + // 0x0000003f [5:0] : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // QSPI output value set + // 0x0000003f [5:0] : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // QSPI output value clear + // 0x0000003f [5:0] : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // QSPI output value XOR + // 0x0000003f [5:0] : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i io_wo_32 gpio_hi_togl; - io_wo_32 gpio_hi_oe; + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // QSPI output enable + // 0x0000003f [5:0] : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // QSPI output enable set + // 0x0000003f [5:0] : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // QSPI output enable clear + // 0x0000003f [5:0] : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // QSPI output enable XOR + // 0x0000003f [5:0] : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_togl; + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes) + // 0x00000008 [3] : ROE (0): Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] : WOF (0): Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] : RDY (1): Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] : VLD (0): Value is 1 if this core's RX FIFO is not empty (i io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state io_ro_32 spinlock_st; + _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND + // Divider unsigned dividend io_rw_32 div_udividend; + + _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR + // Divider unsigned divisor io_rw_32 div_udivisor; + + _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND + // Divider signed dividend io_rw_32 div_sdividend; + + _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR + // Divider signed divisor io_rw_32 div_sdivisor; + _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT + // Divider result quotient io_rw_32 div_quotient; - io_rw_32 div_remainder; - io_rw_32 div_csr; - uint32_t _pad2; + _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER + // Divider result remainder + io_rw_32 div_remainder; + _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR + // Control and status register for divider + // 0x00000002 [1] : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read + // 0x00000001 [0] : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise + io_ro_32 div_csr; + uint32_t _pad1; interp_hw_t interp[2]; } sio_hw_t; -#define sio_hw ((sio_hw_t *)SIO_BASE) +#define sio_hw ((sio_hw_t *const)SIO_BASE) #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h index 5b3b2bab5d5..f7fffb83cac 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,16 +12,85 @@ #include "hardware/address_mapped.h" #include "hardware/regs/spi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] : SCR (0): Serial clock rate + // 0x00000080 [7] : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] : FRF (0): Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] : DSS (0): Data Size Select: 0000 Reserved, undefined operation io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] : SOD (0): Slave-mode output disable + // 0x00000004 [2] : MS (0): Master or slave mode select + // 0x00000002 [1] : SSE (0): Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] : LBM (0): Loop back mode: 0 Normal serial port operation enabled io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] : DATA (0): Transmit/Receive FIFO: Read Receive FIFO io_rw_32 dr; - io_rw_32 sr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] : CPSDVSR (0): Clock prescale divisor io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked + // 0x00000004 [2] : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked + // 0x00000002 [1] : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout... + // 0x00000001 [0] : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition... io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // 0x00000004 [2] : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // 0x00000002 [1] : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // 0x00000001 [0] : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // 0x00000004 [2] : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // 0x00000002 [1] : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // 0x00000001 [0] : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] : RTIC (0): Clears the SSPRTINTR interrupt + // 0x00000001 [0] : RORIC (0): Clears the SSPRORINTR interrupt io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] : TXDMAE (0): Transmit DMA Enable + // 0x00000001 [0] : RXDMAE (0): Receive DMA Enable io_rw_32 dmacr; } spi_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h index 80779fe6ba2..0ab18beb59d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,40 +10,201 @@ #define _HARDWARE_STRUCTS_SSI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/ssi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 + // Control register 0 + // 0x01000000 [24] : SSTE (0): Slave select toggle enable + // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format + // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode + // 0x0000f000 [15:12] : CFS (0): Control frame size + // 0x00000800 [11] : SRL (0): Shift register loop (test mode) + // 0x00000400 [10] : SLV_OE (0): Slave output enable + // 0x00000300 [9:8] : TMOD (0): Transfer mode + // 0x00000080 [7] : SCPOL (0): Serial clock polarity + // 0x00000040 [6] : SCPH (0): Serial clock phase + // 0x00000030 [5:4] : FRF (0): Frame format + // 0x0000000f [3:0] : DFS (0): Data frame size io_rw_32 ctrlr0; + + _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 + // Master Control register 1 + // 0x0000ffff [15:0] : NDF (0): Number of data frames io_rw_32 ctrlr1; + + _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR + // SSI Enable + // 0x00000001 [0] : SSI_EN (0): SSI enable io_rw_32 ssienr; + + _REG_(SSI_MWCR_OFFSET) // SSI_MWCR + // Microwire Control + // 0x00000004 [2] : MHS (0): Microwire handshaking + // 0x00000002 [1] : MDD (0): Microwire control + // 0x00000001 [0] : MWMOD (0): Microwire transfer mode io_rw_32 mwcr; + + _REG_(SSI_SER_OFFSET) // SSI_SER + // Slave enable + // 0x00000001 [0] : SER (0): For each bit: io_rw_32 ser; + + _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR + // Baud rate + // 0x0000ffff [15:0] : SCKDV (0): SSI clock divider io_rw_32 baudr; + + _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR + // TX FIFO threshold level + // 0x000000ff [7:0] : TFT (0): Transmit FIFO threshold io_rw_32 txftlr; + + _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR + // RX FIFO threshold level + // 0x000000ff [7:0] : RFT (0): Receive FIFO threshold io_rw_32 rxftlr; - io_rw_32 txflr; - io_rw_32 rxflr; - io_rw_32 sr; + + _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR + // TX FIFO level + // 0x000000ff [7:0] : TFTFL (0): Transmit FIFO level + io_ro_32 txflr; + + _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR + // RX FIFO level + // 0x000000ff [7:0] : RXTFL (0): Receive FIFO level + io_ro_32 rxflr; + + _REG_(SSI_SR_OFFSET) // SSI_SR + // Status register + // 0x00000040 [6] : DCOL (0): Data collision error + // 0x00000020 [5] : TXE (0): Transmission error + // 0x00000010 [4] : RFF (0): Receive FIFO full + // 0x00000008 [3] : RFNE (0): Receive FIFO not empty + // 0x00000004 [2] : TFE (0): Transmit FIFO empty + // 0x00000002 [1] : TFNF (0): Transmit FIFO not full + // 0x00000001 [0] : BUSY (0): SSI busy flag + io_ro_32 sr; + + _REG_(SSI_IMR_OFFSET) // SSI_IMR + // Interrupt mask + // 0x00000020 [5] : MSTIM (0): Multi-master contention interrupt mask + // 0x00000010 [4] : RXFIM (0): Receive FIFO full interrupt mask + // 0x00000008 [3] : RXOIM (0): Receive FIFO overflow interrupt mask + // 0x00000004 [2] : RXUIM (0): Receive FIFO underflow interrupt mask + // 0x00000002 [1] : TXOIM (0): Transmit FIFO overflow interrupt mask + // 0x00000001 [0] : TXEIM (0): Transmit FIFO empty interrupt mask io_rw_32 imr; - io_rw_32 isr; - io_rw_32 risr; - io_rw_32 txoicr; - io_rw_32 rxoicr; - io_rw_32 rxuicr; - io_rw_32 msticr; - io_rw_32 icr; + + _REG_(SSI_ISR_OFFSET) // SSI_ISR + // Interrupt status + // 0x00000020 [5] : MSTIS (0): Multi-master contention interrupt status + // 0x00000010 [4] : RXFIS (0): Receive FIFO full interrupt status + // 0x00000008 [3] : RXOIS (0): Receive FIFO overflow interrupt status + // 0x00000004 [2] : RXUIS (0): Receive FIFO underflow interrupt status + // 0x00000002 [1] : TXOIS (0): Transmit FIFO overflow interrupt status + // 0x00000001 [0] : TXEIS (0): Transmit FIFO empty interrupt status + io_ro_32 isr; + + _REG_(SSI_RISR_OFFSET) // SSI_RISR + // Raw interrupt status + // 0x00000020 [5] : MSTIR (0): Multi-master contention raw interrupt status + // 0x00000010 [4] : RXFIR (0): Receive FIFO full raw interrupt status + // 0x00000008 [3] : RXOIR (0): Receive FIFO overflow raw interrupt status + // 0x00000004 [2] : RXUIR (0): Receive FIFO underflow raw interrupt status + // 0x00000002 [1] : TXOIR (0): Transmit FIFO overflow raw interrupt status + // 0x00000001 [0] : TXEIR (0): Transmit FIFO empty raw interrupt status + io_ro_32 risr; + + _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR + // TX FIFO overflow interrupt clear + // 0x00000001 [0] : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt + io_ro_32 txoicr; + + _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR + // RX FIFO overflow interrupt clear + // 0x00000001 [0] : RXOICR (0): Clear-on-read receive FIFO overflow interrupt + io_ro_32 rxoicr; + + _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR + // RX FIFO underflow interrupt clear + // 0x00000001 [0] : RXUICR (0): Clear-on-read receive FIFO underflow interrupt + io_ro_32 rxuicr; + + _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR + // Multi-master interrupt clear + // 0x00000001 [0] : MSTICR (0): Clear-on-read multi-master contention interrupt + io_ro_32 msticr; + + _REG_(SSI_ICR_OFFSET) // SSI_ICR + // Interrupt clear + // 0x00000001 [0] : ICR (0): Clear-on-read all active interrupts + io_ro_32 icr; + + _REG_(SSI_DMACR_OFFSET) // SSI_DMACR + // DMA control + // 0x00000002 [1] : TDMAE (0): Transmit DMA enable + // 0x00000001 [0] : RDMAE (0): Receive DMA enable io_rw_32 dmacr; + + _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR + // DMA TX data level + // 0x000000ff [7:0] : DMATDL (0): Transmit data watermark level io_rw_32 dmatdlr; + + _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR + // DMA RX data level + // 0x000000ff [7:0] : DMARDL (0): Receive data watermark level (DMARDLR+1) io_rw_32 dmardlr; - io_rw_32 idr; - io_rw_32 ssi_version_id; + + _REG_(SSI_IDR_OFFSET) // SSI_IDR + // Identification register + // 0xffffffff [31:0] : IDCODE (0x51535049): Peripheral dentification code + io_ro_32 idr; + + _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID + // Version ID + // 0xffffffff [31:0] : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X + io_ro_32 ssi_version_id; + + _REG_(SSI_DR0_OFFSET) // SSI_DR0 + // Data Register 0 (of 36) + // 0xffffffff [31:0] : DR (0): First data register of 36 io_rw_32 dr0; - uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; + + uint32_t _pad0[35]; + + _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY + // RX sample delay + // 0x000000ff [7:0] : RSD (0): RXD sample delay (in SCLK cycles) io_rw_32 rx_sample_dly; + + _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 + // SPI control + // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + // 0x00040000 [18] : SPI_RXDS_EN (0): Read data strobe enable + // 0x00020000 [17] : INST_DDR_EN (0): Instruction DDR transfer enable + // 0x00010000 [16] : SPI_DDR_EN (0): SPI DDR transfer enable + // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles) + // 0x00000300 [9:8] : INST_L (0): Instruction length (0/4/8/16b) + // 0x0000003c [5:2] : ADDR_L (0): Address length (0b-60b in 4b increments) + // 0x00000003 [1:0] : TRANS_TYPE (0): Address and instruction transfer format io_rw_32 spi_ctrlr0; + + _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE + // TX drive edge + // 0x000000ff [7:0] : TDE (0): TXD drive edge io_rw_32 txd_drive_edge; } ssi_hw_t; #define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h index 0bfc7293c10..52218fb1a46 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,65 @@ #define _HARDWARE_STRUCTS_SYSCFG_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/syscfg.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK + // Processor core 0 NMI source mask io_rw_32 proc0_nmi_mask; + + _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK + // Processor core 1 NMI source mask io_rw_32 proc1_nmi_mask; + + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID + // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID + // 0x00000002 [1] : PROC1_HALTED (0): Indication that proc1 has halted + // 0x00000001 [0] : PROC0_HALTED (0): Indication that proc0 has halted io_rw_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + // 0x3fffffff [29:0] : PROC_IN_SYNC_BYPASS (0) io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + // 0x0000003f [5:0] : PROC_IN_SYNC_BYPASS_HI (0) io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the SWD debug port of either processor + // 0x00000080 [7] : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from... + // 0x00000040 [6] : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + // 0x00000020 [5] : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + // 0x00000010 [4] : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output + // 0x00000008 [3] : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from... + // 0x00000004 [2] : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + // 0x00000002 [1] : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + // 0x00000001 [0] : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control power downs to memories + // 0x00000080 [7] : ROM (0) + // 0x00000040 [6] : USB (0) + // 0x00000020 [5] : SRAM5 (0) + // 0x00000010 [4] : SRAM4 (0) + // 0x00000008 [3] : SRAM3 (0) + // 0x00000004 [2] : SRAM2 (0) + // 0x00000002 [1] : SRAM1 (0) + // 0x00000001 [0] : SRAM0 (0) io_rw_32 mempowerdown; } syscfg_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h index 3c999715282..a859feae949 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +12,38 @@ #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR + // Use the SysTick Control and Status Register to enable the SysTick features + // 0x00010000 [16] : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] : CLKSOURCE (0): SysTick clock source + // 0x00000002 [1] : TICKINT (0): Enables SysTick exception request: + // 0x00000001 [0] : ENABLE (0): Enable SysTick counter: io_rw_32 csr; + + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR + // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the... + // 0x00ffffff [23:0] : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0 io_rw_32 rvr; - io_ro_32 cvr; + + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR + // Use the SysTick Current Value Register to find the current value in the register + // 0x00ffffff [23:0] : CURRENT (0): Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB + // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply + // 0x80000000 [31] : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the... + // 0x40000000 [30] : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency) + // 0x00ffffff [23:0] : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock... io_ro_32 calib; } systick_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h index e051a06970c..c7c706692ac 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,28 +10,98 @@ #define _HARDWARE_STRUCTS_TIMER_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/timer.h" -#define NUM_TIMERS 4 +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time io_ro_32 timelr; - io_rw_32 alarm[NUM_TIMERS]; + + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + // + // Arm alarm 0, and configure the time it will fire + io_rw_32 alarm[NUM_TIMERS]; // 4 + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] : ARMED (0) io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] : DBG1 (1): Pause when processor 1 is in debug mode + // 0x00000002 [1] : DBG0 (1): Pause when processor 0 is in debug mode io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] : PAUSE (0) io_rw_32 pause; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_ro_32 ints; } timer_hw_t; #define timer_hw ((timer_hw_t *const)TIMER_BASE) +static_assert( NUM_TIMERS == 4, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h index 42fe8e88bf9..09af33e4397 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,22 +12,162 @@ #include "hardware/address_mapped.h" #include "hardware/regs/uart.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] : OE (0): Overrun error + // 0x00000400 [10] : BE (0): Break error + // 0x00000200 [9] : PE (0): Parity error + // 0x00000100 [8] : FE (0): Framing error + // 0x000000ff [7:0] : DATA (0): Receive (read) data character io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] : OE (0): Overrun error + // 0x00000004 [2] : BE (0): Break error + // 0x00000002 [1] : PE (0): Parity error + // 0x00000001 [0] : FE (0): Framing error io_rw_32 rsr; + uint32_t _pad0[4]; - io_rw_32 fr; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] : RI (0): Ring indicator + // 0x00000080 [7] : TXFE (1): Transmit FIFO empty + // 0x00000040 [6] : RXFF (0): Receive FIFO full + // 0x00000020 [5] : TXFF (0): Transmit FIFO full + // 0x00000010 [4] : RXFE (1): Receive FIFO empty + // 0x00000008 [3] : BUSY (0): UART busy + // 0x00000004 [2] : DCD (0): Data carrier detect + // 0x00000002 [1] : DSR (0): Data set ready + // 0x00000001 [0] : CTS (0): Clear to send + io_ro_32 fr; + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] : ILPDVSR (0): 8-bit low-power divisor value io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] : BAUD_DIVINT (0): The integer baud rate divisor io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] : BAUD_DIVFRAC (0): The fractional baud rate divisor io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] : SPS (0): Stick parity select + // 0x00000060 [6:5] : WLEN (0): Word length + // 0x00000010 [4] : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become... + // 0x00000008 [3] : STP2 (0): Two stop bits select + // 0x00000004 [2] : EPS (0): Even parity select + // 0x00000002 [1] : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =... + // 0x00000001 [0] : BRK (0): Send break io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] : CTSEN (0): CTS hardware flow control enable + // 0x00004000 [14] : RTSEN (0): RTS hardware flow control enable + // 0x00002000 [13] : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output + // 0x00001000 [12] : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output + // 0x00000800 [11] : RTS (0): Request to send + // 0x00000400 [10] : DTR (0): Data transmit ready + // 0x00000200 [9] : RXE (1): Receive enable + // 0x00000100 [8] : TXE (1): Transmit enable + // 0x00000080 [7] : LBE (0): Loopback enable + // 0x00000004 [2] : SIRLP (0): SIR low-power IrDA mode + // 0x00000002 [1] : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] : UARTEN (0): UART enable: 0 = UART is disabled io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] : RXIFLSEL (0x2): Receive interrupt FIFO level select + // 0x00000007 [2:0] : TXIFLSEL (0x2): Transmit interrupt FIFO level select io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] : OEIM (0): Overrun error interrupt mask + // 0x00000200 [9] : BEIM (0): Break error interrupt mask + // 0x00000100 [8] : PEIM (0): Parity error interrupt mask + // 0x00000080 [7] : FEIM (0): Framing error interrupt mask + // 0x00000040 [6] : RTIM (0): Receive timeout interrupt mask + // 0x00000020 [5] : TXIM (0): Transmit interrupt mask + // 0x00000010 [4] : RXIM (0): Receive interrupt mask + // 0x00000008 [3] : DSRMIM (0): nUARTDSR modem interrupt mask + // 0x00000004 [2] : DCDMIM (0): nUARTDCD modem interrupt mask + // 0x00000002 [1] : CTSMIM (0): nUARTCTS modem interrupt mask + // 0x00000001 [0] : RIMIM (0): nUARTRI modem interrupt mask io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] : OERIS (0): Overrun error interrupt status + // 0x00000200 [9] : BERIS (0): Break error interrupt status + // 0x00000100 [8] : PERIS (0): Parity error interrupt status + // 0x00000080 [7] : FERIS (0): Framing error interrupt status + // 0x00000040 [6] : RTRIS (0): Receive timeout interrupt status + // 0x00000020 [5] : TXRIS (0): Transmit interrupt status + // 0x00000010 [4] : RXRIS (0): Receive interrupt status + // 0x00000008 [3] : DSRRMIS (0): nUARTDSR modem interrupt status + // 0x00000004 [2] : DCDRMIS (0): nUARTDCD modem interrupt status + // 0x00000002 [1] : CTSRMIS (0): nUARTCTS modem interrupt status + // 0x00000001 [0] : RIRMIS (0): nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] : OEMIS (0): Overrun error masked interrupt status + // 0x00000200 [9] : BEMIS (0): Break error masked interrupt status + // 0x00000100 [8] : PEMIS (0): Parity error masked interrupt status + // 0x00000080 [7] : FEMIS (0): Framing error masked interrupt status + // 0x00000040 [6] : RTMIS (0): Receive timeout masked interrupt status + // 0x00000020 [5] : TXMIS (0): Transmit masked interrupt status + // 0x00000010 [4] : RXMIS (0): Receive masked interrupt status + // 0x00000008 [3] : DSRMMIS (0): nUARTDSR modem masked interrupt status + // 0x00000004 [2] : DCDMMIS (0): nUARTDCD modem masked interrupt status + // 0x00000002 [1] : CTSMMIS (0): nUARTCTS modem masked interrupt status + // 0x00000001 [0] : RIMMIS (0): nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] : OEIC (0): Overrun error interrupt clear + // 0x00000200 [9] : BEIC (0): Break error interrupt clear + // 0x00000100 [8] : PEIC (0): Parity error interrupt clear + // 0x00000080 [7] : FEIC (0): Framing error interrupt clear + // 0x00000040 [6] : RTIC (0): Receive timeout interrupt clear + // 0x00000020 [5] : TXIC (0): Transmit interrupt clear + // 0x00000010 [4] : RXIC (0): Receive interrupt clear + // 0x00000008 [3] : DSRMIC (0): nUARTDSR modem interrupt clear + // 0x00000004 [2] : DCDMIC (0): nUARTDCD modem interrupt clear + // 0x00000002 [1] : CTSMIC (0): nUARTCTS modem interrupt clear + // 0x00000001 [0] : RIMIC (0): nUARTRI modem interrupt clear io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] : DMAONERR (0): DMA on error + // 0x00000002 [1] : TXDMAE (0): Transmit DMA enable + // 0x00000001 [0] : RXDMAE (0): Receive DMA enable io_rw_32 dmacr; } uart_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h index 5c3c4533995..c9455d06584 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +12,14 @@ #include "hardware/address_mapped.h" #include "hardware/regs/usb.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + // 0-15 #define USB_NUM_ENDPOINTS 16 @@ -39,10 +49,10 @@ #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26 -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u -#define USB_DPRAM_SIZE 4096 +#define USB_DPRAM_SIZE 4096u // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb // Allow user to claim some of the USB RAM for themselves @@ -79,6 +89,7 @@ typedef struct { } usb_device_dpram_t; static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); typedef struct { // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses @@ -108,40 +119,460 @@ typedef struct { } usb_host_dpram_t; static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to + // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to io_rw_32 dev_addr_ctrl; - io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + // + // Interrupt endpoint 1 + // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub) + // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint + // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] : ADDRESS (0): Device address + io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15 + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation + // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1 + // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller io_rw_32 main_ctrl; - io_rw_32 sof_rw; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] : COUNT (0) + io_wo_32 sof_rw; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] : COUNT (0) io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable + // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP + // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM + // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver + // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor + // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors + // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus + // 0x00001000 [12] : RESUME (0): Device: Remote wakeup + // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS + // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF + // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub + // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction + // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host) + // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host) + // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet + // 0x00000001 [0] : START_TRANS (0): Host: Start transaction io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error + // 0x40000000 [30] : ACK_REC (0): ACK received + // 0x20000000 [29] : STALL_REC (0): Host: STALL received + // 0x10000000 [28] : NAK_REC (0): Host: NAK received + // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in... + // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast + // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error + // 0x01000000 [24] : CRC_ERROR (0): CRC Error + // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received + // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete + // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received + // 0x00010000 [16] : CONNECTED (0): Device: connected + // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume + // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected + // 0x00000300 [9:8] : SPEED (0): Host: device speed + // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state + // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state + // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15 io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 buf_status; - io_rw_32 buf_cpu_should_handle; // for double buff + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0 + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device + // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x00000008 [3] : SOFTCON (0) + // 0x00000004 [2] : TO_DIGITAL_PAD (0) + // 0x00000002 [1] : TO_EXTPHY (0) + // 0x00000001 [0] : TO_PHY (0) io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] : OVERCURR_DETECT_EN (0) + // 0x00000010 [4] : OVERCURR_DETECT (0) + // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] : VBUS_DETECT (0) + // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] : VBUS_EN (0) io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // This register allows for direct control of the USB phy + // 0x00400000 [22] : DM_OVV (0): DM over voltage + // 0x00200000 [21] : DP_OVV (0): DP over voltage + // 0x00100000 [20] : DM_OVCN (0): DM overcurrent + // 0x00080000 [19] : DP_OVCN (0): DP overcurrent + // 0x00040000 [18] : RX_DM (0): DPM pin state + // 0x00020000 [17] : RX_DP (0): DPP pin state + // 0x00010000 [16] : RX_DD (0): Differential RX + // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode + // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate + // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set) + // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set) + // 0x00000800 [11] : TX_DM (0): Output data + // 0x00000400 [10] : TX_DP (0): Output data + // 0x00000200 [9] : TX_DM_OE (0): Output enable + // 0x00000100 [8] : TX_DP_OE (0): Output enable + // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable + // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable + // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor + // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable + // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable + // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct + // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0) + // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0) io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Used to adjust trim values of USB phy pull down resistors + // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY + // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY io_rw_32 phy_trim; - io_rw_32 linestate_tuning; - io_rw_32 intr; + + uint32_t _pad0; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i io_rw_32 intf; - io_rw_32 ints; -} usb_hw_t; -check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + io_ro_32 ints; +} usb_hw_t; -#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE) #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h index 9956d683152..554d9e4470a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,12 +10,37 @@ #define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/vreg_and_chip_reset.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG + // Voltage regulator control and status + // 0x00001000 [12] : ROK (0): regulation status + // 0x000000f0 [7:4] : VSEL (0xb): output voltage select + // 0x00000002 [1] : HIZ (0): high impedance mode select + // 0x00000001 [0] : EN (1): enable io_rw_32 vreg; + + _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD + // brown-out detection control + // 0x000000f0 [7:4] : VSEL (0x9): threshold select + // 0x00000001 [0] : EN (1): enable io_rw_32 bod; + + _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET + // Chip reset control and status + // 0x01000000 [24] : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger + // 0x00100000 [20] : HAD_PSM_RESTART (0): Last reset was from the debug port + // 0x00010000 [16] : HAD_RUN (0): Last reset was from the RUN pin + // 0x00000100 [8] : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks io_rw_32 chip_reset; } vreg_and_chip_reset_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h index 2cf05f19d1e..9579700b633 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,50 @@ #define _HARDWARE_STRUCTS_WATCHDOG_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/watchdog.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + // 0x80000000 [31] : TRIGGER (0): Trigger a watchdog reset + // 0x40000000 [30] : ENABLE (0): When not enabled the watchdog timer is paused + // 0x04000000 [26] : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will... io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer + // 0x00ffffff [23:0] : LOAD (0) io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset + // 0x00000002 [1] : FORCE (0) + // 0x00000001 [0] : TIMER (0) io_ro_32 reason; + + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + // + // Scratch register io_rw_32 scratch[8]; + + _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK + // Controls the tick generator + // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated + // 0x00000400 [10] : RUNNING (0): Is the tick generator running? + // 0x00000200 [9] : ENABLE (1): start / stop tick generation + // 0x000001ff [8:0] : CYCLES (0): Total number of clk_tick cycles before the next tick io_rw_32 tick; } watchdog_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h index bfa5b1c0cb4..21885e8676c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h @@ -1,29 +1,72 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_XIP_CTRL_H #define _HARDWARE_STRUCTS_XIP_CTRL_H #include "hardware/address_mapped.h" #include "hardware/regs/xip.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control + // 0x00000008 [3] : POWER_DOWN (0): When 1, the cache memories are powered down + // 0x00000002 [1] : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating) + // 0x00000001 [0] : EN (1): When 1, enable the cache io_rw_32 ctrl; + + _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH + // Cache Flush control + // 0x00000001 [0] : FLUSH (0): Write 1 to flush the cache io_rw_32 flush; - io_rw_32 stat; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // Cache Status + // 0x00000004 [2] : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty + // 0x00000001 [0] : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] : STREAM_CTR (0): Write a nonzero value to start a streaming read io_rw_32 stream_ctr; - io_rw_32 stream_fifo; -} xip_ctrl_hw_t; -#define XIP_STAT_FIFO_FULL 0x4u -#define XIP_STAT_FIFO_EMPTY 0x2u -#define XIP_STAT_FLUSH_RDY 0x1u + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; #define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h index 698e6a2ff2c..0ff4db487b5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,47 @@ #define _HARDWARE_STRUCTS_XOSC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/xosc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::xosc_hw[] typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC + // 0x00000fff [11:0] : FREQ_RANGE (0): Frequency range io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] : STABLE (0): Oscillator is running and stable + // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0 + // 0x00000003 [1:0] : FREQ_RANGE (0): The current frequency range setting, always reads 0 io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] : X4 (0): Multiplies the startup_delay by 4 + // 0x00003fff [13:0] : DELAY (0xc4): in multiples of 256*xtal_period io_rw_32 startup; - io_rw_32 _reserved[3]; + + uint32_t _pad0[3]; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the xosc frequency which counts to zero and stops + // 0x000000ff [7:0] : COUNT (0) io_rw_32 count; } xosc_hw_t; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake index 76126602fea..c04e55144ad 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common.cmake @@ -3,17 +3,17 @@ enable_language(ASM) function(pico_add_hex_output TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.hex) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $ $>,$,$>.hex) endfunction() function(pico_add_bin_output TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.bin) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $ $>,$,$>.bin) endfunction() function(pico_add_dis_output TARGET) add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${CMAKE_OBJDUMP} -h ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >${TARGET}.dis - COMMAND ${CMAKE_OBJDUMP} -d ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >>${TARGET}.dis + COMMAND ${CMAKE_OBJDUMP} -h $ >$>,$,$>.dis + COMMAND ${CMAKE_OBJDUMP} -d $ >>$>,$,$>.dis ) endfunction() @@ -36,8 +36,8 @@ function(pico_add_extra_outputs TARGET) add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}" - COMMAND ln -s -r ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} "${PICO_SYMLINK_ELF_AS_FILENAME}" - COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}${CMAKE_EXECUTABLE_SUFFIX}" + COMMAND ln -s -r $ "${PICO_SYMLINK_ELF_AS_FILENAME}" + COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}" ) endif () # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt index ae0561fd7fe..4ca55becba2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/CMakeLists.txt @@ -10,6 +10,7 @@ pico_add_subdirectory(hardware_adc) pico_add_subdirectory(hardware_clocks) pico_add_subdirectory(hardware_dma) pico_add_subdirectory(hardware_divider) +pico_add_subdirectory(hardware_exception) pico_add_subdirectory(hardware_flash) pico_add_subdirectory(hardware_gpio) pico_add_subdirectory(hardware_i2c) @@ -36,6 +37,7 @@ if (NOT PICO_BARE_METAL) # NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS pico_add_subdirectory(boot_stage2) + pico_add_subdirectory(pico_bootsel_via_double_reset) pico_add_subdirectory(pico_multicore) pico_add_subdirectory(pico_unique_id) @@ -52,6 +54,7 @@ if (NOT PICO_BARE_METAL) pico_add_subdirectory(pico_stdio_semihosting) pico_add_subdirectory(pico_stdio_uart) + pico_add_subdirectory(cmsis) pico_add_subdirectory(tinyusb) pico_add_subdirectory(pico_stdio_usb) @@ -69,3 +72,6 @@ endif() set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE) pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) +pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/cmsis) + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt index 454e11cf83f..a2f3960d8a0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/CMakeLists.txt @@ -1,22 +1,44 @@ -# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default stage2 file to use unless overridden by pico_set_boot_stage2 on the TARGET, type=bool, default=.../boot2_w25q080.S, group=build -if (NOT PICO_DEFAULT_BOOT_STAGE2_FILE) - set(PICO_DEFAULT_BOOT_STAGE2_FILE "${CMAKE_CURRENT_LIST_DIR}/boot2_w25q080.S") +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, group=build +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, default=compile_time_choice, group=build + +if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) + set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) + message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')") +elseif (PICO_DEFAULT_BOOT_STAGE2_FILE) + # explicitly set, so cache it + set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE) endif() -set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot_stage2 source file" FORCE) +set(PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME compile_time_choice) # local var +if (NOT PICO_DEFAULT_BOOT_STAGE2_FILE) + if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2}) + set(PICO_DEFAULT_BOOT_STAGE2 $ENV{PICO_DEFAULT_BOOT_STAGE2}) + message("Using PICO_DEFAULT_BOOT_STAGE2 from environment ('${PICO_DEFAULT_BOOT_STAGE2}')") + endif() + if (NOT DEFINED PICO_DEFAULT_BOOT_STAGE2) + set(PICO_DEFAULT_BOOT_STAGE2 ${PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME}) + endif() + set(PICO_DEFAULT_BOOT_STAGE2 "${PICO_DEFAULT_BOOT_STAGE2}" CACHE STRING "boot stage 2 short name" FORCE) + set(PICO_DEFAULT_BOOT_STAGE2_FILE "${CMAKE_CURRENT_LIST_DIR}/${PICO_DEFAULT_BOOT_STAGE2}.S") +endif() if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE}) - message(FATAL_ERROR "Specified boot_stage2 source '${PICO_BOOT_STAGE2_FILE}' does not exist.") + message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.") endif() +pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE) # needed by function below set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") +add_library(boot_stage2_headers INTERFACE) +target_include_directories(boot_stage2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +# by convention the first source file name without extension is used for the binary info name function(pico_define_boot_stage2 NAME SOURCES) add_executable(${NAME} ${SOURCES} ) - + # todo bit of an abstraction failure - revisit for Clang support anyway if (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${NAME} PRIVATE "-nostdlib") @@ -28,13 +50,13 @@ function(pico_define_boot_stage2 NAME SOURCES) # boot2_helpers include dir target_include_directories(${NAME} PRIVATE ${PICO_BOOT_STAGE2_DIR}/asminclude) - target_link_libraries(${NAME} hardware_regs) + target_link_libraries(${NAME} hardware_regs boot_stage2_headers) target_link_options(${NAME} PRIVATE "LINKER:--script=${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld") set_target_properties(${NAME} PROPERTIES LINK_DEPENDS ${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld) pico_add_dis_output(${NAME}) pico_add_map_output(${NAME}) - + set(ORIGINAL_BIN ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.bin) set(PADDED_CHECKSUMMED_ASM ${CMAKE_CURRENT_BINARY_DIR}/${NAME}_padded_checksummed.S) @@ -42,17 +64,28 @@ function(pico_define_boot_stage2 NAME SOURCES) add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN}) add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${ORIGINAL_BIN}) - + add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM}) add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN} COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM} ) - add_library(${NAME}_library INTERFACE) add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm) # not strictly (or indeed actually) a link library, but this avoids dependency cycle target_link_libraries(${NAME}_library INTERFACE ${PADDED_CHECKSUMMED_ASM}) + target_link_libraries(${NAME}_library INTERFACE boot_stage2_headers) + + list(GET SOURCES 0 FIRST_SOURCE) + get_filename_component(BOOT_STAGE2_BI_NAME ${FIRST_SOURCE} NAME_WE) + + # we only set the PICO_BUILD_STAGE2_NAME if it isn't 'compile_time_choice' + if (NOT BOOT_STAGE2_BI_NAME STREQUAL PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME) + target_compile_definitions(${NAME} INTERFACE + -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}") + target_compile_definitions(${NAME}_library INTERFACE + -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}") + endif() endfunction() macro(pico_set_boot_stage2 TARGET NAME) @@ -60,9 +93,15 @@ macro(pico_set_boot_stage2 TARGET NAME) if ("EXECUTABLE" STREQUAL "${target_type}") set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BOOT_STAGE2 "${NAME}") else() - message(FATAL_ERROR "boot stage2 implementation must be set on executable not library") + message(FATAL_ERROR "boot stage 2 implementation must be set on executable not library") endif() endmacro() pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE}) +# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived) +function(pico_clone_default_boot_stage2 NAME) + pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE}) +endfunction() + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_at25sf128a.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_at25sf128a.S new file mode 100644 index 00000000000..be232ff1123 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/boot2_at25sf128a.S @@ -0,0 +1,285 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Adesto AT25SF128A +// Based on W25Q080 code: main difference is the QE bit is being set +// via command 0x31 +// +// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register 2 to determine if QSPI mode is enabled, +// and perform an SR2 programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Jump to exit pointer passed in via lr. Bootrom passes null, +// in which case this code uses a default 256 byte flash offset +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" +#include "hardware/regs/pads_qspi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif +#if PICO_FLASH_SPI_CLKDIV & 1 +#error PICO_FLASH_SPI_CLKDIV must be even +#endif + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0x20 + +// The number of address + mode bits, divided by 4 (always 4, not function of +// interface width). +#define ADDR_L 8 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to +// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS2 0x35 +#define CMD_WRITE_STATUS 0x01 +#define CMD_WRITE_STATUS2 0x31 +#define SREG_DATA 0x02 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.syntax unified +.cpu cortex-m0plus +.thumb + +.section .text + +// The exit point is passed in lr. If entered from bootrom, this will be the +// flash address immediately following this second stage (0x10000100). +// Otherwise it will be a return address -- second stage being called as a +// function by user code, after copying out of XIP region. r3 holds SSI base, +// r0...2 used as temporaries. Other GPRs not used. +.global _stage2_boot +.type _stage2_boot,%function +.thumb_func +_stage2_boot: + push {lr} + + // Set pad configuration: + // - SCLK 8mA drive, no slew limiting + // - SDx disable input Schmitt to reduce delay + + ldr r3, =PADS_QSPI_BASE + movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] + ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + bics r0, r1 + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] + + ldr r3, =XIP_SSI_BASE + + // Disable SSI to allow further config + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + + // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, + // if the flash launches data on SCLK posedge, we capture it at the time that + // the next SCLK posedge is launched. This is shortly before that posedge + // arrives at the flash, so data hold time should be ok. For + // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. + + movs r1, #1 + movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance + str r1, [r3, r2] + + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating + movs r0, #CMD_READ_STATUS2 + bl read_flash_sreg + movs r2, #SREG_DATA + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + movs r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes + movs r1, #CMD_WRITE_STATUS2 + str r1, [r3, #SSI_DR0_OFFSET] + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Poll status register for write completion +1: + movs r0, #CMD_READ_STATUS + bl read_flash_sreg + movs r1, #1 + tst r0, r1 + bne 1b + +skip_sreg_programming: + + // Disable SSI again so that it can be reconfigured + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + +// Currently the flash expects an 8 bit serial command prefix on every +// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O +// command, with mode bits set such that the flash will not expect a serial +// command prefix on *subsequent* transfers. We don't care about the results +// of the read, the important part is the mode bits. + +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// The flash is in a state where we can blast addresses in parallel, and get +// parallel data back. Now configure the SSI to translate XIP bus accesses +// into QSPI transfers of this form. + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// Bus accesses to the XIP window will now be transparently serviced by the +// external flash on cache miss. We are ready to run code from flash. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/compile_time_choice.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/compile_time_choice.S new file mode 100644 index 00000000000..5aa2b96cd65 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/compile_time_choice.S @@ -0,0 +1,19 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------- +// +// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick +// amongst a menu of known boot stage 2 implementations, allowing the board +// configuration header to be able to specify the boot stage 2 + +#include "boot_stage2/config.h" + +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + // boot stage 2 is configured by cmake, so use the name specified there + #error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds +#else + // boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h + #include PICO_BOOT_STAGE2_ASM +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/include/boot_stage2/config.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/include/boot_stage2/config.h new file mode 100644 index 00000000000..5e57f953d48 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/boot_stage2/include/boot_stage2/config.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_STAGE2_CONFIG_H_ +#define _BOOT_STAGE2_CONFIG_H_ + +// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY + +#include "pico/config.h" + +// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, The name of the boot stage 2 if selected by the build, group=boot_stage2 +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + #define _BOOT_STAGE2_SELECTED +#else + // check that multiple boot stage 2 options haven't been set... + +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0 +#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0 +#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0 +#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0 +#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif + +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2 +#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif + +#endif // PICO_BUILD_BOOT_STAGE2_NAME + +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + // boot stage 2 is configured by cmake, so use the name specified there + #define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME +#else + // boot stage 2 is selected by board config header, so we have to do some work + #if PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #define _BOOT_STAGE2 boot2_is25lp080 + #elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #define _BOOT_STAGE2 boot2_w25q080 + #elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #define _BOOT_STAGE2 boot2_w25x10cl + #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #define _BOOT_STAGE2 boot2_at25sf128a + #elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 + #define _BOOT_STAGE2 boot2_generic_03h + #else + #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro + #endif + // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion + #define _PICO__STRING(x) #x + #define _PICO__XSTRING(x) _PICO__STRING(x) + #define _PICO__CONCAT1(x, y) x ## y + #define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2) + #define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S)) +#endif +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/CMakeLists.txt new file mode 100644 index 00000000000..0d663e1278a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/CMakeLists.txt @@ -0,0 +1,66 @@ +# Deferring this config until we decide how to include other CMSIS libraries... it is likely that we always want to use the stub version of the core +# at least if the vendor/device is RaspberryPi/RP2040... + +## PICO_CMAKE_CONFIG: PICO_CMSIS_PATH, directory to locate CMSIS installation, default="included stub CORE only impl", group=build +#if (DEFINED PICO_CMSIS_PATH) +# set(PICO_CMSIS_PATH "${PICO_CMSIS_PATH}" CACHE PATH "Path to the CMSIS tree to use with Raspberry Pi Pico SDK") +# message("Using specified PICO_CMSIS_PATH for CMSIS ('${PICO_CMSIS_PATH}')") +#elseif (DEFINED ENV{PICO_CMSIS_PATH}) +# set(PICO_CMSIS_PATH $ENV{PICO_CMSIS_PATH}) +# message("Using PICO_CMSIS_PATH from environment for CMSIS ('${PICO_CMSIS_PATH}')") +#endif() +# +## PICO_CMAKE_CONFIG: PICO_CMSIS_VENDOR, vendor name for CMSIS, default="RaspberryPi", group=build +#if (DEFINED PICO_CMSIS_VENDOR) +# set(PICO_CMSIS_VENDOR "${PICO_CMSIS_VENDOR}" CACHE STRING "CMSIS vendor name to use") +# message("Using specified PICO_CMSIS_VENDOR for CMSIS ('${PICO_CMSIS_VENDOR}')") +#elseif (DEFINED ENV{PICO_CMSIS_VENDOR}) +# set(PICO_CMSIS_VENDOR $ENV{PICO_CMSIS_VENDOR}) +# message("Using PICO_CMSIS_VENDOR from environment for CMSIS ('${PICO_CMSIS_VENDOR}')") +#else() +# set(PICO_CMSIS_VENDOR RaspberryPi) +#endif() +# +## PICO_CMAKE_CONFIG: PICO_CMSIS_DEVICE, device name for CMSIS, default="RP2040", group=build +#if (DEFINED PICO_CMSIS_DEVICE) +# set(PICO_CMSIS_DEVICE "${PICO_CMSIS_DEVICE}" CACHE STRING "CMSIS device name to use") +# message("Using specified PICO_CMSIS_DEVICE for CMSIS ('${PICO_CMSIS_DEVICE}')") +#elseif (DEFINED ENV{PICO_CMSIS_DEVICE}) +# set(PICO_CMSIS_DEVICE $ENV{PICO_CMSIS_DEVICE}) +# message("Using PICO_CMSIS_DEVICE from environment for CMSIS ('${PICO_CMSIS_DEVICE}')") +#else() +# set(PICO_CMSIS_DEVICE RP2040) +#endif() +# +#if (PICO_CMSIS_PATH AND EXISTS ${PICO_CMSIS_PATH}/CMSIS/Core/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}) +# message("CMSIS Core found for path ${PICO_CMSIS_PATH}, vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}") +# set(PICO_CMSIS_CORE_PATH ${PICO_CMSIS_PATH}/CMSIS/Core) +#elseif (PICO_CMSIS_VENDOR STREQUAL "RaspberryPi" AND PICO_CMSIS_DEVICE STREQUAL "RP2040") +# set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub) +#elseif (PICO_CMSIS_PATH) +# message(WARNING "CMSIS core not found in ${PICO_CMSIS_PATH} for vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}") +# set(PICO_CMSIS_CORE_PATH) +#else() +# message(WARNING "Non-standard vendor ${PICO_CMSIS_VENDOR} amd device ${PICO_CMSIS_DEVICE} specified, but PICO_CMSIS_PATH was not set") +#endif() + +# ... using these 3 lines instead +set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub) +set(PICO_CMSIS_VENDOR RaspberryPi) +set(PICO_CMSIS_DEVICE RP2040) + +if (PICO_CMSIS_CORE_PATH) + pico_add_impl_library(cmsis_core) + target_sources(cmsis_core INTERFACE + ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c + ) + target_include_directories(cmsis_core INTERFACE + ${PICO_CMSIS_CORE_PATH}/CMSIS/Core/Include + ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Include + ) + target_link_libraries(cmsis_core INTERFACE hardware_clocks pico_platform) + + list(APPEND PICO_RP2040_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/cmsis/rename_exceptions.h) + pico_promote_common_scope_vars() +endif() + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h new file mode 100644 index 00000000000..a523d27f1c9 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/include/cmsis/rename_exceptions.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CMSIS_RENAME_EXCEPTIONS_H +#define _CMSIS_RENAME_EXCEPTIONS_H + +#if LIB_CMSIS_CORE +// PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core + +// Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define +#ifndef PICO_CMSIS_RENAME_EXCEPTIONS +#define PICO_CMSIS_RENAME_EXCEPTIONS 1 +#endif + +#if PICO_CMSIS_RENAME_EXCEPTIONS +#define isr_nmi NMI_Handler +#define isr_hardfault HardFault_Handler +#define isr_svcall SVC_Handler +#define isr_pendsv PendSV_Handler +#define isr_systick SysTick_Handler +#define isr_irq0 TIMER_IRQ_0_Handler +#define isr_irq1 TIMER_IRQ_1_Handler +#define isr_irq2 TIMER_IRQ_2_Handler +#define isr_irq3 TIMER_IRQ_3_Handler +#define isr_irq4 PWM_IRQ_WRAP_Handler +#define isr_irq5 USBCTRL_IRQ_Handler +#define isr_irq6 XIP_IRQ_Handler +#define isr_irq7 PIO0_IRQ_0_Handler +#define isr_irq8 PIO0_IRQ_1_Handler +#define isr_irq9 PIO1_IRQ_0_Handler +#define isr_irq10 PIO1_IRQ_1_Handler +#define isr_irq11 DMA_IRQ_0_Handler +#define isr_irq12 DMA_IRQ_1_Handler +#define isr_irq13 IO_IRQ_BANK0_Handler +#define isr_irq14 IO_IRQ_QSPI_Handler +#define isr_irq15 SIO_IRQ_PROC0_Handler +#define isr_irq16 SIO_IRQ_PROC1_Handler +#define isr_irq17 CLOCKS_IRQ_Handler +#define isr_irq18 SPI0_IRQ_Handler +#define isr_irq19 SPI1_IRQ_Handler +#define isr_irq20 UART0_IRQ_Handler +#define isr_irq21 UART1_IRQ_Handler +#define isr_irq22 ADC_IRQ_FIFO_Handler +#define isr_irq23 I2C0_IRQ_Handler +#define isr_irq24 I2C1_IRQ_Handler +#define isr_irq25 RTC_IRQ_Handler +#endif + +#endif +#endif /* _CMSIS_RENAME_EXCEPTIONS_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000000..237ff6ec3ea --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000000..90de9dbf8f8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..0e5c7349d3e --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000000..a2778f58e8f --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..7eeffca5c71 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000000..2f048e4552d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000000..4e7179a6146 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000000..791a8dae65a --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h new file mode 100644 index 00000000000..a29b9e09537 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h @@ -0,0 +1,109 @@ +/*************************************************************************//** + * @file RP2040.h + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CMSIS_RP2040_H_ +#define _CMSIS_RP2040_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ + /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ + TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ + TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ + TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ + TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ + PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ + USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ + XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ + PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ + PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ + PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ + PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ + DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ + DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ + IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ + IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ + SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ + SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ + CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ + SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ + SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ + UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ + UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ + ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ + I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ + I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ + RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_RP2040.h" /*!< RP2040 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ +#define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ +#define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ +#define __IOM __IO +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CMSIS_RP2040_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h new file mode 100644 index 00000000000..30881ccc63b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h @@ -0,0 +1,65 @@ +/*************************************************************************//** + * @file system_RP2040.h + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CMSIS_SYSTEM_RP2040_H +#define _CMSIS_SYSTEM_RP2040_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMSIS_SYSTEM_RP2040_H */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c new file mode 100644 index 00000000000..055a0752c16 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c @@ -0,0 +1,52 @@ +/*************************************************************************//** + * @file system_RP2040.c + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "RP2040.h" +#include "hardware/clocks.h" + +/*--------------------------------------------------------------------------- + System Core Clock Variable + *---------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ + +/*--------------------------------------------------------------------------- + System Core Clock function + *---------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = clock_get_hz(clk_sys); +} + +/*--------------------------------------------------------------------------- + System initialization function + *---------------------------------------------------------------------------*/ +void __attribute__((constructor)) SystemInit (void) +{ + SystemCoreClockUpdate(); +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h index 13d7c418f2b..be82025a5d6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h @@ -19,7 +19,7 @@ * The RP2040 has an internal analogue-digital converter (ADC) with the following features: * - SAR ADC * - 500 kS/s (Using an independent 48MHz clock) - * - 12 bit (9.5 ENOB) + * - 12 bit (8.7 ENOB) * - 5 input mux: * - 4 inputs that are available on package pins shared with GPIO[29:26] * - 1 input is dedicated to the internal temperature sensor @@ -28,7 +28,7 @@ * - DMA interface * * Although there is only one ADC you can specify the input to it using the adc_select_input() function. - * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read. + * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read. * * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. * @@ -62,7 +62,7 @@ void adc_init(void); /*! \brief Initialise the gpio for use as an ADC pin * \ingroup hardware_adc * - * Prepare a GPIO for use with ADC, by disabling all digital functions. + * Prepare a GPIO for use with ADC by disabling all digital functions. * * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive. */ @@ -84,10 +84,19 @@ static inline void adc_gpio_init(uint gpio) { * \param input Input to select. */ static inline void adc_select_input(uint input) { - invalid_params_if(ADC, input > 4); + valid_params_if(ADC, input < NUM_ADC_CHANNELS); hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS); } +/*! \brief Get the currently selected ADC input channel + * \ingroup hardware_adc + * + * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + */ +static inline uint adc_get_selected_input(void) { + return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB; +} + /*! \brief Round Robin sampling selector * \ingroup hardware_adc * @@ -127,7 +136,7 @@ static inline uint16_t adc_read(void) { while (!(adc_hw->cs & ADC_CS_READY_BITS)) tight_loop_contents(); - return adc_hw->result; + return (uint16_t) adc_hw->result; } /*! \brief Enable or disable free-running sampling mode @@ -158,7 +167,7 @@ static inline void adc_set_clkdiv(float clkdiv) { /*! \brief Setup the ADC FIFO * \ingroup hardware_adc * - * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped. + * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped. * * \param en Enables write each conversion result to the FIFO * \param dreq_en Enable DMA requests when FIFO contains data @@ -166,13 +175,13 @@ static inline void adc_set_clkdiv(float clkdiv) { * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers. */ -static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { + static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { hw_write_masked(&adc_hw->fcs, - (!!en << ADC_FCS_EN_LSB) | - (!!dreq_en << ADC_FCS_DREQ_EN_LSB) | - (dreq_thresh << ADC_FCS_THRESH_LSB) | - (!!err_in_fifo << ADC_FCS_ERR_LSB) | - (!!byte_shift << ADC_FCS_SHIFT_LSB), + (bool_to_bit(en) << ADC_FCS_EN_LSB) | + (bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) | + (((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) | + (bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) | + (bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB), ADC_FCS_EN_BITS | ADC_FCS_DREQ_EN_BITS | ADC_FCS_THRESH_BITS | @@ -184,7 +193,7 @@ static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, b /*! \brief Check FIFO empty state * \ingroup hardware_adc * - * \return Returns true if the fifo is empty + * \return Returns true if the FIFO is empty */ static inline bool adc_fifo_is_empty(void) { return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS); @@ -205,7 +214,7 @@ static inline uint8_t adc_fifo_get_level(void) { * Pops the latest result from the ADC FIFO. */ static inline uint16_t adc_fifo_get(void) { - return adc_hw->fifo; + return (uint16_t)adc_hw->fifo; } /*! \brief Wait for the ADC FIFO to have data. @@ -216,13 +225,13 @@ static inline uint16_t adc_fifo_get(void) { static inline uint16_t adc_fifo_get_blocking(void) { while (adc_fifo_is_empty()) tight_loop_contents(); - return adc_hw->fifo; + return (uint16_t)adc_hw->fifo; } /*! \brief Drain the ADC FIFO * \ingroup hardware_adc * - * Will wait for any conversion to complete then drain the FIFO discarding any results. + * Will wait for any conversion to complete then drain the FIFO, discarding any results. */ static inline void adc_fifo_drain(void) { // Potentially there is still a conversion in progress -- wait for this to complete before draining diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h index 6645fbdd0a1..a3b958413d6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h @@ -48,9 +48,18 @@ * leaving the other bits unchanged. */ +#ifdef __cplusplus +extern "C" { +#endif + #define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") #define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base +#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS +#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0 +#endif + typedef volatile uint32_t io_rw_32; typedef const volatile uint32_t io_ro_32; typedef volatile uint32_t io_wo_32; @@ -64,15 +73,44 @@ typedef volatile uint8_t io_wo_8; typedef volatile uint8_t *const ioptr; typedef ioptr const const_ioptr; +// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated +// hardware struct headers in hardware/structs/xxx.h to the raw register definitions +// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset) +// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is +// included outside of a comment instead +#define _REG_(x) + +// Helper method used by hw_alias macros to optionally check input validity +#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) +// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility +//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) { +// uint32_t rc = (uintptr_t)addr; +// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types +// return rc; +//} + +// Helper method used by xip_alias macros to optionally check input validity +static __force_inline uint32_t xip_alias_check_addr(const void *addr) { + uint32_t rc = (uintptr_t)addr; + valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE); + return rc; +} + // Untyped conversion alias pointer generation macros -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr))) +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr))) +#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr))) // Typed conversion alias pointer generation macros #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) #define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) #define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) +#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p)) +#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p)) +#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p)) /*! \brief Atomically set the specified bits to 1 in a HW register * \ingroup hardware_base @@ -80,7 +118,7 @@ typedef ioptr const const_ioptr; * \param addr Address of writable register * \param mask Bit-mask specifying bits to set */ -inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; } @@ -90,7 +128,7 @@ inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { * \param addr Address of writable register * \param mask Bit-mask specifying bits to clear */ -inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; } @@ -100,7 +138,7 @@ inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { * \param addr Address of writable register * \param mask Bit-mask specifying bits to invert */ -inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; } @@ -116,8 +154,12 @@ inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { * \param values Bits values * \param write_mask Mask of bits to change */ -inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { +__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { hw_xor_bits(addr, (*addr ^ values) & write_mask); } +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt index 33213fa2c1a..63f4806ee03 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/CMakeLists.txt @@ -1,6 +1,2 @@ -add_library(hardware_claim INTERFACE) -target_include_directories(hardware_claim INTERFACE include) -target_sources(hardware_claim INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/claim.c) - +pico_simple_hardware_target(claim) target_link_libraries(hardware_claim INTERFACE hardware_sync) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c index 2c5c8eda21c..c96764f5b1d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/claim.c @@ -14,25 +14,16 @@ void hw_claim_unlock(uint32_t save) { spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save); } -bool hw_is_claimed(uint8_t *bits, uint bit_index) { - bool rc; - uint32_t save = hw_claim_lock(); - if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) { - rc = false; - } else { - bits[bit_index >> 3u] |= (1u << (bit_index & 7u)); - rc = true; - } - hw_claim_unlock(save); - return rc; +inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) { + return (bits[bit_index >> 3u] & (1u << (bit_index & 7u))); } void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) { uint32_t save = hw_claim_lock(); - if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) { + if (hw_is_claimed(bits, bit_index)) { panic(message, bit_index); } else { - bits[bit_index >> 3u] |= (1u << (bit_index & 7u)); + bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u)); } hw_claim_unlock(save); } @@ -42,9 +33,9 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint uint32_t save = hw_claim_lock(); int found_bit = -1; for(uint bit=bit_lsb; bit <= bit_msb; bit++) { - if (!(bits[bit >> 3u] & (1u << (bit & 7u)))) { - bits[bit >> 3u] |= (1u << (bit & 7u)); - found_bit = bit; + if (!hw_is_claimed(bits, bit)) { + bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u)); + found_bit = (int)bit; break; } } @@ -57,8 +48,8 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint void hw_claim_clear(uint8_t *bits, uint bit_index) { uint32_t save = hw_claim_lock(); - assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u))); - bits[bit_index >> 3u] &= ~(1u << (bit_index & 7u)); + assert(hw_is_claimed(bits, bit_index)); + bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u)); hw_claim_unlock(save); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h index 0c055135570..5c93453943f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h @@ -32,6 +32,10 @@ * 3. Finding unused resources */ +#ifdef __cplusplus +extern "C" { +#endif + /*! \brief Atomically claim a resource, panicking if it is already in use * \ingroup hardware_claim * @@ -61,10 +65,10 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint * The resource ownership is indicated by the bit_index bit in an array of bits. * * \param bits pointer to an array of bits (8 bits per byte) - * \param bit_index resource to unclaim (bit index into array of bits) + * \param bit_index resource to check (bit index into array of bits) * \return true if the resource is claimed */ -bool hw_is_claimed(uint8_t *bits, uint bit_index); +bool hw_is_claimed(const uint8_t *bits, uint bit_index); /*! \brief Atomically unclaim a resource * \ingroup hardware_claim @@ -87,7 +91,7 @@ void hw_claim_clear(uint8_t *bits, uint bit_index); * * \return a token to pass to hw_claim_unlock() */ -uint32_t hw_claim_lock(); +uint32_t hw_claim_lock(void); /*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library * \ingroup hardware_claim @@ -98,4 +102,8 @@ uint32_t hw_claim_lock(); */ void hw_claim_unlock(uint32_t token); -#endif \ No newline at end of file +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt index 3718d833cc5..ceb29e22510 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/CMakeLists.txt @@ -1,11 +1,13 @@ pico_simple_hardware_target(clocks) target_link_libraries(hardware_clocks INTERFACE + hardware_gpio + hardware_irq hardware_resets - hardware_watchdog - hardware_xosc hardware_pll # not currently used by clocks.c, but sensibly bundled here # as changing frequencies may require upping voltage hardware_vreg + hardware_watchdog + hardware_xosc ) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c index 6195dcd5756..f51331aacdf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/clocks.c @@ -7,7 +7,6 @@ #include "pico.h" #include "hardware/regs/clocks.h" #include "hardware/platform_defs.h" -#include "hardware/resets.h" #include "hardware/clocks.h" #include "hardware/watchdog.h" #include "hardware/pll.h" @@ -71,6 +70,8 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, // propagating when changing aux mux. Note it would be a really bad idea // to do this on one of the glitchless clocks (clk_sys, clk_ref). else { + // Disable clock. On clk_ref and clk_sys this does nothing, + // all other clocks have the ENABLE bit in the same position. hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); if (configured_freq[clk_index] > 0) { // Delay for 3 cycles of the target clock, for ENABLE propagation. @@ -78,8 +79,9 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, // necessarily running, nor is timer... so, 3 cycles per loop: uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1; asm volatile ( + ".syntax unified \n\t" "1: \n\t" - "sub %0, #1 \n\t" + "subs %0, #1 \n\t" "bne 1b" : "+r" (delay_cyc) ); @@ -101,6 +103,8 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, tight_loop_contents(); } + // Enable clock. On clk_ref and clk_sys this does nothing, + // all other clocks have the ENABLE bit in the same position. hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); // Now that the source is configured, we can trust that the user-supplied @@ -108,7 +112,7 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, clock->div = div; // Store the configured frequency - configured_freq[clk_index] = freq; + configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div); return true; } @@ -148,9 +152,6 @@ void clocks_init(void) { // PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz /// \end::pll_settings[] - reset_block(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS); - unreset_block_wait(RESETS_RESET_PLL_SYS_BITS | RESETS_RESET_PLL_USB_BITS); - /// \tag::pll_init[] pll_init(pll_sys, 1, 1500 * MHZ, 6, 2); pll_init(pll_usb, 1, 480 * MHZ, 5, 2); @@ -321,7 +322,7 @@ void clock_gpio_init(uint gpio, uint src, uint div) { if (gpio == 21) gpclk = clk_gpout0; else if (gpio == 23) gpclk = clk_gpout1; else if (gpio == 24) gpclk = clk_gpout2; - else if (gpio == 26) gpclk = clk_gpout3; + else if (gpio == 25) gpclk = clk_gpout3; else { invalid_params_if(CLOCKS, true); } @@ -386,4 +387,4 @@ bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_fr // Now we have the src, auxsrc, and configured the gpio input // call clock configure to run the clock from a gpio return clock_configure(clk_index, src, auxsrc, src_freq, freq); -} \ No newline at end of file +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h index 35940eaaeeb..04d373dcb78 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h @@ -99,7 +99,7 @@ extern "C" { * * Must be called before any other clock function. */ -void clocks_init(); +void clocks_init(void); /*! \brief Configure the specified clock * \ingroup hardware_clocks @@ -140,7 +140,7 @@ uint32_t frequency_count_khz(uint src); /*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock * \ingroup hardware_clocks * - * \see clock_get_hz + * \see clock_get_hz() */ void clock_set_reported_hz(enum clock_index clk_index, uint hz); @@ -170,7 +170,7 @@ void clocks_enable_resus(resus_callback_t resus_callback); /*! \brief Output an optionally divided clock to the specified gpio pin. * \ingroup hardware_clocks * - * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 26. These GPIOs are connected to the GPOUT0-3 clock generators. + * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators. * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator. * \param div The amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt index 3bbdded5a11..296a1efef6d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/CMakeLists.txt @@ -1,4 +1,3 @@ -add_library(hardware_divider INTERFACE) +pico_simple_hardware_headers_only_target(divider) target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S) -target_include_directories(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(hardware_divider INTERFACE hardware_structs) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h index 42a7b6dbb0e..0be2ef818f9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider.h @@ -36,6 +36,10 @@ * \include hello_divider.c */ +#ifdef __cplusplus +extern "C" { +#endif + typedef uint64_t divmod_result_t; /*! \brief Start a signed asynchronous divide @@ -49,8 +53,8 @@ typedef uint64_t divmod_result_t; */ static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET); - sio_hw->div_sdividend = a; - sio_hw->div_sdivisor = b; + sio_hw->div_sdividend = (uint32_t)a; + sio_hw->div_sdivisor = (uint32_t)b; } /*! \brief Start an unsigned asynchronous divide @@ -74,7 +78,7 @@ static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { * * Wait for a divide to complete */ -static inline void hw_divider_wait_ready() { +static inline void hw_divider_wait_ready(void) { // this is #1 in lsr below static_assert(SIO_DIV_CSR_READY_BITS == 1, ""); @@ -99,7 +103,7 @@ static inline void hw_divider_wait_ready() { * * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. */ -static inline divmod_result_t hw_divider_result_nowait() { +static inline divmod_result_t hw_divider_result_nowait(void) { // as ugly as this looks it is actually quite efficient divmod_result_t rc = (((divmod_result_t) sio_hw->div_remainder) << 32u) | sio_hw->div_quotient; return rc; @@ -112,7 +116,7 @@ static inline divmod_result_t hw_divider_result_nowait() { * * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. */ -static inline divmod_result_t hw_divider_result_wait() { +static inline divmod_result_t hw_divider_result_wait(void) { hw_divider_wait_ready(); return hw_divider_result_nowait(); } @@ -124,7 +128,7 @@ static inline divmod_result_t hw_divider_result_wait() { * * \return Current unsigned quotient result. */ -static inline uint32_t hw_divider_u32_quotient_wait() { +static inline uint32_t hw_divider_u32_quotient_wait(void) { hw_divider_wait_ready(); return sio_hw->div_quotient; } @@ -136,9 +140,9 @@ static inline uint32_t hw_divider_u32_quotient_wait() { * * \return Current signed quotient result. */ -static inline int32_t hw_divider_s32_quotient_wait() { +static inline int32_t hw_divider_s32_quotient_wait(void) { hw_divider_wait_ready(); - return sio_hw->div_quotient; + return (int32_t)sio_hw->div_quotient; } /*! \brief Return result of last asynchronous HW divide, unsigned remainder only @@ -148,9 +152,9 @@ static inline int32_t hw_divider_s32_quotient_wait() { * * \return Current unsigned remainder result. */ -static inline uint32_t hw_divider_u32_remainder_wait() { +static inline uint32_t hw_divider_u32_remainder_wait(void) { hw_divider_wait_ready(); - int32_t rc = sio_hw->div_remainder; + uint32_t rc = sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; } @@ -162,9 +166,9 @@ static inline uint32_t hw_divider_u32_remainder_wait() { * * \return Current remainder results. */ -static inline int32_t hw_divider_s32_remainder_wait() { +static inline int32_t hw_divider_s32_remainder_wait(void) { hw_divider_wait_ready(); - int32_t rc = sio_hw->div_remainder; + int32_t rc = (int32_t)sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; } @@ -290,7 +294,7 @@ static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) { /*! \brief Pause for exact amount of time needed for a asynchronous divide to complete * \ingroup hardware_divider */ -static inline void hw_divider_pause() { +static inline void hw_divider_pause(void) { asm volatile ( "b _1_%=\n" "_1_%=:\n" @@ -330,7 +334,7 @@ static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { hw_divider_divmod_u32_start(a, b); hw_divider_pause(); - int32_t rc = sio_hw->div_remainder; + uint32_t rc = sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; } @@ -347,7 +351,7 @@ static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { hw_divider_divmod_s32_start(a, b); hw_divider_pause(); - return sio_hw->div_quotient; + return (int32_t)sio_hw->div_quotient; } /*! \brief Do a hardware signed HW divide, wait for result, return remainder @@ -362,7 +366,7 @@ static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { hw_divider_divmod_s32_start(a, b); hw_divider_pause(); - int32_t rc = sio_hw->div_remainder; + int32_t rc = (int32_t)sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; } @@ -392,4 +396,8 @@ void hw_divider_save_state(hw_divider_state_t *dest); void hw_divider_restore_state(hw_divider_state_t *src); +#ifdef __cplusplus +} +#endif + #endif // _HARDWARE_DIVIDER_H diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S new file mode 100644 index 00000000000..062e12d62c1 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_divider/include/hardware/divider_helper.S @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" + +#if SIO_DIV_CSR_READY_LSB == 0 +.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 +#else +need to change SHIFT above +#endif +#if SIO_DIV_CSR_DIRTY_LSB == 1 +.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2 +#else +need to change SHIFT above +#endif + +// SIO_BASE ptr in r2; pushes r4-r7, lr to stack +// requires that division started at least 2 cycles prior to the start of the macro +.macro save_div_state_and_lr +// originally we did this, however a) it uses r3, and b) the push takes 6 cycles, b) +// any IRQ which uses the divider will necessarily put the data back, which will +// immediately make it ready +// +// // ldr r3, [r2, #SIO_DIV_CSR_OFFSET] +// // // wait for results as we can't save signed-ness of operation +// // 1: +// // lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY +// // bcc 1b + +// 6 cycles +push {r4, r5, r6, r7, lr} +// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! +ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] +ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] +ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] +ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] +.endm + +// restores divider state from r4-r7, then pops them and pc +.macro restore_div_state_and_return +// writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order +// +// it is worth considering what happens if we are interrupted +// +// after writing r4: we are DIRTY and !READY +// ... interruptor using div will complete based on incorrect inputs, but dividend at least will be +// saved/restored correctly and we'll restore the rest ourselves +// after writing r4, r5: we are DIRTY and !READY +// ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor +// at least will be saved/restored correctly and and we'll restore the rest ourselves +// after writing r4, r5, r6: we are DIRTY and READY +// ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), +// and we'll restore the remainder after the fact + +// note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space +// and so 4 reads is cheaper (and we don't have to adjust r2) +// note also, that we must restore via UDIVI* rather than SDIVI* to prevent the quotient/remainder being negated on read based +// on the signs of the inputs +str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] +str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] +str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] +str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] +pop {r4, r5, r6, r7, pc} +.endm \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c index c912e7f0c59..90fde06b4ac 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/dma.c @@ -18,6 +18,7 @@ static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG static_assert(NUM_DMA_CHANNELS <= 16, ""); static uint16_t _claimed; +static uint8_t _timer_claimed; void dma_channel_claim(uint channel) { check_dma_channel_param(channel); @@ -39,6 +40,30 @@ int dma_claim_unused_channel(bool required) { return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available"); } +bool dma_channel_is_claimed(uint channel) { + check_dma_channel_param(channel); + return hw_is_claimed((uint8_t *) &_claimed, channel); +} + +void dma_timer_claim(uint timer) { + check_dma_timer_param(timer); + hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed"); +} + +void dma_timer_unclaim(uint timer) { + check_dma_timer_param(timer); + hw_claim_clear(&_timer_claimed, timer); +} + +int dma_claim_unused_timer(bool required) { + return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available"); +} + +bool dma_timer_is_claimed(uint timer) { + check_dma_timer_param(timer); + return hw_is_claimed(&_timer_claimed, timer); +} + #ifndef NDEBUG void print_dma_ctrl(dma_channel_hw_t *channel) { @@ -60,9 +85,10 @@ void print_dma_ctrl(dma_channel_hw_t *channel) { ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0, ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0); } +#endif -void check_dma_channel_param_impl(uint channel) { +#if PARAM_ASSERTIONS_ENABLED(DMA) +void check_dma_channel_param_impl(uint __unused channel) { valid_params_if(DMA, channel < NUM_DMA_CHANNELS); } - #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h index bd30eaf4b3f..7c9406f3177 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h @@ -34,15 +34,19 @@ extern "C" { * * Memory to memory */ -// this is not defined in generated dreq.h -#define DREQ_FORCE 63 +// these are not defined in generated dreq.h +#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 +#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 +#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 +#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 +#define DREQ_FORCE DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma #ifndef PARAM_ASSERTIONS_ENABLED_DMA #define PARAM_ASSERTIONS_ENABLED_DMA 0 #endif -static inline void check_dma_channel_param(uint channel) { +static inline void check_dma_channel_param(__unused uint channel) { #if PARAM_ASSERTIONS_ENABLED(DMA) // this method is used a lot by inline functions so avoid code bloat by deferring to function extern void check_dma_channel_param_impl(uint channel); @@ -50,6 +54,10 @@ static inline void check_dma_channel_param(uint channel) { #endif } +static inline void check_dma_timer_param(__unused uint timer_num) { + valid_params_if(DMA, timer_num < NUM_DMA_TIMERS); +} + inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) { check_dma_channel_param(channel); return &dma_hw->ch[channel]; @@ -94,6 +102,16 @@ void dma_channel_unclaim(uint channel); */ int dma_claim_unused_channel(bool required); +/*! \brief Determine if a dma channel is claimed + * \ingroup hardware_dma + * + * \param channel the dma channel + * \return true if the channel is claimed, false otherwise + * \see dma_channel_claim + * \see dma_channel_claim_mask + */ +bool dma_channel_is_claimed(uint channel); + /** \brief DMA channel configuration * \defgroup channel_config channel_config * \ingroup hardware_dma @@ -186,7 +204,7 @@ static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain */ static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) { assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32); - c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (size << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); + c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); } /*! \brief Set address wrapping parameters @@ -353,7 +371,7 @@ static inline void dma_channel_set_read_addr(uint channel, const volatile void * } } -/*! \brief Set the DMA initial read address +/*! \brief Set the DMA initial write address * \ingroup hardware_dma * * \param channel DMA channel @@ -409,7 +427,8 @@ static inline void dma_channel_configure(uint channel, const dma_channel_config * \param read_addr Sets the initial read address * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. */ -inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, void *read_addr, +inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, + const volatile void *read_addr, uint32_t transfer_count) { // check_dma_channel_param(channel); dma_channel_hw_t *hw = dma_channel_hw_addr(channel); @@ -424,7 +443,7 @@ inline static void __attribute__((always_inline)) dma_channel_transfer_from_buff * \param write_addr Sets the initial write address * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. */ -inline static void dma_channel_transfer_to_buffer_now(uint channel, void *write_addr, uint32_t transfer_count) { +inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) { dma_channel_hw_t *hw = dma_channel_hw_addr(channel); hw->write_addr = (uintptr_t) write_addr; hw->al1_transfer_count_trig = transfer_count; @@ -464,7 +483,7 @@ static inline void dma_channel_abort(uint channel) { while (dma_hw->abort & (1ul << channel)) tight_loop_contents(); } -/*! \brief Enable single DMA channel interrupt 0 +/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0 * \ingroup hardware_dma * * \param channel DMA channel @@ -479,7 +498,7 @@ static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) { hw_clear_bits(&dma_hw->inte0, 1u << channel); } -/*! \brief Enable multiple DMA channels interrupt 0 +/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0 * \ingroup hardware_dma * * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. @@ -493,7 +512,7 @@ static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool } } -/*! \brief Enable single DMA channel interrupt 1 +/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1 * \ingroup hardware_dma * * \param channel DMA channel @@ -508,7 +527,7 @@ static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) { hw_clear_bits(&dma_hw->inte1, 1u << channel); } -/*! \brief Enable multiple DMA channels interrupt 0 +/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1 * \ingroup hardware_dma * * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. @@ -522,6 +541,105 @@ static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool } } +/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + * \param enabled true to enable interrupt via irq_index for specified channel, false to disable. + */ +static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) { + invalid_params_if(DMA, irq_index > 1); + if (irq_index) { + dma_channel_set_irq1_enabled(channel, enabled); + } else { + dma_channel_set_irq0_enabled(channel, enabled); + } +} + +/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. + */ +static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) { + invalid_params_if(DMA, irq_index > 1); + if (irq_index) { + dma_set_irq1_channel_mask_enabled(channel_mask, enabled); + } else { + dma_set_irq0_channel_mask_enabled(channel_mask, enabled); + } +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \return true if the channel is a cause of DMA_IRQ_0, false otherwise + */ +static inline bool dma_channel_get_irq0_status(uint channel) { + check_dma_channel_param(channel); + return dma_hw->ints0 & (1u << channel); +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \return true if the channel is a cause of DMA_IRQ_1, false otherwise + */ +static inline bool dma_channel_get_irq1_status(uint channel) { + check_dma_channel_param(channel); + return dma_hw->ints1 & (1u << channel); +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise + */ +static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) { + invalid_params_if(DMA, irq_index > 1); + check_dma_channel_param(channel); + return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0 + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +static inline void dma_channel_acknowledge_irq0(uint channel) { + check_dma_channel_param(channel); + hw_set_bits(&dma_hw->ints0, (1u << channel)); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +static inline void dma_channel_acknowledge_irq1(uint channel) { + check_dma_channel_param(channel); + hw_set_bits(&dma_hw->ints1, (1u << channel)); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + */ +static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) { + invalid_params_if(DMA, irq_index > 1); + check_dma_channel_param(channel); + hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel)); +} + /*! \brief Check if DMA channel is busy * \ingroup hardware_dma * @@ -540,6 +658,8 @@ inline static bool dma_channel_is_busy(uint channel) { */ inline static void dma_channel_wait_for_finish_blocking(uint channel) { while (dma_channel_is_busy(channel)) tight_loop_contents(); + // stop the compiler hoisting a non volatile buffer access above the DMA completion. + __compiler_memory_barrier(); } /*! \brief Enable the DMA sniffing targeting the specified channel @@ -595,10 +715,75 @@ inline static void dma_sniffer_set_byte_swap_enabled(bool swap) { * \ingroup hardware_dma * */ -inline static void dma_sniffer_disable() { +inline static void dma_sniffer_disable(void) { dma_hw->sniff_ctrl = 0; } +/*! \brief Mark a dma timer as used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. Will cause a panic if the timer + * is already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param timer the dma timer + */ +void dma_timer_claim(uint timer); + +/*! \brief Mark a dma timer as no longer used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. + * + * \param timer the dma timer to release + */ +void dma_timer_unclaim(uint timer); + +/*! \brief Claim a free dma timer + * \ingroup hardware_dma + * + * \param required if true the function will panic if none are available + * \return the dma timer number or -1 if required was false, and none were free + */ +int dma_claim_unused_timer(bool required); + +/*! \brief Determine if a dma timer is claimed + * \ingroup hardware_dma + * + * \param timer the dma timer + * \return true if the timer is claimed, false otherwise + * \see dma_timer_claim + */ +bool dma_timer_is_claimed(uint timer); + +/*! \brief Set the divider for the given DMA timer + * \ingroup hardware_dma + * + * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed + * that data elements will be transferred at via a DMA channel using this timer as a DREQ + * + * \param timer the dma timer + * \param numerator the fraction's numerator + * \param denominator the fraction's denominator + */ +static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) { + check_dma_timer_param(timer); + dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB); +} + +/*! \brief Return the DREQ number for a given DMA timer + * \ingroup hardware_dma + * + * \param timer_num DMA timer number 0-3 + */ +static inline uint dma_get_timer_dreq(uint timer_num) { + static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, ""); + static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, ""); + static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, ""); + check_dma_timer_param(timer_num); + return DREQ_DMA_TIMER0 + timer_num; +} + #ifndef NDEBUG void print_dma_ctrl(dma_channel_hw_t *channel); #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/CMakeLists.txt new file mode 100644 index 00000000000..a994dc08d1b --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(exception) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/exception.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/exception.c new file mode 100644 index 00000000000..8a9a108fd7c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/exception.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/exception.h" +#include "hardware/regs/m0plus.h" +#include "hardware/platform_defs.h" +#include "hardware/structs/scb.h" + +#include "pico/mutex.h" +#include "pico/assert.h" + +#ifndef exception_is_compile_time_default +static bool exception_is_compile_time_default(exception_handler_t handler) { + extern char __default_isrs_start; + extern char __default_isrs_end; + return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start && + ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end; +} +#endif + +static inline exception_handler_t *get_vtable(void) { + return (exception_handler_t *) scb_hw->vtor; +} + +static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) { + // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness) + get_vtable()[16 + num] = handler; + __dmb(); + restore_interrupts(save); +} + +static inline void check_exception_param(__unused enum exception_number num) { + invalid_params_if(EXCEPTION, num < NMI_EXCEPTION || num >=0); +} + +exception_handler_t exception_get_vtable_handler(enum exception_number num) { + check_exception_param(num); + return get_vtable()[16 + num]; +} + +exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) { + check_exception_param(num); +#if !PICO_NO_RAM_VECTOR_TABLE + uint32_t save = save_and_disable_interrupts(); + exception_handler_t current = exception_get_vtable_handler(num); + hard_assert(handler == current || exception_is_compile_time_default(current)); + set_raw_exception_handler_and_restore_interrupts(num, handler, save); +#else + panic_unsupported(); +#endif + return current; +} + +void exception_restore_handler(enum exception_number num, exception_handler_t original_handler) { + hard_assert(exception_is_compile_time_default(original_handler)); +#if !PICO_NO_RAM_VECTOR_TABLE + uint32_t save = save_and_disable_interrupts(); + set_raw_exception_handler_and_restore_interrupts(num, original_handler, save); +#else + panic_unsupported(); +#endif +} \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h new file mode 100644 index 00000000000..005168bcdd8 --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_EXCEPTION_H_ +#define _HARDWARE_EXCEPTION_H_ + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +/** \file exception.h + * \defgroup hardware_exception hardware_exception + * + * Methods for setting processor exception handlers + * + * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to + * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16) + * + * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent. + * + * \note That all exception APIs affect the executing core only (i.e. the core calling the function). + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception +#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION +#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Exception number definitions + * + * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is + * the number here plus 16. + * + * Name | Value | Exception + * ---------------------|-------|---------- + * NMI_EXCEPTION | -14 | Non Maskable Interrupt + * HARDFAULT_EXCEPTION | -13 | HardFault + * SVCALL_EXCEPTION | -5 | SV Call + * PENDSV_EXCEPTION | -2 | Pend SV + * SYSTICK_EXCEPTION | -1 | System Tick + * + * \ingroup hardware_exception + */ +enum exception_number { + NMI_EXCEPTION = -14, /* Non Maskable Interrupt */ + HARDFAULT_EXCEPTION = -13, /* HardFault Interrupt */ + SVCALL_EXCEPTION = -5, /* SV Call Interrupt */ + PENDSV_EXCEPTION = -2, /* Pend SV Interrupt */ + SYSTICK_EXCEPTION = -1, /* System Tick Interrupt */ +}; + +/*! \brief Exception handler function type + * \ingroup hardware_exception + * + * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions + */ +typedef void (*exception_handler_t)(void); + +/*! \brief Set the exception handler for an exception on the executing core. + * \ingroup hardware_exception + * + * This method will assert if an exception handler has been set for this exception number on this core via + * this method, without an intervening restore via exception_restore_handler. + * + * \note this method may not be used to override an exception handler that was specified at link time by + * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too. + * + * \param num Exception number + * \param handler The handler to set + * \see exception_number + */ +exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler); + +/*! \brief Restore the original exception handler for an exception on this core + * \ingroup hardware_exception + * + * This method may be used to restore the exception handler for an exception on this core to the state + * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler() + * may be called again in the future. + * + * \param num Exception number \ref exception_number + * \param original_handler The original handler returned from \ref exception_set_exclusive_handler + * \see exception_set_exclusive_handler() + */ +void exception_restore_handler(enum exception_number num, exception_handler_t original_handler); + +/*! \brief Get the current exception handler for the specified exception from the currently installed vector table + * of the execution core + * \ingroup hardware_exception + * + * \param num Exception number + * \return the address stored in the VTABLE for the given exception number + */ +exception_handler_t exception_get_vtable_handler(enum exception_number num); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt index 1ccab3351ff..968256661d9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/CMakeLists.txt @@ -1,8 +1,2 @@ -add_library(hardware_flash INTERFACE) - -target_sources(hardware_flash INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/flash.c - ) - -target_include_directories(hardware_flash INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) -target_link_libraries(hardware_flash INTERFACE pico_base_headers pico_bootrom) +pico_simple_hardware_target(flash) +target_link_libraries(hardware_flash INTERFACE pico_bootrom) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c index 8657ba50233..56993026b97 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/flash.c @@ -18,8 +18,6 @@ #define FLASH_RUID_DATA_BYTES 8 #define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES) -#define __compiler_barrier() asm volatile("" ::: "memory") - //----------------------------------------------------------------------------- // Infrastructure for reentering XIP mode after exiting for programming (take // a copy of boot2 before XIP exit). Calling boot2 as a function works because @@ -33,26 +31,26 @@ static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; static bool boot2_copyout_valid = false; -static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() { +static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) { if (boot2_copyout_valid) return; for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i]; - __compiler_barrier(); + __compiler_memory_barrier(); boot2_copyout_valid = true; } -static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() { +static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { ((void (*)(void))boot2_copyout+1)(); } #else -static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() {} +static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {} -static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() { +static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { // Set up XIP for 03h read on bus access (slow but generic) - void (*flash_enter_cmd_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('C', 'X')); + rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); assert(flash_enter_cmd_xip); flash_enter_cmd_xip(); } @@ -68,16 +66,15 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_ #endif invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1)); invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1)); - void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); - void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); - void (*flash_range_erase)(uint32_t, size_t, uint32_t, uint8_t) = - (void(*)(uint32_t, size_t, uint32_t, uint8_t))rom_func_lookup(rom_table_code('R', 'E')); - void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); + rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); + rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); + rom_flash_range_erase_fn flash_range_erase = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); + rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache); flash_init_boot2_copyout(); // No flash accesses after this point - __compiler_barrier(); + __compiler_memory_barrier(); connect_internal_flash(); flash_exit_xip(); @@ -92,15 +89,14 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con #endif invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1)); invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1)); - void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); - void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); - void (*flash_range_program)(uint32_t, const uint8_t*, size_t) = - (void(*)(uint32_t, const uint8_t*, size_t))rom_func_lookup(rom_table_code('R', 'P')); - void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); + rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); + rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); + rom_flash_range_program_fn flash_range_program = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); + rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache); flash_init_boot2_copyout(); - __compiler_barrier(); + __compiler_memory_barrier(); connect_internal_flash(); flash_exit_xip(); @@ -125,15 +121,13 @@ static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) { ); } -// May want to expose this at some point but this is unlikely to be the right -// interface to do so. Keep it static -static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { - void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F')); - void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X')); - void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C')); +void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { + rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); + rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); + rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); assert(connect_internal_flash && flash_exit_xip && flash_flush_cache); flash_init_boot2_copyout(); - __compiler_barrier(); + __compiler_memory_barrier(); connect_internal_flash(); flash_exit_xip(); @@ -151,7 +145,7 @@ static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, ui --tx_remaining; } if (can_get && rx_remaining) { - *rxbuf++ = ssi_hw->dr0; + *rxbuf++ = (uint8_t)ssi_hw->dr0; --rx_remaining; } } @@ -169,6 +163,7 @@ static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, ""); void flash_get_unique_id(uint8_t *id_out) { #if PICO_NO_FLASH + __unused uint8_t *ignore = id_out; panic_unsupported(); #else uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0}; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h index 40e2949d6e6..e6cd229bb3e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h @@ -9,17 +9,6 @@ #include "pico.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash -#ifndef PARAM_ASSERTIONS_ENABLED_FLASH -#define PARAM_ASSERTIONS_ENABLED_FLASH 0 -#endif - -#define FLASH_PAGE_SIZE (1u << 8) -#define FLASH_SECTOR_SIZE (1u << 12) -#define FLASH_BLOCK_SIZE (1u << 16) - -#define FLASH_UNIQUE_ID_SIZE_BYTES 8 - /** \file flash.h * \defgroup hardware_flash hardware_flash * @@ -44,6 +33,22 @@ * \include flash_program.c */ +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash +#ifndef PARAM_ASSERTIONS_ENABLED_FLASH +#define PARAM_ASSERTIONS_ENABLED_FLASH 0 +#endif + +#define FLASH_PAGE_SIZE (1u << 8) +#define FLASH_SECTOR_SIZE (1u << 12) +#define FLASH_BLOCK_SIZE (1u << 16) + +#define FLASH_UNIQUE_ID_SIZE_BYTES 8 + +// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash + +#ifdef __cplusplus +extern "C" { +#endif /*! \brief Erase areas of flash * \ingroup hardware_flash @@ -75,4 +80,34 @@ void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count) */ void flash_get_unique_id(uint8_t *id_out); +/*! \brief Execute bidirectional flash command + * \ingroup hardware_flash + * + * Low-level function to execute a serial command on a flash device attached + * to the QSPI interface. Bytes are simultaneously transmitted and received + * from txbuf and to rxbuf. Therefore, both buffers must be the same length, + * count, which is the length of the overall transaction. This is useful for + * reading metadata from the flash chip, such as device ID or SFDP + * parameters. + * + * The XIP cache is flushed following each command, in case flash state + * has been modified. Like other hardware_flash functions, the flash is not + * accessible for execute-in-place transfers whilst the command is in + * progress, so entering a flash-resident interrupt handler or executing flash + * code on the second core concurrently will be fatal. To avoid these pitfalls + * it is recommended that this function only be used to extract flash metadata + * during startup, before the main application begins to run: see the + * implementation of pico_get_unique_id() for an example of this. + * + * \param txbuf Pointer to a byte buffer which will be transmitted to the flash + * \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer. + * \param count Length in bytes of txbuf and of rxbuf + */ +void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count); + + +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c index 28a137663b9..2816b971851 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c @@ -10,7 +10,9 @@ #include "hardware/structs/iobank0.h" #include "hardware/irq.h" +#if LIB_PICO_BINARY_INFO #include "pico/binary_info.h" +#endif static gpio_irq_callback_t _callbacks[NUM_CORES]; @@ -27,7 +29,7 @@ int gpio_get_pad(uint gpio) { // This also clears the input/output/irq override bits. void gpio_set_function(uint gpio, enum gpio_function fn) { invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); - invalid_params_if(GPIO, fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); + invalid_params_if(GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); // Set input enable on, output disable off hw_write_masked(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS, @@ -50,11 +52,20 @@ void gpio_set_pulls(uint gpio, bool up, bool down) { invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); hw_write_masked( &padsbank0_hw->io[gpio], - (!!up << PADS_BANK0_GPIO0_PUE_LSB) | (!!down << PADS_BANK0_GPIO0_PDE_LSB), + (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB), PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS ); } +// Direct override for per-GPIO IRQ signal +void gpio_set_irqover(uint gpio, uint value) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&iobank0_hw->io[gpio].ctrl, + value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB, + IO_BANK0_GPIO0_CTRL_IRQOVER_BITS + ); +} + // Direct overrides for pad controls void gpio_set_inover(uint gpio, uint value) { invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); @@ -80,11 +91,58 @@ void gpio_set_oeover(uint gpio, uint value) { ); } -static void _gpio_irq_handler(void) { +void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + if (enabled) + hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); + else + hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); +} + + +bool gpio_is_input_hysteresis_enabled(uint gpio) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0; +} + +void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&padsbank0_hw->io[gpio], + (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB, + PADS_BANK0_GPIO0_SLEWFAST_BITS + ); +} + +enum gpio_slew_rate gpio_get_slew_rate(uint gpio) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + return (enum gpio_slew_rate)((padsbank0_hw->io[gpio] + & PADS_BANK0_GPIO0_SLEWFAST_BITS) + >> PADS_BANK0_GPIO0_SLEWFAST_LSB); +} + + +// Enum encoding should match hardware encoding on RP2040 +static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, ""); +void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + hw_write_masked(&padsbank0_hw->io[gpio], + (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB, + PADS_BANK0_GPIO0_DRIVE_BITS + ); +} + +enum gpio_drive_strength gpio_get_drive_strength(uint gpio) { + invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + return (enum gpio_drive_strength)((padsbank0_hw->io[gpio] + & PADS_BANK0_GPIO0_DRIVE_BITS) + >> PADS_BANK0_GPIO0_DRIVE_LSB); +} + +static void gpio_irq_handler(void) { io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) { - io_rw_32 *status_reg = &irq_ctrl_base->ints[gpio / 8]; + io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8]; uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf; if (events) { // TODO: If both cores care about this event then the second core won't get the irq? @@ -124,7 +182,7 @@ void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled // TODO: Do we want to support a callback per GPIO pin? // Install IRQ handler _callbacks[get_core_num()] = callback; - irq_set_exclusive_handler(IO_IRQ_BANK0, _gpio_irq_handler); + irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler); irq_set_enabled(IO_IRQ_BANK0, true); } @@ -141,7 +199,9 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events) { void gpio_debug_pins_init() { gpio_init_mask(DEBUG_PIN_MASK); gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK); +#if LIB_PICO_BINARY_INFO bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug")); +#endif } void gpio_set_input_enabled(uint gpio, bool enabled) { @@ -151,7 +211,7 @@ void gpio_set_input_enabled(uint gpio, bool enabled) { hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); } -void _gpio_init(uint gpio) { +void gpio_init(uint gpio) { sio_hw->gpio_oe_clr = 1ul << gpio; sio_hw->gpio_clr = 1ul << gpio; gpio_set_function(gpio, GPIO_FUNC_SIO); @@ -160,7 +220,7 @@ void _gpio_init(uint gpio) { void gpio_init_mask(uint gpio_mask) { for(uint i=0;i<32;i++) { if (gpio_mask & 1) { - _gpio_init(i); + gpio_init(i); } gpio_mask >>= 1; } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h index 563c6a0137e..7037e85d99b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h @@ -96,7 +96,7 @@ enum gpio_function { GPIO_FUNC_PIO1 = 7, GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, - GPIO_FUNC_NULL = 0xf, + GPIO_FUNC_NULL = 0x1f, }; #define GPIO_OUT 1 @@ -124,6 +124,13 @@ enum gpio_irq_level { GPIO_IRQ_EDGE_RISE = 0x8u, }; +/*! Callback function type for GPIO events + * \ingroup hardware_gpio + * + * \param gpio Which GPIO caused this interrupt + * \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details. + * \sa gpio_set_irq_enabled_with_callback() + */ typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events); enum gpio_override { @@ -133,6 +140,31 @@ enum gpio_override { GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output }; +/*! \brief Slew rate limiting levels for GPIO outputs + * \ingroup hardware_gpio + * + * Slew rate limiting increases the minimum rise/fall time when a GPIO output + * is lightly loaded, which can help to reduce electromagnetic emissions. + * \sa gpio_set_slew_rate + */ +enum gpio_slew_rate { + GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled + GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled +}; + +/*! \brief Drive strength levels for GPIO outputs + * \ingroup hardware_gpio + * + * Drive strength levels for GPIO outputs. + * \sa gpio_set_drive_strength + */ +enum gpio_drive_strength { + GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength + GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength + GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength + GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength +}; + // ---------------------------------------------------------------------------- // Pad Controls + IO Muxing // ---------------------------------------------------------------------------- @@ -146,6 +178,12 @@ enum gpio_override { */ void gpio_set_function(uint gpio, enum gpio_function fn); +/*! \brief Determine current GPIO function + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return Which GPIO function is currently selected from list \ref gpio_function + */ enum gpio_function gpio_get_function(uint gpio); /*! \brief Select up and down pulls on specific GPIO @@ -207,6 +245,16 @@ static inline void gpio_disable_pulls(uint gpio) { gpio_set_pulls(gpio, false, false); } +/*! \brief Set GPIO IRQ override + * \ingroup hardware_gpio + * + * Optionally invert a GPIO IRQ signal, or drive it high or low + * + * \param gpio GPIO number + * \param value See \ref gpio_override + */ +void gpio_set_irqover(uint gpio, uint value); + /*! \brief Set GPIO output override * \ingroup hardware_gpio * @@ -239,6 +287,65 @@ void gpio_set_oeover(uint gpio, uint value); */ void gpio_set_input_enabled(uint gpio, bool enabled); +/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger) + * \ingroup hardware_gpio + * + * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is + * enabled on all GPIOs by default. Disabling input hysteresis can lead to + * inconsistent readings when the input signal has very long rise or fall + * times, but slightly reduces the GPIO's input delay. + * + * \sa gpio_is_input_hysteresis_enabled + * \param gpio GPIO number + * \param enabled true to enable input hysteresis on specified GPIO + */ +void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); + +/*! \brief Determine whether input hysteresis is enabled on a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_input_hysteresis_enabled + * \param gpio GPIO number + */ +bool gpio_is_input_hysteresis_enabled(uint gpio); + + +/*! \brief Set slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_get_slew_rate + * \param gpio GPIO number + * \param slew GPIO output slew rate + */ +void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew); + +/*! \brief Determine current slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_slew_rate + * \param gpio GPIO number + * \return Current slew rate of that GPIO + */ +enum gpio_slew_rate gpio_get_slew_rate(uint gpio); + +/*! \brief Set drive strength for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_get_drive_strength + * \param gpio GPIO number + * \param drive GPIO output drive strength + */ +void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive); + +/*! \brief Determine current slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_drive_strength + * \param gpio GPIO number + * \return Current drive strength of that GPIO + */ +enum gpio_drive_strength gpio_get_drive_strength(uint gpio); + /*! \brief Enable or disable interrupts for specified GPIO * \ingroup hardware_gpio * @@ -267,7 +374,7 @@ void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled); * the processor that calls the function. * * \param gpio GPIO number - * \param events Which events will cause an interrupt See \ref gpio_set_irq_enabled for details. + * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details. * \param enabled Enable or disable flag * \param callback user function to call on GPIO irq. Note only one of these can be set per processor. * @@ -300,17 +407,17 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events); /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) * \ingroup hardware_gpio * - * Clear the output enable (i.e. set to input) + * Clear the output enable (i.e. set to input). * Clear any output value. * * \param gpio GPIO number */ -void _gpio_init(uint gpio); +void gpio_init(uint gpio); /*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) * \ingroup hardware_gpio * - * Clear the output enable (i.e. set to input) + * Clear the output enable (i.e. set to input). * Clear any output value. * * \param gpio_mask Mask with 1 bit per GPIO number to initialize @@ -335,7 +442,7 @@ static inline bool gpio_get(uint gpio) { * * \return Bitmask of raw GPIO values, as bits 0-29 */ -static inline uint32_t gpio_get_all() { +static inline uint32_t gpio_get_all(void) { return sio_hw->gpio_in; } @@ -408,6 +515,26 @@ static inline void gpio_put(uint gpio, bool value) { gpio_clr_mask(mask); } +/*! \brief Determine whether a GPIO is currently driven high or low + * \ingroup hardware_gpio + * + * This function returns the high/low output level most recently assigned to a + * GPIO via gpio_put() or similar. This is the value that is presented outward + * to the IO muxing, *not* the input level back from the pad (which can be + * read using gpio_get()). + * + * To avoid races, this function must not be used for read-modify-write + * sequences when driving GPIOs -- instead functions like gpio_put() should be + * used to atomically update GPIOs. This accessor is intended for debug use + * only. + * + * \param gpio GPIO number + * \return true if the GPIO output level is high, false if low. + */ +static inline bool gpio_get_out_level(uint gpio) { + return !!(sio_hw->gpio_out & (1u << gpio)); +} + // ---------------------------------------------------------------------------- // Direction // ---------------------------------------------------------------------------- @@ -490,7 +617,7 @@ static inline uint gpio_get_dir(uint gpio) { return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway } -extern void gpio_debug_pins_init(); +extern void gpio_debug_pins_init(void); #ifdef __cplusplus } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c index dc2810187ea..95bcfea1104 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c @@ -31,7 +31,7 @@ static inline bool i2c_reserved_addr(uint8_t addr) { return (addr & 0x78) == 0 || (addr & 0x78) == 0x78; } -uint _i2c_init(i2c_inst_t *i2c, uint baudrate) { +uint i2c_init(i2c_inst_t *i2c, uint baudrate) { i2c_reset(i2c); i2c_unreset(i2c); i2c->restart_on_next = false; @@ -43,7 +43,8 @@ uint _i2c_init(i2c_inst_t *i2c, uint baudrate) { I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB | I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS | - I2C_IC_CON_IC_RESTART_EN_BITS; + I2C_IC_CON_IC_RESTART_EN_BITS | + I2C_IC_CON_TX_EMPTY_CTRL_BITS; // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0. i2c->hw->tx_tl = 0; @@ -67,14 +68,32 @@ uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { // TODO there are some subtleties to I2C timing which we are completely ignoring here uint period = (freq_in + baudrate / 2) / baudrate; - uint hcnt = period * 3 / 5; // oof this one hurts - uint lcnt = period - hcnt; + uint lcnt = period * 3 / 5; // oof this one hurts + uint hcnt = period - lcnt; // Check for out-of-range divisors: invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS); invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS); invalid_params_if(I2C, hcnt < 8); invalid_params_if(I2C, lcnt < 8); + // Per I2C-bus specification a device in standard or fast mode must + // internally provide a hold time of at least 300ns for the SDA signal to + // bridge the undefined region of the falling edge of SCL. A smaller hold + // time of 120ns is used for fast mode plus. + uint sda_tx_hold_count; + if (baudrate < 1000000) { + // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns) + // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint. + // Add 1 to avoid division truncation. + sda_tx_hold_count = ((freq_in * 3) / 10000000) + 1; + } else { + // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns) + // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint. + // Add 1 to avoid division truncation. + sda_tx_hold_count = ((freq_in * 3) / 25000000) + 1; + } + assert(sda_tx_hold_count <= lcnt - 2); + i2c->hw->enable = 0; // Always use "fast" mode (<= 400 kHz, works fine for standard mode too) hw_write_masked(&i2c->hw->con, @@ -84,6 +103,9 @@ uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { i2c->hw->fs_scl_hcnt = hcnt; i2c->hw->fs_scl_lcnt = lcnt; i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16; + hw_write_masked(&i2c->hw->sda_hold, + sda_tx_hold_count << I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB, + I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS); i2c->hw->enable = 1; return freq_in / period; @@ -93,16 +115,18 @@ void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) { invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses invalid_params_if(I2C, i2c_reserved_addr(addr)); i2c->hw->enable = 0; + uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS; + uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS; if (slave) { - hw_clear_bits(&i2c->hw->con, - I2C_IC_CON_MASTER_MODE_BITS | - I2C_IC_CON_IC_SLAVE_DISABLE_BITS + hw_write_masked(&i2c->hw->con, + ctrl_set_if_slave, + ctrl_set_if_master | ctrl_set_if_slave ); i2c->hw->sar = addr; } else { - hw_set_bits(&i2c->hw->con, - I2C_IC_CON_MASTER_MODE_BITS | - I2C_IC_CON_IC_SLAVE_DISABLE_BITS + hw_write_masked(&i2c->hw->con, + ctrl_set_if_master, + ctrl_set_if_master | ctrl_set_if_slave ); } i2c->hw->enable = 1; @@ -115,6 +139,7 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint // Synopsys hw accepts start/stop flags alongside data items in the same // FIFO word, so no 0 byte transfers. invalid_params_if(I2C, len == 0); + invalid_params_if(I2C, ((int)len) < 0); i2c->hw->enable = 0; i2c->hw->tar = addr; @@ -123,29 +148,63 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint bool abort = false; bool timeout = false; - uint32_t abort_reason; - size_t byte_ctr; + uint32_t abort_reason = 0; + int byte_ctr; - for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) { + int ilen = (int)len; + for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) { bool first = byte_ctr == 0; - bool last = byte_ctr == len - 1; + bool last = byte_ctr == ilen - 1; i2c->hw->data_cmd = - !!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | - !!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | + bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | + bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | *src++; + // Wait until the transmission of the address/data from the internal + // shift register has completed. For this to function correctly, the + // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag + // was set in i2c_init. do { - // Note clearing the abort flag also clears the reason, and this - // instance of flag is clear-on-read! - abort_reason = i2c->hw->tx_abrt_source; - abort = (bool) i2c->hw->clr_tx_abrt; if (timeout_check) { timeout = timeout_check(ts); abort |= timeout; } tight_loop_contents(); - } while (!abort && !(i2c->hw->status & I2C_IC_STATUS_TFE_BITS)); + } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS)); + + // If there was a timeout, don't attempt to do anything else. + if (!timeout) { + abort_reason = i2c->hw->tx_abrt_source; + if (abort_reason) { + // Note clearing the abort flag also clears the reason, and + // this instance of flag is clear-on-read! Note also the + // IC_CLR_TX_ABRT register always reads as 0. + i2c->hw->clr_tx_abrt; + abort = true; + } + + if (abort || (last && !nostop)) { + // If the transaction was aborted or if it completed + // successfully wait until the STOP condition has occured. + + // TODO Could there be an abort while waiting for the STOP + // condition here? If so, additional code would be needed here + // to take care of the abort. + do { + if (timeout_check) { + timeout = timeout_check(ts); + abort |= timeout; + } + tight_loop_contents(); + } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS)); + + // If there was a timeout, don't attempt to do anything else. + if (!timeout) { + i2c->hw->clr_stop_det; + } + } + } // Note the hardware issues a STOP automatically on an abort condition. // Note also the hardware clears RX FIFO as well as TX on abort, @@ -203,6 +262,7 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses invalid_params_if(I2C, i2c_reserved_addr(addr)); invalid_params_if(I2C, len == 0); + invalid_params_if(I2C, ((int)len) < 0); i2c->hw->enable = 0; i2c->hw->tar = addr; @@ -211,17 +271,17 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds bool abort = false; bool timeout = false; uint32_t abort_reason; - size_t byte_ctr; - - for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) { + int byte_ctr; + int ilen = (int)len; + for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) { bool first = byte_ctr == 0; - bool last = byte_ctr == len - 1; + bool last = byte_ctr == ilen - 1; while (!i2c_get_write_available(i2c)) tight_loop_contents(); i2c->hw->data_cmd = - !!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | - !!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | + bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | + bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read do { @@ -236,7 +296,7 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds if (abort) break; - *dst++ = i2c->hw->data_cmd; + *dst++ = (uint8_t) i2c->hw->data_cmd; } int rval; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index 2b5dca7798b..23ff8f1697a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -10,7 +10,7 @@ #include "pico.h" #include "pico/time.h" #include "hardware/structs/i2c.h" -#include "stdio.h" +#include "hardware/regs/dreq.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c #ifndef PARAM_ASSERTIONS_ENABLED_I2C @@ -27,10 +27,12 @@ extern "C" { * I2C Controller API * * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry - * information between the devices connected to the bus. Each device is recognized by a unique address and can operate as + * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as * either a “transmitter†or “receiverâ€, depending on the function of the device. Devices can also be considered as masters or * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the - * clock signals to permit that transfer. At that time, any device addressed is considered a slave. + * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and + * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed + * is considered a slave. * * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function. * @@ -49,6 +51,10 @@ extern "C" { typedef struct i2c_inst i2c_inst_t; +// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c + /** The I2C identifiers for use in I2C functions. * * e.g. i2c_init(i2c0, 48000) @@ -62,6 +68,14 @@ extern i2c_inst_t i2c1_inst; #define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0 #define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1 +#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C) +#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C)) +#endif + +#ifdef PICO_DEFAULT_I2C_INSTANCE +#define i2c_default PICO_DEFAULT_I2C_INSTANCE +#endif + /** @} */ // ---------------------------------------------------------------------------- @@ -81,7 +95,7 @@ extern i2c_inst_t i2c1_inst; * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) * \return Actual set baudrate */ -uint _i2c_init(i2c_inst_t *i2c, uint baudrate); +uint i2c_init(i2c_inst_t *i2c, uint baudrate); /*! \brief Disable the I2C HW block * \ingroup hardware_i2c @@ -123,11 +137,11 @@ struct i2c_inst { bool restart_on_next; }; -/*! \brief Convert I2c instance to hardware instance number +/*! \brief Convert I2C instance to hardware instance number * \ingroup hardware_i2c * * \param i2c I2C instance - * \return Number of UART, 0 or 1. + * \return Number of I2C, 0 or 1. */ static inline uint i2c_hw_index(i2c_inst_t *i2c) { invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); @@ -143,7 +157,7 @@ static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) { * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -160,7 +174,7 @@ int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -174,7 +188,7 @@ int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -196,7 +210,7 @@ int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t * * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -215,7 +229,7 @@ int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, si * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -228,12 +242,12 @@ int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), * and the next transfer will begin with a Restart rather than a Start. - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present. + * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present. */ int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop); @@ -246,7 +260,7 @@ int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, b * least that many bytes can be written without blocking. */ static inline size_t i2c_get_write_available(i2c_inst_t *i2c) { - const size_t IC_TX_BUFFER_DEPTH = 32; + const size_t IC_TX_BUFFER_DEPTH = 16; return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr; } @@ -268,7 +282,7 @@ static inline size_t i2c_get_read_available(i2c_inst_t *i2c) { * \param src Data to send * \param len Number of bytes to send * - * Writes directly to the to I2C TX FIFO which us mainly useful for + * Writes directly to the I2C TX FIFO which is mainly useful for * slave-mode operation. */ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) { @@ -280,45 +294,35 @@ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, s } } -/*! \brief Write direct to TX FIFO +/*! \brief Read direct from RX FIFO * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 * \param dst Buffer to accept data - * \param len Number of bytes to send + * \param len Number of bytes to read * - * Reads directly from the I2C RX FIFO which us mainly useful for + * Reads directly from the I2C RX FIFO which is mainly useful for * slave-mode operation. */ -static inline size_t i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { - - size_t bytes_read = 0; - +static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { for (size_t i = 0; i < len; ++i) { - - while (!i2c_get_read_available(i2c)) { + while (!i2c_get_read_available(i2c)) tight_loop_contents(); - } - - *dst = i2c_get_hw(i2c)->data_cmd; - bytes_read++; - - //printf("dst %d ,", *dst); - - //Check stop condition - int stop = (i2c->hw->raw_intr_stat & 0x00000200) >> 9; - if (stop && !i2c_get_read_available(i2c)) { - //Clear stop - int clear_stop = i2c_get_hw(i2c)->clr_stop_det; - printf("clear_stop reg: %d\n", clear_stop); - break; - } else { - *dst++; - } - + *dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd; } +} - return bytes_read; +/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance + */ +static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) { + static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, ""); + static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, ""); + static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, ""); + return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx; } #ifdef __cplusplus diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h index 18cefc53eca..35372e97501 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h @@ -55,7 +55,7 @@ typedef struct { } interp_config; static inline uint interp_index(interp_hw_t *interp) { - assert(interp == interp0 || interp == interp1); + valid_params_if(INTERP, interp == interp0 || interp == interp1); return interp == interp1 ? 1 : 0; } @@ -70,6 +70,8 @@ static inline uint interp_index(interp_hw_t *interp) { * \param lane The lane number, 0 or 1. */ void interp_claim_lane(interp_hw_t *interp, uint lane); +// The above really should be called this for consistency +#define interp_lane_claim interp_claim_lane /*! \brief Claim the interpolator lanes specified in the mask * \ingroup hardware_interp @@ -86,6 +88,27 @@ void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask); * \param lane The lane number, 0 or 1 */ void interp_unclaim_lane(interp_hw_t *interp, uint lane); +// The above really should be called this for consistency +#define interp_lane_unclaim interp_unclaim_lane + +/*! \brief Determine if an interpolator lane is claimed + * \ingroup hardware_interp + * + * \param interp Interpolator whose lane to check + * \param lane The lane number, 0 or 1 + * \return true if claimed, false otherwise + * \see interp_claim_lane + * \see interp_claim_lane_mask + */ +bool interp_lane_is_claimed(interp_hw_t *interp, uint lane); + +/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask + * \ingroup hardware_interp + * + * \param interp Interpolator on which to release lanes. interp0 or interp1 + * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid) + */ +void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask); /*! \brief Set the interpolator shift value * \ingroup interp_config @@ -231,7 +254,7 @@ static inline void interp_config_set_force_bits(interp_config *c, uint bits) { * * \return A default interpolation configuration */ -static inline interp_config interp_default_config() { +static inline interp_config interp_default_config(void) { interp_config c = {0}; // Just pass through everything interp_config_set_mask(&c, 0, 31); @@ -277,9 +300,9 @@ static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bi } typedef struct { - io_rw_32 accum[2]; - io_rw_32 base[3]; - io_rw_32 ctrl[2]; + uint32_t accum[2]; + uint32_t base[3]; + uint32_t ctrl[2]; } interp_hw_save_t; /*! \brief Save the specified interpolator state diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c index 5fdad93c191..37e8a913360 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/interp.c @@ -16,10 +16,13 @@ static_assert(NUM_DMA_CHANNELS <= 16, ""); static uint8_t _claimed; +static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) { + return (interp_index(interp) << 1u) | lane; +} + void interp_claim_lane(interp_hw_t *interp, uint lane) { valid_params_if(INTERP, lane < 2); - uint bit = (interp_index(interp) << 1u) | lane; - hw_claim_or_assert((uint8_t *) &_claimed, bit, "Lane is already claimed"); + hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed"); } void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) { @@ -30,8 +33,18 @@ void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) { void interp_unclaim_lane(interp_hw_t *interp, uint lane) { valid_params_if(INTERP, lane < 2); - uint bit = (interp_index(interp) << 1u) | lane; - hw_claim_clear((uint8_t *) &_claimed, bit); + hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); +} + +bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) { + valid_params_if(INTERP, lane < 2); + return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); +} + +void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) { + valid_params_if(INTERP, lane_mask <= 0x3); + if (lane_mask & 1u) interp_unclaim_lane(interp, 0); + if (lane_mask & 2u) interp_unclaim_lane(interp, 1); } void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h index 6075118f273..424a49712fa 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h @@ -8,12 +8,12 @@ #define _HARDWARE_IRQ_H_ // These two config items are also used by assembler, so keeping separate -// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum Number of shared IRQ handers, default=4, advanced=true, group=hardware_irq +// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq #ifndef PICO_MAX_SHARED_IRQ_HANDLERS #define PICO_MAX_SHARED_IRQ_HANDLERS 4u #endif -// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handers, type=bool, default=0, group=hardware_irq +// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq #ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS #define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 #endif @@ -21,6 +21,7 @@ #ifndef __ASSEMBLER__ #include "pico.h" +#include "hardware/address_mapped.h" #include "hardware/regs/intctrl.h" #include "hardware/regs/m0plus.h" @@ -36,13 +37,13 @@ * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). * * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts - * where there is one IO interrupt per bank, per core. These are completely independent, so for example, processor 0 can be + * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. * * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). * * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions - * or starvation of one of the cores. Additionally don't forget that disabling interrupts on one core does not disable interrupts + * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts * on the other core. * * There are three different ways to set handlers for an IRQ: @@ -52,7 +53,7 @@ * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). * * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will - * be in r0. + * be in register r0. * * \section interrupt_nums Interrupt Numbers * @@ -94,8 +95,8 @@ #define PICO_DEFAULT_IRQ_PRIORITY 0x80 #endif -#define PICO_LOWEST_IRQ_PRIORITY 0x01 -#define PICO_HIGHEST_IRQ_PRIORITY 0xff +#define PICO_LOWEST_IRQ_PRIORITY 0xff +#define PICO_HIGHEST_IRQ_PRIORITY 0x00 // PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq #ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY @@ -116,19 +117,41 @@ extern "C" { * * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions */ -typedef void (*irq_handler_t)(); +typedef void (*irq_handler_t)(void); -/*! \brief Set specified interrupts priority +static inline void check_irq_param(__unused uint num) { + invalid_params_if(IRQ, num >= NUM_IRQS); +} + +/*! \brief Set specified interrupt's priority * \ingroup hardware_irq * * \param num Interrupt number - * \param hardware_priority Priority to set. Hardware priorities range from 0 (lowest) to 255 (highest) though only - * the top 2 bits are significant on ARM Cortex M0+. To make it easier to specify higher or lower priorities - * than the default, all IRQ priorities are initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * \param hardware_priority Priority to set. + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 */ void irq_set_priority(uint num, uint8_t hardware_priority); +/*! \brief Get specified interrupt's priority + * \ingroup hardware_irq + * + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + * + * \param num Interrupt number + * \return the IRQ priority + */ +uint irq_get_priority(uint num); + /*! \brief Enable or disable a specific interrupt on the executing core * \ingroup hardware_irq * @@ -165,7 +188,7 @@ void irq_set_mask_enabled(uint32_t mask, bool enabled); * * \param num Interrupt number \ref interrupt_nums * \param handler The handler to set. See \ref irq_handler_t - * \see irq_add_shared_handler + * \see irq_add_shared_handler() */ void irq_set_exclusive_handler(uint num, irq_handler_t handler); @@ -176,7 +199,7 @@ void irq_set_exclusive_handler(uint num, irq_handler_t handler); * by irq_set_exclusive_handler if there is one. * * \param num Interrupt number \ref interrupt_nums - * \see irq_set_exclusive_handler + * \see irq_set_exclusive_handler() * \return handler The handler if an exclusive handler is set for the IRQ, * NULL if no handler is set or shared/shareable handlers are installed */ @@ -201,7 +224,7 @@ irq_handler_t irq_get_exclusive_handler(uint num); * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of * the priority range by default. * - * \see irq_set_exclusive_handler + * \see irq_set_exclusive_handler() */ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); @@ -218,8 +241,8 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior * * \param num Interrupt number \ref interrupt_nums * \param handler The handler to removed. - * \see irq_set_exclusive_handler - * \see irq_add_shared_handler + * \see irq_set_exclusive_handler() + * \see irq_add_shared_handler() */ void irq_remove_handler(uint num, irq_handler_t handler); @@ -241,7 +264,7 @@ static inline void irq_clear(uint int_num) { *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F))); } -/*! \brief Force an interrupt to pending on the executing core +/*! \brief Force an interrupt to be pending on the executing core * \ingroup hardware_irq * * This should generally not be used for IRQs connected to hardware. @@ -251,11 +274,11 @@ static inline void irq_clear(uint int_num) { void irq_set_pending(uint num); -/*! \brief Perform IRQ priority intiialization for the current core +/*! \brief Perform IRQ priority initialization for the current core * * \note This is an internal method and user should generally not call it. */ -void irq_init_priorities(); +void irq_init_priorities(void); #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c index 255c00df808..211f6d02b98 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq.c @@ -12,10 +12,9 @@ #include "pico/mutex.h" #include "pico/assert.h" -extern void __unhandled_user_irq(); -extern uint __get_current_exception(); +extern void __unhandled_user_irq(void); -static inline irq_handler_t *get_vtable() { +static inline irq_handler_t *get_vtable(void) { return (irq_handler_t *) scb_hw->vtor; } @@ -24,7 +23,7 @@ static inline void *add_thumb_bit(void *addr) { } static inline void *remove_thumb_bit(void *addr) { - return (void *) (((uintptr_t) addr) & ~0x1); + return (void *) (((uintptr_t) addr) & (uint)~0x1); } static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) { @@ -34,10 +33,6 @@ static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save); } -static inline void check_irq_param(uint num) { - invalid_params_if(IRQ, num >= NUM_IRQS); -} - void irq_set_enabled(uint num, bool enabled) { check_irq_param(num); irq_set_mask_enabled(1u << num, enabled); @@ -64,13 +59,13 @@ void irq_set_pending(uint num) { *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; } -#if PICO_MAX_SHARED_IRQ_HANDLERS +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS // limited by 8 bit relative links (and reality) static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, ""); // note these are not real functions, they are code fragments (i.e. don't call them) -extern void irq_handler_chain_first_slot(); -extern void irq_handler_chain_remove_tail(); +extern void irq_handler_chain_first_slot(void); +extern void irq_handler_chain_remove_tail(void); extern struct irq_handler_chain_slot { // first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next @@ -93,11 +88,13 @@ extern struct irq_handler_chain_slot { } irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS]; static int8_t irq_hander_chain_free_slot_head; -#endif static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) { return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots); } +#else +#define is_shared_irq_raw_handler(h) false +#endif irq_handler_t irq_get_vtable_handler(uint num) { check_irq_param(num); @@ -134,12 +131,13 @@ irq_handler_t irq_get_exclusive_handler(uint num) { } +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS static uint16_t make_branch(uint16_t *from, void *to) { uint32_t ui_from = (uint32_t)from; uint32_t ui_to = (uint32_t)to; uint32_t delta = (ui_to - ui_from - 4) / 2; assert(!(delta >> 11u)); - return 0xe000 | (delta & 0x7ff); + return (uint16_t)(0xe000 | (delta & 0x7ff)); } static void insert_branch_and_link(uint16_t *from, void *to) { @@ -147,8 +145,8 @@ static void insert_branch_and_link(uint16_t *from, void *to) { uint32_t ui_to = (uint32_t)to; uint32_t delta = (ui_to - ui_from - 4) / 2; assert(!(delta >> 11u)); - from[0] = 0xf000 | ((delta >> 11u) & 0x7ffu); - from[1] = 0xf800 | (delta & 0x7ffu); + from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu)); + from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu)); } static inline void *resolve_branch(uint16_t *inst) { @@ -161,35 +159,38 @@ static inline void *resolve_branch(uint16_t *inst) { // GCC produces horrible code for subtraction of pointers here, and it was bugging me static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) { static_assert(sizeof(struct irq_handler_chain_slot) == 12, ""); - int32_t result; + int32_t result = 0xaaaa; // return (to - from); // note this implementation has limited range, but is fine for plenty more than -128->127 result asm (".syntax unified\n" "subs %1, %2\n" "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding) - "ldr %0, =0xaaaa\n" "muls %0, %1\n" "lsrs %0, 20\n" - : "=l" (result), "+l" (to) - : "l" (from) - : - ); - return result; + : "+l" (result), "+l" (to) + : "l" (from) + : + ); + return (int8_t)result; +} + +static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) { + return slot_diff(slot, irq_handler_chain_slots); } +#endif void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) { check_irq_param(num); -#if PICO_DISABLE_SHARED_IRQ_HANDLERS - -#endif -#if PICO_NO_RAM_VECTOR_TABLE || !PICO_MAX_SHARED_IRQ_HANDLERS +#if PICO_NO_RAM_VECTOR_TABLE panic_unsupported() +#elif PICO_DISABLE_SHARED_IRQ_HANDLERS + irq_set_exclusive_handler(num, handler); #else spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); uint32_t save = spin_lock_blocking(lock); - hard_assert(irq_hander_chain_free_slot_head >= 0); + hard_assert(irq_hander_chain_free_slot_head >= 0); // we must have a slot struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head]; - int slot_index = irq_hander_chain_free_slot_head; + int8_t slot_index = irq_hander_chain_free_slot_head; irq_hander_chain_free_slot_head = slot->link; irq_handler_t vtable_handler = get_vtable()[16 + num]; if (!is_shared_irq_raw_handler(vtable_handler)) { @@ -237,7 +238,7 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior .inst1 = 0xa100, // add r1, pc, #0 .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot .inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot - .link = slot_diff(existing_vtable_slot, irq_handler_chain_slots), + .link = get_slot_index(existing_vtable_slot), .priority = order_priority, .handler = handler }; @@ -258,7 +259,7 @@ void irq_remove_handler(uint num, irq_handler_t handler) { uint32_t save = spin_lock_blocking(lock); irq_handler_t vtable_handler = get_vtable()[16 + num]; if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) { -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS if (is_shared_irq_raw_handler(vtable_handler)) { // This is a bit tricky, as an executing IRQ handler doesn't take a lock. @@ -286,14 +287,14 @@ void irq_remove_handler(uint num, irq_handler_t handler) { struct irq_handler_chain_slot *prev_slot = NULL; struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler); struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot; - int to_free_slot_index = to_free_slot - irq_handler_chain_slots; + int8_t to_free_slot_index = get_slot_index(to_free_slot); while (to_free_slot->handler != handler) { prev_slot = to_free_slot; if (to_free_slot->link < 0) break; to_free_slot = &irq_handler_chain_slots[to_free_slot->link]; } if (to_free_slot->handler == handler) { - int next_slot_index = to_free_slot->link; + int8_t next_slot_index = to_free_slot->link; if (next_slot_index >= 0) { // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid // Note this only matters in the exception case anyway, and it that case, we will skip the next handler, @@ -358,18 +359,26 @@ void irq_set_priority(uint num, uint8_t hardware_priority) { *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); } -#if !PICO_DISABLE_SHARED_IRQ_HANDLERS && PICO_MAX_SHARED_IRQ_HANDLERS +uint irq_get_priority(uint num) { + check_irq_param(num); + + // note that only 32 bit reads are supported + io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); + return (uint8_t)(*p >> (8 * (num & 3u))); +} + +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS // used by irq_handler_chain.S to remove the last link in a handler chain after it executes // note this must be called only with the last slot in a chain (and during the exception) void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) { irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot); assert(is_shared_irq_raw_handler(slot_handler)); - int exception = __get_current_exception(); + uint exception = __get_current_exception(); assert(exception); spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); uint32_t save = spin_lock_blocking(lock); - int slot_index = slot - irq_handler_chain_slots; + int8_t slot_index = get_slot_index(slot); if (slot_handler == get_vtable()[exception]) { get_vtable()[exception] = __unhandled_user_irq; } else { @@ -394,8 +403,11 @@ void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) { void irq_init_priorities() { #if PICO_DEFAULT_IRQ_PRIORITY != 0 - for (uint irq = 0; irq < NUM_IRQS; irq++) { - irq_set_priority(irq, PICO_DEFAULT_IRQ_PRIORITY); + static_assert(!(NUM_IRQS & 3), ""); + uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u; + io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET); + for (uint i = 0; i < NUM_IRQS / 4; i++) { + *p++ = prio4; } #endif } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S index 6a8a4b688f3..7d7be7d36aa 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/irq_handler_chain.S @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "hardware/platform_defs.h" +#include "pico.h" #include "hardware/irq.h" #if !PICO_DISABLE_SHARED_IRQ_HANDLERS diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h index 68975a9777f..d2377ac843b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h @@ -25,7 +25,7 @@ * Programmable I/O (PIO) API * * A programmable input/output block (PIO) is a versatile hardware interface which - * can support a number of different IO standards. There are two PIO blocks in the RP2040 + * can support a number of different IO standards. There are two PIO blocks in the RP2040. * * Each PIO is programmable in the same sense as a processor: the four state machines independently * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general @@ -58,6 +58,9 @@ enum pio_fifo_join { PIO_FIFO_JOIN_RX = 2, }; +/** \brief MOV status types + * \ingroup hardware_pio + */ enum pio_mov_status_type { STATUS_TX_LESSTHAN = 0, STATUS_RX_LESSTHAN = 1 @@ -104,10 +107,19 @@ typedef struct { uint32_t pinctrl; } pio_sm_config; -static inline void check_sm_param(uint sm) { +static inline void check_sm_param(__unused uint sm) { valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES); } +static inline void check_sm_mask(__unused uint mask) { + valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); +} + + +static inline void check_pio_param(__unused PIO pio) { + valid_params_if(PIO, pio == pio0 || pio == pio1); +} + /*! \brief Set the 'out' pins in a state machine configuration * \ingroup sm_config * @@ -118,8 +130,8 @@ static inline void check_sm_param(uint sm) { * \param out_count 0-32 Number of pins to set. */ static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) { - assert(out_base < 32); - assert(out_count <= 32); + valid_params_if(PIO, out_base < 32); + valid_params_if(PIO, out_count <= 32); c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); @@ -135,8 +147,8 @@ static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint * \param set_count 0-5 Number of pins to set. */ static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) { - assert(set_base < 32); - assert(set_count <= 5); + valid_params_if(PIO, set_base < 32); + valid_params_if(PIO, set_count <= 5); c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); @@ -148,10 +160,10 @@ static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint * Can overlap with the 'out', ''set' and 'sideset' pins * * \param c Pointer to the configuration structure to modify - * \param in_base 0-31 First pin to set as input + * \param in_base 0-31 First pin to use as input */ static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { - assert(in_base < 32); + valid_params_if(PIO, in_base < 32); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); } @@ -162,10 +174,10 @@ static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { * Can overlap with the 'in', 'out' and 'set' pins * * \param c Pointer to the configuration structure to modify - * \param sideset_base base pin for 'side set' + * \param sideset_base 0-31 base pin for 'side set' */ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) { - assert(sideset_base < 32); + valid_params_if(PIO, sideset_base < 32); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } @@ -174,55 +186,70 @@ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_bas * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param bit_count Number of bits to steal from delay field in the instruction for use of side set + * \param bit_count Number of bits to steal from delay field in the instruction for use of side set (max 5) * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction * \param pindirs True if the side set affects pin directions rather than values */ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) { - assert(bit_count <= 32); + valid_params_if(PIO, bit_count <= 5); + valid_params_if(PIO, !optional || bit_count >= 1); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | - (!!optional << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | - (!!pindirs << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); + (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | + (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); } -/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration +/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration * \ingroup sm_config * - * The clock divider acts on the system clock to provide a clock for the state machine. - * See the datasheet for more details. + * The clock divider can slow the state machine's execution to some rate below + * the system clock frequency, by enabling the state machine on some cycles + * but not on others, in a regular pattern. This can be used to generate e.g. + * a given UART baud rate. See the datasheet for further detail. * * \param c Pointer to the configuration structure to modify - * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n - * will cause the state machine to run 1 cycle in every n. - * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable - * although it will depend on the use case. + * \param div_int Integer part of the divisor + * \param div_frac Fractional part in 1/256ths + * \sa sm_config_set_clkdiv() */ -static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { - uint16_t div_int = (uint16_t) div; - uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); +static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { c->clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | + (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); } -/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration +static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) { + valid_params_if(PIO, div >= 1 && div <= 65536); + *div_int = (uint16_t)div; + if (*div_int == 0) { + *div_frac = 0; + } else { + *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u)); + } +} + +/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration * \ingroup sm_config * - * The clock divider acts on the system clock to provide a clock for the state machine. - * See the datasheet for more details. + * The clock divider slows the state machine's execution by masking the + * system clock on some cycles, in a repeating pattern, so that the state + * machine does not advance. Effectively this produces a slower clock for the + * state machine to run from, which can be used to generate e.g. a particular + * UART baud rate. See the datasheet for further detail. * * \param c Pointer to the configuration structure to modify - * \param div_int Integer part of the divisor - * \param div_frac Fractional part in 1/256ths - * \sa sm_config_set_clkdiv + * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n + * will cause the state machine to run 1 cycle in every n. + * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable + * although it will depend on the use case. */ -static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { - c->clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); +static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { + uint16_t div_int; + uint8_t div_frac; + pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); + sm_config_set_clkdiv_int_frac(c, div_int, div_frac); } /*! \brief Set the wrap addresses in a state machine configuration @@ -234,8 +261,8 @@ static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_ * if the instruction does not itself update the program_counter */ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) { - assert(wrap < PIO_INSTRUCTION_COUNT); - assert(wrap_target < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); @@ -245,10 +272,10 @@ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint w * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction + * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction */ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { - assert(pin < 32); + valid_params_if(PIO, pin < 32); c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); } @@ -259,7 +286,7 @@ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { * \param c Pointer to the configuration structure to modify * \param shift_right true to shift ISR to right, false to shift ISR to left * \param autopush whether autopush is enabled - * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR + * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR */ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) { valid_params_if(PIO, push_threshold <= 32); @@ -267,8 +294,8 @@ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bo ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | - (!!shift_right << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | - (!!autopush << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | + (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | + (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); } @@ -278,7 +305,7 @@ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bo * \param c Pointer to the configuration structure to modify * \param shift_right true to shift OSR to right, false to shift OSR to left * \param autopull whether autopull is enabled - * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR + * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR */ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) { valid_params_if(PIO, pull_threshold <= 32); @@ -286,8 +313,8 @@ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, b ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | - (!!shift_right << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | - (!!autopull << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | + (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | + (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); } @@ -298,9 +325,9 @@ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, b * \param join Specifies the join type. \see enum pio_fifo_join */ static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) { - assert(join >= 0 && join <= 2); - c->shiftctrl = (c->shiftctrl & ~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | - (join << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); + valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX); + c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | + (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); } /*! \brief Set special 'out' operations in a state machine configuration @@ -308,15 +335,15 @@ static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join * * \param c Pointer to the configuration structure to modify * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles) - * \param has_enable_pin true to enable auxiliary OUT enable pin + * \param has_enable_pin true to enable auxiliary OUT enable pin * \param enable_pin_index pin index for auxiliary OUT enable */ -static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, int enable_pin_index) { +static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) { c->execctrl = (c->execctrl & - ~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | + (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | - (!!sticky << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | - (!!has_enable_pin << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | + (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | + (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); } @@ -324,13 +351,14 @@ static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param status_sel the status operation selector + * \param status_sel the status operation selector. \see enum pio_mov_status_type * \param status_n parameter for the mov status operation (currently a bit count) */ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) { + valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN); c->execctrl = (c->execctrl - & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) - | ((status_sel << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) + & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) + | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS); } @@ -349,13 +377,13 @@ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_statu * In Shift | shift_direction=right, autopush=false, push_thrshold=32 * Out Shift | shift_direction=right, autopull=false, pull_thrshold=32 * Jmp Pin | 0 - * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 + * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0 * * \return the default state machine configuration which can then be modified. */ -static inline pio_sm_config pio_get_default_sm_config() { - pio_sm_config c = {0, 0, 0}; +static inline pio_sm_config pio_get_default_sm_config(void) { + pio_sm_config c = {0, 0, 0, 0}; sm_config_set_clkdiv_int_frac(&c, 1, 0); sm_config_set_wrap(&c, 0, 31); sm_config_set_in_shift(&c, true, false, 32); @@ -371,6 +399,7 @@ static inline pio_sm_config pio_get_default_sm_config() { * \param config the configuration to apply */ static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { + check_pio_param(pio); check_sm_param(sm); pio->sm[sm].clkdiv = config->clkdiv; pio->sm[sm].execctrl = config->execctrl; @@ -385,30 +414,42 @@ static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *conf * \return the PIO instance number (either 0 or 1) */ static inline uint pio_get_index(PIO pio) { - assert(pio == pio0 || pio == pio1); + check_pio_param(pio); return pio == pio1 ? 1 : 0; } -/*! \brief Setup the function select for a GPIO to use output from the given PIO instance +/*! \brief Setup the function select for a GPIO to use output from the given PIO instance * \ingroup hardware_pio * + * PIO appears as an alternate function in the GPIO muxing, just like an SPI + * or UART. This function configures that multiplexing to connect a given PIO + * instance to a GPIO. Note that this is not necessary for a state machine to + * be able to read the *input* value from a GPIO, but only for it to set the + * output value or output enable. + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param pin the GPIO pin whose function select to set */ static inline void pio_gpio_init(PIO pio, uint pin) { - assert(pio == pio0 || pio == pio1); + check_pio_param(pio); + valid_params_if(PIO, pin < 32); gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1); } -/*! \brief Return the DREQ to use for pacing transfers to a particular state machine +/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param is_tx true for sending data to the state machine, false for received data from the state machine + * \param is_tx true for sending data to the state machine, false for receiving data from the state machine */ static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) { - assert(pio == pio0 || pio == pio1); + static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, ""); + static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, ""); + static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, ""); + static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, ""); + static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, ""); + check_pio_param(pio); check_sm_param(sm); return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0); } @@ -441,7 +482,7 @@ bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint o /*! \brief Attempt to load the program, panicking if not possible * \ingroup hardware_pio * - * \see pico_can_add_program if you need to check whether the program can be loaded + * \see pio_can_add_program() if you need to check whether the program can be loaded * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param program the program definition @@ -452,7 +493,7 @@ uint pio_add_program(PIO pio, const pio_program_t *program); /*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible * \ingroup hardware_pio * - * \see pico_can_add_program_at_offset if you need to check whether the program can be loaded + * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param program the program definition @@ -480,13 +521,13 @@ void pio_clear_instruction_memory(PIO pio); * \ingroup hardware_pio * * This method: - * - disables the state machine (if running) - * - clears the FIFOs - * - applies the configuration - * - resets any internal state - * - jumps to the initial program location + * - Disables the state machine (if running) + * - Clears the FIFOs + * - Applies the configuration specified by 'config' + * - Resets any internal state e.g. shift counters + * - Jumps to the initial program location given by 'initial_pc' * - * The state machine is disabled on return from this call + * The state machine is left disabled on return from this call. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) @@ -503,7 +544,9 @@ void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) * \param enabled true to enable the state machine; false to disable */ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { - pio->ctrl = (pio->ctrl & ~(1u << sm)) | (!!enabled << sm); + check_pio_param(pio); + check_sm_param(sm); + pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm); } /*! \brief Enable or disable multiple PIO state machines @@ -512,7 +555,7 @@ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { * Note that this method just sets the enabled state of the state machine; * if now enabled they continue exactly from where they left off. * - * \see pio_enable_sm_mask_in_sync if you wish to enable multiple state machines + * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines * and ensure their clock dividers are in sync. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -520,6 +563,8 @@ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { * \param enabled true to enable the state machines; false to disable */ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); } @@ -533,6 +578,8 @@ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) * \param sm State machine index (0..3) */ static inline void pio_sm_restart(PIO pio, uint sm) { + check_pio_param(pio); + check_sm_param(sm); pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm); } @@ -546,43 +593,234 @@ static inline void pio_sm_restart(PIO pio, uint sm) { * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS; } -/*! \brief Restart a state machine's clock divider (resetting the fractional count) +/*! \brief Restart a state machine's clock divider from a phase of 0 * \ingroup hardware_pio * + * Each state machine's clock divider is a free-running piece of hardware, + * that generates a pattern of clock enable pulses for the state machine, + * based *only* on the configured integer/fractional divisor. The pattern of + * running/halted cycles slows the state machine's execution to some + * controlled rate. + * + * This function clears the divider's integer and fractional phase + * accumulators so that it restarts this pattern from the beginning. It is + * called automatically by pio_sm_init() but can also be called at a later + * time, when you enable the state machine, to ensure precisely consistent + * timing each time you load and run a given PIO program. + * + * More commonly this hardware mechanism is used to synchronise the execution + * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask(). + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { + check_pio_param(pio); + check_sm_param(sm); pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm); } -/*! \brief Restart multiple state machines' clock dividers (resetting the fractional count) +/*! \brief Restart multiple state machines' clock dividers from a phase of 0. * \ingroup hardware_pio * - * This method can be used to guarantee that multiple state machines with fractional clock dividers - * are exactly in sync + * Each state machine's clock divider is a free-running piece of hardware, + * that generates a pattern of clock enable pulses for the state machine, + * based *only* on the configured integer/fractional divisor. The pattern of + * running/halted cycles slows the state machine's execution to some + * controlled rate. + * + * This function simultaneously clears the integer and fractional phase + * accumulators of multiple state machines' clock dividers. If these state + * machines all have the same integer and fractional divisors configured, + * their clock dividers will run in precise deterministic lockstep from this + * point. + * + * With their execution clocks synchronised in this way, it is then safe to + * e.g. have multiple state machines performing a 'wait irq' on the same flag, + * and all clear it on the same cycle. + * + * Also note that this function can be called whilst state machines are + * running (e.g. if you have just changed the clock divisors of some state + * machines and wish to resynchronise them), and that disabling a state + * machine does not halt its clock divider: that is, if multiple state + * machines have their clocks synchronised, you can safely disable and + * reenable one of the state machines without losing synchronisation. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS; } /*! \brief Enable multiple PIO state machines synchronizing their clock dividers * \ingroup hardware_pio * + * This is equivalent to calling both pio_set_sm_mask_enabled() and + * pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines + * specified by 'mask' are started simultaneously and, assuming they have the + * same clock divisors, their divided clocks will stay precisely synchronised. + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS); } +/*! \brief PIO interrupt source numbers for pio related IRQs + * \ingroup hardware_pio + */ +enum pio_interrupt_source { + pis_interrupt0 = PIO_INTR_SM0_LSB, + pis_interrupt1 = PIO_INTR_SM1_LSB, + pis_interrupt2 = PIO_INTR_SM2_LSB, + pis_interrupt3 = PIO_INTR_SM3_LSB, + pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB, + pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB, + pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB, + pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB, + pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB, + pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB, + pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB, + pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB, +}; + +/*! \brief Enable/Disable a single source on a PIO's IRQ 0 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable IRQ 0 for the source, false to disable. + */ +static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source >= 12); + if (enabled) + hw_set_bits(&pio->inte0, 1u << source); + else + hw_clear_bits(&pio->inte0, 1u << source); +} + +/*! \brief Enable/Disable a single source on a PIO's IRQ 1 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable IRQ 0 for the source, false to disable. + */ +static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source >= 12); + if (enabled) + hw_set_bits(&pio->inte1, 1u << source); + else + hw_clear_bits(&pio->inte1, 1u << source); +} + +/*! \brief Enable/Disable multiple sources on a PIO's IRQ 0 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0 + */ +static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + if (enabled) { + hw_set_bits(&pio->inte0, source_mask); + } else { + hw_clear_bits(&pio->inte0, source_mask); + } +} + +/*! \brief Enable/Disable multiple sources on a PIO's IRQ 1 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1 + */ +static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + if (enabled) { + hw_set_bits(&pio->inte1, source_mask); + } else { + hw_clear_bits(&pio->inte1, source_mask); + } +} + +/*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param irq_index the IRQ index; either 0 or 1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable the source on the specified IRQ, false to disable. + */ +static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) { + invalid_params_if(PIO, irq_index > 1); + if (irq_index) { + pio_set_irq1_source_enabled(pio, source, enabled); + } else { + pio_set_irq0_source_enabled(pio, source, enabled); + } +} + +/*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param irq_index the IRQ index; either 0 or 1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ + */ +static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) { + invalid_params_if(PIO, irq_index > 1); + if (irq_index) { + pio_set_irq0_source_mask_enabled(pio, source_mask, enabled); + } else { + pio_set_irq1_source_mask_enabled(pio, source_mask, enabled); + } +} + +/*! \brief Determine if a particular PIO interrupt is set + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio_interrupt_num the PIO interrupt number 0-7 + * \return true if corresponding PIO interrupt is currently set + */ +static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) { + check_pio_param(pio); + invalid_params_if(PIO, pio_interrupt_num >= 8); + return pio->irq & (1u << pio_interrupt_num); +} + +/*! \brief Clear a particular PIO interrupt + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio_interrupt_num the PIO interrupt number 0-7 + */ +static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) { + check_pio_param(pio); + invalid_params_if(PIO, pio_interrupt_num >= 8); + hw_set_bits(&pio->irq, (1u << pio_interrupt_num)); +} + /*! \brief Return the current program counter for a state machine * \ingroup hardware_pio * @@ -591,6 +829,7 @@ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { * \return the program counter */ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (uint8_t) pio->sm[sm].addr; } @@ -600,7 +839,7 @@ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { * * This instruction is executed instead of the next instruction in the normal control flow on the state machine. * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -608,6 +847,7 @@ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { * \param instr the encoded PIO instruction */ inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { + check_pio_param(pio); check_sm_param(sm); pio->sm[sm].instr = instr; } @@ -620,6 +860,7 @@ inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { * \return true if the executed instruction is still running (stalled) */ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS); } @@ -629,7 +870,7 @@ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { * * This instruction is executed instead of the next instruction in the normal control flow on the state machine. * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -637,6 +878,8 @@ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { * \param instr the encoded PIO instruction */ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { + check_pio_param(pio); + check_sm_param(sm); pio_sm_exec(pio, sm, instr); while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents(); } @@ -651,7 +894,10 @@ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { * if the instruction does not itself update the program_counter */ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) { + check_pio_param(pio); check_sm_param(sm); + valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); pio->sm[sm].execctrl = (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | @@ -669,9 +915,10 @@ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap * \param out_count 0-32 Number of pins to set. */ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) { + check_pio_param(pio); check_sm_param(sm); - assert(out_base < 32); - assert(out_count <= 32); + valid_params_if(PIO, out_base < 32); + valid_params_if(PIO, out_count <= 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); @@ -689,9 +936,10 @@ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out * \param set_count 0-5 Number of pins to set. */ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) { + check_pio_param(pio); check_sm_param(sm); - assert(set_base < 32); - assert(set_count <= 5); + valid_params_if(PIO, set_base < 32); + valid_params_if(PIO, set_count <= 5); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); @@ -704,11 +952,12 @@ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param in_base 0-31 First pin to set as input + * \param in_base 0-31 First pin to use as input */ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { + check_pio_param(pio); check_sm_param(sm); - assert(in_base < 32); + valid_params_if(PIO, in_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); } @@ -720,11 +969,12 @@ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param sideset_base base pin for 'side set' + * \param sideset_base 0-31 base pin for 'side set' */ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) { + check_pio_param(pio); check_sm_param(sm); - assert(sideset_base < 32); + valid_params_if(PIO, sideset_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } @@ -732,13 +982,19 @@ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) /*! \brief Write a word of data to a state machine's TX FIFO * \ingroup hardware_pio * - * If the FIFO is full, the most recent value will be overwritten + * This is a raw FIFO access that does not check for fullness. If the FIFO is + * full, the FIFO contents and state are not affected by the write attempt. + * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate + * that the system attempted to write to a full FIFO. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param data the 32 bit data value + * + * \sa pio_sm_put_blocking() */ static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { + check_pio_param(pio); check_sm_param(sm); pio->txf[sm] = data; } @@ -746,12 +1002,20 @@ static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { /*! \brief Read a word of data from a state machine's RX FIFO * \ingroup hardware_pio * - * If the FIFO is empty, the return value is zero. + * This is a raw FIFO access that does not check for emptiness. If the FIFO is + * empty, the hardware ignores the attempt to read from the FIFO (the FIFO + * remains in an empty state following the read) and the sticky RXUNDER flag + * for this FIFO is set in FDEBUG to indicate that the system tried to read + * from this FIFO when empty. The data returned by this function is undefined + * when the FIFO is empty. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) + * + * \sa pio_sm_get_blocking() */ static inline uint32_t pio_sm_get(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return pio->rxf[sm]; } @@ -764,6 +1028,7 @@ static inline uint32_t pio_sm_get(PIO pio, uint sm) { * \return true if the RX FIFO is full */ static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0; } @@ -776,6 +1041,7 @@ static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { * \return true if the RX FIFO is empty */ static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0; } @@ -788,8 +1054,9 @@ static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { * \return the number of elements in the RX FIFO */ static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); - int bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); + uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB; return (pio->flevel >> bitoffs) & mask; } @@ -802,6 +1069,7 @@ static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { * \return true if the TX FIFO is full */ static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0; } @@ -814,6 +1082,7 @@ static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { * \return true if the TX FIFO is empty */ static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0; } @@ -826,6 +1095,7 @@ static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { * \return the number of elements in the TX FIFO */ static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB); const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB; @@ -840,6 +1110,7 @@ static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { * \param data the 32 bit data value */ static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { + check_pio_param(pio); check_sm_param(sm); while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents(); pio_sm_put(pio, sm, data); @@ -852,6 +1123,7 @@ static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { * \param sm State machine index (0..3) */ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents(); return pio_sm_get(pio, sm); @@ -860,45 +1132,51 @@ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { /*! \brief Empty out a state machine's TX FIFO * \ingroup hardware_pio * - * This method executes `pull` instructions on the state machine until the TX FIFO is empty + * This method executes `pull` instructions on the state machine until the TX + * FIFO is empty. This disturbs the contents of the OSR, so see also + * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's + * internal state undisturbed. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) + * + * \sa pio_sm_clear_fifos() */ void pio_sm_drain_tx_fifo(PIO pio, uint sm); -/*! \brief set the current clock divider for a state machine +/*! \brief set the current clock divider for a state machine using a 16:8 fraction * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param div the floating point clock divider + * \param div_int the integer part of the clock divider + * \param div_frac the fractional part of the clock divider in 1/256s */ -static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { +static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { + check_pio_param(pio); check_sm_param(sm); - uint16_t div_int = (uint16_t) div; - uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); pio->sm[sm].clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | + (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); } -/*! \brief set the current clock divider for a state machine using a 16:8 fraction +/*! \brief set the current clock divider for a state machine * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param div_int the integer part of the clock divider - * \param div_frac the fractional part of the clock divider in 1/256s + * \param div the floating point clock divider */ -static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { +static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { + check_pio_param(pio); check_sm_param(sm); - pio->sm[sm].clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + uint16_t div_int; + uint8_t div_frac; + pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); + pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac); } -/*! \brief Clear a state machine's TX and RX FIFOFs +/*! \brief Clear a state machine's TX and RX FIFOs * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -906,6 +1184,7 @@ static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int */ static inline void pio_sm_clear_fifos(PIO pio, uint sm) { // changing the FIFO join state clears the fifo + check_pio_param(pio); check_sm_param(sm); hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); @@ -1014,6 +1293,17 @@ void pio_sm_unclaim(PIO pio, uint sm); */ int pio_claim_unused_sm(PIO pio, bool required); +/*! \brief Determine if a PIO state machine is claimed + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if claimed, false otherwise + * \see pio_sm_claim + * \see pio_claim_sm_mask + */ +bool pio_sm_is_claimed(PIO pio, uint sm); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h index 757411d5e2d..366213580bf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h @@ -9,7 +9,18 @@ #include "pico.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=hardware_pio +/** \brief PIO instruction encoding + * \defgroup pio_instructions pio_instructions + * \ingroup hardware_pio + * + * Functions for generating PIO instruction encodings programmatically. In debug builds + *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function + * parameters. + * + * For fuller descriptions of the instructions in question see the "RP2040 Datasheet" + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions #ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS #define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0 #endif @@ -44,6 +55,12 @@ enum pio_instr_bits { #define _PIO_INVALID_MOV_DEST 0u #endif +/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions + * \ingroup pio_instructions + * + * \note Not all values are suitable for all functions. Validity is only checked in debug mode when + * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1 + */ enum pio_src_dest { pio_pins = 0u, pio_x = 1u, @@ -58,11 +75,11 @@ enum pio_src_dest { pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, }; -inline static uint _pio_major_instr_bits(uint instr) { +static inline uint _pio_major_instr_bits(uint instr) { return instr & 0xe000u; } -inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { +static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7); #if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS) uint32_t major = _pio_major_instr_bits(instr_bits); @@ -75,99 +92,388 @@ inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, ui return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); } -inline static uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { +static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { return _pio_encode_instr_and_args(instr_bits, dest & 7u, value); } -inline static uint pio_encode_delay(uint cycles) { +/*! \brief Encode just the delay slot bits of an instruction + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay + * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt + * as they share the same bits within the instruction encoding. + * + * \param cycles the number of cycles 0-31 (or less if side set is being used) + * \return the delay slot bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_delay(uint cycles) { + // note that the maximum cycles will be smaller if sideset_bit_count > 0 valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f); return cycles << 8u; } -inline static uint pio_encode_sideset(uint sideset_bit_count, uint value) { +/*! \brief Encode just the side set bits of an instruction (in non optional side set mode) + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. + * + * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm + * \param value the value to sideset on the pins + * \return the side set bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) { valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5); - valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); + valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return value << (13u - sideset_bit_count); } -inline static uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 2 && sideset_bit_count <= 5); - valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); +/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode) + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. + * + * \param sideset_bit_count number of side set bits as would be specified via `.sideset opt` in pioasm + * \param value the value to sideset on the pins + * \return the side set bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4); + valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return 0x1000u | value << (12u - sideset_bit_count); } -inline static uint pio_encode_jmp(uint addr) { +/*! \brief Encode an unconditional JMP instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr); } -inline static uint _pio_encode_irq(bool relative, uint irq) { +/*! \brief Encode a conditional JMP if scratch X zero instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !X ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_x(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr); +} + +/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP X-- ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_x_dec(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr); +} + +/*! \brief Encode a conditional JMP if scratch Y zero instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !Y ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_y(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr); +} + +/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP Y-- ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_y_dec(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr); +} + +/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP X!=Y ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_x_ne_y(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr); +} + +/*! \brief Encode a conditional JMP if input pin high instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP PIN ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_pin(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr); +} + +/*! \brief Encode a conditional JMP if output shift register not empty instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !OSRE ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_osre(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr); +} + +static inline uint _pio_encode_irq(bool relative, uint irq) { valid_params_if(PIO_INSTRUCTIONS, irq <= 7); return (relative ? 0x10u : 0x0u) | irq; } -inline static uint pio_encode_wait_gpio(bool polarity, uint pin) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), pin); +/*! \brief Encode a WAIT for GPIO pin instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT GPIO ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param gpio The real GPIO number 0-31 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { + return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio); } -inline static uint pio_encode_wait_pin(bool polarity, uint pin) { +/*! \brief Encode a WAIT for pin instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT PIN ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param pin The pin number 0-31 relative to the executing SM's input pin mapping + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_pin(bool polarity, uint pin) { return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin); } -inline static uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { +/*! \brief Encode a WAIT for IRQ instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT IRQ ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param relative true for a `WAIT IRQ REL`, false for regular `WAIT IRQ ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { valid_params_if(PIO_INSTRUCTIONS, irq <= 7); return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_in(enum pio_src_dest src, uint value) { +/*! \brief Encode an IN instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IN , ` + * + * \param src The source to take data from + * \param count The number of bits 1-32 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_in(enum pio_src_dest src, uint count) { valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, value); + return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count); } -inline static uint pio_encode_out(enum pio_src_dest dest, uint value) { +/*! \brief Encode an OUT instruction + * \ingroup pio_instructions + * + * This is the equivalent of `OUT , ` + * + * \param dest The destination to write data to + * \param count The number of bits 1-32 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_out(enum pio_src_dest dest, uint count) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, value); + return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count); } -inline static uint pio_encode_push(bool if_full, bool block) { +/*! \brief Encode a PUSH instruction + * \ingroup pio_instructions + * + * This is the equivalent of `PUSH , ` + * + * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...` + * \param block true for `PUSH ... BLOCK`, false for `PUSH ...` + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_push(bool if_full, bool block) { return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); } -inline static uint pio_encode_pull(bool if_empty, bool block) { +/*! \brief Encode a PULL instruction + * \ingroup pio_instructions + * + * This is the equivalent of `PULL , ` + * + * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...` + * \param block true for `PULL ... BLOCK`, false for `PULL ...` + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_pull(bool if_empty, bool block) { return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); } -inline static uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ` + * + * \param dest The destination to write data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u); } -inline static uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction with bit invert + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ~` + * + * \param dest The destination to write inverted data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u)); } -inline static uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction with bit reverse + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ::` + * + * \param dest The destination to write bit reversed data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u)); } -inline static uint pio_encode_irq_set(bool relative, uint irq) { +/*! \brief Encode a IRQ SET instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ SET ` + * + * \param relative true for a `IRQ SET REL`, false for regular `IRQ SET ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_set(bool relative, uint irq) { return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_irq_clear(bool relative, uint irq) { +/*! \brief Encode a IRQ WAIT instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ WAIT ` + * + * \param relative true for a `IRQ WAIT REL`, false for regular `IRQ WAIT ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_wait(bool relative, uint irq) { + return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq)); +} + +/*! \brief Encode a IRQ CLEAR instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ CLEAR ` + * + * \param relative true for a `IRQ CLEAR REL`, false for regular `IRQ CLEAR ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_clear(bool relative, uint irq) { return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_set(enum pio_src_dest dest, uint value) { +/*! \brief Encode a SET instruction + * \ingroup pio_instructions + * + * This is the equivalent of `SET , ` + * + * \param dest The destination to apply the value to + * \param value The value 0-31 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_set(enum pio_src_dest dest, uint value) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST)); return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value); } -inline static uint pio_encode_nop() { +/*! \brief Encode a NOP instruction + * \ingroup pio_instructions + * + * This is the equivalent of `NOP` which is itself encoded as `MOV y, y` + * + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_nop(void) { return pio_encode_mov(pio_y, pio_y); } @@ -175,4 +481,4 @@ inline static uint pio_encode_nop() { } #endif -#endif \ No newline at end of file +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c index 8221225196b..07441105d48 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/pio.c @@ -24,7 +24,7 @@ void pio_sm_claim(PIO pio, uint sm) { check_sm_param(sm); uint which = pio_get_index(pio); if (which) { - hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM %d already claimed"); + hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM (%d - 4) already claimed"); } else { hw_claim_or_assert(&claimed, sm, "PIO 0 SM %d already claimed"); } @@ -35,6 +35,7 @@ void pio_claim_sm_mask(PIO pio, uint sm_mask) { if (sm_mask & 1u) pio_sm_claim(pio, i); } } + void pio_sm_unclaim(PIO pio, uint sm) { check_sm_param(sm); uint which = pio_get_index(pio); @@ -42,25 +43,25 @@ void pio_sm_unclaim(PIO pio, uint sm) { } int pio_claim_unused_sm(PIO pio, bool required) { + // PIO index is 0 or 1. uint which = pio_get_index(pio); uint base = which * NUM_PIO_STATE_MACHINES; int index = hw_claim_unused_from_range((uint8_t*)&claimed, required, base, base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available"); - return index >= base ? index - base : -1; + return index >= (int)base ? index - (int)base : -1; } -void pio_load_program(PIO pio, const uint16_t *prog, uint8_t prog_len, uint8_t load_offset) { - // instructions are only 16 bits, but instruction memory locations are spaced 32 bits apart - // Adjust the addresses of any jump instructions to respect load offset - assert(load_offset + prog_len <= PIO_INSTRUCTION_COUNT); - +bool pio_sm_is_claimed(PIO pio, uint sm) { + check_sm_param(sm); + uint which = pio_get_index(pio); + return hw_is_claimed(&claimed, which * NUM_PIO_STATE_MACHINES + sm); } static_assert(PIO_INSTRUCTION_COUNT <= 32, ""); static uint32_t _used_instruction_space[2]; static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) { - assert(program->length < PIO_INSTRUCTION_COUNT); + assert(program->length <= PIO_INSTRUCTION_COUNT); uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; uint32_t program_mask = (1u << program->length) - 1; if (program->origin >= 0) { @@ -85,9 +86,9 @@ bool pio_can_add_program(PIO pio, const pio_program_t *program) { } static bool _pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - assert(offset < PIO_INSTRUCTION_COUNT); - assert(offset + program->length <= PIO_INSTRUCTION_COUNT); - if (program->origin >= 0 && program->origin != offset) return false; + valid_params_if(PIO, offset < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, offset + program->length <= PIO_INSTRUCTION_COUNT); + if (program->origin >= 0 && (uint)program->origin != offset) return false; uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; uint32_t program_mask = (1u << program->length) - 1; return !(used_mask & (program_mask << offset)); @@ -119,9 +120,9 @@ uint pio_add_program(PIO pio, const pio_program_t *program) { if (offset < 0) { panic("No program space"); } - _pio_add_program_at_offset(pio, program, offset); + _pio_add_program_at_offset(pio, program, (uint)offset); hw_claim_unlock(save); - return offset; + return (uint)offset; } void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { @@ -153,6 +154,8 @@ void pio_clear_instruction_memory(PIO pio) { // which is not currently running a program. This is intended for one-time // setup of initial pin states. void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) { + check_pio_param(pio); + check_sm_param(sm); uint32_t pinctrl_saved = pio->sm[sm].pinctrl; uint remaining = 32; uint base = 0; @@ -170,9 +173,11 @@ void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) { } void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_mask) { + check_pio_param(pio); + check_sm_param(sm); uint32_t pinctrl_saved = pio->sm[sm].pinctrl; while (pin_mask) { - uint base = __builtin_ctz(pin_mask); + uint base = (uint)__builtin_ctz(pin_mask); pio->sm[sm].pinctrl = (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (base << PIO_SM0_PINCTRL_SET_BASE_LSB); @@ -183,9 +188,11 @@ void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_ } void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t pin_mask) { + check_pio_param(pio); + check_sm_param(sm); uint32_t pinctrl_saved = pio->sm[sm].pinctrl; while (pin_mask) { - uint base = __builtin_ctz(pin_mask); + uint base = (uint)__builtin_ctz(pin_mask); pio->sm[sm].pinctrl = (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (base << PIO_SM0_PINCTRL_SET_BASE_LSB); @@ -196,7 +203,9 @@ void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t p } void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) { - assert(pin < 32u); + check_pio_param(pio); + check_sm_param(sm); + valid_params_if(PIO, pin < 32u); uint32_t pinctrl_saved = pio->sm[sm].pinctrl; uint pindir_val = is_out ? 0x1f : 0; while (count > 5) { @@ -211,6 +220,7 @@ void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool } void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) { + valid_params_if(PIO, initial_pc < PIO_INSTRUCTION_COUNT); // Halt the machine, set some sensible defaults pio_sm_set_enabled(pio, sm, false); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h index 023e340339e..ee0c3aef03d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h @@ -39,7 +39,7 @@ typedef pll_hw_t *PLL; * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2 * \param post_div2 Post Divider 2 - range 1-7 */ -void pll_init(PLL pll, uint32_t ref_div, uint32_t vco_freq, uint32_t post_div1, uint8_t post_div2); +void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2); /*! \brief Release/uninitialise specified PLL. * \ingroup hardware_pll diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c index a55ed5ca88f..6cc6184f3b1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/pll.c @@ -7,15 +7,11 @@ // For MHZ definitions etc #include "hardware/clocks.h" #include "hardware/pll.h" +#include "hardware/resets.h" /// \tag::pll_init_calculations[] -void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, uint8_t post_div2) { - // Turn off PLL in case it is already running - pll->pwr = 0xffffffff; - pll->fbdiv_int = 0; - +void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) { uint32_t ref_mhz = XOSC_MHZ / refdiv; - pll->cs = refdiv; // What are we multiplying the reference clock by to get the vco freq // (The regs are called div, because you divide the vco output and compare it to the refclk) @@ -34,11 +30,28 @@ void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, u // than postdiv2 assert(post_div2 <= post_div1); -/// \tag::pll_init_finish[] // Check that reference frequency is no greater than vco / 16 assert(ref_mhz <= (vco_freq / 16)); - // Put calculated value into feedback divider + // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 + uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | + (post_div2 << PLL_PRIM_POSTDIV2_LSB); + +/// \tag::pll_init_finish[] + if ((pll->cs & PLL_CS_LOCK_BITS) && + (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) && + (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) && + (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) { + // do not disrupt PLL that is already correctly configured and operating + return; + } + + uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS; + reset_block(pll_reset); + unreset_block_wait(pll_reset); + + // Load VCO-related dividers before starting VCO + pll->cs = refdiv; pll->fbdiv_int = fbdiv; // Turn on PLL @@ -50,9 +63,7 @@ void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, u // Wait for PLL to lock while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents(); - // Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 - uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | - (post_div2 << PLL_PRIM_POSTDIV2_LSB); + // Set up post dividers pll->prim = pdiv; // Turn on post divider @@ -63,4 +74,4 @@ void pll_init(PLL pll, uint32_t refdiv, uint32_t vco_freq, uint32_t post_div1, u void pll_deinit(PLL pll) { // todo: Make sure there are no sources running from this pll? pll->pwr = PLL_PWR_BITS; -} \ No newline at end of file +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h index 4b572f7711d..634375e7644 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h @@ -9,12 +9,13 @@ #include "pico.h" #include "hardware/structs/pwm.h" +#include "hardware/regs/dreq.h" #ifdef __cplusplus extern "C" { #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hadrware_pwm +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm #ifndef PARAM_ASSERTIONS_ENABLED_PWM #define PARAM_ASSERTIONS_ENABLED_PWM 0 #endif @@ -26,7 +27,7 @@ extern "C" { * * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable - * PWM outputs. All 30 GPIOs can be driven by the PWM block + * PWM outputs. All 30 GPIOs can be driven by the PWM block. * * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of @@ -47,10 +48,10 @@ extern "C" { */ enum pwm_clkdiv_mode { - PWM_DIV_FREE_RUNNING, ///< Free-running counting at rate dictated by fractional divider - PWM_DIV_B_HIGH, ///< Fractional divider is gated by the PWM B pin - PWM_DIV_B_RISING, ///< Fractional divider advances with each rising edge of the PWM B pin - PWM_DIV_B_FALLING ///< Fractional divider advances with each falling edge of the PWM B pin + PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider + PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin + PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin + PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin }; enum pwm_chan @@ -65,6 +66,10 @@ typedef struct { uint32_t top; } pwm_config; +static inline void check_slice_num_param(__unused uint slice_num) { + valid_params_if(PWM, slice_num < NUM_PWM_SLICES); +} + /** \brief Determine the PWM slice that is attached to the specified GPIO * \ingroup hardware_pwm * @@ -98,7 +103,7 @@ static inline uint pwm_gpio_to_channel(uint gpio) { */ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) { c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS) - | (!!phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB); + | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB); } /** \brief Set clock divider in a PWM configuration @@ -112,21 +117,21 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { - c->div = (uint32_t)(div * (float)(1u << PWM_CH1_DIV_INT_LSB)); + c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB)); } /** \brief Set PWM clock divider in a PWM configuration * \ingroup hardware_pwm * * \param c PWM configuration struct to modify - * \param div integer value to reduce counting rate by. Must be greater than or equal to 1. + * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1. * * If the divide mode is free-running, the PWM counter runs at clk_sys / div. * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { - c->div = div << PWM_CH1_DIV_INT_LSB; + c->div = div << PWM_CH0_DIV_INT_LSB; } /** \brief Set PWM counting mode in a PWM configuration @@ -140,9 +145,12 @@ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { * high level, rising edge or falling edge of the B pin input. */ static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) { - valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); + valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + mode == PWM_DIV_B_RISING || + mode == PWM_DIV_B_HIGH || + mode == PWM_DIV_B_FALLING); c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS) - | (mode << PWM_CH0_CSR_DIVMODE_LSB); + | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB); } /** \brief Set output polarity in a PWM configuration @@ -154,7 +162,7 @@ static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mod */ static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) { c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS)) - | ((!!a << PWM_CH0_CSR_A_INV_LSB) | (!!b << PWM_CH0_CSR_B_INV_LSB)); + | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB)); } /** \brief Set PWM counter wrap value in a PWM configuration @@ -181,25 +189,25 @@ static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled() */ static inline void pwm_init(uint slice_num, pwm_config *c, bool start) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].csr = 0; pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET; pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET; pwm_hw->slice[slice_num].top = c->top; pwm_hw->slice[slice_num].div = c->div; - pwm_hw->slice[slice_num].csr = c->csr | (!!start << PWM_CH0_CSR_EN_LSB); + pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB); } /** \brief Get a set of default values for PWM configuration * \ingroup hardware_pwm * - * PWM config is free running at system clock speed, no phase correction, wrapping at 0xffff, + * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff, * with standard polarities for channels A and B. * * \return Set of default values. */ -static inline pwm_config pwm_get_default_config() { +static inline pwm_config pwm_get_default_config(void) { pwm_config c = {0, 0, 0}; pwm_config_set_phase_correct(&c, false); pwm_config_set_clkdiv_int(&c, 1); @@ -212,30 +220,43 @@ static inline pwm_config pwm_get_default_config() { /** \brief Set the current PWM counter wrap value * \ingroup hardware_pwm * - * Set the highest value the counter will reach before returning to 0. Also known as TOP. + * Set the highest value the counter will reach before returning to 0. Also + * known as TOP. + * + * The counter wrap value is double-buffered in hardware. This means that, + * when the PWM is running, a write to the counter wrap value does not take + * effect until after the next time the PWM slice wraps (or, in phase-correct + * mode, the next time the slice reaches 0). If the PWM is not running, the + * write is latched in immediately. * * \param slice_num PWM slice number * \param wrap Value to set wrap to */ static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].top = wrap; } /** \brief Set the current PWM counter compare value for one channel * \ingroup hardware_pwm * - * Set the value of the PWM counter compare value, for either channel A or channel B + * Set the value of the PWM counter compare value, for either channel A or channel B. + * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. * * \param slice_num PWM slice number * \param chan Which channel to update. 0 for A, 1 for B. * \param level new level for the selected output */ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_write_masked( &pwm_hw->slice[slice_num].cc, - level << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), + ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS ); } @@ -243,26 +264,38 @@ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) /** \brief Set PWM counter compare values * \ingroup hardware_pwm * - * Set the value of the PWM counter compare values, A and B + * Set the value of the PWM counter compare values, A and B. + * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. * * \param slice_num PWM slice number * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted */ static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - pwm_hw->slice[slice_num].cc = (level_b << PWM_CH0_CC_B_LSB) | (level_a << PWM_CH0_CC_A_LSB); + check_slice_num_param(slice_num); + pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB); } /** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO. * \ingroup hardware_pwm * * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding - * counter-compare field. + * counter compare field. * * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs * mapping to the same slice and channel (if GPIOs have a difference of 16). * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. + * * \param gpio GPIO to set level of * \param level PWM level for this GPIO */ @@ -277,11 +310,11 @@ static inline void pwm_set_gpio_level(uint gpio, uint16_t level) { * Get current value of PWM counter * * \param slice_num PWM slice number - * \return Current value of PWM counter + * \return Current value of the PWM counter */ -static inline int16_t pwm_get_counter(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - return (pwm_hw->slice[slice_num].ctr); +static inline uint16_t pwm_get_counter(uint slice_num) { + check_slice_num_param(slice_num); + return (uint16_t)(pwm_hw->slice[slice_num].ctr); } /** \brief Set PWM counter @@ -294,7 +327,7 @@ static inline int16_t pwm_get_counter(uint slice_num) { * */ static inline void pwm_set_counter(uint slice_num, uint16_t c) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].ctr = c; } @@ -308,7 +341,7 @@ static inline void pwm_set_counter(uint slice_num, uint16_t c) { * \param slice_num PWM slice number */ static inline void pwm_advance_count(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) { tight_loop_contents(); @@ -325,7 +358,7 @@ static inline void pwm_advance_count(uint slice_num) { * \param slice_num PWM slice number */ static inline void pwm_retard_count(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) { tight_loop_contents(); @@ -335,28 +368,28 @@ static inline void pwm_retard_count(uint slice_num) { /** \brief Set PWM clock divider using an 8:4 fractional value * \ingroup hardware_pwm * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. * * \param slice_num PWM slice number * \param integer 8 bit integer part of the clock divider * \param fract 4 bit fractional part of the clock divider */ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - valid_params_if(PWM, fract >= 0 && slice_num <= 16); - pwm_hw->slice[slice_num].div = (integer << PWM_CH0_DIV_INT_LSB) | (fract << PWM_CH0_DIV_FRAC_LSB); + check_slice_num_param(slice_num); + valid_params_if(PWM, fract < 16); + pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); } /** \brief Set PWM clock divider * \ingroup hardware_pwm * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. * * \param slice_num PWM slice number * \param divider Floating point clock divider, 1.f <= value < 256.f */ static inline void pwm_set_clkdiv(uint slice_num, float divider) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); valid_params_if(PWM, divider >= 1.f && divider < 256.f); uint8_t i = (uint8_t)divider; uint8_t f = (uint8_t)((divider - i) * (0x01 << 4)); @@ -371,8 +404,8 @@ static inline void pwm_set_clkdiv(uint slice_num, float divider) { * \param b true to invert output B */ static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, !!a << PWM_CH0_CSR_A_INV_LSB | !!b << PWM_CH0_CSR_B_INV_LSB, + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB, PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS); } @@ -384,9 +417,12 @@ static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { * \param mode Required divider mode */ static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); - hw_write_masked(&pwm_hw->slice[slice_num].csr, mode << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); + check_slice_num_param(slice_num); + valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + mode == PWM_DIV_B_RISING || + mode == PWM_DIV_B_HIGH || + mode == PWM_DIV_B_FALLING); + hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); } /** \brief Set PWM phase correct on/off @@ -399,19 +435,39 @@ static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. */ static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); } /** \brief Enable/Disable PWM * \ingroup hardware_pwm * + * When a PWM is disabled, it halts its counter, and the output pins are left + * high or low depending on exactly when the counter is halted. When + * re-enabled the PWM resumes immediately from where it left off. + * + * If the PWM's output pins need to be low when halted: + * + * - The counter compare can be set to zero whilst the PWM is enabled, and + * then the PWM disabled once both pins are seen to be low + * + * - The GPIO output overrides can be used to force the actual pins low + * + * - The PWM can be run for one cycle (i.e. enabled then immediately disabled) + * with a TOP of 0, count of 0 and counter compare of 0, to force the pins + * low when the PWM has already been halted. The same method can be used + * with a counter compare value of 1 to force a pin high. + * + * Note that, when disabled, the PWM can still be advanced one count at a time + * by pulsing the PH_ADV bit in its CSR. The output pins transition as though + * the PWM were enabled. + * * \param slice_num PWM slice number - * \param enabled true to enable the specified PWM, false to disable + * \param enabled true to enable the specified PWM, false to disable. */ static inline void pwm_set_enabled(uint slice_num, bool enabled) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, !!enabled << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); } /** \brief Enable/Disable multiple PWM slices simultaneously @@ -426,13 +482,13 @@ static inline void pwm_set_mask_enabled(uint32_t mask) { /*! \brief Enable PWM instance interrupt * \ingroup hardware_pwm * - * Used to enable a single PWM instance interrupt + * Used to enable a single PWM instance interrupt. * * \param slice_num PWM block to enable/disable * \param enabled true to enable, false to disable */ static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); if (enabled) { hw_set_bits(&pwm_hw->inte, 1u << slice_num); } else { @@ -457,7 +513,7 @@ static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) { } } -/*! \brief Clear single PWM channel interrupt +/*! \brief Clear a single PWM channel interrupt * \ingroup hardware_pwm * * \param slice_num PWM slice number @@ -471,7 +527,7 @@ static inline void pwm_clear_irq(uint slice_num) { * * \return Bitmask of all PWM interrupts currently set */ -static inline int32_t pwm_get_irq_status_mask() { +static inline uint32_t pwm_get_irq_status_mask(void) { return pwm_hw->ints; } @@ -484,6 +540,18 @@ static inline void pwm_force_irq(uint slice_num) { pwm_hw->intf = 1u << slice_num; } +/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline uint pwm_get_dreq(uint slice_num) { + static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, ""); + static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, ""); + check_slice_num_param(slice_num); + return DREQ_PWM_WRAP0 + slice_num; +} + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt index 0b314573e60..e0712e709a3 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/CMakeLists.txt @@ -1,2 +1 @@ -add_library(hardware_resets INTERFACE) -target_include_directories(hardware_resets INTERFACE include) \ No newline at end of file +pico_simple_hardware_headers_only_target(resets) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h index fab604bdaeb..a3f7014b7d5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h @@ -56,6 +56,10 @@ * \include hello_reset.c */ +#ifdef __cplusplus +extern "C" { +#endif + /// \tag::reset_funcs[] /*! \brief Reset the specified HW blocks @@ -88,4 +92,8 @@ static inline void unreset_block_wait(uint32_t bits) { } /// \end::reset_funcs[] +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h index dcdcd2285f6..8757e36e0b6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h @@ -28,13 +28,21 @@ * \include hello_rtc.c */ +#ifdef __cplusplus +extern "C" { +#endif +/*! Callback function type for RTC alarms + * \ingroup hardware_rtc + * + * \sa rtc_set_alarm() + */ typedef void (*rtc_callback_t)(void); /*! \brief Initialise the RTC system * \ingroup hardware_rtc */ -void _rtc_init(void); +void rtc_init(void); /*! \brief Set the RTC to the specified time * \ingroup hardware_rtc @@ -66,9 +74,18 @@ bool rtc_running(void); */ void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback); +/*! \brief Enable the RTC alarm (if inactive) + * \ingroup hardware_rtc + */ +void rtc_enable_alarm(void); + /*! \brief Disable the RTC alarm (if active) * \ingroup hardware_rtc */ void rtc_disable_alarm(void); +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c index ebd6783ba00..5429acd4b77 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c @@ -19,7 +19,7 @@ bool rtc_running(void) { return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); } -void _rtc_init(void) { +void rtc_init(void) { // Get clk_rtc freq and make sure it is running uint rtc_freq = clock_get_hz(clk_rtc); assert(rtc_freq != 0); @@ -65,13 +65,13 @@ bool rtc_set_datetime(datetime_t *t) { } // Write to setup registers - rtc_hw->setup_0 = (t->year << RTC_SETUP_0_YEAR_LSB ) | - (t->month << RTC_SETUP_0_MONTH_LSB) | - (t->day << RTC_SETUP_0_DAY_LSB); - rtc_hw->setup_1 = (t->dotw << RTC_SETUP_1_DOTW_LSB) | - (t->hour << RTC_SETUP_1_HOUR_LSB) | - (t->min << RTC_SETUP_1_MIN_LSB) | - (t->sec << RTC_SETUP_1_SEC_LSB); + rtc_hw->setup_0 = (((uint)t->year) << RTC_SETUP_0_YEAR_LSB ) | + (((uint)t->month) << RTC_SETUP_0_MONTH_LSB) | + (((uint)t->day) << RTC_SETUP_0_DAY_LSB); + rtc_hw->setup_1 = (((uint)t->dotw) << RTC_SETUP_1_DOTW_LSB) | + (((uint)t->hour) << RTC_SETUP_1_HOUR_LSB) | + (((uint)t->min) << RTC_SETUP_1_MIN_LSB) | + (((uint)t->sec) << RTC_SETUP_1_SEC_LSB); // Load setup values into rtc clock domain rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; @@ -92,18 +92,21 @@ bool rtc_get_datetime(datetime_t *t) { } // Note: RTC_0 should be read before RTC_1 - t->dotw = (rtc_hw->rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB; - t->hour = (rtc_hw->rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB; - t->min = (rtc_hw->rtc_0 & RTC_RTC_0_MIN_BITS ) >> RTC_RTC_0_MIN_LSB; - t->sec = (rtc_hw->rtc_0 & RTC_RTC_0_SEC_BITS ) >> RTC_RTC_0_SEC_LSB; - t->year = (rtc_hw->rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB; - t->month = (rtc_hw->rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB; - t->day = (rtc_hw->rtc_1 & RTC_RTC_1_DAY_BITS ) >> RTC_RTC_1_DAY_LSB; + uint32_t rtc_0 = rtc_hw->rtc_0; + uint32_t rtc_1 = rtc_hw->rtc_1; + + t->dotw = (rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB; + t->hour = (rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB; + t->min = (rtc_0 & RTC_RTC_0_MIN_BITS ) >> RTC_RTC_0_MIN_LSB; + t->sec = (rtc_0 & RTC_RTC_0_SEC_BITS ) >> RTC_RTC_0_SEC_LSB; + t->year = (rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB; + t->month = (rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB; + t->day = (rtc_1 & RTC_RTC_1_DAY_BITS ) >> RTC_RTC_1_DAY_LSB; return true; } -static void rtc_enable_alarm(void) { +void rtc_enable_alarm(void) { // Set matching and wait for it to be enabled hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)) { @@ -131,13 +134,13 @@ static void rtc_irq_handler(void) { static bool rtc_alarm_repeats(datetime_t *t) { // If any value is set to -1 then we don't match on that value // hence the alarm will eventually repeat - if (t->year == -1) return true; - if (t->month == -1) return true; - if (t->day == -1) return true; - if (t->dotw == -1) return true; - if (t->hour == -1) return true; - if (t->min == -1) return true; - if (t->sec == -1) return true; + if (t->year < 0) return true; + if (t->month < 0) return true; + if (t->day < 0) return true; + if (t->dotw < 0) return true; + if (t->hour < 0) return true; + if (t->min < 0) return true; + if (t->sec < 0) return true; return false; } @@ -145,22 +148,22 @@ void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback) { rtc_disable_alarm(); // Only add to setup if it isn't -1 - rtc_hw->irq_setup_0 = ((t->year == -1) ? 0 : (t->year << RTC_IRQ_SETUP_0_YEAR_LSB )) | - ((t->month == -1) ? 0 : (t->month << RTC_IRQ_SETUP_0_MONTH_LSB)) | - ((t->day == -1) ? 0 : (t->day << RTC_IRQ_SETUP_0_DAY_LSB )); - rtc_hw->irq_setup_1 = ((t->dotw == -1) ? 0 : (t->dotw << RTC_IRQ_SETUP_1_DOTW_LSB)) | - ((t->hour == -1) ? 0 : (t->hour << RTC_IRQ_SETUP_1_HOUR_LSB)) | - ((t->min == -1) ? 0 : (t->min << RTC_IRQ_SETUP_1_MIN_LSB )) | - ((t->sec == -1) ? 0 : (t->sec << RTC_IRQ_SETUP_1_SEC_LSB )); + rtc_hw->irq_setup_0 = ((t->year < 0) ? 0 : (((uint)t->year) << RTC_IRQ_SETUP_0_YEAR_LSB )) | + ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) | + ((t->day < 0) ? 0 : (((uint)t->day) << RTC_IRQ_SETUP_0_DAY_LSB )); + rtc_hw->irq_setup_1 = ((t->dotw < 0) ? 0 : (((uint)t->dotw) << RTC_IRQ_SETUP_1_DOTW_LSB)) | + ((t->hour < 0) ? 0 : (((uint)t->hour) << RTC_IRQ_SETUP_1_HOUR_LSB)) | + ((t->min < 0) ? 0 : (((uint)t->min) << RTC_IRQ_SETUP_1_MIN_LSB )) | + ((t->sec < 0) ? 0 : (((uint)t->sec) << RTC_IRQ_SETUP_1_SEC_LSB )); // Set the match enable bits for things we care about - if (t->year != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); - if (t->month != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); - if (t->day != -1) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); - if (t->dotw != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); - if (t->hour != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); - if (t->min != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); - if (t->sec != -1) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); + if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); + if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); + if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); + if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); + if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); + if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); + if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); // Does it repeat? I.e. do we not match on any of the bits _alarm_repeats = rtc_alarm_repeats(t); @@ -185,4 +188,4 @@ void rtc_disable_alarm(void) { while(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS) { tight_loop_contents(); } -} \ No newline at end of file +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h index 789efc6f0d4..e8dc95251a5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h @@ -10,6 +10,7 @@ #include "pico.h" #include "pico/time.h" #include "hardware/structs/spi.h" +#include "hardware/regs/dreq.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi #ifndef PARAM_ASSERTIONS_ENABLED_SPI @@ -35,6 +36,12 @@ extern "C" { * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information. */ +// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi + /** * Opaque type representing an SPI instance. */ @@ -56,16 +63,33 @@ typedef struct spi_inst spi_inst_t; */ #define spi1 ((spi_inst_t * const)spi1_hw) +#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI) +#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI)) +#endif + +#ifdef PICO_DEFAULT_SPI_INSTANCE +#define spi_default PICO_DEFAULT_SPI_INSTANCE +#endif + +/** \brief Enumeration of SPI CPHA (clock phase) values. + * \ingroup hardware_spi + */ typedef enum { SPI_CPHA_0 = 0, SPI_CPHA_1 = 1 } spi_cpha_t; +/** \brief Enumeration of SPI CPOL (clock polarity) values. + * \ingroup hardware_spi + */ typedef enum { SPI_CPOL_0 = 0, SPI_CPOL_1 = 1 } spi_cpol_t; +/** \brief Enumeration of SPI bit-order values. + * \ingroup hardware_spi + */ typedef enum { SPI_LSB_FIRST = 0, SPI_MSB_FIRST = 1 @@ -79,14 +103,14 @@ typedef enum { * Puts the SPI into a known state, and enable it. Must be called before other * functions. * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param baudrate Baudrate required in Hz + * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen + * and returned * - * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen, - * and this function does not return any indication of this. You can use the \ref spi_set_baudrate function - * which will return the actual baudrate selected if this is important. + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param baudrate Baudrate requested in Hz + * \return the actual baud rate set */ -void _spi_init(spi_inst_t *spi, uint baudrate); +uint spi_init(spi_inst_t *spi, uint baudrate); /*! \brief Deinitialise SPI instances * \ingroup hardware_spi @@ -109,13 +133,23 @@ void spi_deinit(spi_inst_t *spi); */ uint spi_set_baudrate(spi_inst_t *spi, uint baudrate); -/*! \brief Convert I2c instance to hardware instance number +/*! \brief Get SPI baudrate + * \ingroup hardware_spi + * + * Get SPI baudrate which was set by \see spi_set_baudrate + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return The actual baudrate set + */ +uint spi_get_baudrate(const spi_inst_t *spi); + +/*! \brief Convert SPI instance to hardware instance number * \ingroup hardware_spi * * \param spi SPI instance * \return Number of SPI, 0 or 1. */ -static inline uint spi_get_index(spi_inst_t *spi) { +static inline uint spi_get_index(const spi_inst_t *spi) { invalid_params_if(SPI, spi != spi0 && spi != spi1); return spi == spi1 ? 1 : 0; } @@ -125,6 +159,11 @@ static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { return (spi_hw_t *)spi; } +static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) { + spi_get_index(spi); // check it is a hw spi + return (const spi_hw_t *)spi; +} + /*! \brief Configure SPI * \ingroup hardware_spi * @@ -136,16 +175,16 @@ static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022 */ -static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, spi_order_t order) { +static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) { invalid_params_if(SPI, data_bits < 4 || data_bits > 16); // LSB-first not supported on PL022: invalid_params_if(SPI, order != SPI_MSB_FIRST); invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); hw_write_masked(&spi_get_hw(spi)->cr0, - (data_bits - 1) << SPI_SSPCR0_DSS_LSB | - cpol << SPI_SSPCR0_SPO_LSB | - cpha << SPI_SSPCR0_SPH_LSB, + ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB | + ((uint)cpol) << SPI_SSPCR0_SPO_LSB | + ((uint)cpha) << SPI_SSPCR0_SPH_LSB, SPI_SSPCR0_DSS_BITS | SPI_SSPCR0_SPO_BITS | SPI_SSPCR0_SPH_BITS); @@ -174,27 +213,30 @@ static inline void spi_set_slave(spi_inst_t *spi, bool slave) { * \ingroup hardware_spi * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return 0 if no space is available to write. Non-zero if a write is possible - * - * \note Although the controllers each have a 8 deep TX FIFO, the current HW implementation can only return 0 or 1 - * rather than the space available. + * \return false if no space is available to write. True if a write is possible */ -static inline size_t spi_is_writable(spi_inst_t *spi) { - // PL022 doesn't expose levels directly, so return values are only 0 or 1 - return (spi_get_hw(spi)->sr & SPI_SSPSR_TNF_BITS) >> SPI_SSPSR_TNF_LSB; +static inline bool spi_is_writable(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS); } /*! \brief Check whether a read can be done on SPI device * \ingroup hardware_spi * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return Non-zero if a read is possible i.e. data is present + * \return true if a read is possible i.e. data is present + */ +static inline bool spi_is_readable(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS); +} + +/*! \brief Check whether SPI is busy + * \ingroup hardware_spi * - * \note Although the controllers each have a 8 deep RX FIFO, the current HW implementation can only return 0 or 1 - * rather than the data available. + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return true if SPI is busy */ -static inline size_t spi_is_readable(spi_inst_t *spi) { - return (spi_get_hw(spi)->sr & SPI_SSPSR_RNE_BITS) >> SPI_SSPSR_RNE_LSB; +static inline bool spi_is_busy(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS); } /*! \brief Write/Read to/from an SPI device @@ -258,7 +300,7 @@ int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, s * \param src Buffer of data to write * \param dst Buffer for read data * \param len Length of BOTH buffers in halfwords - * \return Number of bytes written/read + * \return Number of halfwords written/read */ int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len); @@ -273,7 +315,7 @@ int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 * \param src Buffer of data to write * \param len Length of buffers - * \return Number of bytes written/read + * \return Number of halfwords written/read */ int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); @@ -291,11 +333,24 @@ int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 * \param repeated_tx_data Buffer of data to write * \param dst Buffer for read data - * \param len Length of buffer \p dst in halfwords - * \return Number of bytes written/read + * \param len Length of buffer \p dst in halfwords + * \return Number of halfwords written/read */ int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len); +/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance + * \ingroup hardware_spi + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance + */ +static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) { + static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, ""); + static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, ""); + static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, ""); + return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx; +} + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c index 1de19764e3c..880b5343159 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c @@ -18,18 +18,18 @@ static inline void spi_unreset(spi_inst_t *spi) { unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); } -void _spi_init(spi_inst_t *spi, uint baudrate) { +uint spi_init(spi_inst_t *spi, uint baudrate) { spi_reset(spi); spi_unreset(spi); - (void) spi_set_baudrate(spi, baudrate); + uint baud = spi_set_baudrate(spi, baudrate); spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); // Always enable DREQ signals -- harmless if DMA is not listening hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); - spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); // Finally enable the SPI hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); + return baud; } void spi_deinit(spi_inst_t *spi) { @@ -65,16 +65,24 @@ uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) { return freq_in / (prescale * postdiv); } +uint spi_get_baudrate(const spi_inst_t *spi) { + uint prescale = spi_get_const_hw(spi)->cpsr; + uint postdiv = ((spi_get_const_hw(spi)->cr0 & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1; + return clock_get_hz(clk_peri) / (prescale * postdiv); +} + // Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst. // Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit) int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) { + invalid_params_if(SPI, 0 > (int)len); + // Never have more transfers in flight than will fit into the RX FIFO, // else FIFO will overflow if this code is heavily interrupted. const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { spi_get_hw(spi)->dr = (uint32_t) *src++; --tx_remaining; } @@ -84,11 +92,12 @@ int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t } } - return len; + return (int)len; } // Write len bytes directly from src to the SPI, and discard any data received back int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) { + invalid_params_if(SPI, 0 > (int)len); // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX // is full, PL022 inhibits RX pushes, and sets a sticky flag on // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set. @@ -109,7 +118,7 @@ int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, // Don't leave overrun flag set spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; - return len; + return (int)len; } // Read len bytes directly from the SPI to dst. @@ -117,11 +126,12 @@ int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, // Generally this can be 0, but some devices require a specific value here, // e.g. SD cards expect 0xff int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) { + invalid_params_if(SPI, 0 > (int)len); const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; --tx_remaining; } @@ -131,18 +141,19 @@ int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_ } } - return len; + return (int)len; } // Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst. int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) { + invalid_params_if(SPI, 0 > (int)len); // Never have more transfers in flight than will fit into the RX FIFO, // else FIFO will overflow if this code is heavily interrupted. const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { spi_get_hw(spi)->dr = (uint32_t) *src++; --tx_remaining; } @@ -152,11 +163,12 @@ int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint } } - return len; + return (int)len; } // Write len bytes directly from src to the SPI, and discard any data received back int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) { + invalid_params_if(SPI, 0 > (int)len); // Deliberately overflow FIFO, then clean up afterward, to minimise amount // of APB polling required per halfword for (size_t i = 0; i < len; ++i) { @@ -175,17 +187,18 @@ int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *s // Don't leave overrun flag set spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS; - return len; + return (int)len; } // Read len halfwords directly from the SPI to dst. // repeated_tx_data is output repeatedly on SO as data is read in from SI. int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) { + invalid_params_if(SPI, 0 > (int)len); const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; while (rx_remaining || tx_remaining) { - if (tx_remaining && spi_is_writable(spi) && rx_remaining - tx_remaining < fifo_depth) { + if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) { spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data; --tx_remaining; } @@ -195,5 +208,5 @@ int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_ } } - return len; + return (int)len; } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h index f375ff8bdad..8f91d55955c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h @@ -15,21 +15,41 @@ extern "C" { #endif - /** \file hardware/sync.h * \defgroup hardware_sync hardware_sync * - * Low level hardware spin-lock, barrier and processor event API + * Low level hardware spin locks, barrier and processor event APIs * - * Functions for synchronisation between core's, HW, etc + * Spin Locks + * ---------- * * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software - * resources. + * and hardware resources. + * + * Generally each spin lock itself is a shared resource, + * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor + * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used + * individually without more flexibility and without regard to other software. Note that no hardware spin lock may + * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related + * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable, + * and spin locks are only expected to be held for brief periods. * - * \note spin locks 0-15 are currently reserved for fixed uses by the SDK - i.e. if you use them other - * functionality may break or not function optimally + * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes + * vs those suitable for more general shared use: + * + * Number (ID) | Description + * :---------: | ----------- + * 0-13 | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those. + * 14,15 | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK. + * 16-23 | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock. + * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused() */ +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync +#ifndef PARAM_ASSERTIONS_ENABLED_SYNC +#define PARAM_ASSERTIONS_ENABLED_SYNC 0 +#endif + /** \brief A spin lock identifier * \ingroup hardware_sync */ @@ -50,38 +70,46 @@ typedef volatile uint32_t spin_lock_t; #define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Spinlock ID for striped first, min=16, max=31, default=16, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS1 +#define PICO_SPINLOCK_ID_OS1 14 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS2 +#define PICO_SPINLOCK_ID_OS2 15 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_FIRST #define PICO_SPINLOCK_ID_STRIPED_FIRST 16 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Spinlock ID for striped last, min=16, max=31, default=23, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_LAST #define PICO_SPINLOCK_ID_STRIPED_LAST 23 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Spinlock ID for claim free first, min=16, max=31, default=24, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync #ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST #define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_END, Spinlock ID for claim free end, min=16, max=31, default=31, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_END -#define PICO_SPINLOCK_ID_CLAIM_FREE_END 31 +#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END +#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync -#ifndef PARAM_ASSERTIONS_ENABLED_SYNC -#define PARAM_ASSERTIONS_ENABLED_SYNC 0 +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 #endif - /*! \brief Insert a SEV instruction in to the code path. * \ingroup hardware_sync * The SEV (send event) instruction sends an event to both cores. */ -inline static void __sev() { +__force_inline static void __sev(void) { __asm volatile ("sev"); } @@ -91,7 +119,7 @@ inline static void __sev() { * The WFE (wait for event) instruction waits until one of a number of * events occurs, including events signalled by the SEV instruction on either core. */ -inline static void __wfe() { +__force_inline static void __wfe(void) { __asm volatile ("wfe"); } @@ -100,7 +128,7 @@ inline static void __wfe() { * * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core. */ -inline static void __wfi() { +__force_inline static void __wfi(void) { __asm volatile ("wfi"); } @@ -110,8 +138,19 @@ inline static void __wfi() { * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this * instruction will be observed before any explicit access after the instruction. */ -inline static void __dmb() { - __asm volatile ("dmb"); +__force_inline static void __dmb(void) { + __asm volatile ("dmb" : : : "memory"); +} + +/*! \brief Insert a DSB instruction in to the code path. + * \ingroup hardware_sync + * + * The DSB (data synchronization barrier) acts as a special kind of data + * memory barrier (DMB). The DSB operation completes when all explicit memory + * accesses before this instruction complete. + */ +__force_inline static void __dsb(void) { + __asm volatile ("dsb" : : : "memory"); } /*! \brief Insert a ISB instruction in to the code path. @@ -121,14 +160,14 @@ inline static void __dmb() { * so that all instructions following the ISB are fetched from cache or memory again, after * the ISB instruction has been completed. */ -inline static void __isb() { +__force_inline static void __isb(void) { __asm volatile ("isb"); } /*! \brief Acquire a memory fence * \ingroup hardware_sync */ -inline static void __mem_fence_acquire() { +__force_inline static void __mem_fence_acquire(void) { // the original code below makes it hard for us to be included from C++ via a header // which itself is in an extern "C", so just use __dmb instead, which is what // is required on Cortex M0+ @@ -144,7 +183,7 @@ inline static void __mem_fence_acquire() { * \ingroup hardware_sync * */ -inline static void __mem_fence_release() { +__force_inline static void __mem_fence_release(void) { // the original code below makes it hard for us to be included from C++ via a header // which itself is in an extern "C", so just use __dmb instead, which is what // is required on Cortex M0+ @@ -161,7 +200,7 @@ inline static void __mem_fence_release() { * * \return The prior interrupt enable status for restoration later via restore_interrupts() */ -inline static uint32_t save_and_disable_interrupts() { +__force_inline static uint32_t save_and_disable_interrupts(void) { uint32_t status; __asm volatile ("mrs %0, PRIMASK" : "=r" (status)::); __asm volatile ("cpsid i"); @@ -173,7 +212,7 @@ inline static uint32_t save_and_disable_interrupts() { * * \param status Previous interrupt status from save_and_disable_interrupts() */ -inline static void restore_interrupts(uint32_t status) { +__force_inline static void restore_interrupts(uint32_t status) { __asm volatile ("msr PRIMASK,%0"::"r" (status) : ); } @@ -183,7 +222,8 @@ inline static void restore_interrupts(uint32_t status) { * \param lock_num Spinlock ID * \return The spinlock instance */ -inline static spin_lock_t *spin_lock_instance(uint lock_num) { +__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { + invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS); return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); } @@ -193,8 +233,11 @@ inline static spin_lock_t *spin_lock_instance(uint lock_num) { * \param lock The Spinlock instance * \return The Spinlock ID */ -inline static uint spin_lock_get_num(spin_lock_t *lock) { - return lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET); +__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { + invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || + (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || + ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); + return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); } /*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) @@ -202,7 +245,7 @@ inline static uint spin_lock_get_num(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { +__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core // anyway which should be finished soon @@ -215,7 +258,7 @@ inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static void spin_unlock_unsafe(spin_lock_t *lock) { +__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { __mem_fence_release(); *lock = 0; } @@ -228,7 +271,7 @@ inline static void spin_unlock_unsafe(spin_lock_t *lock) { * \param lock Spinlock instance * \return interrupt status to be used when unlocking, to restore to original state */ -inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { +__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { uint32_t save = save_and_disable_interrupts(); spin_lock_unsafe_blocking(lock); return save; @@ -239,9 +282,9 @@ inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static bool is_spin_locked(const spin_lock_t *lock) { +inline static bool is_spin_locked(spin_lock_t *lock) { check_hw_size(spin_lock_t, 4); - uint32_t lock_num = lock - spin_lock_instance(0); + uint lock_num = spin_lock_get_num(lock); return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); } @@ -256,7 +299,7 @@ inline static bool is_spin_locked(const spin_lock_t *lock) { * * \sa spin_lock_blocking() */ -inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { +__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { spin_unlock_unsafe(lock); restore_interrupts(saved_irq); } @@ -266,7 +309,7 @@ inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { * * \return The core number the call was made from */ -static inline uint get_core_num() { +__force_inline static uint get_core_num(void) { return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); } @@ -285,8 +328,22 @@ spin_lock_t *spin_lock_init(uint lock_num); */ void spin_locks_reset(void); -// this number is not claimed -uint next_striped_spin_lock_num(); +/*! \brief Return a spin lock number from the _striped_ range + * \ingroup hardware_sync + * + * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST + * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller + * must: + * + * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()), + * and not whilst holding other spin locks. + * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock. + * + * \return lock_num a spin lock number the caller may use (non exclusively) + * \see PICO_SPINLOCK_ID_STRIPED_FIRST + * \see PICO_SPINLOCK_ID_STRIPED_LAST + */ +uint next_striped_spin_lock_num(void); /*! \brief Mark a spin lock as used * \ingroup hardware_sync @@ -327,6 +384,16 @@ void spin_lock_unclaim(uint lock_num); */ int spin_lock_claim_unused(bool required); +/*! \brief Determine if a spin lock is claimed + * \ingroup hardware_sync + * + * \param lock_num the spin lock number + * \return true if claimed, false otherwise + * \see spin_lock_claim + * \see spin_lock_claim_mask + */ +bool spin_lock_is_claimed(uint lock_num); + #define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); }) #ifdef __cplusplus diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c index dba040a1772..a15c8d623ee 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/sync.c @@ -22,7 +22,7 @@ void spin_locks_reset(void) { } spin_lock_t *spin_lock_init(uint lock_num) { - assert(lock_num >= 0 && lock_num < NUM_SPIN_LOCKS); + assert(lock_num < NUM_SPIN_LOCKS); spin_lock_t *lock = spin_lock_instance(lock_num); spin_unlock_unsafe(lock); return lock; @@ -49,10 +49,16 @@ void spin_lock_claim_mask(uint32_t mask) { void spin_lock_unclaim(uint lock_num) { check_lock_num(lock_num); + spin_unlock_unsafe(spin_lock_instance(lock_num)); hw_claim_clear((uint8_t *) &claimed, lock_num); } int spin_lock_claim_unused(bool required) { - return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_END, "No spinlocks are available"); + return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_LAST, "No spinlocks are available"); +} + +bool spin_lock_is_claimed(uint lock_num) { + check_lock_num(lock_num); + return hw_is_claimed((uint8_t *) &claimed, lock_num); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h index 1815a2780eb..1799cd00ee6 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h @@ -50,7 +50,7 @@ extern "C" { #define PARAM_ASSERTIONS_ENABLED_TIMER 0 #endif -static inline void check_hardware_alarm_num_param(uint alarm_num) { +static inline void check_hardware_alarm_num_param(__unused uint alarm_num) { invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); } @@ -62,7 +62,7 @@ static inline void check_hardware_alarm_num_param(uint alarm_num) { * * \return the 32 bit timestamp */ -static inline uint32_t time_us_32() { +static inline uint32_t time_us_32(void) { return timer_hw->timerawl; } @@ -75,22 +75,29 @@ static inline uint32_t time_us_32() { * * \return the 64 bit timestamp */ -uint64_t time_us_64(); +uint64_t time_us_64(void); /*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds * \ingroup hardware_timer * - * \param delay_us delay amount + * \param delay_us delay amount in microseconds */ void busy_wait_us_32(uint32_t delay_us); /*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds * \ingroup hardware_timer * - * \param delay_us delay amount + * \param delay_us delay amount in microseconds */ void busy_wait_us(uint64_t delay_us); +/*! \brief Busy wait wasting cycles for the given number of milliseconds + * \ingroup hardware_timer + * + * \param delay_ms delay amount in milliseconds + */ +void busy_wait_ms(uint32_t delay_ms); + /*! \brief Busy wait wasting cycles until after the specified timestamp * \ingroup hardware_timer * @@ -106,7 +113,7 @@ void busy_wait_until(absolute_time_t t); */ static inline bool time_reached(absolute_time_t t) { uint64_t target = to_us_since_boot(t); - uint32_t hi_target = target >> 32u; + uint32_t hi_target = (uint32_t)(target >> 32u); uint32_t hi = timer_hw->timerawh; return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target)); } @@ -115,7 +122,7 @@ static inline bool time_reached(absolute_time_t t) { * \ingroup hardware_timer * * \param alarm_num the hardware alarm number - * \sa hardware_alarm_set_callback + * \sa hardware_alarm_set_callback() */ typedef void (*hardware_alarm_callback_t)(uint alarm_num); @@ -137,6 +144,15 @@ void hardware_alarm_claim(uint alarm_num); */ void hardware_alarm_unclaim(uint alarm_num); +/*! \brief Determine if a hardware alarm has been claimed + * \ingroup hardware_timer + * + * \param alarm_num the hardware alarm number + * \return true if claimed, false otherwise + * \see hardware_alarm_claim + */ +bool hardware_alarm_is_claimed(uint alarm_num); + /*! \brief Enable/Disable a callback for a hardware timer on this core * \ingroup hardware_timer * @@ -151,12 +167,13 @@ void hardware_alarm_unclaim(uint alarm_num); * \param alarm_num the hardware alarm number * \param callback the callback to install, or NULL to unset * - * \sa hardware_alarm_set_target + * \sa hardware_alarm_set_target() */ void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); /** * \brief Set the current target for the specified hardware alarm + * \ingroup hardware_timer * * This will replace any existing target * @@ -168,6 +185,7 @@ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); /** * \brief Cancel an existing target (if any) for a given hardware_alarm + * \ingroup hardware_timer * * @param alarm_num */ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c index 76d5f9038ac..f13d2499607 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/timer.c @@ -28,6 +28,11 @@ void hardware_alarm_unclaim(uint alarm_num) { hw_claim_clear(&claimed, alarm_num); } +bool hardware_alarm_is_claimed(uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + return hw_is_claimed(&claimed, alarm_num); +} + /// tag::time_us_64[] uint64_t time_us_64() { // Need to make sure that the upper 32 bits of the timer @@ -73,9 +78,18 @@ void busy_wait_us(uint64_t delay_us) { busy_wait_until(t); } +void busy_wait_ms(uint32_t delay_ms) +{ + if (delay_ms <= 0x7fffffffu / 1000) { + busy_wait_us_32(delay_ms * 1000); + } else { + busy_wait_us(delay_ms * 1000ull); + } +} + void busy_wait_until(absolute_time_t t) { uint64_t target = to_us_since_boot(t); - uint32_t hi_target = target >> 32u; + uint32_t hi_target = (uint32_t)(target >> 32u); uint32_t hi = timer_hw->timerawh; while (hi < hi_target) { hi = timer_hw->timerawh; @@ -92,7 +106,7 @@ static inline uint harware_alarm_irq_number(uint alarm_num) { return TIMER_IRQ_0 + alarm_num; } -static void hardware_alarm_irq_handler() { +static void hardware_alarm_irq_handler(void) { // Determine which timer this IRQ is for uint32_t ipsr; __asm volatile ("mrs %0, ipsr" : "=r" (ipsr)::); @@ -113,7 +127,7 @@ static void hardware_alarm_irq_handler() { if (timer_hw->timerawh >= target_hi[alarm_num]) { // we have reached the right high word as well as low word value callback = alarm_callbacks[alarm_num]; - timer_callbacks_pending &= ~(1u << alarm_num); + timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); } else { // try again in 2^32 us timer_hw->alarm[alarm_num] = timer_hw->alarm[alarm_num]; // re-arm the timer @@ -147,7 +161,7 @@ void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callb alarm_callbacks[alarm_num] = callback; } else { alarm_callbacks[alarm_num] = NULL; - timer_callbacks_pending &= ~(1u << alarm_num); + timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); irq_remove_handler(irq_num, hardware_alarm_irq_handler); irq_set_enabled(irq_num, false); } @@ -166,11 +180,12 @@ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) { // 1) actually set the hardware timer spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); - timer_hw->intr = 1u << alarm_num; - timer_callbacks_pending |= 1u << alarm_num; + uint8_t old_timer_callbacks_pending = timer_callbacks_pending; + timer_callbacks_pending |= (uint8_t)(1u << alarm_num); + timer_hw->intr = 1u << alarm_num; // clear any IRQ timer_hw->alarm[alarm_num] = (uint32_t) t; // Set the alarm. Writing time should arm it - target_hi[alarm_num] = t >> 32u; + target_hi[alarm_num] = (uint32_t)(t >> 32u); // 2) check for races if (!(timer_hw->armed & 1u << alarm_num)) { @@ -178,18 +193,26 @@ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) { assert(timer_hw->ints & 1u << alarm_num); } else { if (time_us_64() >= t) { - // ok well it is time now; the irq isn't being handled yet because of the spin lock - // however the other core might be in the IRQ handler itself about to do a callback - // we do the firing ourselves (and indicate to the IRQ handler if any that it shouldn't + // we are already at or past the right time; there is no point in us racing against the IRQ + // we are about to generate. note however that, if there was already a timer pending before, + // then we still let the IRQ fire, as whatever it was, is not handled by our setting missed=true here missed = true; - // disarm the timer - timer_hw->armed = 1u << alarm_num; - timer_hw->intr = 1u << alarm_num; // clear the IRQ too - // and set flag in case we're already in the IRQ handler waiting on the spinlock (on the other core) - timer_callbacks_pending &= ~(1u << alarm_num); + if (timer_callbacks_pending != old_timer_callbacks_pending) { + // disarm the timer + timer_hw->armed = 1u << alarm_num; + // clear the IRQ... + timer_hw->intr = 1u << alarm_num; + // ... including anything pending on the processor - perhaps unnecessary, but + // our timer flag says we aren't expecting anything. + irq_clear(harware_alarm_irq_number(alarm_num)); + // and clear our flag so that if the IRQ handler is already active (because it is on + // the other core) it will also skip doing anything + timer_callbacks_pending = old_timer_callbacks_pending; + } } } spin_unlock(lock, save); + // note at this point any pending timer IRQ can likely run } return missed; } @@ -200,7 +223,7 @@ void hardware_alarm_cancel(uint alarm_num) { spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); timer_hw->armed = 1u << alarm_num; - timer_callbacks_pending &= ~(1u << alarm_num); + timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); spin_unlock(lock, save); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h index 58c0e800bec..bce0d2f0f81 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -9,6 +9,7 @@ #include "pico.h" #include "hardware/structs/uart.h" +#include "hardware/regs/dreq.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart #ifndef PARAM_ASSERTIONS_ENABLED_UART @@ -29,26 +30,15 @@ extern "C" { #define PICO_UART_DEFAULT_CRLF 0 #endif -// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, default=0, group=hardware_uart -#ifndef PICO_DEFAULT_UART -#define PICO_DEFAULT_UART 0 ///< Default UART instance -#endif +// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, group=hardware_uart // PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart #ifndef PICO_DEFAULT_UART_BAUD_RATE #define PICO_DEFAULT_UART_BAUD_RATE 115200 ///< Default baud rate #endif -// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, default=0, group=hardware_uart -#ifndef PICO_DEFAULT_UART_TX_PIN -#define PICO_DEFAULT_UART_TX_PIN 0 ///< Default TX pin -#endif - -// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, default=1, group=hardware_uart -#ifndef PICO_DEFAULT_UART_RX_PIN -#define PICO_DEFAULT_UART_RX_PIN 1 ///< Default RX pin -#endif - /** \file hardware/uart.h * \defgroup hardware_uart hardware_uart * @@ -93,11 +83,13 @@ typedef struct uart_inst uart_inst_t; /** @} */ -#ifndef PICO_DEFAULT_UART_INSTANCE +#if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART) #define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART)) #endif +#ifdef PICO_DEFAULT_UART_INSTANCE #define uart_default PICO_DEFAULT_UART_INSTANCE +#endif /*! \brief Convert UART instance to hardware instance number * \ingroup hardware_uart @@ -110,6 +102,12 @@ static inline uint uart_get_index(uart_inst_t *uart) { return uart == uart1 ? 1 : 0; } +static inline uart_inst_t *uart_get_instance(uint instance) { + static_assert(NUM_UARTS == 2, ""); + invalid_params_if(UART, instance >= NUM_UARTS); + return instance ? uart1 : uart0; +} + static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) { uart_get_index(uart); // check it is a hw uart return (uart_hw_t *)uart; @@ -172,7 +170,7 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate); */ static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) { hw_write_masked(&uart_get_hw(uart)->cr, - (!!cts << UART_UARTCR_CTSEN_LSB) | (!!rts << UART_UARTCR_RTSEN_LSB), + (bool_to_bit(cts) << UART_UARTCR_CTSEN_LSB) | (bool_to_bit(rts) << UART_UARTCR_RTSEN_LSB), UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS); } @@ -191,10 +189,10 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_ invalid_params_if(UART, stop_bits != 1 && stop_bits != 2); invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); hw_write_masked(&uart_get_hw(uart)->lcr_h, - ((data_bits - 5) << UART_UARTLCR_H_WLEN_LSB) | - ((stop_bits - 1) << UART_UARTLCR_H_STP2_LSB) | - ((parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | - ((parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), + ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) | + ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) | + (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | + (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS | UART_UARTLCR_H_PEN_BITS | @@ -208,13 +206,17 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_ * this function. * * \param uart UART instance. \ref uart0 or \ref uart1 - * \param rx_has_data If true an interrupt will be fired when the RX FIFO contain data. + * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data. * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data. */ static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { - uart_get_hw(uart)->imsc = (!!tx_needs_data << UART_UARTIMSC_TXIM_LSB) | - (!!rx_has_data << UART_UARTIMSC_RXIM_LSB) | - (1 << UART_UARTIMSC_RTIM_LSB); + // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are + // required for rx_has_data. RX asserts when >=4 characters are in the RX + // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no + // more have been received for 32 bit periods. + uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) | + (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) | + (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB); if (rx_has_data) { // Set minimum threshold hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB, @@ -245,7 +247,7 @@ static inline bool uart_is_enabled(uart_inst_t *uart) { */ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { hw_write_masked(&uart_get_hw(uart)->lcr_h, - (!!enabled << UART_UARTLCR_H_FEN_LSB), + (bool_to_bit(enabled) << UART_UARTLCR_H_FEN_LSB), UART_UARTLCR_H_FEN_BITS); } @@ -253,14 +255,14 @@ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { // ---------------------------------------------------------------------------- // Generic input/output -/*! \brief Determine if the TX FIFO is empty. +/*! \brief Determine if space is available in the TX FIFO * \ingroup hardware_uart * * \param uart UART instance. \ref uart0 or \ref uart1 * \return false if no space available, true otherwise */ static inline bool uart_is_writable(uart_inst_t *uart) { - return (uart_get_hw(uart)->fr & UART_UARTFR_TXFE_BITS); + return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS); } /*! \brief Wait for the UART TX fifo to be drained @@ -315,7 +317,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le for (size_t i = 0; i < len; ++i) { while (!uart_is_readable(uart)) tight_loop_contents(); - *dst++ = uart_get_hw(uart)->dr; + *dst++ = (uint8_t) uart_get_hw(uart)->dr; } } @@ -325,7 +327,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le /*! \brief Write single character to UART for transmission. * \ingroup hardware_uart * - * This function will block until all the character has been sent + * This function will block until the entire character has been sent * * \param uart UART instance. \ref uart0 or \ref uart1 * \param c The character to send @@ -411,11 +413,15 @@ static inline void uart_set_break(uart_inst_t *uart, bool en) { */ void uart_set_translate_crlf(uart_inst_t *uart, bool translate); -/*! \brief Wait for the default UART'S TX fifo to be drained +/*! \brief Wait for the default UART's TX FIFO to be drained * \ingroup hardware_uart */ -static inline void uart_default_tx_wait_blocking() { +static inline void uart_default_tx_wait_blocking(void) { +#ifdef uart_default uart_tx_wait_blocking(uart_default); +#else + assert(false); +#endif } /*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty @@ -427,6 +433,19 @@ static inline void uart_default_tx_wait_blocking() { */ bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us); +/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance + */ +static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) { + static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, ""); + static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, ""); + static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, ""); + return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx; +} + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c index 51d8d74b223..ba48e87b11c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/uart.c @@ -74,7 +74,7 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { invalid_params_if(UART, baudrate == 0); uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate); uint32_t baud_ibrd = baud_rate_div >> 7; - uint32_t baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; + uint32_t baud_fbrd; if (baud_ibrd == 0) { baud_ibrd = 1; @@ -82,6 +82,8 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { } else if (baud_ibrd >= 65535) { baud_ibrd = 65535; baud_fbrd = 0; + } else { + baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; } // Load PL011's baud divisor registers diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c index 654ab5af3d3..501b0d4e096 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_vreg/vreg.c @@ -8,5 +8,5 @@ #include "hardware/vreg.h" void vreg_set_voltage(enum vreg_voltage voltage) { - hw_write_masked(&vreg_and_chip_reset_hw->vreg, voltage << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS); + hw_write_masked(&vreg_and_chip_reset_hw->vreg, ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h index ae5ccdc8639..747838be851 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h @@ -8,6 +8,7 @@ #define _HARDWARE_WATCHDOG_H #include "pico.h" +#include "hardware/structs/watchdog.h" /** \file hardware/watchdog.h * \defgroup hardware_watchdog hardware_watchdog @@ -25,10 +26,14 @@ * \include hello_watchdog.c */ +#ifdef __cplusplus +extern "C" { +#endif + /*! \brief Define actions to perform at watchdog timeout * \ingroup hardware_watchdog * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms * parameter will not be in microseconds. See the datasheet for more details. * * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. @@ -57,11 +62,16 @@ void watchdog_update(void); * \brief Enable the watchdog * \ingroup hardware_watchdog * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms * parameter will not be in microseconds. See the datasheet for more details. * * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. * + * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot. + * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2 + * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will + * return false. + * * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code */ @@ -71,11 +81,30 @@ void watchdog_enable(uint32_t delay_ms, bool pause_on_debug); * \brief Did the watchdog cause the last reboot? * \ingroup hardware_watchdog * - * @return true if the watchdog timer or a watchdog force caused the last reboot - * @return false there has been no watchdog reboot since run has been + * @return true If the watchdog timer or a watchdog force caused the last reboot + * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. */ bool watchdog_caused_reboot(void); +/** + * \brief Did watchdog_enable cause the last reboot? + * \ingroup hardware_watchdog + * + * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by + * \ref watchdog_enable caused the last reboot. + * + * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable. + * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom + * (e.g. dragging a UF2 onto the RPI-RP2 drive). + * + * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot + * and the watchdog reboot happened after \ref watchdog_enable was called + * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused + * by a watchdog timeout after \ref watchdog_enable was called. + * A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. + */ +bool watchdog_enable_caused_reboot(void); + /** * @brief Returns the number of microseconds before the watchdog will reboot the chip. * \ingroup hardware_watchdog @@ -84,4 +113,8 @@ bool watchdog_caused_reboot(void); */ uint32_t watchdog_get_count(void); +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c index 36031aaffca..954520577d4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/watchdog.c @@ -49,25 +49,28 @@ void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); } - if (!delay_ms) delay_ms = 50; - - // Note, we have x2 here as the watchdog HW currently decrements twice per tick - load_value = delay_ms * 1000 * 2; - - if (load_value > 0xffffffu) - load_value = 0xffffffu; + if (!delay_ms) { + hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); + } else { + // Note, we have x2 here as the watchdog HW currently decrements twice per tick + load_value = delay_ms * 1000 * 2; + if (load_value > 0xffffffu) + load_value = 0xffffffu; - watchdog_update(); + watchdog_update(); - hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); + hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); + } } // end::watchdog_enable[] +#define WATCHDOG_NON_REBOOT_MAGIC 0x6ab73121 + void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { - // This watchdog enable doesn't reboot so clear scratch register - // with magic word to jump into code - watchdog_hw->scratch[4] = 0; + // update scratch[4] to distinguish from magic used for reboot to specific address, or 0 used to reboot + // into regular flash path + watchdog_hw->scratch[4] = WATCHDOG_NON_REBOOT_MAGIC; _watchdog_enable(delay_ms, pause_on_debug); } @@ -96,4 +99,8 @@ void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { bool watchdog_caused_reboot(void) { // If any reason bits are set this is true return watchdog_hw->reason; +} + +bool watchdog_enable_caused_reboot(void) { + return watchdog_hw->reason && watchdog_hw->scratch[4] == WATCHDOG_NON_REBOOT_MAGIC; } \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h index 0aa0842dbcb..a5e33b03710 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h @@ -10,6 +10,15 @@ #include "pico.h" #include "hardware/structs/xosc.h" + +// Allow lengthening startup delay to accommodate slow-starting oscillators + +// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1 +#endif + + #ifdef __cplusplus extern "C" { #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c index 977f0bdc007..7a7055cb7ec 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/xosc.c @@ -11,16 +11,25 @@ #include "hardware/platform_defs.h" #include "hardware/regs/xosc.h" -#include "hardware/structs/xosc.h" +#include "hardware/xosc.h" + +#if XOSC_MHZ < 1 || XOSC_MHZ > 50 +#error XOSC_MHZ must be in the range 1-50 +#endif + +#define STARTUP_DELAY (((((XOSC_MHZ * MHZ) / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER) + +// The DELAY field in xosc_hw->startup is 14 bits wide. +#if STARTUP_DELAY >= (1 << 13) +#error PICO_XOSC_STARTUP_DELAY_MULTIPLIER is too large: XOSC STARTUP.DELAY must be < 8192 +#endif void xosc_init(void) { - // Assumes 1-15 MHz input - assert(XOSC_MHZ <= 15); + // Assumes 1-15 MHz input, checked above. xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; // Set xosc startup delay - uint32_t startup_delay = (((12 * MHZ) / 1000) + 128) / 256; - xosc_hw->startup = startup_delay; + xosc_hw->startup = STARTUP_DELAY; // Set the enable bit now that we have set freq range and startup delay hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); @@ -43,4 +52,4 @@ void xosc_dormant(void) { xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT; // Wait for it to become stable once woken up while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)); -} \ No newline at end of file +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt index 7e5f2b97c73..962c3078ddd 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/CMakeLists.txt @@ -1,13 +1,9 @@ if (NOT TARGET pico_bit_ops) #shims for ROM functions for -lgcc functions (listed below) - add_library(pico_bit_ops INTERFACE) + pico_add_impl_library(pico_bit_ops) # no custom implementation; falls thru to compiler - add_library(pico_bit_ops_compiler INTERFACE) - # PICO_BUILD_DEFINE: PICO_BIT_OPS_COMPILER, whether compiler provided bit_ops bit functions support is being used, type=bool, default=0, but dependent on CMake options, group=pico_bit_ops - target_compile_definitions(pico_bit_ops_compiler INTERFACE - PICO_BIT_OPS_COMPILER=1 - ) + pico_add_impl_library(pico_bit_ops_compiler) # add alias "default" which is just pico. add_library(pico_bit_ops_default INTERFACE) @@ -15,15 +11,10 @@ if (NOT TARGET pico_bit_ops) set(PICO_DEFAULT_BIT_OPS_IMPL pico_bit_ops_default) - add_library(pico_bit_ops_pico INTERFACE) + pico_add_impl_library(pico_bit_ops_pico) target_link_libraries(pico_bit_ops INTERFACE $>,$,${PICO_DEFAULT_BIT_OPS_IMPL}>) - # PICO_BUILD_DEFINE: PICO_BIT_OPS_PICO, whether optimized pico/bootrom provided bit_ops bit functions support is being used, type=bool, default=1, but dependent on CMake options, group=pico_bit_ops - target_compile_definitions(pico_bit_ops_pico INTERFACE - PICO_BIT_OPS_PICO=1 - ) - target_sources(pico_bit_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/bit_ops_aeabi.S ) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S index 7c0b42cc672..eba839eed42 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bit_ops/bit_ops_aeabi.S @@ -9,6 +9,8 @@ .thumb #include "pico/asm_helper.S" +#include "pico/bootrom.h" + __pre_init __aeabi_bits_init, 00010 .macro bits_section name @@ -24,10 +26,10 @@ __pre_init __aeabi_bits_init, 00010 .equ BITS_FUNC_COUNT, 4 .align 4 aeabi_bits_funcs: - .word rom_table_code('P','3') // popcount32 - .word rom_table_code('L','3') // clz32 - .word rom_table_code('T','3') // ctz32 - .word rom_table_code('R','3') // reverse32 + .word ROM_FUNC_POPCOUNT32 + .word ROM_FUNC_CLZ32 + .word ROM_FUNC_CTZ32 + .word ROM_FUNC_REVERSE32 aeabi_bits_funcs_end: .section .text diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c index 08cdb33738e..af7d09148cf 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/bootrom.c @@ -16,9 +16,7 @@ typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); #define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address) void *rom_func_lookup(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); - uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); - return rom_table_lookup(func_table, code); + return rom_func_lookup_inline(code); } void *rom_data_lookup(uint32_t code) { diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h index 1aa12973ef9..e55789315cc 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h @@ -12,20 +12,75 @@ /** \file bootrom.h * \defgroup pico_bootrom pico_bootrom * Access to functions and data in the RP2040 bootrom + * + * This header may be included by assembly code */ +// ROM FUNCTIONS + +#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') +#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') +#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') +#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') +#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') +#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') +#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') +#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') +#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') +#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') +#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') +#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') +#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') +#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') +#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') /*! \brief Return a bootrom lookup code based on two ASCII characters * \ingroup pico_bootrom * * These codes are uses to lookup data or function addresses in the bootrom - * + * * \param c1 the first character * \param c2 the second character * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() */ -static inline uint32_t rom_table_code(char c1, char c2) { - return (c2 << 8u) | c1; +#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) + +#ifndef __ASSEMBLER__ + +// ROM FUNCTION SIGNATURES + +typedef uint32_t (*rom_popcount32_fn)(uint32_t); +typedef uint32_t (*rom_reverse32_fn)(uint32_t); +typedef uint32_t (*rom_clz32_fn)(uint32_t); +typedef uint32_t (*rom_ctz32_fn)(uint32_t); +typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t); +typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t); +typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t); +typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t); +typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t); +typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility +typedef void (*rom_connect_internal_flash_fn)(void); +typedef void (*rom_flash_exit_xip_fn)(void); +typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t); +typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t); +typedef void (*rom_flash_flush_cache_fn)(void); +typedef void (*rom_flash_enter_cmd_xip_fn)(void); + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Return a bootrom lookup code based on two ASCII characters + * \ingroup pico_bootrom + * + * These codes are uses to lookup data or function addresses in the bootrom + * + * \param c1 the first character + * \param c2 the second character + * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() + */ +static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) { + return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2); } /*! @@ -57,7 +112,24 @@ void *rom_data_lookup(uint32_t code); */ bool rom_funcs_lookup(uint32_t *table, unsigned int count); -typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t); +// Bootrom function: rom_table_lookup +// Returns the 32 bit pointer into the ROM if found or NULL otherwise. +typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); + +// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer +#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address) + +/*! + * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage + * \ingroup pico_bootrom + * \param code the code + * \return a pointer to the function, or NULL if the code does not match any bootrom function + */ +static __force_inline void *rom_func_lookup_inline(uint32_t code) { + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); + uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); + return rom_table_lookup(func_table, code); +} /*! * \brief Reboot the device into BOOTSEL mode @@ -78,8 +150,13 @@ typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t); */ static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { - reset_usb_boot_fn func = (reset_usb_boot_fn) rom_func_lookup(rom_table_code('U', 'B')); + rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); func(usb_activity_gpio_pin_mask, disable_interface_mask); } +#ifdef __cplusplus +} +#endif + +#endif // !__ASSEMBLER__ #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt new file mode 100644 index 00000000000..17b4042bd4c --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt @@ -0,0 +1,10 @@ +pico_add_impl_library(pico_bootsel_via_double_reset) + +target_sources(pico_bootsel_via_double_reset INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/pico_bootsel_via_double_reset.c + ) + +target_link_libraries(pico_bootsel_via_double_reset INTERFACE + pico_bootrom + pico_time + ) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c new file mode 100644 index 00000000000..d333ab2ff4d --- /dev/null +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "pico/time.h" +#include "pico/bootrom.h" +#include "pico/binary_info.h" + +// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS, Window of opportunity for a second press of a reset button to enter BOOTSEL mode (milliseconds), type=int, default=200, group=pico_bootsel_via_double_reset +#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS +#define PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS 200 +#endif + +// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via reset double tap, type=int, min=0, max=29, group=pico_bootsel_via_double_reset + +// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via double reset, type=int, min=0, max=3, default=0, group=pico_bootsel_via_double_reset +#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK +#define PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK 0u +#endif + +/** \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset + * + * When the 'pico_bootsel_via_double_reset' library is linked, a function is + * injected before main() which will detect when the system has been reset + * twice in quick succession, and enter the USB ROM bootloader (BOOTSEL mode) + * when this happens. This allows a double tap of a reset button on a + * development board to be used to enter the ROM bootloader, provided this + * library is always linked. + */ + +#if !PICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET +bi_decl(bi_program_feature("double reset -> BOOTSEL")); +#endif + +// Doesn't make any sense for a RAM only binary +#if !PICO_NO_FLASH +static const uint32_t magic_token[] = { + 0xf01681de, 0xbd729b29, 0xd359be7a, +}; + +static uint32_t __uninitialized_ram(magic_location)[count_of(magic_token)]; + +/* Check for double reset and enter BOOTSEL mode if detected + * + * This function is registered to run automatically before main(). The + * algorithm is: + * + * 1. Check for magic token in memory; enter BOOTSEL mode if found. + * 2. Initialise that memory with that magic token. + * 3. Do nothing for a short while (few hundred ms). + * 4. Clear the magic token. + * 5. Continue with normal boot. + * + * Resetting the device twice quickly will interrupt step 3, leaving the token + * in place so that the second boot will go to the bootloader. + */ +static void __attribute__((constructor)) boot_double_tap_check(void) { + for (uint i = 0; i < count_of(magic_token); i++) { + if (magic_location[i] != magic_token[i]) { + // Arm, wait, then disarm and continue booting + for (i = 0; i < count_of(magic_token); i++) { + magic_location[i] = magic_token[i]; + } + busy_wait_us(PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS * 1000); + magic_location[0] = 0; + return; + } + } + // Detected a double reset, so enter USB bootloader + magic_location[0] = 0; +#ifdef PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED + const uint32_t led_mask = 1u << PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED; +#else + const uint32_t led_mask = 0u; +#endif + reset_usb_boot( + led_mask, + PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK + ); +} + +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt index 9eda2355633..ceed04275a9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/CMakeLists.txt @@ -1,12 +1,9 @@ if (NOT TARGET pico_divider) # library to be depended on - we make this depend on particular implementations using per target generator expressions - add_library(pico_divider INTERFACE) + pico_add_impl_library(pico_divider) # no custom implementation; falls thru to compiler - add_library(pico_divider_compiler INTERFACE) - target_compile_definitions(pico_divider_compiler INTERFACE - PICO_DIVIDER_COMPILER=1 - ) + pico_add_impl_library(pico_divider_compiler) # add alias "default" which is just hardware. add_library(pico_divider_default INTERFACE) @@ -24,13 +21,11 @@ if (NOT TARGET pico_divider) target_link_libraries(pico_divider_hardware_explicit INTERFACE pico_divider_headers + hardware_divider hardware_regs ) - add_library(pico_divider_hardware INTERFACE) - target_compile_definitions(pico_divider_hardware INTERFACE - PICO_DIVIDER_HARDWARE=1 - ) + pico_add_impl_library(pico_divider_hardware) target_link_libraries(pico_divider_hardware INTERFACE pico_divider_hardware_explicit) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S index 12eae389959..234c1a472b7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S @@ -4,23 +4,28 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "hardware/regs/sio.h" #include "hardware/regs/addressmap.h" +#include "hardware/divider_helper.S" .syntax unified .cpu cortex-m0plus .thumb +// PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider + #include "pico/asm_helper.S" +// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider #ifndef PICO_DIVIDER_CALL_IDIV0 #define PICO_DIVIDER_CALL_IDIV0 1 #endif +// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 64 bit division by zero should call __aeabi_ldiv0, default=1, group=pico_divider #ifndef PICO_DIVIDER_CALL_LDIV0 #define PICO_DIVIDER_CALL_LDIV0 1 #endif +// PICO_CONFIG: PICO_DIVIDER_IN_RAM, Whether divider functions should be placed in RAM, default=0, group=pico_divider .macro div_section name #if PICO_DIVIDER_IN_RAM .section RAM_SECTION_NAME(\name), "ax" @@ -29,17 +34,6 @@ #endif .endm -#if SIO_DIV_CSR_READY_LSB == 0 -.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 -#else -need to change SHIFT above -#endif -#if SIO_DIV_CSR_DIRTY_LSB == 1 -.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2 -#else -need to change SHIFT above -#endif - @ wait 8-n cycles for the hardware divider .macro wait_div n .rept (8-\n) / 2 @@ -51,56 +45,17 @@ need to change SHIFT above .endif .endm - #if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4) #error register layout has changed - we rely on this order to make sure we save/restore in the right order #endif -# SIO_BASE ptr in r2 -.macro save_div_state_and_lr - ldr r3, [r2, #SIO_DIV_CSR_OFFSET] - # wait for results as we can't save signed-ness of operation -1: - lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY - bcc 1b - push {r4, r5, r6, r7, lr} - // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! - ldr r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] - ldr r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] - ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] - ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] -.endm - -.macro restore_div_state_and_return - // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order - // - // it is worth considering what happens if we are interrupted - // - // after writing r4: we are DIRTY and !READY - // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be - // saved/restored correctly and we'll restore the rest ourselves - // after writing r4, r5: we are DIRTY and !READY - // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor - // at least will be saved/restored correctly and and we'll restore the rest ourselves - // after writing r4, r5, r6: we are DIRTY and READY - // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), - // and we'll restore the remainder after the fact - - // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space - // and so 4 reads is cheaper (and we don't have to adjust r2) - str r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] - str r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] - str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] - str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] - pop {r4, r5, r6, r7, pc} -.endm - +#if !PICO_DIVIDER_DISABLE_INTERRUPTS .macro save_div_state_and_lr_64 push {r4, r5, r6, r7, lr} ldr r6, =SIO_BASE 1: ldr r5, [r6, #SIO_DIV_CSR_OFFSET] - # wait for results as we can't save signed-ness of operation + // wait for results as we can't save signed-ness of operation lsrs r5, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY bcc 1b // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! @@ -137,6 +92,7 @@ need to change SHIFT above pop {r4, r5, r6, r7, pc} .endm +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ // since idiv and idivmod only differ by a cycle, we'll make them the same! div_section WRAPPER_FUNC_NAME(__aeabi_idiv) @@ -145,12 +101,23 @@ wrapper_func __aeabi_idiv wrapper_func __aeabi_idivmod regular_func div_s32s32 regular_func divmod_s32s32 +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty ldr r2, =(SIO_BASE) - # to support IRQ usage we must save/restore ldr r3, [r2, #SIO_DIV_CSR_OFFSET] lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY bcs divmod_s32s32_savestate regular_func divmod_s32s32_unsafe +#else +// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs +// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there +// are the hardware_divider functions that can be used instead anyway +regular_func divmod_s32s32_unsafe + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + ldr r2, =(SIO_BASE) + mrs r3, PRIMASK + cpsid i +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET] str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET] cmp r1, #0 @@ -159,8 +126,14 @@ regular_func divmod_s32s32_unsafe // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] +#if PICO_DIVIDER_DISABLE_INTERRUPTS + msr PRIMASK, r3 +#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ bx lr 1: +#if PICO_DIVIDER_DISABLE_INTERRUPTS + msr PRIMASK, r3 +#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ push {r2, lr} movs r1, #0x80 lsls r1, #24 @@ -176,11 +149,15 @@ regular_func divmod_s32s32_unsafe movs r1, #0 // remainder 0 // need to restore saved r2 as it hold SIO ptr pop {r2, pc} +#if !PICO_DIVIDER_DISABLE_INTERRUPTS .align 2 regular_func divmod_s32s32_savestate + // note that we must be at least 2 cycles into division at this point, + // which we are because of the firty check before getting here (and of course the function call before that) save_div_state_and_lr bl divmod_s32s32_unsafe restore_div_state_and_return +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ // since uidiv and uidivmod only differ by a cycle, we'll make them the same! div_section WRAPPER_FUNC_NAME(__aeabi_uidiv) @@ -188,12 +165,23 @@ regular_func div_u32u32 regular_func divmod_u32u32 wrapper_func __aeabi_uidiv wrapper_func __aeabi_uidivmod +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty ldr r2, =(SIO_BASE) - # to support IRQ usage we must save/restore ldr r3, [r2, #SIO_DIV_CSR_OFFSET] lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY bcs divmod_u32u32_savestate regular_func divmod_u32u32_unsafe +#else +// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs +// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there +// are the hardware_divider functions that can be used instead anyway +regular_func divmod_u32u32_unsafe + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + ldr r2, =(SIO_BASE) + mrs r3, PRIMASK + cpsid i +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET] str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET] cmp r1, #0 @@ -202,8 +190,14 @@ regular_func divmod_u32u32_unsafe // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] +#if PICO_DIVIDER_DISABLE_INTERRUPTS + msr PRIMASK, r3 +#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ bx lr 1: +#if PICO_DIVIDER_DISABLE_INTERRUPTS + msr PRIMASK, r3 +#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ push {r2, lr} cmp r0, #0 beq 1f @@ -216,11 +210,13 @@ regular_func divmod_u32u32_unsafe movs r1, #0 // remainder 0 // need to restore saved r2 as it hold SIO ptr pop {r2, pc} +#if !PICO_DIVIDER_DISABLE_INTERRUPTS .align 2 regular_func divmod_u32u32_savestate save_div_state_and_lr bl divmod_u32u32_unsafe restore_div_state_and_return +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) @@ -228,9 +224,10 @@ div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) wrapper_func __aeabi_ldivmod regular_func div_s64s64 regular_func divmod_s64s64 +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty mov ip, r2 ldr r2, =(SIO_BASE) - # to support IRQ usage we must save/restore ldr r2, [r2, #SIO_DIV_CSR_OFFSET] lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY mov r2, ip @@ -241,14 +238,24 @@ divmod_s64s64_savestate: save_div_state_and_lr_64 bl divmod_s64s64_unsafe restore_div_state_and_return_64 +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl divmod_s64s64_unsafe + msr PRIMASK, r4 + pop {r4, pc} +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ .align 2 wrapper_func __aeabi_uldivmod regular_func div_u64u64 regular_func divmod_u64u64 +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty mov ip, r2 ldr r2, =(SIO_BASE) - # to support IRQ usage we must save/restore ldr r2, [r2, #SIO_DIV_CSR_OFFSET] lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY mov r2, ip @@ -259,6 +266,16 @@ regular_func divmod_u64u64_savestate save_div_state_and_lr_64 bl divmod_u64u64_unsafe restore_div_state_and_return_64 +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl divmod_u64u64_unsafe + msr PRIMASK, r4 + pop {r4, pc} +#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ + .macro dneg lo,hi mvns \hi,\hi rsbs \lo,#0 @@ -396,6 +413,7 @@ y64: lsls r3,#16 orrs r3,r4 str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16); + str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty wait_div 1 uxth r4,r0 ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1>16); + str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty wait_div 3 movs r3,#0 lsls r4,r5,#16 @ quotient=(q0<<32)+(q1<<16)+q2 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt index a707385aa48..efe1b63bbc1 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/CMakeLists.txt @@ -1,13 +1,9 @@ if (NOT TARGET pico_double) # library to be depended on - we make this depend on particular implementations using per target generator expressions - add_library(pico_double INTERFACE) + pico_add_impl_library(pico_double) # no custom implementation; falls thru to compiler - add_library(pico_double_compiler INTERFACE) - # PICO_BUILD_DEFINE: PICO_DOUBLE_COMPILER, whether compiler provided double support is being used, type=bool, default=0, but dependent on CMake options, group=pico_double - target_compile_definitions(pico_double_compiler INTERFACE - PICO_DOUBLE_COMPILER=1 - ) + pico_add_impl_library(pico_double_compiler) add_library(pico_double_headers INTERFACE) target_include_directories(pico_double_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) @@ -21,30 +17,24 @@ if (NOT TARGET pico_double) target_link_libraries(pico_double INTERFACE $>,$,${PICO_DEFAULT_DOUBLE_IMPL}>) - add_library(pico_double_pico INTERFACE) + pico_add_impl_library(pico_double_pico) target_sources(pico_double_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/double_aeabi.S ${CMAKE_CURRENT_LIST_DIR}/double_init_rom.c ${CMAKE_CURRENT_LIST_DIR}/double_math.c ${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim.S ) - # PICO_BUILD_DEFINE: PICO_DOUBLE_PICO, whether optimized pico/bootrom provided double support is being used, type=bool, default=1, but dependent on CMake options, group=pico_double - target_compile_definitions(pico_double_pico INTERFACE - PICO_DOUBLE_PICO=1 - ) target_link_libraries(pico_double_pico INTERFACE pico_bootrom pico_double_headers) - add_library(pico_double_none INTERFACE) + pico_add_impl_library(pico_double_none) target_sources(pico_double_none INTERFACE ${CMAKE_CURRENT_LIST_DIR}/double_none.S ) target_link_libraries(pico_double_none INTERFACE pico_double_headers) - # PICO_BUILD_DEFINE: PICO_DOUBLE_NONE, whether double support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_double target_compile_definitions(pico_double_none INTERFACE - PICO_DOUBLE_NONE=1 PICO_PRINTF_SUPPORT_FLOAT=0 # printing floats/doubles won't work, so we can save space by removing it ) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S index 4ef7748e9a8..0c597384163 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_aeabi.S @@ -6,6 +6,7 @@ #include "pico/asm_helper.S" #include "pico/bootrom/sf_table.h" +#include "hardware/divider_helper.S" __pre_init __aeabi_double_init, 00020 @@ -82,7 +83,7 @@ __check_nan_d2: .macro table_tail_call SF_TABLE_OFFSET push {r3, r4} -#if PICO_DOUBLE_SUPPORT_ROM_V1 +#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED #ifndef NDEBUG movs r3, #0 mov ip, r3 @@ -98,12 +99,12 @@ __check_nan_d2: push {r3, r4} ldr r3, =sd_table ldr r3, [r3, #\SF_TABLE_OFFSET] -#if PICO_DOUBLE_SUPPORT_ROM_V1 +#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED mov ip, pc #endif str r3, [sp, #4] pop {r3, pc} -#if PICO_DOUBLE_SUPPORT_ROM_V1 +#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED .byte \SF_TABLE_OFFSET, 0xdf .word \shim #endif @@ -131,16 +132,16 @@ regular_func pop_r8_r11 mov r11,r7 bx r14 -# note generally each function is in a separate section unless there is fall thru or branching between them -# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool +// note generally each function is in a separate section unless there is fall thru or branching between them +// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool -# note functions are word aligned except where they are an odd number of linear instructions +// note functions are word aligned except where they are an odd number of linear instructions // double FUNC_NAME(__aeabi_dadd)(double, double) double-precision addition double_wrapper_section __aeabi_darithmetic // double FUNC_NAME(__aeabi_drsub)(double x, double y) double-precision reverse subtraction, y - x -# frsub first because it is the only one that needs alignment +// frsub first because it is the only one that needs alignment .align 2 wrapper_func __aeabi_drsub eors r0, r1 @@ -177,7 +178,35 @@ wrapper_func_d2 __aeabi_ddiv b ddiv_dsub_nan_helper 1: #endif - shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty + mov ip, r2 + ldr r2, =(SIO_BASE) + ldr r2, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs ddiv_save_state + mov r2, ip +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl ddiv_shim_call + msr PRIMASK, r4 + pop {r4, pc} +#endif +ddiv_shim_call: + shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim + +#if !PICO_DIVIDER_DISABLE_INTERRUPTS +ddiv_save_state: + ldr r2, =(SIO_BASE) + save_div_state_and_lr + mov r2, ip + bl ddiv_shim_call + ldr r2, =(SIO_BASE) + restore_div_state_and_return +#endif ddiv_dsub_nan_helper: #if PICO_DOUBLE_PROPAGATE_NANS @@ -592,6 +621,8 @@ regular_func sincostan_remainder ldr r2, =0x54442D18 // 2 * M_PI ldr r3, =0x401921FB push {lr} + // note remainder only uses the divider thru integer divider functions + // which save and restore themselves bl remainder pop {pc} @@ -677,7 +708,7 @@ double_wrapper_section sincos bl sincostan_remainder pop {r2} mov lr, r2 - b 1f + b 1f // continue with sincos wrapper_func sincos push {r2-r5, lr} @@ -688,8 +719,7 @@ wrapper_func sincos cmp r2, #9 bge 2b 1: - - bl 2f + bl 2f // call the shim pop {r4-r5} stmia r4!, {r0, r1} stmia r5!, {r2, r3} @@ -697,22 +727,13 @@ wrapper_func sincos 2: shimmable_table_tail_call SF_TABLE_V3_FSINCOS sincos_shim_bootstrap -#if PICO_DOUBLE_PROPAGATE_NANS -.align 2 -1: - pop {r2, r3} - stmia r2!, {r0, r1} - mov lr, r3 - pop {r3} - stmia r3!, {r0, r1} - bx lr -#endif + .thumb_func sincos_shim_bootstrap: push {r2, r3, r4} movs r3, #0x13 ldrb r3, [r3] -#if PICO_DOUBLE_SUPPORT_ROM_V1 +#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED cmp r3, #1 bne 1f ldr r3, =dsincos_shim @@ -762,13 +783,40 @@ double_wrapper_section tan wrapper_func tan // rom version only works for -1024 < angle < 1024 lsls r2, r1, #2 - bcc 1f + bcc dtan_in_range lsrs r2, #22 cmp r2, #9 - bge 2f -1: + bge dtan_angle_out_of_range +dtan_in_range: +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty + mov ip, r2 + ldr r2, =(SIO_BASE) + ldr r2, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs dtan_save_state + mov r2, ip +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl dtan_shim_call + msr PRIMASK, r4 + pop {r4, pc} +#endif +dtan_shim_call: shimmable_table_tail_call SF_TABLE_FTAN dtan_shim -2: +#if !PICO_DIVIDER_DISABLE_INTERRUPTS +dtan_save_state: + ldr r2, =(SIO_BASE) + save_div_state_and_lr + mov r2, ip + bl dtan_shim_call + ldr r2, =(SIO_BASE) + restore_div_state_and_return +#endif +dtan_angle_out_of_range: #if PICO_DOUBLE_PROPAGATE_NANS lsls r2, r1, #1 asrs r2, #21 @@ -785,7 +833,7 @@ wrapper_func tan bl sincostan_remainder pop {r2} mov lr, r2 - b 1b + b dtan_in_range double_wrapper_section atan2 wrapper_func_d2 atan2 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c index 82950b41500..af6f6a2c3be 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_init_rom.c @@ -12,16 +12,18 @@ // IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE uint32_t sd_table[SF_TABLE_V2_SIZE / 2]; -#if !PICO_DOUBLE_SUPPORT_ROM_V1 -static __attribute__((noreturn)) void missing_double_func_shim() { +#if !(PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED) +static __attribute__((noreturn)) void missing_double_func_shim(void) { panic("missing double function"); } #endif -extern void double_table_shim_on_use_helper(); +extern void double_table_shim_on_use_helper(void); -void __aeabi_double_init() { +void __attribute__((weak)) *sf_clz_func; + +void __aeabi_double_init(void) { int rom_version = rp2040_rom_version(); -#if PICO_DOUBLE_SUPPORT_ROM_V1 +#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED if (rom_version == 1) { // this is a little tricky.. we only want to pull in a shim if the corresponding function @@ -63,4 +65,6 @@ void __aeabi_double_init() { // we use the unused entry for SINCOS sd_table[SF_TABLE_V3_FSINCOS / 4] = (uintptr_t) double_table_shim_on_use_helper; } + + sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c index 41d4380e7c8..6c35ded4ad2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_double/double_math.c @@ -9,6 +9,11 @@ #include "pico/double.h" #include "pico/platform.h" +// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all +_Pragma("GCC diagnostic push") +_Pragma("GCC diagnostic ignored \"-Wconversion\"") +_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"") + typedef uint64_t ui64; typedef uint32_t ui32; typedef int64_t i64; @@ -36,11 +41,25 @@ typedef int64_t i64; #define DUNPACK(x,e,m) e=((x)>>52)&0x7ff,m=((x)&0x000fffffffffffffULL)|0x0010000000000000ULL #define DUNPACKS(x,s,e,m) s=((x)>>63),DUNPACK((x),(e),(m)) -_Pragma("GCC diagnostic push") -_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"") +typedef union { + double d; + ui64 ix; +} double_ui64; + +static inline double ui642double(ui64 ix) { + double_ui64 tmp; + tmp.ix = ix; + return tmp.d; +} + +static inline ui64 double2ui64(double d) { + double_ui64 tmp; + tmp.d = d; + return tmp.ix; +} static inline bool disnan(double x) { - ui64 ix=*(i64*)&x; + ui64 ix= double2ui64(x); // checks the top bit of the low 32 bit of the NAN, but it I think that is ok return ((uint32_t)(ix >> 31)) > 0xffe00000u; } @@ -54,17 +73,17 @@ static inline bool disnan(double x) { #endif static inline int dgetsignexp(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); return (ix>>52)&0xfff; } static inline int dgetexp(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); return (ix>>52)&0x7ff; } static inline double dldexp(double x,int de) { - ui64 ix=*(ui64*)&x,iy; + ui64 ix=double2ui64(x),iy; int e; e=dgetexp(x); if(e==0||e==0x7ff) return x; @@ -72,7 +91,7 @@ static inline double dldexp(double x,int de) { if(e<=0) iy=ix&0x8000000000000000ULL; // signed zero for underflow else if(e>=0x7ff) iy=(ix&0x8000000000000000ULL)|0x7ff0000000000000ULL; // signed infinity on overflow else iy=ix+((ui64)de<<52); - return *(double*)&iy; + return ui642double(iy); } double WRAPPER_FUNC(ldexp)(double x, int de) { @@ -82,9 +101,9 @@ double WRAPPER_FUNC(ldexp)(double x, int de) { static inline double dcopysign(double x,double y) { - ui64 ix=*(ui64*)&x,iy=*(ui64*)&y; + ui64 ix=double2ui64(x),iy=double2ui64(y); ix=((ix&0x7fffffffffffffffULL)|(iy&0x8000000000000000ULL)); - return *(double*)&ix; + return ui642double(ix); } double WRAPPER_FUNC(copysign)(double x, double y) { @@ -99,7 +118,7 @@ static inline int dispinf(double x) { return dgetsignexp(x)==0x7ff; } static inline int disminf(double x) { return dgetsignexp(x)==0xfff; } static inline int disint(double x) { - ui64 ix=*(ui64*)&x,m; + ui64 ix=double2ui64(x),m; int e=dgetexp(x); if(e==0) return 1; // 0 is an integer e-=0x3ff; // remove exponent bias @@ -112,7 +131,7 @@ static inline int disint(double x) { } static inline int disoddint(double x) { - ui64 ix=*(ui64*)&x,m; + ui64 ix=double2ui64(x),m; int e=dgetexp(x); e-=0x3ff; // remove exponent bias if(e<0) return 0; // |x|<1; 0 is not odd @@ -125,24 +144,24 @@ static inline int disoddint(double x) { } static inline int disstrictneg(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); if(diszero(x)) return 0; return ix>>63; } static inline int disneg(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); return ix>>63; } static inline double dneg(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); ix^=0x8000000000000000ULL; - return *(double*)&ix; + return ui642double(ix); } static inline int dispo2(double x) { - ui64 ix=*(ui64*)&x; + ui64 ix=double2ui64(x); if(diszero(x)) return 0; if(disinf(x)) return 0; ix&=0x000fffffffffffffULL; @@ -159,33 +178,33 @@ static inline double dnan_or(double x) { double WRAPPER_FUNC(trunc)(double x) { check_nan_d1(x); - ui64 ix=*(ui64*)&x,m; + ui64 ix=double2ui64(x),m; int e=dgetexp(x); e-=0x3ff; // remove exponent bias if(e<0) { // |x|<1 ix&=0x8000000000000000ULL; - return *(double*)&ix; + return ui642double(ix); } e=52-e; // bit position in mantissa with significance 1 if(e<=0) return x; // |x| large, so must be an integer m=(1ULL<>,$,${PICO_DEFAULT_FLOAT_IMPL}>) - add_library(pico_float_pico INTERFACE) + pico_add_impl_library(pico_float_pico) target_sources(pico_float_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/float_aeabi.S ${CMAKE_CURRENT_LIST_DIR}/float_init_rom.c ${CMAKE_CURRENT_LIST_DIR}/float_math.c ${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim.S ) - # PICO_BUILD_DEFINE: PICO_FLOAT_PICO, whether optimized pico/bootrom provided float support is being used, type=bool, default=1, but dependent on CMake options, group=pico_float - target_compile_definitions(pico_float_pico INTERFACE - PICO_FLOAT_PICO=1 - ) target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers) - add_library(pico_float_none INTERFACE) + pico_add_impl_library(pico_float_none) target_sources(pico_float_none INTERFACE ${CMAKE_CURRENT_LIST_DIR}/float_none.S ) target_link_libraries(pico_float_none INTERFACE pico_float_headers) - # PICO_BUILD_DEFINE: PICO_FLOAT_NONE, whether float support is disabled and functions will panic, type=bool, default=0, but dependent on CMake options, group=pico_float - target_compile_definitions(pico_float_none INTERFACE - PICO_FLOAT_NONE=1 - ) - function(wrap_float_functions TARGET) pico_wrap_function(${TARGET} __aeabi_fadd) pico_wrap_function(${TARGET} __aeabi_fdiv) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S index 2aee5f250ad..db393dfa38b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_aeabi.S @@ -6,6 +6,7 @@ #include "pico/asm_helper.S" #include "pico/bootrom/sf_table.h" +#include "hardware/divider_helper.S" __pre_init __aeabi_float_init, 00020 @@ -79,7 +80,7 @@ __check_nan_f2: #endif .macro table_tail_call SF_TABLE_OFFSET -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED #ifndef NDEBUG movs r3, #0 mov ip, r3 @@ -93,27 +94,27 @@ __check_nan_f2: .macro shimmable_table_tail_call SF_TABLE_OFFSET shim ldr r3, =sf_table ldr r3, [r3, #\SF_TABLE_OFFSET] -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED mov ip, pc #endif bx r3 -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED .byte \SF_TABLE_OFFSET, 0xdf .word \shim #endif .endm -# note generally each function is in a separate section unless there is fall thru or branching between them -# note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool +// note generally each function is in a separate section unless there is fall thru or branching between them +// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool -# note functions are word aligned except where they are an odd number of linear instructions +// note functions are word aligned except where they are an odd number of linear instructions // float FUNC_NAME(__aeabi_fadd)(float, float) single-precision addition float_wrapper_section __aeabi_farithmetic // float FUNC_NAME(__aeabi_frsub)(float x, float y) single-precision reverse subtraction, y - x -# frsub first because it is the only one that needs alignment +// frsub first because it is the only one that needs alignment .align 2 wrapper_func __aeabi_frsub eors r0, r1 @@ -146,7 +147,30 @@ wrapper_func_f2 __aeabi_fdiv b fdiv_fsub_nan_helper 1: #endif +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty + ldr r2, =(SIO_BASE) + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs fdiv_save_state +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl fdiv_shim_call + msr PRIMASK, r4 + pop {r4, pc} +#endif +fdiv_shim_call: table_tail_call SF_TABLE_FDIV +#if !PICO_DIVIDER_DISABLE_INTERRUPTS +fdiv_save_state: + save_div_state_and_lr + bl fdiv_shim_call + ldr r2, =(SIO_BASE) + restore_div_state_and_return +#endif fdiv_fsub_nan_helper: #if PICO_FLOAT_PROPAGATE_NANS @@ -560,13 +584,13 @@ wrapper_func __aeabi_f2d float_wrapper_section srqtf wrapper_func_f1 sqrtf -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED // check for negative asrs r1, r0, #23 bmi 1f #endif table_tail_call SF_TABLE_FSQRT -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED 1: mvns r0, r1 cmp r0, #255 @@ -689,10 +713,33 @@ wrapper_func tanf lsls r1, r0, #1 lsrs r1, #24 cmp r1, #127 + 7 - bge 1f -2: + bge ftan_out_of_range +ftan_in_range: +#if !PICO_DIVIDER_DISABLE_INTERRUPTS + // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty + ldr r2, =(SIO_BASE) + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY + bcs ftan_save_state +#else + // to avoid worrying about IRQs (or context switches), simply disable interrupts around call + push {r4, lr} + mrs r4, PRIMASK + cpsid i + bl ftan_shim_call + msr PRIMASK, r4 + pop {r4, pc} +#endif +ftan_shim_call: table_tail_call SF_TABLE_FTAN -1: +#if !PICO_DIVIDER_DISABLE_INTERRUPTS +ftan_save_state: + save_div_state_and_lr + bl ftan_shim_call + ldr r2, =(SIO_BASE) + restore_div_state_and_return +#endif +ftan_out_of_range: #if PICO_FLOAT_PROPAGATE_NANS // also check for infinites cmp r1, #255 @@ -709,7 +756,7 @@ wrapper_func tanf bl remainderf pop {r1} mov lr, r1 - b 2b + b ftan_in_range float_wrapper_section atan2f wrapper_func_f2 atan2f diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c index 3dbefa67465..646c0e9403b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_init_rom.c @@ -11,21 +11,21 @@ // NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE... // IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE uint32_t sf_table[SF_TABLE_V2_SIZE / 2]; -void *sf_clz_func; +void __attribute__((weak)) *sf_clz_func; -#if !PICO_FLOAT_SUPPORT_ROM_V1 -static __attribute__((noreturn)) void missing_float_func_shim() { +#if !(PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED) +static __attribute__((noreturn)) void missing_float_func_shim(void) { panic(""); } #endif -void __aeabi_float_init() { +void __aeabi_float_init(void) { int rom_version = rp2040_rom_version(); void *rom_table = rom_data_lookup(rom_table_code('S', 'F')); -#if PICO_FLOAT_SUPPORT_ROM_V1 +#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED if (rom_version == 1) { memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE); - extern void float_table_shim_on_use_helper(); + extern void float_table_shim_on_use_helper(void); // todo replace NDEBUG with a more exclusive assertion guard #ifndef NDEBUG if (*(uint16_t *)0x29ee != 0x0fc4 || // this is packx @@ -66,5 +66,5 @@ void __aeabi_float_init() { assert(*((uint8_t *)(rom_table-2)) * 4 >= SF_TABLE_V2_SIZE); memcpy(&sf_table, rom_table, SF_TABLE_V2_SIZE); } - sf_clz_func = rom_func_lookup(rom_table_code('L', '3')); + sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c index e54c8688039..a48a2d72420 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/float_math.c @@ -8,11 +8,16 @@ #include "pico/float.h" #include "pico/platform.h" +// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all +_Pragma("GCC diagnostic push") +_Pragma("GCC diagnostic ignored \"-Wconversion\"") +_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"") + typedef uint32_t ui32; typedef int32_t i32; -#define PINF ( HUGE_VAL) -#define MINF (-HUGE_VAL) +#define FPINF ( HUGE_VALF) +#define FMINF (-HUGE_VALF) #define NANF ((float)NAN) #define PZERO (+0.0) #define MZERO (-0.0) @@ -34,11 +39,25 @@ typedef int32_t i32; #define FUNPACK(x,e,m) e=((x)>>23)&0xff,m=((x)&0x007fffff)|0x00800000 #define FUNPACKS(x,s,e,m) s=((x)>>31),FUNPACK((x),(e),(m)) -_Pragma("GCC diagnostic push") -_Pragma("GCC diagnostic ignored \"-Wstrict-aliasing\"") +typedef union { + float f; + ui32 ix; +} float_ui32; + +static inline float ui322float(ui32 ix) { + float_ui32 tmp; + tmp.ix = ix; + return tmp.f; +} + +static inline ui32 float2ui32(float f) { + float_ui32 tmp; + tmp.f = f; + return tmp.ix; +} static inline bool fisnan(float x) { - ui32 ix=*(i32*)&x; + ui32 ix=float2ui32(x); return ix * 2 > 0xff000000u; } @@ -51,17 +70,17 @@ static inline bool fisnan(float x) { #endif static inline int fgetsignexp(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); return (ix>>23)&0x1ff; } static inline int fgetexp(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); return (ix>>23)&0xff; } static inline float fldexp(float x,int de) { - ui32 ix=*(ui32*)&x,iy; + ui32 ix=float2ui32(x),iy; int e; e=fgetexp(x); if(e==0||e==0xff) return x; @@ -69,7 +88,7 @@ static inline float fldexp(float x,int de) { if(e<=0) iy=ix&0x80000000; // signed zero for underflow else if(e>=0xff) iy=(ix&0x80000000)|0x7f800000ULL; // signed infinity on overflow else iy=ix+((ui32)de<<23); - return *(float*)&iy; + return ui322float(iy); } float WRAPPER_FUNC(ldexpf)(float x, int de) { @@ -78,9 +97,9 @@ float WRAPPER_FUNC(ldexpf)(float x, int de) { } static inline float fcopysign(float x,float y) { - ui32 ix=*(ui32*)&x,iy=*(ui32*)&y; + ui32 ix=float2ui32(x),iy=float2ui32(y); ix=((ix&0x7fffffff)|(iy&0x80000000)); - return *(float*)&ix; + return ui322float(ix); } float WRAPPER_FUNC(copysignf)(float x, float y) { @@ -96,7 +115,7 @@ static inline int fispinf(float x) { return fgetsignexp(x)==0xff; } static inline int fisminf(float x) { return fgetsignexp(x)==0x1ff; } static inline int fisint(float x) { - ui32 ix=*(ui32*)&x,m; + ui32 ix=float2ui32(x),m; int e=fgetexp(x); if(e==0) return 1; // 0 is an integer e-=0x7f; // remove exponent bias @@ -109,7 +128,7 @@ static inline int fisint(float x) { } static inline int fisoddint(float x) { - ui32 ix=*(ui32*)&x,m; + ui32 ix=float2ui32(x),m; int e=fgetexp(x); e-=0x7f; // remove exponent bias if(e<0) return 0; // |x|<1; 0 is not odd @@ -122,24 +141,24 @@ static inline int fisoddint(float x) { } static inline int fisstrictneg(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); if(fiszero(x)) return 0; return ix>>31; } static inline int fisneg(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); return ix>>31; } static inline float fneg(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); ix^=0x80000000; - return *(float*)&ix; + return ui322float(ix); } static inline int fispo2(float x) { - ui32 ix=*(ui32*)&x; + ui32 ix=float2ui32(x); if(fiszero(x)) return 0; if(fisinf(x)) return 0; ix&=0x007fffff; @@ -156,33 +175,33 @@ static inline float fnan_or(float x) { float WRAPPER_FUNC(truncf)(float x) { check_nan_f1(x); - ui32 ix=*(ui32*)&x,m; + ui32 ix=float2ui32(x),m; int e=fgetexp(x); e-=0x7f; // remove exponent bias if(e<0) { // |x|<1 ix&=0x80000000; - return *(float*)&ix; + return ui322float(ix); } e=23-e; // bit position in mantissa with significance 1 if(e<=0) return x; // |x| large, so must be an integer m=(1<0) { - if((y&1)) return MINF; - else return PINF; + if((y&1)) return FMINF; + else return FPINF; } if((y&1)) return MZERO; else return PZERO; @@ -420,31 +439,31 @@ float WRAPPER_FUNC(powf)(float x,float y) { if(fisoddint(y)) return x; else return 0; } - if(fisoddint(y)) return fcopysign(PINF,x); - return PINF; + if(fisoddint(y)) return fcopysign(FPINF,x); + return FPINF; } if(fispinf(x)) { if(fisneg(y)) return 0; - else return PINF; + else return FPINF; } if(fisminf(x)) { if(!fisneg(y)) { - if(fisoddint(y)) return MINF; - else return PINF; + if(fisoddint(y)) return FMINF; + else return FPINF; } if(fisoddint(y)) return MZERO; else return PZERO; } if(fispinf(y)) { if(fgetexp(x)<0x7f) return PZERO; - else return PINF; + else return FPINF; } if(fisminf(y)) { - if(fgetexp(x)<0x7f) return PINF; + if(fgetexp(x)<0x7f) return FPINF; else return PZERO; } if(fisint(y)) return fpow_0(x,y); - if(fisneg(x)) return PINF; + if(fisneg(x)) return FPINF; return fpow_1(x,y); } @@ -500,15 +519,15 @@ static i32 frem_0(i32 mx,i32 my,int e,int*pquo) { float WRAPPER_FUNC(fmodf)(float x,float y) { check_nan_f2(x,y); - ui32 ix=*(ui32*)&x,iy=*(ui32*)&y; + ui32 ix=float2ui32(x),iy=float2ui32(y); int sx,ex,ey; i32 mx,my; FUNPACKS(ix,sx,ex,mx); FUNPACK(iy,ey,my); if(ex==0xff) { - return fnan_or(PINF); + return fnan_or(FPINF); } - if(ey==0) return PINF; + if(ey==0) return FPINF; if(ex==0) { if(!fisneg(x)) return PZERO; return MZERO; @@ -521,14 +540,14 @@ float WRAPPER_FUNC(fmodf)(float x,float y) { float WRAPPER_FUNC(remquof)(float x,float y,int*quo) { check_nan_f2(x,y); - ui32 ix=*(ui32*)&x,iy=*(ui32*)&y; + ui32 ix=float2ui32(x),iy=float2ui32(y); int sx,sy,ex,ey,q; i32 mx,my; FUNPACKS(ix,sx,ex,mx); FUNPACKS(iy,sy,ey,my); if(quo) *quo=0; - if(ex==0xff) return PINF; - if(ey==0) return PINF; + if(ex==0xff) return FPINF; + if(ey==0) return FPINF; if(ex==0) return PZERO; if(ey==0xff) return x; if(ex>,$,${PICO_DEFAULT_INT64_OPS_IMPL}>) - add_library(pico_int64_ops_pico INTERFACE) + pico_add_impl_library(pico_int64_ops_pico) target_include_directories(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/pico_int64_ops_aeabi.S ) - # PICO_BUILD_DEFINE: PICO_INT64_OPS_PICO, whether optimized pico/bootrom provided int64_ops multiplication support is being used, type=bool, default=1, but dependent on CMake options, group=pico_int64_ops - target_compile_definitions(pico_int64_ops_pico INTERFACE - PICO_INT64_OPS_PICO=1 - ) - pico_wrap_function(pico_int64_ops_pico __aeabi_lmul) macro(pico_set_int64_ops_implementation TARGET IMPL) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S index 903820bff33..0dbc67cec63 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S @@ -10,7 +10,11 @@ #include "pico/asm_helper.S" +#if PICO_INT64_OPS_IN_RAM +.section RAM_SECTION_NAME(__aeabi_lmul) +#else .section SECTION_NAME(__aeabi_lmul) +#endif wrapper_func __aeabi_lmul muls r1, r2 muls r3, r0 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt index fddacc90c7a..deeb30f3f47 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/CMakeLists.txt @@ -1,11 +1,13 @@ if (NOT TARGET pico_malloc) #shims for ROM functions for -lgcc functions (listed below) - add_library(pico_malloc INTERFACE) + pico_add_impl_library(pico_malloc) target_sources(pico_malloc INTERFACE ${CMAKE_CURRENT_LIST_DIR}/pico_malloc.c ) + target_include_directories(pico_malloc INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + pico_wrap_function(pico_malloc malloc) pico_wrap_function(pico_malloc calloc) pico_wrap_function(pico_malloc free) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h index e84dd4d16cf..b4ae2b63688 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/include/pico/malloc.h @@ -16,7 +16,7 @@ */ // PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc -#if PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX) +#if LIB_PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX) #define PICO_USE_MALLOC_MUTEX 1 #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c index 548a48b9e08..4928a8e9a98 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_malloc/pico_malloc.c @@ -7,6 +7,7 @@ #include #include #include "pico.h" +#include "pico/malloc.h" #if PICO_USE_MALLOC_MUTEX #include "pico/mutex.h" @@ -19,7 +20,7 @@ extern void __real_free(void *mem); extern char __StackLimit; /* Set by linker. */ -static inline void check_alloc(void *mem, uint8_t size) { +static inline void check_alloc(__unused void *mem, __unused uint size) { #if PICO_MALLOC_PANIC if (!mem || (((char *)mem) + size) > &__StackLimit) { panic("Out of memory"); @@ -35,7 +36,7 @@ void *__wrap_malloc(size_t size) { #if PICO_USE_MALLOC_MUTEX mutex_exit(&malloc_mutex); #endif -#ifdef PICO_DEBUG_MALLOC +#if PICO_DEBUG_MALLOC if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size); } @@ -52,7 +53,7 @@ void *__wrap_calloc(size_t count, size_t size) { #if PICO_USE_MALLOC_MUTEX mutex_exit(&malloc_mutex); #endif -#ifdef PICO_DEBUG_MALLOC +#if PICO_DEBUG_MALLOC if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size); } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt index 20d410a361f..997bb207354 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/CMakeLists.txt @@ -1,13 +1,9 @@ if (NOT TARGET pico_mem_ops) #shims for ROM functions for -lgcc functions (listed below) - add_library(pico_mem_ops INTERFACE) + pico_add_impl_library(pico_mem_ops) # no custom implementation; falls thru to compiler - add_library(pico_mem_ops_compiler INTERFACE) - # PICO_BUILD_DEFINE: PICO_MEM_OPS_COMPILER, whether compiler provided mem_ops memcpy etc. support is being used, type=bool, default=0, but dependent on CMake options, group=pico_mem_ops - target_compile_definitions(pico_mem_ops_compiler INTERFACE - PICO_MEM_OPS_COMPILER=1 - ) + pico_add_impl_library(pico_mem_ops_compiler) # add alias "default" which is just pico. add_library(pico_mem_ops_default INTERFACE) @@ -15,16 +11,10 @@ if (NOT TARGET pico_mem_ops) set(PICO_DEFAULT_MEM_OPS_IMPL pico_mem_ops_default) - add_library(pico_mem_ops_pico INTERFACE) + pico_add_impl_library(pico_mem_ops_pico) target_link_libraries(pico_mem_ops INTERFACE $>,$,${PICO_DEFAULT_MEM_OPS_IMPL}>) - # PICO_BUILD_DEFINE: PICO_MEM_OPS_PICO, whether optimized pico/bootrom provided mem_ops memcpy etc. support is being used, type=bool, default=1, but dependent on CMake options, group=pico_mem_ops - target_compile_definitions(pico_mem_ops_pico INTERFACE - PICO_MEM_OPS_PICO=1 - ) - - target_sources(pico_mem_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/mem_ops_aeabi.S ) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S index e07a9feeec7..85409053342 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_mem_ops/mem_ops_aeabi.S @@ -9,6 +9,7 @@ .thumb #include "pico/asm_helper.S" +#include "pico/bootrom.h" __pre_init __aeabi_mem_init, 00001 @@ -34,10 +35,10 @@ __pre_init __aeabi_mem_init, 00001 .align 2 aeabi_mem_funcs: - .word rom_table_code('M','S') - .word rom_table_code('M','C') - .word rom_table_code('S','4') - .word rom_table_code('C','4') + .word ROM_FUNC_MEMSET + .word ROM_FUNC_MEMCPY + .word ROM_FUNC_MEMSET4 + .word ROM_FUNC_MEMCPY44 aeabi_mem_funcs_end: .section .text @@ -58,20 +59,20 @@ regular_func __aeabi_mem_init mem_section aeabi_memset_memcpy wrapper_func __aeabi_memset - // args are backwards - eors r0, r1 - eors r1, r0 - eors r0, r1 + // 2nd/3rd args are reversed + eors r2, r1 + eors r1, r2 + eors r2, r1 ldr r3, =aeabi_mem_funcs ldr r3, [r3, #MEMSET] bx r3 wrapper_func __aeabi_memset4 wrapper_func __aeabi_memset8 - // args are backwards - eors r0, r1 - eors r1, r0 - eors r0, r1 + // 2nd/3rd args are reversed + eors r2, r1 + eors r1, r2 + eors r2, r1 ldr r3, =aeabi_mem_funcs ldr r3, [r3, #MEMSET4] bx r3 diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt index 06f378230cd..240106156af 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/CMakeLists.txt @@ -1,16 +1,12 @@ if (NOT TARGET pico_multicore) - add_library(pico_multicore INTERFACE) + pico_add_impl_library(pico_multicore) target_sources(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/multicore.c) target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) - target_compile_definitions(pico_multicore INTERFACE - PICO_MULTICORE=1 - ) - - target_link_libraries(pico_multicore INTERFACE pico_sync) + target_link_libraries(pico_multicore INTERFACE pico_sync hardware_irq) endif() diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h index bc0c64d21f7..6f12f412b07 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h @@ -9,6 +9,7 @@ #include "pico/types.h" #include "pico/sync.h" +#include "hardware/structs/sio.h" #ifdef __cplusplus extern "C" { @@ -16,14 +17,14 @@ extern "C" { /** \file multicore.h * \defgroup pico_multicore pico_multicore - * Adds support for running code on the second processor core (core1) + * Adds support for running code on the second processor core (core 1) * * \subsection multicore_example Example * \addtogroup pico_multicore * \include multicore.c */ -// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE/0x800, group=pico_multicore +// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore #ifndef PICO_CORE1_STACK_SIZE #ifdef PICO_STACK_SIZE #define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE @@ -32,140 +33,276 @@ extern "C" { #endif #endif -/*! \brief Reset Core 1 +/*! \brief Reset core 1 * \ingroup pico_multicore * + * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods) + * + * \note this function should only be called from core 0 */ -void multicore_reset_core1(); +void multicore_reset_core1(void); /*! \brief Run code on core 1 * \ingroup pico_multicore * - * Reset core1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack) + * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack). + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * - * \param entry Function entry point, this function should not return. + * core 1 will use the same vector table as core 0 + * + * \param entry Function entry point + * \see multicore_reset_core1 */ void multicore_launch_core1(void (*entry)(void)); /*! \brief Launch code on core 1 with stack * \ingroup pico_multicore * - * Reset core1 and enter the given function on core 1 using the passed stack for core 1 - */ -void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); - -/*! \brief Send core 1 to sleep. - * \ingroup pico_multicore + * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1 + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * + * core 1 will use the same vector table as core 0 + * + * \param entry Function entry point + * \param stack_bottom The bottom (lowest address) of the stack + * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4) + * \see multicore_reset_core1 */ -void multicore_sleep_core1(); +void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); /*! \brief Launch code on core 1 with no stack protection * \ingroup pico_multicore * - * Reset core1 and enter the given function using the passed sp as the initial stack pointer. - * This is a bare bones functions that does not provide a stack guard even if USE_STACK_GUARDS is defined + * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer + * and vector table. + * + * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * + * \param entry Function entry point + * \param sp Pointer to the top of the core 1 stack + * \param vector_table address of the vector table to use for core 1 + * \see multicore_reset_core1 */ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); /*! * \defgroup multicore_fifo fifo * \ingroup pico_multicore - * \brief Functions for inter-core FIFO + * \brief Functions for the inter-core FIFOs * * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written * by core 1, and read by core 0. + * + * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during + * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use + * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes + * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully + * well handled by using a \ref queue */ - -/*! \brief Check the read FIFO to see if there is data waiting +/*! \brief Check the read FIFO to see if there is data available (sent by the other core) * \ingroup multicore_fifo * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * * \return true if the FIFO has data in it, false otherwise */ -static inline bool multicore_fifo_rvalid() { +static inline bool multicore_fifo_rvalid(void) { return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); } -/*! \brief Check the FIFO to see if the write FIFO is full +/*! \brief Check the write FIFO to see if it has space for more data * \ingroup multicore_fifo * - * @return true if the FIFO is full, false otherwise + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * @return true if the FIFO has room for more data, false otherwise */ -static inline bool multicore_fifo_wready() { +static inline bool multicore_fifo_wready(void) { return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); } -/*! \brief Push data on to the FIFO. +/*! \brief Push data on to the write FIFO (data to the other core). * \ingroup multicore_fifo * * This function will block until there is space for the data to be sent. * Use multicore_fifo_wready() to check if it is possible to write to the * FIFO if you don't want to block. * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * * \param data A 32 bit value to push on to the FIFO */ void multicore_fifo_push_blocking(uint32_t data); +/*! \brief Push data on to the write FIFO (data to the other core) with timeout. + * \ingroup multicore_fifo + * + * This function will block until there is space for the data to be sent + * or the timeout is reached + * + * \param data A 32 bit value to push on to the FIFO + * \param timeout_us the timeout in microseconds + * \return true if the data was pushed, false if the timeout occurred before data could be pushed + */ bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); -/*! \brief Pop data from the FIFO. +/*! \brief Pop data from the read FIFO (data from the other core). * \ingroup multicore_fifo * * This function will block until there is data ready to be read * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't * want to block. * - * \return 32 bit unsigned data from the FIFO. + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \return 32 bit data from the read FIFO. */ -uint32_t multicore_fifo_pop_blocking(); +uint32_t multicore_fifo_pop_blocking(void); +/*! \brief Pop data from the read FIFO (data from the other core) with timeout. + * \ingroup multicore_fifo + * + * This function will block until there is data ready to be read or the timeout is reached + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \param timeout_us the timeout in microseconds + * \param out the location to store the popped data if available + * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped + */ bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); -/*! \brief Flush any data in the outgoing FIFO +/*! \brief Discard any data in the read FIFO * \ingroup multicore_fifo * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs */ -static inline void multicore_fifo_drain() { +static inline void multicore_fifo_drain(void) { while (multicore_fifo_rvalid()) (void) sio_hw->fifo_rd; } /*! \brief Clear FIFO interrupt * \ingroup multicore_fifo + * + * Note that this only clears an interrupt that was caused by the ROE or WOF flags. + * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions. + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \see multicore_fifo_get_status */ -static inline void multicore_fifo_clear_irq() { - // Write any value to clear any interrupts +static inline void multicore_fifo_clear_irq(void) { + // Write any value to clear the error flags sio_hw->fifo_st = 0xff; } -/*! \brief Get FIFO status +/*! \brief Get FIFO statuses * \ingroup multicore_fifo * - * \return The status as a bitfield + * \return The statuses as a bitfield * * Bit | Description * ----|------------ - * 3 | Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - * 2 | Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO. + * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO. * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data) * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid) + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * */ -static inline int32_t multicore_fifo_get_status() { +static inline uint32_t multicore_fifo_get_status(void) { return sio_hw->fifo_st; } -// call this from the lockout victim thread -void multicore_lockout_victim_init(); +/*! + * \defgroup multicore_lockout lockout + * \ingroup pico_multicore + * \brief Functions to enable one core to force the other core to pause execution in a known state. + * + * Sometimes it is useful to enter a critical section on both cores at once. On a single + * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core + * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted + * in order to cooperatively enter a blocked state. + * + * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage + * waiting for the other core to enter the "locked out" state. + * + * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls + * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this. + * + * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled. + * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing + * from flash) + * + * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or + * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a + * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or + * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation. + * + * \note Because multicore lockout uses the intercore FIFOs, the FIFOs cannot be used for any other purpose + */ + +/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core) + * \ingroup multicore_lockout + * + * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this. + */ +void multicore_lockout_victim_init(void); + +/*! \brief Request the other core to pause in a known state and wait for it to do so + * \ingroup multicore_lockout + * + * The other (victim) core must have previously executed \ref multicore_lockout_victim_init() + * + * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding + * \ref multicore_lockout_end_blocking + */ +void multicore_lockout_start_blocking(void); -// start locking out the other core (it will be +/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so + * \ingroup multicore_lockout + * + * The other core must have previously executed \ref multicore_lockout_victim_init() + * + * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding + * \ref multicore_lockout_end_blocking + * + * \param timeout_us the timeout in microseconds + * \return true if the other core entered the locked out state within the timeout, false otherwise + */ bool multicore_lockout_start_timeout_us(uint64_t timeout_us); -void multicore_lockout_start_blocking(); +/*! \brief Release the other core from a locked out state amd wait for it to acknowledge + * \ingroup multicore_lockout + * + * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function + * from this core + */ +void multicore_lockout_end_blocking(void); + +/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge + * \ingroup multicore_lockout + * + * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function + * from this core + * + * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality + * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have + * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit + * the lockout state very quickly. + * + * \param timeout_us the timeout in microseconds + * \return true if the other core successfully exited locked out state within the timeout, false otherwise + */ bool multicore_lockout_end_timeout_us(uint64_t timeout_us); -void multicore_lockout_end_blocking(); #ifdef __cplusplus } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c index 6b2321f12fc..810328e6b99 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/multicore.c @@ -4,12 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "hardware/structs/sio.h" #include "pico/time.h" -#include "hardware/sync.h" #include "pico/multicore.h" +#include "hardware/sync.h" #include "hardware/irq.h" #include "hardware/structs/scb.h" +#include "hardware/structs/sio.h" #include "hardware/regs/psm.h" #include "hardware/claim.h" #if PICO_USE_STACK_GUARDS @@ -46,7 +46,7 @@ bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) { return true; } -static inline uint32_t multicore_fifo_pop_blocking_inline() { +static inline uint32_t multicore_fifo_pop_blocking_inline(void) { // If nothing there yet, we wait for an event first, // to try and avoid too much busy waiting while (!multicore_fifo_rvalid()) @@ -75,7 +75,7 @@ bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) { // Default stack for core1 ... if multicore_launch_core1 is not included then .stack1 section will be garbage collected static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)]; -static void __attribute__ ((naked)) core1_trampoline() { +static void __attribute__ ((naked)) core1_trampoline(void) { __asm("pop {r0, r1, pc}"); } @@ -83,13 +83,15 @@ int core1_wrapper(int (*entry)(void), void *stack_base) { #if PICO_USE_STACK_GUARDS // install core1 stack guard runtime_install_stack_guard(stack_base); +#else + __unused void *ignore = stack_base; #endif irq_init_priorities(); return (*entry)(); } void multicore_reset_core1() { - // Use atomic aliases just in case core 1 is also manipulating some posm state + // Use atomic aliases just in case core 1 is also manipulating some PSM state io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET); io_rw_32 *power_off_set = hw_set_alias(power_off); io_rw_32 *power_off_clr = hw_clear_alias(power_off); @@ -105,15 +107,6 @@ void multicore_reset_core1() { *power_off_clr = PSM_FRCE_OFF_PROC1_BITS; } -void multicore_sleep_core1() { - multicore_reset_core1(); - // note we give core1 an invalid stack pointer, as it should not be used - // note also if we ge simply passed a function that returned immediately, we'd end up in core1_hang anyway - // however that would waste 2 bytes for that function (the horror!) - extern void core1_hang(); // in crt0.S - multicore_launch_core1_raw(core1_hang, (uint32_t *) -1, scb_hw->vtor); -} - void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) { assert(!(stack_size_bytes & 3u)); uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t); @@ -126,7 +119,7 @@ void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bott } void multicore_launch_core1(void (*entry)(void)) { - extern char __StackOneBottom; + extern uint32_t __StackOneBottom; uint32_t *stack_limit = (uint32_t *) &__StackOneBottom; // hack to reference core1_stack although that pointer is wrong.... core1_stack should always be <= stack_limit, if not boom! uint32_t *stack = core1_stack <= stack_limit ? stack_limit : (uint32_t *) -1; @@ -134,25 +127,40 @@ void multicore_launch_core1(void (*entry)(void)) { } void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) { - uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry}; + // Allow for the fact that the caller may have already enabled the FIFO IRQ for their + // own purposes (expecting FIFO content after core 1 is launched). We must disable + // the IRQ during the handshake, then restore afterwards. + bool enabled = irq_is_enabled(SIO_IRQ_PROC0); + irq_set_enabled(SIO_IRQ_PROC0, false); + + // Values to be sent in order over the FIFO from core 0 to core 1 + // + // vector_table is value for VTOR register + // sp is initial stack pointer (SP) + // entry is the initial program counter (PC) (don't forget to set the thumb bit!) + const uint32_t cmd_sequence[] = + {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry}; uint seq = 0; do { uint cmd = cmd_sequence[seq]; - // we drain before sending a 0 + // Always drain the READ FIFO (from core 1) before sending a 0 if (!cmd) { multicore_fifo_drain(); - __sev(); // core 1 may be waiting for fifo space + // Execute a SEV as core 1 may be waiting for FIFO space via WFE + __sev(); } multicore_fifo_push_blocking(cmd); uint32_t response = multicore_fifo_pop_blocking(); - // move to next state on correct response otherwise start over + // Move to next state on correct response (echo-d value) otherwise start over seq = cmd == response ? seq + 1 : 0; } while (seq < count_of(cmd_sequence)); + + irq_set_enabled(SIO_IRQ_PROC0, enabled); } -#define LOCKOUT_MAGIC_START 0x73a8831e -#define LOCKOUT_MAGIC_END (LOCKOUT_MAGIC_START ^ -1) +#define LOCKOUT_MAGIC_START 0x73a8831eu +#define LOCKOUT_MAGIC_END (~LOCKOUT_MAGIC_START) static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, ""); @@ -161,7 +169,7 @@ static bool lockout_in_progress; // note this method is in RAM because lockout is used when writing to flash // it only makes inline calls -static void __isr __not_in_flash_func(multicore_lockout_handler)() { +static void __isr __not_in_flash_func(multicore_lockout_handler)(void) { multicore_fifo_clear_irq(); while (multicore_fifo_rvalid()) { if (sio_hw->fifo_rd == LOCKOUT_MAGIC_START) { @@ -176,10 +184,10 @@ static void __isr __not_in_flash_func(multicore_lockout_handler)() { } } -static void check_lockout_mutex_init() { +static void check_lockout_mutex_init(void) { // use known available lock - we only need it briefly uint32_t save = hw_claim_lock(); - if (!mutex_is_initialzed(&lockout_mutex)) { + if (!mutex_is_initialized(&lockout_mutex)) { mutex_init(&lockout_mutex); } hw_claim_unlock(save); @@ -202,13 +210,13 @@ static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) { if (next_timeout_us < 0) { break; } - multicore_fifo_push_timeout_us(magic, next_timeout_us); + multicore_fifo_push_timeout_us(magic, (uint64_t)next_timeout_us); next_timeout_us = absolute_time_diff_us(get_absolute_time(), until); if (next_timeout_us < 0) { break; } uint32_t word = 0; - if (!multicore_fifo_pop_timeout_us(next_timeout_us, &word)) { + if (!multicore_fifo_pop_timeout_us((uint64_t)next_timeout_us, &word)) { break; } if (word == magic) { @@ -240,7 +248,7 @@ void multicore_lockout_start_blocking() { } static bool multicore_lockout_end_block_until(absolute_time_t until) { - assert(mutex_is_initialzed(&lockout_mutex)); + assert(mutex_is_initialized(&lockout_mutex)); if (!mutex_enter_block_until(&lockout_mutex, until)) { return false; } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt index 00000f38cf0..8a6f1d24d51 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/CMakeLists.txt @@ -13,7 +13,7 @@ if (NOT TARGET pico_platform_headers) endif() if (NOT TARGET pico_platform) - add_library(pico_platform INTERFACE) + pico_add_impl_library(pico_platform) target_sources(pico_platform INTERFACE ${CMAKE_CURRENT_LIST_DIR}/platform.c) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S index 050e6a5fb51..3e01c665a18 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/asm_helper.S @@ -4,13 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include "hardware/platform_defs.h" -#include "pico/config.h" - -#define WRAPPER_FUNC_NAME(x) __wrap_##x -#define SECTION_NAME(x) .text.##x -#define RAM_SECTION_NAME(x) .time_critical.##x -#define rom_table_code(c1, c2) ((c1) | ((c2) << 8)) +#include "pico.h" // do not put align in here as it is used mid function sometimes .macro regular_func x diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h index 718a5ecab28..ee1d360cee9 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h @@ -7,94 +7,405 @@ #ifndef _PICO_PLATFORM_H_ #define _PICO_PLATFORM_H_ +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture + * to provide a common abstraction over low level compiler / platform specifics. + * + * This header may be included by assembly code + */ + +#include "hardware/platform_defs.h" + +// Marker for builds targeting the RP2040 +#define PICO_RP2040 1 + +// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_FLOAT_SUPPORT_ROM_V1 +#define PICO_FLOAT_SUPPORT_ROM_V1 1 +#endif + +// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 +#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#endif + + +// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B1_SUPPORTED +#define PICO_RP2040_B1_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B2_SUPPORTED +#define PICO_RP2040_B2_SUPPORTED 1 +#endif + +// --- remainder of file is not included by assembly code --- + +#ifndef __ASSEMBLER__ + #include #include "pico/types.h" -#include "hardware/platform_defs.h" #ifdef __cplusplus extern "C" { #endif -/** \file platform.h -* \defgroup pico_platform pico_platform -* Compiler definitions for the selected PICO_PLATFORM -*/ - +/*! \brief Marker for an interrupt handler + * \ingroup pico_platform + * For example an IRQ handler function called my_interrupt_handler: + * + * void __isr my_interrupt_handler(void) { + */ #define __isr -#define __not_in_flash(group) __attribute__((section(".time_critical." group))) -#define __not_in_flash_func(x) __not_in_flash(__STRING(x)) x -#define __no_inline_not_in_flash_func(x) __attribute__((noinline)) __not_in_flash_func(x) +/*! \brief Section attribute macro for placement in RAM after the `.data` section + * \ingroup pico_platform + * + * For example a 400 element `uint32_t` array placed after the .data section + * + * uint32_t __after_data("my_group_name") a_big_array[400]; + * + * The section attribute is `.after_data.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __after_data(group) __attribute__((section(".after_data." group))) -// For use with PICO_COPY_TO_RAM: -#define __in_flash(group) __attribute__((section(".flashdata" group))) +/*! \brief Section attribute macro for placement not in flash (i.e in RAM) + * \ingroup pico_platform + * + * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`) + * + * static const uint32_t __not_in_flash("my_group_name") an_array[3]; + * + * The section attribute is `.time_critical.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __not_in_flash(group) __attribute__((section(".time_critical." group))) +/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X") + * \ingroup pico_platform + * + * Scratch X is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch X" + * + * uint32_t __scratch_x("my_group_name") foo = 23; + * + * The section attribute is `.scratch_x.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ #define __scratch_x(group) __attribute__((section(".scratch_x." group))) + +/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y") + * \ingroup pico_platform + * + * Scratch Y is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch Y" + * + * uint32_t __scratch_y("my_group_name") foo = 23; + * + * The section attribute is `.scratch_y.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ #define __scratch_y(group) __attribute__((section(".scratch_y." group))) -#define __time_critical_func(x) __not_in_flash_func(x) -#define __after_data(group) __attribute__((section(".after_data." group))) +/*! \brief Section attribute macro for data that is to be left uninitialized + * \ingroup pico_platform + * + * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss + * section) is initialized to zero during runtime initialization + * + * For example a `uint32_t` foo that will retain its value if the program is restarted by reset. + * + * uint32_t __uninitialized_ram("my_group_name") foo; + * + * The section attribute is `.uninitialized_ram.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group + +/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary + * \ingroup pico_platform + * + * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!) + * + * uint32_t __in_flash("my_group_name") foo = 23; + * + * The section attribute is `.flashdata.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __in_flash(group) __attribute__((section(".flashdata" group))) + +/*! \brief Indicates a function should not be stored in flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) + * + * For example a function called my_func taking an int parameter: + * + * void __not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __no_inline_not_in_flash_func + */ +#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name + +/*! \brief Indicates a function is time/latency critical and should not run from flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical + * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func` + * may in the future be treated more specially to reduce the overhead when calling such function from a flash + * function. + * + * For example a function called my_func taking an int parameter: + * + * void __time_critical(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __not_in_flash_func + */ +#define __time_critical_func(func_name) __not_in_flash_func(func_name) + +/*! \brief Indicate a function should not be stored in flash and should not be inlined + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM, explicitly marking it as + * noinline to prevent it being inlined into a flash function by the compiler + * + * For example a function called my_func taking an int parameter: + * + * void __no_inline_not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + */ +#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name) + #define __packed_aligned __packed __aligned(4) +/*! \brief Attribute to force inlining of a function regardless of optimization level + * \ingroup pico_platform + * + * For example my_function here will always be inlined: + * + * int __force_inline my_function(int x) { + * + */ +#if defined(__GNUC__) && __GNUC__ <= 7 +#define __force_inline inline __always_inline +#else +#define __force_inline __always_inline +#endif + +/*! \brief Macro to determine the number of elements in an array + * \ingroup pico_platform + */ #ifndef count_of #define count_of(a) (sizeof(a)/sizeof((a)[0])) #endif +/*! \brief Macro to return the maximum of two comparable values + * \ingroup pico_platform + */ #ifndef MAX #define MAX(a, b) ((a)>(b)?(a):(b)) #endif +/*! \brief Macro to return the minimum of two comparable values + * \ingroup pico_platform + */ #ifndef MIN #define MIN(a, b) ((b)>(a)?(a):(b)) #endif -#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group - -inline static void __breakpoint() { +/*! \brief Execute a breakpoint instruction + * \ingroup pico_platform + */ +static inline void __breakpoint(void) { __asm__("bkpt #0"); } -// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values -// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore -// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode +/*! \brief Ensure that the compiler does not move memory access across this method call + * \ingroup pico_platform + * + * For example in the following code: + * + * *some_memory_location = var_a; + * __compiler_memory_barrier(); + * uint32_t var_b = *some_other_memory_location + * + * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise + * might - even above the memory store!) + */ +__force_inline static void __compiler_memory_barrier(void) { + __asm__ volatile ("" : : : "memory"); +} + +/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA + * \ingroup pico_platform + * + * This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code + * that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers + * in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native + * pointer to a 32 bit value for storage, which can be done using this macro. + */ #define host_safe_hw_ptr(x) ((uintptr_t)(x)) +#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) + -void __attribute__((noreturn)) panic_unsupported(); +/*! \brief Panics with the message "Unsupported" + * \ingroup pico_platform + * \see panic + */ +void __attribute__((noreturn)) panic_unsupported(void); +/*! \brief Displays a panic message and halts execution + * \ingroup pico_platform + * + * An attempt is made to output the message to all registered STDOUT drivers + * after which this method executes a BKPT instruction. + * + * @param fmt format string (printf-like) + * @param ... printf-like arguments + */ void __attribute__((noreturn)) panic(const char *fmt, ...); -bool running_on_fpga(); -uint8_t rp2040_chip_version(); +// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=0, advanced=true, group=pico_runtime +#ifndef PICO_NO_FPGA_CHECK +#define PICO_NO_FPGA_CHECK 0 +#endif -static inline uint8_t rp2040_rom_version() { +#if PICO_NO_FPGA_CHECK +static inline bool running_on_fpga(void) {return false;} +#else +bool running_on_fpga(void); +#endif + +/*! \brief Returns the RP2040 chip revision number + * \ingroup pico_platform + * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2) + */ +uint8_t rp2040_chip_version(void); + +/*! \brief Returns the RP2040 rom version number + * \ingroup pico_platform + * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) + */ +static inline uint8_t rp2040_rom_version(void) { return *(uint8_t*)0x13; } -// called by any tight hardware polling loop... nominally empty, but can be modified for debugging -static inline void tight_loop_contents() {} - -// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values -// which of course does not work if we're running the code natively on a 64 bit platform for testing. -// Therefore we provide this function which allows the host runtime to provide a mapping -#define native_safe_hw_ptr(x) ((uintptr_t)(x)) +/*! \brief No-op function for the body of tight loops + * \ingroup pico_platform + * + * Np-op function intended to be called by any tight hardware polling loop. Using this ubiquitously + * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup + * debugging might be added + */ +static __force_inline void tight_loop_contents(void) {} -// multiplies a by b using multiply instruction using the ARM mul instruction regardless of values -inline static int32_t __mul_instruction(int32_t a, int32_t b) { -asm ("mul %0, %1" : "+l" (a) : "l" (b) : ); -return a; +/*! \brief Multiply two integers using an assembly `MUL` instruction + * \ingroup pico_platform + * + * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler + * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { + asm ("mul %0, %1" : "+l" (a) : "l" (b) : ); + return a; } -#define WRAPPER_FUNC(x) __wrap_ ## x -#define REAL_FUNC(x) __real_ ## x - -// macro to multiply value a by possibly constant value b -// if b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default +/*! \brief multiply two integer values using the fastest method possible + * \ingroup pico_platform + * + * Efficiently multiplies value a by possibly constant value b. + * + * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default + * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable + * and will be used + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ #define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ (a)*(b)) +/*! \brief Utility macro to assert two types are equivalent. + * \ingroup pico_platform + * + * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type + * (or that a single parameter is of an expected type) + */ #define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); + +/*! \brief Get the current exception level on this core + * \ingroup pico_platform + * + * \return the exception number if the CPU is handling an exception, or 0 otherwise + */ +uint __get_current_exception(void); + +#define WRAPPER_FUNC(x) __wrap_ ## x +#define REAL_FUNC(x) __real_ ## x + #ifdef __cplusplus } #endif + +#else // __ASSEMBLER__ + +#define WRAPPER_FUNC_NAME(x) __wrap_##x +#define SECTION_NAME(x) .text.##x +#define RAM_SECTION_NAME(x) .time_critical.##x + +#endif // !__ASSEMBLER__ + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c index 86167ab2dff..9bbcf26e593 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/platform.c @@ -9,9 +9,19 @@ #include "hardware/regs/tbman.h" #include "hardware/regs/sysinfo.h" +// Note we leave the FPGA check in by default so that we can run bug repro +// binaries coming in from the wild on the FPGA platform. It takes up around +// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1 +// to remove it. The FPGA check is used to skip initialisation of hardware +// (mainly clock generators and oscillators) that aren't present on FPGA. + +#if !PICO_NO_FPGA_CHECK +// Inline stub provided in header if this code is unused (so folding can be +// done in each TU instead of relying on LTO) bool running_on_fpga() { return !!((*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS); } +#endif #define MANUFACTURER_RPI 0x927 #define PART_RP2 0x2 @@ -24,6 +34,6 @@ uint8_t rp2040_chip_version() { assert(manufacturer == MANUFACTURER_RPI); assert(part == PART_RP2); // Version 1 == B0/B1 - int version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; - return version; + uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; + return (uint8_t)version; } \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt index cf2082e81b8..989dcd1b776 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/CMakeLists.txt @@ -1,12 +1,9 @@ if (NOT TARGET pico_printf) # library to be depended on - we make this depend on particular implementations using per target generator expressions - add_library(pico_printf INTERFACE) + pico_add_impl_library(pico_printf) # no custom implementation; falls thru to compiler - add_library(pico_printf_compiler INTERFACE) - target_compile_definitions(pico_printf_compiler INTERFACE - PICO_PRINTF_COMPILER=1 - ) + pico_add_impl_library(pico_printf_compiler) add_library(pico_printf_headers INTERFACE) target_include_directories(pico_printf_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) @@ -20,28 +17,20 @@ if (NOT TARGET pico_printf) target_link_libraries(pico_printf INTERFACE $>,$,${PICO_DEFAULT_PRINTF_IMPL}>) - add_library(pico_printf_pico INTERFACE) + pico_add_impl_library(pico_printf_pico) target_sources(pico_printf_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/printf.c ) - target_compile_definitions(pico_printf_pico INTERFACE - PICO_PRINTF_PICO=1 - ) - target_link_libraries(pico_printf_pico INTERFACE pico_printf_headers) - add_library(pico_printf_none INTERFACE) + pico_add_impl_library(pico_printf_none) target_sources(pico_printf_none INTERFACE ${CMAKE_CURRENT_LIST_DIR}/printf_none.S ) target_link_libraries(pico_printf_none INTERFACE pico_printf_headers) - target_compile_definitions(pico_printf_none INTERFACE - PICO_PRINTF_NONE=1 - ) - function(wrap_printf_functions TARGET) # note that printf and vprintf are in pico_stdio so we can provide thread safety pico_wrap_function(${TARGET} sprintf) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h index 6a82b8db4a0..25cea483d28 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/include/pico/printf.h @@ -55,7 +55,7 @@ extern "C" { #endif #endif -#if PICO_PRINTF_PICO +#if LIB_PICO_PRINTF_PICO // weak raw printf may be a puts if printf has not been called, // so that we can support gc of printf when it isn't called // diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c index 833bd7fcf1c..2594c5718a7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_printf/printf.c @@ -51,13 +51,13 @@ #define PICO_PRINTF_FTOA_BUFFER_SIZE 32U #endif -// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, default=1, group=pico_printf +// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, type=bool, default=1, group=pico_printf // support for the floating point type (%f) #ifndef PICO_PRINTF_SUPPORT_FLOAT #define PICO_PRINTF_SUPPORT_FLOAT 1 #endif -// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, default=1, group=pico_printf +// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, type=bool, default=1, group=pico_printf // support for exponential floating point notation (%e/%g) #ifndef PICO_PRINTF_SUPPORT_EXPONENTIAL #define PICO_PRINTF_SUPPORT_EXPONENTIAL 1 @@ -73,12 +73,12 @@ #define PICO_PRINTF_MAX_FLOAT 1e9 #endif -// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), default=1, group=pico_printf +// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), type=bool, default=1, group=pico_printf #ifndef PICO_PRINTF_SUPPORT_LONG_LONG #define PICO_PRINTF_SUPPORT_LONG_LONG 1 #endif -// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), default=1, group=pico_printf +// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), type=bool, default=1, group=pico_printf // ptrdiff_t is normally defined in as long or long long type #ifndef PICO_PRINTF_SUPPORT_PTRDIFF_T #define PICO_PRINTF_SUPPORT_PTRDIFF_T 1 @@ -290,7 +290,7 @@ static size_t _ntoa_long(out_fct_type out, char *buffer, size_t idx, size_t maxl if (!(flags & FLAGS_PRECISION) || value) { do { const char digit = (char) (value % base); - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10); value /= base; } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); } @@ -317,7 +317,7 @@ static size_t _ntoa_long_long(out_fct_type out, char *buffer, size_t idx, size_t if (!(flags & FLAGS_PRECISION) || value) { do { const char digit = (char) (value % base); - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10); value /= base; } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)); } @@ -490,21 +490,26 @@ static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, d } conv; conv.F = value; - int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 - conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) - // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 - int expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); - // now we want to compute 10^expval but we want to be sure it won't overflow - exp2 = (int) (expval * 3.321928094887362 + 0.5); - const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; - const double z2 = z * z; - conv.U = (uint64_t) (exp2 + 1023) << 52U; - // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex - conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); - // correct for rounding errors - if (value < conv.F) { - expval--; - conv.F /= 10; + int expval; + if (conv.U) { + int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 + conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) + // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 + expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); + // now we want to compute 10^expval but we want to be sure it won't overflow + exp2 = (int) (expval * 3.321928094887362 + 0.5); + const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; + const double z2 = z * z; + conv.U = (uint64_t) (exp2 + 1023) << 52U; + // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex + conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); + // correct for rounding errors + if (value < conv.F) { + expval--; + conv.F /= 10; + } + } else { + expval = 0; } // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters @@ -513,7 +518,7 @@ static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, d // in "%g" mode, "prec" is the number of *significant figures* not decimals if (flags & FLAGS_ADAPT_EXP) { // do we want to fall-back to "%f" mode? - if ((value >= 1e-4) && (value < 1e6)) { + if ((conv.U == 0) || ((value >= 1e-4) && (value < 1e6))) { if ((int) prec > expval) { prec = (unsigned) ((int) prec - expval - 1); } else { @@ -559,7 +564,7 @@ static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, d // output the exponential symbol out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); // output the exponent value - idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth - 1, + idx = _ntoa_long(out, buffer, idx, maxlen, (uint)((expval < 0) ? -expval : expval), expval < 0, 10, 0, minwidth - 1, FLAGS_ZEROPAD | FLAGS_PLUS); // might need to right-pad spaces if (flags & FLAGS_LEFT) { @@ -913,7 +918,7 @@ int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *fo return _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va); } -#if PICO_PRINTF_PICO +#if LIB_PICO_PRINTF_PICO #if !PICO_PRINTF_ALWAYS_INCLUDED bool weak_raw_printf(const char *fmt, ...) { va_list va; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt index 83c08f61e04..3b6cc1817db 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/CMakeLists.txt @@ -1,4 +1,4 @@ -add_library(pico_runtime INTERFACE) +pico_add_impl_library(pico_runtime) target_sources(pico_runtime INTERFACE ${CMAKE_CURRENT_LIST_DIR}/runtime.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c index 22ff5208e62..575e23e08b0 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c @@ -20,15 +20,16 @@ #include "pico/mutex.h" #include "pico/time.h" -// Use mbed printf -//#include "pico/printf.h" -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" +#if LIB_PICO_PRINTF_PICO +#include "pico/printf.h" +#else +#define weak_raw_printf printf +#define weak_raw_vprintf vprintf #endif -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" #endif extern char __StackLimit; /* Set by linker. */ @@ -53,7 +54,7 @@ void runtime_install_stack_guard(void *stack_bottom) { // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u)); mpu_hw->ctrl = 5; // enable mpu with background default map - mpu_hw->rbar = (addr & ~0xff) | 0x8 | 0; + mpu_hw->rbar = (addr & (uint)~0xff) | 0x8 | 0; mpu_hw->rasr = 1 // enable region | (0x7 << 1) // size 2^(7 + 1) = 256 | (subregion_select << 8) @@ -64,10 +65,13 @@ void runtime_init(void) { // Reset all peripherals to put system into a known state, // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot + // - and USB, syscfg, as this disturbs USB-to-SWD on core 1 reset_block(~( RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS | RESETS_RESET_PLL_USB_BITS | + RESETS_RESET_USBCTRL_BITS | + RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS )); @@ -88,13 +92,13 @@ void runtime_init(void) { // Start and end points of the constructor list, // defined by the linker script. - extern void (*__preinit_array_start)(); - extern void (*__preinit_array_end)(); + extern void (*__preinit_array_start)(void); + extern void (*__preinit_array_end)(void); // Call each function in the list. // We have to take the address of the symbols, as __preinit_array_start *is* // the first function pointer, not the address of it. - for (void (**p)() = &__preinit_array_start; p < &__preinit_array_end; ++p) { + for (void (**p)(void) = &__preinit_array_start; p < &__preinit_array_end; ++p) { (*p)(); } @@ -111,23 +115,37 @@ void runtime_init(void) { hw_clear_alias(padsbank0_hw)->io[28] = hw_clear_alias(padsbank0_hw)->io[29] = PADS_BANK0_GPIO0_IE_BITS; #endif - extern mutex_t __mutex_array_start; - extern mutex_t __mutex_array_end; - - // the first function pointer, not the address of it. - for (mutex_t *m = &__mutex_array_start; m < &__mutex_array_end; m++) { - mutex_init(m); + // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size) + // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive + // spinlock and 0 for a regular one. + + static_assert(!(sizeof(mutex_t)&3), ""); + static_assert(!(sizeof(recursive_mutex_t)&3), ""); + static_assert(!offsetof(mutex_t, core), ""); + static_assert(!offsetof(recursive_mutex_t, core), ""); + extern lock_core_t __mutex_array_start; + extern lock_core_t __mutex_array_end; + + for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) { + if (l->spin_lock) { + assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex + recursive_mutex_t *rm = (recursive_mutex_t *)l; + recursive_mutex_init(rm); + l = &rm[1].core; // next + } else { + mutex_t *m = (mutex_t *)l; + mutex_init(m); + l = &m[1].core; // next + } } #if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH) __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table)); - scb_hw->vtor = (intptr_t) ram_vector_table; + scb_hw->vtor = (uintptr_t) ram_vector_table; #endif #ifndef NDEBUG - uint32_t xpsr; - __asm volatile ("mrs %0, XPSR" : "=r" (xpsr)::); - if (xpsr & 0xffu) { + if (__get_current_exception()) { // crap; started in exception handler __asm ("bkpt #0"); } @@ -142,9 +160,22 @@ void runtime_init(void) { spin_locks_reset(); irq_init_priorities(); alarm_pool_init_default(); + + // Start and end points of the constructor list, + // defined by the linker script. + extern void (*__init_array_start)(void); + extern void (*__init_array_end)(void); + + // Call each function in the list. + // We have to take the address of the symbols, as __init_array_start *is* + // the first function pointer, not the address of it. + for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { + (*p)(); + } + } -void __exit(int status) { +void _exit(__unused int status) { #if PICO_ENTER_USB_BOOT_ON_EXIT reset_usb_boot(0,0); #else @@ -154,7 +185,7 @@ void __exit(int status) { #endif } -void *__sbrk(int incr) { +void *_sbrk(int incr) { extern char end; /* Set by linker. */ static char *heap_end; char *prev_heap_end; @@ -165,9 +196,9 @@ void *__sbrk(int incr) { prev_heap_end = heap_end; char *next_heap_end = heap_end + incr; - if (__builtin_expect(next_heap_end >= (&__StackLimit), false)) { + if (__builtin_expect(next_heap_end > (&__StackLimit), false)) { #if PICO_USE_OPTIMISTIC_SBRK - if (next_heap_end == &__StackLimit) { + if (heap_end == &__StackLimit) { // errno = ENOMEM; return (char *) -1; } @@ -183,18 +214,18 @@ void *__sbrk(int incr) { // exit is not useful... no desire to pull in __call_exitprocs void exit(int status) { - __exit(status); + _exit(status); } // incorrect warning from GCC 6 #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsuggest-attribute=format" void __assert_func(const char *file, int line, const char *func, const char *failedexpr) { - printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", + weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", failedexpr, file, line, func ? ", function: " : "", func ? func : ""); - exit(1); + _exit(1); } #pragma GCC diagnostic pop @@ -203,16 +234,38 @@ void __attribute__((noreturn)) panic_unsupported() { panic("not supported"); } +// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime +// note the default is not "panic" it is undefined +#ifdef PICO_PANIC_FUNCTION +#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1) +#if !PICO_PANIC_FUNCTION_EMPTY +extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...); +#endif +// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler +void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) { + // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION! + __asm ( + "push {lr}\n" +#if !PICO_PANIC_FUNCTION_EMPTY + "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n" +#endif + "bkpt #0\n" + "1: b 1b\n" // loop for ever as we are no return + : + : + : + ); +} +#else // todo consider making this try harder to output if we panic early // right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC") // more importantly there may be no stdout/UART initialized yet // todo we may want to think about where we print panic messages to; writing to USB appears to work // though it doesn't seem like we can expect it to... fine for now -// void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { puts("\n*** PANIC ***\n"); if (fmt) { -#if PICO_PRINTF_NONE +#if LIB_PICO_PRINTF_NONE puts(fmt); #else va_list args; @@ -220,15 +273,16 @@ void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { #if PICO_PRINTF_ALWAYS_INCLUDED vprintf(fmt, args); #else - vprintf(fmt, args); + weak_raw_vprintf(fmt, args); #endif va_end(args); puts("\n"); #endif } - exit(1); + _exit(1); } +#endif void hard_assertion_failure(void) { panic("Hard assert"); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt index 8dc8ab8c3a4..a7305403ca2 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_standard_link) - add_library(pico_standard_link INTERFACE) + pico_add_impl_library(pico_standard_link) target_sources(pico_standard_link INTERFACE ${CMAKE_CURRENT_LIST_DIR}/crt0.S @@ -14,7 +14,7 @@ if (NOT TARGET pico_standard_link) target_link_options(pico_standard_link INTERFACE "LINKER:-nostdlib") endif () - target_link_libraries(pico_standard_link INTERFACE hardware_regs pico_bootrom pico_binary_info pico_cxx_options) + target_link_libraries(pico_standard_link INTERFACE hardware_regs boot_stage2_headers pico_bootrom pico_binary_info pico_cxx_options) function(pico_add_link_depend TARGET dependency) get_target_property(target_type ${TARGET} TYPE) @@ -79,11 +79,15 @@ if (NOT TARGET pico_standard_link) # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0 target_link_libraries(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>>:$>,$,bs2_default>_library>) + # PICO_CMAKE_CONFIG: PICO_USE_DEFAULT_MAX_PAGE_SIZE, Don't shrink linker max page to 4096, type=bool, default=0, advanced=true, group=pico_standard_link + if (NOT PICO_USE_DEFAULT_MAX_PAGE_SIZE) + target_link_options(pico_standard_link INTERFACE "LINKER:-z,max-page-size=4096") + endif() # done in compiler now #target_link_options(pico_standard_link INTERFACE "LINKER:--build-id=none") # this line occasionally useful for debugging ... todo maybe make a PICO_ var -# target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only + # target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections, and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link if (NOT PICO_NO_GC_SECTIONS) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c index 9a879c7bff7..aa67ac4c506 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/binary_info.c @@ -7,6 +7,10 @@ #if !PICO_NO_BINARY_INFO && !PICO_NO_PROGRAM_INFO #include "pico/binary_info.h" +#if !PICO_NO_FLASH +#include "boot_stage2/config.h" +#endif + // Note we put at most 4 pieces of binary info in the reset section because that's how much spare space we had // (picked the most common ones)... if there is a link failure because of .reset section overflow then move // more out. @@ -15,7 +19,7 @@ #if !PICO_NO_FLASH #ifndef PICO_NO_BI_BINARY_SIZE extern char __flash_binary_end; -bi_decl_with_attr(bi_binary_end((uintptr_t)&__flash_binary_end), reset_section_attr) +bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), reset_section_attr) #endif #endif @@ -66,7 +70,13 @@ bi_decl(bi_program_url(PICO_PROGRAM_URL)) #endif #endif -#if !PICO_NO_BUILD_TYPE_FEATURE +#if !PICO_NO_BI_BOOT_STAGE2_NAME +#ifdef PICO_BOOT_STAGE2_NAME +bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BOOT2_NAME, PICO_BOOT_STAGE2_NAME)) +#endif +#endif + +#if !PICO_NO_BI_BUILD_TYPE #ifdef PICO_CMAKE_BUILD_TYPE bi_decl(bi_program_build_attribute(PICO_CMAKE_BUILD_TYPE)) #else @@ -82,4 +92,4 @@ bi_decl(bi_program_build_attribute("All optimization disabled")) #endif #endif -#endif \ No newline at end of file +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S index 97af458711d..f57ddfdefc4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include "pico.h" #include "hardware/regs/m0plus.h" -#include "hardware/platform_defs.h" #include "hardware/regs/addressmap.h" #include "hardware/regs/sio.h" #include "pico/binary_info/defs.h" @@ -23,24 +23,25 @@ .section .vectors, "ax" .align 2 -.global __vectors +.global __vectors, __VECTOR_TABLE +__VECTOR_TABLE: __vectors: .word __StackTop .word _reset_handler .word isr_nmi -.word HardFault_Handler -.word MemManage_Handler -.word BusFault_Handler -.word UsageFault_Handler +.word isr_hardfault .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire -.word SVC_Handler .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire -.word PendSV_Handler -.word SysTick_Handler +.word isr_invalid // Reserved, should never fire +.word isr_svcall +.word isr_invalid // Reserved, should never fire +.word isr_invalid // Reserved, should never fire +.word isr_pendsv +.word isr_systick .word isr_irq0 .word isr_irq1 .word isr_irq2 @@ -74,6 +75,11 @@ __vectors: .word isr_irq30 .word isr_irq31 +// all default exception handlers do nothing, and we can check for them being set to our +// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end +.global __default_isrs_start +__default_isrs_start: + // Declare a weak symbol for each ISR. // By default, they will fall through to the undefined IRQ handler below (breakpoint), // but can be overridden by C functions with correct name. @@ -89,10 +95,13 @@ __vectors: // these are separated out for clarity decl_isr_bkpt isr_invalid decl_isr_bkpt isr_nmi -decl_isr_bkpt HardFault_Handler -decl_isr_bkpt SVC_Handler -decl_isr_bkpt PendSV_Handler -decl_isr_bkpt SysTick_Handler +decl_isr_bkpt isr_hardfault +decl_isr_bkpt isr_svcall +decl_isr_bkpt isr_pendsv +decl_isr_bkpt isr_systick + +.global __default_isrs_end +__default_isrs_end: .macro decl_isr name .weak \name @@ -241,9 +250,9 @@ bss_fill_test: platform_entry: // symbol for stack traces // Use 32-bit jumps, in case these symbols are moved out of branch range // (e.g. if main is in SRAM and crt0 in flash) - //ldr r1, =runtime_init - //blx r1 - ldr r1, =_start + ldr r1, =runtime_init + blx r1 + ldr r1, =main blx r1 ldr r1, =exit blx r1 @@ -313,3 +322,17 @@ __get_current_exception: mrs r0, ipsr uxtb r0, r0 bx lr + +// ---------------------------------------------------------------------------- +// Stack/heap dummies to set size + +.section .stack +// align to allow for memory protection (although this alignment is pretty much ignored by linker script) +.align 5 + .equ StackSize, PICO_STACK_SIZE +.space StackSize + +.section .heap +.align 2 + .equ HeapSize, PICO_HEAP_SIZE +.space HeapSize diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp index ecb04b4e6c0..c122dc0e96a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/new_delete.cpp @@ -17,10 +17,16 @@ void *operator new[](std::size_t n) { return std::malloc(n); } -void operator delete(void *p, std::size_t n) noexcept { std::free(p); } - void operator delete(void *p) { std::free(p); } void operator delete[](void *p) noexcept { std::free(p); } +#if __cpp_sized_deallocation + +void operator delete(void *p, __unused std::size_t n) noexcept { std::free(p); } + +void operator delete[](void *p, __unused std::size_t n) noexcept { std::free(p); } + +#endif + #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt index 15ca07ba4ab..cdc9c3b9e15 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_stdio) - add_library(pico_stdio INTERFACE) + pico_add_impl_library(pico_stdio) target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) @@ -11,6 +11,7 @@ if (NOT TARGET pico_stdio) pico_wrap_function(pico_stdio vprintf) pico_wrap_function(pico_stdio puts) pico_wrap_function(pico_stdio putchar) + pico_wrap_function(pico_stdio getchar) if (TARGET pico_printf) target_link_libraries(pico_stdio INTERFACE pico_printf) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h index aec49dfb353..e44c01d05c5 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio.h @@ -47,21 +47,24 @@ typedef struct stdio_driver stdio_driver_t; * \ingroup pico_stdio * * Call this method once you have set up your clocks to enable the stdio support for UART, USB - * and semihosting based on the presence of the respective librariess in the binary. + * and semihosting based on the presence of the respective libraries in the binary. + * + * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection + * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS) * * \see stdio_uart, stdio_usb, stdio_semihosting */ -void stdio_init_all(); +void stdio_init_all(void); /*! \brief Initialize all of the present standard stdio types that are linked into the binary. * \ingroup pico_stdio * * Call this method once you have set up your clocks to enable the stdio support for UART, USB - * and semihosting based on the presence of the respective librariess in the binary. + * and semihosting based on the presence of the respective libraries in the binary. * * \see stdio_uart, stdio_usb, stdio_semihosting */ -void stdio_flush(); +void stdio_flush(void); /*! \brief Return a character from stdin if there is one available within a timeout * \ingroup pico_stdio @@ -74,7 +77,7 @@ int getchar_timeout_us(uint32_t timeout_us); /*! \brief Adds or removes a driver from the list of active drivers used for input/output * \ingroup pico_stdio * - * \note this method should always be called on an initialized driver + * \note this method should always be called on an initialized driver and is not re-entrant * \param driver the driver * \param enabled true to add, false to remove */ @@ -100,6 +103,16 @@ void stdio_filter_driver(stdio_driver_t *driver); */ void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate); +/*! \brief putchar variant that skips any CR/LF conversion if enabled + * \ingroup pico_stdio + */ +int putchar_raw(int c); + +/*! \brief puts variant that skips any CR/LF conversion if enabled + * \ingroup pico_stdio + */ +int puts_raw(const char *s); + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h index 017206d3cd2..1c8c27c3f3d 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/include/pico/stdio/driver.h @@ -12,7 +12,7 @@ struct stdio_driver { void (*out_chars)(const char *buf, int len); - void (*out_flush)(); + void (*out_flush)(void); int (*in_chars)(char *buf, int len); stdio_driver_t *next; #if PICO_STDIO_ENABLE_CRLF_SUPPORT diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c index aecc488891e..b457b8a16db 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio/stdio.c @@ -10,20 +10,22 @@ #include "pico.h" #include "pico/mutex.h" +#if LIB_PICO_PRINTF_PICO #include "pico/printf.h" +#endif #include "pico/stdio.h" #include "pico/stdio/driver.h" #include "pico/time.h" -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART #include "pico/stdio_uart.h" #endif -#if PICO_STDIO_USB +#if LIB_PICO_STDIO_USB #include "pico/stdio_usb.h" #endif -#if PICO_STDIO_SEMIHOSTING +#if LIB_PICO_STDIO_SEMIHOSTING #include "pico/stdio_semihosting.h" #endif @@ -33,30 +35,35 @@ static stdio_driver_t *filter; #if PICO_STDOUT_MUTEX auto_init_mutex(print_mutex); -bool stdout_serialize_begin() { - int core_num = get_core_num(); +bool stdout_serialize_begin(void) { + lock_owner_id_t caller = lock_get_caller_owner_id(); + // not using lock_owner_id_t to avoid backwards incompatibility change to mutex_try_enter API + static_assert(sizeof(lock_owner_id_t) <= 4, ""); uint32_t owner; if (!mutex_try_enter(&print_mutex, &owner)) { - if (owner == core_num) { + if (owner == (uint32_t)caller) { return false; } - // other core owns the mutex, so lets wait + // we are not a nested call, so lets wait mutex_enter_blocking(&print_mutex); } return true; } -void stdout_serialize_end() { +void stdout_serialize_end(void) { mutex_exit(&print_mutex); } #else -static bool print_serialize_begin() { +static bool stdout_serialize_begin(void) { return true; } -static void print_serialize_end() { +static void stdout_serialize_end(void) { } #endif +static void stdio_out_chars_no_crlf(stdio_driver_t *driver, const char *s, int len) { + driver->out_chars(s, len); +} static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) { #if PICO_STDIO_ENABLE_CRLF_SUPPORT @@ -87,24 +94,25 @@ static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) #endif } -static bool stdio_put_string(const char *s, int len, bool newline) { - bool serialzed = stdout_serialize_begin(); - if (!serialzed) { +static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) { + bool serialized = stdout_serialize_begin(); + if (!serialized) { #if PICO_STDIO_IGNORE_NESTED_STDOUT return false; #endif } - if (len == -1) len = strlen(s); + if (len == -1) len = (int)strlen(s); + void (*out_func)(stdio_driver_t *, const char *, int) = no_cr ? stdio_out_chars_no_crlf : stdio_out_chars_crlf; for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { if (!driver->out_chars) continue; if (filter && filter != driver) continue; - stdio_out_chars_crlf(driver, s, len); + out_func(driver, s, len); if (newline) { const char c = '\n'; - stdio_out_chars_crlf(driver, &c, 1); + out_func(driver, &c, 1); } } - if (serialzed) { + if (serialized) { stdout_serialize_end(); } return len; @@ -123,20 +131,35 @@ static int stdio_get_until(char *buf, int len, absolute_time_t until) { } } } - // todo maybe a little sleep here? + // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and + // potentially starve out what they are waiting on (have seen this with USB) + busy_wait_us(1); } while (!time_reached(until)); return PICO_ERROR_TIMEOUT; } int WRAPPER_FUNC(putchar)(int c) { - char cc = c; - stdio_put_string(&cc, 1, false); + char cc = (char)c; + stdio_put_string(&cc, 1, false, false); return c; } int WRAPPER_FUNC(puts)(const char *s) { - int len = strlen(s); - stdio_put_string(s, len, true); + int len = (int)strlen(s); + stdio_put_string(s, len, true, false); + stdio_flush(); + return len; +} + +int putchar_raw(int c) { + char cc = (char)c; + stdio_put_string(&cc, 1, false, true); + return c; +} + +int puts_raw(const char *s) { + int len = (int)strlen(s); + stdio_put_string(s, len, true, true); stdio_flush(); return len; } @@ -150,7 +173,7 @@ int _read(int handle, char *buffer, int length) { int _write(int handle, char *buffer, int length) { if (handle == 1) { - stdio_put_string(buffer, length, false); + stdio_put_string(buffer, length, false, false); return length; } return -1; @@ -181,7 +204,7 @@ void stdio_flush() { } typedef struct stdio_stack_buffer { - uint used; + int used; char buf[PICO_STDIO_STACK_BUFFER_SIZE]; } stdio_stack_buffer_t; @@ -212,12 +235,12 @@ int WRAPPER_FUNC(vprintf)(const char *format, va_list va) { #endif } int ret; -#if PICO_PRINTF_PICO +#if LIB_PICO_PRINTF_PICO struct stdio_stack_buffer buffer = {.used = 0}; ret = vfctprintf(stdio_buffered_printer, &buffer, format, va); stdio_stack_buffer_flush(&buffer); stdio_flush(); -#elif PICO_PRINTF_NONE +#elif LIB_PICO_PRINTF_NONE extern void printf_none_assert(); printf_none_assert(); #else @@ -239,27 +262,27 @@ int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...) return ret; } -void stdio_init_all() { +void stdio_init_all(void) { // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway // These are well known ones -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART stdio_uart_init(); #endif -#if PICO_STDIO_SEMIHOSTING +#if LIB_PICO_STDIO_SEMIHOSTING stdio_semihosting_init(); #endif -#if PICO_STDIO_USB +#if LIB_PICO_STDIO_USB stdio_usb_init(); #endif } -int WRAPPER_FUNC(getchar)() { +int WRAPPER_FUNC(getchar)(void) { char buf[1]; - if (0 == stdio_get_until(buf, sizeof(buf), at_the_end_of_time)) { - return PICO_ERROR_TIMEOUT; - } + int len = stdio_get_until(buf, 1, at_the_end_of_time); + if (len < 0) return len; + assert(len == 1); return (uint8_t)buf[0]; } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt index c65aa91d55a..699170e7eb3 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/CMakeLists.txt @@ -1,4 +1,4 @@ -add_library(pico_stdio_semihosting INTERFACE) +pico_add_impl_library(pico_stdio_semihosting) target_sources(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio_semihosting.c @@ -6,8 +6,4 @@ target_sources(pico_stdio_semihosting INTERFACE target_include_directories(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) -target_compile_definitions(pico_stdio_semihosting INTERFACE - PICO_STDIO_SEMIHOSTING=1 -) - target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio) \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h index 0c2f00639b8..3304368e751 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h @@ -22,6 +22,10 @@ #define PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF #endif +#ifdef __cplusplus +extern "C" { +#endif + extern stdio_driver_t stdio_semihosting; /*! \brief Explicitly initialize stdout over semihosting and add it to the current set of stdout targets @@ -29,6 +33,10 @@ extern stdio_driver_t stdio_semihosting; * * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_semihosting` is included in the build */ -void stdio_semihosting_init(); +void stdio_semihosting_init(void); + +#ifdef __cplusplus +} +#endif #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c index 89367702e4f..4eb673f2d68 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_semihosting/stdio_semihosting.c @@ -18,7 +18,7 @@ // ); //} -static void __attribute__((naked)) semihosting_putc(char c) { +static void __attribute__((naked)) semihosting_putc(__unused const char *c) { __asm ( "mov r1, r0\n" @@ -30,8 +30,8 @@ static void __attribute__((naked)) semihosting_putc(char c) { static void stdio_semihosting_out_chars(const char *buf, int length) { - for (uint i = 0; i = 0) gpio_set_function((uint)tx_pin, GPIO_FUNC_UART); + if (rx_pin >= 0) gpio_set_function((uint)rx_pin, GPIO_FUNC_UART); stdio_set_driver_enabled(&stdio_uart, true); } static void stdio_uart_out_chars(const char *buf, int length) { - for (uint i = 0; i bInterfaceClass && + RESET_INTERFACE_SUBCLASS == itf_desc->bInterfaceSubClass && + RESET_INTERFACE_PROTOCOL == itf_desc->bInterfaceProtocol, 0); + + uint16_t const drv_len = sizeof(tusb_desc_interface_t); + TU_VERIFY(max_len >= drv_len, 0); + + itf_num = itf_desc->bInterfaceNumber; + return drv_len; +} + +// Support for parameterized reset via vendor interface control request +static bool resetd_control_xfer_cb(uint8_t __unused rhport, uint8_t stage, tusb_control_request_t const * request) { + // nothing to do with DATA & ACK stage + if (stage != CONTROL_STAGE_SETUP) return true; + + if (request->wIndex == itf_num) { + +#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL + if (request->bRequest == RESET_REQUEST_BOOTSEL) { +#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED + uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED; +#else + uint gpio_mask = 0u; +#endif +#if !PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED + if (request->wValue & 0x100) { + gpio_mask = 1u << (request->wValue >> 9u); + } +#endif + reset_usb_boot(gpio_mask, (request->wValue & 0x7f) | PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK); + // does not return, otherwise we'd return true + } +#endif + +#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT + if (request->bRequest == RESET_REQUEST_FLASH) { + watchdog_reboot(0, 0, PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS); + return true; + } +#endif + + } + return false; +} + +static bool resetd_xfer_cb(uint8_t __unused rhport, uint8_t __unused ep_addr, xfer_result_t __unused result, uint32_t __unused xferred_bytes) { + return true; +} + +static usbd_class_driver_t const _resetd_driver = +{ +#if CFG_TUSB_DEBUG >= 2 + .name = "RESET", +#endif + .init = resetd_init, + .reset = resetd_reset, + .open = resetd_open, + .control_xfer_cb = resetd_control_xfer_cb, + .xfer_cb = resetd_xfer_cb, + .sof = NULL +}; + +// Implement callback to add our custom driver +usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) { + *driver_count = 1; + return &_resetd_driver; +} +#endif + +#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE +// Support for default BOOTSEL reset by changing baud rate +void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_line_coding) { + if (p_line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) { +#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED + const uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED; +#else + const uint gpio_mask = 0u; +#endif + reset_usb_boot(gpio_mask, PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK); + } +} +#endif + diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c index 7bb9aea528c..913d606c470 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb.c @@ -4,19 +4,19 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#if !defined(TINYUSB_HOST_LINKED) && !defined(TINYUSB_DEVICE_LINKED) +#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE) #include "tusb.h" #include "pico/time.h" -#include "pico/stdio_usb.h" #include "pico/stdio/driver.h" #include "pico/binary_info.h" +#include "pico/mutex.h" #include "hardware/irq.h" static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ > RTC_IRQ, ""); // note RTC_IRQ is currently the last one static mutex_t stdio_usb_mutex; -static void low_priority_worker_irq() { +static void low_priority_worker_irq(void) { // if the mutex is already owned, then we are in user code // in this file which will do a tud_task itself, so we'll just do nothing // until the next tick; we won't starve @@ -41,10 +41,10 @@ static void stdio_usb_out_chars(const char *buf, int length) { if (tud_cdc_connected()) { for (int i = 0; i < length;) { int n = length - i; - int avail = tud_cdc_write_available(); + int avail = (int) tud_cdc_write_available(); if (n > avail) n = avail; if (n) { - int n2 = tud_cdc_write(buf + i, n); + int n2 = (int) tud_cdc_write(buf + i, (uint32_t)n); tud_task(); tud_cdc_write_flush(); i += n2; @@ -73,7 +73,7 @@ int stdio_usb_in_chars(char *buf, int length) { } int rc = PICO_ERROR_NO_DATA; if (tud_cdc_connected() && tud_cdc_available()) { - int count = tud_cdc_read(buf, length); + int count = (int) tud_cdc_read(buf, (uint32_t) length); rc = count ? count : PICO_ERROR_NO_DATA; } mutex_exit(&stdio_usb_mutex); @@ -103,9 +103,29 @@ bool stdio_usb_init(void) { bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true); if (rc) { stdio_set_driver_enabled(&stdio_usb, true); +#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS +#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS > 0 + absolute_time_t until = make_timeout_time_ms(PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS); +#else + absolute_time_t until = at_the_end_of_time; +#endif + do { + if (stdio_usb_connected()) { +#if PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS != 0 + sleep_ms(PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS); +#endif + break; + } + sleep_ms(10); + } while (!time_reached(until)); +#endif } return rc; } + +bool stdio_usb_connected(void) { + return tud_cdc_connected(); +} #else #include "pico/stdio_usb.h" #warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c index 3199886e88a..b3cfed01f7e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c @@ -26,18 +26,30 @@ * THE SOFTWARE. */ -#if !defined(TINYUSB_HOST_LINKED) && !defined(TINYUSB_DEVICE_LINKED) +#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE) #include "tusb.h" +#include "pico/stdio_usb/reset_interface.h" +#include "pico/unique_id.h" #define USBD_VID (0x2E8A) // Raspberry Pi #define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC +#define TUD_RPI_RESET_DESC_LEN 9 +#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE #define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) +#else +#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_RPI_RESET_DESC_LEN) +#endif #define USBD_MAX_POWER_MA (250) -#define USBD_ITF_CDC (0) // needs 2 interfaces -#define USBD_ITF_MAX (2) +#define USBD_ITF_CDC (0) // needs 2 interfaces +#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE +#define USBD_ITF_MAX (2) +#else +#define USBD_ITF_RPI_RESET (2) +#define USBD_ITF_MAX (3) +#endif #define USBD_CDC_EP_CMD (0x81) #define USBD_CDC_EP_OUT (0x02) @@ -50,6 +62,7 @@ #define USBD_STR_PRODUCT (0x02) #define USBD_STR_SERIAL (0x03) #define USBD_STR_CDC (0x04) +#define USBD_STR_RPI_RESET (0x05) // Note: descriptors returned from callbacks must exist long enough for transfer to complete @@ -70,34 +83,51 @@ static const tusb_desc_device_t usbd_desc_device = { .bNumConfigurations = 1, }; +#define TUD_RPI_RESET_DESCRIPTOR(_itfnum, _stridx) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_VENDOR_SPECIFIC, RESET_INTERFACE_SUBCLASS, RESET_INTERFACE_PROTOCOL, _stridx, + static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = { TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_MAX, USBD_STR_0, USBD_DESC_LEN, - TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, USBD_MAX_POWER_MA), + 0, USBD_MAX_POWER_MA), TUD_CDC_DESCRIPTOR(USBD_ITF_CDC, USBD_STR_CDC, USBD_CDC_EP_CMD, USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE), + +#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE + TUD_RPI_RESET_DESCRIPTOR(USBD_ITF_RPI_RESET, USBD_STR_RPI_RESET) +#endif }; +static char usbd_serial_str[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1]; + static const char *const usbd_desc_str[] = { [USBD_STR_MANUF] = "Raspberry Pi", [USBD_STR_PRODUCT] = "Pico", - [USBD_STR_SERIAL] = "000000000000", // TODO + [USBD_STR_SERIAL] = usbd_serial_str, [USBD_STR_CDC] = "Board CDC", +#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE + [USBD_STR_RPI_RESET] = "Reset", +#endif }; const uint8_t *tud_descriptor_device_cb(void) { return (const uint8_t *)&usbd_desc_device; } -const uint8_t *tud_descriptor_configuration_cb(uint8_t index) { - (void)index; +const uint8_t *tud_descriptor_configuration_cb(__unused uint8_t index) { return usbd_desc_cfg; } -const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { +const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid) { #define DESC_STR_MAX (20) static uint16_t desc_str[DESC_STR_MAX]; + // Assign the SN using the unique flash id + if (!usbd_serial_str[0]) { + pico_get_unique_board_id_string(usbd_serial_str, sizeof(usbd_serial_str)); + } + uint8_t len; if (index == 0) { desc_str[1] = 0x0409; // supported language is English @@ -113,9 +143,9 @@ const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { } // first byte is length (including header), second byte is string type - desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * len + 2); + desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * len + 2)); return desc_str; } -#endif \ No newline at end of file +#endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt index 900ae09fe70..b54639b440e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/CMakeLists.txt @@ -6,7 +6,7 @@ option(PICO_STDIO_USB "Globablly enable stdio USB" 0) option(PICO_STDIO_USB "Globablly enable stdio semihosting " 0) if (NOT TARGET pico_stdlib) - add_library(pico_stdlib INTERFACE) + pico_add_impl_library(pico_stdlib) target_sources(pico_stdlib INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdlib.c ) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c index 28d5d386af1..7c9854e7a6c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_stdlib/stdlib.c @@ -7,7 +7,7 @@ #include "pico/stdlib.h" #include "hardware/pll.h" #include "hardware/clocks.h" -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART #include "pico/stdio_uart.h" #else #include "pico/binary_info.h" @@ -90,7 +90,7 @@ bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, u } void setup_default_uart() { -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART stdio_uart_init(); #elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) // this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt index 4c367d79ba6..4c690749184 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/CMakeLists.txt @@ -1,4 +1,4 @@ -add_library(pico_unique_id INTERFACE) +pico_add_impl_library(pico_unique_id) target_sources(pico_unique_id INTERFACE ${CMAKE_CURRENT_LIST_DIR}/unique_id.c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h index be956cae619..4132a60e0f8 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/include/pico/unique_id.h @@ -7,6 +7,8 @@ #ifndef _PICO_UNIQUE_ID_H_ #define _PICO_UNIQUE_ID_H_ +#include "pico.h" + #ifdef __cplusplus extern "C" { #endif @@ -57,6 +59,21 @@ typedef struct { */ void pico_get_unique_board_id(pico_unique_board_id_t *id_out); +/*! \brief Get unique ID in string format + * \ingroup pico_unique_id + * + * Get the unique 64-bit device identifier which was retrieved from the + * external NOR flash device at boot, formatted as an ASCII hex string. + * Will always 0-terminate. + * + * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE. + * + * \param id_out a pointer to a char buffer of size len, to which the identifier will be written + * \param len the size of id_out. For full serial, len >= 2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1 + */ +void pico_get_unique_board_id_string(char *id_out, uint len); + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c index dd2f96ddc67..2e652c8f60a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_unique_id/unique_id.c @@ -11,7 +11,7 @@ static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Bo static pico_unique_board_id_t retrieved_id; -static void __attribute__((constructor)) _retrieve_unique_id_on_boot() { +static void __attribute__((constructor)) _retrieve_unique_id_on_boot(void) { #if PICO_NO_FLASH // The hardware_flash call will panic() if called directly on a NO_FLASH // build. Since this constructor is pre-main it would be annoying to @@ -26,3 +26,14 @@ static void __attribute__((constructor)) _retrieve_unique_id_on_boot() { void pico_get_unique_board_id(pico_unique_board_id_t *id_out) { *id_out = retrieved_id; } + +void pico_get_unique_board_id_string(char *id_out, uint len) { + assert(len > 0); + size_t i; + // Generate hex one nibble at a time + for (i = 0; (i < len - 1) && (i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2); i++) { + int nibble = (retrieved_id.id[i/2] >> (4 - 4 * (i&1))) & 0xf; + id_out[i] = (char)(nibble < 10 ? nibble + '0' : nibble + 'A' - 10); + } + id_out[i] = 0; +} diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt index a48c65475aa..80a6e7819fe 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/tinyusb/CMakeLists.txt @@ -8,104 +8,42 @@ if (NOT PICO_TINYUSB_PATH) set(PICO_TINYUSB_PATH ${PROJECT_SOURCE_DIR}/lib/tinyusb) if (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) message(WARNING "TinyUSB submodule has not been initialized; USB support will be unavailable - hint: try 'git submodule update --init'.") +hint: try 'git submodule update --init' from your SDK directory (${PICO_SDK_PATH}).") endif() elseif (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) message(WARNING "PICO_TINYUSB_PATH specified but content not present.") endif() if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) - message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; adding USB support.") + message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; enabling build support for USB.") - add_library(tinyusb_common INTERFACE) - target_link_libraries(tinyusb_common INTERFACE - hardware_structs - hardware_irq - hardware_resets - pico_sync - ) - - target_sources(tinyusb_common INTERFACE - ${PICO_TINYUSB_PATH}/src/tusb.c - ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c - ) + pico_register_common_scope_var(PICO_TINYUSB_PATH) - set(TINYUSB_DEBUG_LEVEL 0) - if (CMAKE_BUILD_TYPE STREQUAL "Debug") - message("Compiling TinyUSB with CFG_TUSB_DEBUG=1") - set(TINYUSB_DEBUG_LEVEL 1) - endif () + set(BOARD pico_sdk) + set(FAMILY rp2040) + include(${PICO_TINYUSB_PATH}/hw/bsp/family_support.cmake) - target_compile_definitions(tinyusb_common INTERFACE - CFG_TUSB_MCU=OPT_MCU_RP2040 - CFG_TUSB_OS=OPT_OS_PICO #seems examples are hard coded to OPT_OS_NONE - CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL} - ) - - target_include_directories(tinyusb_common INTERFACE - ${PICO_TINYUSB_PATH}/src - ${PICO_TINYUSB_PATH}/src/common - ${PICO_TINYUSB_PATH}/hw - ) + add_library(tinyusb_common INTERFACE) + target_link_libraries(tinyusb_common INTERFACE tinyusb_common_base) add_library(tinyusb_device_unmarked INTERFACE) - target_sources(tinyusb_device_unmarked INTERFACE - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/dcd_rp2040.c - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c - ${PICO_TINYUSB_PATH}/src/device/usbd.c - ${PICO_TINYUSB_PATH}/src/device/usbd_control.c - ${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c - ${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c - ${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c - ${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c - ${PICO_TINYUSB_PATH}/src/class/msc/msc_device.c - ${PICO_TINYUSB_PATH}/src/class/net/net_device.c - ${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c - ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_device.c - ) - + target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_device_base) target_compile_definitions(tinyusb_device_unmarked INTERFACE # off by default note TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX defaults from PICO_RP2040_USB_DEVICE_ENUMERATION_FIX # TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1 ) # unmarked version used by stdio USB - target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration) + target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration tinyusb_device_base) - add_library(tinyusb_device INTERFACE) + pico_add_impl_library(tinyusb_device) target_link_libraries(tinyusb_device INTERFACE tinyusb_device_unmarked) - target_compile_definitions(tinyusb_device INTERFACE - RP2040_USB_DEVICE_MODE=1 - TINYUSB_DEVICE_LINKED=1 - ) - - add_library(tinyusb_host INTERFACE) - target_sources(tinyusb_host INTERFACE - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c - ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c - ${PICO_TINYUSB_PATH}/src/host/usbh.c - ${PICO_TINYUSB_PATH}/src/host/usbh_control.c - ${PICO_TINYUSB_PATH}/src/host/hub.c - ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c - ${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c - ${PICO_TINYUSB_PATH}/src/class/msc/msc_host.c - ${PICO_TINYUSB_PATH}/src/class/vendor/vendor_host.c - ) - # Sometimes have to do host specific actions in mostly - # common functions - target_compile_definitions(tinyusb_host INTERFACE - RP2040_USB_HOST_MODE=1 - TINYUSB_HOST_LINKED=1 - ) + pico_add_impl_library(tinyusb_host) + target_link_libraries(tinyusb_host INTERFACE tinyusb_host_base tinyusb_common) - target_link_libraries(tinyusb_host INTERFACE tinyusb_common) - - add_library(tinyusb_board INTERFACE) - target_sources(tinyusb_board INTERFACE - ${PICO_TINYUSB_PATH}/hw/bsp/raspberry_pi_pico/board_raspberry_pi_pico.c - ) + pico_add_impl_library(tinyusb_board) + target_link_libraries(tinyusb_board INTERFACE tinyusb_bsp) + pico_promote_common_scope_vars() endif() - From 33c4c2259d3fc357729895e153448de3862fa8bb Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 10:34:03 +0200 Subject: [PATCH 161/227] RP2040: add placeholder files --- .../TARGET_RP2040/pico-sdk/boards/include/placeholder.h | 0 .../pico-sdk/common/pico_stdlib/include/placeholder.h | 0 .../TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h | 0 .../rp2040/hardware_structs/include/hardware/placeholder.h | 0 .../pico-sdk/rp2_common/hardware_spi/include/placeholder.h | 0 .../pico-sdk/rp2_common/pico_float/include/placeholder.h | 0 6 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h create mode 100644 targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_float/include/placeholder.h new file mode 100644 index 00000000000..e69de29bb2d From 646866f23470716c7ee5f63273aea291ce3ed037 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:59:06 +0200 Subject: [PATCH 162/227] RP2040: Fix multiple definitions errors and clashes --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore | 1 + .../TARGET_RP2040/pico-sdk/host/boot_stage2.c | 4 +--- .../Device/RaspberryPi/RP2040/Source/system_RP2040.c | 2 +- .../pico-sdk/rp2_common/pico_runtime/runtime.c | 8 ++++---- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore index 0581f97d6eb..b5d6dbeacf8 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -5,6 +5,7 @@ pico-sdk/rp2_common/pico_printf* pico-sdk/boards/include/boards/* pico-sdk/common/pico_base/include/pico/* pico-sdk/rp2_common/boot_stage2/* +pico-sdk/rp2_common/pico_bootsel_via_double_reset/* pico-sdk/rp2_common/pico_malloc/* pico-sdk/rp2_common/pico_stdlib/ pico-sdk/rp2_common/pico_mem_ops/* diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c index 52794b155c6..cfa374bdb67 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/host/boot_stage2.c @@ -1,3 +1 @@ -void main() { - -} \ No newline at end of file +// empty \ No newline at end of file diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c index 055a0752c16..01b4c6d357f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c @@ -33,7 +33,7 @@ /*--------------------------------------------------------------------------- System Core Clock Variable *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock = 125000000; /* System Clock Frequency (Core Clock)*/ /*--------------------------------------------------------------------------- System Core Clock function diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c index 575e23e08b0..50920bcad04 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c @@ -175,7 +175,7 @@ void runtime_init(void) { } -void _exit(__unused int status) { +void __exit(__unused int status) { #if PICO_ENTER_USB_BOOT_ON_EXIT reset_usb_boot(0,0); #else @@ -214,7 +214,7 @@ void *_sbrk(int incr) { // exit is not useful... no desire to pull in __call_exitprocs void exit(int status) { - _exit(status); + __exit(status); } // incorrect warning from GCC 6 @@ -225,7 +225,7 @@ void __assert_func(const char *file, int line, const char *func, const char *fai failedexpr, file, line, func ? ", function: " : "", func ? func : ""); - _exit(1); + __exit(1); } #pragma GCC diagnostic pop @@ -280,7 +280,7 @@ void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { #endif } - _exit(1); + __exit(1); } #endif From a4240109ddebcd8508b6d5c29acaaf73a19f5ae5 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 20 Apr 2022 12:08:58 +0200 Subject: [PATCH 163/227] RP2040: Restore previous divider.S to avoid including hardware_divider folder --- .../rp2_common/pico_divider/divider.S | 133 ++++++++---------- 1 file changed, 57 insertions(+), 76 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S index 234c1a472b7..12eae389959 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_divider/divider.S @@ -4,28 +4,23 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include "hardware/regs/sio.h" #include "hardware/regs/addressmap.h" -#include "hardware/divider_helper.S" .syntax unified .cpu cortex-m0plus .thumb -// PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider - #include "pico/asm_helper.S" -// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider #ifndef PICO_DIVIDER_CALL_IDIV0 #define PICO_DIVIDER_CALL_IDIV0 1 #endif -// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 64 bit division by zero should call __aeabi_ldiv0, default=1, group=pico_divider #ifndef PICO_DIVIDER_CALL_LDIV0 #define PICO_DIVIDER_CALL_LDIV0 1 #endif -// PICO_CONFIG: PICO_DIVIDER_IN_RAM, Whether divider functions should be placed in RAM, default=0, group=pico_divider .macro div_section name #if PICO_DIVIDER_IN_RAM .section RAM_SECTION_NAME(\name), "ax" @@ -34,6 +29,17 @@ #endif .endm +#if SIO_DIV_CSR_READY_LSB == 0 +.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1 +#else +need to change SHIFT above +#endif +#if SIO_DIV_CSR_DIRTY_LSB == 1 +.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2 +#else +need to change SHIFT above +#endif + @ wait 8-n cycles for the hardware divider .macro wait_div n .rept (8-\n) / 2 @@ -45,17 +51,56 @@ .endif .endm + #if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4) #error register layout has changed - we rely on this order to make sure we save/restore in the right order #endif -#if !PICO_DIVIDER_DISABLE_INTERRUPTS +# SIO_BASE ptr in r2 +.macro save_div_state_and_lr + ldr r3, [r2, #SIO_DIV_CSR_OFFSET] + # wait for results as we can't save signed-ness of operation +1: + lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY + bcc 1b + push {r4, r5, r6, r7, lr} + // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! + ldr r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] + ldr r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] + ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] + ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] +.endm + +.macro restore_div_state_and_return + // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order + // + // it is worth considering what happens if we are interrupted + // + // after writing r4: we are DIRTY and !READY + // ... interruptor using div will complete based on incorrect inputs, but dividend at least will be + // saved/restored correctly and we'll restore the rest ourselves + // after writing r4, r5: we are DIRTY and !READY + // ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor + // at least will be saved/restored correctly and and we'll restore the rest ourselves + // after writing r4, r5, r6: we are DIRTY and READY + // ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves), + // and we'll restore the remainder after the fact + + // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space + // and so 4 reads is cheaper (and we don't have to adjust r2) + str r4, [r2, #SIO_DIV_SDIVIDEND_OFFSET] + str r5, [r2, #SIO_DIV_SDIVISOR_OFFSET] + str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] + str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] + pop {r4, r5, r6, r7, pc} +.endm + .macro save_div_state_and_lr_64 push {r4, r5, r6, r7, lr} ldr r6, =SIO_BASE 1: ldr r5, [r6, #SIO_DIV_CSR_OFFSET] - // wait for results as we can't save signed-ness of operation + # wait for results as we can't save signed-ness of operation lsrs r5, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY bcc 1b // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! @@ -92,7 +137,6 @@ pop {r4, r5, r6, r7, pc} .endm -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ // since idiv and idivmod only differ by a cycle, we'll make them the same! div_section WRAPPER_FUNC_NAME(__aeabi_idiv) @@ -101,23 +145,12 @@ wrapper_func __aeabi_idiv wrapper_func __aeabi_idivmod regular_func div_s32s32 regular_func divmod_s32s32 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore ldr r3, [r2, #SIO_DIV_CSR_OFFSET] lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY bcs divmod_s32s32_savestate regular_func divmod_s32s32_unsafe -#else -// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs -// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there -// are the hardware_divider functions that can be used instead anyway -regular_func divmod_s32s32_unsafe - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - ldr r2, =(SIO_BASE) - mrs r3, PRIMASK - cpsid i -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET] str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET] cmp r1, #0 @@ -126,14 +159,8 @@ regular_func divmod_s32s32_unsafe // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ bx lr 1: -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ push {r2, lr} movs r1, #0x80 lsls r1, #24 @@ -149,15 +176,11 @@ regular_func divmod_s32s32_unsafe movs r1, #0 // remainder 0 // need to restore saved r2 as it hold SIO ptr pop {r2, pc} -#if !PICO_DIVIDER_DISABLE_INTERRUPTS .align 2 regular_func divmod_s32s32_savestate - // note that we must be at least 2 cycles into division at this point, - // which we are because of the firty check before getting here (and of course the function call before that) save_div_state_and_lr bl divmod_s32s32_unsafe restore_div_state_and_return -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ // since uidiv and uidivmod only differ by a cycle, we'll make them the same! div_section WRAPPER_FUNC_NAME(__aeabi_uidiv) @@ -165,23 +188,12 @@ regular_func div_u32u32 regular_func divmod_u32u32 wrapper_func __aeabi_uidiv wrapper_func __aeabi_uidivmod -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore ldr r3, [r2, #SIO_DIV_CSR_OFFSET] lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY bcs divmod_u32u32_savestate regular_func divmod_u32u32_unsafe -#else -// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs -// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there -// are the hardware_divider functions that can be used instead anyway -regular_func divmod_u32u32_unsafe - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - ldr r2, =(SIO_BASE) - mrs r3, PRIMASK - cpsid i -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET] str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET] cmp r1, #0 @@ -190,14 +202,8 @@ regular_func divmod_u32u32_unsafe // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last) ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET] ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET] -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ bx lr 1: -#if PICO_DIVIDER_DISABLE_INTERRUPTS - msr PRIMASK, r3 -#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */ push {r2, lr} cmp r0, #0 beq 1f @@ -210,13 +216,11 @@ regular_func divmod_u32u32_unsafe movs r1, #0 // remainder 0 // need to restore saved r2 as it hold SIO ptr pop {r2, pc} -#if !PICO_DIVIDER_DISABLE_INTERRUPTS .align 2 regular_func divmod_u32u32_savestate save_div_state_and_lr bl divmod_u32u32_unsafe restore_div_state_and_return -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) @@ -224,10 +228,9 @@ div_section WRAPPER_FUNC_NAME(__aeabi_ldiv) wrapper_func __aeabi_ldivmod regular_func div_s64s64 regular_func divmod_s64s64 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty mov ip, r2 ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore ldr r2, [r2, #SIO_DIV_CSR_OFFSET] lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY mov r2, ip @@ -238,24 +241,14 @@ divmod_s64s64_savestate: save_div_state_and_lr_64 bl divmod_s64s64_unsafe restore_div_state_and_return_64 -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl divmod_s64s64_unsafe - msr PRIMASK, r4 - pop {r4, pc} -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ .align 2 wrapper_func __aeabi_uldivmod regular_func div_u64u64 regular_func divmod_u64u64 -#if !PICO_DIVIDER_DISABLE_INTERRUPTS - // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty mov ip, r2 ldr r2, =(SIO_BASE) + # to support IRQ usage we must save/restore ldr r2, [r2, #SIO_DIV_CSR_OFFSET] lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY mov r2, ip @@ -266,16 +259,6 @@ regular_func divmod_u64u64_savestate save_div_state_and_lr_64 bl divmod_u64u64_unsafe restore_div_state_and_return_64 -#else - // to avoid worrying about IRQs (or context switches), simply disable interrupts around call - push {r4, lr} - mrs r4, PRIMASK - cpsid i - bl divmod_u64u64_unsafe - msr PRIMASK, r4 - pop {r4, pc} -#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */ - .macro dneg lo,hi mvns \hi,\hi rsbs \lo,#0 @@ -413,7 +396,6 @@ y64: lsls r3,#16 orrs r3,r4 str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16); - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty wait_div 1 uxth r4,r0 ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1>16); - str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET] @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty wait_div 3 movs r3,#0 lsls r4,r5,#16 @ quotient=(q0<<32)+(q1<<16)+q2 From debf97b52779b0d6ae8b5d3d0e6df5fe9196fd23 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:46:41 +0200 Subject: [PATCH 164/227] RP2040: Prepend '_' to clashing functions names --- .../pico-sdk/rp2_common/hardware_gpio/gpio.c | 8 ++++---- .../rp2_common/hardware_gpio/include/hardware/gpio.h | 2 +- .../TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c | 2 +- .../rp2_common/hardware_i2c/include/hardware/i2c.h | 2 +- .../rp2_common/hardware_rtc/include/hardware/rtc.h | 2 +- .../TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c | 2 +- .../rp2_common/hardware_spi/include/hardware/spi.h | 2 +- .../TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c index 2816b971851..f4c604eb255 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/gpio.c @@ -138,7 +138,7 @@ enum gpio_drive_strength gpio_get_drive_strength(uint gpio) { >> PADS_BANK0_GPIO0_DRIVE_LSB); } -static void gpio_irq_handler(void) { +static void _gpio_irq_handler(void) { io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) { @@ -182,7 +182,7 @@ void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled // TODO: Do we want to support a callback per GPIO pin? // Install IRQ handler _callbacks[get_core_num()] = callback; - irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler); + irq_set_exclusive_handler(IO_IRQ_BANK0, _gpio_irq_handler); irq_set_enabled(IO_IRQ_BANK0, true); } @@ -211,7 +211,7 @@ void gpio_set_input_enabled(uint gpio, bool enabled) { hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); } -void gpio_init(uint gpio) { +void _gpio_init(uint gpio) { sio_hw->gpio_oe_clr = 1ul << gpio; sio_hw->gpio_clr = 1ul << gpio; gpio_set_function(gpio, GPIO_FUNC_SIO); @@ -220,7 +220,7 @@ void gpio_init(uint gpio) { void gpio_init_mask(uint gpio_mask) { for(uint i=0;i<32;i++) { if (gpio_mask & 1) { - gpio_init(i); + _gpio_init(i); } gpio_mask >>= 1; } diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h index 7037e85d99b..87e75e7a5a4 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h @@ -412,7 +412,7 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events); * * \param gpio GPIO number */ -void gpio_init(uint gpio); +void _gpio_init(uint gpio); /*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) * \ingroup hardware_gpio diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c index 95bcfea1104..b89ddb58f4c 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/i2c.c @@ -31,7 +31,7 @@ static inline bool i2c_reserved_addr(uint8_t addr) { return (addr & 0x78) == 0 || (addr & 0x78) == 0x78; } -uint i2c_init(i2c_inst_t *i2c, uint baudrate) { +uint _i2c_init(i2c_inst_t *i2c, uint baudrate) { i2c_reset(i2c); i2c_unreset(i2c); i2c->restart_on_next = false; diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index 23ff8f1697a..73b2d0aca51 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -95,7 +95,7 @@ extern i2c_inst_t i2c1_inst; * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000) * \return Actual set baudrate */ -uint i2c_init(i2c_inst_t *i2c, uint baudrate); +uint _i2c_init(i2c_inst_t *i2c, uint baudrate); /*! \brief Disable the I2C HW block * \ingroup hardware_i2c diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h index 8757e36e0b6..f9ec793d4c7 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h @@ -42,7 +42,7 @@ typedef void (*rtc_callback_t)(void); /*! \brief Initialise the RTC system * \ingroup hardware_rtc */ -void rtc_init(void); +void _rtc_init(void); /*! \brief Set the RTC to the specified time * \ingroup hardware_rtc diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c index 5429acd4b77..ea4e0c8733f 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/rtc.c @@ -19,7 +19,7 @@ bool rtc_running(void) { return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); } -void rtc_init(void) { +void _rtc_init(void) { // Get clk_rtc freq and make sure it is running uint rtc_freq = clock_get_hz(clk_rtc); assert(rtc_freq != 0); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h index e8dc95251a5..eea7062131e 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h @@ -110,7 +110,7 @@ typedef enum { * \param baudrate Baudrate requested in Hz * \return the actual baud rate set */ -uint spi_init(spi_inst_t *spi, uint baudrate); +uint _spi_init(spi_inst_t *spi, uint baudrate); /*! \brief Deinitialise SPI instances * \ingroup hardware_spi diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c index 880b5343159..036b842fc01 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/spi.c @@ -18,7 +18,7 @@ static inline void spi_unreset(spi_inst_t *spi) { unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); } -uint spi_init(spi_inst_t *spi, uint baudrate) { +uint _spi_init(spi_inst_t *spi, uint baudrate) { spi_reset(spi); spi_unreset(spi); From 01fab82fb411f87c618054ec4ca820d8893b1e88 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:47:37 +0200 Subject: [PATCH 165/227] RP2040: Change standard interrupt names and linker script to be CMSIS compliant --- .../TARGET_RP2040/.mbedignore | 1 + .../rp2_common/pico_standard_link/crt0.S | 22 +++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore index b5d6dbeacf8..7207322652a 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/.mbedignore @@ -5,6 +5,7 @@ pico-sdk/rp2_common/pico_printf* pico-sdk/boards/include/boards/* pico-sdk/common/pico_base/include/pico/* pico-sdk/rp2_common/boot_stage2/* +pico-sdk/rp2_common/cmsis/* pico-sdk/rp2_common/pico_bootsel_via_double_reset/* pico-sdk/rp2_common/pico_malloc/* pico-sdk/rp2_common/pico_stdlib/ diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S index f57ddfdefc4..d22620507ed 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -29,7 +29,7 @@ __vectors: .word __StackTop .word _reset_handler .word isr_nmi -.word isr_hardfault +.word HardFault_Handler .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire @@ -37,11 +37,11 @@ __vectors: .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire -.word isr_svcall +.word SVC_Handler .word isr_invalid // Reserved, should never fire .word isr_invalid // Reserved, should never fire -.word isr_pendsv -.word isr_systick +.word PendSV_Handler +.word SysTick_Handler .word isr_irq0 .word isr_irq1 .word isr_irq2 @@ -95,10 +95,10 @@ __default_isrs_start: // these are separated out for clarity decl_isr_bkpt isr_invalid decl_isr_bkpt isr_nmi -decl_isr_bkpt isr_hardfault -decl_isr_bkpt isr_svcall -decl_isr_bkpt isr_pendsv -decl_isr_bkpt isr_systick +decl_isr_bkpt HardFault_Handler +decl_isr_bkpt SVC_Handler +decl_isr_bkpt PendSV_Handler +decl_isr_bkpt SysTick_Handler .global __default_isrs_end __default_isrs_end: @@ -250,9 +250,9 @@ bss_fill_test: platform_entry: // symbol for stack traces // Use 32-bit jumps, in case these symbols are moved out of branch range // (e.g. if main is in SRAM and crt0 in flash) - ldr r1, =runtime_init - blx r1 - ldr r1, =main + //ldr r1, =runtime_init + //blx r1 + ldr r1, =_start blx r1 ldr r1, =exit blx r1 From c776c054be4f31e140cfccf1ddd7b27bcbde7acf Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:49:28 +0200 Subject: [PATCH 166/227] RP2040: i2c read() modification to make it compliant with mbed APIs --- .../hardware_i2c/include/hardware/i2c.h | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index 73b2d0aca51..258bad6a57b 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -11,6 +11,7 @@ #include "pico/time.h" #include "hardware/structs/i2c.h" #include "hardware/regs/dreq.h" +#include "stdio.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c #ifndef PARAM_ASSERTIONS_ENABLED_I2C @@ -304,12 +305,34 @@ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, s * Reads directly from the I2C RX FIFO which is mainly useful for * slave-mode operation. */ -static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { +static inline size_t i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { + size_t bytes_read = 0; + for (size_t i = 0; i < len; ++i) { - while (!i2c_get_read_available(i2c)) + + while (!i2c_get_read_available(i2c)) { tight_loop_contents(); - *dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd; + } + + *dst = i2c_get_hw(i2c)->data_cmd; + bytes_read++; + + //printf("dst %d ,", *dst); + + //Check stop condition + int stop = (i2c->hw->raw_intr_stat & 0x00000200) >> 9; + if (stop && !i2c_get_read_available(i2c)) { + //Clear stop + int clear_stop = i2c_get_hw(i2c)->clr_stop_det; + printf("clear_stop reg: %d\n", clear_stop); + break; + } else { + *dst++; + } + } + + return bytes_read; } /*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance From 753b07f1f4dab602cf2c09357a41bcd2123d7b81 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:50:07 +0200 Subject: [PATCH 167/227] RP2040: Change uart is_writable() logic to handle FIFO --- .../pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h index bce0d2f0f81..a274207ee43 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -255,14 +255,14 @@ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { // ---------------------------------------------------------------------------- // Generic input/output -/*! \brief Determine if space is available in the TX FIFO +/*! \brief Determine if the TX FIFO is empty. * \ingroup hardware_uart * * \param uart UART instance. \ref uart0 or \ref uart1 * \return false if no space available, true otherwise */ static inline bool uart_is_writable(uart_inst_t *uart) { - return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS); + return (uart_get_hw(uart)->fr & UART_UARTFR_TXFE_BITS); } /*! \brief Wait for the UART TX fifo to be drained From aeebdfba8cfe13225ce4ee03de0e592704926d8f Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:52:35 +0200 Subject: [PATCH 168/227] RP2040: don't initalize contructors during runtime_init() --- .../pico-sdk/rp2_common/pico_runtime/runtime.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c index 50920bcad04..6a43cb5e184 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_runtime/runtime.c @@ -160,19 +160,6 @@ void runtime_init(void) { spin_locks_reset(); irq_init_priorities(); alarm_pool_init_default(); - - // Start and end points of the constructor list, - // defined by the linker script. - extern void (*__init_array_start)(void); - extern void (*__init_array_end)(void); - - // Call each function in the list. - // We have to take the address of the symbols, as __init_array_start *is* - // the first function pointer, not the address of it. - for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { - (*p)(); - } - } void __exit(__unused int status) { From 8d731e640a9cf647d8f604775a7299eb078fff12 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Fri, 13 May 2022 09:53:51 +0200 Subject: [PATCH 169/227] RP2040: adapt linker script to mbed --- .../pico-sdk/rp2_common/pico_standard_link/crt0.S | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S index d22620507ed..704a5d97950 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_standard_link/crt0.S @@ -322,17 +322,3 @@ __get_current_exception: mrs r0, ipsr uxtb r0, r0 bx lr - -// ---------------------------------------------------------------------------- -// Stack/heap dummies to set size - -.section .stack -// align to allow for memory protection (although this alignment is pretty much ignored by linker script) -.align 5 - .equ StackSize, PICO_STACK_SIZE -.space StackSize - -.section .heap -.align 2 - .equ HeapSize, PICO_HEAP_SIZE -.space HeapSize From 72ff3c4438dca686a1c36927d71dcb587f382f7b Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 20 Apr 2022 15:47:27 +0200 Subject: [PATCH 170/227] RP2040: watchdog: return timeout value in ms --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c index 7526f6b6085..7fc05cb0a45 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/watchdog_api.c @@ -41,6 +41,7 @@ uint32_t hal_watchdog_get_reload_value(void) load_value = 0xffffffu; } } + load_value = load_value / 1000 / 2; return load_value; } From cd779cab129aefb8f416025a821009e4d0a06fe1 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 18 May 2022 15:59:30 +0200 Subject: [PATCH 171/227] can: stm32: use FDCAN_IT_RX_FIFO0_NEW_MESSAGE for RX interrupt --- targets/TARGET_STM/can_api.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index c579c19a7ee..8e9780c9c3e 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -550,21 +550,12 @@ static void can_irq(CANName name, int id) irq_handler(can_irq_contexts[id], IRQ_TX); } } -#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) - if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { - if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { - __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE); - irq_handler(can_irq_contexts[id], IRQ_RX); - } - } -#else if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE); irq_handler(can_irq_contexts[id], IRQ_RX); } } -#endif if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_ERROR_WARNING)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING); @@ -632,11 +623,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) interrupts = FDCAN_IT_TX_COMPLETE; break; case IRQ_RX: -#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) - interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE; -#else interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; -#endif break; case IRQ_ERROR: interrupts = FDCAN_IT_ERROR_WARNING; From 93261a0755feaa8e6aea793c28055d34022b147e Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 12 Jul 2022 15:51:58 +0200 Subject: [PATCH 172/227] RP2040: align gpio_irq_init API with mainline --- targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c index a10a7d6c892..e53887bc321 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/gpio_api.c @@ -87,19 +87,19 @@ static void _gpio_irq(uint gpio, uint32_t events) m_irq_handler(m_channel_ids[gpio], ev); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; } MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); - m_channel_ids[pin] = id; + m_channel_ids[pin] = context; m_irq_handler = handler; obj->irq_n = IO_IRQ_BANK0; obj->pin = pin; - obj->irq_index = id; + obj->irq_index = context; return 0; } From a4bb7444ca738c5410e12d3f4e67b5ac595b7ffd Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 19 Jul 2022 11:18:08 +0200 Subject: [PATCH 173/227] STM32H7: arduino: give full 2MB flash for pure CM7 applications --- targets/targets.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index e3409dc9640..045b273f31e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3446,7 +3446,7 @@ ], "core": "Cortex-M7FD", "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x100000", + "mbed_rom_size": "0x200000", "mbed_ram_start": "0x24000000", "mbed_ram_size": "0x80000", "macros_add": [ @@ -3578,7 +3578,7 @@ "inherits": ["PORTENTA_H7"], "core": "Cortex-M7FD", "mbed_rom_start": "0x08000000", - "mbed_rom_size" : "0x100000", + "mbed_rom_size" : "0x200000", "mbed_ram_start": "0x24000000", "mbed_ram_size" : "0x80000", "extra_labels_add": [ @@ -3624,7 +3624,7 @@ "overrides": { "system_power_supply": "PWR_LDO_SUPPLY", "clock_source": "USE_PLL_HSE_EXTC", - "lse_available": 0, + "lse_available": 1, "lpticker_delay_ticks": 0, "network-default-interface-type": "WIFI", "i2c_timing_value_algo": true, From 578b697ad1002da949b102c602bd3a0ed2c2f174 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 11 Aug 2022 10:29:34 +0200 Subject: [PATCH 174/227] WHD: force disconnect on roamed due to low RSSI --- .../drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp index 6fec15adb08..509a2c0981e 100644 --- a/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp +++ b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp @@ -178,7 +178,10 @@ static void *whd_wifi_link_state_change_handler(whd_interface_t ifp, (event_header->event_type == WLC_E_DISASSOC_IND) || ((event_header->event_type == WLC_E_PSK_SUP) && (event_header->status == WLC_SUP_KEYED) && - (event_header->reason == WLC_E_SUP_DEAUTH))) { + (event_header->reason == WLC_E_SUP_DEAUTH)) || + ((event_header->event_type == WLC_E_LINK) && + (event_header->status == WLC_E_STATUS_SUCCESS) && + (event_header->reason == WLC_E_REASON_LOW_RSSI))) { whd_emac_wifi_link_state_changed(ifp, WHD_FALSE); return handler_user_data; } From 670d0318a92e657b3ef74036dd83912113f27f61 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 7 Oct 2021 17:00:27 +0200 Subject: [PATCH 175/227] STM32: lpticker: allow dynamic configuration Step1: allow automatic fallback to LSI if LSE is not functional Step2: expose two reconfiguration APIs, so the user can check if LSE is precise enough and eventually revert to LSI --- targets/TARGET_STM/lp_ticker.c | 121 ++++++++++++++++++++++----------- 1 file changed, 83 insertions(+), 38 deletions(-) diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index d5292566e55..6dc806ccf65 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -126,20 +126,35 @@ LPTIM_HandleTypeDef LptimHandle; +static uint8_t using_lse = MBED_CONF_TARGET_LSE_AVAILABLE; -const ticker_info_t *lp_ticker_get_info() +static const ticker_info_t *lp_ticker_get_info_lse() { - static const ticker_info_t info = { -#if MBED_CONF_TARGET_LSE_AVAILABLE + const static ticker_info_t info = { LSE_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK, -#else + 16 + }; + return &info; +} + +static const ticker_info_t *lp_ticker_get_info_lsi() +{ + const static ticker_info_t info = { LSI_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK, -#endif 16 }; return &info; } +const ticker_info_t *lp_ticker_get_info() +{ + if (using_lse) { + return lp_ticker_get_info_lse(); + } else { + return lp_ticker_get_info_lsi(); + } +} + volatile uint8_t lp_Fired = 0; /* Flag and stored counter to handle delayed programing at low level */ volatile bool lp_delayed_prog = false; @@ -154,71 +169,101 @@ volatile bool sleep_manager_locked = false; static int LPTICKER_inited = 0; static void LPTIM_IRQHandler(void); -void lp_ticker_init(void) -{ - /* Check if LPTIM is already configured */ - if (LPTICKER_inited) { - lp_ticker_disable_interrupt(); - return; - } - LPTICKER_inited = 1; - - RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - -#if MBED_CONF_TARGET_LSE_AVAILABLE +static void configureClocksLSE(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct, + RCC_OscInitTypeDef* RCC_OscInitStruct){ /* Enable LSE clock */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSE; #if MBED_CONF_TARGET_LSE_BYPASS - RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS; + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; #else - RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct->LSEState = RCC_LSE_ON; #endif - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE; /* Select the LSE clock as LPTIM peripheral clock */ - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; + RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM; #if (TARGET_STM32L0) - RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE; + RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE; #else #if (LPTIM_MST_BASE == LPTIM1_BASE) - RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE; + RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE; #elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) - RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE; + RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE; #endif /* LPTIM_MST_BASE == LPTIM1 */ #endif /* TARGET_STM32L0 */ -#else /* MBED_CONF_TARGET_LSE_AVAILABLE */ +} + +static void configureClocksLSI(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct, + RCC_OscInitTypeDef* RCC_OscInitStruct){ /* Enable LSI clock */ #if TARGET_STM32WB - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI1; #else - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI; #endif - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE; /* Select the LSI clock as LPTIM peripheral clock */ - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; + RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM; #if (TARGET_STM32L0) - RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI; + RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI; #else #if (LPTIM_MST_BASE == LPTIM1_BASE) - RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI; + RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI; #elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) - RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI; + RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI; #endif /* LPTIM_MST_BASE == LPTIM1 */ #endif /* TARGET_STM32L0 */ +} + +void lp_ticker_reconfigure_with_lsi() { + lp_ticker_disable_interrupt(); + LPTICKER_inited = 0; + using_lse = 0; + lp_ticker_init(); +} + +void lp_ticker_reconfigure_with_lse() { + lp_ticker_disable_interrupt(); + LPTICKER_inited = 0; + using_lse = 1; + lp_ticker_init(); +} + +void lp_ticker_init(void) +{ + /* Check if LPTIM is already configured */ + if (LPTICKER_inited) { + lp_ticker_disable_interrupt(); + return; + } + LPTICKER_inited = 1; + + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + if (using_lse) { + configureClocksLSE(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); + } else { + configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); + } -#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #if defined(DUAL_CORE) && (TARGET_STM32H7) while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("HAL_RCC_OscConfig ERROR\n"); - return; + + // retry with LSI + using_lse = 0; + configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("HAL_RCC_OscConfig ERROR\n"); + return; + } } if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) { From e1e70baec4ec65aee64dbddbcc1957f8c7843317 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 7 Oct 2021 17:02:45 +0200 Subject: [PATCH 176/227] Portenta: use LSE for low power ticker --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 045b273f31e..a11fc881295 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3567,7 +3567,7 @@ "overrides": { "system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO", "clock_source": "USE_PLL_HSE_EXTC", - "lse_available": 0, + "lse_available": 1, "lpticker_delay_ticks": 0, "network-default-interface-type": "ETHERNET", "i2c_timing_value_algo": true From 77fb09b520e9914d457882ef63e4a795d3e87529 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 23 Sep 2022 09:51:20 +0200 Subject: [PATCH 177/227] QSPI: make _qspi object protected to allow subclassing --- .../COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h index 2903ecad32f..695a3961970 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h @@ -340,9 +340,11 @@ class QSPIFBlockDevice : public mbed::BlockDevice { QSPIF_BP_CLEAR_SR, // Clear protection bits in status register 1 }; +protected: // QSPI Driver Object mbed::QSPI _qspi; +private: // Static List of different QSPI based Flash devices csel that already exist // Each QSPI Flash device csel can have only 1 QSPIFBlockDevice instance // _devices_mutex is used to lock csel list - only one QSPIFBlockDevice instance per csel is allowed From 1cabe13a9a69a2c821085e29a344655f475cf7a2 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 28 Sep 2022 17:27:56 +0200 Subject: [PATCH 178/227] STM32H747: linker: set bootloader_info section for all bootloaders --- .../TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 3e84731230b..2914967e382 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -113,7 +113,7 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) -#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) +#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) *ltrans2*.o(.rodata*) From 89e07b3d16c661124b6ecb7b1eb7add20d79572c Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 28 Sep 2022 17:28:59 +0200 Subject: [PATCH 179/227] STM32: RTC: allow runtime clock source selection --- targets/TARGET_STM/rtc_api.c | 80 +++++++++++++++++++++--------------- 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 3fb6cc73209..4b0d386e393 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -44,6 +44,14 @@ static int RTC_inited = 0; static RTC_HandleTypeDef RtcHandle; +MBED_WEAK bool isLSEAvailableAndPrecise() { +#if MBED_CONF_TARGET_LSE_AVAILABLE + return true; +#else + return false; +#endif +} + void rtc_init(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -73,44 +81,48 @@ void rtc_init(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("PeriphClkInitStruct RTC failed with HSE\n"); } -#elif (MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSE_OR_LSI) && MBED_CONF_TARGET_LSE_AVAILABLE - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; -#if MBED_CONF_TARGET_LSE_BYPASS - RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS; -#else - RCC_OscInitStruct.LSEState = RCC_LSE_ON; -#endif - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("Cannot initialize RTC with LSE\n"); - } +#elif (MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSE_OR_LSI) + + // Request if LSE is precise (fallback to WEAK implementation in case) + if (isLSEAvailableAndPrecise()) { + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + #if MBED_CONF_TARGET_LSE_BYPASS + RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS; + #else + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + #endif + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("Cannot initialize RTC with LSE\n"); + } - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - error("PeriphClkInitStruct RTC failed with LSE\n"); - } -#else /* Fallback to LSI */ -#if TARGET_STM32WB - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; -#else - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; -#endif - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("Cannot initialize RTC with LSI\n"); - } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + error("PeriphClkInitStruct RTC failed with LSE\n"); + } + } else { + #if TARGET_STM32WB + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; + #else + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + #endif + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("Cannot initialize RTC with LSI\n"); + } - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - error("PeriphClkInitStruct RTC failed with LSI\n"); + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + error("PeriphClkInitStruct RTC failed with LSI\n"); + } } #endif /* MBED_CONF_TARGET_RTC_CLOCK_SOURCE */ #if defined(DUAL_CORE) && (TARGET_STM32H7) From 8123f6ff78c23ece018a40ac5fa2055c9084db9f Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 13 Oct 2022 16:31:46 +0200 Subject: [PATCH 180/227] Increase the default EAPOL key messages timeout. --- .../wifi/COMPONENT_WHD/wifi-host-driver/src/whd_wifi_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/whd_wifi_api.c b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/whd_wifi_api.c index 52c0d7523bb..5294104ab4d 100755 --- a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/whd_wifi_api.c +++ b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/src/whd_wifi_api.c @@ -65,7 +65,7 @@ JOIN_EAPOL_KEY_G1_TIMEOUT | JOIN_EAPOL_KEY_FAILURE) #define DEFAULT_JOIN_ATTEMPT_TIMEOUT (7000) /* Overall join attempt timeout in milliseconds. */ -#define DEFAULT_EAPOL_KEY_PACKET_TIMEOUT (2500) /* Timeout when waiting for EAPOL key packet M1 or M3 in milliseconds.*/ +#define DEFAULT_EAPOL_KEY_PACKET_TIMEOUT (5000) /* Timeout when waiting for EAPOL key packet M1 or M3 in milliseconds.*/ /* Some APs may be slow to provide M1 and 1000 ms is not long enough for edge of cell. */ #ifndef DEFAULT_PM2_SLEEP_RET_TIME #define DEFAULT_PM2_SLEEP_RET_TIME (200) From 7a0c5d14cc2c96c03677adb74c8517ea3e6d334d Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 10 Nov 2022 14:04:15 +0100 Subject: [PATCH 181/227] Portenta: WHD: add function to mount wlan firmware fs from WiFi library --- .../COMPONENT_WHD/port/wiced_filesystem.cpp | 5 +++++ .../COMPONENT_WHD/port/wiced_filesystem.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp index bea07abdef5..31405c9d775 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -170,6 +170,11 @@ wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_hand return WICED_ERROR; } +wiced_result_t wiced_filesystem_mount_default(void) +{ + return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); +} + wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) { /* This is called by mbed test system */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.h index a65aa3c1489..77d49d18202 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/wiced_filesystem.h @@ -81,6 +81,15 @@ typedef int wiced_filesystem_handle_type_t; */ wiced_result_t wiced_filesystem_init(void); +/** + * Mount the physical device using default parameters + * + * This assumes that the device is ready to read/write immediately. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount_default(void); + /** * Open a file for reading or writing * From 96fae35c07c2d98f4cfdfe3ae4a45c220cd46e38 Mon Sep 17 00:00:00 2001 From: Riccardo Date: Mon, 14 Nov 2022 11:12:56 +0100 Subject: [PATCH 182/227] STM32: fix HRTIM pwm corner cases (0-100%) --- targets/TARGET_STM/pwmout_api.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index 906dc1dcfdc..e20ac918a35 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -359,10 +359,10 @@ void pwmout_write(pwmout_t *obj, float value) #if defined(HRTIM1) if (obj->pwm == PWM_I) { - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { + if (value <= (float)0.0) { value = 1.0; + } else if (value >= (float)1.0) { + value = 0.0; } obj->pulse = (uint32_t)((float)obj->period * value + 0.5); sConfig_compare.CompareValue = obj->pulse; From 955f9f4d1707a09f733094319ffeb50a20b6abde Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 14 Nov 2022 15:47:50 +0100 Subject: [PATCH 183/227] NiclaVision: WHD: add function to mount wlan firmware fs from WiFi library --- .../COMPONENT_WHD/port/wiced_filesystem.cpp | 5 +++++ .../COMPONENT_WHD/port/wiced_filesystem.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp index d66225ffd07..fe5a78a98fa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -170,6 +170,11 @@ wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_hand return WICED_ERROR; } +wiced_result_t wiced_filesystem_mount_default(void) +{ + return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); +} + wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) { /* This is called by mbed test system */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h index a65aa3c1489..77d49d18202 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/wiced_filesystem.h @@ -81,6 +81,15 @@ typedef int wiced_filesystem_handle_type_t; */ wiced_result_t wiced_filesystem_init(void); +/** + * Mount the physical device using default parameters + * + * This assumes that the device is ready to read/write immediately. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount_default(void); + /** * Open a file for reading or writing * From 9f249ac3ebd087bca0bf1b941b3c9e19eff1805c Mon Sep 17 00:00:00 2001 From: Riccardo Date: Thu, 3 Nov 2022 12:05:21 +0100 Subject: [PATCH 184/227] Cellular: add API to set Modem bands --- .../cellular/framework/API/CellularContext.h | 19 +++++++++++++++++++ .../framework/AT/AT_CellularContext.h | 2 ++ .../framework/AT/AT_CellularContext.cpp | 15 ++++++++++++--- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/API/CellularContext.h b/connectivity/cellular/include/cellular/framework/API/CellularContext.h index 1061d5d9264..325f93db4b9 100644 --- a/connectivity/cellular/include/cellular/framework/API/CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/API/CellularContext.h @@ -35,6 +35,24 @@ enum RadioAccessTechnologyType { CATNB = 8 }; +enum FrequencyBand { + BAND_1 = 0x01, + BAND_2 = 0x02, + BAND_3 = 0x04, + BAND_4 = 0x08, + BAND_5 = 0x10, + BAND_8 = 0x80, + BAND_12 = 0x800, + BAND_13 = 0x1000, + BAND_18 = 0x20000, + BAND_19 = 0x40000, + BAND_20 = 0x80000, + BAND_25 = 0x1000000, + BAND_26 = 0x2000000, + BAND_28 = 0x8000000 +}; + + namespace mbed { /** @@ -160,6 +178,7 @@ class CellularContext : public CellularInterface { const char *pwd = 0) = 0; virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0) = 0; virtual void set_access_technology(RadioAccessTechnologyType rat = CATM1) = 0; + virtual void set_band(FrequencyBand band = BAND_20) = 0; virtual bool is_connected() = 0; /** Same as NetworkInterface::get_default_instance() diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index 0eb83531b06..eb3bf5afdd1 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -48,6 +48,7 @@ class AT_CellularContext : public CellularContext { const char *pwd = 0); virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0); virtual void set_access_technology(RadioAccessTechnologyType rat = CATM1); + virtual void set_band(FrequencyBand band = BAND_20); // from CellularContext virtual nsapi_error_t get_pdpcontext_params(pdpContextList_t ¶ms_list); @@ -135,6 +136,7 @@ class AT_CellularContext : public CellularContext { PinName _dcd_pin; bool _active_high; RadioAccessTechnologyType _rat; + FrequencyBand _band; protected: char _found_apn[MAX_APN_LENGTH]; diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index 620af5ac765..087846e9b5d 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -48,7 +48,7 @@ using namespace rtos; using namespace std::chrono_literals; AT_CellularContext::AT_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) : - _current_op(OP_INVALID), _dcd_pin(NC), _active_high(false), _rat(CATM1), _cp_req(cp_req), _is_connected(false), _at(at) + _current_op(OP_INVALID), _dcd_pin(NC), _active_high(false), _rat(CATM1), _band(BAND_20), _cp_req(cp_req), _is_connected(false), _at(at) { tr_info("New CellularContext %s (%p)", apn ? apn : "", this); _nonip_req = nonip_req; @@ -284,6 +284,11 @@ void AT_CellularContext::set_access_technology(RadioAccessTechnologyType rat) _rat = rat; } +void AT_CellularContext::set_band(FrequencyBand band) +{ + _band = band; +} + // PDP Context handling void AT_CellularContext::delete_current_context() { @@ -440,11 +445,14 @@ bool AT_CellularContext::set_new_context(int cid) void AT_CellularContext::enable_access_technology() { + char *buffer = new char [8]; + memset(buffer, 0, 8); + sprintf(buffer,"%08X", _band); switch (_rat) { case CATM1: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.cmd_start_stop("^SCFG", "=","%s%d", "Radio/Band/CatM",80000); + _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); _at.resp_start("^SCFG"); _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); _at.resp_start("^SCFG"); @@ -452,7 +460,7 @@ void AT_CellularContext::enable_access_technology() case CATNB: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.cmd_start_stop("^SCFG", "=","%s%d", "Radio/Band/CatNB",80000); + _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); _at.resp_start("^SCFG"); _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); _at.resp_start("^SCFG"); @@ -464,6 +472,7 @@ void AT_CellularContext::enable_access_technology() _at.cmd_start_stop("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); _at.resp_start("^SCFG"); + free(buffer); } From 06e36fe08b90d1ea6a80bec04b039f704a68d5d7 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 5 Dec 2022 17:31:42 +0100 Subject: [PATCH 185/227] STM32H7: set ADC PLL clock for various source configurations Replaces c65d254dcac7e2c44ee459871472fc1f7955699f --- .../TARGET_STM32H7/analogin_device.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index bdf3277e1c3..be16b16cdaa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -36,10 +36,25 @@ void analogin_pll_configuration(void) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; - PeriphClkInitStruct.PLL2.PLL2M = 4; - PeriphClkInitStruct.PLL2.PLL2N = 240; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 2; + if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) { + PeriphClkInitStruct.PLL2.PLL2M = 16; + PeriphClkInitStruct.PLL2.PLL2N = 120; + } else { + #if HSE_VALUE==8000000 + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 120; + #elif HSE_VALUE==16000000 + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 60; + #elif HSE_VALUE==25000000 + PeriphClkInitStruct.PLL2.PLL2M = 5; + PeriphClkInitStruct.PLL2.PLL2N = 96; + #else + error("HSE not configured properly"); + #endif + } + PeriphClkInitStruct.PLL2.PLL2P = 3; + PeriphClkInitStruct.PLL2.PLL2Q = 4; PeriphClkInitStruct.PLL2.PLL2R = 2; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; From 4d9daca838e075694f48b2890bf855420dbd1a19 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Thu, 28 Oct 2021 09:46:47 +0200 Subject: [PATCH 186/227] Opta: initial: Add target --- .../TARGET_STM/TARGET_STM32H7/CMakeLists.txt | 2 + .../TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt | 7 + .../TARGET_OPTA/stm32h7_eth_init.c | 175 + connectivity/lwipstack/mbed_lib.json | 3 + .../TARGET_OPTA/CMakeLists.txt | 20 + .../COMPONENT_CYW43XXX/CMakeLists.txt | 4 + .../firmware/CMakeLists.txt | 6 + .../COMPONENT_4343W_FS/CMakeLists.txt | 7 + .../w_bt_firmware_controller.c | 2101 ++ .../TARGET_OPTA/COMPONENT_WHD/CMakeLists.txt | 34 + .../COMPONENT_WHD/generated_mac_address.txt | 9 + .../COMPONENT_WHD/interface/cy_result.h | 228 + .../COMPONENT_WHD/interface/cyabs_rtos.h | 711 + .../COMPONENT_WHD/interface/cyabs_rtos_impl.h | 77 + .../interface/cyabs_rtos_rtxv5.c | 863 + .../COMPONENT_WHD/interface/cyhal_gpio.h | 247 + .../COMPONENT_WHD/interface/cyhal_sdio.h | 366 + .../COMPONENT_WHD/interface/cyhal_spi.h | 383 + .../TARGET_OPTA/COMPONENT_WHD/port/cy_hal.c | 63 + .../COMPONENT_WHD/port/cy_syslib.h | 592 + .../TARGET_OPTA/COMPONENT_WHD/port/cy_utils.h | 81 + .../TARGET_OPTA/COMPONENT_WHD/port/cybsp.h | 50 + .../TARGET_OPTA/COMPONENT_WHD/port/cycfg.h | 20 + .../TARGET_OPTA/COMPONENT_WHD/port/cyhal.h | 52 + .../COMPONENT_WHD/port/cyhal_gpio.cpp | 104 + .../COMPONENT_WHD/port/cyhal_hw_types.h | 112 + .../COMPONENT_WHD/port/cyhal_sdio.c | 483 + .../COMPONENT_WHD/port/cyhal_spi.c | 29 + .../COMPONENT_WHD/port/cyhal_system.h | 20 + .../TARGET_OPTA/COMPONENT_WHD/port/wiced_bd.h | 49 + .../COMPONENT_WHD/port/wiced_filesystem.cpp | 220 + .../COMPONENT_WHD/port/wiced_filesystem.h | 139 + .../LICENSE-permissive-binary-license-1.0.txt | 49 + .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 25493 ++++++++++++++++ .../COMPONENT_4343W_FS/4343WA1_clm_blob.c | 400 + .../firmware/COMPONENT_4343W_FS/resources.h | 30 + .../resources/nvram/wifi_nvram_image.h | 87 + .../TARGET_OPTA/COMPONENT_WHD/whd_config.h | 61 + .../TARGET_OPTA/PeripheralPins.c | 570 + .../TARGET_STM32H747xI/TARGET_OPTA/PinNames.h | 450 + .../TARGET_OPTA/opta_power.cpp | 53 + .../TARGET_OPTA/opta_power.h | 31 + .../TARGET_OPTA/system_clock_override.c | 311 + targets/targets.json | 51 + 44 files changed, 34843 insertions(+) create mode 100644 connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt create mode 100644 connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/stm32h7_eth_init.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/generated_mac_address.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cy_result.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_impl.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_gpio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_sdio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_spi.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_hal.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_syslib.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_utils.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cybsp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cycfg.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_gpio.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_hw_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_spi.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_system.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_bd.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/whd_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/system_clock_override.c diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt index bfb91ae1544..dea17fcb08c 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt @@ -5,6 +5,8 @@ if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_DISCO_H747I) elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_PORTENTA_H7) +elseif("OPTA" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_OPTA) elseif("NUCLEO_H743ZI" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUCLEO_H743ZI) elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt new file mode 100644 index 00000000000..5e6c9d6be72 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-emac + INTERFACE + stm32h7_eth_init.c +) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/stm32h7_eth_init.c new file mode 100644 index 00000000000..0572fae7a2a --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_OPTA/stm32h7_eth_init.c @@ -0,0 +1,175 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define ETHERNET 1 + +#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT + +#include "stm32h7xx_hal.h" +#include "opta_power.h" + +#define ETH_TX_EN_Pin GPIO_PIN_11 +#define ETH_TX_EN_GPIO_Port GPIOG +#define ETH_TXD1_Pin GPIO_PIN_12 +#define ETH_TXD1_GPIO_Port GPIOG +#define ETH_TXD0_Pin GPIO_PIN_13 +#define ETH_TXD0_GPIO_Port GPIOG +#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1 +#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC +#define ETH_MDIO_Pin GPIO_PIN_2 +#define ETH_MDIO_GPIO_Port GPIOA +#define ETH_REF_CLK_Pin GPIO_PIN_1 +#define ETH_REF_CLK_GPIO_Port GPIOA +#define ETH_CRS_DV_Pin GPIO_PIN_7 +#define ETH_CRS_DV_GPIO_Port GPIOA +#define ETH_RXD0_Pin GPIO_PIN_4 +#define ETH_RXD0_GPIO_Port GPIOC +#define ETH_RXD1_Pin GPIO_PIN_5 +#define ETH_RXD1_GPIO_Port GPIOC + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if (heth->Instance == ETH) { + enableEthPowerSupply(); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Disable DCache for STM32H7 family */ + SCB_DisableDCache(); +#endif + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + // __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + // __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Enable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + /* Set pinstrap for 100mbit */ + // TODO + + /* Reset ETH Phy */ + __HAL_RCC_GPIOJ_CLK_ENABLE(); + GPIO_InitTypeDef gpio_eth_rst_init_structure; + gpio_eth_rst_init_structure.Pin = GPIO_PIN_15; + gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_eth_rst_init_structure.Pull = GPIO_NOPULL; + gpio_eth_rst_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOJ, &gpio_eth_rst_init_structure); + + gpio_eth_rst_init_structure.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin; + HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure); + HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1); + HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1); + gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin; + HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure); + HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1); + + HAL_Delay(25); + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); + HAL_Delay(100); + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 1); + + /**ETH GPIO Configuration + PG11 ------> ETH_TX_EN + PG12 ------> ETH_TXD1 + PG13 ------> ETH_TXD0 + PC1 ------> ETH_MDC + PA2 ------> ETH_MDIO + PA1 ------> ETH_REF_CLK + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + */ + GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH1MAC_CLK_DISABLE(); + __HAL_RCC_ETH1TX_CLK_DISABLE(); + __HAL_RCC_ETH1RX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PG11 ------> ETH_TX_EN + PG12 ------> ETH_TXD1 + PG13 ------> ETH_TXD0 + PC1 ------> ETH_MDC + PA2 ------> ETH_MDIO + PA1 ------> ETH_REF_CLK + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + */ + HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin); + + HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin); + + HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin); + + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); + } +} + +#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */ diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index 54ab36d62c3..d4488ba8015 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -228,6 +228,9 @@ "NICLA_VISION": { "mem-size": 16000 }, + "OPTA": { + "mem-size": 16000 + }, "FVP_MPS2_M3": { "mem-size": 36560 }, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/CMakeLists.txt new file mode 100644 index 00000000000..46cadd8eb0a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) + +add_library(mbed-opta INTERFACE) + +target_sources(mbed-opta + INTERFACE + PeripheralPins.c + system_clock_override.c + opta_power.cpp +) + +target_include_directories(mbed-opta + INTERFACE + . +) + +target_link_libraries(mbed-opta INTERFACE mbed-stm32h747xi-cm7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/CMakeLists.txt new file mode 100644 index 00000000000..82be36e1f09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(firmware) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt new file mode 100644 index 00000000000..fbbc3b979de --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("4343W_FS" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_4343W) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt new file mode 100644 index 00000000000..31fecb8fe09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-ble + INTERFACE + w_bt_firmware_controller.c +) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c new file mode 100644 index 00000000000..ac2bc973e1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c @@ -0,0 +1,2101 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = "BCM4343A1_001.002.009.0083.0000_Generic_UART_37_4MHz_wlbga_wiced"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[] = { + 76, 252, 70, 16, 24, 33, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, + 0, 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 18, 161, + 67, 67, 0, 1, 28, 82, 24, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 255, 82, 24, + 33, 0, 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 79, 133, 0, 0, + 3, 3, 40, 66, 67, 77, 52, 51, 52, 51, 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3, 0, 155, 240, 130, + 189, 0, 0, 216, 6, 13, 0, 16, 1, 15, 98, 116, 77, 3, 0, 155, 240, 180, + 188, 76, 252, 255, 180, 155, 33, 0, 0, 0, 224, 6, 13, 0, 16, 1, 15, + 99, 28, 71, 3, 0, 155, 240, 230, 191, 0, 0, 236, 6, 13, 0, 16, 1, 15, + 100, 52, 53, 3, 0, 157, 240, 222, 184, 0, 0, 244, 6, 13, 0, 16, 1, 15, + 101, 156, 55, 3, 0, 156, 240, 184, 191, 0, 0, 16, 7, 13, 0, 16, 1, 15, + 102, 236, 23, 2, 0, 179, 240, 230, 185, 0, 0, 188, 75, 13, 0, 16, 1, + 15, 103, 56, 199, 1, 0, 179, 240, 242, 191, 0, 0, 32, 7, 13, 0, 16, + 1, 15, 104, 16, 68, 0, 0, 208, 240, 242, 188, 0, 0, 248, 77, 13, 0, + 16, 1, 15, 105, 4, 199, 1, 0, 180, 240, 15, 184, 0, 0, 38, 7, 13, 0, + 16, 1, 15, 106, 132, 211, 2, 0, 167, 240, 32, 191, 0, 0, 200, 81, 13, + 0, 16, 1, 15, 107, 240, 210, 2, 0, 163, 240, 32, 186, 0, 0, 52, 7, 13, + 0, 6, 1, 4, 124, 85, 13, 0, 6, 1, 4, 104, 88, 13, 0, 16, 1, 15, 108, + 240, 175, 1, 0, 186, 240, 96, 188, 0, 0, 180, 88, 13, 0, 16, 1, 15, + 109, 12, 7, 2, 0, 176, 240, 32, 184, 0, 0, 80, 7, 13, 0, 16, 1, 15, + 110, 100, 57, 8, 0, 81, 240, 228, 191, 0, 0, 48, 89, 13, 0, 16, 1, 15, + 111, 100, 86, 4, 0, 139, 240, 124, 184, 0, 0, 96, 76, 252, 255, 175, + 156, 33, 0, 7, 13, 0, 16, 1, 15, 112, 60, 86, 4, 0, 144, 240, 209, 185, + 0, 0, 226, 89, 13, 0, 16, 1, 15, 113, 176, 87, 4, 0, 138, 240, 217, + 191, 0, 0, 102, 7, 13, 0, 16, 1, 15, 114, 204, 45, 5, 0, 125, 240, 206, + 188, 0, 0, 108, 7, 13, 0, 16, 1, 15, 115, 128, 42, 3, 0, 157, 240, 122, + 190, 0, 0, 120, 7, 13, 0, 16, 1, 15, 116, 84, 164, 6, 0, 102, 240, 164, + 185, 0, 0, 160, 7, 13, 0, 16, 1, 15, 117, 20, 105, 5, 0, 121, 240, 72, + 191, 0, 0, 168, 7, 13, 0, 16, 1, 15, 118, 232, 112, 7, 0, 89, 240, 98, + 187, 0, 0, 176, 7, 13, 0, 16, 1, 15, 119, 132, 103, 7, 0, 90, 240, 28, + 184, 0, 0, 192, 7, 13, 0, 16, 1, 15, 120, 84, 47, 0, 0, 205, 240, 60, + 188, 0, 0, 208, 7, 13, 0, 16, 1, 15, 121, 224, 49, 0, 0, 205, 240, 250, + 186, 0, 0, 216, 7, 13, 0, 16, 1, 15, 122, 252, 181, 1, 0, 181, 240, + 248, 184, 0, 0, 240, 7, 13, 0, 16, 1, 15, 123, 252, 199, 1, 0, 179, + 240, 254, 191, 0, 0, 252, 7, 13, 0, 16, 1, 15, 124, 100, 200, 1, 0, + 179, 240, 207, 191, 0, 0, 6, 8, 13, 0, 16, 1, 15, 125, 80, 180, 1, 0, + 181, 240, 224, 185, 0, 0, 76, 252, 11, 170, 157, 33, 0, 20, 8, 13, 0, + 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 +}; + +const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/CMakeLists.txt new file mode 100644 index 00000000000..55b7e63ecf3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-portenta-whd-4343w-fw INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS +) +target_sources(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c + resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +) + +add_library(mbed-portenta-whd-4343w-nvram INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-nvram INTERFACE resources/nvram) + +add_library(mbed-portenta-whd INTERFACE) +target_include_directories(mbed-portenta-whd + INTERFACE + . + port + interface +) + +target_sources(mbed-portenta-whd + INTERFACE + port/cyhal.c + port/cyhalgpio.cpp + port/cyhalsdio.c + port/wiced_filesystem.cpp + interface/cyabs_rtos_rtxv5.c +) + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/generated_mac_address.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/generated_mac_address.txt new file mode 100644 index 00000000000..eb735ba173d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during WHD power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:6f:b2:ea" diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cy_result.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cy_result.h new file mode 100644 index 00000000000..8277169ab99 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cy_result.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cy_result.h +* +* \brief +* Basic function result handling. Defines a simple type for conveying +* information about whether something succeeded or details about any issues +* that were detected. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_result Result Type +* \ingroup group_abstraction +* \{ +* \anchor anchor_general_description +* \brief Defines a type and related utilities for function result handling. +* +* The @ref cy_rslt_t type is a structured bitfield which encodes information +* about result type, the originating module, and a code for the specific +* error (or warning etc). In order to extract these individual fields from +* a @ref cy_rslt_t value, the utility macros @ref CY_RSLT_GET_TYPE, @ref CY_RSLT_GET_MODULE, +* and @ref CY_RSLT_GET_CODE are provided. For example: +* \code +* cy_rslt_t result = cy_hal_do_operation(arg); +* // Will be CY_RSLT_TYPE_INFO, CY_RSLT_TYPE_WARNING, CY_RSLT_TYPE_ERROR, or CY_RSLT_TYPE_FATAL +* uint8_t type = CY_RSLT_GET_TYPE(result) +* // See the "Modules" section for possible values +* uint16_t module_id = CY_RSLT_GET_MODULE(result); +* // Specific error codes are defined by each module +* uint16_t error_code = CY_RSLT_GET_CODE(result); +* \endcode +*/ + +#if !defined(CY_RESULT_H) +#define CY_RESULT_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief Provides the result of an operation as a structured bitfield. + * + * See the \ref anchor_general_description "General Description" + * for more details on structure and usage. + */ +typedef uint32_t cy_rslt_t; + +/** @ref cy_rslt_t return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) + +/** \cond INTERNAL */ +/** Mask for the bit at position "x" */ +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) + +/** Bit position of the result type */ +#define CY_RSLT_TYPE_POSITION (16U) +/** Bit width of the result type */ +#define CY_RSLT_TYPE_WIDTH (2U) +/** Bit position of the module identifier */ +#define CY_RSLT_MODULE_POSITION (18U) +/** Bit width of the module identifier */ +#define CY_RSLT_MODULE_WIDTH (14U) +/** Bit position of the result code */ +#define CY_RSLT_CODE_POSITION (0U) +/** Bit width of the result code */ +#define CY_RSLT_CODE_WIDTH (16U) + +/** Mask for the result type */ +#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) +/** Mask for the module identifier */ +#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH) +/** Mask for the result code */ +#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH) + +/** \endcond */ + +/** +* \{ +* @name Fields +* Utility macros for constructing result values and extracting individual fields from existing results. +*/ + +/** + * @brief Get the value of the result type field + * @param x the @ref cy_rslt_t value from which to extract the result type + */ +#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK) +/** + * @brief Get the value of the module identifier field + * @param x the @ref cy_rslt_t value from which to extract the module id + */ +#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) +/** + * @brief Get the value of the result code field + * @param x the @ref cy_rslt_t value from which to extract the result code + */ +#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) + +/** + * @brief Create a new @ref cy_rslt_t value that encodes the specified type, module, and result code. + * @param type one of @ref CY_RSLT_TYPE_INFO, @ref CY_RSLT_TYPE_WARNING, + * @ref CY_RSLT_TYPE_ERROR, @ref CY_RSLT_TYPE_FATAL + * @param module Identifies the module where this result originated; see @ref anchor_modules "Modules". + * @param code a module-defined identifier to identify the specific situation that + * this result describes. + */ +#define CY_RSLT_CREATE(type, module, code) \ + ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ + (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ + (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) + +/** \} fields */ + +/** +* \{ +* @name Result Types +* Defines codes to identify the type of result. +*/ + +/** @brief The result code is informational-only */ +#define CY_RSLT_TYPE_INFO (0U) +/** @brief The result code is warning of a problem but will proceed */ +#define CY_RSLT_TYPE_WARNING (1U) +/** @brief The result code is an error */ +#define CY_RSLT_TYPE_ERROR (2U) +/** @brief The result code is a fatal error */ +#define CY_RSLT_TYPE_FATAL (3U) + +/** \} severity */ + +/** +* \{ +* @name Modules +* @anchor anchor_modules +* Defines codes to identify the module from which an error originated. +* For some large libraries, a range of module codes is defined here; +* see the library documentation for values corresponding to individual modules. +* Valid range is 0x0000-0x4000. +*/ +/**** DRIVER Module codes: 0x0000 - 0x00FF ****/ +/** Base module identifier for peripheral driver library drivers (0x0000 - 0x007F) */ +#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) +/** Base module identifier for wireless host driver library modules (0x0080 - 0x00FF) */ +#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) + +/** Deprecated. Use \ref CY_RSLT_MODULE_ABSTRACTION_HAL */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) +/** Module identifier for the Hardware Abstraction Layer */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL (0x0100U) +/** Module identifier for board support package */ +#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) +/** Module identifier for file system abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) +/** Module identifier for resource abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) +/** Module identifier for rtos abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) +/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ +#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) + +/** Base module identifier for Board Libraries (0x01A0 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_LIB_BASE (0x01A0U) +/** Module identifier for the Retarget IO Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RETARGET_IO (0x1A0U) +/** Module identifier for the RGB LED Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RGB_LED (0x01A1U) +/** Module identifier for the Serial Flash Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH (0x01A2U) +/** Module identifier for the WiFi Host Driver + Board Support Integration Library */ +#define CY_RSLT_MODULE_BOARD_LIB_WHD_INTEGRATION (0x01A3U) + +/** Base module identifier for Shield Board Libraries (0x01B8 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_SHIELD_BASE (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-EPD */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_EPD (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-TFT */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_TFT (0x01B9U) +/** Module identifier for Shield Board CY8CKIT-032 */ +#define CY_RSLT_MODULE_BOARD_SHIELD_032 (0x01BAU) + +/** Base module identifier for Board Hardware Libraries (0x01C0 - 0x01FF) */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BASE (0x01C0U) +/** Module identifier for the BMI160 Motion Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BMI160 (0x01C0U) +/** Module identifier for the E2271CS021 E-Ink Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_E2271CS021 (0x01C1U) +/** Module identifier for the NTC GPIO Thermistor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_THERMISTOR (0x01C2U) +/** Module identifier for the SSD1306 OLED Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_SSD1306 (0x01C3U) +/** Module identifier for the ST7789V TFT Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_ST7789V (0x01C4U) +/** Module identifier for the Light Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_LIGHT_SENSOR (0x01C5U) +/** Module identifier for the AK4954A Audio Codec Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_AK4954A (0x01C6U) + +/** Base module identifier for Middleware Libraries (0x0200 - 0x02FF) */ +#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) + +/** \} modules */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_RESULT_H */ + +/** \} group_result */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos.h new file mode 100644 index 00000000000..e19ffc49f79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos.h @@ -0,0 +1,711 @@ +/***************************************************************************//** +* \file cyabs_rtos.h +* +* \brief +* Defines the Cypress RTOS Interface. Provides prototypes for functions that +* allow Cypress libraries to use RTOS resources such as threads, mutexes & +* timing functions in an abstract way. The APIs are implemented in the Port +* Layer RTOS interface which is specific to the RTOS in use. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef INCLUDED_CY_RTOS_INTERFACE_H_ +#define INCLUDED_CY_RTOS_INTERFACE_H_ + +#include "cyabs_rtos_impl.h" +#include "cy_result.h" +#include +#include +#include + +/** +* \defgroup group_abstraction_rtos_common Common + * General types and defines for working with the RTOS abstraction layer. +* \defgroup group_abstraction_rtos_mutex Mutex + * APIs for acquiring and working with Mutexes. +* \defgroup group_abstraction_rtos_queue Queue + * APIs for creating and working with Queues. +* \defgroup group_abstraction_rtos_semaphore Semaphore + * APIs for acquiring and working with Semaphores. +* \defgroup group_abstraction_rtos_threads Threads + * APIs for creating and working with Threads. +* \defgroup group_abstraction_rtos_time Time + * APIs for getting the current time and waiting. +* \defgroup group_abstraction_rtos_timer Timer + * APIs for creating and working with Timers. +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*********************************************** CONSTANTS **********************************************/ + +/** + * \ingroup group_abstraction_rtos_common + * \{ + */ + +#if defined(DOXYGEN) +//#include "Template/cyabs_rtos_impl.h" + +/** Return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) +#endif + +/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ +#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) + +// +// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty +// queues), the these errors are listed here and the abstraction layer implementation must map from the +// underlying errors to these. If the errors are special cases, the the error \ref CY_RTOS_GENERAL_ERROR +// will be returned and \ref cy_rtos_last_error() can be used to retrieve the RTOS specific error message. +// +/** Requested operation did not complete in the specified time */ +#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) +/** The RTOS could not allocate memory for the specified operation */ +#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) +/** An error occured in the RTOS */ +#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) +/** A bad argument was passed into the APIs */ +#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) +/** A memory alignment issue was detected. Ensure memory provided is aligned per \ref CY_RTOS_ALIGNMENT_MASK */ +#define CY_RTOS_ALIGNMENT_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 6) + +/** \} group_abstraction_rtos_common */ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** The Queue is already full and can't accept any more items at this time */ +#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) +/** The Queue is empty and has nothing to remove */ +#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** TYPES **********************************************/ + +/** + * The state a thread can be in + * + * \ingroup group_abstraction_rtos_threads + */ +typedef enum cy_thread_state +{ + CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ + CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ + CY_THREAD_STATE_RUNNING, /**< thread is currently running */ + CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ + CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ + CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ +} cy_thread_state_t; + +/** + * The type of timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef enum cy_timer_trigger_type +{ + CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ + CY_TIMER_TYPE_ONCE, /**< called once only */ + cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by \ref CY_TIMER_TYPE_PERIODIC */ + cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by \ref CY_TIMER_TYPE_ONCE */ +} cy_timer_trigger_type_t; + +/** + * The type of a function that is the entry point for a thread + * + * @param[in] arg the argument passed from the thread create call to the entry function + * + * \ingroup group_abstraction_rtos_threads + */ +typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg); + +/** + * The callback function to be called by a timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); + +/** + * Return the last error from the RTOS. + * + * The functions in the RTOS abstraction layer adhere to the Cypress return + * results calling convention. The underlying RTOS implementations will not but rather + * will have their own error code conventions. This function is provided as a service + * to the developer, mostly for debugging, and returns the underlying RTOS error code + * from the last RTOS abstraction layer that returned \ref CY_RTOS_GENERAL_ERROR. + * + * @return RTOS specific error code. + * + * \ingroup group_abstraction_rtos_common + */ +cy_rtos_error_t cy_rtos_last_error(); + +/*********************************************** Threads **********************************************/ + +/** + * \ingroup group_abstraction_rtos_threads + * \{ + */ + +/** Create a thread with specific thread argument. + * + * This function is called to startup a new thread. If the thread can exit, it must call + * \ref cy_rtos_exit_thread() just before doing so. All created threads that can terminate, either + * by themselves or forcefully by another thread MUST have \ref cy_rtos_join_thread() called on them + * by another thread in order to cleanup any resources that might have been allocated for them. + * + * @param[out] thread Pointer to a variable which will receive the new thread handle + * @param[in] entry_function Function pointer which points to the main function for the new thread + * @param[in] name String thread name used for a debugger + * @param[in] stack The buffer to use for the thread stack. This must be aligned to + * \ref CY_RTOS_ALIGNMENT_MASK with a size of at least \ref CY_RTOS_MIN_STACK_SIZE. + * If stack is null, cy_rtos_create_thread will allocate a stack from the heap. + * @param[in] stack_size The size of the thread stack in bytes + * @param[in] priority The priority of the thread. Values are operating system specific, but some + * common priority levels are defined: + * CY_THREAD_PRIORITY_LOW + * CY_THREAD_PRIORITY_NORMAL + * CY_THREAD_PRIORITY_HIGH + * @param[in] arg The argument to pass to the new thread + * + * @return The status of thread create request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); + +/** Exit the current thread. + * + * This function is called just before a thread exits. In some cases it is sufficient + * for a thread to just return to exit, but in other cases, the RTOS must be explicitly + * signaled. In cases where a return is sufficient, this should be a null funcition. + * where the RTOS must be signaled, this function should perform that In cases operation. + * In code using RTOS services, this function should be placed at any at any location + * where the main thread function will return, exiting the thread. Threads that can + * exit must still be joined (\ref cy_rtos_join_thread) to ensure their resources are + * fully cleaned up. + * + * @return The status of thread exit request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_exit_thread(); + +/** Terminates another thread. + * + * This function is called to terminate another thread and reap the resources claimed + * by the thread. This should be called both when forcibly terminating another thread + * as well as any time a thread can exit on its own. For some RTOS implementations + * this is not required as the thread resources are claimed as soon as it exits. In + * other cases, this must be called to reclaim resources. Threads that are terminated + * must still be joined (\ref cy_rtos_join_thread) to ensure their resources are fully + * cleaned up. + * + * @param[in] thread Handle of the thread to terminate + * + * @returns The status of the thread terminate. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); + +/** Waits for a thread to complete. + * + * This must be called on any thread that can complete to ensure that any resources that + * were allocated for it are cleaned up. + * + * @param[in] thread Handle of the thread to wait for + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); + +/** Checks if the thread is running + * + * This function is called to determine if a thread is actively running or not. For information on + * the thread state, use the \ref cy_rtos_get_thread_state() function. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] running Returns true if the thread is running, otherwise false + * + * @returns The status of the thread running check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); + +/** Gets the state the thread is currently in + * + * This function is called to determine if a thread is running/blocked/inactive/ready etc. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] state Returns the state the thread is currently in + * + * @returns The status of the thread state check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); + +/** Get current thread handle + * + * Returns the unique thread handle of the current running thread. + * + * @param[out] thread Handle of the current running thread + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread); + +/** \} group_abstraction_rtos_threads */ + +/*********************************************** Mutexes **********************************************/ + +/** + * \ingroup group_abstraction_rtos_mutex + * \{ + */ + +/** Create a recursive mutex. + * + * Creates a binary mutex which can be used to synchronize between threads + * and between threads and ISRs. Created mutexes are recursive and support priority inheritance. + * + * This function has been replaced by \ref cy_rtos_init_mutex2 which allow for specifying + * whether or not the mutex supports recursion or not. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +#define cy_rtos_init_mutex(mutex) cy_rtos_init_mutex2(mutex, true) + +/** Create a mutex which can support recursion or not. + * + * Creates a binary mutex which can be used to synchronize between threads and between threads and + * ISRs. Created mutexes can support priority inheritance if recursive. + * + * \note Not all RTOS implementations support non-recursive mutexes. In this case a recursive + * mutex will be created. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * @param[in] recursive Should the created mutex support recursion or not + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive); + +/** Get a mutex. + * + * If the mutex is available, it is acquired and this function returned. + * If the mutex is not available, the thread waits until the mutex is available + * or until the timeout occurs. + * + * @note This function must not be called from an interrupt context as it may block. + * + * @param[in] mutex Pointer to the mutex handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the mutex. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. + * Must be zero if in_isr is true. + * + * @return The status of the get mutex. Returns timeout if mutex was not acquired + * before timeout_ms period. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); + +/** Set a mutex. + * + * The mutex is released allowing any other threads waiting on the mutex to + * obtain the semaphore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status of the set mutex request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + * + */ +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); + +/** Deletes a mutex. + * + * This function frees the resources associated with a sempahore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status to the delete request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); + +/** \} group_abstraction_rtos_mutex */ + +/*********************************************** Semaphores **********************************************/ + +/** + * \ingroup group_abstraction_rtos_semaphore + * \{ + */ + +/** + * Create a semaphore + * + * This is basically a counting semaphore. + * + * @param[in,out] semaphore Pointer to the semaphore handle to be initialized + * @param[in] maxcount The maximum count for this semaphore + * @param[in] initcount The initial count for this semaphore + * + * @return The status of the semaphore creation. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount); + +/** + * Get/Acquire a semaphore + * + * If the semaphore count is zero, waits until the semaphore count is greater than zero. + * Once the semaphore count is greater than zero, this function decrements + * the count and return. It may also return if the timeout is exceeded. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the semaphore. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. Must + * be zero is in_isr is true + * @param[in] in_isr true if we are trying to get the semaphore from with an ISR + * @return The status of get semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); + +/** + * Set/Release a semaphore + * + * Increments the semaphore count, up to the maximum count for this semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] in_isr Value of true indicates calling from interrupt context + * Value of false indicates calling from normal thread context + * @return The status of set semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); + +/** + * Get the count of a semaphore. + * + * Gets the number of available tokens on the semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[out] count Pointer to the return count + * @return The status of get semaphore count operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count); + +/** + * Deletes a semaphore + * + * This function frees the resources associated with a semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * + * @return The status of semaphore deletion [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); + +/** \} group_abstraction_rtos_semaphore */ + +/*********************************************** Events **********************************************/ + +/** + * \ingroup group_abstraction_rtos_event + * \{ + */ + +/** Create an event. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. + * + * @param[in,out] event Pointer to the event handle to be initialized + * + * @return The status of the event initialization request. + * [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_event(cy_event_t *event); + +/** Set the event flag bits. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. Any threads waiting on this event are released + * + * @param[in] event Pointer to the event handle + * @param[in] bits The value of the 32 bit flags + * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread + * + * @return The status of the set request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** + * Clear the event flag bits + * + * This function clears bits in the event. + * + * @param[in] event Pointer to the event handle + * @param[in] bits Any bits set in this value, will be cleared in the event. + * @param[in] in_isr if true, this is called from an ISR, otherwise from a thread + * + * @return The status of the clear flags request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** Get the event bits. + * + * Returns the current bits for the event. + * + * @param[in] event Pointer to the event handle + * @param[out] bits pointer to receive the value of the event flags + * + * @return The status of the get request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); + +/** Wait for the event and return bits. + * + * Waits for the event to be set and then returns the bits associated + * with the event, or waits for the given timeout period. + * @note This function returns if any bit in the set is set. + * + * @param[in] event Pointer to the event handle + * @param[in,out] bits pointer to receive the value of the event flags + * @param[in] clear if true, clear any bits set that cause the wait to return + * if false, do not clear bits + * @param[in] all if true, all bits in the initial bits value must be set to return + * if false, any one bit in the initial bits value must be set to return + * @param[in] timeout The amount of time to wait in milliseconds + * + * @return The status of the wait for event request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); + +/** Deinitialize a event. + * + * This function frees the resources associated with an event. + * + * @param[in] event Pointer to the event handle + * + * @return The status of the deletion request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); + +/** \} group_abstraction_rtos_event */ + +/*********************************************** Queues **********************************************/ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** Create a queue. + * + * This is a queue of data where entries are placed on the back of the queue + * and removed from the front of the queue. + * + * @param[out] queue Pointer to the queue handle + * @param[in] length The maximum length of the queue in items + * @param[in] itemsize The size of each item in the queue. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); + +/** Put an item in a queue. + * + * This function puts an item in the queue. The item is copied + * into the queue using a memory copy and the data pointed to by item_ptr + * is no longer referenced once the call returns. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the item to place in the queue + * @param[in] timeout_ms The time to wait to place the item in the queue + * @param[in] in_isr If true this is being called from within and ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_FULL] + */ +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Gets an item in a queue. + * + * This function gets an item from the queue. The item is copied + * out of the queue into the memory provide by item_ptr. This space must be + * large enough to hold a queue entry as defined when the queue was initialized. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the memory for the item from the queue + * @param[in] timeout_ms The time to wait to get an item from the queue + * @param[in] in_isr If true this is being called from within an ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_EMPTY] + */ +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Return the number of items in the queue. + * + * This function returns the number of items currently in the queue. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_waiting Pointer to the return count + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); + +/** Return the amount of empty space in the queue. + * + * This function returns the amount of empty space in the + * queue. For instance, if the queue was created with 10 entries max and there + * are currently 2 entries in the queue, this will return 8. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_spaces Pointer to the return count. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); + +/** Reset the queue. + * + * This function sets the queue to empty. + * + * @param[in] queue pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); + +/** Deinitialize the queue handle. + * + * This function de-initializes the queue and returns all + * resources used by the queue. + * + * @param[in] queue Pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** Timers **********************************************/ + +/** + * \ingroup group_abstraction_rtos_timer + * \{ + */ + +/** Create a new timer. + * + * This function initializes a timer object. + * @note The timer is not active until start is called. + * @note The callback may be (likely will be) called from a different thread. + * + * @param[out] timer Pointer to the timer handle to initialize + * @param[in] type Type of timer (periodic or once) + * @param[in] fun The function + * @param[in] arg Argument to pass along to the callback function + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg); + +/** Start a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[in] num_ms The number of milliseconds to wait before the timer fires + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); + +/** Stop a timer. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); + +/** Returns state of a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[out] state Return value for state, true if running, false otherwise + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); + +/** Deinit the timer. + * + * This function deinitializes the timer and frees all consumed resources. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); + +/** \} group_abstraction_rtos_timer */ + +/*********************************************** Time **********************************************/ + +/** + * \ingroup group_abstraction_rtos_time + * \{ + */ + +/** Gets time in milliseconds since RTOS start. + * + * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds + * + * @param[out] tval Pointer to the struct to populate with the RTOS time + * + * @returns Time in milliseconds since the RTOS started. + */ +cy_rslt_t cy_rtos_get_time(cy_time_t *tval); + +/** Delay for a number of milliseconds. + * + * Processing of this function depends on the minimum sleep + * time resolution of the RTOS. The current thread should sleep for + * the longest period possible which is less than the delay required, + * then makes up the difference with a tight loop. + * + * @param[in] num_ms The number of milliseconds to delay for + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); + +/** \} group_abstraction_rtos_time */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_impl.h new file mode 100644 index 00000000000..8b36a68844a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_impl.h @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cyabs_rtos_impl.h +* +* \brief +* Internal definitions for RTOS abstraction layer +* +******************************************************************************** +* \copyright +* Copyright 2019-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + + +#ifndef INCLUDED_CYABS_RTOS_IMPL_H_ +#define INCLUDED_CYABS_RTOS_IMPL_H_ + +#include "cmsis_os2.h" +#include "rtx_os.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size in bytes */ +#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ +#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignment of created RTOS objects */ + + +/****************************************************** +* Type Definitions +******************************************************/ + +/* RTOS thread priority */ +typedef enum +{ + CY_RTOS_PRIORITY_MIN = osPriorityNone, + CY_RTOS_PRIORITY_LOW = osPriorityLow, + CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal, + CY_RTOS_PRIORITY_NORMAL = osPriorityNormal, + CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal, + CY_RTOS_PRIORITY_HIGH = osPriorityHigh, + CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime, + CY_RTOS_PRIORITY_MAX = osPriorityRealtime7 +} cy_thread_priority_t ; + +typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */ +typedef void * cy_thread_arg_t; /** Argument passed to the entry function of a thread */ +typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */ +typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */ +typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */ +typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */ +typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */ +typedef void * cy_timer_callback_arg_t; /** Argument passed to the timer callback function */ +typedef uint32_t cy_time_t; /** Time in milliseconds */ +typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c new file mode 100644 index 00000000000..37c70fe5c74 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c @@ -0,0 +1,863 @@ +/***************************************************************************//** +* \file cyabs_rtos.c +* +* \brief +* Implementation for CMSIS RTOS v2 abstraction +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + + +/****************************************************** +* Error Converter +******************************************************/ + +/* Last received error status */ +static cy_rtos_error_t dbgErr; +cy_rtos_error_t cy_rtos_last_error() { return dbgErr; } + +/* Converts internal error type to external error type */ +static cy_rslt_t error_converter(cy_rtos_error_t internalError) +{ + cy_rslt_t value; + + switch (internalError) + { + case osOK: + value = CY_RSLT_SUCCESS; + break; + case osErrorTimeout: + value = CY_RTOS_TIMEOUT; + break; + case osErrorParameter: + value = CY_RTOS_BAD_PARAM; + break; + case osErrorNoMemory: + value = CY_RTOS_NO_MEMORY; + break; + case osError: + case osErrorResource: + case osErrorISR: + default: + value = CY_RTOS_GENERAL_ERROR; + break; + } + + /* Update the last known error status */ + dbgErr = internalError; + return value; +} + + +/****************************************************** +* Threads +******************************************************/ + +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + osThreadAttr_t attr; + + if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE) + status = CY_RTOS_BAD_PARAM; + else if (stack != NULL && (0 != (((uint32_t)stack) & CY_RTOS_ALIGNMENT_MASK))) + status = CY_RTOS_ALIGNMENT_ERROR; + else + { + attr.name = name; + attr.attr_bits = osThreadJoinable; + attr.cb_size = osRtxThreadCbSize; + attr.stack_size = stack_size; + attr.priority = (osPriority_t)priority; + attr.tz_module = 0; + attr.reserved = 0; + + /* Allocate stack if NULL was passed */ + if ((uint32_t *)stack == NULL) + { + /* Note: 1 malloc so that it can be freed with 1 call when terminating */ + uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK; + attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size); + if (attr.cb_mem != NULL) + attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad); + } + else + { + attr.cb_mem = malloc(osRtxThreadCbSize); + attr.stack_mem = stack; + } + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *thread = osThreadNew((osThreadFunc_t)entry_function, arg, &attr); + CY_ASSERT((*thread == attr.cb_mem) || (*thread == NULL)); + status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_exit_thread() +{ + /* This does not have a return statement because the osThreadExit() function + * does not return so the return statement would be unreachable and causes a + * warning for IAR compiler. + */ + osThreadExit(); +} + +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadTerminate(*thread); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (running == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + switch (osThreadGetState(*thread)) + { + case osThreadInactive: + *state = CY_THREAD_STATE_INACTIVE; + break; + case osThreadReady: + *state = CY_THREAD_STATE_READY; + break; + case osThreadRunning: + *state = CY_THREAD_STATE_RUNNING; + break; + case osThreadBlocked: + *state = CY_THREAD_STATE_BLOCKED; + break; + case osThreadTerminated: + *state = CY_THREAD_STATE_TERMINATED; + break; + case osThreadError: + case osThreadReserved: + default: + *state = CY_THREAD_STATE_UNKNOWN; + break; + } + } + + return status; +} + +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadJoin(*thread); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*thread); + *thread = NULL; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + *thread = osThreadGetId(); + + return status; +} + + +/****************************************************** +* Mutexes +******************************************************/ + +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive) +{ + cy_rslt_t status; + osMutexAttr_t attr; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = osMutexPrioInherit; + if (recursive) + { + attr.attr_bits |= osMutexRecursive; + } + attr.cb_mem = malloc(osRtxMutexCbSize); + attr.cb_size = osRtxMutexCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *mutex = osMutexNew(&attr); + CY_ASSERT((*mutex == attr.cb_mem) || (*mutex == NULL)); + status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexAcquire(*mutex, timeout_ms); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexRelease(*mutex); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexDelete(*mutex); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*mutex); + *mutex = NULL; + } + } + + return status; +} + + +/****************************************************** +* Semaphores +******************************************************/ + +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount) +{ + cy_rslt_t status; + osSemaphoreAttr_t attr; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxSemaphoreCbSize); + attr.cb_size = osRtxSemaphoreCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *semaphore = osSemaphoreNew(maxcount, initcount, &attr); + CY_ASSERT((*semaphore == attr.cb_mem) || (*semaphore == NULL)); + status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreRelease(*semaphore); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count) +{ + cy_rslt_t status; + if (semaphore == NULL || count == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + *count = osSemaphoreGetCount(*semaphore); + status = CY_RSLT_SUCCESS; + } + return status; +} + +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreDelete(*semaphore); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*semaphore); + *semaphore = NULL; + } + } + + return status; +} + + +/****************************************************** +* Events +******************************************************/ + +#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL +#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL + +cy_rslt_t cy_rtos_init_event(cy_event_t *event) +{ + cy_rslt_t status; + osEventFlagsAttr_t attr; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxEventFlagsCbSize); + attr.cb_size = osRtxEventFlagsCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *event = osEventFlagsNew(&attr); + CY_ASSERT((*event == attr.cb_mem) || (*event == NULL)); + status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsSet(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsClear(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *bits = osEventFlagsGet(*event); + + return status; +} + +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + uint32_t flagOption; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny; + if (!clear) + flagOption |= osFlagsNoClear; + + statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL) + *bits = statusInternal; + else + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osEventFlagsDelete(*event); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*event); + *event = NULL; + } + } + + return status; +} + + +/****************************************************** +* Queues +******************************************************/ + +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) +{ + cy_rslt_t status; + osMessageQueueAttr_t attr; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_size = osRtxMessageQueueCbSize; + uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); + attr.mq_size = blockSize * length; + + /* Note: 1 malloc for both so that they can be freed with 1 call */ + uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; + attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); + if (attr.cb_mem != NULL) + attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad); + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *queue = osMessageQueueNew(length, itemsize, &attr); + CY_ASSERT((*queue == attr.cb_mem) || (*queue == NULL)); + status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_waiting == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_waiting = osMessageQueueGetCount(*queue); + + return status; +} + +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_spaces == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_spaces = osMessageQueueGetSpace(*queue); + + return status; +} + +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueReset(*queue); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueDelete(*queue); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*queue); + *queue = NULL; + } + } + + return status; +} + + +/****************************************************** +* Timers +******************************************************/ + +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg) +{ + cy_rslt_t status; + osTimerAttr_t attr; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxTimerCbSize); + attr.cb_size = osRtxTimerCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) + ? osTimerPeriodic + : osTimerOnce; + + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr ); + CY_ASSERT((*timer == attr.cb_mem) || (*timer == NULL)); + status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + uint32_t tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + { + uint32_t ticks = ((num_ms * tick_freq) / 1000); + statusInternal = osTimerStart(*timer, ticks); + status = error_converter(statusInternal); + } + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerStop(*timer); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((timer == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *state = osTimerIsRunning(*timer); + + return status; +} + +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerDelete(*timer); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*timer); + *timer = NULL; + } + } + + return status; +} + + +/****************************************************** +* Time +******************************************************/ + +cy_rslt_t cy_rtos_get_time(cy_time_t *tval) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + uint32_t tick_freq; + + if (tval == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + *tval = (cy_time_t)((osKernelGetTickCount() * 1000LL) / tick_freq); + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + statusInternal = osDelay(num_ms); + status = error_converter(statusInternal); + + return status; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_gpio.h new file mode 100644 index 00000000000..08d4e5bfb13 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_gpio.h @@ -0,0 +1,247 @@ +/***************************************************************************//** +* \file cyhal_gpio.h +* +* \brief +* Provides a high level interface for interacting with the GPIO on Cypress devices. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_gpio GPIO (General Purpose Input Output) +* \ingroup group_hal +* \{ +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/******************************************************************************* +* Defines +*******************************************************************************/ + +/** Integer representation of no connect pin (required to exist in all BSPs) */ +#define CYHAL_NC_PIN_VALUE (NC) + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Pin events */ +typedef enum { + CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ + CYHAL_GPIO_IRQ_RISE = 1 << 0, /**< Interrupt on rising edge */ + CYHAL_GPIO_IRQ_FALL = 1 << 1, /**< Interrupt on falling edge */ + CYHAL_GPIO_IRQ_BOTH = (CYHAL_GPIO_IRQ_RISE | CYHAL_GPIO_IRQ_FALL), /**< Interrupt on both rising and falling edges */ +} cyhal_gpio_event_t; + +/** Pin direction */ +typedef enum { + CYHAL_GPIO_DIR_INPUT, /**< Input pin */ + CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ + CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ +} cyhal_gpio_direction_t; + +/** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ +typedef enum { + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z. Use only for analog purpose */ + CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_STRONG, /**< Strong output. Output only. Output init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULL_NONE, /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ +} cyhal_gpio_drive_mode_t; + +/** GPIO callback function type */ +typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); + +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin + * + * @return The status of the init request + * + * Guidance for using gpio drive modes ( \ref cyhal_gpio_drive_mode_t for details). + * For default use drive modes: + * Input GPIO direction - \ref CYHAL_GPIO_DRIVE_NONE + * Output GPIO direction - \ref CYHAL_GPIO_DRIVE_STRONG + * Bidirectional GPIO - \ref CYHAL_GPIO_DRIVE_PULLUPDOWN + * \warning Don't use \ref CYHAL_GPIO_DRIVE_STRONG for input GPIO direction. It may cause an overcurrent issue. + */ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); + +/** Uninitialize the gpio peripheral and the cyhal_gpio_t object + * + * @param[in] pin Pin number + */ +void cyhal_gpio_free(cyhal_gpio_t pin); + +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. + * + * @param[in] pin The GPIO pin + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * + * @return The status of the configure request + */ +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode); + +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. + * + * @param[in] pin The GPIO object + * @param[in] value The value to be set (high = true, low = false) + */ +void cyhal_gpio_write(cyhal_gpio_t pin, bool value); + +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO object + * @return The value of the IO (true = high, false = low) + */ +bool cyhal_gpio_read(cyhal_gpio_t pin); + +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. + * @param[in] pin The GPIO object + */ +void cyhal_gpio_toggle(cyhal_gpio_t pin); + +/** Register/clear a callback handler for pin events
+ * + * This function will be called when one of the events enabled by \ref cyhal_gpio_enable_event occurs. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The pin number + * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. + * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL + */ +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); + +/** Enable or Disable the specified GPIO event
+ * + * When an enabled event occurs, the function specified by \ref cyhal_gpio_register_callback will be called. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The GPIO object + * @param[in] event The GPIO event + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) +#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; +/** \endcond */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#ifdef CYHAL_GPIO_IMPL_HEADER +#include CYHAL_GPIO_IMPL_HEADER +#endif /* CYHAL_GPIO_IMPL_HEADER */ + +/** \} group_hal_gpio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_sdio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_sdio.h new file mode 100644 index 00000000000..d5600efd997 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_sdio.h @@ -0,0 +1,366 @@ +/***************************************************************************//** +* \file cyhal_sdio.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SDIO interface. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) +* \ingroup group_hal +* \{ +* High level interface to the Secure Digital Input Output (SDIO). +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in \ref cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). +* +* The SDIO protocol is an extension of the SD +* interface for general I/O functions. Refer to the SD Specifications Part 1 SDIO +* Specifications Version 4.10 for more information on the SDIO protocol and specifications. +* +* +* \section subsection_sdio_features Features +* * Supports 4-bit interface +* * Supports Ultra High Speed (UHS-I) mode +* * Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes +* * Supports SDIO card interrupts in both 1-bit and 4-bit modes +* * Supports Standard capacity (SDSC), High capacity (SDHC) and Extended capacity (SDXC) memory +* +* \section subsection_sdio_quickstart Quick Start +* +* \ref cyhal_sdio_init initializes the SDIO peripheral and passes a pointer to the SDIO block through the **obj** object of type \ref cyhal_sdio_t. +* +* \section subsection_sdio_code_snippets Code Snippets +* +* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example +* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration +* +* \snippet sdio.c snippet_cyhal_sdio_simple_init +* +* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt +* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events. +* +* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback +* +* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands +* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands. +* +* \snippet sdio.c snippet_cyhal_sdio_send_command +* +* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer +* The following snippet shows how to start a bulk data transfer. +* +* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer +* +* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer +* +* The following snippet shows how to start an async data transfer. +* \snippet sdio.c snippet_cyhal_sdio_async_transfer +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Defines +*******************************************************************************/ + +#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ +#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ +#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ +#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ +#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ +#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ +#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ + +#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ +#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ +#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ +#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ +#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/ + +/* HAL return value defines */ + +/** \addtogroup group_hal_results_sdio SDIO HAL Results + * SDIO specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Incorrect parameter value define */ +#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT)) +/** Clock initialization error define */ +#define CYHAL_SDIO_RSLT_ERR_CLOCK \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR)) +/** Semaphore not initiated error define */ +#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED)) +/** Error define based on SDIO lower function return value */ +#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal))) +/** Define to indicate canceled operation */ +#define CYHAL_SDIO_RSLT_CANCELED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED)) +/** Transfers are not allowed after the SDIO block has allowed power mode transition. */ +#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR)) + +/** + * \} + */ + + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Commands that can be issued */ +typedef enum +{ + CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!< Go to idle state + CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!< Send a relative address + CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!< Send an OP IO + CYHAL_SDIO_CMD_SELECT_CARD = 7, //!< Send a card select + CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!< Go to inactive state + CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!< Perform a direct read/write + CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!< Perform an extended read/write +} cyhal_sdio_command_t; + +/** Types of transfer that can be performed */ +typedef enum +{ + CYHAL_READ, //!< Read from the card + CYHAL_WRITE //!< Write to the card +} cyhal_transfer_t; + +/** Types of events that could be asserted by SDIO */ +typedef enum { + /* Interrupt-based thread events */ + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!< Command Complete + CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete + CYHAL_SDIO_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped + CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDIO_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDIO_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDIO_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!< The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDIO_INT_A = 0x00200, //!< Reserved: set to 0 + CYHAL_SDIO_INT_B = 0x00400, //!< Reserved: set to 0 + CYHAL_SDIO_INT_C = 0x00800, //!< Reserved: set to 0 + CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!< Reserved: set to 0 + CYHAL_SDIO_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1 + CYHAL_SDIO_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set + + /* Non-interrupt-based thread events */ + CYHAL_SDIO_GOING_DOWN = 0x10000, //!< The interface is going away (eg: powering down for some period of time) + CYHAL_SDIO_COMING_UP = 0x20000, //!< The interface is back up (eg: came back from a low power state) + + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!< Is used to enable/disable all interrupts events +} cyhal_sdio_event_t; + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ + +/** @brief SDIO controller initial configuration */ +typedef struct +{ + uint32_t frequencyhal_hz; //!< Clock frequency, in hertz + uint16_t block_size; //!< Block size +} cyhal_sdio_cfg_t; + +/** Callback for SDIO events */ +typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ +/** Initialize the SDIO peripheral + * + * @param[out] obj Pointer to an SDIO object. + * The caller must allocate the memory for this object but the init + * function will initialize its contents. + * @param[out] clk The pin connected to the clk signal + * @param[in] cmd The pin connected to the command signal + * @param[in] data0 The pin connected to the data0 signal + * @param[in] data1 The pin connected to the data1 signal + * @param[in] data2 The pin connected to the data2 signal + * @param[in] data3 The pin connected to the data3 signal + * @return The status of the init request + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_1 for more information. + */ +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3); + +/** Release the SDIO block. + * + * @param[in,out] obj The SDIO object + */ +void cyhal_sdio_free(cyhal_sdio_t *obj); + +/** Configure the SDIO block with required parameters. Refer \ref cyhal_sdio_cfg_t for more information. + * + * @param[in,out] obj The SDIO object + * @param[in] config The SDIO configuration to apply + * @return The status of the configure request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); + +/** Sends command to the SDIO device. See \ref cyhal_sdio_command_t for list of available commands. + * + * This will block until the command is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] command The command to send to the SDIO device + * @param[in] argument The argument to the command + * @param[out] response The response from the SDIO device + * @return The status of the command transfer. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_3 for more information. + */ +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response); + +/** Performs a bulk data transfer. Sends \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command (CMD=53) which allows writing and reading of a large number of I/O registers with a single command. + * + * This will block until the transfer is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. + * @param[in] length The number of bytes to send + * @param[out] response The response from the SDIO device + * @return The status of the bulk transfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_4 for more information. + */ +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response); + +/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block. + * After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted. + * + * To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy() + * until it returns false. + * The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled + * after the asynchronous transfer is complete and in the condition they were + * enabled in before the transfer operation started. Handle these events in the interrupt callback. + * + * When the transfer is complete, the \ref CYHAL_SDIO_XFER_COMPLETE event will be raised. + * See \ref cyhal_sdio_register_callback and \ref cyhal_sdio_enable_event. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device + * @param[in] length The number of bytes to send + * @return The status of the async tranfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_5 for more information. + */ +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length); + +/** Checks if the specified SDIO is in use + * + * @param[in] obj The SDIO peripheral to check + * @return true if SDIO is in use. false, otherwise. + */ +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); + +/** Abort an SDIO transfer + * + * @param[in] obj The SDIO peripheral to stop + * @return The status of the abort_async request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); + +/** Register an SDIO event callback to be invoked when the event is triggered. + * + * This function will be called when one of the events enabled by \ref cyhal_sdio_enable_event occurs. + * + * @param[in] obj The SDIO object + * @param[in] callback The callback function which will be invoked when the event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when executed + * + * Refer \ref subsection_sdio_use_case_2 for more implementation. + */ +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); + +/** Enables callbacks to be triggered for specified SDIO events. Refer \ref cyhal_sdio_event_t for all events. + * + * @param[in] obj The SDIO object + * @param[in] event The SDIO event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable Set to true to enable events, or false to disable them + * + * Refer \ref subsection_sdio_use_case_2 for more information. + */ +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_sdio_register_irq cyhal_sdio_register_callback +#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; +typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SDIO_IMPL_HEADER +#include CYHAL_SDIO_IMPL_HEADER +#endif /* CYHAL_SDIO_IMPL_HEADER */ + +/** \} group_hal_sdio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_spi.h new file mode 100644 index 00000000000..f5ba47669f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/interface/cyhal_spi.h @@ -0,0 +1,383 @@ +/***************************************************************************//** +* \file cyhal_spi.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SPI. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_spi SPI (Serial Peripheral Interface) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. +* +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_results_spi SPI HAL Results + * SPI specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Bad argument */ +#define CYHAL_SPI_RSLT_BAD_ARGUMENT \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) +/** Failed to initialize SPI clock */ +#define CYHAL_SPI_RSLT_CLOCK_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1)) +/** Failed to Transfer SPI data */ +#define CYHAL_SPI_RSLT_TRANSFER_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2)) +/** Provided clock is not supported by SPI */ +#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6)) +/** The requested resource type is invalid */ +#define CYHAL_SPI_RSLT_ERR_INVALID_PIN \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) +/** Cannot configure SSEL signal */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_CONFIG_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 8)) +/** Cannot switch SSEL - device is busy or incorrect pin provided */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 9)) + +/** + * \} + */ + +/** Compatibility define for cyhal_spi_set_frequency. */ +#define cyhal_spi_frequency cyhal_spi_set_frequency + +/** SPI interrupt triggers */ +typedef enum { + /** All transfer data has been moved into data FIFO */ + CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, + /** Transfer complete. */ + CYHAL_SPI_IRQ_DONE = 1 << 2, + /** An error occurred while transferring data */ + CYHAL_SPI_IRQ_ERROR = 1 << 3, +} cyhal_spi_event_t; + +/** SPI Slave Select polarity */ +typedef enum { + /** SSEL signal is active low */ + CYHAL_SPI_SSEL_ACTIVE_LOW = 0, + /** SSEL signal is active high */ + CYHAL_SPI_SSEL_ACTIVE_HIGH = 1, +} cyhal_spi_ssel_polarity_t; + +/** Handler for SPI interrupts */ +typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); + +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the LSB is sent first. */ +#define CYHAL_SPI_MODE_FLAG_LSB (0x01u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPHA=1. */ +#define CYHAL_SPI_MODE_FLAG_CPHA (0x02u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPOL=1. */ +#define CYHAL_SPI_MODE_FLAG_CPOL (0x04u) +/** Creates a \ref cyhal_spi_mode_t value given the cpol, cpha, lsb values. */ +#define CYHAL_SPI_MODE(cpol, cpha, lsb) (((cpol > 0) ? CYHAL_SPI_MODE_FLAG_CPOL : 0) | \ + ((cpha > 0) ? CYHAL_SPI_MODE_FLAG_CPHA : 0) | \ + (( lsb > 0) ? CYHAL_SPI_MODE_FLAG_LSB : 0)) + +/** SPI operating modes */ +typedef enum +{ + /** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_00_MSB = CYHAL_SPI_MODE(0, 0, 0), + /** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_00_LSB = CYHAL_SPI_MODE(0, 0, 1), + /** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_01_MSB = CYHAL_SPI_MODE(0, 1, 0), + /** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_01_LSB = CYHAL_SPI_MODE(0, 1, 1), + /** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_10_MSB = CYHAL_SPI_MODE(1, 0, 0), + /** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_10_LSB = CYHAL_SPI_MODE(1, 0, 1), + /** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_11_MSB = CYHAL_SPI_MODE(1, 1, 0), + /** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1), +} cyhal_spi_mode_t; + +/** @brief Initial SPI configuration. */ +typedef struct +{ + cyhal_spi_mode_t mode; //!< The operating mode + uint8_t data_bits; //!< The number of bits per transfer + bool is_slave; //!< Whether the peripheral is operating as slave or master +} cyhal_spi_cfg_t; + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj Pointer to a SPI object. The caller must allocate the memory + * for this object but the init function will initialize its contents. + * @param[in] mosi The pin to use for MOSI + * @note At least MOSI or MISO pin should be non-NC + * @param[in] miso The pin to use for MISO + * @note At least MOSI or MISO pin should be non-NC + * @param[in] sclk The pin to use for SCLK + * @note This pin cannot be NC + * @param[in] ssel The pin to use for SSEL + * @note Provided pin will be configured for \ref CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed + * (as well as additional ssel pins can be added) by \ref cyhal_spi_slave_select_config and \ref cyhal_spi_select_active_ssel + * functions. This pin can be NC. + * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[in] bits The number of bits per frame + * @note bits should be 8 or 16 + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] is_slave false for master mode or true for slave mode operation + * @return The status of the init request + */ +cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, + const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave); + +/** Release a SPI object + * + * Return the peripheral, pins and clock owned by the SPI object to their reset state + * @param[in,out] obj The SPI object to deinitialize + */ +void cyhal_spi_free(cyhal_spi_t *obj); + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + * @return The status of the set_frequency request + */ +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); + +/** Configures provided ssel pin to work as SPI slave select with specified polarity. + * + * Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching + * between configured slave select pins is done by \ref cyhal_spi_select_active_ssel function. + * Unless modified with this function, the SSEL pin provided as part of \ref cyhal_spi_init is the default. + * @param[in] obj The SPI object to add slave select for + * @param[in] ssel Slave select pin to be added + * @param[in] polarity Polarity of slave select + * @return The status of ssel pin configuration + */ +cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity); + +/** Selects an active slave select line from one of available. + * + * This function is applicable for the master and slave. + * SSEL pin should be configured by \ref cyhal_spi_slave_select_config or \ref cyhal_spi_init functions prior + * to selecting it as active. The active slave select line will automatically be toggled as part of any transfer. + * @param[in] obj The SPI object for switching + * @param[in] ssel Slave select pin to be set as active + * @return CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL + */ +cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel); + +/** Synchronously get a received value out of the SPI receive buffer + * + * In Master mode - transmits fill-in value and read the data from RxFifo + * In Slave mode - Blocks until a value is available + * + * @param[in] obj The SPI peripheral to read + * @param[in] value The value received + * @return The status of the read request + * @note + * - In Master mode, MISO pin required to be non-NC for this API to operate + * - In Slave mode, MOSI pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); + +/** Synchronously send a byte out + * + * In Master mode transmits value to slave and read/drop a value from the RxFifo. + * In Slave mode writes a value to TxFifo + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return The status of the write request + * @note + * - In Master mode, MOSI pin required to be non-NC for this API to operate + * - In Slave mode, MISO pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); + +/** Synchronously Write a block out and receive a value + * + * The total number of bytes sent and received will be the maximum of tx_length + * and rx_length. The bytes written will be padded (at the end) with the value + * given by write_fill. + * + * This function will block for the duration of the transfer. \ref cyhal_spi_transfer_async + * can be used for non-blocking transfers. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx Pointer to the byte-array of data to write to the device + * @param[in,out] tx_length Number of bytes to write, updated with the number actually written + * @param[out] rx Pointer to the byte-array of data to read from the device + * @param[in,out] rx_length Number of bytes to read, updated with the number actually read + * @param[in] write_fill Default data transmitted while performing a read + * @return The status of the transfer request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill); + +/** Start an asynchronous SPI transfer. + * + * This will transfer `rx_length` bytes into the buffer pointed to by `rx`, while simultaneously transfering + * `tx_length` bytes of data from the buffer pointed to by `tx`, both in the background. + * When the transfer is complete, the @ref CYHAL_SPI_IRQ_DONE event will be raised. + * See @ref cyhal_spi_register_callback and @ref cyhal_spi_enable_event. + * \note For blocking transfers cyhal_spi_transfer can be used. + * + * @param[in] obj The SPI object that holds the transfer information + * @param[in] tx The transmit buffer + * @param[in,out] tx_length The number of bytes to transmit + * @param[out] rx The receive buffer + * @param[in,out] rx_length The number of bytes to receive + * @return The status of the transfer_async request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length); + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return Indication of whether the SPI is still transmitting + */ +bool cyhal_spi_is_busy(cyhal_spi_t *obj); + +/** Abort an SPI transfer + * + * @param[in] obj The SPI peripheral to stop + * @return The status of the abort_async request + */ +cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); + +/** Register a SPI callback handler + * + * This function will be called when one of the events enabled by \ref cyhal_spi_enable_event occurs. + * + * @param[in] obj The SPI object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); + +/** Configure SPI interrupt. This function is used for word-approach + * + * When an enabled event occurs, the function specified by \ref cyhal_spi_register_callback will be called. + * + * @param[in] obj The SPI object + * @param[in] event The SPI event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +typedef cyhal_spi_event_t cyhal_spi_irq_event_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SPI_IMPL_HEADER +#include CYHAL_SPI_IMPL_HEADER +#endif /* CYHAL_SPI_IMPL_HEADER */ + +/** \} group_hal_spi */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_hal.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_hal.c new file mode 100644 index 00000000000..f5a0716697c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_hal.c @@ -0,0 +1,63 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "cyhal.h" +#include "mbed_thread.h" +#include "mbed_wait_api.h" + +static cyhal_sdio_t sdio_obj; + +/* Edit Pin configuration */ +const pinconfig_t PinConfig[] = { + + [CYBSP_WIFI_WL_REG_ON] = WIFI_WL_REG_ON, +#ifdef CYBSP_WIFI_32K_CLK + [CYBSP_WIFI_32K_CLK] = WIFI_32K_CLK, +#endif /* CYBSP_WIFI_32K_CLK */ + [CYBSP_LED1 ] = BSP_LED1, + [CYBSP_LED2 ] = BSP_LED2, + [CYBSP_WIFI_SDIO_CMD] = WIFI_SDIO_CMD, + [CYBSP_WIFI_SDIO_CLK] = WIFI_SDIO_CLK, + [CYBSP_WIFI_SDIO_D0 ] = WIFI_SDIO_D0, + [CYBSP_WIFI_SDIO_D1 ] = WIFI_SDIO_D1, + [CYBSP_WIFI_SDIO_D2 ] = WIFI_SDIO_D2, + [CYBSP_WIFI_SDIO_D3 ] = WIFI_SDIO_D3, + [CYBSP_SDIO_OOB_IRQ ] = WIFI_SDIO_OOB_IRQ //VIKR +}; + +void Cy_SysLib_Delay(uint32_t milliseconds) +{ + thread_sleep_for(milliseconds); +} + +void Cy_SysLib_DelayUs(uint16_t microseconds) +{ + wait_us(microseconds); +} + +void cyhal_system_delay_ms(uint32_t milliseconds) +{ + Cy_SysLib_Delay(milliseconds); +} + +cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_syslib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_syslib.h new file mode 100644 index 00000000000..7671d853cfc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_syslib.h @@ -0,0 +1,592 @@ +/***************************************************************************//** +* \file cy_syslib.h +* \version 2.40.1 +* +* Provides an API declaration of the SysLib driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_syslib +* \{ +* The system libraries provide APIs that can be called in the user application +* to handle the timing, logical checking or register. +* +* The functions and other declarations used in this driver are in cy_syslib.h. +* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* and declarations in the PDL. +* +* The SysLib driver contains a set of different system functions. These functions +* can be called in the application routine. Major features of the system library: +* * Delay functions +* * The register Read/Write macro +* * Assert and Halt +* * Assert Classes and Levels +* * A software reset +* * Reading the reset cause +* * An API to invalidate the flash cache and buffer +* * Data manipulation macro +* * A variable type definition from MISRA-C which specifies signedness +* * Cross compiler compatible attributes +* * Getting a silicon-unique ID API +* * Setting wait states API +* * Resetting the backup domain API +* * APIs to serve Fault handler +* +* \section group_syslib_configuration Configuration Considerations +* Assertion Usage
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the +* program is running correctly. It is a convenient way to insert sanity checks. +* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of +* the PDL library. The behavior of the macro is as follows: if the expression +* passed to the macro is false, output an error message that includes the file +* name and line number, and then halts the CPU. \n +* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function. +* This is a weakly linked function. The default implementation stores the file +* name and line number of the ASSERT into global variables, cy_assertFileName +* and cy_assertLine . It then calls the Cy_SysLib_Halt() function. +* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing. +* +* The PDL source code uses this assert mechanism extensively. It is recommended +* that you enable asserts when debugging firmware. \n +* Assertion Classes and Levels
+* The PDL defines three assert classes, which correspond to different kinds +* of parameters. There is a corresponding assert "level" for each class. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Class MacroLevel MacroType of check
CY_ASSERT_CLASS_1CY_ASSERT_L1A parameter that could change between different PSoC devices +* (e.g. the number of clock paths)
CY_ASSERT_CLASS_2CY_ASSERT_L2A parameter that has fixed limits such as a counter period
CY_ASSERT_CLASS_3CY_ASSERT_L3A parameter that is an enum constant
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. +* This is a compiler command line argument, similar to how the DEBUG / NDEBUG +* macro is passed. \n +* Enabling any class also enables any lower-numbered class. +* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three +* classes. The following example shows the command-line option to enable all +* the assert levels: +* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode +* \note The use of special characters, such as spaces, parenthesis, etc. must +* be protected with quotes. +* +* After CY_ASSERT_LEVEL is defined, firmware can use +* one of the three level macros to make an assertion. For example, if the +* parameter can vary between devices, firmware uses the L1 macro. +* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode +* If the parameter has bounds, firmware uses L2. +* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode +* If the parameter is an enum, firmware uses L3. +* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode +* Each check uses the appropriate level macro for the kind of parameter being checked. +* If a particular assert class/level is not enabled, then the assert does nothing. +* +* \section group_syslib_more_information More Information +* Refer to the technical reference manual (TRM). +* +* \section group_syslib_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.This si required by design of the Cy_SysLib_Halt function.
18.4RUnions shall not be used.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers +* content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be +* defined, redefined or undefined.The driver defines the macros with leading underscores +* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
+* +* \section group_syslib_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.
Minor documentation edits.Documentation update and clarification.
Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
2.20Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.Provided support for the PDL static library in Release mode.
Minor documentation edits.Documentation update and clarification.
2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETRegister access simplification.
Removed the Cy_SysLib_GetNumHfclkResetCause API function.This feature is not supported by SRSS_ver1.
Added register access layer. Use register access macros instead +* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* not need to be recompiled for each supported part number.
2.0.1Minor documentation editsDocumentation update and clarification
2.0 +* Added Cy_SysLib_ResetBackupDomain() API implementation. \n +* Added CY_NOINLINE attribute implementation. \n +* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n +* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n +* Optimized Cy_SysLib_SetWaitStates() API implementation. +* Improvements made based on usability feedback.
Added Assertion Classes and Levels.For error checking, parameter validation and status returns in the PDL API.
Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.To store debug information into a non-zero init area for future analysis.
Removed CY_WEAK attribute implementation.CMSIS __WEAK attribute should be used instead.
1.0Initial version
+* +* \defgroup group_syslib_macros Macros +* \defgroup group_syslib_functions Functions +* \defgroup group_syslib_data_structures Data Structures +* \defgroup group_syslib_enumerated_types Enumerated Types +* +*/ + +#if !defined(CY_SYSLIB_H) +#define CY_SYSLIB_H + +#include +#include + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/** Get the lower 8 bits of a 16-bit value. */ +#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) +/** Get the upper 8 bits of a 16-bit value. */ +#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) + +/** Get the lower 16 bits of a 32-bit value. */ +#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) +/** Get the upper 16 bits of a 32-bit value. */ +#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) + +/** Swap the byte ordering of a 16-bit value */ +#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) + +/** Swap the byte ordering of a 32-bit value */ +#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ + (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) + +/** Swap the byte ordering of a 64-bit value */ +#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ + CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) + +/* MISRA rule 6.3 recommends using specific-length typedef for the basic + * numerical types of signed and unsigned variants of char, float, and double. + */ +typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ +typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ +typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ + + +/******************************************************************************* +* Macro Name: CY_GET_REG8(addr) +****************************************************************************//** +* +* Reads the 8-bit value from the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG8(addr, value) +****************************************************************************//** +* +* Writes an 8-bit value to the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG16(addr) +****************************************************************************//** +* +* Reads the 16-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG16(addr, value) +****************************************************************************//** +* +* Writes the 16-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG24(addr) +****************************************************************************//** +* +* Reads the 24-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) + + +/******************************************************************************* +* Macro Name: CY_SET_REG24(addr, value) +****************************************************************************//** +* +* Writes the 24-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG24(addr, value) do \ + { \ + (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ + (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ + (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ + } \ + while(0) + + +/******************************************************************************* +* Macro Name: CY_GET_REG32(addr) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG32(addr, value) +****************************************************************************//** +* +* Writes the 32-bit value to the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD32U +****************************************************************************//** +* +* The macro for setting a register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the register. +* +*******************************************************************************/ +#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) + + +/******************************************************************************* +* Macro Name: CY_REG32_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 32-bit register. +* +*******************************************************************************/ +#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD16U +****************************************************************************//** +* +* The macro for setting a 16-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 16-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ + ((uint16_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG16_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 16-bit register. +* +*******************************************************************************/ +#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD8U +****************************************************************************//** +* +* The macro for setting a 8-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 8-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ + ((uint8_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG8_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 8-bit register. +* +*******************************************************************************/ +#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _BOOL2FLD +****************************************************************************//** +* +* Returns a field mask if the value is not false. +* Returns 0, if the value is false. +* +*******************************************************************************/ +#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) + + +/******************************************************************************* +* Macro Name: _FLD2BOOL +****************************************************************************//** +* +* Returns true, if the value includes the field mask. +* Returns false, if the value doesn't include the field mask. +* +*******************************************************************************/ +#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUND +****************************************************************************//** +* +* Calculates a / b with rounding to the nearest integer, +* a and b must have the same sign. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUNDUP +****************************************************************************//** +* +* Calculates a / b with rounding up if remainder != 0, +* both a and b must be positive. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) + +typedef uint32_t cy_status; +/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ +typedef uint32_t cystatus; +typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ +typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ +typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ +typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ +typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ +typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ +typedef float float32; /**< Alias to float for backward compatibility */ +typedef double float64; /**< Alias to double for backward compatibility */ +typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ +typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; /**< Alias to char for backward compatibility */ +typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ +typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ +typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ + +/** The ARM 32-bit Return error / status code for backward compatibility. +* Do not use them in your code. +*/ +#define CY_RET_SUCCESS (0x00U) /* Successful */ +#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CY_RET_MEMORY (0x03U) /* A memory-related failure */ +#define CY_RET_LOCKED (0x04U) /* A resource lock failure */ +#define CY_RET_EMPTY (0x05U) /* No more objects available */ +#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CY_RET_FINISHED (0x08U) /* Operation is completed */ +#define CY_RET_CANCELED (0x09U) /* Operation is canceled */ +#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */ +#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */ + +/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. +* Do not use them in your code. +*/ +#define CYRET_SUCCESS (0x00U) /* Successful */ +#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CYRET_MEMORY (0x03U) /* A memory-related failure */ +#define CYRET_LOCKED (0x04U) /* A resource lock failure */ +#define CYRET_EMPTY (0x05U) /* No more objects available */ +#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08U) /* Operation is completed */ +#define CYRET_CANCELED (0x09U) /* Operation is canceled */ +#define CYRET_TIMEOUT (0x10U) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */ + +/** \} group_syslib_functions */ + +#endif /* CY_SYSLIB_H */ + +/** \} group_syslib */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_utils.h new file mode 100644 index 00000000000..db8c143f361 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cy_utils.h @@ -0,0 +1,81 @@ +/***************************************************************************//** +* \file cy_utils.h +* +* \brief +* Basic utility macros and functions. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_utils Utilities +* \ingroup group_abstraction +* \{ +* Basic utility macros and functions. +* +* \defgroup group_utils_macros Macros +*/ + +#pragma once + +#include "stdint.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_utils_macros +* \{ +*/ + +/** Simple macro to supress the unused parameter warning by casting to void. */ +#define CY_UNUSED_PARAMETER(x) ( (void)(x) ) + +/** Halt the processor in the debug state + * @return + */ +static inline uint32_t CY_HALT() +{ + __asm(" bkpt 1"); + return 0; +} + +#ifdef CY_ASSERT +#undef CY_ASSERT +#endif /* ifdef(CY_ASSERT) */ + +/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */ +#if defined(NDEBUG) || defined(CY_NO_ASSERT) + #define CY_ASSERT(x) CY_UNUSED_PARAMETER(x) +#else + #define CY_ASSERT(x) do { \ + if(!(x)) \ + { \ + CY_HALT(); \ + } \ + } while(0) +#endif /* defined(NDEBUG) */ + +/** \} group_utils_macros */ + +#ifdef __cplusplus +} +#endif + +/** \} group_utils */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cybsp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cybsp.h new file mode 100644 index 00000000000..06226f327bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cybsp.h @@ -0,0 +1,50 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cycfg.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cycfg.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cycfg.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal.h new file mode 100644 index 00000000000..e56be0e0132 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal.h @@ -0,0 +1,52 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "whd_config.h" +#include "cyhal_hw_types.h" +#include "cyhal_gpio.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +typedef enum +{ + CYBSP_WIFI_WL_REG_ON, + CYBSP_WIFI_32K_CLK, + CYBSP_LED1, + CYBSP_LED2, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3, + CYBSP_SDIO_OOB_IRQ, + CYBSP_WIFI_MAX, +} wwd_sdio_pin_t; + +void cyhal_system_delay_ms(uint32_t milliseconds); +cy_rslt_t sdio_enable_high_speed(void); + +#if defined(__cplusplus) +} +#endif + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_gpio.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_gpio.cpp new file mode 100644 index 00000000000..c4bf1a9dc46 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_gpio.cpp @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 GPIOs on WHD driver + */ + +#include +#include "cyhal.h" +#include "cybsp.h" +#include "mbed.h" +#include "wiced_filesystem.h" + +extern pinconfig_t PinConfig[]; + +/******************************************************************************* +* Internal +*******************************************************************************/ +static mbed::InterruptIn *oob_irq; +static cyhal_gpio_event_t oob_event = CYHAL_GPIO_IRQ_FALL; +static cyhal_gpio_event_callback_t oob_handler; +static void *oob_handler_arg; + +/******************************************************************************* +* Internal Interrrupt Service Routine +*******************************************************************************/ +static void cb() +{ + oob_handler(oob_handler_arg, oob_event); +} + +/******************************************************************************* +* HAL Implementation +*******************************************************************************/ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + // Workaround to enable GPIOJ clock + if (pin == CYBSP_WIFI_WL_REG_ON) { + __HAL_RCC_GPIOJ_CLK_ENABLE(); + // Ensure FS and BlockDevice are initialized on time if needed + wiced_filesystem_init(); + } + // Ignore the parameter and take the pin config directly from a static array defintions + HAL_GPIO_Init(PinConfig[pin].port, &PinConfig[pin].config); + if (direction == CYHAL_GPIO_DIR_OUTPUT) { + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (initVal) ? GPIO_PIN_SET : GPIO_PIN_RESET); + } + // Workaround to initialize sdio interface without cypress bsp init + if (pin == CYBSP_WIFI_WL_REG_ON) { + cyhal_sdio_t *sdio_p = cybsp_get_wifi_sdio_obj(); + ret = cyhal_sdio_init(sdio_p, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); + } + return ret; +} + +void cyhal_gpio_write(cyhal_gpio_t pin, bool value) +{ + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (value) ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t handler, void *handler_arg) +{ + if (handler && handler_arg && (oob_irq == NULL)) { + oob_irq = new mbed::InterruptIn(WL_HOST_WAKE); + oob_handler = handler; + oob_handler_arg = handler_arg; + } +} + +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable) +{ + oob_event = event; + if (enable) { + if (event == CYHAL_GPIO_IRQ_RISE) { + oob_irq->rise(cb); + } + if (event == CYHAL_GPIO_IRQ_FALL) { + oob_irq->fall(cb); + } + } else if (oob_irq != NULL) { + delete oob_irq; + } +} + +void cyhal_gpio_free(cyhal_gpio_t pin) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_hw_types.h new file mode 100644 index 00000000000..1f872abb373 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_hw_types.h @@ -0,0 +1,112 @@ +/***************************************************************************//** +* \file cyhal_hw_types_template.h +* +* \brief +* Provides a template for configuration resources used by the HAL. Items +* here need to be implemented for each HAL port. It is up to the environment +* being ported into what the actual types are. There are some suggestions below +* but these are not required. All that is required is that the type is defined; +* it does not matter to the HAL what type is actually chosen for the +* implementation +* All TODOs and references to 'PORT' need to be replaced by with meaningful +* values for the device being supported. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_hw_types PORT Hardware Types + * \ingroup group_hal_PORT + * \{ + * Struct definitions for configuration resources in the PORT. + * + * \defgroup group_hal_hw_types_data_structures Data Structures + */ + +#pragma once +#include +#include "stm32h7xx_hal.h" +#include "PinNames.h" + +/* + #include "TODO: Port specific header file" + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef CYHAL_ISR_PRIORITY_DEFAULT +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ +#define CYHAL_ISR_PRIORITY_DEFAULT (7) +#endif + +/** + * \addtogroup group_hal_hw_types_data_structures + * \{ + */ + +typedef int32_t cyhal_gpio_t; + +/** GPIO object */ +typedef struct +{ + GPIO_TypeDef *port; + GPIO_InitTypeDef config; +} pinconfig_t; + +/** Clock divider object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *div_type; +} cyhal_clock_divider_t; + +/** Clock object */ +typedef struct +{ + //For backwards compatibility with cyhal_clock_divider_t only. Do not use going forward. + int div_type; /*!< Deprecated */ + uint8_t div_num; /*!< Deprecated */ + //End BWC items + int block; + uint8_t channel; + bool reserved; +} cyhal_clock_t; + +/** SDIO object */ +typedef void* *cyhal_sdio_t; + +/** SPI object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *empty; +} cyhal_spi_t; + +#include "whd_config.h" +#include "whd_debug.h" + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_hw_types */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c new file mode 100644 index 00000000000..34aa5498e1a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c @@ -0,0 +1,483 @@ +/* + * Copyright 2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 SDIO on WHD driver + */ + +#include +#include +#include "whd_thread.h" +#include "bus_protocols/whd_bus_sdio_protocol.h" +#include "cyabs_rtos.h" +#include "cyhal_sdio.h" + +#define SDIO_RESPONSE_SHORT SDMMC_RESPONSE_SHORT +#define SDIO_WAIT_NO SDMMC_WAIT_NO +#define SDIO_CPSM_ENABLE SDMMC_CPSM_ENABLE +#define SDIO_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO_FLAG_CMDACT (SDMMC_STA_CPSMACT | SDMMC_STA_DPSMACT) +#define SDIO_TRANSFER_DIR_TO_SDIO SDMMC_TRANSFER_DIR_TO_SDMMC +#define SDIO_TRANSFER_DIR_TO_CARD SDMMC_TRANSFER_DIR_TO_CARD +#define SDIO_TRANSFER_MODE_BLOCK SDMMC_TRANSFER_MODE_BLOCK +#define SDIO_DPSM_ENABLE SDMMC_DPSM_ENABLE +#define SDIO_DPSM_DISABLE SDMMC_DPSM_DISABLE +#define SDIO_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN /* 1 << 11 */ +#define SDIO_DCTRL_DTMODE_1 SDMMC_DCTRL_DTMODE_1 /* 1<<3 */ +#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR +#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR +#define SDIO_STA_TXACT SDMMC_STA_CPSMACT +#define SDIO_STA_RXACT SDMMC_STA_DPSMACT +#define SDIO_STA_CMDREND SDMMC_STA_CMDREND +#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT +#define SDIO_CMD_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO SDMMC1 + +#define COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS (100000) +#define BUS_LEVEL_MAX_RETRIES 10 + +#define SDIO_CMD_5 5 +#define SDIO_CMD_53 53 + +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!b)?a:b + +extern pinconfig_t PinConfig[]; +extern SD_HandleTypeDef hsd; + +/* for debug prints only */ +//static int num = 0; + +static uint32_t dctrl; + +static whd_driver_t whd_handler; +static cyhal_sdio_irq_handler_t sdio_irq_handler; + +static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +static uint8_t *user_data; +static uint32_t user_data_size; +static uint8_t *dma_data_source; +static uint32_t dma_transfer_size; +static cyhal_transfer_t current_transfer_direction; + +static cy_semaphore_t sdio_transfer_finished_semaphore; +static volatile uint32_t sdio_transfer_failed = 0; +static volatile uint32_t irqstatus = 0; +static int current_command = 0; + +static cy_rslt_t sdio_enable_high_speed(void) +{ + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; + + SDMMC_Init(SDMMC1, sdio_init_structure); + return CY_RSLT_SUCCESS; +} + +static uint32_t find_optimal_block_size(uint32_t data_size) +{ + if (data_size > (uint32_t) 256) { + return 512; + } + if (data_size > (uint32_t) 128) { + return 256; + } + if (data_size > (uint32_t) 64) { + return 128; + } + if (data_size > (uint32_t) 32) { + return 64; + } + if (data_size > (uint32_t) 16) { + return 32; + } + if (data_size > (uint32_t) 8) { + return 16; + } + if (data_size > (uint32_t) 4) { + return 8; + } + if (data_size > (uint32_t) 2) { + return 4; + } + + return 4; +} + +static uint32_t sdio_get_blocksize(uint32_t blocksize) +{ + uint32_t n = 0; + blocksize >>= 1; + while (blocksize) { + n++; + blocksize >>= 1; + } + n <<= 4; + return n; +} + +static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t block_size, uint8_t *data, uint16_t data_size) +{ + /* Setup a single transfer using the temp buffer */ + user_data = data; + user_data_size = data_size; + dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); + + if (direction == CYHAL_WRITE) { + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + memcpy(temp_dma_buffer, data, data_size); + dma_data_source = temp_dma_buffer; + } else { + dma_data_source = (uint8_t *)temp_dma_buffer; + //VIKR + //memset(dma_data_source,0x12,data_size); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Cache-Invalidate the output from DMA */ + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + } + + SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; + SDIO->DLEN = dma_transfer_size; + dctrl = sdio_get_blocksize(block_size) | ((direction == CYHAL_READ) ? SDIO_TRANSFER_DIR_TO_SDIO : SDIO_TRANSFER_DIR_TO_CARD) | SDIO_TRANSFER_MODE_BLOCK | SDIO_DPSM_DISABLE | SDIO_DCTRL_SDIOEN; + SDIO->DCTRL = dctrl; + + SDMMC1->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + SDMMC1->IDMABASE0 = (uint32_t) dma_data_source; +} + +static void sdio_enable_bus_irq(void) +{ + SDMMC1->MASK = SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_CMDREND | SDMMC_IT_CMDSENT; +} + +void SDMMC1_IRQHandler(void) +{ + uint32_t intstatus = SDIO->STA; + + irqstatus = intstatus; + //VIKR | SDIO_STA_STBITERR ) + if ((intstatus & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0) { + WPRINT_WHD_DEBUG(("sdio error flagged\n")); + sdio_transfer_failed = intstatus; + SDIO->ICR = (uint32_t) 0xffffffff; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } else { + if ((intstatus & (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT)) != 0) { + if ((SDMMC1->RESP1 & 0x800) != 0) { + sdio_transfer_failed = irqstatus; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + + /* Clear all command/response interrupts */ + SDMMC1->ICR = (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT); + } + + /* Check whether the external interrupt was triggered */ + if (intstatus & SDMMC_STA_SDIOIT) { + /* Clear the interrupt */ + SDMMC1->ICR = SDMMC_STA_SDIOIT; + /* Inform WICED WWD thread */ + sdio_irq_handler(whd_handler, CYHAL_SDIO_CARD_INTERRUPT); + } + + if (intstatus & SDMMC_STA_DATAEND) { + SDMMC1->ICR = SDMMC_STA_DATAEND; + SDMMC1->DLEN = 0; + SDMMC1->DCTRL = SDMMC_DCTRL_SDIOEN; + SDMMC1->IDMACTRL = SDMMC_DISABLE_IDMA; + SDMMC1->CMD = 0; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + } +} + +//void sdio_dma_irq(void) +//{ +// /* Clear interrupt */ +// DMA2->LIFCR = (uint32_t)(0x3F << 22); +// cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); +//} + +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + HAL_GPIO_Init(PinConfig[cmd].port, &PinConfig[cmd].config); + HAL_GPIO_Init(PinConfig[clk].port, &PinConfig[clk].config); + HAL_GPIO_Init(PinConfig[data0].port, &PinConfig[data0].config); + HAL_GPIO_Init(PinConfig[data1].port, &PinConfig[data1].config); + HAL_GPIO_Init(PinConfig[data2].port, &PinConfig[data2].config); + HAL_GPIO_Init(PinConfig[data3].port, &PinConfig[data3].config); + + /* Reset SDIO Block */ + SDMMC_PowerState_OFF(SDMMC1); + __HAL_RCC_SDMMC1_FORCE_RESET(); + __HAL_RCC_SDMMC1_RELEASE_RESET(); + + /* Enable the SDIO Clock */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Disable DCache for STM32H7 family */ + SCB_CleanDCache(); + SCB_DisableDCache(); +#endif + + WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); + + // Lower speed configuration + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_INIT_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_1B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + ret = SDMMC_Init(SDMMC1, sdio_init_structure); + ret |= SDMMC_PowerState_ON(SDMMC1); + ret |= SDMMC_SetSDMMCReadWaitMode(SDMMC1, SDMMC_READ_WAIT_MODE_CLK); + if (ret) { + return ret; + } + + /* Clear all SDIO interrupts */ + SDMMC1->ICR = (uint32_t) 0xffffffff; + + /* Turn on SDIO IRQ */ + /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */ + /* otherwise FreeRTOS will not be able to mask the interrupt */ + /* keep in mind that ARMCM7 interrupt priority logic is inverted, the highest value */ + /* is the lowest priority */ + HAL_NVIC_EnableIRQ((IRQn_Type) SDMMC1_IRQn); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0); + + WPRINT_WHD_DEBUG(("after enable sdio: %p\n", sdio_transfer_finished_semaphore)); + + if (cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0) != WHD_SUCCESS) { + cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); + return -1; + } + + WPRINT_WHD_DEBUG(("cy_rtos_init_semaphore: %p\n", sdio_transfer_finished_semaphore)); + + return ret; +} + +void cyhal_sdio_free(cyhal_sdio_t *obj) +{ + //TODO +} + +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) +{ + return sdio_enable_high_speed(); +} + +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t *response) +{ + uint32_t loop_count = 0; + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t temp_sta; + + if (response != NULL) { + *response = 0; + } + current_command = 0; + +restart: + SDIO->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + result = -1; + goto exit; + } + + /* Send the command */ + SDIO->ARG = argument; + SDIO->CMD = (uint32_t)(command | SDIO_RESPONSE_SHORT | SDIO_WAIT_NO | SDIO_CPSM_ENABLE); + loop_count = (uint32_t) COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS; + do { + temp_sta = SDIO->STA; + loop_count--; + if (loop_count == 0 /*|| ((response != NULL) && ((temp_sta & SDIO_ERROR_MASK) != 0))*/) { + WPRINT_WHD_DEBUG(("Restart single access loop count %ld stat %lx\n", loop_count, temp_sta)); + HAL_Delay(10U); + goto restart; + } + } while ((temp_sta & SDIO_FLAG_CMDACT) != 0); + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + if (result) { + WPRINT_WHD_ERROR(("SDIO->POWER %lx \n", SDIO->POWER)); + WPRINT_WHD_ERROR(("SDIO->CLKCR %lx \n", SDIO->CLKCR)); + WPRINT_WHD_ERROR(("result %lx \n", result)); + WPRINT_WHD_ERROR(("cyhal_sdio_send_cmd %s\n", (result == 0) ? "Passed" : "Failed")); + while (1); + } + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 0x%x arg 0x%x resp 0x%x\n",num++,(direction!=CYHAL_READ)?"Write":"Read",command,argument,(response)?*response:0)); + return result; +} + +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length, uint32_t *response) +{ + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t block_size = 64; + sdio_cmd_argument_t arg; + uint32_t cmd; + current_command = SDIO_CMD_53; + current_transfer_direction = direction; + arg.value = argument; + + sdio_enable_bus_irq(); + if (response != NULL) { + *response = 0; + } + +restart: + sdio_transfer_failed = 0; + SDMMC1->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + WPRINT_WHD_ERROR(("Too much attempt\n")); + result = -1; + goto exit; + } + + /* Dodgy STM32 hack to set the CMD53 byte mode size to be the same as the block size */ + if (arg.cmd53.block_mode == 0) { + block_size = find_optimal_block_size(arg.cmd53.count); + if (block_size < SDIO_512B_BLOCK) { + arg.cmd53.count = block_size; + } else { + arg.cmd53.count = 0; + } + argument = arg.value; + } + + SDMMC1->CMD |= SDMMC_CMD_CMDTRANS; + + /* Prepare the SDIO for a data transfer */ + sdio_prepare_data_transfer(direction, block_size, (uint8_t *) data, (uint32_t) length); + + /* Send the command */ + //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); + SDMMC1->ARG = argument; + cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); + SDMMC1->CMD = cmd; + + /* Wait for the whole transfer to complete */ + //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); + result = cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 50, WHD_FALSE); + + if (result != CY_RSLT_SUCCESS) { + WPRINT_WHD_ERROR(("failed getting semaphore\n")); + goto exit; + } + if (sdio_transfer_failed) { + WPRINT_WHD_DEBUG(("try again sdio_transfer_failed %"PRIu32" irq %"PRIu32"\n", sdio_transfer_failed, irqstatus)); + goto restart; + } + /* Check if there were any SDIO errors */ + if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); + goto restart; + } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); + goto restart; + } + + if (direction == CYHAL_READ) { + memcpy(user_data, dma_data_source, (size_t) user_data_size); + } + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 53 argument %lx datasize %d blocknumber 0x%x cmdis %lx %lu dctrl = %x\n", num++, (direction != CYHAL_READ) ? "Write" : "Read", argument, length, arg.cmd53.count, cmd, cmd, dctrl)); + + return result; +} + +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) +{ + return false; +} + +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +{ + whd_handler = (whd_driver_t)handler_arg; + sdio_irq_handler = handler; +} + +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intr_priority, bool enable) +{ + //TODO +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_spi.c new file mode 100644 index 00000000000..162c7a6801f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_spi.c @@ -0,0 +1,29 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides stubs for the WHD driver needed by ARMClang + */ + +#include +#include +#include "cyhal_spi.h" + +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_system.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_system.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_system.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_bd.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_bd.h new file mode 100644 index 00000000000..578b2d9e4eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_bd.h @@ -0,0 +1,49 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" +#include "BlockDevice.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * Mount the physical device + * + * This assumes that the device is ready to read/write immediately. + * + * @param[in] device - physical media to init + * @param[out] fs_handle_out - Receives the filesystem handle. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount(mbed::BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp new file mode 100644 index 00000000000..43f0ff22a5d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -0,0 +1,220 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#include +#include +#include +#include +#include "sockets.h" +#include "resources.h" +#include "wiced_filesystem.h" +#include "wiced_bd.h" +#include "QSPIFBlockDevice.h" +#include "MBRBlockDevice.h" +#include "FATFileSystem.h" + +#define WIFI_DEFAULT_FIRMWARE_PATH "/wlan/4343WA1.BIN" +#define WIFI_DEFAULT_MOUNT_NAME "wlan" +#define WIFI_DEFAULT_PARTITION 1 +#define WIFI_DEFAULT_FS 0 + +BlockDevice *qspi_bd = NULL; +MBRBlockDevice *mbr_bd = NULL; +FATFileSystem *wifi_fs = NULL; + +wiced_filesystem_t resource_fs_handle; + +MBED_WEAK BlockDevice *BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PD_12, PE_2, PD_13, PB_2, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} + +MBED_WEAK void wiced_filesystem_mount_error(void) +{ + WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK void wiced_filesystem_firmware_error(void) +{ + WPRINT_WHD_ERROR(("Please run the \"PortentaWiFiFirmwareUpdater\" sketch once to install the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int mount_err) +{ + DIR *dir; + struct dirent *ent; + std::string dir_name(mounted_name); + if (mount_err) { + wiced_filesystem_mount_error(); + } else { + if ((dir = opendir(mounted_name)) != NULL) { + // print all the files and directories within directory + while ((ent = readdir(dir)) != NULL) { + std::string fullname = "/" + dir_name + "/" + std::string(ent->d_name); + if (fullname == WIFI_DEFAULT_FIRMWARE_PATH) { + closedir(dir); + return WICED_SUCCESS; + } + } + closedir(dir); + } + wiced_filesystem_firmware_error(); + } + return WICED_ERROR; +} + +static wiced_result_t whd_default_firmware_restore(void) +{ +#if MBED_CONF_APP_WIFI_FIRMWARE_RESTORE + size_t ret; + FILE *fp; + + //This should only happen the firs time or if the partition table has been overwritten i.e QSPI tests + WPRINT_WHD_DEBUG(("MBRBlockDevice init failed, repatitioning\n\r")); + if (mbr_bd->partition(qspi_bd, 1, 0x0B, 0, 1024 * 1024) != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice repatitioning OK, reinit\n\r")); + + if (mbr_bd->init() != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice init OK\n\r")); + + wifi_fs = new FATFileSystem(WIFI_DEFAULT_MOUNT_NAME); + + if (wifi_fs->reformat(mbr_bd) != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("FATFileSystem reformat and mount OK\n\r")); + + fp = fopen(WIFI_DEFAULT_FIRMWARE_PATH, "wb"); + if (fp == NULL) { + return WICED_ERROR; + } + ret = fwrite(wifi_firmware_image_data, wifi_firmware_image.size, 1, fp); + if (ret != wifi_firmware_image.size) { + return WICED_ERROR; + } + fclose(fp); + + if (mbr_bd->sync() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Sync BlockDevice OK\n\r")); + + if (wifi_fs->unmount() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Unmount FS\n\r")); + wifi_fs = NULL; +#endif + + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_init(void) +{ + if (mbr_bd == NULL && wifi_fs == NULL) { + WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); + qspi_bd = mbed::BlockDevice::get_default_instance(); + + if (qspi_bd->init() == BD_ERROR_OK) { + mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); + if (mbr_bd->init() == BD_ERROR_OK) { + return WICED_SUCCESS; + } else { + return whd_default_firmware_restore(); + } + } + return WICED_ERROR; + } else { + WPRINT_WHD_DEBUG(("FileSystem initialized with user settings\n\r")); + return WICED_SUCCESS; + } +} + +wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) +{ + wifi_fs = new FATFileSystem(mounted_name); + + int err = wifi_fs->mount(device); + whd_firmware_check_hook(mounted_name, err); + if (!err) { + //fs_handle_out = wifi_fs + return WICED_SUCCESS; + } + return WICED_ERROR; +} + +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) +{ + /* This is called by mbed test system */ + //if (mbr_bd == NULL && wifi_fs == NULL) { + // wiced_filesystem_init(); + //} + //This can be called from user sketch to provide custom block device and mount point before WiFi.beginAP or WiFi.begin + if (wifi_fs == NULL) { + wiced_filesystem_mount(mbr_bd, WIFI_DEFAULT_FS, fs_handle, WIFI_DEFAULT_MOUNT_NAME); + } + + if (wifi_fs == NULL) { + return WICED_ERROR; + } + + *file_handle_out = open(filename, mode); + if (*file_handle_out == -1) { + return WICED_ERROR; + } + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + lseek(*file_handle, offset, whence); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + *returned_bytes_count = read(*file_handle, data, bytes_to_read); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + close(*file_handle); + return WICED_SUCCESS; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h new file mode 100644 index 00000000000..a65aa3c1489 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h @@ -0,0 +1,139 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************** + * Enumerations + ******************************************************/ + +typedef enum { + WICED_FILESYSTEM_OPEN_FOR_READ, /** Specifies read access to the object. Data can be read from the file - equivalent to "r" or "rb" */ + WICED_FILESYSTEM_OPEN_FOR_WRITE, /** Specifies read/write access to the object. Data can be written to the file - equivalent to "r+" or "rb+" or "r+b" */ + WICED_FILESYSTEM_OPEN_WRITE_CREATE, /** Opens for read/write access, creates it if it doesn't exist */ + WICED_FILESYSTEM_OPEN_ZERO_LENGTH, /** Opens for read/write access, Truncates file to zero length if it exists, or creates it if it doesn't - equivalent to "w+", "wb+" or "w+b" */ + WICED_FILESYSTEM_OPEN_APPEND, /** Opens for read/write access, places the current location at the end of the file ready for appending - equivalent to "a", "ab" */ + WICED_FILESYSTEM_OPEN_APPEND_CREATE, /** Opens for read/write access, creates it if it doesn't exist, and places the current location at the end of the file ready for appending - equivalent to "a+", "ab+" or "a+b" */ +} wiced_filesystem_open_mode_t; + +typedef enum { + WICED_FILESYSTEM_SEEK_SET = SEEK_SET, /* Offset from start of file */ + WICED_FILESYSTEM_SEEK_CUR = SEEK_CUR, /* Offset from current position in file */ + WICED_FILESYSTEM_SEEK_END = SEEK_END, /* Offset from end of file */ +} wiced_filesystem_seek_type_t; + +typedef enum { + WICED_SUCCESS = 0, + WICED_ERROR = 1 +} wiced_result_t; + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * File-system Handle Structure + */ +typedef int wiced_filesystem_t; + +/** + * File Handle Structure + * + */ +typedef int wiced_file_t; + +/** + * File-system type Handle Structure + */ +typedef int wiced_filesystem_handle_type_t; + +/** + * Initialise the BlockDevice and filesystem module + * + * Initialises the BlockDevice and filesystem module before mounting a physical device. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_init(void); + +/** + * Open a file for reading or writing + * + * @param[in] fs_handle - The filesystem handle to use - obtained from wiced_filesystem_mount + * @param[out] file_handle_out - a pointer to a wiced_file_t structure which will receive the + * file handle after it is opened + * @param[in] filename - The filename of the file to open + * @param[in] mode - Specifies read or write access + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode); + +/** + * Seek to a location within a file + * + * This is similar to the fseek() in ISO C. + * + * @param[in] file_handle - The file handle on which to perform the seek. + * Must have been previously opened with wiced_filesystem_fopen. + * @param[in] offset - The offset in bytes + * @param[in] whence - WICED_FILESYSTEM_SEEK_SET = Offset from start of file + * WICED_FILESYSTEM_SEEK_CUR = Offset from current position in file + * WICED_FILESYSTEM_SEEK_END = Offset from end of file + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence); + +/** + * Reads data from a file into a memory buffer + * + * @param[in] file_handle - the file handle to read from + * @param[out] data - A pointer to the memory buffer that will + * receive the data that is read + * @param[in] bytes_to_read - the number of bytes to read + * @param[out] returned_item_count - the number of items successfully read. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count); + +/** + * Close a file + * + * This is similar to the fclose() in ISO C. + * + * @param[in] file_handle - the file handle to close + * + * @return WICED_SUCCESS = success + */ +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt new file mode 100644 index 00000000000..cbb51f9c99e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, July 2019 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named �DEPENDENCIES� and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c new file mode 100644 index 00000000000..ddaf0f7188f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c @@ -0,0 +1,25493 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_image_data[421098] = { + 0, 0, 0, 0, 237, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 0, 72, 0, 71, 237, 33, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 68, 66, 80, 80, 128, 109, 4, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 149, 212, 1, 0, 223, 145, 2, 0, 59, 146, 2, 0, 73, 140, + 2, 0, 193, 137, 2, 0, 13, 137, 2, 0, 85, 138, 2, 0, 203, 135, 2, 0, + 167, 136, 2, 0, 181, 146, 2, 0, 189, 146, 2, 0, 141, 135, 2, 0, 167, + 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98, 116, 99, 120, 104, 121, 98, 114, 105, + 100, 104, 119, 45, 110, 111, 99, 108, 109, 105, 110, 99, 45, 99, 108, + 109, 95, 109, 105, 110, 45, 102, 98, 116, 45, 109, 102, 112, 45, 115, + 97, 101, 45, 116, 107, 111, 32, 86, 101, 114, 115, 105, 111, 110, 58, + 32, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, 52, + 51, 48, 51, 32, 67, 89, 41, 32, 67, 82, 67, 58, 32, 101, 54, 98, 55, + 57, 50, 97, 54, 32, 68, 97, 116, 101, 58, 32, 84, 104, 117, 32, 50, + 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, 52, 51, 58, 53, + 51, 32, 80, 83, 84, 32, 85, 99, 111, 100, 101, 32, 86, 101, 114, 58, + 32, 49, 48, 52, 51, 46, 50, 49, 51, 55, 32, 70, 87, 73, 68, 32, 48, + 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, + 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 +}; +resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c new file mode 100644 index 00000000000..616bdedf2e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_clm_blob_image_data[7222] = { + 66, 76, 79, 66, 60, 0, 0, 0, 132, 159, 16, 216, 1, 0, 0, 0, 2, 0, 0, + 0, 0, 0, 0, 0, 60, 0, 0, 0, 246, 27, 0, 0, 183, 10, 32, 40, 0, 0, 0, + 0, 0, 0, 0, 0, 50, 28, 0, 0, 4, 0, 0, 0, 42, 255, 237, 159, 0, 0, 0, + 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, 57, 46, 49, 48, + 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 46, 50, 57, 46, + 52, 0, 0, 0, 0, 0, 0, 0, 0, 184, 10, 0, 0, 67, 108, 109, 73, 109, 112, + 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, 109, 45, 48, 46, 48, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 49, 0, 81, 50, 0, 3, 3, 3, 9, 3, 11, + 4, 4, 4, 7, 4, 8, 4, 10, 4, 11, 5, 7, 8, 8, 9, 9, 9, 11, 11, 11, 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84, 20, 1, 112, 38, 1, 4, 0, 255, 1, 23, 18, 2, 1, 84, 18, 1, 20, 1, + 255, 2, 23, 20, 30, 49, 2, 2, 84, 20, 1, 84, 49, 1, 21, 1, 255, 3, 23, + 20, 30, 37, 30, 46, 2, 2, 84, 21, 1, 84, 46, 1, 26, 1, 255, 3, 23, 20, + 24, 39, 30, 49, 2, 1, 84, 25, 1, 26, 1, 255, 3, 23, 20, 24, 39, 30, + 49, 2, 1, 84, 25, 1, 17, 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 20, 1, + 112, 40, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 30, + 49, 0, 1, 78, 49, 1, 14, 0, 255, 2, 27, 19, 27, 49, 2, 2, 84, 19, 1, + 84, 49, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 20, + 49, 2, 1, 76, 49, 1, 33, 0, 255, 1, 20, 48, 2, 1, 76, 48, 1, 31, 2, + 255, 2, 17, 33, 30, 49, 0, 2, 68, 33, 1, 68, 49, 1, 30, 2, 255, 3, 17, + 33, 24, 38, 30, 49, 0, 3, 56, 33, 1, 68, 38, 1, 68, 49, 1, 28, 2, 255, + 3, 17, 28, 24, 38, 30, 49, 0, 3, 56, 28, 1, 58, 38, 1, 62, 49, 1, 33, + 0, 255, 1, 27, 48, 2, 1, 84, 48, 1, 0, 0, 3, 0, 0, 0, 120, 11, 0, 0, + 16, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1, 18, + 1, 255, 1, 52, 1, 14, 1, 15, 3, 28, 39, 49, 2, 19, 49, 166, 169, 0, + 0 +}; +const resource_hnd_t wifi_firmware_clm_blob = { RESOURCE_IN_MEMORY, 7222, {.mem = { (const char *) wifi_firmware_clm_blob_image_data }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h new file mode 100644 index 00000000000..01bad9226f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Automatically generated file - this comment ensures resources.h file creation */ +/* Auto-generated header file. Do not edit */ +#ifndef INCLUDED_RESOURCES_H_ +#define INCLUDED_RESOURCES_H_ +#include "wiced_resource.h" +#include "wiced_filesystem.h" + +extern wiced_filesystem_t resource_fs_handle; + +extern const resource_hnd_t wifi_firmware_image; +extern const unsigned char wifi_firmware_image_data[421098]; +extern const resource_hnd_t wifi_firmware_clm_blob; +extern const unsigned char wifi_firmware_clm_blob_image_data[7222]; + +#endif /* ifndef INCLUDED_RESOURCES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h new file mode 100644 index 00000000000..3f2279c2be9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * NVRAM file for CY8CKIT-062-WiFi-BT (PSoC6 WiFi-BT Pioneer Kit) using + * Murata's Type 1DX module - Copied from bcm94343wwcd1.txt on 08/04/2019 + * # 2.4 GHz, 20 MHz BW mode; No Antenna Diversity + */ + +#ifndef INCLUDED_NVRAM_IMAGE_H_ +#define INCLUDED_NVRAM_IMAGE_H_ + +#include +#include +#include "generated_mac_address.txt" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Character array of NVRAM image + * + * Generated from cyw94343cy8ckit-062-wifi-bt.txt + */ + +static const char wifi_nvram_image[] = + "manfid=0x2d0" "\x00" + "prodid=0x0726" "\x00" + "vendid=0x14e4" "\x00" + "devid=0x43e2" "\x00" + "boardtype=0x0726" "\x00" + "boardrev=0x1202" "\x00" + "boardnum=22" "\x00" + NVRAM_GENERATED_MAC_ADDRESS "\x00" + "sromrev=11" "\x00" + "boardflags=0x00404201" "\x00" + "boardflags3=0x04000000" "\x00" + "xtalfreq=37400" "\x00" + "nocrc=1" "\x00" + "ag0=0" "\x00" + "aa2g=1" "\x00" + "ccode=ALL" "\x00" + "extpagain2g=0" "\x00" + "pa2ga0=-145,6667,-751" "\x00" + "AvVmid_c0=0x0,0xc8" "\x00" + "cckpwroffset0=2" "\x00" + "maxp2ga0=74" "\x00" + "cckbw202gpo=0" "\x00" + "legofdmbw202gpo=0x88888888" "\x00" + "mcsbw202gpo=0xaaaaaaaa" "\x00" + "propbw202gpo=0xdd" "\x00" + "ofdmdigfilttype=18" "\x00" + "ofdmdigfilttypebe=18" "\x00" + "papdmode=1" "\x00" + "papdvalidtest=1" "\x00" + "pacalidx2g=48" "\x00" + "papdepsoffset=-22" "\x00" + "papdendidx=58" "\x00" + "il0"NVRAM_GENERATED_MAC_ADDRESS "\x00" + "wl0id=0x431b" "\x00" + "muxenab=0x10" "\x00" + "\x00\x00"; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ + +#error Wi-Fi NVRAM image included twice + +#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/whd_config.h new file mode 100644 index 00000000000..23eed23f2c7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/whd_config.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides configuration for WHD driver on Arduino Portenta H7 + */ + +#ifndef __WHD_CONFIG__ +#define __WHD_CONFIG__ + +#include "whd_types.h" +#include "stm32h7xx_hal.h" +#include + +/* disable WPRINT_MACRO */ +#define WHD_PRINT_DISABLE + +/* please define your configuration , either SDIO or SPI */ +#define CY_WHD_CONFIG_USE_SDIO +//#define CY_WHD_CONFIG_USE_SPI + +/* select resource implementation */ +#define USES_RESOURCE_GENERIC_FILESYSTEM + +/* if not defined default value is 2 */ +#define CY_WIFI_OOB_INTR_PRIORITY 0 + +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_FALL +#define CYBSP_WIFI_HOST_WAKE CYBSP_SDIO_OOB_IRQ + +#define BSP_LED1 {GPIOK,{.Pin= GPIO_PIN_5 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED2 {GPIOK,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED3 {GPIOK,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} + +/* power pin */ +#define WIFI_WL_REG_ON {GPIOJ,{.Pin= GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +//#define WIFI_32K_CLK {GPIOA,{.Pin= GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW , .Alternate = GPIO_AF0_MCO}} + +#define WIFI_SDIO_CMD {GPIOD,{.Pin= GPIO_PIN_2 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_CLK {GPIOC,{.Pin= GPIO_PIN_12, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D0 {GPIOC,{.Pin= GPIO_PIN_8 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D1 {GPIOC,{.Pin= GPIO_PIN_9 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D2 {GPIOC,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D3 {GPIOC,{.Pin= GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_OOB_IRQ {GPIOJ,{.Pin= GPIO_PIN_5, .Mode = GPIO_MODE_IT_FALLING , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH}} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PeripheralPins.c new file mode 100644 index 00000000000..3b1cf1075bf --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PeripheralPins.c @@ -0,0 +1,570 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NC, 0} +}; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h new file mode 100644 index 00000000000..93baf9ee198 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h @@ -0,0 +1,450 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +/* MBED TARGET LIST: PORTENTA_H7_M4, PORTENTA_H7_M7 */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0C = PA_0 | DUAL_PAD, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | DUAL_PAD, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + WL_REG_ON = PJ_1, + WL_HOST_WAKE = PJ_5, + WL_SDIO_0 = PC_8, + WL_SDIO_1 = PC_9, + WL_SDIO_2 = PC_10, + WL_SDIO_3 = PC_11, + WL_SDIO_CMD = PD_2, + WL_SDIO_CLK = PC_12, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PG_14, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PG_9, +#endif + + //Led mappings + LED_RED = PH_11, //Red + LED_GREEN = PH_12, //Green + //LED_BLUE = PK_7, //Blue + + LED_SYS_1 = PH_11, + LED_SYS_2 = PH_12, + LED_BLE = PE_5, + + + CYBSP_BT_UART_RX = PH_14, + CYBSP_BT_UART_TX = PB_9, + CYBSP_BT_UART_RTS = PA_15, + CYBSP_BT_UART_CTS = PB_15, + + CYBSP_BT_POWER = PJ_12, + CYBSP_BT_HOST_WAKE = PJ_13, + CYBSP_BT_DEVICE_WAKE = PJ_14, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PD_11, + QSPI_FLASH1_IO1 = PD_12, + QSPI_FLASH1_IO2 = PE_2, + QSPI_FLASH1_IO3 = PD_13, + QSPI_FLASH1_SCK = PB_2, + QSPI_FLASH1_CSN = PG_6, + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_CRS_DV = PA_7, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RX_CLK = PA_1, + ETH_TXD0 = PG_13, + ETH_TXD1 = PG_12, + ETH_TX_EN = PG_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PC_6, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_TRGIO = PC_7, + SYS_WKUP0 = PA_0, + SYS_WKUP1 = PA_2, + SYS_WKUP2 = PC_13, + SYS_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define BUTTON1 PC_13 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.cpp new file mode 100644 index 00000000000..e73e8a0b5bc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.cpp @@ -0,0 +1,53 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +/****************************************************************************** + INCLUDE + ******************************************************************************/ + +#include "mbed.h" +#include "opta_power.h" + +/****************************************************************************** + PUBLIC MEMBER FUNCTIONS + ******************************************************************************/ +void enableEthPowerSupply(void) +{ + /* Ensure ETH power supply */ + /* + mbed::I2C i2c(PB_7, PB_6); + + char data[2]; + + // LDO3 to 1.2V + data[0] = 0x52; + data[1] = 0x9; + i2c.write(8 << 1, data, sizeof(data)); + data[0] = 0x53; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW2 to 3.3V (SW2_VOLT) + data[0] = 0x3B; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW1 to 3.0V (SW1_VOLT) + data[0] = 0x35; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + */ +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.h new file mode 100644 index 00000000000..ea0f5ce2610 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/opta_power.h @@ -0,0 +1,31 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +#ifndef OPTA_POWER +#define OPTA_POWER + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern void enableEthPowerSupply(void); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/system_clock_override.c new file mode 100644 index 00000000000..19923b626d1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/system_clock_override.c @@ -0,0 +1,311 @@ +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2020 Arduino SA. + * All rights reserved.

+ * + * SPDX-License-Identifier: BSD-3-Clause + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 480 + * AHBCLK (MHz) | 240 + * APB1CLK (MHz) | 120 + * APB2CLK (MHz) | 120 + * APB3CLK (MHz) | 120 + * APB4CLK (MHz) | 120 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ + + bool lowspeed = false; +#if defined(LOWSPEED) && (LOWSPEED == 1) + lowspeed = true; +#endif + +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } + + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_LSE, RCC_MCODIV_1); +} + +static const uint32_t _keep; +bool isBootloader() +{ + return ((uint32_t)&_keep < 0x8040000); +} + +bool isBetaBoard() +{ + uint8_t *bootloader_data = (uint8_t *)(0x801F000); + if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { + return true; + } else { + return (bootloader_data[10] == 27); + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) { + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; + } + } + + /* Enable oscillator pin */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + GPIO_InitTypeDef gpio_osc_init_structure; + gpio_osc_init_structure.Pin = GPIO_PIN_1; + gpio_osc_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_osc_init_structure.Pull = GPIO_PULLUP; + gpio_osc_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure); + HAL_Delay(10); + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1); + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO); +#endif + /* Configure the main internal regulator output voltage */ + + if (lowspeed) { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + } else { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + } + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 40; + } else { + RCC_OscInitStruct.PLL.PLLN = 160; + } + +#if HSE_VALUE == 27000000 + RCC_OscInitStruct.PLL.PLLM = 9; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 80; + } else { + RCC_OscInitStruct.PLL.PLLN = 300; + } +#endif + + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (lowspeed) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + return 0; // FAIL + } + } else { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + } + + // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); + +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + __HAL_RCC_CSI_ENABLE() ; + + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO); +#endif + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if defined (CORE_CM4) +void HSEM2_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif + +#if defined (CORE_CM7) +void HSEM1_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif diff --git a/targets/targets.json b/targets/targets.json index a11fc881295..ac53c070b2a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3713,6 +3713,57 @@ "i2c_timing_value_algo": true } }, + "OPTA": { + "inherits": ["MCU_STM32H747xI_CM7"], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "25000000", + "macro_name": "HSE_VALUE" + }, + "lse_bypass": { + "help": "1 to use an oscillator (not a crystal) on 32k LSE", + "value": "1" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_FS" + } + }, + "overrides": { + "system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO", + "clock_source": "USE_PLL_HSE_EXTC", + "lse_available": 1, + "lpticker_delay_ticks": 0, + "network-default-interface-type": "ETHERNET", + "i2c_timing_value_algo": true + }, + "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", + "CM4_BOOT_BY_APPLICATION", + "QSPI_NO_SAMPLE_SHIFT", + "CYW43XXX_UNBUFFERED_UART" + ], + "device_has_add": [ + "USBDEVICE", + "EMAC", + "QSPI" + ], + "extra_labels_add": [ + "CORDIO" + ], + "features": [ + "BLE" + ], + "components_add": [ + "QSPIF", + "WHD", + "4343W_FS", + "CYW43XXX" + ], + "device_name": "STM32H747XIHx" + }, "MCU_STM32H750xB": { "inherits": [ "MCU_STM32H7" From 456854bf42eeed7ed899732853298adbd92a9cb7 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 18 Oct 2021 16:45:48 +0200 Subject: [PATCH 187/227] QSPI: Disable fast mode for vendor ID 0xc22018 --- .../blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 898141f780d..20af57f2574 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -1092,8 +1092,10 @@ int QSPIFBlockDevice::_handle_vendor_quirks() // 2. Require setting a "fast mode" bit in config register 2 to operate at higher clock rates // 3. Should never attempt to enable 4-byte addressing (it causes reads and writes to fail) tr_debug("Applying quirks for macronix"); - _needs_fast_mode = true; - _num_status_registers = 3; + if (vendor_device_ids[1] != 0x20) { + _needs_fast_mode = true; + _num_status_registers = 3; + } _read_status_reg_2_inst = QSPIF_INST_RDCR; _attempt_4_byte_addressing = false; break; From 9c35b625f17ea84d7e65c2287ae554ea68c79229 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Mon, 8 Nov 2021 12:58:01 +0100 Subject: [PATCH 188/227] Opta: enable power save mode on SDIO CLK pin --- .../TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c index 34aa5498e1a..2174d7f58f3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c @@ -92,7 +92,7 @@ static cy_rslt_t sdio_enable_high_speed(void) sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_ENABLE; sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; From 3724f4267a7fbf993aaf4cadb3e0249b210af908 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 29 Mar 2022 16:19:01 +0200 Subject: [PATCH 189/227] QSPI: call is_mem_ready before trying to set write enable bit --- .../blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 20af57f2574..197be5e56b0 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -1186,6 +1186,11 @@ int QSPIFBlockDevice::_set_write_enable() uint8_t status_value = 0; int status = -1; + if (false == _is_mem_ready()) { + tr_error("Device not ready, set_write_enable failed"); + return -1; + } + do { if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_INST_WREN, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) { tr_error("Sending WREN command FAILED"); From 182799684402ec2c783f121e7147843e1056ad99 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Tue, 29 Mar 2022 16:43:31 +0200 Subject: [PATCH 190/227] QSPI: add Adesto quirks and adapt QSPIFBlockDevice functions --- .../include/QSPIF/QSPIFBlockDevice.h | 2 + .../source/QSPIFBlockDevice.cpp | 83 +++++++++++++++---- storage/blockdevice/source/SFDP.cpp | 3 + 3 files changed, 74 insertions(+), 14 deletions(-) diff --git a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h index 695a3961970..191000e274a 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h @@ -380,6 +380,8 @@ class QSPIFBlockDevice : public mbed::BlockDevice { // S25FS512S needs a quirk bool _S25FS512S_quirk; + // AT25SF128A needs a quirk + bool _AT25SF128A_quirk; // Clear block protection qspif_clear_protection_method_t _clear_protection_method; diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 197be5e56b0..05968ba7b1e 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -179,6 +179,8 @@ QSPIFBlockDevice::QSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinNam // Quirk for Cypress S25FS512S _S25FS512S_quirk = false; + // Quirk for AT25SF128A + _AT25SF128A_quirk = false; } int QSPIFBlockDevice::init() @@ -622,14 +624,44 @@ int QSPIFBlockDevice::_sfdp_parse_basic_param_table(Callback> 4; + uint8_t qer_value = 0; + + if (_AT25SF128A_quirk) { + qer_value = 1; + } else { + // QUAD Enable procedure is specified by 3 bits + qer_value = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QER_BYTE] & 0x70) >> 4; + } switch (qer_value) { case 0: @@ -1018,15 +1056,26 @@ int QSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param int status = QSPIF_BD_ERROR_OK; #if RESET_SEQUENCE_FROM_SFDP - uint8_t examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_SOFT_RESET_BYTE]; + uint8_t examined_byte = 0; + if (_AT25SF128A_quirk) { + // Table ptr is at offset 0x30 + // in AT25SF128A SW Reset byte is at address 0x64 + examined_byte = basic_param_table_ptr[0x34]; + } else { + examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_SOFT_RESET_BYTE]; + } // Ignore bit indicating need to exit 0-4-4 mode - should not enter 0-4-4 mode from QSPIFBlockDevice if (examined_byte & SOFT_RESET_RESET_INST_BITMASK) { #endif #if !MBED_CONF_QSPIF_ENABLE_AND_RESET // i.e. direct reset, or determined from SFDP - // Issue instruction 0xF0 to reset the device - qspi_status_t qspi_status = _qspi_send_general_command(0xF0, QSPI_NO_ADDRESS_COMMAND, // Send reset instruction + // Issue instruction to reset the device + uint8_t reset_cmd = 0xF0; + if (_AT25SF128A_quirk) { + reset_cmd = 0x99; + } + qspi_status_t qspi_status = _qspi_send_general_command(reset_cmd, QSPI_NO_ADDRESS_COMMAND, // Send reset instruction NULL, 0, NULL, 0); status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED; #endif @@ -1121,6 +1170,12 @@ int QSPIFBlockDevice::_handle_vendor_quirks() _S25FS512S_quirk = true; } break; + case 0x1f: + // Adesto device + tr_debug("Applying quirks for Adesto AT25SF128A"); + _write_status_reg_2_inst = 0x31; + _AT25SF128A_quirk = true; + break; } return 0; @@ -1595,7 +1650,7 @@ qspi_status_t QSPIFBlockDevice::_qspi_write_status_registers(uint8_t *reg_buffer return QSPI_STATUS_ERROR; } status = _qspi_send_general_command(_write_status_reg_2_inst, QSPI_NO_ADDRESS_COMMAND, - (char *) ®_buffer[0], 1, + (char *) ®_buffer[1], 1, NULL, 0); if (QSPI_STATUS_OK == status) { tr_debug("Writing Status Register 2 Success: value = 0x%x", diff --git a/storage/blockdevice/source/SFDP.cpp b/storage/blockdevice/source/SFDP.cpp index e523c3449c4..9fa6e59acae 100644 --- a/storage/blockdevice/source/SFDP.cpp +++ b/storage/blockdevice/source/SFDP.cpp @@ -145,6 +145,9 @@ int sfdp_parse_single_param_header(sfdp_prm_hdr *phdr_ptr, sfdp_hdr_info &hdr_in case 0x06: tr_info("UNSUPPORTED:Parameter header: eXtended Serial Peripheral Interface (xSPI) Profile 2.0"); break; + case 0x1F: + tr_info("Adesto header"); + break; case 0x87: tr_info("UNSUPPORTED:Parameter header: SCCR Map for SPI Memory Devices"); break; From b2fe6fc558dd16ac5bace654c69e66e9d5d0004d Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 14 Nov 2022 16:27:37 +0100 Subject: [PATCH 191/227] Opta: fix bootloader info --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 2914967e382..fc963145e73 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -46,7 +46,7 @@ MEMORY } -#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) _ConfigStart = 0x0802F000; _IdentificationStart = 0x080002F0; _EncryptKeyStart = 0x08000300; @@ -88,7 +88,7 @@ SECTIONS .text : { KEEP(*(.isr_vector)) -#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) . = ABSOLUTE(0x080002F0); KEEP(*(.bootloader_identification)) KEEP(*(.signing_key)) @@ -113,7 +113,7 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) -#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION)) +#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) *ltrans2*.o(.rodata*) From a97d37232d096b8947b01c1bcec2689da41062ea Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 14 Nov 2022 17:02:33 +0100 Subject: [PATCH 192/227] Opta: WHD: add function to mount wlan firmware fs from WiFi library --- .../TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp | 5 +++++ .../TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp index 43f0ff22a5d..9b7d76409ed 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -170,6 +170,11 @@ wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_hand return WICED_ERROR; } +wiced_result_t wiced_filesystem_mount_default(void) +{ + return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); +} + wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) { /* This is called by mbed test system */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h index a65aa3c1489..77d49d18202 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/wiced_filesystem.h @@ -81,6 +81,15 @@ typedef int wiced_filesystem_handle_type_t; */ wiced_result_t wiced_filesystem_init(void); +/** + * Mount the physical device using default parameters + * + * This assumes that the device is ready to read/write immediately. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount_default(void); + /** * Open a file for reading or writing * From 727e2e12cc425f467c630640e3c1b5a9fc9b1b7f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 15 Nov 2022 10:10:29 +0100 Subject: [PATCH 193/227] stm32h747: linker: set bootloader_version sectionat the end of flash --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index fc963145e73..8db1cd9189b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -113,22 +113,22 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) -#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) + *(.rodata*) + KEEP(*(.eh_frame*)) + *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) *ltrans2*.o(.rodata*) *ltrans3*.o(.rodata*) *ltrans4*.o(.rodata*) + *lib*.o(.rodata*) + +#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) . = ABSOLUTE(0x0801F000); KEEP(*(.bootloader_version)) - - *lib*.o(.rodata*) #endif - *(.rodata*) - - KEEP(*(.eh_frame*)) } > FLASH .ARM.extab : From a38dc2a6d7e84d01e6148b801fe149280a300a23 Mon Sep 17 00:00:00 2001 From: pennam Date: Wed, 23 Nov 2022 09:38:07 +0100 Subject: [PATCH 194/227] MCUboot:PORTENTA_H7:Tune rodata to fit flash --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index 8db1cd9189b..e026a61d4a3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -113,8 +113,10 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) +#if !(defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7)) *(.rodata*) KEEP(*(.eh_frame*)) +#endif *ltrans0*.o(.rodata*) *ltrans1*.o(.rodata*) @@ -122,13 +124,23 @@ SECTIONS *ltrans3*.o(.rodata*) *ltrans4*.o(.rodata*) +#if (defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7)) + . = ABSOLUTE(0x0801F000); + KEEP(*(.bootloader_version)) +#endif + *lib*.o(.rodata*) -#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && (defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) +#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && ( defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) . = ABSOLUTE(0x0801F000); KEEP(*(.bootloader_version)) #endif +#if (defined(MCUBOOT_BOOTLOADER_BUILD) && defined(TARGET_PORTENTA_H7_M7)) + *(.rodata*) + KEEP(*(.eh_frame*)) +#endif + } > FLASH .ARM.extab : From 770813ee6cf6aa812a3f32f9969eee0f0365c562 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 2 Jan 2023 09:40:40 +0100 Subject: [PATCH 195/227] QSPI: apply Adesto quirk only for AT25SF128A Fixes https://github.com/arduino/ArduinoCore-mbed/issues/600 --- .../COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 05968ba7b1e..cd21a7354db 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -1172,9 +1172,11 @@ int QSPIFBlockDevice::_handle_vendor_quirks() break; case 0x1f: // Adesto device - tr_debug("Applying quirks for Adesto AT25SF128A"); - _write_status_reg_2_inst = 0x31; - _AT25SF128A_quirk = true; + if (vendor_device_ids[1] == 0x89) { + tr_debug("Applying quirks for Adesto AT25SF128A"); + _write_status_reg_2_inst = 0x31; + _AT25SF128A_quirk = true; + } break; } From 2ad3e123d01a9af3c5799d8f01b502f4cc110802 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 12 Jan 2023 12:07:59 +0100 Subject: [PATCH 196/227] STM32: USBDevice: fix USB_FS on H7 USB_FS IP, despite the name, shares everything with USBOTG_HS, so the properties (like endpoints number) need to be aligned --- targets/TARGET_STM/USBPhy_STM32.cpp | 30 +++++++++++------------------ 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index 3c86f208832..70be7479da5 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -33,15 +33,19 @@ /* endpoint defines */ +#if defined(TARGET_STM32H7) +#define NUM_ENDPOINTS 6 // should be 8 but this would complicate everything +#else +#define NUM_ENDPOINTS 4 +#endif + #if (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_HS) -#define NUM_ENDPOINTS 6 #define MAX_PACKET_SIZE_NON_ISO 512 #define MAX_PACKET_SIZE_ISO 1023 #else -#define NUM_ENDPOINTS 4 #define MAX_PACKET_SIZE_NON_ISO 64 #define MAX_PACKET_SIZE_ISO (256 + 128) // Spec can go up to 1023, only ram for this though @@ -51,7 +55,7 @@ static const uint32_t tx_ep_sizes[NUM_ENDPOINTS] = { MAX_PACKET_SIZE_NON_ISO, MAX_PACKET_SIZE_NON_ISO, MAX_PACKET_SIZE_NON_ISO, -#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_HS) +#if defined(TARGET_STM32H7) MAX_PACKET_SIZE_NON_ISO, MAX_PACKET_SIZE_NON_ISO, #endif @@ -435,7 +439,7 @@ void USBPhyHw::init(USBPhyEvents *events) total_bytes += fifo_size; } -#if (MBED_CONF_TARGET_USB_SPEED != USE_USB_OTG_HS) +#if !defined(TARGET_STM32H7) /* 1.25 kbytes */ MBED_ASSERT(total_bytes <= 1280); #endif @@ -545,24 +549,12 @@ const usb_ep_table_t *USBPhyHw::endpoint_table() {USB_EP_ATTR_ALLOW_CTRL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, // NON ISO {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, // NON ISO -#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_HS) +#if defined(TARGET_STM32H7) + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, -#endif {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, -#if (MBED_CONF_TARGET_USB_SPEED != USE_USB_OTG_HS) - {0 | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0} #endif + {USB_EP_ATTR_ALLOW_ALL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, } }; return &table; From 817a5dd49cdf7362d177579bf8a3c2c098990a7d Mon Sep 17 00:00:00 2001 From: Alexander Entinger Date: Fri, 10 Feb 2023 09:41:36 +0100 Subject: [PATCH 197/227] Fix PWM initialisation when using both channel A and channel B of a single PWM unit. --- .../pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h | 6 ++++-- targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h index 634375e7644..201be3c7dda 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h @@ -177,6 +177,8 @@ static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { c->top = wrap; } +static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level); + /** \brief Initialise a PWM with settings from a configuration object * \ingroup hardware_pwm * @@ -188,12 +190,12 @@ static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { * \param start If true the PWM will be started running once configured. If false you will need to start * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled() */ -static inline void pwm_init(uint slice_num, pwm_config *c, bool start) { +static inline void pwm_init(uint slice_num, uint chan, pwm_config *c, bool start) { check_slice_num_param(slice_num); pwm_hw->slice[slice_num].csr = 0; pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET; - pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET; + pwm_set_chan_level(slice_num, chan, PWM_CH0_CC_A_RESET); pwm_hw->slice[slice_num].top = c->top; pwm_hw->slice[slice_num].div = c->div; pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB); diff --git a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c index e4bc4daa806..46c5b51df10 100644 --- a/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c +++ b/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pwmout_api.c @@ -66,7 +66,7 @@ void pwmout_init(pwmout_t *obj, PinName pin) obj->cfg = pwm_get_default_config(); pwm_config_set_wrap(&(obj->cfg), count_top); - pwm_init(obj->slice, &(obj->cfg), false); + pwm_init(obj->slice, obj->channel, &(obj->cfg), false); gpio_set_function(pin, GPIO_FUNC_PWM); } @@ -142,7 +142,7 @@ void pwmout_period_us(pwmout_t *obj, int period) uint32_t min_period = 1000000 * count_top / clock_get_hz(clk_sys); pwm_config_set_clkdiv(&(obj->cfg), (float)period / (float)min_period); - pwm_init(obj->slice, &(obj->cfg), false); + pwm_init(obj->slice, obj->channel, &(obj->cfg), false); } int pwmout_read_period_us(pwmout_t *obj) From 6ab64508cd416b99dfbc05783036c4e03c6eb864 Mon Sep 17 00:00:00 2001 From: giulcioffi Date: Wed, 16 Mar 2022 14:57:17 +0100 Subject: [PATCH 198/227] Giga: Initial: Add target --- connectivity/lwipstack/mbed_lib.json | 3 + .../STM32Cube_FW/stm32h7xx_hal_conf.h | 2 +- .../TARGET_GIGA/CMakeLists.txt | 37 + .../COMPONENT_CYW43XXX/CMakeLists.txt | 4 + .../firmware/CMakeLists.txt | 6 + .../COMPONENT_4343W_FS/CMakeLists.txt | 7 + .../w_bt_firmware_controller.c | 2101 ++ .../TARGET_GIGA/COMPONENT_WHD/CMakeLists.txt | 34 + .../COMPONENT_WHD/generated_mac_address.txt | 9 + .../COMPONENT_WHD/interface/cy_result.h | 228 + .../COMPONENT_WHD/interface/cyabs_rtos.h | 711 + .../COMPONENT_WHD/interface/cyabs_rtos_impl.h | 77 + .../interface/cyabs_rtos_rtxv5.c | 863 + .../COMPONENT_WHD/interface/cyhal_gpio.h | 247 + .../COMPONENT_WHD/interface/cyhal_sdio.h | 366 + .../COMPONENT_WHD/interface/cyhal_spi.h | 383 + .../TARGET_GIGA/COMPONENT_WHD/port/cy_hal.c | 63 + .../COMPONENT_WHD/port/cy_syslib.h | 592 + .../TARGET_GIGA/COMPONENT_WHD/port/cy_utils.h | 81 + .../TARGET_GIGA/COMPONENT_WHD/port/cybsp.h | 50 + .../TARGET_GIGA/COMPONENT_WHD/port/cycfg.h | 20 + .../TARGET_GIGA/COMPONENT_WHD/port/cyhal.h | 52 + .../COMPONENT_WHD/port/cyhal_gpio.cpp | 104 + .../COMPONENT_WHD/port/cyhal_hw_types.h | 112 + .../COMPONENT_WHD/port/cyhal_sdio.c | 483 + .../COMPONENT_WHD/port/cyhal_spi.c | 29 + .../COMPONENT_WHD/port/cyhal_system.h | 20 + .../TARGET_GIGA/COMPONENT_WHD/port/wiced_bd.h | 49 + .../COMPONENT_WHD/port/wiced_filesystem.cpp | 220 + .../COMPONENT_WHD/port/wiced_filesystem.h | 139 + .../LICENSE-permissive-binary-license-1.0.txt | 49 + .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 25493 ++++++++++++++++ .../COMPONENT_4343W_FS/4343WA1_clm_blob.c | 400 + .../firmware/COMPONENT_4343W_FS/resources.h | 30 + .../resources/nvram/wifi_nvram_image.h | 87 + .../TARGET_GIGA/COMPONENT_WHD/whd_config.h | 61 + .../TARGET_GIGA/PeripheralPins.c | 570 + .../TARGET_STM32H747xI/TARGET_GIGA/PinNames.h | 445 + .../TARGET_GIGA/giga_power.cpp | 52 + .../TARGET_GIGA/giga_power.h | 31 + .../TARGET_GIGA/system_clock_override.c | 237 + .../TARGET_STM32H747xI/system_clock.c | 3 + targets/targets.json | 52 + 43 files changed, 34601 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/generated_mac_address.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cy_result.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_impl.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_gpio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_sdio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_spi.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_hal.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_syslib.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_utils.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cybsp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cycfg.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_gpio.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_hw_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_spi.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_system.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_bd.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/whd_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index d4488ba8015..f6607b6ffc9 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -231,6 +231,9 @@ "OPTA": { "mem-size": 16000 }, + "GIGA": { + "mem-size": 16000 + }, "FVP_MPS2_M3": { "mem-size": 36560 }, diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h index 524bb2dd528..a5f5d900f5e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h @@ -50,7 +50,7 @@ #define HAL_SD_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED -#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) +#if (!defined(TARGET_PORTENTA_H7_M7) && !defined(TARGET_GIGA)) || !defined(MCUBOOT_BOOTLOADER_BUILD) #define HAL_ADC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/CMakeLists.txt new file mode 100644 index 00000000000..e2f5e770381 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) + +add_library(mbed-portenta-h7-m4 INTERFACE) + +target_sources(mbed-portenta-h7-m4 + INTERFACE + PeripheralPins.c + system_clock_override.c + portenta_power.cpp +) + +target_include_directories(mbed-portenta-h7-m4 + INTERFACE + . +) + +target_link_libraries(mbed-portenta-h7-m4 INTERFACE mbed-stm32h747xi-cm4) + + +add_library(mbed-portenta-h7-m7 INTERFACE) + +target_sources(mbed-portenta-h7-m7 + INTERFACE + PeripheralPins.c + system_clock_override.c + portenta_power.cpp +) + +target_include_directories(mbed-portenta-h7-m7 + INTERFACE + . +) + +target_link_libraries(mbed-portenta-h7-m7 INTERFACE mbed-stm32h747xi-cm7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/CMakeLists.txt new file mode 100644 index 00000000000..82be36e1f09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(firmware) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt new file mode 100644 index 00000000000..fbbc3b979de --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("4343W_FS" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_4343W) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt new file mode 100644 index 00000000000..31fecb8fe09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-ble + INTERFACE + w_bt_firmware_controller.c +) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c new file mode 100644 index 00000000000..ac2bc973e1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c @@ -0,0 +1,2101 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = "BCM4343A1_001.002.009.0083.0000_Generic_UART_37_4MHz_wlbga_wiced"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[] = { + 76, 252, 70, 16, 24, 33, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, + 0, 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 18, 161, + 67, 67, 0, 1, 28, 82, 24, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 255, 82, 24, + 33, 0, 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 79, 133, 0, 0, + 3, 3, 40, 66, 67, 77, 52, 51, 52, 51, 65, 49, 32, 85, 65, 82, 84, 32, + 51, 55, 46, 52, 32, 77, 72, 122, 32, 119, 108, 98, 103, 97, 95, 114, + 101, 102, 32, 119, 105, 99, 101, 100, 0, 22, 3, 2, 83, 0, 2, 1, 248, + 3, 8, 1, 50, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 50, 0, 255, 15, 0, 0, + 98, 8, 0, 0, 112, 0, 100, 0, 128, 0, 0, 0, 128, 0, 0, 0, 172, 0, 50, + 0, 255, 255, 255, 1, 0, 0, 47, 0, 140, 0, 50, 0, 0, 240, 255, 15, 0, + 16, 17, 1, 120, 0, 50, 0, 255, 255, 255, 255, 185, 184, 184, 184, 96, + 44, 32, 0, 255, 0, 0, 0, 0, 0, 0, 0, 16, 1, 50, 0, 0, 0, 255, 255, 0, + 0, 24, 24, 108, 1, 96, 0, 255, 255, 255, 255, 11, 0, 0, 0, 112, 1, 96, + 0, 255, 255, 255, 255, 16, 0, 0, 0, 116, 1, 96, 0, 255, 255, 255, 255, + 21, 0, 0, 0, 120, 1, 96, 0, 255, 255, 255, 255, 25, 0, 0, 0, 124, 1, + 96, 0, 255, 255, 0, 0, 29, 0, 0, 0, 132, 1, 96, 0, 255, 255, 255, 255, + 33, 0, 0, 0, 96, 6, 65, 0, 255, 255, 0, 0, 51, 3, 0, 0, 100, 6, 65, + 76, 252, 255, 77, 25, 33, 0, 0, 255, 255, 0, 0, 41, 58, 0, 0, 100, 6, + 65, 0, 255, 255, 0, 0, 41, 58, 0, 0, 104, 6, 65, 0, 255, 255, 0, 0, + 104, 5, 0, 0, 108, 6, 65, 0, 255, 255, 0, 0, 168, 48, 0, 0, 112, 6, + 65, 0, 255, 255, 0, 0, 232, 62, 0, 0, 116, 6, 65, 0, 255, 255, 0, 0, + 28, 50, 0, 0, 120, 6, 65, 0, 255, 255, 0, 0, 187, 51, 0, 0, 124, 6, + 65, 0, 255, 255, 0, 0, 48, 9, 0, 0, 80, 3, 65, 0, 255, 255, 0, 0, 16, + 5, 0, 0, 84, 3, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 92, 3, 65, 0, 255, + 255, 0, 0, 9, 8, 0, 0, 96, 3, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 100, + 3, 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 108, 3, 65, 0, 255, 255, 0, 0, + 14, 9, 0, 0, 116, 3, 65, 0, 255, 255, 0, 0, 5, 9, 0, 0, 120, 3, 65, + 0, 255, 255, 0, 0, 16, 10, 0, 0, 64, 1, 65, 0, 255, 255, 0, 0, 16, 5, + 0, 0, 68, 1, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 76, 1, 65, 0, 255, 255, + 0, 0, 9, 8, 0, 0, 80, 1, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 84, 1, + 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 92, 1, 76, 252, 255, 72, 26, 33, + 0, 65, 0, 255, 255, 0, 0, 14, 9, 0, 0, 96, 1, 65, 0, 255, 255, 0, 0, + 5, 9, 0, 0, 100, 1, 65, 0, 255, 255, 0, 0, 16, 10, 0, 0, 224, 6, 65, + 0, 255, 255, 0, 0, 113, 32, 0, 0, 156, 1, 96, 0, 255, 0, 0, 0, 3, 0, + 0, 0, 100, 1, 96, 0, 255, 255, 255, 255, 0, 0, 0, 0, 9, 1, 4, 2, 1, + 0, 0, 34, 3, 2, 1, 0, 240, 1, 40, 4, 0, 0, 0, 32, 21, 50, 0, 255, 255, + 250, 255, 217, 3, 62, 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, + 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, 240, 1, 40, 1, 0, 0, 0, + 32, 21, 50, 0, 255, 255, 250, 255, 221, 3, 62, 254, 40, 21, 50, 0, 0, + 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, + 240, 1, 40, 2, 0, 0, 0, 32, 21, 50, 0, 255, 255, 250, 255, 217, 3, 62, + 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, + 0, 0, 0, 12, 0, 0, 0, 240, 1, 160, 1, 3, 0, 0, 0, 16, 21, 50, 0, 0, + 0, 0, 0, 240, 240, 240, 0, 20, 21, 50, 0, 0, 0, 0, 0, 240, 240, 240, + 0, 24, 21, 50, 0, 0, 0, 0, 0, 76, 252, 255, 67, 27, 33, 0, 240, 240, + 240, 0, 28, 21, 50, 0, 0, 0, 0, 0, 76, 76, 0, 0, 32, 21, 50, 0, 255, + 255, 250, 255, 221, 3, 62, 254, 36, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 52, 21, 50, 0, 0, 0, + 0, 0, 240, 0, 0, 0, 56, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 21, 50, + 0, 0, 0, 0, 0, 202, 6, 0, 0, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, + 248, 0, 100, 0, 81, 0, 0, 0, 16, 0, 0, 0, 120, 8, 100, 0, 2, 0, 0, 0, + 0, 0, 0, 0, 1, 7, 181, 3, 4, 6, 10, 35, 60, 90, 110, 125, 5, 56, 4, + 136, 4, 156, 4, 136, 4, 216, 4, 116, 4, 196, 4, 216, 4, 196, 4, 20, + 5, 176, 4, 0, 5, 20, 5, 0, 5, 80, 5, 246, 4, 70, 5, 90, 5, 70, 5, 150, + 5, 60, 5, 140, 5, 160, 5, 140, 5, 220, 5, 130, 5, 210, 5, 230, 5, 210, + 5, 34, 6, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 168, + 2, 168, 2, 168, 2, 168, 2, 168, 2, 228, 2, 228, 2, 228, 2, 228, 2, 228, + 2, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 102, 3, 102, 3, 102, 3, 102, 3, + 102, 3, 172, 3, 76, 252, 255, 62, 28, 33, 0, 172, 3, 172, 3, 172, 3, + 172, 3, 242, 3, 242, 3, 242, 3, 242, 3, 242, 3, 20, 255, 20, 255, 20, + 255, 20, 255, 20, 255, 20, 255, 6, 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0, 244, 31, 3, 250, 102, 3, 204, 153, + 153, 153, 153, 153, 116, 116, 116, 116, 116, 132, 132, 132, 132, 131, + 165, 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 3, 204, 179, 179, + 179, 179, 179, 130, 130, 130, 130, 130, 132, 132, 132, 132, 131, 165, + 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 35, 255, 1, 7, 181, 3, + 0, 6, 10, 35, 60, 90, 110, 125, 5, 92, 3, 62, 3, 72, 3, 92, 3, 72, 3, + 152, 3, 122, 3, 132, 3, 152, 3, 132, 3, 212, 3, 182, 3, 192, 3, 212, + 3, 192, 3, 26, 4, 252, 3, 6, 4, 26, 4, 6, 4, 96, 4, 66, 4, 76, 4, 96, + 4, 76, 4, 166, 4, 136, 4, 146, 4, 166, 4, 146, 4, 20, 255, 20, 255, + 20, 255, 20, 255, 20, 255, 20, 255, 68, 2, 48, 2, 38, 2, 18, 2, 28, + 2, 128, 2, 108, 2, 98, 2, 78, 2, 88, 2, 188, 2, 168, 2, 158, 2, 138, + 2, 148, 2, 2, 3, 238, 2, 228, 2, 208, 2, 218, 2, 72, 3, 52, 3, 42, 3, + 22, 3, 32, 3, 142, 3, 122, 3, 112, 3, 92, 3, 102, 3, 20, 255, 20, 255, + 20, 255, 20, 255, 20, 255, 20, 255, 6, 0, 0, 0, 96, 0, 5, 156, 2, 255, + 160, 2, 255, 164, 2, 255, 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152, + 33, 0, 16, 1, 15, 58, 12, 197, 5, 0, 115, 240, 220, 191, 0, 0, 200, + 4, 13, 0, 16, 1, 15, 59, 112, 198, 5, 0, 115, 240, 66, 191, 0, 0, 248, + 4, 13, 0, 16, 1, 15, 60, 32, 108, 5, 0, 121, 240, 110, 188, 0, 0, 0, + 5, 13, 0, 16, 1, 15, 61, 16, 190, 4, 0, 152, 70, 11, 48, 0, 0, 0, 0, + 0, 0, 16, 1, 15, 62, 176, 100, 6, 0, 108, 240, 199, 191, 0, 0, 66, 52, + 13, 0, 16, 1, 15, 63, 248, 103, 6, 0, 105, 240, 138, 190, 0, 0, 16, + 5, 13, 0, 16, 1, 15, 64, 252, 97, 6, 0, 109, 240, 112, 185, 0, 0, 224, + 52, 13, 0, 16, 1, 15, 65, 20, 172, 3, 0, 149, 240, 132, 188, 0, 0, 32, + 5, 13, 0, 16, 1, 15, 66, 224, 155, 6, 0, 105, 240, 202, 188, 0, 0, 120, + 53, 13, 0, 16, 1, 15, 67, 28, 161, 6, 0, 102, 240, 6, 186, 0, 0, 44, + 5, 13, 0, 16, 1, 15, 68, 144, 51, 4, 0, 141, 240, 212, 184, 0, 0, 60, + 5, 13, 0, 16, 1, 15, 69, 4, 62, 4, 0, 140, 240, 160, 187, 0, 0, 72, + 5, 13, 0, 16, 1, 15, 70, 144, 56, 4, 0, 140, 240, 126, 190, 0, 0, 144, + 5, 13, 0, 16, 1, 15, 71, 196, 101, 2, 0, 169, 240, 238, 191, 0, 0, 164, + 5, 13, 76, 252, 255, 190, 153, 33, 0, 0, 16, 1, 15, 72, 32, 76, 7, 0, + 91, 240, 204, 188, 0, 0, 188, 5, 13, 0, 16, 1, 15, 73, 204, 239, 3, + 0, 148, 240, 98, 187, 0, 0, 148, 54, 13, 0, 16, 1, 15, 74, 140, 248, + 3, 0, 144, 240, 164, 190, 0, 0, 216, 5, 13, 0, 16, 1, 15, 75, 12, 249, + 3, 0, 144, 240, 112, 190, 0, 0, 240, 5, 13, 0, 16, 1, 15, 76, 12, 242, + 3, 0, 145, 240, 0, 186, 0, 0, 16, 6, 13, 0, 16, 1, 15, 77, 32, 245, + 6, 0, 97, 240, 138, 184, 0, 0, 56, 6, 13, 0, 16, 1, 15, 78, 200, 242, + 6, 0, 97, 240, 191, 185, 0, 0, 74, 6, 13, 0, 16, 1, 15, 79, 164, 222, + 4, 0, 130, 240, 218, 187, 0, 0, 92, 6, 13, 0, 16, 1, 15, 80, 44, 66, + 5, 0, 124, 240, 30, 186, 0, 0, 108, 6, 13, 0, 16, 1, 15, 81, 252, 71, + 5, 0, 123, 240, 62, 191, 0, 0, 124, 6, 13, 0, 16, 1, 15, 82, 36, 32, + 3, 0, 161, 240, 216, 187, 0, 0, 216, 55, 13, 0, 16, 1, 15, 83, 108, + 32, 3, 0, 161, 240, 219, 187, 0, 0, 38, 56, 13, 0, 6, 1, 4, 136, 57, + 13, 0, 16, 1, 15, 84, 144, 200, 7, 0, 64, 26, 128, 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3, 0, 155, 240, 130, + 189, 0, 0, 216, 6, 13, 0, 16, 1, 15, 98, 116, 77, 3, 0, 155, 240, 180, + 188, 76, 252, 255, 180, 155, 33, 0, 0, 0, 224, 6, 13, 0, 16, 1, 15, + 99, 28, 71, 3, 0, 155, 240, 230, 191, 0, 0, 236, 6, 13, 0, 16, 1, 15, + 100, 52, 53, 3, 0, 157, 240, 222, 184, 0, 0, 244, 6, 13, 0, 16, 1, 15, + 101, 156, 55, 3, 0, 156, 240, 184, 191, 0, 0, 16, 7, 13, 0, 16, 1, 15, + 102, 236, 23, 2, 0, 179, 240, 230, 185, 0, 0, 188, 75, 13, 0, 16, 1, + 15, 103, 56, 199, 1, 0, 179, 240, 242, 191, 0, 0, 32, 7, 13, 0, 16, + 1, 15, 104, 16, 68, 0, 0, 208, 240, 242, 188, 0, 0, 248, 77, 13, 0, + 16, 1, 15, 105, 4, 199, 1, 0, 180, 240, 15, 184, 0, 0, 38, 7, 13, 0, + 16, 1, 15, 106, 132, 211, 2, 0, 167, 240, 32, 191, 0, 0, 200, 81, 13, + 0, 16, 1, 15, 107, 240, 210, 2, 0, 163, 240, 32, 186, 0, 0, 52, 7, 13, + 0, 6, 1, 4, 124, 85, 13, 0, 6, 1, 4, 104, 88, 13, 0, 16, 1, 15, 108, + 240, 175, 1, 0, 186, 240, 96, 188, 0, 0, 180, 88, 13, 0, 16, 1, 15, + 109, 12, 7, 2, 0, 176, 240, 32, 184, 0, 0, 80, 7, 13, 0, 16, 1, 15, + 110, 100, 57, 8, 0, 81, 240, 228, 191, 0, 0, 48, 89, 13, 0, 16, 1, 15, + 111, 100, 86, 4, 0, 139, 240, 124, 184, 0, 0, 96, 76, 252, 255, 175, + 156, 33, 0, 7, 13, 0, 16, 1, 15, 112, 60, 86, 4, 0, 144, 240, 209, 185, + 0, 0, 226, 89, 13, 0, 16, 1, 15, 113, 176, 87, 4, 0, 138, 240, 217, + 191, 0, 0, 102, 7, 13, 0, 16, 1, 15, 114, 204, 45, 5, 0, 125, 240, 206, + 188, 0, 0, 108, 7, 13, 0, 16, 1, 15, 115, 128, 42, 3, 0, 157, 240, 122, + 190, 0, 0, 120, 7, 13, 0, 16, 1, 15, 116, 84, 164, 6, 0, 102, 240, 164, + 185, 0, 0, 160, 7, 13, 0, 16, 1, 15, 117, 20, 105, 5, 0, 121, 240, 72, + 191, 0, 0, 168, 7, 13, 0, 16, 1, 15, 118, 232, 112, 7, 0, 89, 240, 98, + 187, 0, 0, 176, 7, 13, 0, 16, 1, 15, 119, 132, 103, 7, 0, 90, 240, 28, + 184, 0, 0, 192, 7, 13, 0, 16, 1, 15, 120, 84, 47, 0, 0, 205, 240, 60, + 188, 0, 0, 208, 7, 13, 0, 16, 1, 15, 121, 224, 49, 0, 0, 205, 240, 250, + 186, 0, 0, 216, 7, 13, 0, 16, 1, 15, 122, 252, 181, 1, 0, 181, 240, + 248, 184, 0, 0, 240, 7, 13, 0, 16, 1, 15, 123, 252, 199, 1, 0, 179, + 240, 254, 191, 0, 0, 252, 7, 13, 0, 16, 1, 15, 124, 100, 200, 1, 0, + 179, 240, 207, 191, 0, 0, 6, 8, 13, 0, 16, 1, 15, 125, 80, 180, 1, 0, + 181, 240, 224, 185, 0, 0, 76, 252, 11, 170, 157, 33, 0, 20, 8, 13, 0, + 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 +}; + +const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/CMakeLists.txt new file mode 100644 index 00000000000..55b7e63ecf3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-portenta-whd-4343w-fw INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS +) +target_sources(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c + resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +) + +add_library(mbed-portenta-whd-4343w-nvram INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-nvram INTERFACE resources/nvram) + +add_library(mbed-portenta-whd INTERFACE) +target_include_directories(mbed-portenta-whd + INTERFACE + . + port + interface +) + +target_sources(mbed-portenta-whd + INTERFACE + port/cyhal.c + port/cyhalgpio.cpp + port/cyhalsdio.c + port/wiced_filesystem.cpp + interface/cyabs_rtos_rtxv5.c +) + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/generated_mac_address.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/generated_mac_address.txt new file mode 100644 index 00000000000..eb735ba173d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during WHD power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:6f:b2:ea" diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cy_result.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cy_result.h new file mode 100644 index 00000000000..8277169ab99 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cy_result.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cy_result.h +* +* \brief +* Basic function result handling. Defines a simple type for conveying +* information about whether something succeeded or details about any issues +* that were detected. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_result Result Type +* \ingroup group_abstraction +* \{ +* \anchor anchor_general_description +* \brief Defines a type and related utilities for function result handling. +* +* The @ref cy_rslt_t type is a structured bitfield which encodes information +* about result type, the originating module, and a code for the specific +* error (or warning etc). In order to extract these individual fields from +* a @ref cy_rslt_t value, the utility macros @ref CY_RSLT_GET_TYPE, @ref CY_RSLT_GET_MODULE, +* and @ref CY_RSLT_GET_CODE are provided. For example: +* \code +* cy_rslt_t result = cy_hal_do_operation(arg); +* // Will be CY_RSLT_TYPE_INFO, CY_RSLT_TYPE_WARNING, CY_RSLT_TYPE_ERROR, or CY_RSLT_TYPE_FATAL +* uint8_t type = CY_RSLT_GET_TYPE(result) +* // See the "Modules" section for possible values +* uint16_t module_id = CY_RSLT_GET_MODULE(result); +* // Specific error codes are defined by each module +* uint16_t error_code = CY_RSLT_GET_CODE(result); +* \endcode +*/ + +#if !defined(CY_RESULT_H) +#define CY_RESULT_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief Provides the result of an operation as a structured bitfield. + * + * See the \ref anchor_general_description "General Description" + * for more details on structure and usage. + */ +typedef uint32_t cy_rslt_t; + +/** @ref cy_rslt_t return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) + +/** \cond INTERNAL */ +/** Mask for the bit at position "x" */ +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) + +/** Bit position of the result type */ +#define CY_RSLT_TYPE_POSITION (16U) +/** Bit width of the result type */ +#define CY_RSLT_TYPE_WIDTH (2U) +/** Bit position of the module identifier */ +#define CY_RSLT_MODULE_POSITION (18U) +/** Bit width of the module identifier */ +#define CY_RSLT_MODULE_WIDTH (14U) +/** Bit position of the result code */ +#define CY_RSLT_CODE_POSITION (0U) +/** Bit width of the result code */ +#define CY_RSLT_CODE_WIDTH (16U) + +/** Mask for the result type */ +#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) +/** Mask for the module identifier */ +#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH) +/** Mask for the result code */ +#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH) + +/** \endcond */ + +/** +* \{ +* @name Fields +* Utility macros for constructing result values and extracting individual fields from existing results. +*/ + +/** + * @brief Get the value of the result type field + * @param x the @ref cy_rslt_t value from which to extract the result type + */ +#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK) +/** + * @brief Get the value of the module identifier field + * @param x the @ref cy_rslt_t value from which to extract the module id + */ +#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) +/** + * @brief Get the value of the result code field + * @param x the @ref cy_rslt_t value from which to extract the result code + */ +#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) + +/** + * @brief Create a new @ref cy_rslt_t value that encodes the specified type, module, and result code. + * @param type one of @ref CY_RSLT_TYPE_INFO, @ref CY_RSLT_TYPE_WARNING, + * @ref CY_RSLT_TYPE_ERROR, @ref CY_RSLT_TYPE_FATAL + * @param module Identifies the module where this result originated; see @ref anchor_modules "Modules". + * @param code a module-defined identifier to identify the specific situation that + * this result describes. + */ +#define CY_RSLT_CREATE(type, module, code) \ + ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ + (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ + (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) + +/** \} fields */ + +/** +* \{ +* @name Result Types +* Defines codes to identify the type of result. +*/ + +/** @brief The result code is informational-only */ +#define CY_RSLT_TYPE_INFO (0U) +/** @brief The result code is warning of a problem but will proceed */ +#define CY_RSLT_TYPE_WARNING (1U) +/** @brief The result code is an error */ +#define CY_RSLT_TYPE_ERROR (2U) +/** @brief The result code is a fatal error */ +#define CY_RSLT_TYPE_FATAL (3U) + +/** \} severity */ + +/** +* \{ +* @name Modules +* @anchor anchor_modules +* Defines codes to identify the module from which an error originated. +* For some large libraries, a range of module codes is defined here; +* see the library documentation for values corresponding to individual modules. +* Valid range is 0x0000-0x4000. +*/ +/**** DRIVER Module codes: 0x0000 - 0x00FF ****/ +/** Base module identifier for peripheral driver library drivers (0x0000 - 0x007F) */ +#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) +/** Base module identifier for wireless host driver library modules (0x0080 - 0x00FF) */ +#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) + +/** Deprecated. Use \ref CY_RSLT_MODULE_ABSTRACTION_HAL */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) +/** Module identifier for the Hardware Abstraction Layer */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL (0x0100U) +/** Module identifier for board support package */ +#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) +/** Module identifier for file system abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) +/** Module identifier for resource abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) +/** Module identifier for rtos abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) +/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ +#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) + +/** Base module identifier for Board Libraries (0x01A0 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_LIB_BASE (0x01A0U) +/** Module identifier for the Retarget IO Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RETARGET_IO (0x1A0U) +/** Module identifier for the RGB LED Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RGB_LED (0x01A1U) +/** Module identifier for the Serial Flash Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH (0x01A2U) +/** Module identifier for the WiFi Host Driver + Board Support Integration Library */ +#define CY_RSLT_MODULE_BOARD_LIB_WHD_INTEGRATION (0x01A3U) + +/** Base module identifier for Shield Board Libraries (0x01B8 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_SHIELD_BASE (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-EPD */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_EPD (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-TFT */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_TFT (0x01B9U) +/** Module identifier for Shield Board CY8CKIT-032 */ +#define CY_RSLT_MODULE_BOARD_SHIELD_032 (0x01BAU) + +/** Base module identifier for Board Hardware Libraries (0x01C0 - 0x01FF) */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BASE (0x01C0U) +/** Module identifier for the BMI160 Motion Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BMI160 (0x01C0U) +/** Module identifier for the E2271CS021 E-Ink Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_E2271CS021 (0x01C1U) +/** Module identifier for the NTC GPIO Thermistor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_THERMISTOR (0x01C2U) +/** Module identifier for the SSD1306 OLED Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_SSD1306 (0x01C3U) +/** Module identifier for the ST7789V TFT Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_ST7789V (0x01C4U) +/** Module identifier for the Light Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_LIGHT_SENSOR (0x01C5U) +/** Module identifier for the AK4954A Audio Codec Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_AK4954A (0x01C6U) + +/** Base module identifier for Middleware Libraries (0x0200 - 0x02FF) */ +#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) + +/** \} modules */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_RESULT_H */ + +/** \} group_result */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos.h new file mode 100644 index 00000000000..e19ffc49f79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos.h @@ -0,0 +1,711 @@ +/***************************************************************************//** +* \file cyabs_rtos.h +* +* \brief +* Defines the Cypress RTOS Interface. Provides prototypes for functions that +* allow Cypress libraries to use RTOS resources such as threads, mutexes & +* timing functions in an abstract way. The APIs are implemented in the Port +* Layer RTOS interface which is specific to the RTOS in use. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef INCLUDED_CY_RTOS_INTERFACE_H_ +#define INCLUDED_CY_RTOS_INTERFACE_H_ + +#include "cyabs_rtos_impl.h" +#include "cy_result.h" +#include +#include +#include + +/** +* \defgroup group_abstraction_rtos_common Common + * General types and defines for working with the RTOS abstraction layer. +* \defgroup group_abstraction_rtos_mutex Mutex + * APIs for acquiring and working with Mutexes. +* \defgroup group_abstraction_rtos_queue Queue + * APIs for creating and working with Queues. +* \defgroup group_abstraction_rtos_semaphore Semaphore + * APIs for acquiring and working with Semaphores. +* \defgroup group_abstraction_rtos_threads Threads + * APIs for creating and working with Threads. +* \defgroup group_abstraction_rtos_time Time + * APIs for getting the current time and waiting. +* \defgroup group_abstraction_rtos_timer Timer + * APIs for creating and working with Timers. +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*********************************************** CONSTANTS **********************************************/ + +/** + * \ingroup group_abstraction_rtos_common + * \{ + */ + +#if defined(DOXYGEN) +//#include "Template/cyabs_rtos_impl.h" + +/** Return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) +#endif + +/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ +#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) + +// +// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty +// queues), the these errors are listed here and the abstraction layer implementation must map from the +// underlying errors to these. If the errors are special cases, the the error \ref CY_RTOS_GENERAL_ERROR +// will be returned and \ref cy_rtos_last_error() can be used to retrieve the RTOS specific error message. +// +/** Requested operation did not complete in the specified time */ +#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) +/** The RTOS could not allocate memory for the specified operation */ +#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) +/** An error occured in the RTOS */ +#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) +/** A bad argument was passed into the APIs */ +#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) +/** A memory alignment issue was detected. Ensure memory provided is aligned per \ref CY_RTOS_ALIGNMENT_MASK */ +#define CY_RTOS_ALIGNMENT_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 6) + +/** \} group_abstraction_rtos_common */ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** The Queue is already full and can't accept any more items at this time */ +#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) +/** The Queue is empty and has nothing to remove */ +#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** TYPES **********************************************/ + +/** + * The state a thread can be in + * + * \ingroup group_abstraction_rtos_threads + */ +typedef enum cy_thread_state +{ + CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ + CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ + CY_THREAD_STATE_RUNNING, /**< thread is currently running */ + CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ + CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ + CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ +} cy_thread_state_t; + +/** + * The type of timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef enum cy_timer_trigger_type +{ + CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ + CY_TIMER_TYPE_ONCE, /**< called once only */ + cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by \ref CY_TIMER_TYPE_PERIODIC */ + cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by \ref CY_TIMER_TYPE_ONCE */ +} cy_timer_trigger_type_t; + +/** + * The type of a function that is the entry point for a thread + * + * @param[in] arg the argument passed from the thread create call to the entry function + * + * \ingroup group_abstraction_rtos_threads + */ +typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg); + +/** + * The callback function to be called by a timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); + +/** + * Return the last error from the RTOS. + * + * The functions in the RTOS abstraction layer adhere to the Cypress return + * results calling convention. The underlying RTOS implementations will not but rather + * will have their own error code conventions. This function is provided as a service + * to the developer, mostly for debugging, and returns the underlying RTOS error code + * from the last RTOS abstraction layer that returned \ref CY_RTOS_GENERAL_ERROR. + * + * @return RTOS specific error code. + * + * \ingroup group_abstraction_rtos_common + */ +cy_rtos_error_t cy_rtos_last_error(); + +/*********************************************** Threads **********************************************/ + +/** + * \ingroup group_abstraction_rtos_threads + * \{ + */ + +/** Create a thread with specific thread argument. + * + * This function is called to startup a new thread. If the thread can exit, it must call + * \ref cy_rtos_exit_thread() just before doing so. All created threads that can terminate, either + * by themselves or forcefully by another thread MUST have \ref cy_rtos_join_thread() called on them + * by another thread in order to cleanup any resources that might have been allocated for them. + * + * @param[out] thread Pointer to a variable which will receive the new thread handle + * @param[in] entry_function Function pointer which points to the main function for the new thread + * @param[in] name String thread name used for a debugger + * @param[in] stack The buffer to use for the thread stack. This must be aligned to + * \ref CY_RTOS_ALIGNMENT_MASK with a size of at least \ref CY_RTOS_MIN_STACK_SIZE. + * If stack is null, cy_rtos_create_thread will allocate a stack from the heap. + * @param[in] stack_size The size of the thread stack in bytes + * @param[in] priority The priority of the thread. Values are operating system specific, but some + * common priority levels are defined: + * CY_THREAD_PRIORITY_LOW + * CY_THREAD_PRIORITY_NORMAL + * CY_THREAD_PRIORITY_HIGH + * @param[in] arg The argument to pass to the new thread + * + * @return The status of thread create request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); + +/** Exit the current thread. + * + * This function is called just before a thread exits. In some cases it is sufficient + * for a thread to just return to exit, but in other cases, the RTOS must be explicitly + * signaled. In cases where a return is sufficient, this should be a null funcition. + * where the RTOS must be signaled, this function should perform that In cases operation. + * In code using RTOS services, this function should be placed at any at any location + * where the main thread function will return, exiting the thread. Threads that can + * exit must still be joined (\ref cy_rtos_join_thread) to ensure their resources are + * fully cleaned up. + * + * @return The status of thread exit request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_exit_thread(); + +/** Terminates another thread. + * + * This function is called to terminate another thread and reap the resources claimed + * by the thread. This should be called both when forcibly terminating another thread + * as well as any time a thread can exit on its own. For some RTOS implementations + * this is not required as the thread resources are claimed as soon as it exits. In + * other cases, this must be called to reclaim resources. Threads that are terminated + * must still be joined (\ref cy_rtos_join_thread) to ensure their resources are fully + * cleaned up. + * + * @param[in] thread Handle of the thread to terminate + * + * @returns The status of the thread terminate. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); + +/** Waits for a thread to complete. + * + * This must be called on any thread that can complete to ensure that any resources that + * were allocated for it are cleaned up. + * + * @param[in] thread Handle of the thread to wait for + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); + +/** Checks if the thread is running + * + * This function is called to determine if a thread is actively running or not. For information on + * the thread state, use the \ref cy_rtos_get_thread_state() function. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] running Returns true if the thread is running, otherwise false + * + * @returns The status of the thread running check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); + +/** Gets the state the thread is currently in + * + * This function is called to determine if a thread is running/blocked/inactive/ready etc. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] state Returns the state the thread is currently in + * + * @returns The status of the thread state check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); + +/** Get current thread handle + * + * Returns the unique thread handle of the current running thread. + * + * @param[out] thread Handle of the current running thread + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread); + +/** \} group_abstraction_rtos_threads */ + +/*********************************************** Mutexes **********************************************/ + +/** + * \ingroup group_abstraction_rtos_mutex + * \{ + */ + +/** Create a recursive mutex. + * + * Creates a binary mutex which can be used to synchronize between threads + * and between threads and ISRs. Created mutexes are recursive and support priority inheritance. + * + * This function has been replaced by \ref cy_rtos_init_mutex2 which allow for specifying + * whether or not the mutex supports recursion or not. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +#define cy_rtos_init_mutex(mutex) cy_rtos_init_mutex2(mutex, true) + +/** Create a mutex which can support recursion or not. + * + * Creates a binary mutex which can be used to synchronize between threads and between threads and + * ISRs. Created mutexes can support priority inheritance if recursive. + * + * \note Not all RTOS implementations support non-recursive mutexes. In this case a recursive + * mutex will be created. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * @param[in] recursive Should the created mutex support recursion or not + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive); + +/** Get a mutex. + * + * If the mutex is available, it is acquired and this function returned. + * If the mutex is not available, the thread waits until the mutex is available + * or until the timeout occurs. + * + * @note This function must not be called from an interrupt context as it may block. + * + * @param[in] mutex Pointer to the mutex handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the mutex. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. + * Must be zero if in_isr is true. + * + * @return The status of the get mutex. Returns timeout if mutex was not acquired + * before timeout_ms period. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); + +/** Set a mutex. + * + * The mutex is released allowing any other threads waiting on the mutex to + * obtain the semaphore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status of the set mutex request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + * + */ +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); + +/** Deletes a mutex. + * + * This function frees the resources associated with a sempahore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status to the delete request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); + +/** \} group_abstraction_rtos_mutex */ + +/*********************************************** Semaphores **********************************************/ + +/** + * \ingroup group_abstraction_rtos_semaphore + * \{ + */ + +/** + * Create a semaphore + * + * This is basically a counting semaphore. + * + * @param[in,out] semaphore Pointer to the semaphore handle to be initialized + * @param[in] maxcount The maximum count for this semaphore + * @param[in] initcount The initial count for this semaphore + * + * @return The status of the semaphore creation. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount); + +/** + * Get/Acquire a semaphore + * + * If the semaphore count is zero, waits until the semaphore count is greater than zero. + * Once the semaphore count is greater than zero, this function decrements + * the count and return. It may also return if the timeout is exceeded. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the semaphore. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. Must + * be zero is in_isr is true + * @param[in] in_isr true if we are trying to get the semaphore from with an ISR + * @return The status of get semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); + +/** + * Set/Release a semaphore + * + * Increments the semaphore count, up to the maximum count for this semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] in_isr Value of true indicates calling from interrupt context + * Value of false indicates calling from normal thread context + * @return The status of set semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); + +/** + * Get the count of a semaphore. + * + * Gets the number of available tokens on the semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[out] count Pointer to the return count + * @return The status of get semaphore count operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count); + +/** + * Deletes a semaphore + * + * This function frees the resources associated with a semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * + * @return The status of semaphore deletion [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); + +/** \} group_abstraction_rtos_semaphore */ + +/*********************************************** Events **********************************************/ + +/** + * \ingroup group_abstraction_rtos_event + * \{ + */ + +/** Create an event. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. + * + * @param[in,out] event Pointer to the event handle to be initialized + * + * @return The status of the event initialization request. + * [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_event(cy_event_t *event); + +/** Set the event flag bits. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. Any threads waiting on this event are released + * + * @param[in] event Pointer to the event handle + * @param[in] bits The value of the 32 bit flags + * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread + * + * @return The status of the set request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** + * Clear the event flag bits + * + * This function clears bits in the event. + * + * @param[in] event Pointer to the event handle + * @param[in] bits Any bits set in this value, will be cleared in the event. + * @param[in] in_isr if true, this is called from an ISR, otherwise from a thread + * + * @return The status of the clear flags request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** Get the event bits. + * + * Returns the current bits for the event. + * + * @param[in] event Pointer to the event handle + * @param[out] bits pointer to receive the value of the event flags + * + * @return The status of the get request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); + +/** Wait for the event and return bits. + * + * Waits for the event to be set and then returns the bits associated + * with the event, or waits for the given timeout period. + * @note This function returns if any bit in the set is set. + * + * @param[in] event Pointer to the event handle + * @param[in,out] bits pointer to receive the value of the event flags + * @param[in] clear if true, clear any bits set that cause the wait to return + * if false, do not clear bits + * @param[in] all if true, all bits in the initial bits value must be set to return + * if false, any one bit in the initial bits value must be set to return + * @param[in] timeout The amount of time to wait in milliseconds + * + * @return The status of the wait for event request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); + +/** Deinitialize a event. + * + * This function frees the resources associated with an event. + * + * @param[in] event Pointer to the event handle + * + * @return The status of the deletion request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); + +/** \} group_abstraction_rtos_event */ + +/*********************************************** Queues **********************************************/ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** Create a queue. + * + * This is a queue of data where entries are placed on the back of the queue + * and removed from the front of the queue. + * + * @param[out] queue Pointer to the queue handle + * @param[in] length The maximum length of the queue in items + * @param[in] itemsize The size of each item in the queue. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); + +/** Put an item in a queue. + * + * This function puts an item in the queue. The item is copied + * into the queue using a memory copy and the data pointed to by item_ptr + * is no longer referenced once the call returns. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the item to place in the queue + * @param[in] timeout_ms The time to wait to place the item in the queue + * @param[in] in_isr If true this is being called from within and ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_FULL] + */ +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Gets an item in a queue. + * + * This function gets an item from the queue. The item is copied + * out of the queue into the memory provide by item_ptr. This space must be + * large enough to hold a queue entry as defined when the queue was initialized. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the memory for the item from the queue + * @param[in] timeout_ms The time to wait to get an item from the queue + * @param[in] in_isr If true this is being called from within an ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_EMPTY] + */ +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Return the number of items in the queue. + * + * This function returns the number of items currently in the queue. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_waiting Pointer to the return count + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); + +/** Return the amount of empty space in the queue. + * + * This function returns the amount of empty space in the + * queue. For instance, if the queue was created with 10 entries max and there + * are currently 2 entries in the queue, this will return 8. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_spaces Pointer to the return count. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); + +/** Reset the queue. + * + * This function sets the queue to empty. + * + * @param[in] queue pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); + +/** Deinitialize the queue handle. + * + * This function de-initializes the queue and returns all + * resources used by the queue. + * + * @param[in] queue Pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** Timers **********************************************/ + +/** + * \ingroup group_abstraction_rtos_timer + * \{ + */ + +/** Create a new timer. + * + * This function initializes a timer object. + * @note The timer is not active until start is called. + * @note The callback may be (likely will be) called from a different thread. + * + * @param[out] timer Pointer to the timer handle to initialize + * @param[in] type Type of timer (periodic or once) + * @param[in] fun The function + * @param[in] arg Argument to pass along to the callback function + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg); + +/** Start a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[in] num_ms The number of milliseconds to wait before the timer fires + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); + +/** Stop a timer. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); + +/** Returns state of a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[out] state Return value for state, true if running, false otherwise + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); + +/** Deinit the timer. + * + * This function deinitializes the timer and frees all consumed resources. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); + +/** \} group_abstraction_rtos_timer */ + +/*********************************************** Time **********************************************/ + +/** + * \ingroup group_abstraction_rtos_time + * \{ + */ + +/** Gets time in milliseconds since RTOS start. + * + * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds + * + * @param[out] tval Pointer to the struct to populate with the RTOS time + * + * @returns Time in milliseconds since the RTOS started. + */ +cy_rslt_t cy_rtos_get_time(cy_time_t *tval); + +/** Delay for a number of milliseconds. + * + * Processing of this function depends on the minimum sleep + * time resolution of the RTOS. The current thread should sleep for + * the longest period possible which is less than the delay required, + * then makes up the difference with a tight loop. + * + * @param[in] num_ms The number of milliseconds to delay for + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); + +/** \} group_abstraction_rtos_time */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_impl.h new file mode 100644 index 00000000000..8b36a68844a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_impl.h @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cyabs_rtos_impl.h +* +* \brief +* Internal definitions for RTOS abstraction layer +* +******************************************************************************** +* \copyright +* Copyright 2019-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + + +#ifndef INCLUDED_CYABS_RTOS_IMPL_H_ +#define INCLUDED_CYABS_RTOS_IMPL_H_ + +#include "cmsis_os2.h" +#include "rtx_os.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size in bytes */ +#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ +#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignment of created RTOS objects */ + + +/****************************************************** +* Type Definitions +******************************************************/ + +/* RTOS thread priority */ +typedef enum +{ + CY_RTOS_PRIORITY_MIN = osPriorityNone, + CY_RTOS_PRIORITY_LOW = osPriorityLow, + CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal, + CY_RTOS_PRIORITY_NORMAL = osPriorityNormal, + CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal, + CY_RTOS_PRIORITY_HIGH = osPriorityHigh, + CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime, + CY_RTOS_PRIORITY_MAX = osPriorityRealtime7 +} cy_thread_priority_t ; + +typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */ +typedef void * cy_thread_arg_t; /** Argument passed to the entry function of a thread */ +typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */ +typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */ +typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */ +typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */ +typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */ +typedef void * cy_timer_callback_arg_t; /** Argument passed to the timer callback function */ +typedef uint32_t cy_time_t; /** Time in milliseconds */ +typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c new file mode 100644 index 00000000000..37c70fe5c74 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c @@ -0,0 +1,863 @@ +/***************************************************************************//** +* \file cyabs_rtos.c +* +* \brief +* Implementation for CMSIS RTOS v2 abstraction +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + + +/****************************************************** +* Error Converter +******************************************************/ + +/* Last received error status */ +static cy_rtos_error_t dbgErr; +cy_rtos_error_t cy_rtos_last_error() { return dbgErr; } + +/* Converts internal error type to external error type */ +static cy_rslt_t error_converter(cy_rtos_error_t internalError) +{ + cy_rslt_t value; + + switch (internalError) + { + case osOK: + value = CY_RSLT_SUCCESS; + break; + case osErrorTimeout: + value = CY_RTOS_TIMEOUT; + break; + case osErrorParameter: + value = CY_RTOS_BAD_PARAM; + break; + case osErrorNoMemory: + value = CY_RTOS_NO_MEMORY; + break; + case osError: + case osErrorResource: + case osErrorISR: + default: + value = CY_RTOS_GENERAL_ERROR; + break; + } + + /* Update the last known error status */ + dbgErr = internalError; + return value; +} + + +/****************************************************** +* Threads +******************************************************/ + +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + osThreadAttr_t attr; + + if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE) + status = CY_RTOS_BAD_PARAM; + else if (stack != NULL && (0 != (((uint32_t)stack) & CY_RTOS_ALIGNMENT_MASK))) + status = CY_RTOS_ALIGNMENT_ERROR; + else + { + attr.name = name; + attr.attr_bits = osThreadJoinable; + attr.cb_size = osRtxThreadCbSize; + attr.stack_size = stack_size; + attr.priority = (osPriority_t)priority; + attr.tz_module = 0; + attr.reserved = 0; + + /* Allocate stack if NULL was passed */ + if ((uint32_t *)stack == NULL) + { + /* Note: 1 malloc so that it can be freed with 1 call when terminating */ + uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK; + attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size); + if (attr.cb_mem != NULL) + attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad); + } + else + { + attr.cb_mem = malloc(osRtxThreadCbSize); + attr.stack_mem = stack; + } + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *thread = osThreadNew((osThreadFunc_t)entry_function, arg, &attr); + CY_ASSERT((*thread == attr.cb_mem) || (*thread == NULL)); + status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_exit_thread() +{ + /* This does not have a return statement because the osThreadExit() function + * does not return so the return statement would be unreachable and causes a + * warning for IAR compiler. + */ + osThreadExit(); +} + +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadTerminate(*thread); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (running == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + switch (osThreadGetState(*thread)) + { + case osThreadInactive: + *state = CY_THREAD_STATE_INACTIVE; + break; + case osThreadReady: + *state = CY_THREAD_STATE_READY; + break; + case osThreadRunning: + *state = CY_THREAD_STATE_RUNNING; + break; + case osThreadBlocked: + *state = CY_THREAD_STATE_BLOCKED; + break; + case osThreadTerminated: + *state = CY_THREAD_STATE_TERMINATED; + break; + case osThreadError: + case osThreadReserved: + default: + *state = CY_THREAD_STATE_UNKNOWN; + break; + } + } + + return status; +} + +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadJoin(*thread); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*thread); + *thread = NULL; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + *thread = osThreadGetId(); + + return status; +} + + +/****************************************************** +* Mutexes +******************************************************/ + +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive) +{ + cy_rslt_t status; + osMutexAttr_t attr; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = osMutexPrioInherit; + if (recursive) + { + attr.attr_bits |= osMutexRecursive; + } + attr.cb_mem = malloc(osRtxMutexCbSize); + attr.cb_size = osRtxMutexCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *mutex = osMutexNew(&attr); + CY_ASSERT((*mutex == attr.cb_mem) || (*mutex == NULL)); + status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexAcquire(*mutex, timeout_ms); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexRelease(*mutex); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexDelete(*mutex); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*mutex); + *mutex = NULL; + } + } + + return status; +} + + +/****************************************************** +* Semaphores +******************************************************/ + +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount) +{ + cy_rslt_t status; + osSemaphoreAttr_t attr; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxSemaphoreCbSize); + attr.cb_size = osRtxSemaphoreCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *semaphore = osSemaphoreNew(maxcount, initcount, &attr); + CY_ASSERT((*semaphore == attr.cb_mem) || (*semaphore == NULL)); + status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreRelease(*semaphore); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count) +{ + cy_rslt_t status; + if (semaphore == NULL || count == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + *count = osSemaphoreGetCount(*semaphore); + status = CY_RSLT_SUCCESS; + } + return status; +} + +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreDelete(*semaphore); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*semaphore); + *semaphore = NULL; + } + } + + return status; +} + + +/****************************************************** +* Events +******************************************************/ + +#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL +#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL + +cy_rslt_t cy_rtos_init_event(cy_event_t *event) +{ + cy_rslt_t status; + osEventFlagsAttr_t attr; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxEventFlagsCbSize); + attr.cb_size = osRtxEventFlagsCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *event = osEventFlagsNew(&attr); + CY_ASSERT((*event == attr.cb_mem) || (*event == NULL)); + status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsSet(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsClear(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *bits = osEventFlagsGet(*event); + + return status; +} + +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + uint32_t flagOption; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny; + if (!clear) + flagOption |= osFlagsNoClear; + + statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL) + *bits = statusInternal; + else + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osEventFlagsDelete(*event); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*event); + *event = NULL; + } + } + + return status; +} + + +/****************************************************** +* Queues +******************************************************/ + +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) +{ + cy_rslt_t status; + osMessageQueueAttr_t attr; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_size = osRtxMessageQueueCbSize; + uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); + attr.mq_size = blockSize * length; + + /* Note: 1 malloc for both so that they can be freed with 1 call */ + uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; + attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); + if (attr.cb_mem != NULL) + attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad); + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *queue = osMessageQueueNew(length, itemsize, &attr); + CY_ASSERT((*queue == attr.cb_mem) || (*queue == NULL)); + status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_waiting == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_waiting = osMessageQueueGetCount(*queue); + + return status; +} + +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_spaces == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_spaces = osMessageQueueGetSpace(*queue); + + return status; +} + +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueReset(*queue); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueDelete(*queue); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*queue); + *queue = NULL; + } + } + + return status; +} + + +/****************************************************** +* Timers +******************************************************/ + +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg) +{ + cy_rslt_t status; + osTimerAttr_t attr; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxTimerCbSize); + attr.cb_size = osRtxTimerCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) + ? osTimerPeriodic + : osTimerOnce; + + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr ); + CY_ASSERT((*timer == attr.cb_mem) || (*timer == NULL)); + status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + uint32_t tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + { + uint32_t ticks = ((num_ms * tick_freq) / 1000); + statusInternal = osTimerStart(*timer, ticks); + status = error_converter(statusInternal); + } + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerStop(*timer); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((timer == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *state = osTimerIsRunning(*timer); + + return status; +} + +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerDelete(*timer); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*timer); + *timer = NULL; + } + } + + return status; +} + + +/****************************************************** +* Time +******************************************************/ + +cy_rslt_t cy_rtos_get_time(cy_time_t *tval) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + uint32_t tick_freq; + + if (tval == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + *tval = (cy_time_t)((osKernelGetTickCount() * 1000LL) / tick_freq); + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + statusInternal = osDelay(num_ms); + status = error_converter(statusInternal); + + return status; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_gpio.h new file mode 100644 index 00000000000..08d4e5bfb13 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_gpio.h @@ -0,0 +1,247 @@ +/***************************************************************************//** +* \file cyhal_gpio.h +* +* \brief +* Provides a high level interface for interacting with the GPIO on Cypress devices. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_gpio GPIO (General Purpose Input Output) +* \ingroup group_hal +* \{ +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/******************************************************************************* +* Defines +*******************************************************************************/ + +/** Integer representation of no connect pin (required to exist in all BSPs) */ +#define CYHAL_NC_PIN_VALUE (NC) + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Pin events */ +typedef enum { + CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ + CYHAL_GPIO_IRQ_RISE = 1 << 0, /**< Interrupt on rising edge */ + CYHAL_GPIO_IRQ_FALL = 1 << 1, /**< Interrupt on falling edge */ + CYHAL_GPIO_IRQ_BOTH = (CYHAL_GPIO_IRQ_RISE | CYHAL_GPIO_IRQ_FALL), /**< Interrupt on both rising and falling edges */ +} cyhal_gpio_event_t; + +/** Pin direction */ +typedef enum { + CYHAL_GPIO_DIR_INPUT, /**< Input pin */ + CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ + CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ +} cyhal_gpio_direction_t; + +/** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ +typedef enum { + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z. Use only for analog purpose */ + CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_STRONG, /**< Strong output. Output only. Output init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULL_NONE, /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ +} cyhal_gpio_drive_mode_t; + +/** GPIO callback function type */ +typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); + +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin + * + * @return The status of the init request + * + * Guidance for using gpio drive modes ( \ref cyhal_gpio_drive_mode_t for details). + * For default use drive modes: + * Input GPIO direction - \ref CYHAL_GPIO_DRIVE_NONE + * Output GPIO direction - \ref CYHAL_GPIO_DRIVE_STRONG + * Bidirectional GPIO - \ref CYHAL_GPIO_DRIVE_PULLUPDOWN + * \warning Don't use \ref CYHAL_GPIO_DRIVE_STRONG for input GPIO direction. It may cause an overcurrent issue. + */ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); + +/** Uninitialize the gpio peripheral and the cyhal_gpio_t object + * + * @param[in] pin Pin number + */ +void cyhal_gpio_free(cyhal_gpio_t pin); + +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. + * + * @param[in] pin The GPIO pin + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * + * @return The status of the configure request + */ +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode); + +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. + * + * @param[in] pin The GPIO object + * @param[in] value The value to be set (high = true, low = false) + */ +void cyhal_gpio_write(cyhal_gpio_t pin, bool value); + +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO object + * @return The value of the IO (true = high, false = low) + */ +bool cyhal_gpio_read(cyhal_gpio_t pin); + +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. + * @param[in] pin The GPIO object + */ +void cyhal_gpio_toggle(cyhal_gpio_t pin); + +/** Register/clear a callback handler for pin events
+ * + * This function will be called when one of the events enabled by \ref cyhal_gpio_enable_event occurs. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The pin number + * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. + * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL + */ +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); + +/** Enable or Disable the specified GPIO event
+ * + * When an enabled event occurs, the function specified by \ref cyhal_gpio_register_callback will be called. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The GPIO object + * @param[in] event The GPIO event + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) +#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; +/** \endcond */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#ifdef CYHAL_GPIO_IMPL_HEADER +#include CYHAL_GPIO_IMPL_HEADER +#endif /* CYHAL_GPIO_IMPL_HEADER */ + +/** \} group_hal_gpio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_sdio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_sdio.h new file mode 100644 index 00000000000..d5600efd997 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_sdio.h @@ -0,0 +1,366 @@ +/***************************************************************************//** +* \file cyhal_sdio.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SDIO interface. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) +* \ingroup group_hal +* \{ +* High level interface to the Secure Digital Input Output (SDIO). +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in \ref cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). +* +* The SDIO protocol is an extension of the SD +* interface for general I/O functions. Refer to the SD Specifications Part 1 SDIO +* Specifications Version 4.10 for more information on the SDIO protocol and specifications. +* +* +* \section subsection_sdio_features Features +* * Supports 4-bit interface +* * Supports Ultra High Speed (UHS-I) mode +* * Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes +* * Supports SDIO card interrupts in both 1-bit and 4-bit modes +* * Supports Standard capacity (SDSC), High capacity (SDHC) and Extended capacity (SDXC) memory +* +* \section subsection_sdio_quickstart Quick Start +* +* \ref cyhal_sdio_init initializes the SDIO peripheral and passes a pointer to the SDIO block through the **obj** object of type \ref cyhal_sdio_t. +* +* \section subsection_sdio_code_snippets Code Snippets +* +* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example +* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration +* +* \snippet sdio.c snippet_cyhal_sdio_simple_init +* +* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt +* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events. +* +* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback +* +* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands +* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands. +* +* \snippet sdio.c snippet_cyhal_sdio_send_command +* +* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer +* The following snippet shows how to start a bulk data transfer. +* +* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer +* +* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer +* +* The following snippet shows how to start an async data transfer. +* \snippet sdio.c snippet_cyhal_sdio_async_transfer +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Defines +*******************************************************************************/ + +#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ +#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ +#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ +#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ +#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ +#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ +#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ + +#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ +#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ +#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ +#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ +#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/ + +/* HAL return value defines */ + +/** \addtogroup group_hal_results_sdio SDIO HAL Results + * SDIO specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Incorrect parameter value define */ +#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT)) +/** Clock initialization error define */ +#define CYHAL_SDIO_RSLT_ERR_CLOCK \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR)) +/** Semaphore not initiated error define */ +#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED)) +/** Error define based on SDIO lower function return value */ +#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal))) +/** Define to indicate canceled operation */ +#define CYHAL_SDIO_RSLT_CANCELED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED)) +/** Transfers are not allowed after the SDIO block has allowed power mode transition. */ +#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR)) + +/** + * \} + */ + + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Commands that can be issued */ +typedef enum +{ + CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!< Go to idle state + CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!< Send a relative address + CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!< Send an OP IO + CYHAL_SDIO_CMD_SELECT_CARD = 7, //!< Send a card select + CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!< Go to inactive state + CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!< Perform a direct read/write + CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!< Perform an extended read/write +} cyhal_sdio_command_t; + +/** Types of transfer that can be performed */ +typedef enum +{ + CYHAL_READ, //!< Read from the card + CYHAL_WRITE //!< Write to the card +} cyhal_transfer_t; + +/** Types of events that could be asserted by SDIO */ +typedef enum { + /* Interrupt-based thread events */ + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!< Command Complete + CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete + CYHAL_SDIO_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped + CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDIO_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDIO_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDIO_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!< The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDIO_INT_A = 0x00200, //!< Reserved: set to 0 + CYHAL_SDIO_INT_B = 0x00400, //!< Reserved: set to 0 + CYHAL_SDIO_INT_C = 0x00800, //!< Reserved: set to 0 + CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!< Reserved: set to 0 + CYHAL_SDIO_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1 + CYHAL_SDIO_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set + + /* Non-interrupt-based thread events */ + CYHAL_SDIO_GOING_DOWN = 0x10000, //!< The interface is going away (eg: powering down for some period of time) + CYHAL_SDIO_COMING_UP = 0x20000, //!< The interface is back up (eg: came back from a low power state) + + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!< Is used to enable/disable all interrupts events +} cyhal_sdio_event_t; + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ + +/** @brief SDIO controller initial configuration */ +typedef struct +{ + uint32_t frequencyhal_hz; //!< Clock frequency, in hertz + uint16_t block_size; //!< Block size +} cyhal_sdio_cfg_t; + +/** Callback for SDIO events */ +typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ +/** Initialize the SDIO peripheral + * + * @param[out] obj Pointer to an SDIO object. + * The caller must allocate the memory for this object but the init + * function will initialize its contents. + * @param[out] clk The pin connected to the clk signal + * @param[in] cmd The pin connected to the command signal + * @param[in] data0 The pin connected to the data0 signal + * @param[in] data1 The pin connected to the data1 signal + * @param[in] data2 The pin connected to the data2 signal + * @param[in] data3 The pin connected to the data3 signal + * @return The status of the init request + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_1 for more information. + */ +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3); + +/** Release the SDIO block. + * + * @param[in,out] obj The SDIO object + */ +void cyhal_sdio_free(cyhal_sdio_t *obj); + +/** Configure the SDIO block with required parameters. Refer \ref cyhal_sdio_cfg_t for more information. + * + * @param[in,out] obj The SDIO object + * @param[in] config The SDIO configuration to apply + * @return The status of the configure request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); + +/** Sends command to the SDIO device. See \ref cyhal_sdio_command_t for list of available commands. + * + * This will block until the command is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] command The command to send to the SDIO device + * @param[in] argument The argument to the command + * @param[out] response The response from the SDIO device + * @return The status of the command transfer. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_3 for more information. + */ +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response); + +/** Performs a bulk data transfer. Sends \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command (CMD=53) which allows writing and reading of a large number of I/O registers with a single command. + * + * This will block until the transfer is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. + * @param[in] length The number of bytes to send + * @param[out] response The response from the SDIO device + * @return The status of the bulk transfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_4 for more information. + */ +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response); + +/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block. + * After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted. + * + * To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy() + * until it returns false. + * The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled + * after the asynchronous transfer is complete and in the condition they were + * enabled in before the transfer operation started. Handle these events in the interrupt callback. + * + * When the transfer is complete, the \ref CYHAL_SDIO_XFER_COMPLETE event will be raised. + * See \ref cyhal_sdio_register_callback and \ref cyhal_sdio_enable_event. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device + * @param[in] length The number of bytes to send + * @return The status of the async tranfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_5 for more information. + */ +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length); + +/** Checks if the specified SDIO is in use + * + * @param[in] obj The SDIO peripheral to check + * @return true if SDIO is in use. false, otherwise. + */ +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); + +/** Abort an SDIO transfer + * + * @param[in] obj The SDIO peripheral to stop + * @return The status of the abort_async request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); + +/** Register an SDIO event callback to be invoked when the event is triggered. + * + * This function will be called when one of the events enabled by \ref cyhal_sdio_enable_event occurs. + * + * @param[in] obj The SDIO object + * @param[in] callback The callback function which will be invoked when the event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when executed + * + * Refer \ref subsection_sdio_use_case_2 for more implementation. + */ +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); + +/** Enables callbacks to be triggered for specified SDIO events. Refer \ref cyhal_sdio_event_t for all events. + * + * @param[in] obj The SDIO object + * @param[in] event The SDIO event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable Set to true to enable events, or false to disable them + * + * Refer \ref subsection_sdio_use_case_2 for more information. + */ +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_sdio_register_irq cyhal_sdio_register_callback +#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; +typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SDIO_IMPL_HEADER +#include CYHAL_SDIO_IMPL_HEADER +#endif /* CYHAL_SDIO_IMPL_HEADER */ + +/** \} group_hal_sdio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_spi.h new file mode 100644 index 00000000000..f5ba47669f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/interface/cyhal_spi.h @@ -0,0 +1,383 @@ +/***************************************************************************//** +* \file cyhal_spi.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SPI. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_spi SPI (Serial Peripheral Interface) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. +* +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_results_spi SPI HAL Results + * SPI specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Bad argument */ +#define CYHAL_SPI_RSLT_BAD_ARGUMENT \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) +/** Failed to initialize SPI clock */ +#define CYHAL_SPI_RSLT_CLOCK_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1)) +/** Failed to Transfer SPI data */ +#define CYHAL_SPI_RSLT_TRANSFER_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2)) +/** Provided clock is not supported by SPI */ +#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6)) +/** The requested resource type is invalid */ +#define CYHAL_SPI_RSLT_ERR_INVALID_PIN \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) +/** Cannot configure SSEL signal */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_CONFIG_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 8)) +/** Cannot switch SSEL - device is busy or incorrect pin provided */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 9)) + +/** + * \} + */ + +/** Compatibility define for cyhal_spi_set_frequency. */ +#define cyhal_spi_frequency cyhal_spi_set_frequency + +/** SPI interrupt triggers */ +typedef enum { + /** All transfer data has been moved into data FIFO */ + CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, + /** Transfer complete. */ + CYHAL_SPI_IRQ_DONE = 1 << 2, + /** An error occurred while transferring data */ + CYHAL_SPI_IRQ_ERROR = 1 << 3, +} cyhal_spi_event_t; + +/** SPI Slave Select polarity */ +typedef enum { + /** SSEL signal is active low */ + CYHAL_SPI_SSEL_ACTIVE_LOW = 0, + /** SSEL signal is active high */ + CYHAL_SPI_SSEL_ACTIVE_HIGH = 1, +} cyhal_spi_ssel_polarity_t; + +/** Handler for SPI interrupts */ +typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); + +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the LSB is sent first. */ +#define CYHAL_SPI_MODE_FLAG_LSB (0x01u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPHA=1. */ +#define CYHAL_SPI_MODE_FLAG_CPHA (0x02u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPOL=1. */ +#define CYHAL_SPI_MODE_FLAG_CPOL (0x04u) +/** Creates a \ref cyhal_spi_mode_t value given the cpol, cpha, lsb values. */ +#define CYHAL_SPI_MODE(cpol, cpha, lsb) (((cpol > 0) ? CYHAL_SPI_MODE_FLAG_CPOL : 0) | \ + ((cpha > 0) ? CYHAL_SPI_MODE_FLAG_CPHA : 0) | \ + (( lsb > 0) ? CYHAL_SPI_MODE_FLAG_LSB : 0)) + +/** SPI operating modes */ +typedef enum +{ + /** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_00_MSB = CYHAL_SPI_MODE(0, 0, 0), + /** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_00_LSB = CYHAL_SPI_MODE(0, 0, 1), + /** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_01_MSB = CYHAL_SPI_MODE(0, 1, 0), + /** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_01_LSB = CYHAL_SPI_MODE(0, 1, 1), + /** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_10_MSB = CYHAL_SPI_MODE(1, 0, 0), + /** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_10_LSB = CYHAL_SPI_MODE(1, 0, 1), + /** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_11_MSB = CYHAL_SPI_MODE(1, 1, 0), + /** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1), +} cyhal_spi_mode_t; + +/** @brief Initial SPI configuration. */ +typedef struct +{ + cyhal_spi_mode_t mode; //!< The operating mode + uint8_t data_bits; //!< The number of bits per transfer + bool is_slave; //!< Whether the peripheral is operating as slave or master +} cyhal_spi_cfg_t; + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj Pointer to a SPI object. The caller must allocate the memory + * for this object but the init function will initialize its contents. + * @param[in] mosi The pin to use for MOSI + * @note At least MOSI or MISO pin should be non-NC + * @param[in] miso The pin to use for MISO + * @note At least MOSI or MISO pin should be non-NC + * @param[in] sclk The pin to use for SCLK + * @note This pin cannot be NC + * @param[in] ssel The pin to use for SSEL + * @note Provided pin will be configured for \ref CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed + * (as well as additional ssel pins can be added) by \ref cyhal_spi_slave_select_config and \ref cyhal_spi_select_active_ssel + * functions. This pin can be NC. + * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[in] bits The number of bits per frame + * @note bits should be 8 or 16 + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] is_slave false for master mode or true for slave mode operation + * @return The status of the init request + */ +cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, + const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave); + +/** Release a SPI object + * + * Return the peripheral, pins and clock owned by the SPI object to their reset state + * @param[in,out] obj The SPI object to deinitialize + */ +void cyhal_spi_free(cyhal_spi_t *obj); + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + * @return The status of the set_frequency request + */ +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); + +/** Configures provided ssel pin to work as SPI slave select with specified polarity. + * + * Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching + * between configured slave select pins is done by \ref cyhal_spi_select_active_ssel function. + * Unless modified with this function, the SSEL pin provided as part of \ref cyhal_spi_init is the default. + * @param[in] obj The SPI object to add slave select for + * @param[in] ssel Slave select pin to be added + * @param[in] polarity Polarity of slave select + * @return The status of ssel pin configuration + */ +cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity); + +/** Selects an active slave select line from one of available. + * + * This function is applicable for the master and slave. + * SSEL pin should be configured by \ref cyhal_spi_slave_select_config or \ref cyhal_spi_init functions prior + * to selecting it as active. The active slave select line will automatically be toggled as part of any transfer. + * @param[in] obj The SPI object for switching + * @param[in] ssel Slave select pin to be set as active + * @return CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL + */ +cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel); + +/** Synchronously get a received value out of the SPI receive buffer + * + * In Master mode - transmits fill-in value and read the data from RxFifo + * In Slave mode - Blocks until a value is available + * + * @param[in] obj The SPI peripheral to read + * @param[in] value The value received + * @return The status of the read request + * @note + * - In Master mode, MISO pin required to be non-NC for this API to operate + * - In Slave mode, MOSI pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); + +/** Synchronously send a byte out + * + * In Master mode transmits value to slave and read/drop a value from the RxFifo. + * In Slave mode writes a value to TxFifo + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return The status of the write request + * @note + * - In Master mode, MOSI pin required to be non-NC for this API to operate + * - In Slave mode, MISO pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); + +/** Synchronously Write a block out and receive a value + * + * The total number of bytes sent and received will be the maximum of tx_length + * and rx_length. The bytes written will be padded (at the end) with the value + * given by write_fill. + * + * This function will block for the duration of the transfer. \ref cyhal_spi_transfer_async + * can be used for non-blocking transfers. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx Pointer to the byte-array of data to write to the device + * @param[in,out] tx_length Number of bytes to write, updated with the number actually written + * @param[out] rx Pointer to the byte-array of data to read from the device + * @param[in,out] rx_length Number of bytes to read, updated with the number actually read + * @param[in] write_fill Default data transmitted while performing a read + * @return The status of the transfer request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill); + +/** Start an asynchronous SPI transfer. + * + * This will transfer `rx_length` bytes into the buffer pointed to by `rx`, while simultaneously transfering + * `tx_length` bytes of data from the buffer pointed to by `tx`, both in the background. + * When the transfer is complete, the @ref CYHAL_SPI_IRQ_DONE event will be raised. + * See @ref cyhal_spi_register_callback and @ref cyhal_spi_enable_event. + * \note For blocking transfers cyhal_spi_transfer can be used. + * + * @param[in] obj The SPI object that holds the transfer information + * @param[in] tx The transmit buffer + * @param[in,out] tx_length The number of bytes to transmit + * @param[out] rx The receive buffer + * @param[in,out] rx_length The number of bytes to receive + * @return The status of the transfer_async request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length); + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return Indication of whether the SPI is still transmitting + */ +bool cyhal_spi_is_busy(cyhal_spi_t *obj); + +/** Abort an SPI transfer + * + * @param[in] obj The SPI peripheral to stop + * @return The status of the abort_async request + */ +cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); + +/** Register a SPI callback handler + * + * This function will be called when one of the events enabled by \ref cyhal_spi_enable_event occurs. + * + * @param[in] obj The SPI object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); + +/** Configure SPI interrupt. This function is used for word-approach + * + * When an enabled event occurs, the function specified by \ref cyhal_spi_register_callback will be called. + * + * @param[in] obj The SPI object + * @param[in] event The SPI event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +typedef cyhal_spi_event_t cyhal_spi_irq_event_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SPI_IMPL_HEADER +#include CYHAL_SPI_IMPL_HEADER +#endif /* CYHAL_SPI_IMPL_HEADER */ + +/** \} group_hal_spi */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_hal.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_hal.c new file mode 100644 index 00000000000..f5a0716697c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_hal.c @@ -0,0 +1,63 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "cyhal.h" +#include "mbed_thread.h" +#include "mbed_wait_api.h" + +static cyhal_sdio_t sdio_obj; + +/* Edit Pin configuration */ +const pinconfig_t PinConfig[] = { + + [CYBSP_WIFI_WL_REG_ON] = WIFI_WL_REG_ON, +#ifdef CYBSP_WIFI_32K_CLK + [CYBSP_WIFI_32K_CLK] = WIFI_32K_CLK, +#endif /* CYBSP_WIFI_32K_CLK */ + [CYBSP_LED1 ] = BSP_LED1, + [CYBSP_LED2 ] = BSP_LED2, + [CYBSP_WIFI_SDIO_CMD] = WIFI_SDIO_CMD, + [CYBSP_WIFI_SDIO_CLK] = WIFI_SDIO_CLK, + [CYBSP_WIFI_SDIO_D0 ] = WIFI_SDIO_D0, + [CYBSP_WIFI_SDIO_D1 ] = WIFI_SDIO_D1, + [CYBSP_WIFI_SDIO_D2 ] = WIFI_SDIO_D2, + [CYBSP_WIFI_SDIO_D3 ] = WIFI_SDIO_D3, + [CYBSP_SDIO_OOB_IRQ ] = WIFI_SDIO_OOB_IRQ //VIKR +}; + +void Cy_SysLib_Delay(uint32_t milliseconds) +{ + thread_sleep_for(milliseconds); +} + +void Cy_SysLib_DelayUs(uint16_t microseconds) +{ + wait_us(microseconds); +} + +void cyhal_system_delay_ms(uint32_t milliseconds) +{ + Cy_SysLib_Delay(milliseconds); +} + +cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_syslib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_syslib.h new file mode 100644 index 00000000000..7671d853cfc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_syslib.h @@ -0,0 +1,592 @@ +/***************************************************************************//** +* \file cy_syslib.h +* \version 2.40.1 +* +* Provides an API declaration of the SysLib driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_syslib +* \{ +* The system libraries provide APIs that can be called in the user application +* to handle the timing, logical checking or register. +* +* The functions and other declarations used in this driver are in cy_syslib.h. +* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* and declarations in the PDL. +* +* The SysLib driver contains a set of different system functions. These functions +* can be called in the application routine. Major features of the system library: +* * Delay functions +* * The register Read/Write macro +* * Assert and Halt +* * Assert Classes and Levels +* * A software reset +* * Reading the reset cause +* * An API to invalidate the flash cache and buffer +* * Data manipulation macro +* * A variable type definition from MISRA-C which specifies signedness +* * Cross compiler compatible attributes +* * Getting a silicon-unique ID API +* * Setting wait states API +* * Resetting the backup domain API +* * APIs to serve Fault handler +* +* \section group_syslib_configuration Configuration Considerations +* Assertion Usage
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the +* program is running correctly. It is a convenient way to insert sanity checks. +* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of +* the PDL library. The behavior of the macro is as follows: if the expression +* passed to the macro is false, output an error message that includes the file +* name and line number, and then halts the CPU. \n +* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function. +* This is a weakly linked function. The default implementation stores the file +* name and line number of the ASSERT into global variables, cy_assertFileName +* and cy_assertLine . It then calls the Cy_SysLib_Halt() function. +* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing. +* +* The PDL source code uses this assert mechanism extensively. It is recommended +* that you enable asserts when debugging firmware. \n +* Assertion Classes and Levels
+* The PDL defines three assert classes, which correspond to different kinds +* of parameters. There is a corresponding assert "level" for each class. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Class MacroLevel MacroType of check
CY_ASSERT_CLASS_1CY_ASSERT_L1A parameter that could change between different PSoC devices +* (e.g. the number of clock paths)
CY_ASSERT_CLASS_2CY_ASSERT_L2A parameter that has fixed limits such as a counter period
CY_ASSERT_CLASS_3CY_ASSERT_L3A parameter that is an enum constant
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. +* This is a compiler command line argument, similar to how the DEBUG / NDEBUG +* macro is passed. \n +* Enabling any class also enables any lower-numbered class. +* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three +* classes. The following example shows the command-line option to enable all +* the assert levels: +* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode +* \note The use of special characters, such as spaces, parenthesis, etc. must +* be protected with quotes. +* +* After CY_ASSERT_LEVEL is defined, firmware can use +* one of the three level macros to make an assertion. For example, if the +* parameter can vary between devices, firmware uses the L1 macro. +* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode +* If the parameter has bounds, firmware uses L2. +* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode +* If the parameter is an enum, firmware uses L3. +* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode +* Each check uses the appropriate level macro for the kind of parameter being checked. +* If a particular assert class/level is not enabled, then the assert does nothing. +* +* \section group_syslib_more_information More Information +* Refer to the technical reference manual (TRM). +* +* \section group_syslib_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.This si required by design of the Cy_SysLib_Halt function.
18.4RUnions shall not be used.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers +* content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be +* defined, redefined or undefined.The driver defines the macros with leading underscores +* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
+* +* \section group_syslib_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.
Minor documentation edits.Documentation update and clarification.
Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
2.20Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.Provided support for the PDL static library in Release mode.
Minor documentation edits.Documentation update and clarification.
2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETRegister access simplification.
Removed the Cy_SysLib_GetNumHfclkResetCause API function.This feature is not supported by SRSS_ver1.
Added register access layer. Use register access macros instead +* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* not need to be recompiled for each supported part number.
2.0.1Minor documentation editsDocumentation update and clarification
2.0 +* Added Cy_SysLib_ResetBackupDomain() API implementation. \n +* Added CY_NOINLINE attribute implementation. \n +* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n +* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n +* Optimized Cy_SysLib_SetWaitStates() API implementation. +* Improvements made based on usability feedback.
Added Assertion Classes and Levels.For error checking, parameter validation and status returns in the PDL API.
Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.To store debug information into a non-zero init area for future analysis.
Removed CY_WEAK attribute implementation.CMSIS __WEAK attribute should be used instead.
1.0Initial version
+* +* \defgroup group_syslib_macros Macros +* \defgroup group_syslib_functions Functions +* \defgroup group_syslib_data_structures Data Structures +* \defgroup group_syslib_enumerated_types Enumerated Types +* +*/ + +#if !defined(CY_SYSLIB_H) +#define CY_SYSLIB_H + +#include +#include + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/** Get the lower 8 bits of a 16-bit value. */ +#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) +/** Get the upper 8 bits of a 16-bit value. */ +#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) + +/** Get the lower 16 bits of a 32-bit value. */ +#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) +/** Get the upper 16 bits of a 32-bit value. */ +#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) + +/** Swap the byte ordering of a 16-bit value */ +#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) + +/** Swap the byte ordering of a 32-bit value */ +#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ + (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) + +/** Swap the byte ordering of a 64-bit value */ +#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ + CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) + +/* MISRA rule 6.3 recommends using specific-length typedef for the basic + * numerical types of signed and unsigned variants of char, float, and double. + */ +typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ +typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ +typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ + + +/******************************************************************************* +* Macro Name: CY_GET_REG8(addr) +****************************************************************************//** +* +* Reads the 8-bit value from the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG8(addr, value) +****************************************************************************//** +* +* Writes an 8-bit value to the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG16(addr) +****************************************************************************//** +* +* Reads the 16-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG16(addr, value) +****************************************************************************//** +* +* Writes the 16-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG24(addr) +****************************************************************************//** +* +* Reads the 24-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) + + +/******************************************************************************* +* Macro Name: CY_SET_REG24(addr, value) +****************************************************************************//** +* +* Writes the 24-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG24(addr, value) do \ + { \ + (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ + (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ + (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ + } \ + while(0) + + +/******************************************************************************* +* Macro Name: CY_GET_REG32(addr) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG32(addr, value) +****************************************************************************//** +* +* Writes the 32-bit value to the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD32U +****************************************************************************//** +* +* The macro for setting a register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the register. +* +*******************************************************************************/ +#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) + + +/******************************************************************************* +* Macro Name: CY_REG32_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 32-bit register. +* +*******************************************************************************/ +#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD16U +****************************************************************************//** +* +* The macro for setting a 16-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 16-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ + ((uint16_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG16_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 16-bit register. +* +*******************************************************************************/ +#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD8U +****************************************************************************//** +* +* The macro for setting a 8-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 8-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ + ((uint8_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG8_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 8-bit register. +* +*******************************************************************************/ +#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _BOOL2FLD +****************************************************************************//** +* +* Returns a field mask if the value is not false. +* Returns 0, if the value is false. +* +*******************************************************************************/ +#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) + + +/******************************************************************************* +* Macro Name: _FLD2BOOL +****************************************************************************//** +* +* Returns true, if the value includes the field mask. +* Returns false, if the value doesn't include the field mask. +* +*******************************************************************************/ +#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUND +****************************************************************************//** +* +* Calculates a / b with rounding to the nearest integer, +* a and b must have the same sign. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUNDUP +****************************************************************************//** +* +* Calculates a / b with rounding up if remainder != 0, +* both a and b must be positive. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) + +typedef uint32_t cy_status; +/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ +typedef uint32_t cystatus; +typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ +typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ +typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ +typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ +typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ +typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ +typedef float float32; /**< Alias to float for backward compatibility */ +typedef double float64; /**< Alias to double for backward compatibility */ +typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ +typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; /**< Alias to char for backward compatibility */ +typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ +typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ +typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ + +/** The ARM 32-bit Return error / status code for backward compatibility. +* Do not use them in your code. +*/ +#define CY_RET_SUCCESS (0x00U) /* Successful */ +#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CY_RET_MEMORY (0x03U) /* A memory-related failure */ +#define CY_RET_LOCKED (0x04U) /* A resource lock failure */ +#define CY_RET_EMPTY (0x05U) /* No more objects available */ +#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CY_RET_FINISHED (0x08U) /* Operation is completed */ +#define CY_RET_CANCELED (0x09U) /* Operation is canceled */ +#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */ +#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */ + +/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. +* Do not use them in your code. +*/ +#define CYRET_SUCCESS (0x00U) /* Successful */ +#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CYRET_MEMORY (0x03U) /* A memory-related failure */ +#define CYRET_LOCKED (0x04U) /* A resource lock failure */ +#define CYRET_EMPTY (0x05U) /* No more objects available */ +#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08U) /* Operation is completed */ +#define CYRET_CANCELED (0x09U) /* Operation is canceled */ +#define CYRET_TIMEOUT (0x10U) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */ + +/** \} group_syslib_functions */ + +#endif /* CY_SYSLIB_H */ + +/** \} group_syslib */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_utils.h new file mode 100644 index 00000000000..db8c143f361 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cy_utils.h @@ -0,0 +1,81 @@ +/***************************************************************************//** +* \file cy_utils.h +* +* \brief +* Basic utility macros and functions. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_utils Utilities +* \ingroup group_abstraction +* \{ +* Basic utility macros and functions. +* +* \defgroup group_utils_macros Macros +*/ + +#pragma once + +#include "stdint.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_utils_macros +* \{ +*/ + +/** Simple macro to supress the unused parameter warning by casting to void. */ +#define CY_UNUSED_PARAMETER(x) ( (void)(x) ) + +/** Halt the processor in the debug state + * @return + */ +static inline uint32_t CY_HALT() +{ + __asm(" bkpt 1"); + return 0; +} + +#ifdef CY_ASSERT +#undef CY_ASSERT +#endif /* ifdef(CY_ASSERT) */ + +/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */ +#if defined(NDEBUG) || defined(CY_NO_ASSERT) + #define CY_ASSERT(x) CY_UNUSED_PARAMETER(x) +#else + #define CY_ASSERT(x) do { \ + if(!(x)) \ + { \ + CY_HALT(); \ + } \ + } while(0) +#endif /* defined(NDEBUG) */ + +/** \} group_utils_macros */ + +#ifdef __cplusplus +} +#endif + +/** \} group_utils */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cybsp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cybsp.h new file mode 100644 index 00000000000..06226f327bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cybsp.h @@ -0,0 +1,50 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cycfg.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cycfg.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cycfg.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal.h new file mode 100644 index 00000000000..e56be0e0132 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal.h @@ -0,0 +1,52 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "whd_config.h" +#include "cyhal_hw_types.h" +#include "cyhal_gpio.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +typedef enum +{ + CYBSP_WIFI_WL_REG_ON, + CYBSP_WIFI_32K_CLK, + CYBSP_LED1, + CYBSP_LED2, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3, + CYBSP_SDIO_OOB_IRQ, + CYBSP_WIFI_MAX, +} wwd_sdio_pin_t; + +void cyhal_system_delay_ms(uint32_t milliseconds); +cy_rslt_t sdio_enable_high_speed(void); + +#if defined(__cplusplus) +} +#endif + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_gpio.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_gpio.cpp new file mode 100644 index 00000000000..3b7d33d0fea --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_gpio.cpp @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 GPIOs on WHD driver + */ + +#include +#include "cyhal.h" +#include "cybsp.h" +#include "mbed.h" +#include "wiced_filesystem.h" + +extern pinconfig_t PinConfig[]; + +/******************************************************************************* +* Internal +*******************************************************************************/ +static mbed::InterruptIn *oob_irq; +static cyhal_gpio_event_t oob_event = CYHAL_GPIO_IRQ_FALL; +static cyhal_gpio_event_callback_t oob_handler; +static void *oob_handler_arg; + +/******************************************************************************* +* Internal Interrrupt Service Routine +*******************************************************************************/ +static void cb() +{ + oob_handler(oob_handler_arg, oob_event); +} + +/******************************************************************************* +* HAL Implementation +*******************************************************************************/ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + // Workaround to enable GPIOJ clock + if (pin == CYBSP_WIFI_WL_REG_ON) { + __HAL_RCC_GPIOB_CLK_ENABLE(); + // Ensure FS and BlockDevice are initialized on time if needed + wiced_filesystem_init(); + } + // Ignore the parameter and take the pin config directly from a static array defintions + HAL_GPIO_Init(PinConfig[pin].port, &PinConfig[pin].config); + if (direction == CYHAL_GPIO_DIR_OUTPUT) { + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (initVal) ? GPIO_PIN_SET : GPIO_PIN_RESET); + } + // Workaround to initialize sdio interface without cypress bsp init + if (pin == CYBSP_WIFI_WL_REG_ON) { + cyhal_sdio_t *sdio_p = cybsp_get_wifi_sdio_obj(); + ret = cyhal_sdio_init(sdio_p, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); + } + return ret; +} + +void cyhal_gpio_write(cyhal_gpio_t pin, bool value) +{ + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (value) ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t handler, void *handler_arg) +{ + if (handler && handler_arg && (oob_irq == NULL)) { + oob_irq = new mbed::InterruptIn(WL_HOST_WAKE); + oob_handler = handler; + oob_handler_arg = handler_arg; + } +} + +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable) +{ + oob_event = event; + if (enable) { + if (event == CYHAL_GPIO_IRQ_RISE) { + oob_irq->rise(cb); + } + if (event == CYHAL_GPIO_IRQ_FALL) { + oob_irq->fall(cb); + } + } else if (oob_irq != NULL) { + delete oob_irq; + } +} + +void cyhal_gpio_free(cyhal_gpio_t pin) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_hw_types.h new file mode 100644 index 00000000000..1f872abb373 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_hw_types.h @@ -0,0 +1,112 @@ +/***************************************************************************//** +* \file cyhal_hw_types_template.h +* +* \brief +* Provides a template for configuration resources used by the HAL. Items +* here need to be implemented for each HAL port. It is up to the environment +* being ported into what the actual types are. There are some suggestions below +* but these are not required. All that is required is that the type is defined; +* it does not matter to the HAL what type is actually chosen for the +* implementation +* All TODOs and references to 'PORT' need to be replaced by with meaningful +* values for the device being supported. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_hw_types PORT Hardware Types + * \ingroup group_hal_PORT + * \{ + * Struct definitions for configuration resources in the PORT. + * + * \defgroup group_hal_hw_types_data_structures Data Structures + */ + +#pragma once +#include +#include "stm32h7xx_hal.h" +#include "PinNames.h" + +/* + #include "TODO: Port specific header file" + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef CYHAL_ISR_PRIORITY_DEFAULT +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ +#define CYHAL_ISR_PRIORITY_DEFAULT (7) +#endif + +/** + * \addtogroup group_hal_hw_types_data_structures + * \{ + */ + +typedef int32_t cyhal_gpio_t; + +/** GPIO object */ +typedef struct +{ + GPIO_TypeDef *port; + GPIO_InitTypeDef config; +} pinconfig_t; + +/** Clock divider object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *div_type; +} cyhal_clock_divider_t; + +/** Clock object */ +typedef struct +{ + //For backwards compatibility with cyhal_clock_divider_t only. Do not use going forward. + int div_type; /*!< Deprecated */ + uint8_t div_num; /*!< Deprecated */ + //End BWC items + int block; + uint8_t channel; + bool reserved; +} cyhal_clock_t; + +/** SDIO object */ +typedef void* *cyhal_sdio_t; + +/** SPI object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *empty; +} cyhal_spi_t; + +#include "whd_config.h" +#include "whd_debug.h" + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_hw_types */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c new file mode 100644 index 00000000000..34aa5498e1a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c @@ -0,0 +1,483 @@ +/* + * Copyright 2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 SDIO on WHD driver + */ + +#include +#include +#include "whd_thread.h" +#include "bus_protocols/whd_bus_sdio_protocol.h" +#include "cyabs_rtos.h" +#include "cyhal_sdio.h" + +#define SDIO_RESPONSE_SHORT SDMMC_RESPONSE_SHORT +#define SDIO_WAIT_NO SDMMC_WAIT_NO +#define SDIO_CPSM_ENABLE SDMMC_CPSM_ENABLE +#define SDIO_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO_FLAG_CMDACT (SDMMC_STA_CPSMACT | SDMMC_STA_DPSMACT) +#define SDIO_TRANSFER_DIR_TO_SDIO SDMMC_TRANSFER_DIR_TO_SDMMC +#define SDIO_TRANSFER_DIR_TO_CARD SDMMC_TRANSFER_DIR_TO_CARD +#define SDIO_TRANSFER_MODE_BLOCK SDMMC_TRANSFER_MODE_BLOCK +#define SDIO_DPSM_ENABLE SDMMC_DPSM_ENABLE +#define SDIO_DPSM_DISABLE SDMMC_DPSM_DISABLE +#define SDIO_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN /* 1 << 11 */ +#define SDIO_DCTRL_DTMODE_1 SDMMC_DCTRL_DTMODE_1 /* 1<<3 */ +#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR +#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR +#define SDIO_STA_TXACT SDMMC_STA_CPSMACT +#define SDIO_STA_RXACT SDMMC_STA_DPSMACT +#define SDIO_STA_CMDREND SDMMC_STA_CMDREND +#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT +#define SDIO_CMD_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO SDMMC1 + +#define COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS (100000) +#define BUS_LEVEL_MAX_RETRIES 10 + +#define SDIO_CMD_5 5 +#define SDIO_CMD_53 53 + +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!b)?a:b + +extern pinconfig_t PinConfig[]; +extern SD_HandleTypeDef hsd; + +/* for debug prints only */ +//static int num = 0; + +static uint32_t dctrl; + +static whd_driver_t whd_handler; +static cyhal_sdio_irq_handler_t sdio_irq_handler; + +static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +static uint8_t *user_data; +static uint32_t user_data_size; +static uint8_t *dma_data_source; +static uint32_t dma_transfer_size; +static cyhal_transfer_t current_transfer_direction; + +static cy_semaphore_t sdio_transfer_finished_semaphore; +static volatile uint32_t sdio_transfer_failed = 0; +static volatile uint32_t irqstatus = 0; +static int current_command = 0; + +static cy_rslt_t sdio_enable_high_speed(void) +{ + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; + + SDMMC_Init(SDMMC1, sdio_init_structure); + return CY_RSLT_SUCCESS; +} + +static uint32_t find_optimal_block_size(uint32_t data_size) +{ + if (data_size > (uint32_t) 256) { + return 512; + } + if (data_size > (uint32_t) 128) { + return 256; + } + if (data_size > (uint32_t) 64) { + return 128; + } + if (data_size > (uint32_t) 32) { + return 64; + } + if (data_size > (uint32_t) 16) { + return 32; + } + if (data_size > (uint32_t) 8) { + return 16; + } + if (data_size > (uint32_t) 4) { + return 8; + } + if (data_size > (uint32_t) 2) { + return 4; + } + + return 4; +} + +static uint32_t sdio_get_blocksize(uint32_t blocksize) +{ + uint32_t n = 0; + blocksize >>= 1; + while (blocksize) { + n++; + blocksize >>= 1; + } + n <<= 4; + return n; +} + +static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t block_size, uint8_t *data, uint16_t data_size) +{ + /* Setup a single transfer using the temp buffer */ + user_data = data; + user_data_size = data_size; + dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); + + if (direction == CYHAL_WRITE) { + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + memcpy(temp_dma_buffer, data, data_size); + dma_data_source = temp_dma_buffer; + } else { + dma_data_source = (uint8_t *)temp_dma_buffer; + //VIKR + //memset(dma_data_source,0x12,data_size); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Cache-Invalidate the output from DMA */ + SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); +#endif + } + + SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; + SDIO->DLEN = dma_transfer_size; + dctrl = sdio_get_blocksize(block_size) | ((direction == CYHAL_READ) ? SDIO_TRANSFER_DIR_TO_SDIO : SDIO_TRANSFER_DIR_TO_CARD) | SDIO_TRANSFER_MODE_BLOCK | SDIO_DPSM_DISABLE | SDIO_DCTRL_SDIOEN; + SDIO->DCTRL = dctrl; + + SDMMC1->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + SDMMC1->IDMABASE0 = (uint32_t) dma_data_source; +} + +static void sdio_enable_bus_irq(void) +{ + SDMMC1->MASK = SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_CMDREND | SDMMC_IT_CMDSENT; +} + +void SDMMC1_IRQHandler(void) +{ + uint32_t intstatus = SDIO->STA; + + irqstatus = intstatus; + //VIKR | SDIO_STA_STBITERR ) + if ((intstatus & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0) { + WPRINT_WHD_DEBUG(("sdio error flagged\n")); + sdio_transfer_failed = intstatus; + SDIO->ICR = (uint32_t) 0xffffffff; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } else { + if ((intstatus & (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT)) != 0) { + if ((SDMMC1->RESP1 & 0x800) != 0) { + sdio_transfer_failed = irqstatus; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + + /* Clear all command/response interrupts */ + SDMMC1->ICR = (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT); + } + + /* Check whether the external interrupt was triggered */ + if (intstatus & SDMMC_STA_SDIOIT) { + /* Clear the interrupt */ + SDMMC1->ICR = SDMMC_STA_SDIOIT; + /* Inform WICED WWD thread */ + sdio_irq_handler(whd_handler, CYHAL_SDIO_CARD_INTERRUPT); + } + + if (intstatus & SDMMC_STA_DATAEND) { + SDMMC1->ICR = SDMMC_STA_DATAEND; + SDMMC1->DLEN = 0; + SDMMC1->DCTRL = SDMMC_DCTRL_SDIOEN; + SDMMC1->IDMACTRL = SDMMC_DISABLE_IDMA; + SDMMC1->CMD = 0; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + } +} + +//void sdio_dma_irq(void) +//{ +// /* Clear interrupt */ +// DMA2->LIFCR = (uint32_t)(0x3F << 22); +// cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); +//} + +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + HAL_GPIO_Init(PinConfig[cmd].port, &PinConfig[cmd].config); + HAL_GPIO_Init(PinConfig[clk].port, &PinConfig[clk].config); + HAL_GPIO_Init(PinConfig[data0].port, &PinConfig[data0].config); + HAL_GPIO_Init(PinConfig[data1].port, &PinConfig[data1].config); + HAL_GPIO_Init(PinConfig[data2].port, &PinConfig[data2].config); + HAL_GPIO_Init(PinConfig[data3].port, &PinConfig[data3].config); + + /* Reset SDIO Block */ + SDMMC_PowerState_OFF(SDMMC1); + __HAL_RCC_SDMMC1_FORCE_RESET(); + __HAL_RCC_SDMMC1_RELEASE_RESET(); + + /* Enable the SDIO Clock */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Disable DCache for STM32H7 family */ + SCB_CleanDCache(); + SCB_DisableDCache(); +#endif + + WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); + + // Lower speed configuration + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_INIT_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_1B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + ret = SDMMC_Init(SDMMC1, sdio_init_structure); + ret |= SDMMC_PowerState_ON(SDMMC1); + ret |= SDMMC_SetSDMMCReadWaitMode(SDMMC1, SDMMC_READ_WAIT_MODE_CLK); + if (ret) { + return ret; + } + + /* Clear all SDIO interrupts */ + SDMMC1->ICR = (uint32_t) 0xffffffff; + + /* Turn on SDIO IRQ */ + /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */ + /* otherwise FreeRTOS will not be able to mask the interrupt */ + /* keep in mind that ARMCM7 interrupt priority logic is inverted, the highest value */ + /* is the lowest priority */ + HAL_NVIC_EnableIRQ((IRQn_Type) SDMMC1_IRQn); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0); + + WPRINT_WHD_DEBUG(("after enable sdio: %p\n", sdio_transfer_finished_semaphore)); + + if (cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0) != WHD_SUCCESS) { + cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); + return -1; + } + + WPRINT_WHD_DEBUG(("cy_rtos_init_semaphore: %p\n", sdio_transfer_finished_semaphore)); + + return ret; +} + +void cyhal_sdio_free(cyhal_sdio_t *obj) +{ + //TODO +} + +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) +{ + return sdio_enable_high_speed(); +} + +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t *response) +{ + uint32_t loop_count = 0; + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t temp_sta; + + if (response != NULL) { + *response = 0; + } + current_command = 0; + +restart: + SDIO->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + result = -1; + goto exit; + } + + /* Send the command */ + SDIO->ARG = argument; + SDIO->CMD = (uint32_t)(command | SDIO_RESPONSE_SHORT | SDIO_WAIT_NO | SDIO_CPSM_ENABLE); + loop_count = (uint32_t) COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS; + do { + temp_sta = SDIO->STA; + loop_count--; + if (loop_count == 0 /*|| ((response != NULL) && ((temp_sta & SDIO_ERROR_MASK) != 0))*/) { + WPRINT_WHD_DEBUG(("Restart single access loop count %ld stat %lx\n", loop_count, temp_sta)); + HAL_Delay(10U); + goto restart; + } + } while ((temp_sta & SDIO_FLAG_CMDACT) != 0); + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + if (result) { + WPRINT_WHD_ERROR(("SDIO->POWER %lx \n", SDIO->POWER)); + WPRINT_WHD_ERROR(("SDIO->CLKCR %lx \n", SDIO->CLKCR)); + WPRINT_WHD_ERROR(("result %lx \n", result)); + WPRINT_WHD_ERROR(("cyhal_sdio_send_cmd %s\n", (result == 0) ? "Passed" : "Failed")); + while (1); + } + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 0x%x arg 0x%x resp 0x%x\n",num++,(direction!=CYHAL_READ)?"Write":"Read",command,argument,(response)?*response:0)); + return result; +} + +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length, uint32_t *response) +{ + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t block_size = 64; + sdio_cmd_argument_t arg; + uint32_t cmd; + current_command = SDIO_CMD_53; + current_transfer_direction = direction; + arg.value = argument; + + sdio_enable_bus_irq(); + if (response != NULL) { + *response = 0; + } + +restart: + sdio_transfer_failed = 0; + SDMMC1->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + WPRINT_WHD_ERROR(("Too much attempt\n")); + result = -1; + goto exit; + } + + /* Dodgy STM32 hack to set the CMD53 byte mode size to be the same as the block size */ + if (arg.cmd53.block_mode == 0) { + block_size = find_optimal_block_size(arg.cmd53.count); + if (block_size < SDIO_512B_BLOCK) { + arg.cmd53.count = block_size; + } else { + arg.cmd53.count = 0; + } + argument = arg.value; + } + + SDMMC1->CMD |= SDMMC_CMD_CMDTRANS; + + /* Prepare the SDIO for a data transfer */ + sdio_prepare_data_transfer(direction, block_size, (uint8_t *) data, (uint32_t) length); + + /* Send the command */ + //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); + SDMMC1->ARG = argument; + cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); + SDMMC1->CMD = cmd; + + /* Wait for the whole transfer to complete */ + //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); + result = cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 50, WHD_FALSE); + + if (result != CY_RSLT_SUCCESS) { + WPRINT_WHD_ERROR(("failed getting semaphore\n")); + goto exit; + } + if (sdio_transfer_failed) { + WPRINT_WHD_DEBUG(("try again sdio_transfer_failed %"PRIu32" irq %"PRIu32"\n", sdio_transfer_failed, irqstatus)); + goto restart; + } + /* Check if there were any SDIO errors */ + if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); + goto restart; + } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); + goto restart; + } + + if (direction == CYHAL_READ) { + memcpy(user_data, dma_data_source, (size_t) user_data_size); + } + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 53 argument %lx datasize %d blocknumber 0x%x cmdis %lx %lu dctrl = %x\n", num++, (direction != CYHAL_READ) ? "Write" : "Read", argument, length, arg.cmd53.count, cmd, cmd, dctrl)); + + return result; +} + +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) +{ + return false; +} + +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +{ + whd_handler = (whd_driver_t)handler_arg; + sdio_irq_handler = handler; +} + +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intr_priority, bool enable) +{ + //TODO +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_spi.c new file mode 100644 index 00000000000..162c7a6801f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_spi.c @@ -0,0 +1,29 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides stubs for the WHD driver needed by ARMClang + */ + +#include +#include +#include "cyhal_spi.h" + +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_system.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_system.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_system.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_bd.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_bd.h new file mode 100644 index 00000000000..578b2d9e4eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_bd.h @@ -0,0 +1,49 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" +#include "BlockDevice.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * Mount the physical device + * + * This assumes that the device is ready to read/write immediately. + * + * @param[in] device - physical media to init + * @param[out] fs_handle_out - Receives the filesystem handle. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount(mbed::BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp new file mode 100644 index 00000000000..078f8c82b3d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -0,0 +1,220 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#include +#include +#include +#include +#include "sockets.h" +#include "resources.h" +#include "wiced_filesystem.h" +#include "wiced_bd.h" +#include "QSPIFBlockDevice.h" +#include "MBRBlockDevice.h" +#include "FATFileSystem.h" + +#define WIFI_DEFAULT_FIRMWARE_PATH "/wlan/4343WA1.BIN" +#define WIFI_DEFAULT_MOUNT_NAME "wlan" +#define WIFI_DEFAULT_PARTITION 1 +#define WIFI_DEFAULT_FS 0 + +BlockDevice *qspi_bd = NULL; +MBRBlockDevice *mbr_bd = NULL; +FATFileSystem *wifi_fs = NULL; + +wiced_filesystem_t resource_fs_handle; + +MBED_WEAK BlockDevice *BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PD_12, PE_2, PF_6, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} + +MBED_WEAK void wiced_filesystem_mount_error(void) +{ + WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK void wiced_filesystem_firmware_error(void) +{ + WPRINT_WHD_ERROR(("Please run the \"WiFiFirmwareUpdater\" sketch once to install the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int mount_err) +{ + DIR *dir; + struct dirent *ent; + std::string dir_name(mounted_name); + if (mount_err) { + wiced_filesystem_mount_error(); + } else { + if ((dir = opendir(mounted_name)) != NULL) { + // print all the files and directories within directory + while ((ent = readdir(dir)) != NULL) { + std::string fullname = "/" + dir_name + "/" + std::string(ent->d_name); + if (fullname == WIFI_DEFAULT_FIRMWARE_PATH) { + closedir(dir); + return WICED_SUCCESS; + } + } + closedir(dir); + } + wiced_filesystem_firmware_error(); + } + return WICED_ERROR; +} + +static wiced_result_t whd_default_firmware_restore(void) +{ +#if MBED_CONF_APP_WIFI_FIRMWARE_RESTORE + size_t ret; + FILE *fp; + + //This should only happen the firs time or if the partition table has been overwritten i.e QSPI tests + WPRINT_WHD_DEBUG(("MBRBlockDevice init failed, repatitioning\n\r")); + if (mbr_bd->partition(qspi_bd, 1, 0x0B, 0, 1024 * 1024) != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice repatitioning OK, reinit\n\r")); + + if (mbr_bd->init() != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice init OK\n\r")); + + wifi_fs = new FATFileSystem(WIFI_DEFAULT_MOUNT_NAME); + + if (wifi_fs->reformat(mbr_bd) != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("FATFileSystem reformat and mount OK\n\r")); + + fp = fopen(WIFI_DEFAULT_FIRMWARE_PATH, "wb"); + if (fp == NULL) { + return WICED_ERROR; + } + ret = fwrite(wifi_firmware_image_data, wifi_firmware_image.size, 1, fp); + if (ret != wifi_firmware_image.size) { + return WICED_ERROR; + } + fclose(fp); + + if (mbr_bd->sync() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Sync BlockDevice OK\n\r")); + + if (wifi_fs->unmount() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Unmount FS\n\r")); + wifi_fs = NULL; +#endif + + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_init(void) +{ + if (mbr_bd == NULL && wifi_fs == NULL) { + WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); + qspi_bd = mbed::BlockDevice::get_default_instance(); + + if (qspi_bd->init() == BD_ERROR_OK) { + mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); + if (mbr_bd->init() == BD_ERROR_OK) { + return WICED_SUCCESS; + } else { + return whd_default_firmware_restore(); + } + } + return WICED_ERROR; + } else { + WPRINT_WHD_DEBUG(("FileSystem initialized with user settings\n\r")); + return WICED_SUCCESS; + } +} + +wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) +{ + wifi_fs = new FATFileSystem(mounted_name); + + int err = wifi_fs->mount(device); + whd_firmware_check_hook(mounted_name, err); + if (!err) { + //fs_handle_out = wifi_fs + return WICED_SUCCESS; + } + return WICED_ERROR; +} + +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) +{ + /* This is called by mbed test system */ + //if (mbr_bd == NULL && wifi_fs == NULL) { + // wiced_filesystem_init(); + //} + //This can be called from user sketch to provide custom block device and mount point before WiFi.beginAP or WiFi.begin + if (wifi_fs == NULL) { + wiced_filesystem_mount(mbr_bd, WIFI_DEFAULT_FS, fs_handle, WIFI_DEFAULT_MOUNT_NAME); + } + + if (wifi_fs == NULL) { + return WICED_ERROR; + } + + *file_handle_out = open(filename, mode); + if (*file_handle_out == -1) { + return WICED_ERROR; + } + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + lseek(*file_handle, offset, whence); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + *returned_bytes_count = read(*file_handle, data, bytes_to_read); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + close(*file_handle); + return WICED_SUCCESS; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h new file mode 100644 index 00000000000..a65aa3c1489 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h @@ -0,0 +1,139 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************** + * Enumerations + ******************************************************/ + +typedef enum { + WICED_FILESYSTEM_OPEN_FOR_READ, /** Specifies read access to the object. Data can be read from the file - equivalent to "r" or "rb" */ + WICED_FILESYSTEM_OPEN_FOR_WRITE, /** Specifies read/write access to the object. Data can be written to the file - equivalent to "r+" or "rb+" or "r+b" */ + WICED_FILESYSTEM_OPEN_WRITE_CREATE, /** Opens for read/write access, creates it if it doesn't exist */ + WICED_FILESYSTEM_OPEN_ZERO_LENGTH, /** Opens for read/write access, Truncates file to zero length if it exists, or creates it if it doesn't - equivalent to "w+", "wb+" or "w+b" */ + WICED_FILESYSTEM_OPEN_APPEND, /** Opens for read/write access, places the current location at the end of the file ready for appending - equivalent to "a", "ab" */ + WICED_FILESYSTEM_OPEN_APPEND_CREATE, /** Opens for read/write access, creates it if it doesn't exist, and places the current location at the end of the file ready for appending - equivalent to "a+", "ab+" or "a+b" */ +} wiced_filesystem_open_mode_t; + +typedef enum { + WICED_FILESYSTEM_SEEK_SET = SEEK_SET, /* Offset from start of file */ + WICED_FILESYSTEM_SEEK_CUR = SEEK_CUR, /* Offset from current position in file */ + WICED_FILESYSTEM_SEEK_END = SEEK_END, /* Offset from end of file */ +} wiced_filesystem_seek_type_t; + +typedef enum { + WICED_SUCCESS = 0, + WICED_ERROR = 1 +} wiced_result_t; + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * File-system Handle Structure + */ +typedef int wiced_filesystem_t; + +/** + * File Handle Structure + * + */ +typedef int wiced_file_t; + +/** + * File-system type Handle Structure + */ +typedef int wiced_filesystem_handle_type_t; + +/** + * Initialise the BlockDevice and filesystem module + * + * Initialises the BlockDevice and filesystem module before mounting a physical device. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_init(void); + +/** + * Open a file for reading or writing + * + * @param[in] fs_handle - The filesystem handle to use - obtained from wiced_filesystem_mount + * @param[out] file_handle_out - a pointer to a wiced_file_t structure which will receive the + * file handle after it is opened + * @param[in] filename - The filename of the file to open + * @param[in] mode - Specifies read or write access + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode); + +/** + * Seek to a location within a file + * + * This is similar to the fseek() in ISO C. + * + * @param[in] file_handle - The file handle on which to perform the seek. + * Must have been previously opened with wiced_filesystem_fopen. + * @param[in] offset - The offset in bytes + * @param[in] whence - WICED_FILESYSTEM_SEEK_SET = Offset from start of file + * WICED_FILESYSTEM_SEEK_CUR = Offset from current position in file + * WICED_FILESYSTEM_SEEK_END = Offset from end of file + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence); + +/** + * Reads data from a file into a memory buffer + * + * @param[in] file_handle - the file handle to read from + * @param[out] data - A pointer to the memory buffer that will + * receive the data that is read + * @param[in] bytes_to_read - the number of bytes to read + * @param[out] returned_item_count - the number of items successfully read. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count); + +/** + * Close a file + * + * This is similar to the fclose() in ISO C. + * + * @param[in] file_handle - the file handle to close + * + * @return WICED_SUCCESS = success + */ +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt new file mode 100644 index 00000000000..cbb51f9c99e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, July 2019 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named �DEPENDENCIES� and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c new file mode 100644 index 00000000000..ddaf0f7188f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c @@ -0,0 +1,25493 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_image_data[421098] = { + 0, 0, 0, 0, 237, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 0, + 25, 33, 0, 0, 25, 33, 0, 0, 0, 72, 0, 71, 237, 33, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 68, 66, 80, 80, 128, 109, 4, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 149, 212, 1, 0, 223, 145, 2, 0, 59, 146, 2, 0, 73, 140, + 2, 0, 193, 137, 2, 0, 13, 137, 2, 0, 85, 138, 2, 0, 203, 135, 2, 0, + 167, 136, 2, 0, 181, 146, 2, 0, 189, 146, 2, 0, 141, 135, 2, 0, 167, + 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98, 116, 99, 120, 104, 121, 98, 114, 105, + 100, 104, 119, 45, 110, 111, 99, 108, 109, 105, 110, 99, 45, 99, 108, + 109, 95, 109, 105, 110, 45, 102, 98, 116, 45, 109, 102, 112, 45, 115, + 97, 101, 45, 116, 107, 111, 32, 86, 101, 114, 115, 105, 111, 110, 58, + 32, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, 52, + 51, 48, 51, 32, 67, 89, 41, 32, 67, 82, 67, 58, 32, 101, 54, 98, 55, + 57, 50, 97, 54, 32, 68, 97, 116, 101, 58, 32, 84, 104, 117, 32, 50, + 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, 52, 51, 58, 53, + 51, 32, 80, 83, 84, 32, 85, 99, 111, 100, 101, 32, 86, 101, 114, 58, + 32, 49, 48, 52, 51, 46, 50, 49, 51, 55, 32, 70, 87, 73, 68, 32, 48, + 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, + 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 +}; +resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c new file mode 100644 index 00000000000..616bdedf2e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_clm_blob_image_data[7222] = { + 66, 76, 79, 66, 60, 0, 0, 0, 132, 159, 16, 216, 1, 0, 0, 0, 2, 0, 0, + 0, 0, 0, 0, 0, 60, 0, 0, 0, 246, 27, 0, 0, 183, 10, 32, 40, 0, 0, 0, + 0, 0, 0, 0, 0, 50, 28, 0, 0, 4, 0, 0, 0, 42, 255, 237, 159, 0, 0, 0, + 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, 57, 46, 49, 48, + 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 46, 50, 57, 46, + 52, 0, 0, 0, 0, 0, 0, 0, 0, 184, 10, 0, 0, 67, 108, 109, 73, 109, 112, + 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, 109, 45, 48, 46, 48, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 49, 0, 81, 50, 0, 3, 3, 3, 9, 3, 11, + 4, 4, 4, 7, 4, 8, 4, 10, 4, 11, 5, 7, 8, 8, 9, 9, 9, 11, 11, 11, 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84, 20, 1, 112, 38, 1, 4, 0, 255, 1, 23, 18, 2, 1, 84, 18, 1, 20, 1, + 255, 2, 23, 20, 30, 49, 2, 2, 84, 20, 1, 84, 49, 1, 21, 1, 255, 3, 23, + 20, 30, 37, 30, 46, 2, 2, 84, 21, 1, 84, 46, 1, 26, 1, 255, 3, 23, 20, + 24, 39, 30, 49, 2, 1, 84, 25, 1, 26, 1, 255, 3, 23, 20, 24, 39, 30, + 49, 2, 1, 84, 25, 1, 17, 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 20, 1, + 112, 40, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 30, + 49, 0, 1, 78, 49, 1, 14, 0, 255, 2, 27, 19, 27, 49, 2, 2, 84, 19, 1, + 84, 49, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 20, + 49, 2, 1, 76, 49, 1, 33, 0, 255, 1, 20, 48, 2, 1, 76, 48, 1, 31, 2, + 255, 2, 17, 33, 30, 49, 0, 2, 68, 33, 1, 68, 49, 1, 30, 2, 255, 3, 17, + 33, 24, 38, 30, 49, 0, 3, 56, 33, 1, 68, 38, 1, 68, 49, 1, 28, 2, 255, + 3, 17, 28, 24, 38, 30, 49, 0, 3, 56, 28, 1, 58, 38, 1, 62, 49, 1, 33, + 0, 255, 1, 27, 48, 2, 1, 84, 48, 1, 0, 0, 3, 0, 0, 0, 120, 11, 0, 0, + 16, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1, 18, + 1, 255, 1, 52, 1, 14, 1, 15, 3, 28, 39, 49, 2, 19, 49, 166, 169, 0, + 0 +}; +const resource_hnd_t wifi_firmware_clm_blob = { RESOURCE_IN_MEMORY, 7222, {.mem = { (const char *) wifi_firmware_clm_blob_image_data }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h new file mode 100644 index 00000000000..01bad9226f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Automatically generated file - this comment ensures resources.h file creation */ +/* Auto-generated header file. Do not edit */ +#ifndef INCLUDED_RESOURCES_H_ +#define INCLUDED_RESOURCES_H_ +#include "wiced_resource.h" +#include "wiced_filesystem.h" + +extern wiced_filesystem_t resource_fs_handle; + +extern const resource_hnd_t wifi_firmware_image; +extern const unsigned char wifi_firmware_image_data[421098]; +extern const resource_hnd_t wifi_firmware_clm_blob; +extern const unsigned char wifi_firmware_clm_blob_image_data[7222]; + +#endif /* ifndef INCLUDED_RESOURCES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h new file mode 100644 index 00000000000..3f2279c2be9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * NVRAM file for CY8CKIT-062-WiFi-BT (PSoC6 WiFi-BT Pioneer Kit) using + * Murata's Type 1DX module - Copied from bcm94343wwcd1.txt on 08/04/2019 + * # 2.4 GHz, 20 MHz BW mode; No Antenna Diversity + */ + +#ifndef INCLUDED_NVRAM_IMAGE_H_ +#define INCLUDED_NVRAM_IMAGE_H_ + +#include +#include +#include "generated_mac_address.txt" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Character array of NVRAM image + * + * Generated from cyw94343cy8ckit-062-wifi-bt.txt + */ + +static const char wifi_nvram_image[] = + "manfid=0x2d0" "\x00" + "prodid=0x0726" "\x00" + "vendid=0x14e4" "\x00" + "devid=0x43e2" "\x00" + "boardtype=0x0726" "\x00" + "boardrev=0x1202" "\x00" + "boardnum=22" "\x00" + NVRAM_GENERATED_MAC_ADDRESS "\x00" + "sromrev=11" "\x00" + "boardflags=0x00404201" "\x00" + "boardflags3=0x04000000" "\x00" + "xtalfreq=37400" "\x00" + "nocrc=1" "\x00" + "ag0=0" "\x00" + "aa2g=1" "\x00" + "ccode=ALL" "\x00" + "extpagain2g=0" "\x00" + "pa2ga0=-145,6667,-751" "\x00" + "AvVmid_c0=0x0,0xc8" "\x00" + "cckpwroffset0=2" "\x00" + "maxp2ga0=74" "\x00" + "cckbw202gpo=0" "\x00" + "legofdmbw202gpo=0x88888888" "\x00" + "mcsbw202gpo=0xaaaaaaaa" "\x00" + "propbw202gpo=0xdd" "\x00" + "ofdmdigfilttype=18" "\x00" + "ofdmdigfilttypebe=18" "\x00" + "papdmode=1" "\x00" + "papdvalidtest=1" "\x00" + "pacalidx2g=48" "\x00" + "papdepsoffset=-22" "\x00" + "papdendidx=58" "\x00" + "il0"NVRAM_GENERATED_MAC_ADDRESS "\x00" + "wl0id=0x431b" "\x00" + "muxenab=0x10" "\x00" + "\x00\x00"; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ + +#error Wi-Fi NVRAM image included twice + +#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/whd_config.h new file mode 100644 index 00000000000..4b320b9deeb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/whd_config.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides configuration for WHD driver on Arduino Portenta H7 + */ + +#ifndef __WHD_CONFIG__ +#define __WHD_CONFIG__ + +#include "whd_types.h" +#include "stm32h7xx_hal.h" +#include + +/* disable WPRINT_MACRO */ +#define WHD_PRINT_DISABLE + +/* please define your configuration , either SDIO or SPI */ +#define CY_WHD_CONFIG_USE_SDIO +//#define CY_WHD_CONFIG_USE_SPI + +/* select resource implementation */ +#define USES_RESOURCE_GENERIC_FILESYSTEM + +/* if not defined default value is 2 */ +#define CY_WIFI_OOB_INTR_PRIORITY 0 + +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_FALL +#define CYBSP_WIFI_HOST_WAKE CYBSP_SDIO_OOB_IRQ + +#define BSP_LED1 {GPIOK,{.Pin= GPIO_PIN_5 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED2 {GPIOK,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED3 {GPIOK,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} + +/* power pin */ +#define WIFI_WL_REG_ON {GPIOB,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +//#define WIFI_32K_CLK {GPIOA,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW , .Alternate = GPIO_AF0_MCO}} + +#define WIFI_SDIO_CMD {GPIOD,{.Pin= GPIO_PIN_2 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_CLK {GPIOC,{.Pin= GPIO_PIN_12 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D0 {GPIOC,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D1 {GPIOC,{.Pin= GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D2 {GPIOC,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D3 {GPIOC,{.Pin= GPIO_PIN_11 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_OOB_IRQ {GPIOI,{.Pin= GPIO_PIN_8 , .Mode = GPIO_MODE_IT_FALLING , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH}} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PeripheralPins.c new file mode 100644 index 00000000000..3b1cf1075bf --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PeripheralPins.c @@ -0,0 +1,570 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NC, 0} +}; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h new file mode 100644 index 00000000000..e5463fe093a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h @@ -0,0 +1,445 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +/* MBED TARGET LIST: GIGA */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0C = PA_0 | DUAL_PAD, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | DUAL_PAD, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + WL_REG_ON = PB_10, + WL_HOST_WAKE = PI_8, + WL_SDIO_0 = PC_8, + WL_SDIO_1 = PC_9, + WL_SDIO_2 = PC_10, + WL_SDIO_3 = PC_11, + WL_SDIO_CMD = PD_2, + WL_SDIO_CLK = PC_12, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PB_7, +#endif + + //Led mappings + LED_RED = PI_12, //Red + LED_GREEN = PJ_13, //Green + LED_BLUE = PE_3, //Blue + + CYBSP_BT_UART_RX = PA_8, + CYBSP_BT_UART_TX = PF_7, + CYBSP_BT_UART_RTS = PF_8, + CYBSP_BT_UART_CTS = PF_9, + + CYBSP_BT_POWER = PA_10, + CYBSP_BT_HOST_WAKE = PG_3, + CYBSP_BT_DEVICE_WAKE = PH_7, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PD_11, + QSPI_FLASH1_IO1 = PD_12, + QSPI_FLASH1_IO2 = PE_2, + QSPI_FLASH1_IO3 = PF_6, + QSPI_FLASH1_SCK = PF_10, + QSPI_FLASH1_CSN = PG_6, + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_CRS_DV = PA_7, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RX_CLK = PA_1, + ETH_TXD0 = PG_13, + ETH_TXD1 = PG_12, + ETH_TX_EN = PG_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_TRGIO = PC_7, + SYS_WKUP0 = PA_0, + SYS_WKUP1 = PA_2, + SYS_WKUP2 = PC_13, + SYS_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define BUTTON1 PC_13 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp new file mode 100644 index 00000000000..a47a758e1dd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp @@ -0,0 +1,52 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +/****************************************************************************** + INCLUDE + ******************************************************************************/ + +#include "mbed.h" +#include "giga_power.h" + +/****************************************************************************** + PUBLIC MEMBER FUNCTIONS + ******************************************************************************/ +void enableEthPowerSupply(void) +{ + /* Ensure ETH power supply */ + mbed::I2C i2c(PB_7, PB_6); + + char data[2]; + + // LDO3 to 1.2V + data[0] = 0x52; + data[1] = 0x9; + i2c.write(8 << 1, data, sizeof(data)); + data[0] = 0x53; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW2 to 3.3V (SW2_VOLT) + data[0] = 0x3B; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW1 to 3.0V (SW1_VOLT) + data[0] = 0x35; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.h new file mode 100644 index 00000000000..8632d6f28c4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.h @@ -0,0 +1,31 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +#ifndef GIGA_POWER +#define GIGA_POWER + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern void enableEthPowerSupply(void); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c new file mode 100644 index 00000000000..21aa4979b99 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c @@ -0,0 +1,237 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 480 + * AHBCLK (MHz) | 240 + * APB1CLK (MHz) | 120 + * APB2CLK (MHz) | 120 + * APB3CLK (MHz) | 120 + * APB4CLK (MHz) | 120 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#if HSE_VALUE==16000000 + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 120; +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 16; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + __HAL_RCC_CSI_ENABLE() ; + + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // 8 MHz + RCC_OscInitStruct.PLL.PLLN = 120; // 960 MHz + RCC_OscInitStruct.PLL.PLLP = 2; // 480 MHz + RCC_OscInitStruct.PLL.PLLQ = 16; // PLL1Q used for FDCAN = 10 MHz + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + +#if DEVICE_USBDEVICE + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif + + __HAL_RCC_CSI_ENABLE() ; + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if defined (CORE_CM4) +void HSEM2_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif + +#if defined (CORE_CM7) +void HSEM1_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c index b2e1661388d..bb084a860a0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c @@ -106,6 +106,9 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) #if HSE_VALUE==25000000 RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz +#elif HSE_VALUE==16000000 + RCC_OscInitStruct.PLL.PLLM = 8; // 5 MHz + RCC_OscInitStruct.PLL.PLLN = 120; // 960 MHz #else #error Unsupported externall clock value, check HSE_VALUE define #endif diff --git a/targets/targets.json b/targets/targets.json index ac53c070b2a..dac2c94ddc2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3588,6 +3588,58 @@ "CORE_CM7" ] }, + "GIGA": { + "inherits": ["MCU_STM32H747xI_CM7"], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "16000000", + "macro_name": "HSE_VALUE" + }, + "lse_bypass": { + "help": "1 to use an oscillator (not a crystal) on 32k LSE", + "value": "0" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_FS" + } + }, + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY", + "clock_source": "USE_PLL_HSE_XTAL | USE_PLL_HSI", + "lse_available": 1, + "lpticker_delay_ticks": 0, + "network-default-interface-type": "WIFI", + "i2c_timing_value_algo": true, + "lpuart_clock_source": "USE_LPUART_CLK_HSI" + }, + "components_add": [ + "QSPIF", + "WHD", + "4343W_FS", + "CYW43XXX" + ], + "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", + "CM4_BOOT_BY_APPLICATION", + "QSPI_NO_SAMPLE_SHIFT", + "CYW43XXX_UNBUFFERED_UART", + "BT_UART_NO_3M_SUPPORT" + ], + "device_has_add": [ + "USBDEVICE", + "QSPI" + ], + "extra_labels_add": [ + "CORDIO" + ], + "features": [ + "BLE" + ], + "device_name": "STM32H747XIHx" + }, "NICLA_VISION": { "inherits": ["MCU_STM32H747xI_CM7"], "config": { From d265d18399f454a1c165bc6a15e73288d6d1ecd9 Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 22 Nov 2022 13:31:48 +0100 Subject: [PATCH 199/227] Giga: WHD: add function to mount wlan firmware fs from WiFi library --- .../TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp | 5 +++++ .../TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp index 078f8c82b3d..5973be673a3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -157,6 +157,11 @@ wiced_result_t wiced_filesystem_init(void) } } +wiced_result_t wiced_filesystem_mount_default(void) +{ + return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); +} + wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) { wifi_fs = new FATFileSystem(mounted_name); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h index a65aa3c1489..77d49d18202 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/wiced_filesystem.h @@ -81,6 +81,15 @@ typedef int wiced_filesystem_handle_type_t; */ wiced_result_t wiced_filesystem_init(void); +/** + * Mount the physical device using default parameters + * + * This assumes that the device is ready to read/write immediately. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount_default(void); + /** * Open a file for reading or writing * From 4ae9b1581076af6543d2824abcf8141f31b3482e Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 15 Nov 2022 12:16:43 +0100 Subject: [PATCH 200/227] MCUboot: Giga: reserve space for keys and identification string --- .../TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld index e026a61d4a3..61aebc3ce5a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI_CM7.ld @@ -46,7 +46,7 @@ MEMORY } -#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA) || defined(TARGET_GIGA)) _ConfigStart = 0x0802F000; _IdentificationStart = 0x080002F0; _EncryptKeyStart = 0x08000300; @@ -88,7 +88,7 @@ SECTIONS .text : { KEEP(*(.isr_vector)) -#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) +#if defined(MCUBOOT_BOOTLOADER_BUILD) && ( defined(TARGET_PORTENTA_H7_M7) || defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA) || defined(TARGET_GIGA)) . = ABSOLUTE(0x080002F0); KEEP(*(.bootloader_identification)) KEEP(*(.signing_key)) @@ -131,7 +131,7 @@ SECTIONS *lib*.o(.rodata*) -#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && ( defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA)) +#if (defined(MCUBOOT_BOOTLOADER_BUILD) || defined(BOOTLOADER_BUILD)) && ( defined(TARGET_NICLA_VISION) || defined(TARGET_OPTA) || defined(TARGET_GIGA)) . = ABSOLUTE(0x0801F000); KEEP(*(.bootloader_version)) #endif From b5881034882289d9221d628a748dfea73aa6cc7f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 17 Feb 2023 16:40:01 +0100 Subject: [PATCH 201/227] whd: portentah7: fix dcache maintenance --- .../COMPONENT_WHD/port/cyhal_sdio.c | 55 +++++++++++++------ 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c index 34aa5498e1a..3ddfd858484 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c @@ -63,6 +63,27 @@ #define LINK_MTU 1024 #define MAX(a,b) (a>b)?a:b +/* D-cache maintenance for DMA buffers */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + #define _CYHAL_DCACHE_MAINTENANCE + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) +#else + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) +#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + +/* Macro to ALIGN */ +#if defined (__ARMCC_VERSION) /* ARM Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __align(x) buf +#elif defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf +#endif + +/* Macro to get variable aligned for cache maintenance purpose */ +#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) + + extern pinconfig_t PinConfig[]; extern SD_HandleTypeDef hsd; @@ -74,7 +95,7 @@ static uint32_t dctrl; static whd_driver_t whd_handler; static cyhal_sdio_irq_handler_t sdio_irq_handler; -static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); static uint8_t *user_data; static uint32_t user_data_size; static uint8_t *dma_data_source; @@ -150,22 +171,24 @@ static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t bloc dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); if (direction == CYHAL_WRITE) { - -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif memcpy(temp_dma_buffer, data, data_size); dma_data_source = temp_dma_buffer; } else { dma_data_source = (uint8_t *)temp_dma_buffer; - //VIKR - //memset(dma_data_source,0x12,data_size); + } -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) +#ifdef _CYHAL_DCACHE_MAINTENANCE + if (direction == CYHAL_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); + } + else + { /* Cache-Invalidate the output from DMA */ - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif + SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, + data_size + __SCB_DCACHE_LINE_SIZE); } +#endif SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; SDIO->DLEN = dma_transfer_size; @@ -252,12 +275,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, /* Enable the SDIO Clock */ __HAL_RCC_SDMMC1_CLK_ENABLE(); -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - /* Disable DCache for STM32H7 family */ - SCB_CleanDCache(); - SCB_DisableDCache(); -#endif - WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); // Lower speed configuration @@ -437,6 +454,12 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction } if (direction == CYHAL_READ) { + #ifdef _CYHAL_DCACHE_MAINTENANCE + SCB_CleanInvalidateDCache_by_Addr( + (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), + user_data_size + __SCB_DCACHE_LINE_SIZE); + #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ + memcpy(user_data, dma_data_source, (size_t) user_data_size); } From 0cb9f5795d282597953365c3e9ec4ab66008cf8c Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 23 Feb 2023 15:52:05 +0100 Subject: [PATCH 202/227] whd: giga: fix dcache maintenance --- .../COMPONENT_WHD/port/cyhal_sdio.c | 55 +++++++++++++------ 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c index 34aa5498e1a..3ddfd858484 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/COMPONENT_WHD/port/cyhal_sdio.c @@ -63,6 +63,27 @@ #define LINK_MTU 1024 #define MAX(a,b) (a>b)?a:b +/* D-cache maintenance for DMA buffers */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + #define _CYHAL_DCACHE_MAINTENANCE + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) +#else + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) +#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + +/* Macro to ALIGN */ +#if defined (__ARMCC_VERSION) /* ARM Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __align(x) buf +#elif defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf +#endif + +/* Macro to get variable aligned for cache maintenance purpose */ +#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) + + extern pinconfig_t PinConfig[]; extern SD_HandleTypeDef hsd; @@ -74,7 +95,7 @@ static uint32_t dctrl; static whd_driver_t whd_handler; static cyhal_sdio_irq_handler_t sdio_irq_handler; -static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); static uint8_t *user_data; static uint32_t user_data_size; static uint8_t *dma_data_source; @@ -150,22 +171,24 @@ static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t bloc dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); if (direction == CYHAL_WRITE) { - -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif memcpy(temp_dma_buffer, data, data_size); dma_data_source = temp_dma_buffer; } else { dma_data_source = (uint8_t *)temp_dma_buffer; - //VIKR - //memset(dma_data_source,0x12,data_size); + } -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) +#ifdef _CYHAL_DCACHE_MAINTENANCE + if (direction == CYHAL_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); + } + else + { /* Cache-Invalidate the output from DMA */ - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif + SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, + data_size + __SCB_DCACHE_LINE_SIZE); } +#endif SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; SDIO->DLEN = dma_transfer_size; @@ -252,12 +275,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, /* Enable the SDIO Clock */ __HAL_RCC_SDMMC1_CLK_ENABLE(); -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - /* Disable DCache for STM32H7 family */ - SCB_CleanDCache(); - SCB_DisableDCache(); -#endif - WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); // Lower speed configuration @@ -437,6 +454,12 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction } if (direction == CYHAL_READ) { + #ifdef _CYHAL_DCACHE_MAINTENANCE + SCB_CleanInvalidateDCache_by_Addr( + (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), + user_data_size + __SCB_DCACHE_LINE_SIZE); + #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ + memcpy(user_data, dma_data_source, (size_t) user_data_size); } From 90bc47e81609eddd05fe73f8026ef69d649772b5 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 23 Feb 2023 15:52:34 +0100 Subject: [PATCH 203/227] whd: nicla vision: fix dcache maintenance --- .../COMPONENT_WHD/port/cyhal_sdio.c | 55 +++++++++++++------ 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c index 521917c8deb..33b8b26173f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/COMPONENT_WHD/port/cyhal_sdio.c @@ -63,6 +63,27 @@ #define LINK_MTU 1024 #define MAX(a,b) (a>b)?a:b +/* D-cache maintenance for DMA buffers */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + #define _CYHAL_DCACHE_MAINTENANCE + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) +#else + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) +#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + +/* Macro to ALIGN */ +#if defined (__ARMCC_VERSION) /* ARM Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __align(x) buf +#elif defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf +#endif + +/* Macro to get variable aligned for cache maintenance purpose */ +#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) + + extern pinconfig_t PinConfig[]; extern SD_HandleTypeDef hsd; @@ -74,7 +95,7 @@ static uint32_t dctrl; static whd_driver_t whd_handler; static cyhal_sdio_irq_handler_t sdio_irq_handler; -static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); static uint8_t *user_data; static uint32_t user_data_size; static uint8_t *dma_data_source; @@ -150,22 +171,24 @@ static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t bloc dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); if (direction == CYHAL_WRITE) { - -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif memcpy(temp_dma_buffer, data, data_size); dma_data_source = temp_dma_buffer; } else { dma_data_source = (uint8_t *)temp_dma_buffer; - //VIKR - //memset(dma_data_source,0x12,data_size); + } -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) +#ifdef _CYHAL_DCACHE_MAINTENANCE + if (direction == CYHAL_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); + } + else + { /* Cache-Invalidate the output from DMA */ - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif + SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, + data_size + __SCB_DCACHE_LINE_SIZE); } +#endif SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; SDIO->DLEN = dma_transfer_size; @@ -253,12 +276,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, /* Enable the SDIO Clock */ //__HAL_RCC_SDMMC2_CLK_ENABLE(); -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - /* Disable DCache for STM32H7 family */ - SCB_CleanDCache(); - SCB_DisableDCache(); -#endif - WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); // Lower speed configuration @@ -441,6 +458,12 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction } if (direction == CYHAL_READ) { + #ifdef _CYHAL_DCACHE_MAINTENANCE + SCB_CleanInvalidateDCache_by_Addr( + (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), + user_data_size + __SCB_DCACHE_LINE_SIZE); + #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ + memcpy(user_data, dma_data_source, (size_t) user_data_size); } From 163d2d032821381c665e5a47e9592f7940944485 Mon Sep 17 00:00:00 2001 From: pennam Date: Thu, 23 Feb 2023 15:53:03 +0100 Subject: [PATCH 204/227] whd: opta: fix dcache maintenance --- .../COMPONENT_WHD/port/cyhal_sdio.c | 55 +++++++++++++------ 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c index 2174d7f58f3..fcc35616e97 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/COMPONENT_WHD/port/cyhal_sdio.c @@ -63,6 +63,27 @@ #define LINK_MTU 1024 #define MAX(a,b) (a>b)?a:b +/* D-cache maintenance for DMA buffers */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + #define _CYHAL_DCACHE_MAINTENANCE + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) +#else + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) +#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + +/* Macro to ALIGN */ +#if defined (__ARMCC_VERSION) /* ARM Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __align(x) buf +#elif defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf +#endif + +/* Macro to get variable aligned for cache maintenance purpose */ +#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) + + extern pinconfig_t PinConfig[]; extern SD_HandleTypeDef hsd; @@ -74,7 +95,7 @@ static uint32_t dctrl; static whd_driver_t whd_handler; static cyhal_sdio_irq_handler_t sdio_irq_handler; -static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8))); +CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); static uint8_t *user_data; static uint32_t user_data_size; static uint8_t *dma_data_source; @@ -150,22 +171,24 @@ static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t bloc dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); if (direction == CYHAL_WRITE) { - -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif memcpy(temp_dma_buffer, data, data_size); dma_data_source = temp_dma_buffer; } else { dma_data_source = (uint8_t *)temp_dma_buffer; - //VIKR - //memset(dma_data_source,0x12,data_size); + } -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) +#ifdef _CYHAL_DCACHE_MAINTENANCE + if (direction == CYHAL_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); + } + else + { /* Cache-Invalidate the output from DMA */ - SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32); -#endif + SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, + data_size + __SCB_DCACHE_LINE_SIZE); } +#endif SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; SDIO->DLEN = dma_transfer_size; @@ -252,12 +275,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, /* Enable the SDIO Clock */ __HAL_RCC_SDMMC1_CLK_ENABLE(); -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) - /* Disable DCache for STM32H7 family */ - SCB_CleanDCache(); - SCB_DisableDCache(); -#endif - WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); // Lower speed configuration @@ -437,6 +454,12 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction } if (direction == CYHAL_READ) { + #ifdef _CYHAL_DCACHE_MAINTENANCE + SCB_CleanInvalidateDCache_by_Addr( + (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), + user_data_size + __SCB_DCACHE_LINE_SIZE); + #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ + memcpy(user_data, dma_data_source, (size_t) user_data_size); } From a41dabe711c5d9c041cfb6e675bbb6825ec708d1 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 17 Mar 2023 10:41:58 +0100 Subject: [PATCH 205/227] Nicla Vision: add HRTIM pinmux --- .../TARGET_NICLA_VISION/PeripheralPins.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c index c6e8b9cc078..12956b4e288 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_NICLA_VISION/PeripheralPins.c @@ -289,6 +289,22 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {NC, NC, 0} }; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + //*** SERIAL *** MBED_WEAK const PinMap PinMap_UART_TX[] = { From f6d6cdfcefc77d0bf333cf60812a1d0b7282a5f5 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Tue, 11 Jul 2023 15:21:40 +0200 Subject: [PATCH 206/227] giga: fix QSPI initialization --- .../TARGET_GIGA/system_clock_override.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c index 21aa4979b99..71678d11879 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/system_clock_override.c @@ -76,6 +76,23 @@ void SetSysClock(void) } } } + + // Set seemingly unrelated pins that prevent QSPI from working + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = 0; + + GPIO_InitStruct.Pin = GPIO_PIN_13; + __HAL_RCC_GPIOD_CLK_ENABLE(); + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + __HAL_RCC_GPIOD_CLK_DISABLE(); + + GPIO_InitStruct.Pin = GPIO_PIN_7; + __HAL_RCC_GPIOF_CLK_ENABLE(); + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + __HAL_RCC_GPIOF_CLK_DISABLE(); } #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) From 3636262ae786ae623451985dd40c7a54c40b9ab1 Mon Sep 17 00:00:00 2001 From: Leonardo Cavagnis <45899760+leonardocavagnis@users.noreply.github.com> Date: Fri, 29 Sep 2023 10:06:55 +0200 Subject: [PATCH 207/227] STM32: fix HRTIM pwm init and corner case (#31) * STM32: fix HRTIM pwm corner cases (0-100%) in read function * STM32: fix HRTIM pwm init with default values * STM32: add helper fun to manage pwmout obj period --- targets/TARGET_STM/pwmout_api.c | 59 +++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index e20ac918a35..71a4839728b 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -53,6 +53,8 @@ static hrtim_t hrtim_timer; static HRTIM_HandleTypeDef HrtimHandle; static HRTIM_CompareCfgTypeDef sConfig_compare; static HRTIM_TimeBaseCfgTypeDef sConfig_time_base; + +static void _pwmout_obj_period_us(pwmout_t *obj, int us); #endif /* Convert STM32 Cube HAL channel to LL channel */ @@ -142,9 +144,9 @@ static void _pwmout_init_direct(pwmout_t *obj, const PinMap *pinmap) pin_function(pinmap->pin, pinmap->function); pin_mode(pinmap->pin, PullNone); - obj->period = 0; - obj->pulse = 0; - obj->prescaler = 0; + // Initialize obj with default values (period 550Hz, duty 0%) + _pwmout_obj_period_us(obj, 18000); + obj->pulse = (uint32_t)((float)obj->period * 1.0 + 0.5); // Initialize the HRTIM structure HrtimHandle.Instance = HRTIM1; @@ -444,6 +446,15 @@ float pwmout_read(pwmout_t *obj) if (obj->period > 0) { value = (float)(obj->pulse) / (float)(obj->period); } + + if (obj->pwm == PWM_I) { + if (value <= (float)0.0) { + value = 1.0; + } else if (value >= (float)1.0) { + value = 0.0; + } + } + return ((value > (float)1.0) ? (float)(1.0) : (value)); } @@ -464,24 +475,7 @@ void pwmout_period_us(pwmout_t *obj, int us) if (obj->pwm == PWM_I) { float dc = pwmout_read(obj); - uint32_t frequency; - uint32_t clocksource = __HAL_RCC_GET_HRTIM1_SOURCE(); - switch (clocksource) { - case RCC_HRTIM1CLK_TIMCLK: - frequency = HAL_RCC_GetHCLKFreq(); - break; - case RCC_HRTIM1CLK_CPUCLK: - frequency = HAL_RCC_GetSysClockFreq(); - break; - } - - /* conversion from us to clock tick */ - obj->period = us * (frequency / 1000000) / 4; - obj->prescaler = HRTIM_PRESCALERRATIO_DIV4; - - if (obj->period > 0xFFDFU) { - obj->period = 0xFFDFU; - } + _pwmout_obj_period_us(obj, us); sConfig_time_base.Mode = HRTIM_MODE_CONTINUOUS; sConfig_time_base.Period = obj->period; @@ -602,4 +596,27 @@ const PinMap *pwmout_pinmap() return PinMap_PWM; } +#if defined(HRTIM1) +void _pwmout_obj_period_us(pwmout_t *obj, int us) { + uint32_t frequency; + uint32_t clocksource = __HAL_RCC_GET_HRTIM1_SOURCE(); + switch (clocksource) { + case RCC_HRTIM1CLK_TIMCLK: + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_HRTIM1CLK_CPUCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + } + + /* conversion from us to clock tick */ + obj->period = us * (frequency / 1000000) / 4; + obj->prescaler = HRTIM_PRESCALERRATIO_DIV4; + + if (obj->period > 0xFFDFU) { + obj->period = 0xFFDFU; + } +} +#endif + #endif From 28a199761f80a8400da5cac8fbcaf138d29ea596 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Mon, 13 Nov 2023 09:40:06 +0100 Subject: [PATCH 208/227] gcc: callback: prevent wrong optimizations Porting of https://github.com/arduino/ArduinoCore-mbed/pull/755 --- platform/include/platform/Callback.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/platform/include/platform/Callback.h b/platform/include/platform/Callback.h index e76a4f19795..3df0b9117f2 100644 --- a/platform/include/platform/Callback.h +++ b/platform/include/platform/Callback.h @@ -26,6 +26,14 @@ #include #include +#pragma GCC push_options +// This prevents the GCC compiler from applying optimizations that assume the code follows strict aliasing rules. +// In order to prevent bugs arising from undefined behavior that is tricky to find in the Callback implementation, +// or simply from compiler bugs in GCC. +#pragma GCC optimize("-fno-strict-aliasing") +// This prevents the GCC compiler from generating incorrect inline code for the Callback constructor. +#pragma GCC optimize("-fno-inline") + // Controlling switches from config: // MBED_CONF_PLATFORM_CALLBACK_NONTRIVIAL - support storing non-trivial function objects // MBED_CONF_PLATFORM_CALLBACK_COMPARABLE - support memcmp comparing stored objects (requires zero padding) @@ -835,4 +843,6 @@ Callback(R(*func)(const volatile T *, ArgTs...), const volatile U *arg) -> Callb } // namespace mbed +#pragma GCC pop_options + #endif From acfceb16083e2fe8331a7283c0ce126dfd694378 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Oct 2023 16:37:54 +0200 Subject: [PATCH 209/227] portenta_h7: make sure configuration is only executed by M7 --- .../TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp | 3 ++- .../TARGET_PORTENTA_H7/system_clock_override.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp index 13ba1042de5..59e6ac6ccaa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp @@ -26,6 +26,7 @@ ******************************************************************************/ void enableEthPowerSupply(void) { +#ifndef CORE_CM4 /* Ensure ETH power supply */ mbed::I2C i2c(PB_7, PB_6); @@ -48,5 +49,5 @@ void enableEthPowerSupply(void) data[0] = 0x35; data[1] = 0xF; i2c.write(8 << 1, data, sizeof(data)); - +#endif } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c index ae7821ede03..e47b7d258cf 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c @@ -129,6 +129,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) } } +#ifndef CORE_CM4 /* Enable oscillator pin */ __HAL_RCC_GPIOH_CLK_ENABLE(); GPIO_InitTypeDef gpio_osc_init_structure; @@ -139,6 +140,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure); HAL_Delay(10); HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1); +#endif /* Supply configuration update enable */ #if HSE_VALUE == 27000000 From 212b6912c2768cbf2766cf1445cb8ebf9ebcebc7 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Oct 2023 16:38:15 +0200 Subject: [PATCH 210/227] giga: remove stray function --- .../TARGET_GIGA/giga_power.cpp | 23 ------------------- 1 file changed, 23 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp index a47a758e1dd..1954ff50cc6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/giga_power.cpp @@ -26,27 +26,4 @@ ******************************************************************************/ void enableEthPowerSupply(void) { - /* Ensure ETH power supply */ - mbed::I2C i2c(PB_7, PB_6); - - char data[2]; - - // LDO3 to 1.2V - data[0] = 0x52; - data[1] = 0x9; - i2c.write(8 << 1, data, sizeof(data)); - data[0] = 0x53; - data[1] = 0xF; - i2c.write(8 << 1, data, sizeof(data)); - - // SW2 to 3.3V (SW2_VOLT) - data[0] = 0x3B; - data[1] = 0xF; - i2c.write(8 << 1, data, sizeof(data)); - - // SW1 to 3.0V (SW1_VOLT) - data[0] = 0x35; - data[1] = 0xF; - i2c.write(8 << 1, data, sizeof(data)); - } From 801956920432a89b562f57916cc1912765e8fc1d Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Oct 2023 16:39:04 +0200 Subject: [PATCH 211/227] stm32h7 dual core: allow override of HAL_RCC_GetSysClockFreq It's the only needed entry point to get the right timings for all peripherals --- .../STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c index eb5485dc7d7..f03be381a4e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c @@ -1354,7 +1354,7 @@ void HAL_RCC_DisableCSS(void) * * @retval SYSCLK frequency */ -uint32_t HAL_RCC_GetSysClockFreq(void) +__attribute__((weak)) uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; float_t fracn1, pllvco; From 5f87b5f2e094272f5baf735b07bfb3935557e494 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Oct 2023 16:39:59 +0200 Subject: [PATCH 212/227] ble: remove stray specializations the standard one from Cypress driver is fine --- .../TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp | 105 ------------------ .../TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp | 105 ------------------ 2 files changed, 210 deletions(-) delete mode 100644 connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp delete mode 100644 connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp deleted file mode 100644 index 2d668fed9ce..00000000000 --- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_NICLA_VISION/cy_bt_cordio_cfg.cpp +++ /dev/null @@ -1,105 +0,0 @@ -/******************************************************************************* -* \file cy_bt_cordio_cfg.cpp -* \version 1.0 -* -* -* Low Power Assist BT Pin configuration implementation. -* -******************************************************************************** -* \copyright -* Copyright 2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "ble/driver/CordioHCIDriver.h" -#include "hci_api.h" -#include "hci_cmd.h" -#include "hci_core.h" -#include "bstream.h" -#include "assert.h" -#include -#include "hci_mbed_os_adaptation.h" -#include "CyH4TransportDriver.h" - -#define cyhal_gpio_to_rtos(x) (x) -#define CYCFG_BT_LP_ENABLED (1) -#define CYCFG_BT_HOST_WAKE_IRQ_EVENT WAKE_EVENT_ACTIVE_LOW -#define CYCFG_BT_DEV_WAKE_POLARITY WAKE_EVENT_ACTIVE_LOW - -/******************************************************************************* -* Function Name: ble_cordio_get_h4_transport_driver -******************************************************************************** -* -* Strong implementation of function which calls CyH4TransportDriver constructor and return it -* -* \param none -* -* \return -* Returns the transport driver object -*******************************************************************************/ -ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver() -{ -#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - -#if (defined(CYCFG_BT_LP_ENABLED)) - if (CYCFG_BT_LP_ENABLED) { - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE, - cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), - cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE), - CYCFG_BT_HOST_WAKE_IRQ_EVENT, - CYCFG_BT_DEV_WAKE_POLARITY - ); - return s_transport_driver; - } else { /* CYCFG_BT_LP_ENABLED */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE); - return s_transport_driver; - } -#else /* (defined(CYCFG_BT_LP_ENABLED)) */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE), - cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE) - ); - return s_transport_driver; -#endif /* (defined(CYCFG_BT_LP_ENABLED)) */ - -#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE); - return s_transport_driver; -#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ -} diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp deleted file mode 100644 index 2d668fed9ce..00000000000 --- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_CYW43XXX/TARGET_PORTENTA_H7/cy_bt_cordio_cfg.cpp +++ /dev/null @@ -1,105 +0,0 @@ -/******************************************************************************* -* \file cy_bt_cordio_cfg.cpp -* \version 1.0 -* -* -* Low Power Assist BT Pin configuration implementation. -* -******************************************************************************** -* \copyright -* Copyright 2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "ble/driver/CordioHCIDriver.h" -#include "hci_api.h" -#include "hci_cmd.h" -#include "hci_core.h" -#include "bstream.h" -#include "assert.h" -#include -#include "hci_mbed_os_adaptation.h" -#include "CyH4TransportDriver.h" - -#define cyhal_gpio_to_rtos(x) (x) -#define CYCFG_BT_LP_ENABLED (1) -#define CYCFG_BT_HOST_WAKE_IRQ_EVENT WAKE_EVENT_ACTIVE_LOW -#define CYCFG_BT_DEV_WAKE_POLARITY WAKE_EVENT_ACTIVE_LOW - -/******************************************************************************* -* Function Name: ble_cordio_get_h4_transport_driver -******************************************************************************** -* -* Strong implementation of function which calls CyH4TransportDriver constructor and return it -* -* \param none -* -* \return -* Returns the transport driver object -*******************************************************************************/ -ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver() -{ -#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - -#if (defined(CYCFG_BT_LP_ENABLED)) - if (CYCFG_BT_LP_ENABLED) { - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE, - cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), - cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE), - CYCFG_BT_HOST_WAKE_IRQ_EVENT, - CYCFG_BT_DEV_WAKE_POLARITY - ); - return s_transport_driver; - } else { /* CYCFG_BT_LP_ENABLED */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE); - return s_transport_driver; - } -#else /* (defined(CYCFG_BT_LP_ENABLED)) */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE), - cyhal_gpio_to_rtos(CYBSP_BT_HOST_WAKE), cyhal_gpio_to_rtos(CYBSP_BT_DEVICE_WAKE) - ); - return s_transport_driver; -#endif /* (defined(CYCFG_BT_LP_ENABLED)) */ - -#else /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ - static ble::vendor::cypress_ble::CyH4TransportDriver s_transport_driver( - /* TX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_TX), - /* RX */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RX), - /* cts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_CTS), - /* rts */ cyhal_gpio_to_rtos(CYBSP_BT_UART_RTS), - /* power */ cyhal_gpio_to_rtos(CYBSP_BT_POWER), - DEF_BT_BAUD_RATE); - return s_transport_driver; -#endif /* (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) */ -} From 733dcecd97cf128f2c7d727ee985dfb1e6be1cfa Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 26 Oct 2023 16:41:10 +0200 Subject: [PATCH 213/227] stm32h747_m4: implement a standalone target --- .../COMPONENT_CYW43XXX/CMakeLists.txt | 4 + .../firmware/CMakeLists.txt | 6 + .../COMPONENT_4343W_FS/CMakeLists.txt | 7 + .../w_bt_firmware_controller.c | 2101 ++ .../COMPONENT_WHD/CMakeLists.txt | 34 + .../COMPONENT_WHD/generated_mac_address.txt | 9 + .../COMPONENT_WHD/interface/cy_result.h | 228 + .../COMPONENT_WHD/interface/cyabs_rtos.h | 711 + .../COMPONENT_WHD/interface/cyabs_rtos_impl.h | 77 + .../interface/cyabs_rtos_rtxv5.c | 863 + .../COMPONENT_WHD/interface/cyhal_gpio.h | 247 + .../COMPONENT_WHD/interface/cyhal_sdio.h | 366 + .../COMPONENT_WHD/interface/cyhal_spi.h | 383 + .../COMPONENT_WHD/port/cy_hal.c | 63 + .../COMPONENT_WHD/port/cy_syslib.h | 592 + .../COMPONENT_WHD/port/cy_utils.h | 81 + .../COMPONENT_WHD/port/cybsp.h | 50 + .../COMPONENT_WHD/port/cycfg.h | 20 + .../COMPONENT_WHD/port/cyhal.h | 52 + .../COMPONENT_WHD/port/cyhal_gpio.cpp | 104 + .../COMPONENT_WHD/port/cyhal_hw_types.h | 112 + .../COMPONENT_WHD/port/cyhal_sdio.c | 506 + .../COMPONENT_WHD/port/cyhal_spi.c | 29 + .../COMPONENT_WHD/port/cyhal_system.h | 20 + .../COMPONENT_WHD/port/wiced_bd.h | 49 + .../COMPONENT_WHD/port/wiced_filesystem.cpp | 225 + .../COMPONENT_WHD/port/wiced_filesystem.h | 148 + .../LICENSE-permissive-binary-license-1.0.txt | 49 + .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 25493 ++++++++++++++++ .../COMPONENT_4343W_FS/4343WA1_clm_blob.c | 400 + .../firmware/COMPONENT_4343W_FS/resources.h | 30 + .../resources/nvram/wifi_nvram_image.h | 87 + .../COMPONENT_WHD/whd_config.h | 61 + .../PeripheralPins.c | 578 + .../TARGET_GENERIC_STM32H747_M4/PinNames.h | 356 + targets/targets.json | 50 +- 36 files changed, 34179 insertions(+), 12 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt new file mode 100644 index 00000000000..82be36e1f09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(firmware) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt new file mode 100644 index 00000000000..fbbc3b979de --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("4343W_FS" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_4343W) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt new file mode 100644 index 00000000000..31fecb8fe09 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-ble + INTERFACE + w_bt_firmware_controller.c +) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c new file mode 100644 index 00000000000..ac2bc973e1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_CYW43XXX/firmware/COMPONENT_4343W_FS/w_bt_firmware_controller.c @@ -0,0 +1,2101 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = "BCM4343A1_001.002.009.0083.0000_Generic_UART_37_4MHz_wlbga_wiced"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[] = { + 76, 252, 70, 16, 24, 33, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, + 0, 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 18, 161, + 67, 67, 0, 1, 28, 82, 24, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 255, 82, 24, + 33, 0, 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 79, 133, 0, 0, + 3, 3, 40, 66, 67, 77, 52, 51, 52, 51, 65, 49, 32, 85, 65, 82, 84, 32, + 51, 55, 46, 52, 32, 77, 72, 122, 32, 119, 108, 98, 103, 97, 95, 114, + 101, 102, 32, 119, 105, 99, 101, 100, 0, 22, 3, 2, 83, 0, 2, 1, 248, + 3, 8, 1, 50, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 50, 0, 255, 15, 0, 0, + 98, 8, 0, 0, 112, 0, 100, 0, 128, 0, 0, 0, 128, 0, 0, 0, 172, 0, 50, + 0, 255, 255, 255, 1, 0, 0, 47, 0, 140, 0, 50, 0, 0, 240, 255, 15, 0, + 16, 17, 1, 120, 0, 50, 0, 255, 255, 255, 255, 185, 184, 184, 184, 96, + 44, 32, 0, 255, 0, 0, 0, 0, 0, 0, 0, 16, 1, 50, 0, 0, 0, 255, 255, 0, + 0, 24, 24, 108, 1, 96, 0, 255, 255, 255, 255, 11, 0, 0, 0, 112, 1, 96, + 0, 255, 255, 255, 255, 16, 0, 0, 0, 116, 1, 96, 0, 255, 255, 255, 255, + 21, 0, 0, 0, 120, 1, 96, 0, 255, 255, 255, 255, 25, 0, 0, 0, 124, 1, + 96, 0, 255, 255, 0, 0, 29, 0, 0, 0, 132, 1, 96, 0, 255, 255, 255, 255, + 33, 0, 0, 0, 96, 6, 65, 0, 255, 255, 0, 0, 51, 3, 0, 0, 100, 6, 65, + 76, 252, 255, 77, 25, 33, 0, 0, 255, 255, 0, 0, 41, 58, 0, 0, 100, 6, + 65, 0, 255, 255, 0, 0, 41, 58, 0, 0, 104, 6, 65, 0, 255, 255, 0, 0, + 104, 5, 0, 0, 108, 6, 65, 0, 255, 255, 0, 0, 168, 48, 0, 0, 112, 6, + 65, 0, 255, 255, 0, 0, 232, 62, 0, 0, 116, 6, 65, 0, 255, 255, 0, 0, + 28, 50, 0, 0, 120, 6, 65, 0, 255, 255, 0, 0, 187, 51, 0, 0, 124, 6, + 65, 0, 255, 255, 0, 0, 48, 9, 0, 0, 80, 3, 65, 0, 255, 255, 0, 0, 16, + 5, 0, 0, 84, 3, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 92, 3, 65, 0, 255, + 255, 0, 0, 9, 8, 0, 0, 96, 3, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 100, + 3, 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 108, 3, 65, 0, 255, 255, 0, 0, + 14, 9, 0, 0, 116, 3, 65, 0, 255, 255, 0, 0, 5, 9, 0, 0, 120, 3, 65, + 0, 255, 255, 0, 0, 16, 10, 0, 0, 64, 1, 65, 0, 255, 255, 0, 0, 16, 5, + 0, 0, 68, 1, 65, 0, 255, 255, 0, 0, 9, 9, 0, 0, 76, 1, 65, 0, 255, 255, + 0, 0, 9, 8, 0, 0, 80, 1, 65, 0, 255, 255, 0, 0, 15, 7, 0, 0, 84, 1, + 65, 0, 255, 255, 0, 0, 5, 8, 0, 0, 92, 1, 76, 252, 255, 72, 26, 33, + 0, 65, 0, 255, 255, 0, 0, 14, 9, 0, 0, 96, 1, 65, 0, 255, 255, 0, 0, + 5, 9, 0, 0, 100, 1, 65, 0, 255, 255, 0, 0, 16, 10, 0, 0, 224, 6, 65, + 0, 255, 255, 0, 0, 113, 32, 0, 0, 156, 1, 96, 0, 255, 0, 0, 0, 3, 0, + 0, 0, 100, 1, 96, 0, 255, 255, 255, 255, 0, 0, 0, 0, 9, 1, 4, 2, 1, + 0, 0, 34, 3, 2, 1, 0, 240, 1, 40, 4, 0, 0, 0, 32, 21, 50, 0, 255, 255, + 250, 255, 217, 3, 62, 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, + 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, 240, 1, 40, 1, 0, 0, 0, + 32, 21, 50, 0, 255, 255, 250, 255, 221, 3, 62, 254, 40, 21, 50, 0, 0, + 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, + 240, 1, 40, 2, 0, 0, 0, 32, 21, 50, 0, 255, 255, 250, 255, 217, 3, 62, + 254, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 44, 9, 100, 0, 14, + 0, 0, 0, 12, 0, 0, 0, 240, 1, 160, 1, 3, 0, 0, 0, 16, 21, 50, 0, 0, + 0, 0, 0, 240, 240, 240, 0, 20, 21, 50, 0, 0, 0, 0, 0, 240, 240, 240, + 0, 24, 21, 50, 0, 0, 0, 0, 0, 76, 252, 255, 67, 27, 33, 0, 240, 240, + 240, 0, 28, 21, 50, 0, 0, 0, 0, 0, 76, 76, 0, 0, 32, 21, 50, 0, 255, + 255, 250, 255, 221, 3, 62, 254, 36, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 40, 21, 50, 0, 0, 0, 127, 254, 52, 16, 40, 2, 52, 21, 50, 0, 0, 0, + 0, 0, 240, 0, 0, 0, 56, 21, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 21, 50, + 0, 0, 0, 0, 0, 202, 6, 0, 0, 44, 9, 100, 0, 14, 0, 0, 0, 12, 0, 0, 0, + 248, 0, 100, 0, 81, 0, 0, 0, 16, 0, 0, 0, 120, 8, 100, 0, 2, 0, 0, 0, + 0, 0, 0, 0, 1, 7, 181, 3, 4, 6, 10, 35, 60, 90, 110, 125, 5, 56, 4, + 136, 4, 156, 4, 136, 4, 216, 4, 116, 4, 196, 4, 216, 4, 196, 4, 20, + 5, 176, 4, 0, 5, 20, 5, 0, 5, 80, 5, 246, 4, 70, 5, 90, 5, 70, 5, 150, + 5, 60, 5, 140, 5, 160, 5, 140, 5, 220, 5, 130, 5, 210, 5, 230, 5, 210, + 5, 34, 6, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 168, + 2, 168, 2, 168, 2, 168, 2, 168, 2, 228, 2, 228, 2, 228, 2, 228, 2, 228, + 2, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 102, 3, 102, 3, 102, 3, 102, 3, + 102, 3, 172, 3, 76, 252, 255, 62, 28, 33, 0, 172, 3, 172, 3, 172, 3, + 172, 3, 242, 3, 242, 3, 242, 3, 242, 3, 242, 3, 20, 255, 20, 255, 20, + 255, 20, 255, 20, 255, 20, 255, 6, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, + 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, 200, + 2, 255, 204, 2, 255, 208, 2, 255, 212, 2, 255, 216, 2, 255, 0, 0, 96, + 0, 5, 136, 3, 255, 140, 3, 255, 144, 3, 255, 148, 3, 255, 152, 3, 255, + 0, 0, 96, 0, 5, 156, 3, 255, 160, 3, 255, 164, 3, 255, 168, 3, 255, + 172, 3, 255, 0, 0, 96, 0, 5, 128, 3, 255, 132, 3, 255, 160, 6, 255, + 180, 2, 255, 56, 7, 255, 0, 0, 96, 0, 3, 164, 6, 255, 92, 6, 255, 152, + 6, 255, 76, 76, 76, 76, 76, 65, 65, 65, 65, 65, 133, 133, 133, 133, + 132, 166, 165, 165, 165, 165, 164, 244, 24, 3, 250, 101, 3, 204, 95, + 95, 95, 95, 95, 77, 77, 77, 77, 77, 132, 132, 132, 132, 131, 165, 164, + 164, 164, 164, 164, 244, 26, 3, 250, 102, 3, 204, 108, 108, 108, 108, + 108, 88, 88, 88, 88, 88, 132, 132, 132, 132, 131, 165, 164, 164, 164, + 164, 164, 244, 31, 3, 250, 102, 3, 204, 133, 133, 133, 133, 133, 105, + 105, 105, 105, 105, 132, 132, 132, 132, 131, 165, 164, 164, 164, 164, + 164, 76, 252, 255, 57, 29, 33, 0, 244, 31, 3, 250, 102, 3, 204, 153, + 153, 153, 153, 153, 116, 116, 116, 116, 116, 132, 132, 132, 132, 131, + 165, 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 3, 204, 179, 179, + 179, 179, 179, 130, 130, 130, 130, 130, 132, 132, 132, 132, 131, 165, + 164, 164, 164, 164, 164, 244, 31, 3, 250, 103, 35, 255, 1, 7, 181, 3, + 0, 6, 10, 35, 60, 90, 110, 125, 5, 92, 3, 62, 3, 72, 3, 92, 3, 72, 3, + 152, 3, 122, 3, 132, 3, 152, 3, 132, 3, 212, 3, 182, 3, 192, 3, 212, + 3, 192, 3, 26, 4, 252, 3, 6, 4, 26, 4, 6, 4, 96, 4, 66, 4, 76, 4, 96, + 4, 76, 4, 166, 4, 136, 4, 146, 4, 166, 4, 146, 4, 20, 255, 20, 255, + 20, 255, 20, 255, 20, 255, 20, 255, 68, 2, 48, 2, 38, 2, 18, 2, 28, + 2, 128, 2, 108, 2, 98, 2, 78, 2, 88, 2, 188, 2, 168, 2, 158, 2, 138, + 2, 148, 2, 2, 3, 238, 2, 228, 2, 208, 2, 218, 2, 72, 3, 52, 3, 42, 3, + 22, 3, 32, 3, 142, 3, 122, 3, 112, 3, 92, 3, 102, 3, 20, 255, 20, 255, + 20, 255, 20, 255, 20, 255, 20, 255, 6, 0, 0, 0, 96, 0, 5, 156, 2, 255, + 160, 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, + 200, 2, 255, 204, 76, 252, 255, 52, 30, 33, 0, 2, 255, 208, 2, 255, + 212, 2, 255, 216, 2, 255, 0, 0, 96, 0, 5, 136, 3, 255, 140, 3, 255, + 144, 3, 255, 148, 3, 255, 152, 3, 255, 0, 0, 96, 0, 5, 156, 3, 255, + 160, 3, 255, 164, 3, 255, 168, 3, 255, 172, 3, 255, 0, 0, 96, 0, 5, + 128, 3, 255, 132, 3, 255, 160, 6, 255, 180, 2, 255, 56, 7, 255, 0, 0, + 96, 0, 3, 164, 6, 255, 92, 6, 255, 152, 6, 255, 67, 57, 55, 55, 56, + 56, 53, 53, 54, 53, 136, 134, 134, 134, 133, 168, 166, 166, 166, 164, + 164, 244, 24, 3, 250, 101, 3, 204, 76, 69, 65, 66, 67, 64, 60, 59, 59, + 60, 136, 134, 134, 134, 133, 168, 166, 166, 166, 164, 164, 244, 26, + 3, 250, 102, 3, 204, 92, 82, 82, 82, 82, 75, 71, 71, 71, 71, 136, 134, + 134, 134, 133, 168, 166, 166, 166, 164, 164, 244, 31, 3, 250, 102, 3, + 204, 106, 99, 95, 95, 100, 87, 83, 82, 82, 83, 136, 134, 134, 134, 133, + 168, 166, 166, 166, 164, 164, 244, 31, 3, 250, 102, 3, 204, 124, 113, + 110, 110, 113, 97, 93, 92, 92, 93, 136, 134, 134, 134, 133, 168, 166, + 166, 166, 164, 164, 244, 31, 3, 250, 103, 3, 204, 140, 129, 127, 127, + 129, 111, 104, 103, 103, 104, 136, 134, 134, 134, 133, 168, 166, 166, + 166, 164, 164, 244, 31, 3, 250, 103, 76, 252, 255, 47, 31, 33, 0, 35, + 255, 2, 7, 127, 4, 6, 5, 56, 4, 136, 4, 156, 4, 136, 4, 216, 4, 116, + 4, 196, 4, 216, 4, 196, 4, 20, 5, 176, 4, 0, 5, 20, 5, 0, 5, 80, 5, + 246, 4, 70, 5, 90, 5, 70, 5, 150, 5, 60, 5, 140, 5, 160, 5, 140, 5, + 220, 5, 130, 5, 210, 5, 230, 5, 210, 5, 34, 6, 20, 255, 20, 255, 20, + 255, 20, 255, 20, 255, 20, 255, 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, + 2, 255, 164, 2, 255, 168, 2, 255, 172, 2, 255, 76, 76, 76, 76, 76, 95, + 95, 95, 95, 95, 108, 108, 108, 108, 108, 133, 133, 133, 133, 133, 153, + 153, 153, 153, 153, 179, 179, 179, 179, 179, 2, 7, 127, 0, 6, 5, 92, + 3, 62, 3, 72, 3, 92, 3, 72, 3, 152, 3, 122, 3, 132, 3, 152, 3, 132, + 3, 212, 3, 182, 3, 192, 3, 212, 3, 192, 3, 26, 4, 252, 3, 6, 4, 26, + 4, 6, 4, 96, 4, 66, 4, 76, 4, 96, 4, 76, 4, 166, 4, 136, 4, 146, 4, + 166, 4, 146, 4, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, + 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, + 255, 172, 2, 255, 67, 57, 55, 55, 56, 76, 69, 65, 66, 67, 92, 83, 82, + 82, 82, 106, 99, 95, 95, 76, 252, 255, 42, 32, 33, 0, 100, 124, 113, + 110, 110, 113, 140, 129, 127, 127, 129, 0, 7, 4, 63, 0, 0, 0, 3, 1, + 196, 1, 8, 10, 32, 0, 8, 8, 0, 0, 4, 4, 0, 0, 16, 16, 0, 0, 8, 8, 0, + 0, 24, 24, 0, 0, 40, 40, 0, 0, 32, 32, 0, 0, 44, 44, 0, 0, 40, 40, 0, + 0, 48, 48, 0, 0, 65, 65, 0, 0, 52, 52, 0, 0, 73, 73, 0, 0, 32, 32, 1, + 1, 80, 80, 0, 0, 36, 36, 1, 1, 88, 88, 0, 0, 64, 64, 1, 1, 138, 138, + 0, 0, 96, 96, 1, 1, 139, 139, 0, 0, 100, 100, 1, 1, 140, 140, 0, 0, + 96, 96, 2, 2, 141, 141, 0, 0, 100, 100, 2, 2, 142, 142, 0, 0, 104, 104, + 2, 2, 143, 143, 0, 0, 108, 108, 2, 2, 150, 150, 0, 0, 112, 112, 2, 2, + 165, 165, 0, 0, 80, 80, 3, 3, 166, 166, 0, 0, 84, 84, 3, 3, 221, 221, + 0, 0, 116, 116, 3, 3, 229, 229, 0, 0, 120, 120, 3, 3, 237, 237, 0, 0, + 152, 152, 3, 3, 238, 238, 0, 0, 252, 252, 3, 3, 239, 239, 0, 0, 188, + 188, 3, 3, 239, 239, 0, 0, 188, 188, 3, 3, 3, 1, 100, 200, 10, 32, 0, + 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 64, 0, 0, 1, 65, + 0, 4, 1, 73, 0, 76, 252, 255, 37, 33, 33, 0, 36, 1, 80, 0, 64, 1, 88, + 0, 96, 1, 82, 0, 72, 1, 83, 0, 76, 1, 84, 0, 80, 1, 85, 0, 84, 1, 86, + 0, 88, 1, 87, 0, 92, 1, 102, 0, 152, 1, 110, 0, 184, 1, 118, 0, 216, + 1, 126, 0, 248, 1, 127, 0, 252, 1, 127, 0, 252, 1, 127, 0, 252, 1, 127, + 0, 252, 1, 127, 0, 252, 1, 3, 1, 58, 40, 11, 32, 0, 1, 0, 0, 1, 0, 0, + 5, 0, 0, 13, 0, 0, 29, 0, 0, 14, 0, 0, 30, 0, 0, 62, 0, 0, 15, 0, 0, + 31, 0, 0, 63, 0, 0, 127, 0, 0, 255, 0, 0, 255, 0, 0, 255, 0, 0, 255, + 0, 0, 255, 0, 0, 255, 0, 0, 3, 1, 5, 8, 8, 32, 0, 6, 3, 1, 5, 12, 8, + 32, 0, 5, 3, 1, 5, 16, 8, 32, 0, 11, 3, 1, 5, 20, 8, 32, 0, 10, 4, 7, + 152, 1, 4, 50, 31, 0, 0, 29, 0, 0, 28, 1, 0, 26, 2, 0, 23, 2, 0, 21, + 18, 0, 19, 85, 0, 17, 100, 0, 15, 17, 0, 14, 3, 0, 13, 20, 0, 11, 80, + 0, 10, 100, 0, 9, 35, 0, 8, 35, 0, 7, 3, 0, 7, 22, 0, 6, 21, 0, 5, 19, + 0, 5, 22, 0, 4, 19, 0, 4, 38, 0, 4, 25, 0, 3, 5, 0, 3, 8, 0, 3, 42, + 0, 2, 3, 0, 2, 76, 252, 255, 32, 34, 33, 0, 22, 0, 2, 9, 0, 2, 43, 0, + 2, 61, 0, 2, 63, 0, 1, 2, 0, 1, 21, 0, 1, 24, 0, 1, 58, 0, 1, 29, 0, + 1, 31, 0, 1, 143, 0, 1, 239, 0, 1, 63, 1, 1, 143, 1, 1, 207, 1, 1, 15, + 2, 1, 79, 2, 1, 127, 2, 1, 175, 2, 1, 207, 2, 1, 0, 0, 1, 0, 0, 4, 7, + 152, 1, 0, 50, 31, 0, 0, 29, 0, 0, 28, 1, 0, 26, 2, 0, 23, 2, 0, 21, + 18, 0, 19, 85, 0, 17, 100, 0, 15, 17, 0, 14, 3, 0, 13, 20, 0, 11, 80, + 0, 10, 100, 0, 9, 35, 0, 8, 35, 0, 7, 3, 0, 7, 22, 0, 6, 21, 0, 5, 19, + 0, 5, 22, 0, 4, 19, 0, 4, 38, 0, 4, 25, 0, 3, 5, 0, 3, 8, 0, 3, 42, + 0, 2, 3, 0, 2, 22, 0, 2, 9, 0, 2, 43, 0, 2, 61, 0, 2, 63, 0, 1, 2, 0, + 1, 21, 0, 1, 24, 0, 1, 58, 0, 1, 29, 0, 1, 31, 0, 1, 143, 0, 1, 239, + 0, 1, 63, 1, 1, 143, 1, 1, 207, 1, 1, 15, 2, 1, 79, 2, 1, 127, 2, 1, + 175, 2, 1, 207, 2, 1, 0, 0, 1, 0, 0, 3, 7, 43, 1, 0, 0, 0, 1, 0, 0, + 0, 0, 20, 10, 0, 4, 0, 0, 0, 0, 0, 0, 10, 2, 254, 11, 228, 76, 252, + 255, 27, 35, 33, 0, 254, 28, 1, 228, 254, 28, 1, 10, 2, 254, 11, 241, + 255, 15, 0, 241, 255, 15, 0, 5, 7, 36, 255, 1, 8, 8, 12, 0, 8, 1, 4, + 2, 0, 3, 252, 4, 248, 5, 244, 6, 240, 7, 12, 0, 8, 1, 4, 2, 0, 3, 252, + 4, 248, 5, 244, 6, 240, 7, 15, 3, 40, 2, 120, 20, 127, 90, 0, 20, 2, + 20, 30, 0, 2, 3, 0, 30, 170, 51, 25, 5, 207, 0, 128, 10, 146, 0, 0, + 0, 0, 7, 0, 0, 162, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 5, 24, 19, 33, 0, + 144, 3, 1, 5, 201, 34, 32, 0, 0, 3, 1, 12, 220, 29, 32, 0, 1, 1, 48, + 0, 2, 10, 10, 0, 3, 1, 5, 72, 44, 32, 0, 1, 3, 1, 5, 36, 51, 32, 0, + 1, 3, 1, 5, 78, 5, 32, 0, 0, 3, 1, 6, 8, 30, 32, 0, 0, 0, 3, 1, 8, 184, + 40, 32, 0, 0, 0, 0, 0, 3, 1, 5, 237, 37, 32, 0, 0, 3, 1, 6, 198, 50, + 32, 0, 42, 14, 3, 1, 6, 172, 44, 32, 0, 240, 0, 3, 1, 6, 236, 39, 32, + 0, 128, 7, 3, 1, 5, 152, 52, 32, 0, 0, 4, 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16, 1, 15, 97, 208, 75, 3, 0, 155, 240, 130, + 189, 0, 0, 216, 6, 13, 0, 16, 1, 15, 98, 116, 77, 3, 0, 155, 240, 180, + 188, 76, 252, 255, 180, 155, 33, 0, 0, 0, 224, 6, 13, 0, 16, 1, 15, + 99, 28, 71, 3, 0, 155, 240, 230, 191, 0, 0, 236, 6, 13, 0, 16, 1, 15, + 100, 52, 53, 3, 0, 157, 240, 222, 184, 0, 0, 244, 6, 13, 0, 16, 1, 15, + 101, 156, 55, 3, 0, 156, 240, 184, 191, 0, 0, 16, 7, 13, 0, 16, 1, 15, + 102, 236, 23, 2, 0, 179, 240, 230, 185, 0, 0, 188, 75, 13, 0, 16, 1, + 15, 103, 56, 199, 1, 0, 179, 240, 242, 191, 0, 0, 32, 7, 13, 0, 16, + 1, 15, 104, 16, 68, 0, 0, 208, 240, 242, 188, 0, 0, 248, 77, 13, 0, + 16, 1, 15, 105, 4, 199, 1, 0, 180, 240, 15, 184, 0, 0, 38, 7, 13, 0, + 16, 1, 15, 106, 132, 211, 2, 0, 167, 240, 32, 191, 0, 0, 200, 81, 13, + 0, 16, 1, 15, 107, 240, 210, 2, 0, 163, 240, 32, 186, 0, 0, 52, 7, 13, + 0, 6, 1, 4, 124, 85, 13, 0, 6, 1, 4, 104, 88, 13, 0, 16, 1, 15, 108, + 240, 175, 1, 0, 186, 240, 96, 188, 0, 0, 180, 88, 13, 0, 16, 1, 15, + 109, 12, 7, 2, 0, 176, 240, 32, 184, 0, 0, 80, 7, 13, 0, 16, 1, 15, + 110, 100, 57, 8, 0, 81, 240, 228, 191, 0, 0, 48, 89, 13, 0, 16, 1, 15, + 111, 100, 86, 4, 0, 139, 240, 124, 184, 0, 0, 96, 76, 252, 255, 175, + 156, 33, 0, 7, 13, 0, 16, 1, 15, 112, 60, 86, 4, 0, 144, 240, 209, 185, + 0, 0, 226, 89, 13, 0, 16, 1, 15, 113, 176, 87, 4, 0, 138, 240, 217, + 191, 0, 0, 102, 7, 13, 0, 16, 1, 15, 114, 204, 45, 5, 0, 125, 240, 206, + 188, 0, 0, 108, 7, 13, 0, 16, 1, 15, 115, 128, 42, 3, 0, 157, 240, 122, + 190, 0, 0, 120, 7, 13, 0, 16, 1, 15, 116, 84, 164, 6, 0, 102, 240, 164, + 185, 0, 0, 160, 7, 13, 0, 16, 1, 15, 117, 20, 105, 5, 0, 121, 240, 72, + 191, 0, 0, 168, 7, 13, 0, 16, 1, 15, 118, 232, 112, 7, 0, 89, 240, 98, + 187, 0, 0, 176, 7, 13, 0, 16, 1, 15, 119, 132, 103, 7, 0, 90, 240, 28, + 184, 0, 0, 192, 7, 13, 0, 16, 1, 15, 120, 84, 47, 0, 0, 205, 240, 60, + 188, 0, 0, 208, 7, 13, 0, 16, 1, 15, 121, 224, 49, 0, 0, 205, 240, 250, + 186, 0, 0, 216, 7, 13, 0, 16, 1, 15, 122, 252, 181, 1, 0, 181, 240, + 248, 184, 0, 0, 240, 7, 13, 0, 16, 1, 15, 123, 252, 199, 1, 0, 179, + 240, 254, 191, 0, 0, 252, 7, 13, 0, 16, 1, 15, 124, 100, 200, 1, 0, + 179, 240, 207, 191, 0, 0, 6, 8, 13, 0, 16, 1, 15, 125, 80, 180, 1, 0, + 181, 240, 224, 185, 0, 0, 76, 252, 11, 170, 157, 33, 0, 20, 8, 13, 0, + 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 +}; + +const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt new file mode 100644 index 00000000000..55b7e63ecf3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-portenta-whd-4343w-fw INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS +) +target_sources(mbed-portenta-whd-4343w-fw + INTERFACE + resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c + resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c +) + +add_library(mbed-portenta-whd-4343w-nvram INTERFACE) +target_include_directories(mbed-portenta-whd-4343w-nvram INTERFACE resources/nvram) + +add_library(mbed-portenta-whd INTERFACE) +target_include_directories(mbed-portenta-whd + INTERFACE + . + port + interface +) + +target_sources(mbed-portenta-whd + INTERFACE + port/cyhal.c + port/cyhalgpio.cpp + port/cyhalsdio.c + port/wiced_filesystem.cpp + interface/cyabs_rtos_rtxv5.c +) + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt new file mode 100644 index 00000000000..eb735ba173d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during WHD power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:6f:b2:ea" diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h new file mode 100644 index 00000000000..8277169ab99 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cy_result.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file cy_result.h +* +* \brief +* Basic function result handling. Defines a simple type for conveying +* information about whether something succeeded or details about any issues +* that were detected. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_result Result Type +* \ingroup group_abstraction +* \{ +* \anchor anchor_general_description +* \brief Defines a type and related utilities for function result handling. +* +* The @ref cy_rslt_t type is a structured bitfield which encodes information +* about result type, the originating module, and a code for the specific +* error (or warning etc). In order to extract these individual fields from +* a @ref cy_rslt_t value, the utility macros @ref CY_RSLT_GET_TYPE, @ref CY_RSLT_GET_MODULE, +* and @ref CY_RSLT_GET_CODE are provided. For example: +* \code +* cy_rslt_t result = cy_hal_do_operation(arg); +* // Will be CY_RSLT_TYPE_INFO, CY_RSLT_TYPE_WARNING, CY_RSLT_TYPE_ERROR, or CY_RSLT_TYPE_FATAL +* uint8_t type = CY_RSLT_GET_TYPE(result) +* // See the "Modules" section for possible values +* uint16_t module_id = CY_RSLT_GET_MODULE(result); +* // Specific error codes are defined by each module +* uint16_t error_code = CY_RSLT_GET_CODE(result); +* \endcode +*/ + +#if !defined(CY_RESULT_H) +#define CY_RESULT_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief Provides the result of an operation as a structured bitfield. + * + * See the \ref anchor_general_description "General Description" + * for more details on structure and usage. + */ +typedef uint32_t cy_rslt_t; + +/** @ref cy_rslt_t return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) + +/** \cond INTERNAL */ +/** Mask for the bit at position "x" */ +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) + +/** Bit position of the result type */ +#define CY_RSLT_TYPE_POSITION (16U) +/** Bit width of the result type */ +#define CY_RSLT_TYPE_WIDTH (2U) +/** Bit position of the module identifier */ +#define CY_RSLT_MODULE_POSITION (18U) +/** Bit width of the module identifier */ +#define CY_RSLT_MODULE_WIDTH (14U) +/** Bit position of the result code */ +#define CY_RSLT_CODE_POSITION (0U) +/** Bit width of the result code */ +#define CY_RSLT_CODE_WIDTH (16U) + +/** Mask for the result type */ +#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) +/** Mask for the module identifier */ +#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH) +/** Mask for the result code */ +#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH) + +/** \endcond */ + +/** +* \{ +* @name Fields +* Utility macros for constructing result values and extracting individual fields from existing results. +*/ + +/** + * @brief Get the value of the result type field + * @param x the @ref cy_rslt_t value from which to extract the result type + */ +#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK) +/** + * @brief Get the value of the module identifier field + * @param x the @ref cy_rslt_t value from which to extract the module id + */ +#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) +/** + * @brief Get the value of the result code field + * @param x the @ref cy_rslt_t value from which to extract the result code + */ +#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) + +/** + * @brief Create a new @ref cy_rslt_t value that encodes the specified type, module, and result code. + * @param type one of @ref CY_RSLT_TYPE_INFO, @ref CY_RSLT_TYPE_WARNING, + * @ref CY_RSLT_TYPE_ERROR, @ref CY_RSLT_TYPE_FATAL + * @param module Identifies the module where this result originated; see @ref anchor_modules "Modules". + * @param code a module-defined identifier to identify the specific situation that + * this result describes. + */ +#define CY_RSLT_CREATE(type, module, code) \ + ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ + (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ + (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) + +/** \} fields */ + +/** +* \{ +* @name Result Types +* Defines codes to identify the type of result. +*/ + +/** @brief The result code is informational-only */ +#define CY_RSLT_TYPE_INFO (0U) +/** @brief The result code is warning of a problem but will proceed */ +#define CY_RSLT_TYPE_WARNING (1U) +/** @brief The result code is an error */ +#define CY_RSLT_TYPE_ERROR (2U) +/** @brief The result code is a fatal error */ +#define CY_RSLT_TYPE_FATAL (3U) + +/** \} severity */ + +/** +* \{ +* @name Modules +* @anchor anchor_modules +* Defines codes to identify the module from which an error originated. +* For some large libraries, a range of module codes is defined here; +* see the library documentation for values corresponding to individual modules. +* Valid range is 0x0000-0x4000. +*/ +/**** DRIVER Module codes: 0x0000 - 0x00FF ****/ +/** Base module identifier for peripheral driver library drivers (0x0000 - 0x007F) */ +#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) +/** Base module identifier for wireless host driver library modules (0x0080 - 0x00FF) */ +#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) + +/** Deprecated. Use \ref CY_RSLT_MODULE_ABSTRACTION_HAL */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) +/** Module identifier for the Hardware Abstraction Layer */ +#define CY_RSLT_MODULE_ABSTRACTION_HAL (0x0100U) +/** Module identifier for board support package */ +#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) +/** Module identifier for file system abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) +/** Module identifier for resource abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) +/** Module identifier for rtos abstraction */ +#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) +/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ +#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) + +/** Base module identifier for Board Libraries (0x01A0 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_LIB_BASE (0x01A0U) +/** Module identifier for the Retarget IO Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RETARGET_IO (0x1A0U) +/** Module identifier for the RGB LED Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_RGB_LED (0x01A1U) +/** Module identifier for the Serial Flash Board Library */ +#define CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH (0x01A2U) +/** Module identifier for the WiFi Host Driver + Board Support Integration Library */ +#define CY_RSLT_MODULE_BOARD_LIB_WHD_INTEGRATION (0x01A3U) + +/** Base module identifier for Shield Board Libraries (0x01B8 - 0x01BF) */ +#define CY_RSLT_MODULE_BOARD_SHIELD_BASE (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-EPD */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_EPD (0x01B8U) +/** Module identifier for Shield Board CY8CKIT-028-TFT */ +#define CY_RSLT_MODULE_BOARD_SHIELD_028_TFT (0x01B9U) +/** Module identifier for Shield Board CY8CKIT-032 */ +#define CY_RSLT_MODULE_BOARD_SHIELD_032 (0x01BAU) + +/** Base module identifier for Board Hardware Libraries (0x01C0 - 0x01FF) */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BASE (0x01C0U) +/** Module identifier for the BMI160 Motion Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_BMI160 (0x01C0U) +/** Module identifier for the E2271CS021 E-Ink Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_E2271CS021 (0x01C1U) +/** Module identifier for the NTC GPIO Thermistor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_THERMISTOR (0x01C2U) +/** Module identifier for the SSD1306 OLED Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_SSD1306 (0x01C3U) +/** Module identifier for the ST7789V TFT Controller Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_ST7789V (0x01C4U) +/** Module identifier for the Light Sensor Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_LIGHT_SENSOR (0x01C5U) +/** Module identifier for the AK4954A Audio Codec Library */ +#define CY_RSLT_MODULE_BOARD_HARDWARE_AK4954A (0x01C6U) + +/** Base module identifier for Middleware Libraries (0x0200 - 0x02FF) */ +#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) + +/** \} modules */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_RESULT_H */ + +/** \} group_result */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h new file mode 100644 index 00000000000..e19ffc49f79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos.h @@ -0,0 +1,711 @@ +/***************************************************************************//** +* \file cyabs_rtos.h +* +* \brief +* Defines the Cypress RTOS Interface. Provides prototypes for functions that +* allow Cypress libraries to use RTOS resources such as threads, mutexes & +* timing functions in an abstract way. The APIs are implemented in the Port +* Layer RTOS interface which is specific to the RTOS in use. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef INCLUDED_CY_RTOS_INTERFACE_H_ +#define INCLUDED_CY_RTOS_INTERFACE_H_ + +#include "cyabs_rtos_impl.h" +#include "cy_result.h" +#include +#include +#include + +/** +* \defgroup group_abstraction_rtos_common Common + * General types and defines for working with the RTOS abstraction layer. +* \defgroup group_abstraction_rtos_mutex Mutex + * APIs for acquiring and working with Mutexes. +* \defgroup group_abstraction_rtos_queue Queue + * APIs for creating and working with Queues. +* \defgroup group_abstraction_rtos_semaphore Semaphore + * APIs for acquiring and working with Semaphores. +* \defgroup group_abstraction_rtos_threads Threads + * APIs for creating and working with Threads. +* \defgroup group_abstraction_rtos_time Time + * APIs for getting the current time and waiting. +* \defgroup group_abstraction_rtos_timer Timer + * APIs for creating and working with Timers. +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*********************************************** CONSTANTS **********************************************/ + +/** + * \ingroup group_abstraction_rtos_common + * \{ + */ + +#if defined(DOXYGEN) +//#include "Template/cyabs_rtos_impl.h" + +/** Return value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) +#endif + +/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ +#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) + +// +// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty +// queues), the these errors are listed here and the abstraction layer implementation must map from the +// underlying errors to these. If the errors are special cases, the the error \ref CY_RTOS_GENERAL_ERROR +// will be returned and \ref cy_rtos_last_error() can be used to retrieve the RTOS specific error message. +// +/** Requested operation did not complete in the specified time */ +#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) +/** The RTOS could not allocate memory for the specified operation */ +#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) +/** An error occured in the RTOS */ +#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) +/** A bad argument was passed into the APIs */ +#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) +/** A memory alignment issue was detected. Ensure memory provided is aligned per \ref CY_RTOS_ALIGNMENT_MASK */ +#define CY_RTOS_ALIGNMENT_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 6) + +/** \} group_abstraction_rtos_common */ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** The Queue is already full and can't accept any more items at this time */ +#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) +/** The Queue is empty and has nothing to remove */ +#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** TYPES **********************************************/ + +/** + * The state a thread can be in + * + * \ingroup group_abstraction_rtos_threads + */ +typedef enum cy_thread_state +{ + CY_THREAD_STATE_INACTIVE, /**< thread has not started or was terminated but not yet joined */ + CY_THREAD_STATE_READY, /**< thread can run, but is not currently */ + CY_THREAD_STATE_RUNNING, /**< thread is currently running */ + CY_THREAD_STATE_BLOCKED, /**< thread is blocked waiting for something */ + CY_THREAD_STATE_TERMINATED, /**< thread has terminated but not freed */ + CY_THREAD_STATE_UNKNOWN, /**< thread is in an unknown state */ +} cy_thread_state_t; + +/** + * The type of timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef enum cy_timer_trigger_type +{ + CY_TIMER_TYPE_PERIODIC, /**< called periodically until stopped */ + CY_TIMER_TYPE_ONCE, /**< called once only */ + cy_timer_type_periodic = CY_TIMER_TYPE_PERIODIC, /**< \deprecated replaced by \ref CY_TIMER_TYPE_PERIODIC */ + cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by \ref CY_TIMER_TYPE_ONCE */ +} cy_timer_trigger_type_t; + +/** + * The type of a function that is the entry point for a thread + * + * @param[in] arg the argument passed from the thread create call to the entry function + * + * \ingroup group_abstraction_rtos_threads + */ +typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg); + +/** + * The callback function to be called by a timer + * + * \ingroup group_abstraction_rtos_timer + */ +typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); + +/** + * Return the last error from the RTOS. + * + * The functions in the RTOS abstraction layer adhere to the Cypress return + * results calling convention. The underlying RTOS implementations will not but rather + * will have their own error code conventions. This function is provided as a service + * to the developer, mostly for debugging, and returns the underlying RTOS error code + * from the last RTOS abstraction layer that returned \ref CY_RTOS_GENERAL_ERROR. + * + * @return RTOS specific error code. + * + * \ingroup group_abstraction_rtos_common + */ +cy_rtos_error_t cy_rtos_last_error(); + +/*********************************************** Threads **********************************************/ + +/** + * \ingroup group_abstraction_rtos_threads + * \{ + */ + +/** Create a thread with specific thread argument. + * + * This function is called to startup a new thread. If the thread can exit, it must call + * \ref cy_rtos_exit_thread() just before doing so. All created threads that can terminate, either + * by themselves or forcefully by another thread MUST have \ref cy_rtos_join_thread() called on them + * by another thread in order to cleanup any resources that might have been allocated for them. + * + * @param[out] thread Pointer to a variable which will receive the new thread handle + * @param[in] entry_function Function pointer which points to the main function for the new thread + * @param[in] name String thread name used for a debugger + * @param[in] stack The buffer to use for the thread stack. This must be aligned to + * \ref CY_RTOS_ALIGNMENT_MASK with a size of at least \ref CY_RTOS_MIN_STACK_SIZE. + * If stack is null, cy_rtos_create_thread will allocate a stack from the heap. + * @param[in] stack_size The size of the thread stack in bytes + * @param[in] priority The priority of the thread. Values are operating system specific, but some + * common priority levels are defined: + * CY_THREAD_PRIORITY_LOW + * CY_THREAD_PRIORITY_NORMAL + * CY_THREAD_PRIORITY_HIGH + * @param[in] arg The argument to pass to the new thread + * + * @return The status of thread create request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg); + +/** Exit the current thread. + * + * This function is called just before a thread exits. In some cases it is sufficient + * for a thread to just return to exit, but in other cases, the RTOS must be explicitly + * signaled. In cases where a return is sufficient, this should be a null funcition. + * where the RTOS must be signaled, this function should perform that In cases operation. + * In code using RTOS services, this function should be placed at any at any location + * where the main thread function will return, exiting the thread. Threads that can + * exit must still be joined (\ref cy_rtos_join_thread) to ensure their resources are + * fully cleaned up. + * + * @return The status of thread exit request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_exit_thread(); + +/** Terminates another thread. + * + * This function is called to terminate another thread and reap the resources claimed + * by the thread. This should be called both when forcibly terminating another thread + * as well as any time a thread can exit on its own. For some RTOS implementations + * this is not required as the thread resources are claimed as soon as it exits. In + * other cases, this must be called to reclaim resources. Threads that are terminated + * must still be joined (\ref cy_rtos_join_thread) to ensure their resources are fully + * cleaned up. + * + * @param[in] thread Handle of the thread to terminate + * + * @returns The status of the thread terminate. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread); + +/** Waits for a thread to complete. + * + * This must be called on any thread that can complete to ensure that any resources that + * were allocated for it are cleaned up. + * + * @param[in] thread Handle of the thread to wait for + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); + +/** Checks if the thread is running + * + * This function is called to determine if a thread is actively running or not. For information on + * the thread state, use the \ref cy_rtos_get_thread_state() function. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] running Returns true if the thread is running, otherwise false + * + * @returns The status of the thread running check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running); + +/** Gets the state the thread is currently in + * + * This function is called to determine if a thread is running/blocked/inactive/ready etc. + * + * @param[in] thread Handle of the terminated thread to delete + * @param[out] state Returns the state the thread is currently in + * + * @returns The status of the thread state check. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state); + +/** Get current thread handle + * + * Returns the unique thread handle of the current running thread. + * + * @param[out] thread Handle of the current running thread + * + * @returns The status of thread join request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread); + +/** \} group_abstraction_rtos_threads */ + +/*********************************************** Mutexes **********************************************/ + +/** + * \ingroup group_abstraction_rtos_mutex + * \{ + */ + +/** Create a recursive mutex. + * + * Creates a binary mutex which can be used to synchronize between threads + * and between threads and ISRs. Created mutexes are recursive and support priority inheritance. + * + * This function has been replaced by \ref cy_rtos_init_mutex2 which allow for specifying + * whether or not the mutex supports recursion or not. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +#define cy_rtos_init_mutex(mutex) cy_rtos_init_mutex2(mutex, true) + +/** Create a mutex which can support recursion or not. + * + * Creates a binary mutex which can be used to synchronize between threads and between threads and + * ISRs. Created mutexes can support priority inheritance if recursive. + * + * \note Not all RTOS implementations support non-recursive mutexes. In this case a recursive + * mutex will be created. + * + * @param[out] mutex Pointer to the mutex handle to be initialized + * @param[in] recursive Should the created mutex support recursion or not + * + * @return The status of mutex creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive); + +/** Get a mutex. + * + * If the mutex is available, it is acquired and this function returned. + * If the mutex is not available, the thread waits until the mutex is available + * or until the timeout occurs. + * + * @note This function must not be called from an interrupt context as it may block. + * + * @param[in] mutex Pointer to the mutex handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the mutex. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. + * Must be zero if in_isr is true. + * + * @return The status of the get mutex. Returns timeout if mutex was not acquired + * before timeout_ms period. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms); + +/** Set a mutex. + * + * The mutex is released allowing any other threads waiting on the mutex to + * obtain the semaphore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status of the set mutex request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + * + */ +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); + +/** Deletes a mutex. + * + * This function frees the resources associated with a sempahore. + * + * @param[in] mutex Pointer to the mutex handle + * + * @return The status to the delete request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); + +/** \} group_abstraction_rtos_mutex */ + +/*********************************************** Semaphores **********************************************/ + +/** + * \ingroup group_abstraction_rtos_semaphore + * \{ + */ + +/** + * Create a semaphore + * + * This is basically a counting semaphore. + * + * @param[in,out] semaphore Pointer to the semaphore handle to be initialized + * @param[in] maxcount The maximum count for this semaphore + * @param[in] initcount The initial count for this semaphore + * + * @return The status of the semaphore creation. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount); + +/** + * Get/Acquire a semaphore + * + * If the semaphore count is zero, waits until the semaphore count is greater than zero. + * Once the semaphore count is greater than zero, this function decrements + * the count and return. It may also return if the timeout is exceeded. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get + * the semaphore. Use the \ref CY_RTOS_NEVER_TIMEOUT constant to wait forever. Must + * be zero is in_isr is true + * @param[in] in_isr true if we are trying to get the semaphore from with an ISR + * @return The status of get semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_TIMEOUT, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr); + +/** + * Set/Release a semaphore + * + * Increments the semaphore count, up to the maximum count for this semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[in] in_isr Value of true indicates calling from interrupt context + * Value of false indicates calling from normal thread context + * @return The status of set semaphore operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); + +/** + * Get the count of a semaphore. + * + * Gets the number of available tokens on the semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * @param[out] count Pointer to the return count + * @return The status of get semaphore count operation [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count); + +/** + * Deletes a semaphore + * + * This function frees the resources associated with a semaphore. + * + * @param[in] semaphore Pointer to the semaphore handle + * + * @return The status of semaphore deletion [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); + +/** \} group_abstraction_rtos_semaphore */ + +/*********************************************** Events **********************************************/ + +/** + * \ingroup group_abstraction_rtos_event + * \{ + */ + +/** Create an event. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. + * + * @param[in,out] event Pointer to the event handle to be initialized + * + * @return The status of the event initialization request. + * [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_event(cy_event_t *event); + +/** Set the event flag bits. + * + * This is an event which can be used to signal a set of threads + * with a 32 bit data element. Any threads waiting on this event are released + * + * @param[in] event Pointer to the event handle + * @param[in] bits The value of the 32 bit flags + * @param[in] in_isr If true, this is called from an ISR, otherwise from a thread + * + * @return The status of the set request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** + * Clear the event flag bits + * + * This function clears bits in the event. + * + * @param[in] event Pointer to the event handle + * @param[in] bits Any bits set in this value, will be cleared in the event. + * @param[in] in_isr if true, this is called from an ISR, otherwise from a thread + * + * @return The status of the clear flags request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ; + +/** Get the event bits. + * + * Returns the current bits for the event. + * + * @param[in] event Pointer to the event handle + * @param[out] bits pointer to receive the value of the event flags + * + * @return The status of the get request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits); + +/** Wait for the event and return bits. + * + * Waits for the event to be set and then returns the bits associated + * with the event, or waits for the given timeout period. + * @note This function returns if any bit in the set is set. + * + * @param[in] event Pointer to the event handle + * @param[in,out] bits pointer to receive the value of the event flags + * @param[in] clear if true, clear any bits set that cause the wait to return + * if false, do not clear bits + * @param[in] all if true, all bits in the initial bits value must be set to return + * if false, any one bit in the initial bits value must be set to return + * @param[in] timeout The amount of time to wait in milliseconds + * + * @return The status of the wait for event request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout); + +/** Deinitialize a event. + * + * This function frees the resources associated with an event. + * + * @param[in] event Pointer to the event handle + * + * @return The status of the deletion request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); + +/** \} group_abstraction_rtos_event */ + +/*********************************************** Queues **********************************************/ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + +/** Create a queue. + * + * This is a queue of data where entries are placed on the back of the queue + * and removed from the front of the queue. + * + * @param[out] queue Pointer to the queue handle + * @param[in] length The maximum length of the queue in items + * @param[in] itemsize The size of each item in the queue. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize); + +/** Put an item in a queue. + * + * This function puts an item in the queue. The item is copied + * into the queue using a memory copy and the data pointed to by item_ptr + * is no longer referenced once the call returns. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the item to place in the queue + * @param[in] timeout_ms The time to wait to place the item in the queue + * @param[in] in_isr If true this is being called from within and ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_FULL] + */ +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Gets an item in a queue. + * + * This function gets an item from the queue. The item is copied + * out of the queue into the memory provide by item_ptr. This space must be + * large enough to hold a queue entry as defined when the queue was initialized. + * + * @note If in_isr is true, timeout_ms must be zero. + * + * @param[in] queue Pointer to the queue handle + * @param[in] item_ptr Pointer to the memory for the item from the queue + * @param[in] timeout_ms The time to wait to get an item from the queue + * @param[in] in_isr If true this is being called from within an ISR + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_NO_MEMORY, \ref CY_RTOS_GENERAL_ERROR, \ref CY_RTOS_QUEUE_EMPTY] + */ +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr); + +/** Return the number of items in the queue. + * + * This function returns the number of items currently in the queue. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_waiting Pointer to the return count + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting); + +/** Return the amount of empty space in the queue. + * + * This function returns the amount of empty space in the + * queue. For instance, if the queue was created with 10 entries max and there + * are currently 2 entries in the queue, this will return 8. + * + * @param[in] queue Pointer to the queue handle + * @param[out] num_spaces Pointer to the return count. + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces); + +/** Reset the queue. + * + * This function sets the queue to empty. + * + * @param[in] queue pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); + +/** Deinitialize the queue handle. + * + * This function de-initializes the queue and returns all + * resources used by the queue. + * + * @param[in] queue Pointer to the queue handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); + +/** \} group_abstraction_rtos_queue */ + +/*********************************************** Timers **********************************************/ + +/** + * \ingroup group_abstraction_rtos_timer + * \{ + */ + +/** Create a new timer. + * + * This function initializes a timer object. + * @note The timer is not active until start is called. + * @note The callback may be (likely will be) called from a different thread. + * + * @param[out] timer Pointer to the timer handle to initialize + * @param[in] type Type of timer (periodic or once) + * @param[in] fun The function + * @param[in] arg Argument to pass along to the callback function + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg); + +/** Start a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[in] num_ms The number of milliseconds to wait before the timer fires + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms); + +/** Stop a timer. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer); + +/** Returns state of a timer. + * + * @param[in] timer Pointer to the timer handle + * @param[out] state Return value for state, true if running, false otherwise + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); + +/** Deinit the timer. + * + * This function deinitializes the timer and frees all consumed resources. + * + * @param[in] timer Pointer to the timer handle + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); + +/** \} group_abstraction_rtos_timer */ + +/*********************************************** Time **********************************************/ + +/** + * \ingroup group_abstraction_rtos_time + * \{ + */ + +/** Gets time in milliseconds since RTOS start. + * + * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds + * + * @param[out] tval Pointer to the struct to populate with the RTOS time + * + * @returns Time in milliseconds since the RTOS started. + */ +cy_rslt_t cy_rtos_get_time(cy_time_t *tval); + +/** Delay for a number of milliseconds. + * + * Processing of this function depends on the minimum sleep + * time resolution of the RTOS. The current thread should sleep for + * the longest period possible which is less than the delay required, + * then makes up the difference with a tight loop. + * + * @param[in] num_ms The number of milliseconds to delay for + * + * @return The status of the creation request. [\ref CY_RSLT_SUCCESS, \ref CY_RTOS_GENERAL_ERROR] + */ +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); + +/** \} group_abstraction_rtos_time */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h new file mode 100644 index 00000000000..8b36a68844a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_impl.h @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cyabs_rtos_impl.h +* +* \brief +* Internal definitions for RTOS abstraction layer +* +******************************************************************************** +* \copyright +* Copyright 2019-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + + +#ifndef INCLUDED_CYABS_RTOS_IMPL_H_ +#define INCLUDED_CYABS_RTOS_IMPL_H_ + +#include "cmsis_os2.h" +#include "rtx_os.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size in bytes */ +#define CY_RTOS_ALIGNMENT 0x00000008UL /** Minimum alignment for RTOS objects */ +#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Mask for checking the alignment of created RTOS objects */ + + +/****************************************************** +* Type Definitions +******************************************************/ + +/* RTOS thread priority */ +typedef enum +{ + CY_RTOS_PRIORITY_MIN = osPriorityNone, + CY_RTOS_PRIORITY_LOW = osPriorityLow, + CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal, + CY_RTOS_PRIORITY_NORMAL = osPriorityNormal, + CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal, + CY_RTOS_PRIORITY_HIGH = osPriorityHigh, + CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime, + CY_RTOS_PRIORITY_MAX = osPriorityRealtime7 +} cy_thread_priority_t ; + +typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */ +typedef void * cy_thread_arg_t; /** Argument passed to the entry function of a thread */ +typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */ +typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */ +typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */ +typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */ +typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */ +typedef void * cy_timer_callback_arg_t; /** Argument passed to the timer callback function */ +typedef uint32_t cy_time_t; /** Time in milliseconds */ +typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c new file mode 100644 index 00000000000..37c70fe5c74 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyabs_rtos_rtxv5.c @@ -0,0 +1,863 @@ +/***************************************************************************//** +* \file cyabs_rtos.c +* +* \brief +* Implementation for CMSIS RTOS v2 abstraction +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + + +/****************************************************** +* Error Converter +******************************************************/ + +/* Last received error status */ +static cy_rtos_error_t dbgErr; +cy_rtos_error_t cy_rtos_last_error() { return dbgErr; } + +/* Converts internal error type to external error type */ +static cy_rslt_t error_converter(cy_rtos_error_t internalError) +{ + cy_rslt_t value; + + switch (internalError) + { + case osOK: + value = CY_RSLT_SUCCESS; + break; + case osErrorTimeout: + value = CY_RTOS_TIMEOUT; + break; + case osErrorParameter: + value = CY_RTOS_BAD_PARAM; + break; + case osErrorNoMemory: + value = CY_RTOS_NO_MEMORY; + break; + case osError: + case osErrorResource: + case osErrorISR: + default: + value = CY_RTOS_GENERAL_ERROR; + break; + } + + /* Update the last known error status */ + dbgErr = internalError; + return value; +} + + +/****************************************************** +* Threads +******************************************************/ + +cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function, + const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + osThreadAttr_t attr; + + if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE) + status = CY_RTOS_BAD_PARAM; + else if (stack != NULL && (0 != (((uint32_t)stack) & CY_RTOS_ALIGNMENT_MASK))) + status = CY_RTOS_ALIGNMENT_ERROR; + else + { + attr.name = name; + attr.attr_bits = osThreadJoinable; + attr.cb_size = osRtxThreadCbSize; + attr.stack_size = stack_size; + attr.priority = (osPriority_t)priority; + attr.tz_module = 0; + attr.reserved = 0; + + /* Allocate stack if NULL was passed */ + if ((uint32_t *)stack == NULL) + { + /* Note: 1 malloc so that it can be freed with 1 call when terminating */ + uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK; + attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size); + if (attr.cb_mem != NULL) + attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad); + } + else + { + attr.cb_mem = malloc(osRtxThreadCbSize); + attr.stack_mem = stack; + } + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *thread = osThreadNew((osThreadFunc_t)entry_function, arg, &attr); + CY_ASSERT((*thread == attr.cb_mem) || (*thread == NULL)); + status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_exit_thread() +{ + /* This does not have a return statement because the osThreadExit() function + * does not return so the return statement would be unreachable and causes a + * warning for IAR compiler. + */ + osThreadExit(); +} + +cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadTerminate(*thread); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *running) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (running == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + *running = (osThreadGetState(*thread) == osThreadRunning) ? true : false; + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((thread == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + switch (osThreadGetState(*thread)) + { + case osThreadInactive: + *state = CY_THREAD_STATE_INACTIVE; + break; + case osThreadReady: + *state = CY_THREAD_STATE_READY; + break; + case osThreadRunning: + *state = CY_THREAD_STATE_RUNNING; + break; + case osThreadBlocked: + *state = CY_THREAD_STATE_BLOCKED; + break; + case osThreadTerminated: + *state = CY_THREAD_STATE_TERMINATED; + break; + case osThreadError: + case osThreadReserved: + default: + *state = CY_THREAD_STATE_UNKNOWN; + break; + } + } + + return status; +} + +cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osThreadJoin(*thread); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*thread); + *thread = NULL; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_thread_handle(cy_thread_t *thread) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if (thread == NULL) + status = CY_RTOS_BAD_PARAM; + else + *thread = osThreadGetId(); + + return status; +} + + +/****************************************************** +* Mutexes +******************************************************/ + +cy_rslt_t cy_rtos_init_mutex2(cy_mutex_t *mutex, bool recursive) +{ + cy_rslt_t status; + osMutexAttr_t attr; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = osMutexPrioInherit; + if (recursive) + { + attr.attr_bits |= osMutexRecursive; + } + attr.cb_mem = malloc(osRtxMutexCbSize); + attr.cb_size = osRtxMutexCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *mutex = osMutexNew(&attr); + CY_ASSERT((*mutex == attr.cb_mem) || (*mutex == NULL)); + status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexAcquire(*mutex, timeout_ms); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexRelease(*mutex); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (mutex == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMutexDelete(*mutex); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*mutex); + *mutex = NULL; + } + } + + return status; +} + + +/****************************************************** +* Semaphores +******************************************************/ + +cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount) +{ + cy_rslt_t status; + osSemaphoreAttr_t attr; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxSemaphoreCbSize); + attr.cb_size = osRtxSemaphoreCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *semaphore = osSemaphoreNew(maxcount, initcount, &attr); + CY_ASSERT((*semaphore == attr.cb_mem) || (*semaphore == NULL)); + status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreRelease(*semaphore); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_count_semaphore(cy_semaphore_t *semaphore, size_t *count) +{ + cy_rslt_t status; + if (semaphore == NULL || count == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + *count = osSemaphoreGetCount(*semaphore); + status = CY_RSLT_SUCCESS; + } + return status; +} + +cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (semaphore == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osSemaphoreDelete(*semaphore); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*semaphore); + *semaphore = NULL; + } + } + + return status; +} + + +/****************************************************** +* Events +******************************************************/ + +#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL +#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL + +cy_rslt_t cy_rtos_init_event(cy_event_t *event) +{ + cy_rslt_t status; + osEventFlagsAttr_t attr; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxEventFlagsCbSize); + attr.cb_size = osRtxEventFlagsCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *event = osEventFlagsNew(&attr); + CY_ASSERT((*event == attr.cb_mem) || (*event == NULL)); + status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsSet(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + (void)in_isr; // Unused parameter in this implementation + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = (osStatus_t)osEventFlagsClear(*event, bits); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL) + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *bits = osEventFlagsGet(*event); + + return status; +} + +cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + cy_rtos_error_t statusInternal; + uint32_t flagOption; + + if ((event == NULL) || (bits == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny; + if (!clear) + flagOption |= osFlagsNoClear; + + statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout); + if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL) + *bits = statusInternal; + else + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (event == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osEventFlagsDelete(*event); + status = error_converter(statusInternal); + if (status == CY_RSLT_SUCCESS) + { + free(*event); + *event = NULL; + } + } + + return status; +} + + +/****************************************************** +* Queues +******************************************************/ + +cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) +{ + cy_rslt_t status; + osMessageQueueAttr_t attr; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_size = osRtxMessageQueueCbSize; + uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t); + attr.mq_size = blockSize * length; + + /* Note: 1 malloc for both so that they can be freed with 1 call */ + uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07; + attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size); + if (attr.cb_mem != NULL) + attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad); + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + CY_ASSERT(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *queue = osMessageQueueNew(length, itemsize, &attr); + CY_ASSERT((*queue == attr.cb_mem) || (*queue == NULL)); + status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if ((queue == NULL) || (item_ptr == NULL)) + status = CY_RTOS_BAD_PARAM; + else + { + /* Not allowed to be called in ISR if timeout != 0 */ + if ((!in_isr) || (in_isr && (timeout_ms == 0U))) + statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms); + else + statusInternal = osErrorISR; + + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_waiting == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_waiting = osMessageQueueGetCount(*queue); + + return status; +} + +cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((queue == NULL) || (num_spaces == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *num_spaces = osMessageQueueGetSpace(*queue); + + return status; +} + +cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueReset(*queue); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (queue == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osMessageQueueDelete(*queue); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*queue); + *queue = NULL; + } + } + + return status; +} + + +/****************************************************** +* Timers +******************************************************/ + +cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type, + cy_timer_callback_t fun, cy_timer_callback_arg_t arg) +{ + cy_rslt_t status; + osTimerAttr_t attr; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + attr.name = NULL; + attr.attr_bits = 0U; + attr.cb_mem = malloc(osRtxTimerCbSize); + attr.cb_size = osRtxTimerCbSize; + + if (attr.cb_mem == NULL) + status = CY_RTOS_NO_MEMORY; + else + { + osTimerType_t osTriggerType = (CY_TIMER_TYPE_PERIODIC == type) + ? osTimerPeriodic + : osTimerOnce; + + CY_ASSERT(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL); + *timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr ); + CY_ASSERT((*timer == attr.cb_mem) || (*timer == NULL)); + status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS; + } + } + + return status; +} + +cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + uint32_t tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + { + uint32_t ticks = ((num_ms * tick_freq) / 1000); + statusInternal = osTimerStart(*timer, ticks); + status = error_converter(statusInternal); + } + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerStop(*timer); + status = error_converter(statusInternal); + } + + return status; +} + +cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + + if ((timer == NULL) || (state == NULL)) + status = CY_RTOS_BAD_PARAM; + else + *state = osTimerIsRunning(*timer); + + return status; +} + +cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + if (timer == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + statusInternal = osTimerDelete(*timer); + status = error_converter(statusInternal); + + if (status == CY_RSLT_SUCCESS) + { + free(*timer); + *timer = NULL; + } + } + + return status; +} + + +/****************************************************** +* Time +******************************************************/ + +cy_rslt_t cy_rtos_get_time(cy_time_t *tval) +{ + cy_rslt_t status = CY_RSLT_SUCCESS; + uint32_t tick_freq; + + if (tval == NULL) + status = CY_RTOS_BAD_PARAM; + else + { + /* Get Number of ticks per second */ + tick_freq = osKernelGetTickFreq(); + + /* Convert ticks count to time in milliseconds */ + if (tick_freq != 0) + *tval = (cy_time_t)((osKernelGetTickCount() * 1000LL) / tick_freq); + else + status = CY_RTOS_GENERAL_ERROR; + } + + return status; +} + +cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms) +{ + cy_rslt_t status; + cy_rtos_error_t statusInternal; + + statusInternal = osDelay(num_ms); + status = error_converter(statusInternal); + + return status; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h new file mode 100644 index 00000000000..08d4e5bfb13 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_gpio.h @@ -0,0 +1,247 @@ +/***************************************************************************//** +* \file cyhal_gpio.h +* +* \brief +* Provides a high level interface for interacting with the GPIO on Cypress devices. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_gpio GPIO (General Purpose Input Output) +* \ingroup group_hal +* \{ +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/******************************************************************************* +* Defines +*******************************************************************************/ + +/** Integer representation of no connect pin (required to exist in all BSPs) */ +#define CYHAL_NC_PIN_VALUE (NC) + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Pin events */ +typedef enum { + CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */ + CYHAL_GPIO_IRQ_RISE = 1 << 0, /**< Interrupt on rising edge */ + CYHAL_GPIO_IRQ_FALL = 1 << 1, /**< Interrupt on falling edge */ + CYHAL_GPIO_IRQ_BOTH = (CYHAL_GPIO_IRQ_RISE | CYHAL_GPIO_IRQ_FALL), /**< Interrupt on both rising and falling edges */ +} cyhal_gpio_event_t; + +/** Pin direction */ +typedef enum { + CYHAL_GPIO_DIR_INPUT, /**< Input pin */ + CYHAL_GPIO_DIR_OUTPUT, /**< Output pin */ + CYHAL_GPIO_DIR_BIDIRECTIONAL, /**< Input and output pin */ +} cyhal_gpio_direction_t; + +/** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ +typedef enum { + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z. Input only. Input init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z. Use only for analog purpose */ + CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW, /**< Open-drain, Drives Low. Input and output. Input init value(s): 1, output value(s): 0 */ + CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH, /**< Open-drain, Drives High. Input and output. Input init value(s): 0, output value(s): 1 */ + CYHAL_GPIO_DRIVE_STRONG, /**< Strong output. Output only. Output init value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ + CYHAL_GPIO_DRIVE_PULL_NONE, /**< No Pull-up or pull-down resistors. Input and output. Input init value(s): 0 or 1, output value(s): 0 or 1 */ +} cyhal_gpio_drive_mode_t; + +/** GPIO callback function type */ +typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); + +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin + * + * @return The status of the init request + * + * Guidance for using gpio drive modes ( \ref cyhal_gpio_drive_mode_t for details). + * For default use drive modes: + * Input GPIO direction - \ref CYHAL_GPIO_DRIVE_NONE + * Output GPIO direction - \ref CYHAL_GPIO_DRIVE_STRONG + * Bidirectional GPIO - \ref CYHAL_GPIO_DRIVE_PULLUPDOWN + * \warning Don't use \ref CYHAL_GPIO_DRIVE_STRONG for input GPIO direction. It may cause an overcurrent issue. + */ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); + +/** Uninitialize the gpio peripheral and the cyhal_gpio_t object + * + * @param[in] pin Pin number + */ +void cyhal_gpio_free(cyhal_gpio_t pin); + +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. + * + * @param[in] pin The GPIO pin + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * + * @return The status of the configure request + */ +cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode); + +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. + * + * @param[in] pin The GPIO object + * @param[in] value The value to be set (high = true, low = false) + */ +void cyhal_gpio_write(cyhal_gpio_t pin, bool value); + +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. + * + * @param[in] pin The GPIO object + * @return The value of the IO (true = high, false = low) + */ +bool cyhal_gpio_read(cyhal_gpio_t pin); + +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. + * @param[in] pin The GPIO object + */ +void cyhal_gpio_toggle(cyhal_gpio_t pin); + +/** Register/clear a callback handler for pin events
+ * + * This function will be called when one of the events enabled by \ref cyhal_gpio_enable_event occurs. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The pin number + * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. + * @param[in] callback_arg Generic argument that will be provided to the callback when called, can be NULL + */ +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); + +/** Enable or Disable the specified GPIO event
+ * + * When an enabled event occurs, the function specified by \ref cyhal_gpio_register_callback will be called. + * + * See \ref subsection_gpio_snippet_4. + * + * @param[in] pin The GPIO object + * @param[in] event The GPIO event + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_gpio_register_irq(pin, priority, handler, handler_arg) cyhal_gpio_register_callback(pin, handler, handler_arg) +#define cyhal_gpio_irq_enable(pin, event, enable) cyhal_gpio_enable_event(pin, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_gpio_event_t cyhal_gpio_irq_event_t; +/** \endcond */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#ifdef CYHAL_GPIO_IMPL_HEADER +#include CYHAL_GPIO_IMPL_HEADER +#endif /* CYHAL_GPIO_IMPL_HEADER */ + +/** \} group_hal_gpio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h new file mode 100644 index 00000000000..d5600efd997 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_sdio.h @@ -0,0 +1,366 @@ +/***************************************************************************//** +* \file cyhal_sdio.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SDIO interface. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) +* \ingroup group_hal +* \{ +* High level interface to the Secure Digital Input Output (SDIO). +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in \ref cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). +* +* The SDIO protocol is an extension of the SD +* interface for general I/O functions. Refer to the SD Specifications Part 1 SDIO +* Specifications Version 4.10 for more information on the SDIO protocol and specifications. +* +* +* \section subsection_sdio_features Features +* * Supports 4-bit interface +* * Supports Ultra High Speed (UHS-I) mode +* * Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes +* * Supports SDIO card interrupts in both 1-bit and 4-bit modes +* * Supports Standard capacity (SDSC), High capacity (SDHC) and Extended capacity (SDXC) memory +* +* \section subsection_sdio_quickstart Quick Start +* +* \ref cyhal_sdio_init initializes the SDIO peripheral and passes a pointer to the SDIO block through the **obj** object of type \ref cyhal_sdio_t. +* +* \section subsection_sdio_code_snippets Code Snippets +* +* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example +* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration +* +* \snippet sdio.c snippet_cyhal_sdio_simple_init +* +* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt +* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events. +* +* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback +* +* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands +* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands. +* +* \snippet sdio.c snippet_cyhal_sdio_send_command +* +* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer +* The following snippet shows how to start a bulk data transfer. +* +* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer +* +* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer +* +* The following snippet shows how to start an async data transfer. +* \snippet sdio.c snippet_cyhal_sdio_async_transfer +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Defines +*******************************************************************************/ + +#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ +#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ +#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ +#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/ +#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/ +#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/ +#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/ +#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/ + +#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */ +#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */ +#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */ +#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */ +#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */ +#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/ + +/* HAL return value defines */ + +/** \addtogroup group_hal_results_sdio SDIO HAL Results + * SDIO specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Incorrect parameter value define */ +#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT)) +/** Clock initialization error define */ +#define CYHAL_SDIO_RSLT_ERR_CLOCK \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR)) +/** Semaphore not initiated error define */ +#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED)) +/** Error define based on SDIO lower function return value */ +#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal))) +/** Define to indicate canceled operation */ +#define CYHAL_SDIO_RSLT_CANCELED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED)) +/** Transfers are not allowed after the SDIO block has allowed power mode transition. */ +#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR)) + +/** + * \} + */ + + +/******************************************************************************* +* Enumerations +*******************************************************************************/ + +/** Commands that can be issued */ +typedef enum +{ + CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!< Go to idle state + CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!< Send a relative address + CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!< Send an OP IO + CYHAL_SDIO_CMD_SELECT_CARD = 7, //!< Send a card select + CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!< Go to inactive state + CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!< Perform a direct read/write + CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!< Perform an extended read/write +} cyhal_sdio_command_t; + +/** Types of transfer that can be performed */ +typedef enum +{ + CYHAL_READ, //!< Read from the card + CYHAL_WRITE //!< Write to the card +} cyhal_transfer_t; + +/** Types of events that could be asserted by SDIO */ +typedef enum { + /* Interrupt-based thread events */ + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!< Command Complete + CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete + CYHAL_SDIO_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped + CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer + CYHAL_SDIO_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1 + CYHAL_SDIO_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1 + CYHAL_SDIO_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State + CYHAL_SDIO_CARD_INTERRUPT = 0x00100, //!< The synchronized value of the DAT[1] interrupt input for SD mode + CYHAL_SDIO_INT_A = 0x00200, //!< Reserved: set to 0 + CYHAL_SDIO_INT_B = 0x00400, //!< Reserved: set to 0 + CYHAL_SDIO_INT_C = 0x00800, //!< Reserved: set to 0 + CYHAL_SDIO_RE_TUNE_EVENT = 0x01000, //!< Reserved: set to 0 + CYHAL_SDIO_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1 + CYHAL_SDIO_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred + CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set + + /* Non-interrupt-based thread events */ + CYHAL_SDIO_GOING_DOWN = 0x10000, //!< The interface is going away (eg: powering down for some period of time) + CYHAL_SDIO_COMING_UP = 0x20000, //!< The interface is back up (eg: came back from a low power state) + + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!< Is used to enable/disable all interrupts events +} cyhal_sdio_event_t; + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ + +/** @brief SDIO controller initial configuration */ +typedef struct +{ + uint32_t frequencyhal_hz; //!< Clock frequency, in hertz + uint16_t block_size; //!< Block size +} cyhal_sdio_cfg_t; + +/** Callback for SDIO events */ +typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); + + +/******************************************************************************* +* Data Structures +*******************************************************************************/ +/** Initialize the SDIO peripheral + * + * @param[out] obj Pointer to an SDIO object. + * The caller must allocate the memory for this object but the init + * function will initialize its contents. + * @param[out] clk The pin connected to the clk signal + * @param[in] cmd The pin connected to the command signal + * @param[in] data0 The pin connected to the data0 signal + * @param[in] data1 The pin connected to the data1 signal + * @param[in] data2 The pin connected to the data2 signal + * @param[in] data3 The pin connected to the data3 signal + * @return The status of the init request + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_1 for more information. + */ +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3); + +/** Release the SDIO block. + * + * @param[in,out] obj The SDIO object + */ +void cyhal_sdio_free(cyhal_sdio_t *obj); + +/** Configure the SDIO block with required parameters. Refer \ref cyhal_sdio_cfg_t for more information. + * + * @param[in,out] obj The SDIO object + * @param[in] config The SDIO configuration to apply + * @return The status of the configure request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config); + +/** Sends command to the SDIO device. See \ref cyhal_sdio_command_t for list of available commands. + * + * This will block until the command is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] command The command to send to the SDIO device + * @param[in] argument The argument to the command + * @param[out] response The response from the SDIO device + * @return The status of the command transfer. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_3 for more information. + */ +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response); + +/** Performs a bulk data transfer. Sends \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command (CMD=53) which allows writing and reading of a large number of I/O registers with a single command. + * + * This will block until the transfer is completed. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. + * @param[in] length The number of bytes to send + * @param[out] response The response from the SDIO device + * @return The status of the bulk transfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_4 for more information. + */ +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response); + +/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block. + * After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted. + * + * To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy() + * until it returns false. + * The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled + * after the asynchronous transfer is complete and in the condition they were + * enabled in before the transfer operation started. Handle these events in the interrupt callback. + * + * When the transfer is complete, the \ref CYHAL_SDIO_XFER_COMPLETE event will be raised. + * See \ref cyhal_sdio_register_callback and \ref cyhal_sdio_enable_event. + * + * @param[in,out] obj The SDIO object + * @param[in] direction The direction of transfer (read/write) + * @param[in] argument The argument to the command + * @param[in] data The data to send to the SDIO device + * @param[in] length The number of bytes to send + * @return The status of the async tranfer operation. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. Refer \ref subsection_sdio_use_case_5 for more information. + */ +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length); + +/** Checks if the specified SDIO is in use + * + * @param[in] obj The SDIO peripheral to check + * @return true if SDIO is in use. false, otherwise. + */ +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj); + +/** Abort an SDIO transfer + * + * @param[in] obj The SDIO peripheral to stop + * @return The status of the abort_async request. + * + * Returns \ref CY_RSLT_SUCCESS on successful operation. + */ +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj); + +/** Register an SDIO event callback to be invoked when the event is triggered. + * + * This function will be called when one of the events enabled by \ref cyhal_sdio_enable_event occurs. + * + * @param[in] obj The SDIO object + * @param[in] callback The callback function which will be invoked when the event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when executed + * + * Refer \ref subsection_sdio_use_case_2 for more implementation. + */ +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t callback, void *callback_arg); + +/** Enables callbacks to be triggered for specified SDIO events. Refer \ref cyhal_sdio_event_t for all events. + * + * @param[in] obj The SDIO object + * @param[in] event The SDIO event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable Set to true to enable events, or false to disable them + * + * Refer \ref subsection_sdio_use_case_2 for more information. + */ +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +#define cyhal_sdio_register_irq cyhal_sdio_register_callback +#define cyhal_sdio_irq_enable(obj, event, enable) cyhal_sdio_enable_event(obj, event, CYHAL_ISR_PRIORITY_DEFAULT, enable) +typedef cyhal_sdio_event_t cyhal_sdio_irq_event_t; +typedef cyhal_sdio_event_callback_t cyhal_sdio_irq_handler_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SDIO_IMPL_HEADER +#include CYHAL_SDIO_IMPL_HEADER +#endif /* CYHAL_SDIO_IMPL_HEADER */ + +/** \} group_hal_sdio */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h new file mode 100644 index 00000000000..f5ba47669f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/interface/cyhal_spi.h @@ -0,0 +1,383 @@ +/***************************************************************************//** +* \file cyhal_spi.h +* +* \brief +* Provides a high level interface for interacting with the Cypress SPI. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_spi SPI (Serial Peripheral Interface) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. +* +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_results_spi SPI HAL Results + * SPI specific return codes + * \ingroup group_hal_results + * \{ *//** + */ + +/** Bad argument */ +#define CYHAL_SPI_RSLT_BAD_ARGUMENT \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) +/** Failed to initialize SPI clock */ +#define CYHAL_SPI_RSLT_CLOCK_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1)) +/** Failed to Transfer SPI data */ +#define CYHAL_SPI_RSLT_TRANSFER_ERROR \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2)) +/** Provided clock is not supported by SPI */ +#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5)) +/** Provided PIN configuration is not supported by SPI */ +#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6)) +/** The requested resource type is invalid */ +#define CYHAL_SPI_RSLT_ERR_INVALID_PIN \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) +/** Cannot configure SSEL signal */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_CONFIG_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 8)) +/** Cannot switch SSEL - device is busy or incorrect pin provided */ +#define CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL \ + (CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 9)) + +/** + * \} + */ + +/** Compatibility define for cyhal_spi_set_frequency. */ +#define cyhal_spi_frequency cyhal_spi_set_frequency + +/** SPI interrupt triggers */ +typedef enum { + /** All transfer data has been moved into data FIFO */ + CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1, + /** Transfer complete. */ + CYHAL_SPI_IRQ_DONE = 1 << 2, + /** An error occurred while transferring data */ + CYHAL_SPI_IRQ_ERROR = 1 << 3, +} cyhal_spi_event_t; + +/** SPI Slave Select polarity */ +typedef enum { + /** SSEL signal is active low */ + CYHAL_SPI_SSEL_ACTIVE_LOW = 0, + /** SSEL signal is active high */ + CYHAL_SPI_SSEL_ACTIVE_HIGH = 1, +} cyhal_spi_ssel_polarity_t; + +/** Handler for SPI interrupts */ +typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event); + +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the LSB is sent first. */ +#define CYHAL_SPI_MODE_FLAG_LSB (0x01u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPHA=1. */ +#define CYHAL_SPI_MODE_FLAG_CPHA (0x02u) +/** Flag for SPI \ref cyhal_spi_mode_t values indicating that the CPOL=1. */ +#define CYHAL_SPI_MODE_FLAG_CPOL (0x04u) +/** Creates a \ref cyhal_spi_mode_t value given the cpol, cpha, lsb values. */ +#define CYHAL_SPI_MODE(cpol, cpha, lsb) (((cpol > 0) ? CYHAL_SPI_MODE_FLAG_CPOL : 0) | \ + ((cpha > 0) ? CYHAL_SPI_MODE_FLAG_CPHA : 0) | \ + (( lsb > 0) ? CYHAL_SPI_MODE_FLAG_LSB : 0)) + +/** SPI operating modes */ +typedef enum +{ + /** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_00_MSB = CYHAL_SPI_MODE(0, 0, 0), + /** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_00_LSB = CYHAL_SPI_MODE(0, 0, 1), + /** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_01_MSB = CYHAL_SPI_MODE(0, 1, 0), + /** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_01_LSB = CYHAL_SPI_MODE(0, 1, 1), + /** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */ + CYHAL_SPI_MODE_10_MSB = CYHAL_SPI_MODE(1, 0, 0), + /** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */ + CYHAL_SPI_MODE_10_LSB = CYHAL_SPI_MODE(1, 0, 1), + /** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */ + CYHAL_SPI_MODE_11_MSB = CYHAL_SPI_MODE(1, 1, 0), + /** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */ + CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1), +} cyhal_spi_mode_t; + +/** @brief Initial SPI configuration. */ +typedef struct +{ + cyhal_spi_mode_t mode; //!< The operating mode + uint8_t data_bits; //!< The number of bits per transfer + bool is_slave; //!< Whether the peripheral is operating as slave or master +} cyhal_spi_cfg_t; + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj Pointer to a SPI object. The caller must allocate the memory + * for this object but the init function will initialize its contents. + * @param[in] mosi The pin to use for MOSI + * @note At least MOSI or MISO pin should be non-NC + * @param[in] miso The pin to use for MISO + * @note At least MOSI or MISO pin should be non-NC + * @param[in] sclk The pin to use for SCLK + * @note This pin cannot be NC + * @param[in] ssel The pin to use for SSEL + * @note Provided pin will be configured for \ref CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed + * (as well as additional ssel pins can be added) by \ref cyhal_spi_slave_select_config and \ref cyhal_spi_select_active_ssel + * functions. This pin can be NC. + * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[in] bits The number of bits per frame + * @note bits should be 8 or 16 + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] is_slave false for master mode or true for slave mode operation + * @return The status of the init request + */ +cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, + const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave); + +/** Release a SPI object + * + * Return the peripheral, pins and clock owned by the SPI object to their reset state + * @param[in,out] obj The SPI object to deinitialize + */ +void cyhal_spi_free(cyhal_spi_t *obj); + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + * @return The status of the set_frequency request + */ +cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz); + +/** Configures provided ssel pin to work as SPI slave select with specified polarity. + * + * Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching + * between configured slave select pins is done by \ref cyhal_spi_select_active_ssel function. + * Unless modified with this function, the SSEL pin provided as part of \ref cyhal_spi_init is the default. + * @param[in] obj The SPI object to add slave select for + * @param[in] ssel Slave select pin to be added + * @param[in] polarity Polarity of slave select + * @return The status of ssel pin configuration + */ +cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity); + +/** Selects an active slave select line from one of available. + * + * This function is applicable for the master and slave. + * SSEL pin should be configured by \ref cyhal_spi_slave_select_config or \ref cyhal_spi_init functions prior + * to selecting it as active. The active slave select line will automatically be toggled as part of any transfer. + * @param[in] obj The SPI object for switching + * @param[in] ssel Slave select pin to be set as active + * @return CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL + */ +cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel); + +/** Synchronously get a received value out of the SPI receive buffer + * + * In Master mode - transmits fill-in value and read the data from RxFifo + * In Slave mode - Blocks until a value is available + * + * @param[in] obj The SPI peripheral to read + * @param[in] value The value received + * @return The status of the read request + * @note + * - In Master mode, MISO pin required to be non-NC for this API to operate + * - In Slave mode, MOSI pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t* value); + +/** Synchronously send a byte out + * + * In Master mode transmits value to slave and read/drop a value from the RxFifo. + * In Slave mode writes a value to TxFifo + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return The status of the write request + * @note + * - In Master mode, MOSI pin required to be non-NC for this API to operate + * - In Slave mode, MISO pin required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value); + +/** Synchronously Write a block out and receive a value + * + * The total number of bytes sent and received will be the maximum of tx_length + * and rx_length. The bytes written will be padded (at the end) with the value + * given by write_fill. + * + * This function will block for the duration of the transfer. \ref cyhal_spi_transfer_async + * can be used for non-blocking transfers. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx Pointer to the byte-array of data to write to the device + * @param[in,out] tx_length Number of bytes to write, updated with the number actually written + * @param[out] rx Pointer to the byte-array of data to read from the device + * @param[in,out] rx_length Number of bytes to read, updated with the number actually read + * @param[in] write_fill Default data transmitted while performing a read + * @return The status of the transfer request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill); + +/** Start an asynchronous SPI transfer. + * + * This will transfer `rx_length` bytes into the buffer pointed to by `rx`, while simultaneously transfering + * `tx_length` bytes of data from the buffer pointed to by `tx`, both in the background. + * When the transfer is complete, the @ref CYHAL_SPI_IRQ_DONE event will be raised. + * See @ref cyhal_spi_register_callback and @ref cyhal_spi_enable_event. + * \note For blocking transfers cyhal_spi_transfer can be used. + * + * @param[in] obj The SPI object that holds the transfer information + * @param[in] tx The transmit buffer + * @param[in,out] tx_length The number of bytes to transmit + * @param[out] rx The receive buffer + * @param[in,out] rx_length The number of bytes to receive + * @return The status of the transfer_async request + * @note Both MOSI and MISO pins required to be non-NC for this API to operate + */ +cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length); + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return Indication of whether the SPI is still transmitting + */ +bool cyhal_spi_is_busy(cyhal_spi_t *obj); + +/** Abort an SPI transfer + * + * @param[in] obj The SPI peripheral to stop + * @return The status of the abort_async request + */ +cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj); + +/** Register a SPI callback handler + * + * This function will be called when one of the events enabled by \ref cyhal_spi_enable_event occurs. + * + * @param[in] obj The SPI object + * @param[in] callback The callback handler which will be invoked when the interrupt fires + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg); + +/** Configure SPI interrupt. This function is used for word-approach + * + * When an enabled event occurs, the function specified by \ref cyhal_spi_register_callback will be called. + * + * @param[in] obj The SPI object + * @param[in] event The SPI event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable); + +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ +/** \cond INTERNAL */ +typedef cyhal_spi_event_t cyhal_spi_irq_event_t; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_SPI_IMPL_HEADER +#include CYHAL_SPI_IMPL_HEADER +#endif /* CYHAL_SPI_IMPL_HEADER */ + +/** \} group_hal_spi */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c new file mode 100644 index 00000000000..f5a0716697c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_hal.c @@ -0,0 +1,63 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "cyhal.h" +#include "mbed_thread.h" +#include "mbed_wait_api.h" + +static cyhal_sdio_t sdio_obj; + +/* Edit Pin configuration */ +const pinconfig_t PinConfig[] = { + + [CYBSP_WIFI_WL_REG_ON] = WIFI_WL_REG_ON, +#ifdef CYBSP_WIFI_32K_CLK + [CYBSP_WIFI_32K_CLK] = WIFI_32K_CLK, +#endif /* CYBSP_WIFI_32K_CLK */ + [CYBSP_LED1 ] = BSP_LED1, + [CYBSP_LED2 ] = BSP_LED2, + [CYBSP_WIFI_SDIO_CMD] = WIFI_SDIO_CMD, + [CYBSP_WIFI_SDIO_CLK] = WIFI_SDIO_CLK, + [CYBSP_WIFI_SDIO_D0 ] = WIFI_SDIO_D0, + [CYBSP_WIFI_SDIO_D1 ] = WIFI_SDIO_D1, + [CYBSP_WIFI_SDIO_D2 ] = WIFI_SDIO_D2, + [CYBSP_WIFI_SDIO_D3 ] = WIFI_SDIO_D3, + [CYBSP_SDIO_OOB_IRQ ] = WIFI_SDIO_OOB_IRQ //VIKR +}; + +void Cy_SysLib_Delay(uint32_t milliseconds) +{ + thread_sleep_for(milliseconds); +} + +void Cy_SysLib_DelayUs(uint16_t microseconds) +{ + wait_us(microseconds); +} + +void cyhal_system_delay_ms(uint32_t milliseconds) +{ + Cy_SysLib_Delay(milliseconds); +} + +cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h new file mode 100644 index 00000000000..7671d853cfc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_syslib.h @@ -0,0 +1,592 @@ +/***************************************************************************//** +* \file cy_syslib.h +* \version 2.40.1 +* +* Provides an API declaration of the SysLib driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_syslib +* \{ +* The system libraries provide APIs that can be called in the user application +* to handle the timing, logical checking or register. +* +* The functions and other declarations used in this driver are in cy_syslib.h. +* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* and declarations in the PDL. +* +* The SysLib driver contains a set of different system functions. These functions +* can be called in the application routine. Major features of the system library: +* * Delay functions +* * The register Read/Write macro +* * Assert and Halt +* * Assert Classes and Levels +* * A software reset +* * Reading the reset cause +* * An API to invalidate the flash cache and buffer +* * Data manipulation macro +* * A variable type definition from MISRA-C which specifies signedness +* * Cross compiler compatible attributes +* * Getting a silicon-unique ID API +* * Setting wait states API +* * Resetting the backup domain API +* * APIs to serve Fault handler +* +* \section group_syslib_configuration Configuration Considerations +* Assertion Usage
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the +* program is running correctly. It is a convenient way to insert sanity checks. +* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of +* the PDL library. The behavior of the macro is as follows: if the expression +* passed to the macro is false, output an error message that includes the file +* name and line number, and then halts the CPU. \n +* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function. +* This is a weakly linked function. The default implementation stores the file +* name and line number of the ASSERT into global variables, cy_assertFileName +* and cy_assertLine . It then calls the Cy_SysLib_Halt() function. +* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing. +* +* The PDL source code uses this assert mechanism extensively. It is recommended +* that you enable asserts when debugging firmware. \n +* Assertion Classes and Levels
+* The PDL defines three assert classes, which correspond to different kinds +* of parameters. There is a corresponding assert "level" for each class. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Class MacroLevel MacroType of check
CY_ASSERT_CLASS_1CY_ASSERT_L1A parameter that could change between different PSoC devices +* (e.g. the number of clock paths)
CY_ASSERT_CLASS_2CY_ASSERT_L2A parameter that has fixed limits such as a counter period
CY_ASSERT_CLASS_3CY_ASSERT_L3A parameter that is an enum constant
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL. +* This is a compiler command line argument, similar to how the DEBUG / NDEBUG +* macro is passed. \n +* Enabling any class also enables any lower-numbered class. +* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three +* classes. The following example shows the command-line option to enable all +* the assert levels: +* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode +* \note The use of special characters, such as spaces, parenthesis, etc. must +* be protected with quotes. +* +* After CY_ASSERT_LEVEL is defined, firmware can use +* one of the three level macros to make an assertion. For example, if the +* parameter can vary between devices, firmware uses the L1 macro. +* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode +* If the parameter has bounds, firmware uses L2. +* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode +* If the parameter is an enum, firmware uses L3. +* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode +* Each check uses the appropriate level macro for the kind of parameter being checked. +* If a particular assert class/level is not enabled, then the assert does nothing. +* +* \section group_syslib_more_information More Information +* Refer to the technical reference manual (TRM). +* +* \section group_syslib_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance shall be placed on undefined or unspecified behaviour.This specific behavior is explicitly covered in rule 20.1.
2.1RThis function contains a mixture of in-line assembler statements and C statements.This si required by design of the Cy_SysLib_Halt function.
18.4RUnions shall not be used.The unions are used for CFSR, HFSR and SHCSR Fault Status Registers +* content access as a word in code and as a structure during debug.
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
20.1RReserved identifiers, macros and functions in the standard library, shall not be +* defined, redefined or undefined.The driver defines the macros with leading underscores +* (_CLR_SET_FLD/_BOOL2FLD/_FLD2BOOL) and therefore generates this MISRA violation.
+* +* \section group_syslib_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.40.1Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.Removed the IAR compiler warning.
2.40Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.Improve PDL code base.
2.30Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.Provided support for the ARM Compiler 6.
Minor documentation edits.Documentation update and clarification.
Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.Improve user experience.
2.20Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.Provided support for the PDL static library in Release mode.
Minor documentation edits.Documentation update and clarification.
2.10Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added the following macros: \ref CY_REG32_CLR_SET, \ref _CLR_SET_FLD16U, \ref CY_REG16_CLR_SET, \ref _CLR_SET_FLD8U, \ref CY_REG8_CLR_SETRegister access simplification.
Removed the Cy_SysLib_GetNumHfclkResetCause API function.This feature is not supported by SRSS_ver1.
Added register access layer. Use register access macros instead +* of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* not need to be recompiled for each supported part number.
2.0.1Minor documentation editsDocumentation update and clarification
2.0 +* Added Cy_SysLib_ResetBackupDomain() API implementation. \n +* Added CY_NOINLINE attribute implementation. \n +* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n +* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n +* Optimized Cy_SysLib_SetWaitStates() API implementation. +* Improvements made based on usability feedback.
Added Assertion Classes and Levels.For error checking, parameter validation and status returns in the PDL API.
Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.To store debug information into a non-zero init area for future analysis.
Removed CY_WEAK attribute implementation.CMSIS __WEAK attribute should be used instead.
1.0Initial version
+* +* \defgroup group_syslib_macros Macros +* \defgroup group_syslib_functions Functions +* \defgroup group_syslib_data_structures Data Structures +* \defgroup group_syslib_enumerated_types Enumerated Types +* +*/ + +#if !defined(CY_SYSLIB_H) +#define CY_SYSLIB_H + +#include +#include + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/** Get the lower 8 bits of a 16-bit value. */ +#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU)) +/** Get the upper 8 bits of a 16-bit value. */ +#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U)) + +/** Get the lower 16 bits of a 32-bit value. */ +#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU)) +/** Get the upper 16 bits of a 32-bit value. */ +#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U)) + +/** Swap the byte ordering of a 16-bit value */ +#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU))) + +/** Swap the byte ordering of a 32-bit value */ +#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \ + (((x) & 0x0000FF00U) << 8U) | ((x) << 24U))) + +/** Swap the byte ordering of a 64-bit value */ +#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \ + CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U)))) + +/* MISRA rule 6.3 recommends using specific-length typedef for the basic + * numerical types of signed and unsigned variants of char, float, and double. + */ +typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ +typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ +typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ + + +/******************************************************************************* +* Macro Name: CY_GET_REG8(addr) +****************************************************************************//** +* +* Reads the 8-bit value from the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG8(addr, value) +****************************************************************************//** +* +* Writes an 8-bit value to the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG16(addr) +****************************************************************************//** +* +* Reads the 16-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG16(addr, value) +****************************************************************************//** +* +* Writes the 16-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG24(addr) +****************************************************************************//** +* +* Reads the 24-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG24(addr) (((uint32_t) (*((const volatile uint8_t *)(addr)))) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 1))) << 8U) | \ + (((uint32_t) (*((const volatile uint8_t *)(addr) + 2))) << 16U)) + + +/******************************************************************************* +* Macro Name: CY_SET_REG24(addr, value) +****************************************************************************//** +* +* Writes the 24-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG24(addr, value) do \ + { \ + (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ + (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \ + (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \ + } \ + while(0) + + +/******************************************************************************* +* Macro Name: CY_GET_REG32(addr) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG32(addr, value) +****************************************************************************//** +* +* Writes the 32-bit value to the specified register. The address is the little +* endian order (LSB in lowest address). +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD32U +****************************************************************************//** +* +* The macro for setting a register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the register. +* +*******************************************************************************/ +#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) + + +/******************************************************************************* +* Macro Name: CY_REG32_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 32-bit register. +* +*******************************************************************************/ +#define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD16U +****************************************************************************//** +* +* The macro for setting a 16-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 16-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD16U(reg, field, value) ((uint16_t)(((reg) & ((uint16_t)(~(field ## _Msk)))) | \ + ((uint16_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG16_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD16U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 16-bit register. +* +*******************************************************************************/ +#define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD8U +****************************************************************************//** +* +* The macro for setting a 8-bit register with a name field and value for providing +* get-clear-modify-write operations. +* Returns a resulting value to be assigned to the 8-bit register. +* +*******************************************************************************/ +#define _CLR_SET_FLD8U(reg, field, value) ((uint8_t)(((reg) & ((uint8_t)(~(field ## _Msk)))) | \ + ((uint8_t)_VAL2FLD(field, value)))) + + +/******************************************************************************* +* Macro Name: CY_REG8_CLR_SET +****************************************************************************//** +* +* Uses _CLR_SET_FLD8U macro for providing get-clear-modify-write +* operations with a name field and value and writes a resulting value +* to the 8-bit register. +* +*******************************************************************************/ +#define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) + + +/******************************************************************************* +* Macro Name: _BOOL2FLD +****************************************************************************//** +* +* Returns a field mask if the value is not false. +* Returns 0, if the value is false. +* +*******************************************************************************/ +#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL) + + +/******************************************************************************* +* Macro Name: _FLD2BOOL +****************************************************************************//** +* +* Returns true, if the value includes the field mask. +* Returns false, if the value doesn't include the field mask. +* +*******************************************************************************/ +#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUND +****************************************************************************//** +* +* Calculates a / b with rounding to the nearest integer, +* a and b must have the same sign. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) + + +/******************************************************************************* +* Macro Name: CY_SYSLIB_DIV_ROUNDUP +****************************************************************************//** +* +* Calculates a / b with rounding up if remainder != 0, +* both a and b must be positive. +* +*******************************************************************************/ +#define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) + +typedef uint32_t cy_status; +/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ +typedef uint32_t cystatus; +typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ +typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ +typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ +typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ +typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ +typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ +typedef float float32; /**< Alias to float for backward compatibility */ +typedef double float64; /**< Alias to double for backward compatibility */ +typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ +typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; /**< Alias to char for backward compatibility */ +typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ +typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ +typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ + +/** The ARM 32-bit Return error / status code for backward compatibility. +* Do not use them in your code. +*/ +#define CY_RET_SUCCESS (0x00U) /* Successful */ +#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CY_RET_MEMORY (0x03U) /* A memory-related failure */ +#define CY_RET_LOCKED (0x04U) /* A resource lock failure */ +#define CY_RET_EMPTY (0x05U) /* No more objects available */ +#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CY_RET_FINISHED (0x08U) /* Operation is completed */ +#define CY_RET_CANCELED (0x09U) /* Operation is canceled */ +#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */ +#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */ + +/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. +* Do not use them in your code. +*/ +#define CYRET_SUCCESS (0x00U) /* Successful */ +#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */ +#define CYRET_MEMORY (0x03U) /* A memory-related failure */ +#define CYRET_LOCKED (0x04U) /* A resource lock failure */ +#define CYRET_EMPTY (0x05U) /* No more objects available */ +#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08U) /* Operation is completed */ +#define CYRET_CANCELED (0x09U) /* Operation is canceled */ +#define CYRET_TIMEOUT (0x10U) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */ + +/** \} group_syslib_functions */ + +#endif /* CY_SYSLIB_H */ + +/** \} group_syslib */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h new file mode 100644 index 00000000000..db8c143f361 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cy_utils.h @@ -0,0 +1,81 @@ +/***************************************************************************//** +* \file cy_utils.h +* +* \brief +* Basic utility macros and functions. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_utils Utilities +* \ingroup group_abstraction +* \{ +* Basic utility macros and functions. +* +* \defgroup group_utils_macros Macros +*/ + +#pragma once + +#include "stdint.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_utils_macros +* \{ +*/ + +/** Simple macro to supress the unused parameter warning by casting to void. */ +#define CY_UNUSED_PARAMETER(x) ( (void)(x) ) + +/** Halt the processor in the debug state + * @return + */ +static inline uint32_t CY_HALT() +{ + __asm(" bkpt 1"); + return 0; +} + +#ifdef CY_ASSERT +#undef CY_ASSERT +#endif /* ifdef(CY_ASSERT) */ + +/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */ +#if defined(NDEBUG) || defined(CY_NO_ASSERT) + #define CY_ASSERT(x) CY_UNUSED_PARAMETER(x) +#else + #define CY_ASSERT(x) do { \ + if(!(x)) \ + { \ + CY_HALT(); \ + } \ + } while(0) +#endif /* defined(NDEBUG) */ + +/** \} group_utils_macros */ + +#ifdef __cplusplus +} +#endif + +/** \} group_utils */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h new file mode 100644 index 00000000000..06226f327bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cybsp.h @@ -0,0 +1,50 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cycfg.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h new file mode 100644 index 00000000000..e56be0e0132 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal.h @@ -0,0 +1,52 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides cyhal porting to generic mbed APIs + */ +#include "whd_config.h" +#include "cyhal_hw_types.h" +#include "cyhal_gpio.h" +#include "cyhal_sdio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +typedef enum +{ + CYBSP_WIFI_WL_REG_ON, + CYBSP_WIFI_32K_CLK, + CYBSP_LED1, + CYBSP_LED2, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3, + CYBSP_SDIO_OOB_IRQ, + CYBSP_WIFI_MAX, +} wwd_sdio_pin_t; + +void cyhal_system_delay_ms(uint32_t milliseconds); +cy_rslt_t sdio_enable_high_speed(void); + +#if defined(__cplusplus) +} +#endif + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp new file mode 100644 index 00000000000..3b7d33d0fea --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_gpio.cpp @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 GPIOs on WHD driver + */ + +#include +#include "cyhal.h" +#include "cybsp.h" +#include "mbed.h" +#include "wiced_filesystem.h" + +extern pinconfig_t PinConfig[]; + +/******************************************************************************* +* Internal +*******************************************************************************/ +static mbed::InterruptIn *oob_irq; +static cyhal_gpio_event_t oob_event = CYHAL_GPIO_IRQ_FALL; +static cyhal_gpio_event_callback_t oob_handler; +static void *oob_handler_arg; + +/******************************************************************************* +* Internal Interrrupt Service Routine +*******************************************************************************/ +static void cb() +{ + oob_handler(oob_handler_arg, oob_event); +} + +/******************************************************************************* +* HAL Implementation +*******************************************************************************/ +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + // Workaround to enable GPIOJ clock + if (pin == CYBSP_WIFI_WL_REG_ON) { + __HAL_RCC_GPIOB_CLK_ENABLE(); + // Ensure FS and BlockDevice are initialized on time if needed + wiced_filesystem_init(); + } + // Ignore the parameter and take the pin config directly from a static array defintions + HAL_GPIO_Init(PinConfig[pin].port, &PinConfig[pin].config); + if (direction == CYHAL_GPIO_DIR_OUTPUT) { + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (initVal) ? GPIO_PIN_SET : GPIO_PIN_RESET); + } + // Workaround to initialize sdio interface without cypress bsp init + if (pin == CYBSP_WIFI_WL_REG_ON) { + cyhal_sdio_t *sdio_p = cybsp_get_wifi_sdio_obj(); + ret = cyhal_sdio_init(sdio_p, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); + } + return ret; +} + +void cyhal_gpio_write(cyhal_gpio_t pin, bool value) +{ + HAL_GPIO_WritePin(PinConfig[pin].port, PinConfig[pin].config.Pin, (value) ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + +void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t handler, void *handler_arg) +{ + if (handler && handler_arg && (oob_irq == NULL)) { + oob_irq = new mbed::InterruptIn(WL_HOST_WAKE); + oob_handler = handler; + oob_handler_arg = handler_arg; + } +} + +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable) +{ + oob_event = event; + if (enable) { + if (event == CYHAL_GPIO_IRQ_RISE) { + oob_irq->rise(cb); + } + if (event == CYHAL_GPIO_IRQ_FALL) { + oob_irq->fall(cb); + } + } else if (oob_irq != NULL) { + delete oob_irq; + } +} + +void cyhal_gpio_free(cyhal_gpio_t pin) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h new file mode 100644 index 00000000000..1f872abb373 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_hw_types.h @@ -0,0 +1,112 @@ +/***************************************************************************//** +* \file cyhal_hw_types_template.h +* +* \brief +* Provides a template for configuration resources used by the HAL. Items +* here need to be implemented for each HAL port. It is up to the environment +* being ported into what the actual types are. There are some suggestions below +* but these are not required. All that is required is that the type is defined; +* it does not matter to the HAL what type is actually chosen for the +* implementation +* All TODOs and references to 'PORT' need to be replaced by with meaningful +* values for the device being supported. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_hw_types PORT Hardware Types + * \ingroup group_hal_PORT + * \{ + * Struct definitions for configuration resources in the PORT. + * + * \defgroup group_hal_hw_types_data_structures Data Structures + */ + +#pragma once +#include +#include "stm32h7xx_hal.h" +#include "PinNames.h" + +/* + #include "TODO: Port specific header file" + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef CYHAL_ISR_PRIORITY_DEFAULT +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ +#define CYHAL_ISR_PRIORITY_DEFAULT (7) +#endif + +/** + * \addtogroup group_hal_hw_types_data_structures + * \{ + */ + +typedef int32_t cyhal_gpio_t; + +/** GPIO object */ +typedef struct +{ + GPIO_TypeDef *port; + GPIO_InitTypeDef config; +} pinconfig_t; + +/** Clock divider object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *div_type; +} cyhal_clock_divider_t; + +/** Clock object */ +typedef struct +{ + //For backwards compatibility with cyhal_clock_divider_t only. Do not use going forward. + int div_type; /*!< Deprecated */ + uint8_t div_num; /*!< Deprecated */ + //End BWC items + int block; + uint8_t channel; + bool reserved; +} cyhal_clock_t; + +/** SDIO object */ +typedef void* *cyhal_sdio_t; + +/** SPI object */ +typedef struct +{ + /* TODO: replace with port specific items */ + void *empty; +} cyhal_spi_t; + +#include "whd_config.h" +#include "whd_debug.h" + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_hw_types */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c new file mode 100644 index 00000000000..3ddfd858484 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_sdio.c @@ -0,0 +1,506 @@ +/* + * Copyright 2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides the porting layer for STM32 SDIO on WHD driver + */ + +#include +#include +#include "whd_thread.h" +#include "bus_protocols/whd_bus_sdio_protocol.h" +#include "cyabs_rtos.h" +#include "cyhal_sdio.h" + +#define SDIO_RESPONSE_SHORT SDMMC_RESPONSE_SHORT +#define SDIO_WAIT_NO SDMMC_WAIT_NO +#define SDIO_CPSM_ENABLE SDMMC_CPSM_ENABLE +#define SDIO_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO_FLAG_CMDACT (SDMMC_STA_CPSMACT | SDMMC_STA_DPSMACT) +#define SDIO_TRANSFER_DIR_TO_SDIO SDMMC_TRANSFER_DIR_TO_SDMMC +#define SDIO_TRANSFER_DIR_TO_CARD SDMMC_TRANSFER_DIR_TO_CARD +#define SDIO_TRANSFER_MODE_BLOCK SDMMC_TRANSFER_MODE_BLOCK +#define SDIO_DPSM_ENABLE SDMMC_DPSM_ENABLE +#define SDIO_DPSM_DISABLE SDMMC_DPSM_DISABLE +#define SDIO_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN /* 1 << 11 */ +#define SDIO_DCTRL_DTMODE_1 SDMMC_DCTRL_DTMODE_1 /* 1<<3 */ +#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR +#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR +#define SDIO_STA_TXACT SDMMC_STA_CPSMACT +#define SDIO_STA_RXACT SDMMC_STA_DPSMACT +#define SDIO_STA_CMDREND SDMMC_STA_CMDREND +#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT +#define SDIO_CMD_CMDTRANS SDMMC_CMD_CMDTRANS +#define SDIO SDMMC1 + +#define COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS (100000) +#define BUS_LEVEL_MAX_RETRIES 10 + +#define SDIO_CMD_5 5 +#define SDIO_CMD_53 53 + +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!b)?a:b + +/* D-cache maintenance for DMA buffers */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + #define _CYHAL_DCACHE_MAINTENANCE + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u) +#else + #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u) +#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + +/* Macro to ALIGN */ +#if defined (__ARMCC_VERSION) /* ARM Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __align(x) buf +#elif defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf +#endif + +/* Macro to get variable aligned for cache maintenance purpose */ +#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES) + + +extern pinconfig_t PinConfig[]; +extern SD_HandleTypeDef hsd; + +/* for debug prints only */ +//static int num = 0; + +static uint32_t dctrl; + +static whd_driver_t whd_handler; +static cyhal_sdio_irq_handler_t sdio_irq_handler; + +CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]); +static uint8_t *user_data; +static uint32_t user_data_size; +static uint8_t *dma_data_source; +static uint32_t dma_transfer_size; +static cyhal_transfer_t current_transfer_direction; + +static cy_semaphore_t sdio_transfer_finished_semaphore; +static volatile uint32_t sdio_transfer_failed = 0; +static volatile uint32_t irqstatus = 0; +static int current_command = 0; + +static cy_rslt_t sdio_enable_high_speed(void) +{ + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_HSpeed_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_4B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; + + SDMMC_Init(SDMMC1, sdio_init_structure); + return CY_RSLT_SUCCESS; +} + +static uint32_t find_optimal_block_size(uint32_t data_size) +{ + if (data_size > (uint32_t) 256) { + return 512; + } + if (data_size > (uint32_t) 128) { + return 256; + } + if (data_size > (uint32_t) 64) { + return 128; + } + if (data_size > (uint32_t) 32) { + return 64; + } + if (data_size > (uint32_t) 16) { + return 32; + } + if (data_size > (uint32_t) 8) { + return 16; + } + if (data_size > (uint32_t) 4) { + return 8; + } + if (data_size > (uint32_t) 2) { + return 4; + } + + return 4; +} + +static uint32_t sdio_get_blocksize(uint32_t blocksize) +{ + uint32_t n = 0; + blocksize >>= 1; + while (blocksize) { + n++; + blocksize >>= 1; + } + n <<= 4; + return n; +} + +static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t block_size, uint8_t *data, uint16_t data_size) +{ + /* Setup a single transfer using the temp buffer */ + user_data = data; + user_data_size = data_size; + dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size); + + if (direction == CYHAL_WRITE) { + memcpy(temp_dma_buffer, data, data_size); + dma_data_source = temp_dma_buffer; + } else { + dma_data_source = (uint8_t *)temp_dma_buffer; + } + +#ifdef _CYHAL_DCACHE_MAINTENANCE + if (direction == CYHAL_WRITE) + { + SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size); + } + else + { + /* Cache-Invalidate the output from DMA */ + SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source, + data_size + __SCB_DCACHE_LINE_SIZE); + } +#endif + + SDIO->DTIMER = (uint32_t) 0xFFFFFFFF; + SDIO->DLEN = dma_transfer_size; + dctrl = sdio_get_blocksize(block_size) | ((direction == CYHAL_READ) ? SDIO_TRANSFER_DIR_TO_SDIO : SDIO_TRANSFER_DIR_TO_CARD) | SDIO_TRANSFER_MODE_BLOCK | SDIO_DPSM_DISABLE | SDIO_DCTRL_SDIOEN; + SDIO->DCTRL = dctrl; + + SDMMC1->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + SDMMC1->IDMABASE0 = (uint32_t) dma_data_source; +} + +static void sdio_enable_bus_irq(void) +{ + SDMMC1->MASK = SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_CMDREND | SDMMC_IT_CMDSENT; +} + +void SDMMC1_IRQHandler(void) +{ + uint32_t intstatus = SDIO->STA; + + irqstatus = intstatus; + //VIKR | SDIO_STA_STBITERR ) + if ((intstatus & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0) { + WPRINT_WHD_DEBUG(("sdio error flagged\n")); + sdio_transfer_failed = intstatus; + SDIO->ICR = (uint32_t) 0xffffffff; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } else { + if ((intstatus & (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT)) != 0) { + if ((SDMMC1->RESP1 & 0x800) != 0) { + sdio_transfer_failed = irqstatus; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + + /* Clear all command/response interrupts */ + SDMMC1->ICR = (SDMMC_STA_CMDREND | SDMMC_STA_CMDSENT); + } + + /* Check whether the external interrupt was triggered */ + if (intstatus & SDMMC_STA_SDIOIT) { + /* Clear the interrupt */ + SDMMC1->ICR = SDMMC_STA_SDIOIT; + /* Inform WICED WWD thread */ + sdio_irq_handler(whd_handler, CYHAL_SDIO_CARD_INTERRUPT); + } + + if (intstatus & SDMMC_STA_DATAEND) { + SDMMC1->ICR = SDMMC_STA_DATAEND; + SDMMC1->DLEN = 0; + SDMMC1->DCTRL = SDMMC_DCTRL_SDIOEN; + SDMMC1->IDMACTRL = SDMMC_DISABLE_IDMA; + SDMMC1->CMD = 0; + cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); + } + } +} + +//void sdio_dma_irq(void) +//{ +// /* Clear interrupt */ +// DMA2->LIFCR = (uint32_t)(0x3F << 22); +// cy_rtos_set_semaphore(&sdio_transfer_finished_semaphore, WHD_TRUE); +//} + +cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3) +{ + cy_rslt_t ret = CY_RSLT_SUCCESS; + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + HAL_GPIO_Init(PinConfig[cmd].port, &PinConfig[cmd].config); + HAL_GPIO_Init(PinConfig[clk].port, &PinConfig[clk].config); + HAL_GPIO_Init(PinConfig[data0].port, &PinConfig[data0].config); + HAL_GPIO_Init(PinConfig[data1].port, &PinConfig[data1].config); + HAL_GPIO_Init(PinConfig[data2].port, &PinConfig[data2].config); + HAL_GPIO_Init(PinConfig[data3].port, &PinConfig[data3].config); + + /* Reset SDIO Block */ + SDMMC_PowerState_OFF(SDMMC1); + __HAL_RCC_SDMMC1_FORCE_RESET(); + __HAL_RCC_SDMMC1_RELEASE_RESET(); + + /* Enable the SDIO Clock */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore)); + + // Lower speed configuration + SDMMC_InitTypeDef sdio_init_structure; + + sdio_init_structure.ClockDiv = SDMMC_INIT_CLK_DIV; + sdio_init_structure.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + sdio_init_structure.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + sdio_init_structure.BusWide = SDMMC_BUS_WIDE_1B; + sdio_init_structure.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + ret = SDMMC_Init(SDMMC1, sdio_init_structure); + ret |= SDMMC_PowerState_ON(SDMMC1); + ret |= SDMMC_SetSDMMCReadWaitMode(SDMMC1, SDMMC_READ_WAIT_MODE_CLK); + if (ret) { + return ret; + } + + /* Clear all SDIO interrupts */ + SDMMC1->ICR = (uint32_t) 0xffffffff; + + /* Turn on SDIO IRQ */ + /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */ + /* otherwise FreeRTOS will not be able to mask the interrupt */ + /* keep in mind that ARMCM7 interrupt priority logic is inverted, the highest value */ + /* is the lowest priority */ + HAL_NVIC_EnableIRQ((IRQn_Type) SDMMC1_IRQn); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0); + + WPRINT_WHD_DEBUG(("after enable sdio: %p\n", sdio_transfer_finished_semaphore)); + + if (cy_rtos_init_semaphore(&sdio_transfer_finished_semaphore, 1, 0) != WHD_SUCCESS) { + cy_rtos_deinit_semaphore(&sdio_transfer_finished_semaphore); + return -1; + } + + WPRINT_WHD_DEBUG(("cy_rtos_init_semaphore: %p\n", sdio_transfer_finished_semaphore)); + + return ret; +} + +void cyhal_sdio_free(cyhal_sdio_t *obj) +{ + //TODO +} + +cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) +{ + return sdio_enable_high_speed(); +} + +cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t *response) +{ + uint32_t loop_count = 0; + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t temp_sta; + + if (response != NULL) { + *response = 0; + } + current_command = 0; + +restart: + SDIO->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + result = -1; + goto exit; + } + + /* Send the command */ + SDIO->ARG = argument; + SDIO->CMD = (uint32_t)(command | SDIO_RESPONSE_SHORT | SDIO_WAIT_NO | SDIO_CPSM_ENABLE); + loop_count = (uint32_t) COMMAND_FINISHED_CMD52_TIMEOUT_LOOPS; + do { + temp_sta = SDIO->STA; + loop_count--; + if (loop_count == 0 /*|| ((response != NULL) && ((temp_sta & SDIO_ERROR_MASK) != 0))*/) { + WPRINT_WHD_DEBUG(("Restart single access loop count %ld stat %lx\n", loop_count, temp_sta)); + HAL_Delay(10U); + goto restart; + } + } while ((temp_sta & SDIO_FLAG_CMDACT) != 0); + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + if (result) { + WPRINT_WHD_ERROR(("SDIO->POWER %lx \n", SDIO->POWER)); + WPRINT_WHD_ERROR(("SDIO->CLKCR %lx \n", SDIO->CLKCR)); + WPRINT_WHD_ERROR(("result %lx \n", result)); + WPRINT_WHD_ERROR(("cyhal_sdio_send_cmd %s\n", (result == 0) ? "Passed" : "Failed")); + while (1); + } + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 0x%x arg 0x%x resp 0x%x\n",num++,(direction!=CYHAL_READ)?"Write":"Read",command,argument,(response)?*response:0)); + return result; +} + +cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length, uint32_t *response) +{ + cy_rslt_t result; + uint16_t attempts = 0; + uint32_t block_size = 64; + sdio_cmd_argument_t arg; + uint32_t cmd; + current_command = SDIO_CMD_53; + current_transfer_direction = direction; + arg.value = argument; + + sdio_enable_bus_irq(); + if (response != NULL) { + *response = 0; + } + +restart: + sdio_transfer_failed = 0; + SDMMC1->ICR = (uint32_t) 0xFFFFFFFF; + ++attempts; + + /* Check if we've tried too many times */ + if (attempts >= (uint16_t) BUS_LEVEL_MAX_RETRIES) { + /* WWD_SDIO_RETRIES_EXCEEDED */ + WPRINT_WHD_ERROR(("Too much attempt\n")); + result = -1; + goto exit; + } + + /* Dodgy STM32 hack to set the CMD53 byte mode size to be the same as the block size */ + if (arg.cmd53.block_mode == 0) { + block_size = find_optimal_block_size(arg.cmd53.count); + if (block_size < SDIO_512B_BLOCK) { + arg.cmd53.count = block_size; + } else { + arg.cmd53.count = 0; + } + argument = arg.value; + } + + SDMMC1->CMD |= SDMMC_CMD_CMDTRANS; + + /* Prepare the SDIO for a data transfer */ + sdio_prepare_data_transfer(direction, block_size, (uint8_t *) data, (uint32_t) length); + + /* Send the command */ + //WPRINT_WHD_DEBUG(("%d bs=%d argument=%x\n",num++,block_size,argument)); + SDMMC1->ARG = argument; + cmd = (uint32_t)(SDIO_CMD_53 | SDMMC_RESPONSE_SHORT | SDMMC_WAIT_NO | SDMMC_CPSM_ENABLE | SDMMC_CMD_CMDTRANS); + SDMMC1->CMD = cmd; + + /* Wait for the whole transfer to complete */ + //WPRINT_WHD_DEBUG(("cy_rtos_get_semaphore: %d\n", sdio_transfer_finished_semaphore)); + result = cy_rtos_get_semaphore(&sdio_transfer_finished_semaphore, 50, WHD_FALSE); + + if (result != CY_RSLT_SUCCESS) { + WPRINT_WHD_ERROR(("failed getting semaphore\n")); + goto exit; + } + if (sdio_transfer_failed) { + WPRINT_WHD_DEBUG(("try again sdio_transfer_failed %"PRIu32" irq %"PRIu32"\n", sdio_transfer_failed, irqstatus)); + goto restart; + } + /* Check if there were any SDIO errors */ + if ((SDIO->STA & (SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT)) != 0) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_DTIMEOUT | SDIO_STA_CTIMEOUT\n")); + goto restart; + } else if (((SDIO->STA & (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)) != 0)) { + WPRINT_WHD_DEBUG(("sdio errors SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL | SDIO_STA_TXUNDERR | SDIO_STA_RXOVER \n")); + goto restart; + } + + if (direction == CYHAL_READ) { + #ifdef _CYHAL_DCACHE_MAINTENANCE + SCB_CleanInvalidateDCache_by_Addr( + (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)), + user_data_size + __SCB_DCACHE_LINE_SIZE); + #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */ + + memcpy(user_data, dma_data_source, (size_t) user_data_size); + } + + if (response != NULL) { + *response = SDIO->RESP1; + } + result = CY_RSLT_SUCCESS; + +exit: + SDMMC1->CMD = 0; + + //WPRINT_WHD_DEBUG(("%d %s cmd 53 argument %lx datasize %d blocknumber 0x%x cmdis %lx %lu dctrl = %x\n", num++, (direction != CYHAL_READ) ? "Write" : "Read", argument, length, arg.cmd53.count, cmd, cmd, dctrl)); + + return result; +} + +cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t *data, uint16_t length) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) +{ + return false; +} + +cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) +{ + //TODO + return CYHAL_SDIO_RET_NO_SP_ERRORS; +} + +void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg) +{ + whd_handler = (whd_driver_t)handler_arg; + sdio_irq_handler = handler; +} + +void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, uint8_t intr_priority, bool enable) +{ + //TODO +} + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c new file mode 100644 index 00000000000..162c7a6801f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_spi.c @@ -0,0 +1,29 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides stubs for the WHD driver needed by ARMClang + */ + +#include +#include +#include "cyhal_spi.h" + +cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill) +{ + // Do nothing +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h new file mode 100644 index 00000000000..7a3dee0ca9f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/cyhal_system.h @@ -0,0 +1,20 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Empty file to be compliant with Cypress COMPONENT_WHD + */ \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h new file mode 100644 index 00000000000..578b2d9e4eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_bd.h @@ -0,0 +1,49 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" +#include "BlockDevice.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * Mount the physical device + * + * This assumes that the device is ready to read/write immediately. + * + * @param[in] device - physical media to init + * @param[out] fs_handle_out - Receives the filesystem handle. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount(mbed::BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp new file mode 100644 index 00000000000..5973be673a3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.cpp @@ -0,0 +1,225 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#include +#include +#include +#include +#include "sockets.h" +#include "resources.h" +#include "wiced_filesystem.h" +#include "wiced_bd.h" +#include "QSPIFBlockDevice.h" +#include "MBRBlockDevice.h" +#include "FATFileSystem.h" + +#define WIFI_DEFAULT_FIRMWARE_PATH "/wlan/4343WA1.BIN" +#define WIFI_DEFAULT_MOUNT_NAME "wlan" +#define WIFI_DEFAULT_PARTITION 1 +#define WIFI_DEFAULT_FS 0 + +BlockDevice *qspi_bd = NULL; +MBRBlockDevice *mbr_bd = NULL; +FATFileSystem *wifi_fs = NULL; + +wiced_filesystem_t resource_fs_handle; + +MBED_WEAK BlockDevice *BlockDevice::get_default_instance() +{ + static QSPIFBlockDevice default_bd(PD_11, PD_12, PE_2, PF_6, PF_10, PG_6, QSPIF_POLARITY_MODE_1, 40000000); + return &default_bd; +} + +MBED_WEAK void wiced_filesystem_mount_error(void) +{ + WPRINT_WHD_ERROR(("Failed to mount the filesystem containing the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK void wiced_filesystem_firmware_error(void) +{ + WPRINT_WHD_ERROR(("Please run the \"WiFiFirmwareUpdater\" sketch once to install the WiFi firmware.\n\r")); + whd_print_logbuffer(); + while (1) {} +} + +MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int mount_err) +{ + DIR *dir; + struct dirent *ent; + std::string dir_name(mounted_name); + if (mount_err) { + wiced_filesystem_mount_error(); + } else { + if ((dir = opendir(mounted_name)) != NULL) { + // print all the files and directories within directory + while ((ent = readdir(dir)) != NULL) { + std::string fullname = "/" + dir_name + "/" + std::string(ent->d_name); + if (fullname == WIFI_DEFAULT_FIRMWARE_PATH) { + closedir(dir); + return WICED_SUCCESS; + } + } + closedir(dir); + } + wiced_filesystem_firmware_error(); + } + return WICED_ERROR; +} + +static wiced_result_t whd_default_firmware_restore(void) +{ +#if MBED_CONF_APP_WIFI_FIRMWARE_RESTORE + size_t ret; + FILE *fp; + + //This should only happen the firs time or if the partition table has been overwritten i.e QSPI tests + WPRINT_WHD_DEBUG(("MBRBlockDevice init failed, repatitioning\n\r")); + if (mbr_bd->partition(qspi_bd, 1, 0x0B, 0, 1024 * 1024) != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice repatitioning OK, reinit\n\r")); + + if (mbr_bd->init() != BD_ERROR_OK) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("MBRBockDevice init OK\n\r")); + + wifi_fs = new FATFileSystem(WIFI_DEFAULT_MOUNT_NAME); + + if (wifi_fs->reformat(mbr_bd) != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("FATFileSystem reformat and mount OK\n\r")); + + fp = fopen(WIFI_DEFAULT_FIRMWARE_PATH, "wb"); + if (fp == NULL) { + return WICED_ERROR; + } + ret = fwrite(wifi_firmware_image_data, wifi_firmware_image.size, 1, fp); + if (ret != wifi_firmware_image.size) { + return WICED_ERROR; + } + fclose(fp); + + if (mbr_bd->sync() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Sync BlockDevice OK\n\r")); + + if (wifi_fs->unmount() != 0) { + return WICED_ERROR; + } + WPRINT_WHD_DEBUG(("Unmount FS\n\r")); + wifi_fs = NULL; +#endif + + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_init(void) +{ + if (mbr_bd == NULL && wifi_fs == NULL) { + WPRINT_WHD_DEBUG(("Initialize FileSystem with Mbed default settings\n\r")); + qspi_bd = mbed::BlockDevice::get_default_instance(); + + if (qspi_bd->init() == BD_ERROR_OK) { + mbr_bd = new MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); + if (mbr_bd->init() == BD_ERROR_OK) { + return WICED_SUCCESS; + } else { + return whd_default_firmware_restore(); + } + } + return WICED_ERROR; + } else { + WPRINT_WHD_DEBUG(("FileSystem initialized with user settings\n\r")); + return WICED_SUCCESS; + } +} + +wiced_result_t wiced_filesystem_mount_default(void) +{ + return wiced_filesystem_mount(mbr_bd, 0, &resource_fs_handle, WIFI_DEFAULT_MOUNT_NAME); +} + +wiced_result_t wiced_filesystem_mount(BlockDevice *device, wiced_filesystem_handle_type_t fs_type, wiced_filesystem_t *fs_handle_out, const char *mounted_name) +{ + wifi_fs = new FATFileSystem(mounted_name); + + int err = wifi_fs->mount(device); + whd_firmware_check_hook(mounted_name, err); + if (!err) { + //fs_handle_out = wifi_fs + return WICED_SUCCESS; + } + return WICED_ERROR; +} + +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode) +{ + /* This is called by mbed test system */ + //if (mbr_bd == NULL && wifi_fs == NULL) { + // wiced_filesystem_init(); + //} + //This can be called from user sketch to provide custom block device and mount point before WiFi.beginAP or WiFi.begin + if (wifi_fs == NULL) { + wiced_filesystem_mount(mbr_bd, WIFI_DEFAULT_FS, fs_handle, WIFI_DEFAULT_MOUNT_NAME); + } + + if (wifi_fs == NULL) { + return WICED_ERROR; + } + + *file_handle_out = open(filename, mode); + if (*file_handle_out == -1) { + return WICED_ERROR; + } + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + lseek(*file_handle, offset, whence); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + *returned_bytes_count = read(*file_handle, data, bytes_to_read); + return WICED_SUCCESS; +} + +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle) +{ + if (*file_handle == -1) { + return WICED_ERROR; + } + close(*file_handle); + return WICED_SUCCESS; +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h new file mode 100644 index 00000000000..77d49d18202 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/port/wiced_filesystem.h @@ -0,0 +1,148 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides wiced fs porting to generic mbed APIs + */ + +#pragma once + +#include "whd_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************** + * Enumerations + ******************************************************/ + +typedef enum { + WICED_FILESYSTEM_OPEN_FOR_READ, /** Specifies read access to the object. Data can be read from the file - equivalent to "r" or "rb" */ + WICED_FILESYSTEM_OPEN_FOR_WRITE, /** Specifies read/write access to the object. Data can be written to the file - equivalent to "r+" or "rb+" or "r+b" */ + WICED_FILESYSTEM_OPEN_WRITE_CREATE, /** Opens for read/write access, creates it if it doesn't exist */ + WICED_FILESYSTEM_OPEN_ZERO_LENGTH, /** Opens for read/write access, Truncates file to zero length if it exists, or creates it if it doesn't - equivalent to "w+", "wb+" or "w+b" */ + WICED_FILESYSTEM_OPEN_APPEND, /** Opens for read/write access, places the current location at the end of the file ready for appending - equivalent to "a", "ab" */ + WICED_FILESYSTEM_OPEN_APPEND_CREATE, /** Opens for read/write access, creates it if it doesn't exist, and places the current location at the end of the file ready for appending - equivalent to "a+", "ab+" or "a+b" */ +} wiced_filesystem_open_mode_t; + +typedef enum { + WICED_FILESYSTEM_SEEK_SET = SEEK_SET, /* Offset from start of file */ + WICED_FILESYSTEM_SEEK_CUR = SEEK_CUR, /* Offset from current position in file */ + WICED_FILESYSTEM_SEEK_END = SEEK_END, /* Offset from end of file */ +} wiced_filesystem_seek_type_t; + +typedef enum { + WICED_SUCCESS = 0, + WICED_ERROR = 1 +} wiced_result_t; + +/****************************************************** + * Type Definitions + ******************************************************/ + +/** + * File-system Handle Structure + */ +typedef int wiced_filesystem_t; + +/** + * File Handle Structure + * + */ +typedef int wiced_file_t; + +/** + * File-system type Handle Structure + */ +typedef int wiced_filesystem_handle_type_t; + +/** + * Initialise the BlockDevice and filesystem module + * + * Initialises the BlockDevice and filesystem module before mounting a physical device. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_init(void); + +/** + * Mount the physical device using default parameters + * + * This assumes that the device is ready to read/write immediately. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_mount_default(void); + +/** + * Open a file for reading or writing + * + * @param[in] fs_handle - The filesystem handle to use - obtained from wiced_filesystem_mount + * @param[out] file_handle_out - a pointer to a wiced_file_t structure which will receive the + * file handle after it is opened + * @param[in] filename - The filename of the file to open + * @param[in] mode - Specifies read or write access + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_open(wiced_filesystem_t *fs_handle, wiced_file_t *file_handle_out, const char *filename, wiced_filesystem_open_mode_t mode); + +/** + * Seek to a location within a file + * + * This is similar to the fseek() in ISO C. + * + * @param[in] file_handle - The file handle on which to perform the seek. + * Must have been previously opened with wiced_filesystem_fopen. + * @param[in] offset - The offset in bytes + * @param[in] whence - WICED_FILESYSTEM_SEEK_SET = Offset from start of file + * WICED_FILESYSTEM_SEEK_CUR = Offset from current position in file + * WICED_FILESYSTEM_SEEK_END = Offset from end of file + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_seek(wiced_file_t *file_handle, int64_t offset, wiced_filesystem_seek_type_t whence); + +/** + * Reads data from a file into a memory buffer + * + * @param[in] file_handle - the file handle to read from + * @param[out] data - A pointer to the memory buffer that will + * receive the data that is read + * @param[in] bytes_to_read - the number of bytes to read + * @param[out] returned_item_count - the number of items successfully read. + * + * @return WICED_SUCCESS on success + */ +wiced_result_t wiced_filesystem_file_read(wiced_file_t *file_handle, void *data, uint64_t bytes_to_read, uint64_t *returned_bytes_count); + +/** + * Close a file + * + * This is similar to the fclose() in ISO C. + * + * @param[in] file_handle - the file handle to close + * + * @return WICED_SUCCESS = success + */ +wiced_result_t wiced_filesystem_file_close(wiced_file_t *file_handle); + +#ifdef __cplusplus +} /*extern "C" */ +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt new file mode 100644 index 00000000000..cbb51f9c99e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, July 2019 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named �DEPENDENCIES� and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c new file mode 100644 index 00000000000..ddaf0f7188f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c @@ -0,0 +1,25493 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_image_data[421098] = { + 0, 0, 0, 0, 237, 33, 0, 0, 25, 33, 0, 0, 25, 33, 0, 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98, 116, 99, 120, 104, 121, 98, 114, 105, + 100, 104, 119, 45, 110, 111, 99, 108, 109, 105, 110, 99, 45, 99, 108, + 109, 95, 109, 105, 110, 45, 102, 98, 116, 45, 109, 102, 112, 45, 115, + 97, 101, 45, 116, 107, 111, 32, 86, 101, 114, 115, 105, 111, 110, 58, + 32, 55, 46, 52, 53, 46, 57, 56, 46, 57, 53, 32, 40, 114, 55, 50, 52, + 51, 48, 51, 32, 67, 89, 41, 32, 67, 82, 67, 58, 32, 101, 54, 98, 55, + 57, 50, 97, 54, 32, 68, 97, 116, 101, 58, 32, 84, 104, 117, 32, 50, + 48, 50, 48, 45, 48, 49, 45, 51, 48, 32, 50, 49, 58, 52, 51, 58, 53, + 51, 32, 80, 83, 84, 32, 85, 99, 111, 100, 101, 32, 86, 101, 114, 58, + 32, 49, 48, 52, 51, 46, 50, 49, 51, 55, 32, 70, 87, 73, 68, 32, 48, + 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, + 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 +}; +resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c new file mode 100644 index 00000000000..616bdedf2e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wiced_resource.h" + +#if defined(CY_STORAGE_WIFI_DATA) +CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) +#endif +const unsigned char wifi_firmware_clm_blob_image_data[7222] = { + 66, 76, 79, 66, 60, 0, 0, 0, 132, 159, 16, 216, 1, 0, 0, 0, 2, 0, 0, + 0, 0, 0, 0, 0, 60, 0, 0, 0, 246, 27, 0, 0, 183, 10, 32, 40, 0, 0, 0, + 0, 0, 0, 0, 0, 50, 28, 0, 0, 4, 0, 0, 0, 42, 255, 237, 159, 0, 0, 0, + 0, 67, 76, 77, 32, 68, 65, 84, 65, 0, 0, 12, 0, 2, 0, 57, 46, 49, 48, + 46, 51, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 46, 50, 57, 46, + 52, 0, 0, 0, 0, 0, 0, 0, 0, 184, 10, 0, 0, 67, 108, 109, 73, 109, 112, + 111, 114, 116, 58, 32, 49, 46, 51, 54, 46, 51, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 66, 114, 111, 97, 100, 99, 111, 109, 45, 48, 46, 48, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 49, 0, 81, 50, 0, 3, 3, 3, 9, 3, 11, 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83, 90, 0, 7, 33, 14, 39, 0, 16, 84, 65, 0, 18, 8, 255, + 255, 240, 16, 84, 67, 0, 7, 33, 14, 39, 0, 16, 84, 68, 0, 7, 33, 14, + 39, 0, 16, 84, 70, 0, 7, 33, 14, 39, 0, 16, 84, 71, 0, 7, 33, 14, 39, + 0, 16, 84, 72, 0, 7, 43, 6, 52, 0, 32, 84, 74, 0, 7, 33, 14, 39, 0, + 16, 84, 75, 0, 18, 8, 255, 255, 240, 16, 84, 76, 0, 7, 33, 14, 39, 0, + 48, 84, 77, 0, 7, 33, 14, 39, 0, 16, 84, 78, 0, 7, 5, 6, 4, 0, 32, 84, + 79, 0, 7, 8, 255, 255, 240, 16, 84, 82, 0, 7, 5, 6, 4, 0, 32, 84, 82, + 7, 7, 33, 14, 39, 0, 48, 84, 84, 0, 7, 43, 6, 52, 0, 32, 84, 86, 0, + 7, 8, 255, 255, 240, 16, 84, 87, 0, 0, 52, 0, 64, 0, 0, 84, 87, 2, 0, + 53, 0, 62, 0, 0, 84, 90, 0, 7, 33, 14, 39, 0, 16, 85, 65, 0, 7, 8, 255, + 255, 240, 0, 85, 71, 0, 7, 34, 6, 31, 0, 32, 85, 77, 0, 0, 14, 0, 17, + 0, 0, 85, 83, 0, 5, 32, 4, 30, 0, 0, 85, 83, 25, 12, 8, 10, 7, 0, 0, + 85, 83, 26, 4, 8, 1, 7, 0, 0, 85, 89, 0, 20, 43, 23, 52, 0, 0, 85, 90, + 0, 7, 33, 14, 39, 0, 16, 86, 65, 0, 7, 33, 6, 43, 0, 0, 86, 67, 0, 7, + 15, 13, 18, 0, 16, 86, 69, 0, 7, 41, 6, 47, 0, 0, 86, 71, 0, 7, 33, + 6, 43, 0, 0, 86, 73, 0, 0, 14, 0, 17, 0, 0, 86, 78, 0, 7, 5, 6, 4, 0, + 0, 86, 85, 0, 7, 43, 13, 49, 0, 16, 87, 70, 0, 7, 33, 13, 43, 0, 16, + 87, 83, 0, 7, 43, 12, 49, 0, 16, 88, 48, 0, 3, 20, 0, 21, 0, 0, 88, + 49, 0, 7, 41, 6, 47, 0, 0, 88, 50, 0, 21, 3, 6, 2, 0, 0, 88, 51, 0, + 7, 33, 6, 35, 0, 32, 88, 65, 0, 7, 3, 255, 255, 240, 0, 88, 66, 0, 0, + 23, 255, 255, 240, 0, 88, 82, 0, 1, 54, 3, 63, 0, 0, 88, 83, 0, 13, + 4, 11, 1, 0, 32, 88, 84, 0, 12, 8, 10, 7, 0, 32, 88, 85, 0, 9, 37, 7, + 37, 0, 32, 88, 86, 0, 11, 8, 9, 7, 0, 32, 88, 87, 0, 22, 35, 25, 33, + 0, 32, 88, 88, 0, 10, 33, 255, 255, 240, 32, 88, 89, 0, 7, 33, 6, 43, + 0, 32, 88, 90, 0, 14, 8, 255, 255, 240, 32, 89, 49, 0, 0, 14, 255, 255, + 240, 16, 89, 50, 0, 0, 14, 255, 255, 240, 16, 89, 51, 0, 0, 14, 255, + 255, 240, 16, 89, 52, 0, 0, 14, 255, 255, 240, 16, 89, 53, 0, 0, 14, + 255, 255, 240, 16, 89, 54, 0, 0, 14, 255, 255, 240, 16, 89, 55, 0, 0, + 14, 255, 255, 240, 16, 89, 69, 0, 7, 45, 13, 51, 0, 16, 89, 84, 0, 7, + 33, 6, 43, 0, 0, 89, 89, 0, 18, 8, 255, 255, 240, 0, 90, 49, 0, 18, + 8, 255, 255, 240, 16, 90, 50, 0, 18, 8, 255, 255, 240, 16, 90, 51, 0, + 18, 8, 255, 255, 240, 16, 90, 52, 0, 18, 8, 255, 255, 240, 16, 90, 53, + 0, 18, 8, 255, 255, 240, 16, 90, 54, 0, 18, 8, 255, 255, 240, 16, 90, + 55, 0, 18, 8, 255, 255, 240, 16, 90, 56, 0, 18, 8, 255, 255, 240, 16, + 90, 57, 0, 18, 8, 255, 255, 240, 16, 90, 65, 0, 7, 33, 6, 43, 0, 32, + 90, 77, 0, 19, 41, 22, 47, 0, 0, 90, 87, 0, 7, 33, 14, 39, 0, 48, 10, + 2, 255, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 70, 27, 1, 58, 34, + 1, 70, 49, 1, 14, 0, 255, 2, 23, 19, 23, 49, 2, 2, 84, 19, 1, 84, 49, + 1, 14, 0, 255, 2, 23, 19, 23, 49, 0, 2, 66, 19, 1, 66, 49, 1, 23, 1, + 1, 4, 23, 19, 17, 28, 23, 38, 30, 49, 2, 2, 84, 22, 1, 84, 49, 1, 24, + 1, 5, 2, 23, 23, 30, 49, 0, 4, 56, 19, 1, 58, 28, 1, 60, 39, 1, 70, + 49, 1, 15, 1, 255, 1, 23, 20, 2, 1, 84, 20, 1, 15, 1, 255, 1, 23, 20, + 2, 1, 84, 20, 1, 20, 1, 255, 2, 21, 20, 21, 49, 2, 2, 84, 20, 1, 84, + 49, 1, 0, 0, 255, 0, 0, 0, 19, 1, 255, 2, 23, 20, 23, 48, 0, 2, 66, + 20, 1, 66, 48, 1, 20, 1, 255, 2, 23, 20, 20, 49, 0, 2, 66, 20, 1, 64, + 49, 1, 20, 1, 255, 2, 23, 20, 20, 49, 2, 2, 92, 20, 1, 80, 49, 1, 9, + 0, 255, 1, 23, 19, 2, 1, 84, 19, 1, 9, 0, 255, 1, 20, 19, 0, 1, 56, + 19, 1, 11, 2, 255, 3, 17, 19, 24, 30, 30, 49, 0, 5, 56, 19, 1, 70, 27, + 1, 58, 34, 1, 68, 38, 1, 70, 49, 1, 13, 2, 255, 3, 17, 19, 24, 31, 30, + 49, 0, 5, 56, 19, 1, 78, 27, 1, 64, 34, 1, 68, 36, 1, 78, 43, 1, 26, + 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 23, 1, 112, 49, 1, 14, 2, 255, + 2, 17, 19, 30, 49, 0, 2, 58, 19, 1, 80, 49, 1, 27, 0, 255, 1, 30, 26, + 0, 1, 120, 26, 1, 26, 2, 255, 1, 30, 25, 0, 1, 120, 25, 1, 10, 2, 2, + 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 70, 27, 1, 58, 34, 1, 70, + 49, 1, 10, 2, 255, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, 66, 27, + 1, 60, 34, 1, 66, 49, 1, 20, 2, 255, 2, 23, 20, 33, 49, 2, 2, 84, 20, + 1, 84, 49, 1, 10, 2, 1, 3, 17, 19, 24, 28, 30, 49, 0, 4, 56, 19, 1, + 70, 27, 1, 58, 34, 1, 70, 49, 1, 32, 2, 255, 1, 30, 38, 2, 1, 84, 38, + 1, 29, 2, 255, 2, 21, 28, 30, 49, 0, 2, 60, 28, 1, 68, 49, 1, 29, 1, + 255, 2, 30, 28, 30, 49, 2, 2, 112, 28, 1, 112, 49, 1, 5, 2, 0, 2, 23, + 18, 23, 19, 2, 2, 84, 18, 1, 84, 19, 1, 7, 2, 0, 2, 23, 18, 23, 20, + 2, 2, 84, 18, 1, 84, 20, 1, 8, 2, 0, 3, 23, 18, 23, 20, 30, 38, 2, 2, + 84, 18, 1, 84, 22, 1, 6, 1, 255, 4, 14, 18, 14, 19, 20, 29, 20, 48, + 0, 4, 48, 18, 1, 48, 19, 1, 60, 29, 1, 60, 48, 1, 14, 0, 255, 2, 17, + 19, 30, 49, 0, 2, 56, 19, 1, 68, 49, 1, 12, 2, 255, 3, 17, 19, 24, 31, + 30, 50, 0, 6, 62, 19, 1, 90, 27, 1, 80, 35, 1, 90, 41, 1, 86, 45, 1, + 118, 50, 1, 22, 1, 255, 2, 23, 20, 30, 38, 2, 1, 84, 22, 1, 25, 1, 255, + 1, 23, 24, 2, 1, 84, 24, 1, 14, 0, 6, 2, 17, 19, 20, 49, 0, 2, 56, 19, + 1, 60, 49, 1, 18, 1, 255, 2, 20, 20, 20, 44, 2, 2, 72, 20, 1, 72, 44, + 1, 22, 1, 255, 2, 23, 20, 30, 38, 2, 1, 84, 22, 1, 22, 2, 255, 1, 20, + 22, 0, 2, 62, 20, 1, 66, 38, 1, 16, 2, 255, 2, 20, 20, 28, 38, 2, 2, + 84, 20, 1, 112, 38, 1, 4, 0, 255, 1, 23, 18, 2, 1, 84, 18, 1, 20, 1, + 255, 2, 23, 20, 30, 49, 2, 2, 84, 20, 1, 84, 49, 1, 21, 1, 255, 3, 23, + 20, 30, 37, 30, 46, 2, 2, 84, 21, 1, 84, 46, 1, 26, 1, 255, 3, 23, 20, + 24, 39, 30, 49, 2, 1, 84, 25, 1, 26, 1, 255, 3, 23, 20, 24, 39, 30, + 49, 2, 1, 84, 25, 1, 17, 1, 255, 2, 23, 20, 30, 40, 2, 2, 84, 20, 1, + 112, 40, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 30, + 49, 0, 1, 78, 49, 1, 14, 0, 255, 2, 27, 19, 27, 49, 2, 2, 84, 19, 1, + 84, 49, 1, 34, 0, 255, 1, 27, 49, 2, 1, 84, 49, 1, 34, 0, 255, 1, 20, + 49, 2, 1, 76, 49, 1, 33, 0, 255, 1, 20, 48, 2, 1, 76, 48, 1, 31, 2, + 255, 2, 17, 33, 30, 49, 0, 2, 68, 33, 1, 68, 49, 1, 30, 2, 255, 3, 17, + 33, 24, 38, 30, 49, 0, 3, 56, 33, 1, 68, 38, 1, 68, 49, 1, 28, 2, 255, + 3, 17, 28, 24, 38, 30, 49, 0, 3, 56, 28, 1, 58, 38, 1, 62, 49, 1, 33, + 0, 255, 1, 27, 48, 2, 1, 84, 48, 1, 0, 0, 3, 0, 0, 0, 120, 11, 0, 0, + 16, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1, 18, + 1, 255, 1, 52, 1, 14, 1, 15, 3, 28, 39, 49, 2, 19, 49, 166, 169, 0, + 0 +}; +const resource_hnd_t wifi_firmware_clm_blob = { RESOURCE_IN_MEMORY, 7222, {.mem = { (const char *) wifi_firmware_clm_blob_image_data }}}; + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h new file mode 100644 index 00000000000..01bad9226f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/resources.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Automatically generated file - this comment ensures resources.h file creation */ +/* Auto-generated header file. Do not edit */ +#ifndef INCLUDED_RESOURCES_H_ +#define INCLUDED_RESOURCES_H_ +#include "wiced_resource.h" +#include "wiced_filesystem.h" + +extern wiced_filesystem_t resource_fs_handle; + +extern const resource_hnd_t wifi_firmware_image; +extern const unsigned char wifi_firmware_image_data[421098]; +extern const resource_hnd_t wifi_firmware_clm_blob; +extern const unsigned char wifi_firmware_clm_blob_image_data[7222]; + +#endif /* ifndef INCLUDED_RESOURCES_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h new file mode 100644 index 00000000000..3f2279c2be9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2019, Cypress Semiconductor Corporation, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * NVRAM file for CY8CKIT-062-WiFi-BT (PSoC6 WiFi-BT Pioneer Kit) using + * Murata's Type 1DX module - Copied from bcm94343wwcd1.txt on 08/04/2019 + * # 2.4 GHz, 20 MHz BW mode; No Antenna Diversity + */ + +#ifndef INCLUDED_NVRAM_IMAGE_H_ +#define INCLUDED_NVRAM_IMAGE_H_ + +#include +#include +#include "generated_mac_address.txt" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Character array of NVRAM image + * + * Generated from cyw94343cy8ckit-062-wifi-bt.txt + */ + +static const char wifi_nvram_image[] = + "manfid=0x2d0" "\x00" + "prodid=0x0726" "\x00" + "vendid=0x14e4" "\x00" + "devid=0x43e2" "\x00" + "boardtype=0x0726" "\x00" + "boardrev=0x1202" "\x00" + "boardnum=22" "\x00" + NVRAM_GENERATED_MAC_ADDRESS "\x00" + "sromrev=11" "\x00" + "boardflags=0x00404201" "\x00" + "boardflags3=0x04000000" "\x00" + "xtalfreq=37400" "\x00" + "nocrc=1" "\x00" + "ag0=0" "\x00" + "aa2g=1" "\x00" + "ccode=ALL" "\x00" + "extpagain2g=0" "\x00" + "pa2ga0=-145,6667,-751" "\x00" + "AvVmid_c0=0x0,0xc8" "\x00" + "cckpwroffset0=2" "\x00" + "maxp2ga0=74" "\x00" + "cckbw202gpo=0" "\x00" + "legofdmbw202gpo=0x88888888" "\x00" + "mcsbw202gpo=0xaaaaaaaa" "\x00" + "propbw202gpo=0xdd" "\x00" + "ofdmdigfilttype=18" "\x00" + "ofdmdigfilttypebe=18" "\x00" + "papdmode=1" "\x00" + "papdvalidtest=1" "\x00" + "pacalidx2g=48" "\x00" + "papdepsoffset=-22" "\x00" + "papdendidx=58" "\x00" + "il0"NVRAM_GENERATED_MAC_ADDRESS "\x00" + "wl0id=0x431b" "\x00" + "muxenab=0x10" "\x00" + "\x00\x00"; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#else /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ + +#error Wi-Fi NVRAM image included twice + +#endif /* ifndef INCLUDED_NVRAM_IMAGE_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h new file mode 100644 index 00000000000..4b320b9deeb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/COMPONENT_WHD/whd_config.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides configuration for WHD driver on Arduino Portenta H7 + */ + +#ifndef __WHD_CONFIG__ +#define __WHD_CONFIG__ + +#include "whd_types.h" +#include "stm32h7xx_hal.h" +#include + +/* disable WPRINT_MACRO */ +#define WHD_PRINT_DISABLE + +/* please define your configuration , either SDIO or SPI */ +#define CY_WHD_CONFIG_USE_SDIO +//#define CY_WHD_CONFIG_USE_SPI + +/* select resource implementation */ +#define USES_RESOURCE_GENERIC_FILESYSTEM + +/* if not defined default value is 2 */ +#define CY_WIFI_OOB_INTR_PRIORITY 0 + +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_FALL +#define CYBSP_WIFI_HOST_WAKE CYBSP_SDIO_OOB_IRQ + +#define BSP_LED1 {GPIOK,{.Pin= GPIO_PIN_5 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED2 {GPIOK,{.Pin= GPIO_PIN_6 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +#define BSP_LED3 {GPIOK,{.Pin= GPIO_PIN_7 , .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} + +/* power pin */ +#define WIFI_WL_REG_ON {GPIOB,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW}} +//#define WIFI_32K_CLK {GPIOA,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_LOW , .Alternate = GPIO_AF0_MCO}} + +#define WIFI_SDIO_CMD {GPIOD,{.Pin= GPIO_PIN_2 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_CLK {GPIOC,{.Pin= GPIO_PIN_12 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D0 {GPIOC,{.Pin= GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D1 {GPIOC,{.Pin= GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D2 {GPIOC,{.Pin= GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_D3 {GPIOC,{.Pin= GPIO_PIN_11 , .Mode = GPIO_MODE_AF_PP , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH, .Alternate = GPIO_AF12_SDIO1}} +#define WIFI_SDIO_OOB_IRQ {GPIOI,{.Pin= GPIO_PIN_8 , .Mode = GPIO_MODE_IT_FALLING , .Pull = GPIO_NOPULL , .Speed= GPIO_SPEED_FREQ_VERY_HIGH}} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c new file mode 100644 index 00000000000..34b73f5f20a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PeripheralPins.c @@ -0,0 +1,578 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NC, 0} +}; +//*** PWM_HRTIM *** + +MBED_WEAK const PinMap PinMap_PWM_HRTIM[] = { + {PA_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHB, 1)}, // HRTIM_CHB2 + {PA_9, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 0)}, // HRTIM_CHC1 + {PA_10, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHC, 1)}, // HRTIM_CHC2 + {PA_11, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 0)}, // HRTIM_CHD1 + {PA_12, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHD, 1)}, // HRTIM_CHD2 + {PC_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 0)}, // HRTIM_CHA1 + {PC_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHA, 1)}, // HRTIM_CHA2 + {PC_8, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_HRTIM1, CHB, 0)}, // HRTIM_CHB1 + {PG_6, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 0)}, // HRTIM_CHE1 + {PG_7, PWM_I, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_HRTIM1, CHE, 1)}, // HRTIM_CHE2 + {NC, NC, 0} +}; + + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; + + +#if defined (CORE_CM4) +void HSEM2_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h new file mode 100644 index 00000000000..97d48334d7f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GENERIC_STM32H747_M4/PinNames.h @@ -0,0 +1,356 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +/* MBED TARGET LIST: GIGA */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0C = PA_0 | DUAL_PAD, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | DUAL_PAD, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // Not connected + NC = (int)0xFFFFFFFF, + + CONSOLE_TX = NC, + CONSOLE_RX = NC, + + WL_REG_ON = NC, + WL_HOST_WAKE = NC, + WL_SDIO_0 = NC, + WL_SDIO_1 = NC, + WL_SDIO_2 = NC, + WL_SDIO_3 = NC, + WL_SDIO_CMD = NC, + WL_SDIO_CLK = NC, + + CYBSP_BT_UART_RX = NC, + CYBSP_BT_UART_TX = NC, + CYBSP_BT_UART_RTS = NC, + CYBSP_BT_UART_CTS = NC, + + CYBSP_BT_POWER = NC, + CYBSP_BT_HOST_WAKE = NC, + CYBSP_BT_DEVICE_WAKE = NC, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = NC, + QSPI_FLASH1_IO1 = NC, + QSPI_FLASH1_IO2 = NC, + QSPI_FLASH1_IO3 = NC, + QSPI_FLASH1_SCK = NC, + QSPI_FLASH1_CSN = NC + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/targets.json b/targets/targets.json index dac2c94ddc2..9a124223369 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3711,23 +3711,49 @@ ], "device_name": "STM32H747XIHx" }, - "PORTENTA_H7_M4": { - "inherits": ["PORTENTA_H7"], - "core": "Cortex-M4F", - "mbed_rom_start": "0x08100000", - "mbed_rom_size" : "0x100000", - "mbed_ram_start": "0x10000000", - "mbed_ram_size" : "0x48000", - "extra_labels_add": [ - "STM32H747xI_CM4" - ], + "GENERIC_STM32H747_M4": { + "inherits": ["MCU_STM32H747xI_CM4"], + "config": { + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_HS" + } + }, "macros_add": [ + "MBEDTLS_FS_IO", + "MBEDTLS_SHA1_C", + "CM4_BOOT_BY_APPLICATION", "CORE_CM4", - "MBED_MPU_CUSTOM" + "MBED_MPU_CUSTOM", + "CYW43XXX_UNBUFFERED_UART" ], "device_has_remove": [ "MPU" - ] + ], + "components_add": [ + "QSPIF", + "WHD", + "4343W_FS", + "CYW43XXX" + ], + "device_has_add": [ + "USBDEVICE", + "QSPI" + ], + "extra_labels_add": [ + "CORDIO", + "GENERIC_STM32H747_M4" + ], + "features": [ + "BLE" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY", + "clock_source": "USE_PLL_HSI", + "lse_available": 0, + "lpticker_delay_ticks": 0, + "i2c_timing_value_algo": true + } }, "PORTENTA_X8": { "inherits": ["MCU_STM32H747xI_CM4"], From 71dfad798f4dc0c4de6938417d4db668d88cbb39 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 2 Nov 2023 13:49:35 +0100 Subject: [PATCH 214/227] stm32h7: adc: use CLKP as clock source Fixes analogRead() interferring with DSI/SDRAM --- .../TARGET_STM32H7/analogin_device.c | 25 +------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index be16b16cdaa..8b617e307a3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -36,30 +36,7 @@ void analogin_pll_configuration(void) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) { - PeriphClkInitStruct.PLL2.PLL2M = 16; - PeriphClkInitStruct.PLL2.PLL2N = 120; - } else { - #if HSE_VALUE==8000000 - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 120; - #elif HSE_VALUE==16000000 - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 60; - #elif HSE_VALUE==25000000 - PeriphClkInitStruct.PLL2.PLL2M = 5; - PeriphClkInitStruct.PLL2.PLL2N = 96; - #else - error("HSE not configured properly"); - #endif - } - PeriphClkInitStruct.PLL2.PLL2P = 3; - PeriphClkInitStruct.PLL2.PLL2Q = 4; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; + PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("analogin_init HAL_RCCEx_PeriphCLKConfig"); } From 38a6bac6e4fc2af7948a06ffe223d750be0bf00e Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 7 Nov 2023 10:38:21 +0100 Subject: [PATCH 215/227] Gemalto Cinterion Cellular: Disable urcs while reading --- .../GEMALTO_CINTERION_CellularStack.cpp | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 33a73bf9a35..fc2e8985d74 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -524,6 +524,9 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_sendto_impl(Cellul return (_at.get_last_error() == NSAPI_ERROR_OK) ? accept_len : NSAPI_ERROR_DEVICE_ERROR; } +#define DISABLE_URCs _at.at_cmd_discard("^SCFG", "=", "%s%s","Tcp/WithURCs","off") +#define RESTORE_URCs_AND_RETURN(ret) do { _at.at_cmd_discard("^SCFG", "=", "%s%s","Tcp/WithURCs","on"); return ret; } while(0) + nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(CellularSocket *socket, SocketAddress *address, void *buffer, nsapi_size_t size) { @@ -531,13 +534,15 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell // open on the modem, assert here to catch a programming error MBED_ASSERT(socket->id != -1); + DISABLE_URCs; + // we must use this flag, otherwise ^SISR URC can come while we are reading response and there is // no way to detect if that is really an URC or response if (!socket->pending_bytes) { _at.process_oob(); // check for ^SISR URC if (!socket->pending_bytes) { tr_debug("Socket %d recv would block", socket->id); - return NSAPI_ERROR_WOULD_BLOCK; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); } } @@ -552,7 +557,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell _at.resp_start("^SISR:"); if (!_at.info_resp()) { tr_error("Socket %d not responding", socket->id); - return NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); } int socket_id = _at.read_int(); @@ -564,24 +569,24 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell goto sisr_retry; } tr_error("Socket recvfrom id %d != %d", socket_id, socket->id); - return NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); } nsapi_size_or_error_t len = _at.read_int(); if (len == 0) { tr_warn("Socket %d no data", socket->id); _at.resp_stop(); - return NSAPI_ERROR_WOULD_BLOCK; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); } if (len == -1) { if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleTX62 && _at.get_last_read_error() == -2) { _at.process_oob(); tr_error("Socket %d recvfrom finished!", socket->id); socket->pending_bytes = 0; - return NSAPI_ERROR_OK; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_OK); } tr_error("Socket %d recvfrom failed!", socket->id); - return NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); } if (len >= (nsapi_size_or_error_t)size) { len = (nsapi_size_or_error_t)size; @@ -606,7 +611,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell int len = _at.read_bytes(at_buf + ip_len, 1); if (len <= 0) { tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); - return NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); } ip_len += len; } while (ip_len < ip_address_len && at_buf[ip_len - 2] != '\r' && at_buf[ip_len - 1] != '\n'); @@ -629,7 +634,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell int ip_len = _at.read_string(ip_address, sizeof(ip_address)); if (ip_len <= 0) { tr_error("Socket %d recvfrom addr (len %d)", socket->id, ip_len); - return NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN(NSAPI_ERROR_DEVICE_ERROR); } } @@ -671,7 +676,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell _at.resp_stop(); - return (_at.get_last_error() == NSAPI_ERROR_OK) ? (recv_len ? recv_len : NSAPI_ERROR_WOULD_BLOCK) : NSAPI_ERROR_DEVICE_ERROR; + RESTORE_URCs_AND_RETURN((_at.get_last_error() == NSAPI_ERROR_OK) ? (recv_len ? recv_len : NSAPI_ERROR_WOULD_BLOCK) : NSAPI_ERROR_DEVICE_ERROR); } // setup internet connection profile for sockets From b2415db22ce830834870b0c57464b3f11db2461d Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 7 Nov 2023 14:10:31 +0100 Subject: [PATCH 216/227] AT_CellularContext: Fix ^SCFG commands to configure bands and URCs --- .../source/framework/AT/AT_CellularContext.cpp | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index 087846e9b5d..e876e384c9d 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -452,26 +452,21 @@ void AT_CellularContext::enable_access_technology() { case CATM1: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); - _at.resp_start("^SCFG"); - _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); - _at.resp_start("^SCFG"); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); + _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); break; case CATNB: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.cmd_start_stop("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); - _at.resp_start("^SCFG"); - _at.cmd_start_stop("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); - _at.resp_start("^SCFG"); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); + _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); break; default: break; } - _at.cmd_start_stop("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); - _at.resp_start("^SCFG"); + _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); free(buffer); } From 1e40ec52df661b190e749eb7a8f2b77f474296ca Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 10 Nov 2023 10:30:12 +0100 Subject: [PATCH 217/227] AT_CellularContext: move enable_access_technology() at commands into GEMALTO_CINTERION_CellularContext --- .../framework/AT/AT_CellularContext.h | 4 +-- .../framework/AT/AT_CellularContext.cpp | 25 +---------------- .../GEMALTO_CINTERION_CellularContext.cpp | 28 +++++++++++++++++++ .../GEMALTO_CINTERION_CellularContext.h | 1 + 4 files changed, 32 insertions(+), 26 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index eb3bf5afdd1..2f68f1f97bc 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -135,8 +135,6 @@ class AT_CellularContext : public CellularContext { PinName _dcd_pin; bool _active_high; - RadioAccessTechnologyType _rat; - FrequencyBand _band; protected: char _found_apn[MAX_APN_LENGTH]; @@ -144,6 +142,8 @@ class AT_CellularContext : public CellularContext { bool _cp_req; bool _is_connected; ATHandler &_at; + RadioAccessTechnologyType _rat; + FrequencyBand _band; }; } // namespace mbed diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index e876e384c9d..c05fc386e05 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -445,30 +445,7 @@ bool AT_CellularContext::set_new_context(int cid) void AT_CellularContext::enable_access_technology() { - char *buffer = new char [8]; - memset(buffer, 0, 8); - sprintf(buffer,"%08X", _band); - switch (_rat) - { - case CATM1: - _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); - _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); - break; - - case CATNB: - _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); - _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); - break; - - default: - break; - } - - _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); - free(buffer); - + enable_access_technology(); } nsapi_error_t AT_CellularContext::do_activate_context() diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 7ee2c8e53c7..bc2b1d514c7 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -148,4 +148,32 @@ NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() } #endif // NSAPI_PPP_AVAILABLE +void GEMALTO_CINTERION_CellularContext::enable_access_technology() +{ + char *buffer = new char [8]; + memset(buffer, 0, 8); + sprintf(buffer,"%08X", _band); + switch (_rat) + { + case CATM1: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); + _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); + break; + + case CATNB: + _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); + _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); + break; + + default: + break; + } + + _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); + free(buffer); + +} + } /* namespace mbed */ diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h index 0645b2b87ce..cd9aef02221 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h @@ -34,6 +34,7 @@ class GEMALTO_CINTERION_CellularContext: public AT_CellularContext { virtual NetworkStack *get_stack(); #endif // NSAPI_PPP_AVAILABLE virtual nsapi_error_t do_user_authentication(); + virtual void enable_access_technology(); }; } /* namespace mbed */ From 81478e027e494bb652b24eff781df37020b7687a Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 10 Nov 2023 10:30:54 +0100 Subject: [PATCH 218/227] GEMALTO_CINTERION_CellularContext: do not disable all bands * Switching rat AT command fails and should not be necessary to disable bands since we do not use a fallback rat --- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index bc2b1d514c7..bf7522621b8 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -158,13 +158,11 @@ void GEMALTO_CINTERION_CellularContext::enable_access_technology() case CATM1: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); - _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatNB",0,0); break; case CATNB: _at.at_cmd_discard("^SXRAT", "=","%d", _rat); _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); - _at.at_cmd_discard("^SCFG", "=","%s%d%d", "Radio/Band/CatM",0,0); break; default: From 7af118fd28a75ca23db0148ecaf9a680170041c3 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 10 Nov 2023 10:58:37 +0100 Subject: [PATCH 219/227] GEMALTO_CINTERION_CellularContext: add return value to enable_access_technology() --- .../framework/AT/AT_CellularContext.h | 2 +- .../framework/AT/AT_CellularContext.cpp | 4 +-- .../GEMALTO_CINTERION_CellularContext.cpp | 25 +++++++++++-------- .../GEMALTO_CINTERION_CellularContext.h | 2 +- 4 files changed, 19 insertions(+), 14 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h index 2f68f1f97bc..6291bb11d70 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularContext.h @@ -109,7 +109,7 @@ class AT_CellularContext : public CellularContext { * @return NIDD context text, e.g. Non-IP or NONIP */ virtual const char *get_nonip_context_type_str(); - virtual void enable_access_technology(); + virtual nsapi_error_t enable_access_technology(); virtual void set_cid(int cid); private: diff --git a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp index c05fc386e05..f5e69aac80b 100644 --- a/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp +++ b/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp @@ -443,9 +443,9 @@ bool AT_CellularContext::set_new_context(int cid) return success; } -void AT_CellularContext::enable_access_technology() +nsapi_error_t AT_CellularContext::enable_access_technology() { - enable_access_technology(); + return enable_access_technology(); } nsapi_error_t AT_CellularContext::do_activate_context() diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index bf7522621b8..bbd5c4c4b5e 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -148,30 +148,35 @@ NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() } #endif // NSAPI_PPP_AVAILABLE -void GEMALTO_CINTERION_CellularContext::enable_access_technology() +nsapi_error_t GEMALTO_CINTERION_CellularContext::enable_access_technology() { - char *buffer = new char [8]; - memset(buffer, 0, 8); - sprintf(buffer,"%08X", _band); + nsapi_error_t error = NSAPI_ERROR_OK; + char buffer[9] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; + + snprintf(buffer, 9, "%08X", _band); switch (_rat) { case CATM1: - _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM",buffer); + error = _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatM", buffer); break; case CATNB: - _at.at_cmd_discard("^SXRAT", "=","%d", _rat); - _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB",buffer); + error = _at.at_cmd_discard("^SCFG", "=","%s%s", "Radio/Band/CatNB", buffer); break; default: break; } + if (error != NSAPI_ERROR_OK) { + return error; + } - _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); - free(buffer); + error = _at.at_cmd_discard("^SXRAT", "=","%d", _rat); + if (error != NSAPI_ERROR_OK) { + return error; + } + return _at.at_cmd_discard("^SCFG", "=", "%s%s", "Tcp/withURCs", "on"); } } /* namespace mbed */ diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h index cd9aef02221..24ff87bc084 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.h @@ -34,7 +34,7 @@ class GEMALTO_CINTERION_CellularContext: public AT_CellularContext { virtual NetworkStack *get_stack(); #endif // NSAPI_PPP_AVAILABLE virtual nsapi_error_t do_user_authentication(); - virtual void enable_access_technology(); + virtual nsapi_error_t enable_access_technology(); }; } /* namespace mbed */ From 217ba15d7dabc13541a3b4734109c40e32f8ae74 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 10 Nov 2023 17:06:53 +0100 Subject: [PATCH 220/227] GEMALTO_CINTERION_CellularContext::connect check return codes and print errors --- .../GEMALTO_CINTERION_CellularContext.cpp | 29 +++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index bbd5c4c4b5e..0af08a786d7 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -33,22 +33,41 @@ GEMALTO_CINTERION_CellularContext::~GEMALTO_CINTERION_CellularContext() nsapi_error_t GEMALTO_CINTERION_CellularContext::connect(const char *sim_pin, const char *apn, const char *uname, const char *pwd) { + nsapi_error_t error = NSAPI_ERROR_OK; + set_sim_pin(sim_pin); set_credentials(apn, uname, pwd); - set_device_ready(); + error = set_device_ready(); + if ((error != NSAPI_ERROR_OK) && (error != NSAPI_ERROR_ALREADY)) { + tr_error("Failure connecting to GEMALTO CINTERION modem"); + return error; + } _at.lock(); bool valid_context = get_context(); _at.unlock(); - if(!valid_context) { - set_new_context(_cid); + if (!valid_context) { + valid_context = set_new_context(_cid); + } + + if (!valid_context) { + tr_error("Invalid AT cellular context %d", _cid); + return NSAPI_ERROR_DEVICE_ERROR; } - do_user_authentication(); + error = do_user_authentication(); + if (error != NSAPI_ERROR_OK) { + tr_error("Failure during user authentication"); + return error; + } - enable_access_technology(); + error = enable_access_technology(); + if (error != NSAPI_ERROR_OK) { + tr_error("Failure enabling access technology"); + return error; + } return AT_CellularContext::connect(); } From ab084285328a362fc175992d8826470def92511b Mon Sep 17 00:00:00 2001 From: pennam Date: Mon, 13 Nov 2023 16:22:14 +0100 Subject: [PATCH 221/227] TLSSocketWrapper: allow appending ca_cert to an empty chain --- connectivity/netsocket/source/TLSSocketWrapper.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 6665f64cc0b..1fb9c217694 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -145,10 +145,11 @@ nsapi_error_t TLSSocketWrapper::append_root_ca_cert(const void *root_ca, size_t crt = get_ca_chain(); if (!crt) { - return NSAPI_ERROR_NO_MEMORY; + /* In no chain is configured create a new one */ + return set_root_ca_cert(root_ca, len); } - /* Parse CA certification */ + /* Append root_ca to the crt chain */ int ret; if ((ret = mbedtls_x509_crt_parse(crt, static_cast(root_ca), len)) != 0) { From 2e1da01300f14f12b39c24434fe7fe5488258353 Mon Sep 17 00:00:00 2001 From: Leonardo Cavagnis Date: Mon, 13 Nov 2023 17:14:02 +0100 Subject: [PATCH 222/227] STM32H7: fix DUAL_PAD value to avoid ALTx conflict --- .../TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h | 2 +- .../TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h | 2 +- .../TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h | 2 +- .../TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h | 2 +- .../TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h | 2 +- .../TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h | 2 +- .../TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h | 2 +- .../TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h index 9e4001b55a7..01e4e1b98a9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h index 1fb109f69c5..fbda341823e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h index 1a6dccb193b..d68ecb2c25a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h index e5463fe093a..f7314dbace7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_GIGA/PinNames.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h index 93baf9ee198..efe0f63b297 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_OPTA/PinNames.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h index 585fb0ea8f9..0c088c81e65 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h index 1cce05b2e2e..96f611cde59 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_X8/PinNames.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h index 94ccfc23fa3..a44c8620cda 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define DUAL_PAD 0xF00 +#define DUAL_PAD 0x800 typedef enum { ALT0 = 0x100, From f2a69482f8a9e66c45d1f2d40353288e0472fee1 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 17 Nov 2023 17:25:50 +0100 Subject: [PATCH 223/227] CellularDevice: avoid callback data is changed before attached callback is changed --- .../source/framework/device/CellularDevice.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/connectivity/cellular/source/framework/device/CellularDevice.cpp b/connectivity/cellular/source/framework/device/CellularDevice.cpp index 50d900e14ab..1f53b33e61f 100644 --- a/connectivity/cellular/source/framework/device/CellularDevice.cpp +++ b/connectivity/cellular/source/framework/device/CellularDevice.cpp @@ -180,6 +180,11 @@ void CellularDevice::stm_callback(nsapi_event_t ev, intptr_t ptr) void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr, CellularContext *ctx) { + // forward to callback function if set by attach(...). + if (_status_cb) { + _status_cb(ev, ptr); + } + if (ev >= NSAPI_EVENT_CELLULAR_STATUS_BASE && ev <= NSAPI_EVENT_CELLULAR_STATUS_END) { cellular_connection_status_t cell_ev = (cellular_connection_status_t)ev; cell_callback_data_t *ptr_data = (cell_callback_data_t *)ptr; @@ -220,11 +225,6 @@ void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr, CellularC } curr = curr->_next; } - - // forward to callback function if set by attach(...). - if (_status_cb) { - _status_cb(ev, ptr); - } } nsapi_error_t CellularDevice::shutdown() From 05c0e3f2aebfcd248350baca4c4e232753f0c8bb Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 17 Nov 2023 17:29:39 +0100 Subject: [PATCH 224/227] ATHandler: do not temporarily change debug options to partially trace AT commands --- connectivity/cellular/source/framework/device/ATHandler.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/connectivity/cellular/source/framework/device/ATHandler.cpp b/connectivity/cellular/source/framework/device/ATHandler.cpp index f305fd8af58..36d21243f87 100644 --- a/connectivity/cellular/source/framework/device/ATHandler.cpp +++ b/connectivity/cellular/source/framework/device/ATHandler.cpp @@ -1244,12 +1244,7 @@ void ATHandler::handle_start(const char *cmd, const char *cmd_chr) } _cmd_buffer[len] = '\0'; - const bool temp_state = get_debug(); - set_debug(true); - cmd_start(_cmd_buffer); - - set_debug(temp_state); } void ATHandler::cmd_start_stop(const char *cmd, const char *cmd_chr, const char *format, ...) From 5e4e79dcf827908d28041b869bc9e7972db35550 Mon Sep 17 00:00:00 2001 From: pennam Date: Fri, 17 Nov 2023 17:57:49 +0100 Subject: [PATCH 225/227] CellularStateMachine: add state data to timeout and retry callbacks --- .../framework/common/CellularCommon.h | 20 +++++++++++++++++++ .../framework/device/CellularStateMachine.h | 2 ++ .../framework/device/CellularStateMachine.cpp | 11 +++++++--- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/connectivity/cellular/include/cellular/framework/common/CellularCommon.h b/connectivity/cellular/include/cellular/framework/common/CellularCommon.h index f0466e88cfb..96e25dc991a 100644 --- a/connectivity/cellular/include/cellular/framework/common/CellularCommon.h +++ b/connectivity/cellular/include/cellular/framework/common/CellularCommon.h @@ -47,6 +47,26 @@ struct cell_signal_quality_t { } }; +struct cell_timeout_cb_t { + int timeout; /* configured timeout */ + int state; /* cellular state */ + cell_timeout_cb_t() + { + timeout = -1; + state = -1; + } +}; + +struct cell_retry_cb_t { + int retry_count; /* retry count */ + int state; /* cellular state */ + cell_retry_cb_t() + { + retry_count = -1; + state = -1; + } +}; + /** * Cellular specific event changes. * Connect and disconnect are handled via NSAPI_EVENT_CONNECTION_STATUS_CHANGE diff --git a/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h b/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h index 67912e463cf..aed9d615ce1 100644 --- a/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h +++ b/connectivity/cellular/include/cellular/framework/device/CellularStateMachine.h @@ -189,6 +189,8 @@ class CellularStateMachine { bool _command_success; bool _is_retry; cell_callback_data_t _cb_data; + cell_timeout_cb_t _timeout_cb_data; + cell_retry_cb_t _retry_cb_data; cellular_connection_status_t _current_event; int _status; PlatformMutex _mutex; diff --git a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp index 833f1d2239a..37416ca72ea 100644 --- a/connectivity/cellular/source/framework/device/CellularStateMachine.cpp +++ b/connectivity/cellular/source/framework/device/CellularStateMachine.cpp @@ -61,7 +61,7 @@ CellularStateMachine::CellularStateMachine(CellularDevice &device, events::Event _start_time(rand() % (MBED_CONF_CELLULAR_RANDOM_MAX_START_DELAY)), #endif // MBED_CONF_CELLULAR_RANDOM_MAX_START_DELAY _event_timeout(-1s), _event_id(-1), _plmn(0), _command_success(false), - _is_retry(false), _cb_data(), _current_event(CellularDeviceReady), _status(0) + _is_retry(false), _cb_data(), _timeout_cb_data(), _retry_cb_data(), _current_event(CellularDeviceReady), _status(0) { // set initial retry values in seconds @@ -289,8 +289,10 @@ void CellularStateMachine::retry_state_or_fail() if (_retry_count < _retry_array_length) { tr_debug("%s: retry %d/%d", get_state_string(_state), _retry_count, _retry_array_length); // send info to application/driver about error logic so it can implement proper error logic + _retry_cb_data.retry_count = _retry_count; + _retry_cb_data.state = _state; _cb_data.status_data = _current_event; - _cb_data.data = &_retry_count; + _cb_data.data = &_retry_cb_data; _cb_data.error = NSAPI_ERROR_OK; send_event_cb(CellularStateRetryEvent); @@ -680,8 +682,11 @@ void CellularStateMachine::send_event_cb(cellular_connection_status_t status) void CellularStateMachine::change_timeout(const std::chrono::duration &timeout) { + _timeout_cb_data.timeout = timeout.count(); + _timeout_cb_data.state = _state; + _cb_data.status_data = _current_event; - _cb_data.data = &timeout; + _cb_data.data = &_timeout_cb_data; _cb_data.error = NSAPI_ERROR_OK; // event callback is a preferred method to communicate to CellularDevice, // for example calling CellularDevice::set_timeout would call back to this class From 7d043cf5d8d326719b588c17fe3f96bc259ba1ce Mon Sep 17 00:00:00 2001 From: pennam Date: Tue, 21 Nov 2023 14:50:08 +0100 Subject: [PATCH 226/227] Gemalto Cinterion: improve trace output * Do not flood serial monitor with tr_info prints * Align usage of "\n" --- .../CINTERION/GEMALTO_CINTERION_CellularContext.cpp | 2 +- .../GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 0af08a786d7..78955c599e1 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -141,7 +141,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularContext::do_user_authentication() return NSAPI_ERROR_AUTH_FAILURE; } } else { - tr_info("Empty pwd and username fields: no need for authentication\n"); + tr_info("Empty pwd and username fields: no need for authentication"); } return NSAPI_ERROR_OK; diff --git a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index fc2e8985d74..ac2a54282a2 100644 --- a/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/connectivity/drivers/cellular/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -284,7 +284,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S _at.resp_stop(); if (size > 0) { //Valid string received - tr_info("Read %d bytes. Valid string: %s\n", size, ipAddress); + tr_info("Read %d bytes. Valid string: %s", size, ipAddress); // _at.restore_at_timeout(); if (!address->set_ip_address(ipAddress)) { _at.unlock(); @@ -292,7 +292,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::gethostbyname(const char *host, S } } else { //Null string received - tr_info("Read %d bytes. Null string\n", size); + tr_info("Read %d bytes. Null string", size); return NSAPI_ERROR_NO_ADDRESS; } } @@ -550,7 +550,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell size = UDP_PACKET_SIZE; } - tr_info("requesting %d bytes\n", size); + tr_debug("requesting %d bytes\n", size); _at.cmd_start_stop("^SISR", "=", "%d%d", socket->id, size); sisr_retry: @@ -574,7 +574,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_recvfrom_impl(Cell nsapi_size_or_error_t len = _at.read_int(); if (len == 0) { - tr_warn("Socket %d no data", socket->id); + tr_debug("Socket %d no data", socket->id); _at.resp_stop(); RESTORE_URCs_AND_RETURN(NSAPI_ERROR_WOULD_BLOCK); } From 2d834973fc86b787535204b174303a0311e1f36f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Fri, 19 Jan 2024 11:13:09 +0100 Subject: [PATCH 227/227] stm32h747: cm4: set VTOR at boot --- .../STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c | 2 +- .../TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c index b4a4cc78263..8e0017de2aa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -232,7 +232,7 @@ __weak void SystemInit (void) /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#elif !defined(NO_VTOR_RELOCATE) +#else #include "nvic_addr.h" // MBED SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld index ea81a18b117..7d2651dcb48 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/stm32h747xI_CM4.ld @@ -38,10 +38,16 @@ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + RAM_D2 (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K } +#if (CM4_BINARY_START == 0x60000000) +REGION_ALIAS("RAM", FLASH); +#else +REGION_ALIAS("RAM", RAM_D2); +#endif + /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: